| 4 | 5 | 6 | 7 | 17 | 18 | 19 | 20 | 21 | 22 23 | description |
| - | - | - | - | -- | -- | -- | -- | --- |--------|----------------- |
-|ALL|SNZ| / | / | | | 0 | 0 | / | LRu sz | normal mode |
-|ALL|SNZ| / |VSb| | | 0 | 1 | VLI | LRu sz | VLSET mode |
-|ALL|SNZ|CTi| / | | | 1 | 0 | / | LRu sz | CTR-test mode |
-|ALL|SNZ|CTi|VSb| | | 1 | 1 | VLI | LRu sz | CTR-test+VLSET mode |
+|ALL|SNZ| / | / | SL |SLu | 0 | 0 | / | LRu sz | normal mode |
+|ALL|SNZ| / |VSb| SL |SLu | 0 | 1 | VLI | LRu sz | VLSET mode |
+|ALL|SNZ|CTi| / | SL |SLu | 1 | 0 | / | LRu sz | CTR-test mode |
+|ALL|SNZ|CTi|VSb| SL |SLu | 1 | 1 | VLI | LRu sz | CTR-test+VLSET mode |
TODO bits 17,18 for SVSTATE-variant of LR and LRu.