aarch64: Fix store-exclusive in load-operate LSE helpers

	PR target/91834
	* config/aarch64/lse.S (LDNM): Ensure STXR output does not
	overlap the inputs.

From-SVN: r276133

diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
index 261ea7b9d912f9dfb525bce000299421705d1525..541a8021d0a702fefbf9f158a741caba6d42fe60 100644 (file)
--- a/libgcc/ChangeLog
+++ b/libgcc/ChangeLog
@@ -1,3 +1,9 @@
+2019-09-25  Richard Henderson  <richard.henderson@linaro.org>
+
+       PR target/91834
+       * config/aarch64/lse.S (LDNM): Ensure STXR output does not
+       overlap the inputs.
+
 2019-09-25  Shaokun Zhang  <zhangshaokun@hisilicon.com>
 
        * config/aarch64/sync-cache.c (__aarch64_sync_cache_range): Add support for

diff --git a/libgcc/config/aarch64/lse.S b/libgcc/config/aarch64/lse.S
index a5f6673596c73c497156a6f128799cc43b400504..c7979382ad7770b61bb1c64d32ba2395963a9d7a 100644 (file)
--- a/libgcc/config/aarch64/lse.S
+++ b/libgcc/config/aarch64/lse.S
@@ -227,8 +227,8 @@ STARTFN     NAME(LDNM)
 8:     mov             s(tmp0), s(0)
 0:     LDXR            s(0), [x1]
        OP              s(tmp1), s(0), s(tmp0)
-       STXR            w(tmp1), s(tmp1), [x1]
-       cbnz            w(tmp1), 0b
+       STXR            w(tmp2), s(tmp1), [x1]
+       cbnz            w(tmp2), 0b
        ret
 
 ENDFN  NAME(LDNM)