fix deprecated imports

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index a7d626fcf9b4b3b194fe87bec4566df3f2e29cda..b5d9f5a5955601a0202fb2d4191310bad6432180 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -14,7 +14,7 @@ related bugs:
 """
 
 import re
-from nmigen.back.pysim import Settle
+from nmigen.sim import Settle
 from functools import wraps
 from copy import copy, deepcopy
 from openpower.decoder.orderedset import OrderedSet

diff --git a/src/openpower/decoder/isa/pypowersim.py b/src/openpower/decoder/isa/pypowersim.py
index cb7964fc84384acb429972eb839f7751a2022ba7..20edf56560b248df965d17cb6430a7803e2e3737 100644 (file)
--- a/src/openpower/decoder/isa/pypowersim.py
+++ b/src/openpower/decoder/isa/pypowersim.py
@@ -1,5 +1,5 @@
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+from nmigen.sim import Simulator, Delay, Settle
 import sys
 import getopt
 import struct

diff --git a/src/openpower/decoder/isa/radixmmu.py b/src/openpower/decoder/isa/radixmmu.py
index 44786788708cd287991a3e0f4dca068e39e64f4d..c22a484a2d458a39231665671ae858bf6cc07095 100644 (file)
--- a/src/openpower/decoder/isa/radixmmu.py
+++ b/src/openpower/decoder/isa/radixmmu.py
@@ -13,7 +13,7 @@ related bugs:
 * https://bugs.libre-soc.org/show_bug.cgi?id=604
 """
 
-#from nmigen.back.pysim import Settle
+#from nmigen.sim import Settle
 from copy import copy
 from openpower.decoder.selectable_int import (FieldSelectableInt, SelectableInt,
                                         selectconcat)

diff --git a/src/openpower/decoder/isa/test_caller_fp.py b/src/openpower/decoder/isa/test_caller_fp.py
index b5f2bcec7a9e616e8d89fa73a7f7c4056b58fef8..1b11dfc6a35a38977134ff15a7e25d741d168123 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_fp.py
+++ b/src/openpower/decoder/isa/test_caller_fp.py
@@ -1,5 +1,5 @@
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+from nmigen.sim import Simulator, Delay, Settle
 from nmutil.formaltest import FHDLTestCase
 import unittest
 from openpower.decoder.isa.caller import ISACaller

diff --git a/src/openpower/decoder/isa/test_caller_ldst_exceptions.py b/src/openpower/decoder/isa/test_caller_ldst_exceptions.py
index 58beb304b98e9137d59bc8351b5d91fdc82b8c8f..c9982365533d16028c4dd0534c3464a510ff4af2 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_ldst_exceptions.py
+++ b/src/openpower/decoder/isa/test_caller_ldst_exceptions.py
@@ -1,5 +1,5 @@
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+from nmigen.sim import Simulator, Delay, Settle
 from nmutil.formaltest import FHDLTestCase
 import unittest
 from openpower.decoder.isa.caller import ISACaller

diff --git a/src/openpower/decoder/isa/test_caller_radix.py b/src/openpower/decoder/isa/test_caller_radix.py
index d5fe3ef16942d6f1b18144b15dd56b352865f575..29759b7ba6c14642112dfea535bea72c085e1089 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_radix.py
+++ b/src/openpower/decoder/isa/test_caller_radix.py
@@ -1,5 +1,5 @@
 from nmigen import Module, Signal
-#from nmigen.back.pysim import Simulator, Delay, Settle
+#from nmigen.sim import Simulator, Delay, Settle
 from nmutil.formaltest import FHDLTestCase
 import unittest
 from openpower.decoder.isa.caller import ISACaller

diff --git a/src/openpower/decoder/isa/test_caller_setvl.py b/src/openpower/decoder/isa/test_caller_setvl.py
index e1f665051d0080ba4965fd9cf78650c055b54c85..be118bd8df4ecc3c02428d67420ddb22ab9ea2cb 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_setvl.py
+++ b/src/openpower/decoder/isa/test_caller_setvl.py
@@ -1,5 +1,5 @@
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+from nmigen.sim import Simulator, Delay, Settle
 from nmutil.formaltest import FHDLTestCase
 import unittest
 from openpower.decoder.isa.caller import ISACaller

diff --git a/src/openpower/decoder/isa/test_caller_svindex.py b/src/openpower/decoder/isa/test_caller_svindex.py
index d91a07e6abb0a5516ddbefd1e5882d0347447142..ad4a1987b2181c0639e63f3f49d6c19e368add5d 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svindex.py
+++ b/src/openpower/decoder/isa/test_caller_svindex.py
@@ -2,7 +2,7 @@
 svindex SVG,rmm,SVd,ew,yx,mm,sk
 """
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+from nmigen.sim import Simulator, Delay, Settle
 from nmutil.formaltest import FHDLTestCase
 import unittest
 from openpower.decoder.isa.caller import ISACaller

diff --git a/src/openpower/decoder/isa/test_caller_svp64_bc.py b/src/openpower/decoder/isa/test_caller_svp64_bc.py
index d42d7fbd1103a8cb064889766bdcb742ee922192..1b814a65478694a29ec0f5e8a967359c2c08e378 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_bc.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_bc.py
@@ -1,5 +1,5 @@
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+from nmigen.sim import Simulator, Delay, Settle
 from nmutil.formaltest import FHDLTestCase
 import unittest
 from openpower.decoder.isa.caller import ISACaller

diff --git a/src/openpower/decoder/isa/test_caller_svp64_dct.py b/src/openpower/decoder/isa/test_caller_svp64_dct.py
index 9a8c1158bafc111fa6d0d0d4d26a541d1040590b..ce64cd2d85b1056240c2906bb0565bb4647fa2be 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_dct.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_dct.py
@@ -1,5 +1,5 @@
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+from nmigen.sim import Simulator, Delay, Settle
 from nmutil.formaltest import FHDLTestCase
 from openpower.decoder.power_decoder import (create_pdecode)
 from openpower.simulator.program import Program

diff --git a/src/openpower/decoder/isa/test_caller_svp64_fft.py b/src/openpower/decoder/isa/test_caller_svp64_fft.py
index 81602fa35f7fbc1026b8812c68cab7d5b7b48b4f..114e88538782e1765e9b7719212f3ad012641747 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_fft.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_fft.py
@@ -1,5 +1,5 @@
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+from nmigen.sim import Simulator, Delay, Settle
 from nmutil.formaltest import FHDLTestCase
 import unittest
 from openpower.decoder.power_decoder import (create_pdecode)

diff --git a/src/openpower/decoder/isa/test_caller_svp64_mapreduce.py b/src/openpower/decoder/isa/test_caller_svp64_mapreduce.py
index 5fd6968ae2d2df3a6762581822b232baf49b4c99..6c6f751bcc6b3349f26fe83f0f0d50256794cec4 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_mapreduce.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_mapreduce.py
@@ -1,5 +1,5 @@
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+from nmigen.sim import Simulator, Delay, Settle
 from nmutil.formaltest import FHDLTestCase
 import unittest
 from openpower.decoder.isa.caller import ISACaller

diff --git a/src/openpower/decoder/isa/test_caller_svp64_matrix.py b/src/openpower/decoder/isa/test_caller_svp64_matrix.py
index 43f14c8e807d37b6c27a822002b5f02cb2b33662..051199c8b2e302379673a33e3da15eedcffda121 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_matrix.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_matrix.py
@@ -1,5 +1,5 @@
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+from nmigen.sim import Simulator, Delay, Settle
 from nmutil.formaltest import FHDLTestCase
 import unittest
 from openpower.decoder.isa.caller import ISACaller

diff --git a/src/openpower/decoder/isa/test_caller_svstate.py b/src/openpower/decoder/isa/test_caller_svstate.py
index 5ba0f77f75e15f6ad4d8d352fcc31e783a6b1cdb..7612b5c6c0927a9a7f39f5a95803d359ba61b337 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svstate.py
+++ b/src/openpower/decoder/isa/test_caller_svstate.py
@@ -1,7 +1,7 @@
 """SVP64 unit test for doing strange things to SVSTATE, manually.
 """
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+from nmigen.sim import Simulator, Delay, Settle
 from nmutil.formaltest import FHDLTestCase
 import unittest
 from openpower.decoder.isa.caller import ISACaller

diff --git a/src/openpower/decoder/isa/test_caller_transcendentals.py b/src/openpower/decoder/isa/test_caller_transcendentals.py
index f5536f06d30e9ccf1730d0c8eda1adff7fcdde8c..08488bfb05a387fdf3b762ad2f6b5d28b57e3c6c 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_transcendentals.py
+++ b/src/openpower/decoder/isa/test_caller_transcendentals.py
@@ -1,5 +1,5 @@
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Delay, Settle
+from nmigen.sim import Simulator, Delay, Settle
 from nmutil.formaltest import FHDLTestCase
 import unittest
 from openpower.decoder.isa.caller import ISACaller

diff --git a/src/openpower/decoder/isa/test_runner.py b/src/openpower/decoder/isa/test_runner.py
index b49ec6ff781aea3c39dc82ae8207e64b76d09f58..b84354cc099cfba908629b9c17b903990fc79388 100644 (file)
--- a/src/openpower/decoder/isa/test_runner.py
+++ b/src/openpower/decoder/isa/test_runner.py
@@ -1,5 +1,5 @@
 from nmigen import Module, Signal
-from nmigen.back.pysim import Simulator, Settle
+from nmigen.sim import Simulator, Settle
 from openpower.decoder.isa.caller import ISACaller
 from openpower.decoder.power_decoder import create_pdecode
 from openpower.decoder.power_decoder2 import (PowerDecode2)

diff --git a/src/openpower/decoder/orderedset.py b/src/openpower/decoder/orderedset.py
index d5f0b41172a3cdbe7548a6e1098d6806c3be4af9..aa237f56837716392809bd233826e3ec3647c9b6 100644 (file)
--- a/src/openpower/decoder/orderedset.py
+++ b/src/openpower/decoder/orderedset.py
@@ -1,9 +1,10 @@
 # Originally from http://code.activestate.com/recipes/576694/
 # cut down to minimum
 
-import collections
+from collections.abc import MutableSet
 
-class OrderedSet(collections.MutableSet):
+
+class OrderedSet(MutableSet):
 
     def __init__(self, iterable=None):
         self.end = end = [] 

diff --git a/src/openpower/decoder/power_pseudo.py b/src/openpower/decoder/power_pseudo.py
index 05d5938a0ac14cd7a15c81b258d145088f5508ab..f8d87dce3d6806e8b7cd8dffc517cd2f9887fc0f 100644 (file)
--- a/src/openpower/decoder/power_pseudo.py
+++ b/src/openpower/decoder/power_pseudo.py
@@ -16,7 +16,7 @@ import astor
 import ast
 
 from openpower.decoder.power_decoder import create_pdecode
-from nmigen.back.pysim import Simulator, Delay
+from nmigen.sim import Simulator, Delay
 from nmigen import Module, Signal
 
 from openpower.decoder.pseudo.parser import GardenSnakeCompiler

diff --git a/src/openpower/simulator/test_sim.py b/src/openpower/simulator/test_sim.py
index 0b6f223097b20c09eb932ab53966a234d8fc237a..7c240bd8943c46b0a6e072817140d8443105508f 100644 (file)
--- a/src/openpower/simulator/test_sim.py
+++ b/src/openpower/simulator/test_sim.py
@@ -1,6 +1,6 @@
 import unittest
 from nmigen import Module
-from nmigen.back.pysim import Simulator, Delay, Settle
+from nmigen.sim import Simulator, Delay, Settle
 from nmutil.formaltest import FHDLTestCase
 from openpower.decoder.power_decoder import create_pdecode
 from openpower.decoder.power_decoder2 import (PowerDecode2)