self.t1000 = T1000()
self.t1000.attachOnChipIO(self.membus)
self.t1000.attachIO(self.iobus)
- self.physmem = MemClass(range = AddrRange(Addr('1MB'), size = '64MB'),
- zero = True)
- self.physmem2 = MemClass(range = AddrRange(Addr('2GB'), size ='256MB'),
- zero = True)
+ self.physmem = MemClass(range = AddrRange(Addr('1MB'), size = '64MB'))
+ self.physmem2 = MemClass(range = AddrRange(Addr('2GB'), size ='256MB'))
self.mem_ranges = [self.physmem.range, self.physmem2.range]
self.bridge.master = self.iobus.slave
self.bridge.slave = self.membus.master
if bare_metal:
# EOT character on UART will end the simulation
self.realview.uart.end_on_eot = True
- self.physmem = MemClass(range = AddrRange(Addr(mdesc.mem())),
- zero = True)
+ self.physmem = MemClass(range = AddrRange(Addr(mdesc.mem())))
self.mem_ranges = [self.physmem.range]
else:
self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
def setupBootLoader(self, mem_bus, cur_sys, loc):
self.nvmem = SimpleMemory(range = AddrRange(Addr('2GB'),
- size = '64MB'),
- zero = True)
+ size = '64MB'))
self.nvmem.port = mem_bus.master
cur_sys.boot_loader = loc('boot.arm')
InterruptLine=2, InterruptPin=2)
- vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'),
- zero = True)
+ vram = SimpleMemory(range = AddrRange(0x18000000, size='32MB'))
rtc = PL031(pio_addr=0x1C170000, int_num=36)
l2x0_fake = IsaFake(pio_addr=0x2C100000, pio_size=0xfff)
mmc_fake = AmbaFake(pio_addr=0x1c050000)
def setupBootLoader(self, mem_bus, cur_sys, loc):
- self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB'),
- zero = True)
+ self.nvmem = SimpleMemory(range = AddrRange(0, size = '64MB'))
self.nvmem.port = mem_bus.master
cur_sys.boot_loader = loc('boot_emm.arm')
cur_sys.atags_addr = 0x80000100
cxx_header = "mem/abstract_mem.hh"
range = Param.AddrRange(AddrRange('128MB'), "Address range")
null = Param.Bool(False, "Do not store data, always return zero")
- zero = Param.Bool(False, "Initialize memory with zeros")
# All memories are passed to the global physical memory, and
# certain memories may be excluded from the global address map,
*/
bool isNull() const { return params()->null; }
- /**
- * See if this memory should be initialized to zero or not.
- *
- * @return true if zero
- */
- bool initToZero() const { return params()->zero; }
-
/**
* Set the host memory backing store to be used by this memory
* controller.
// it appropriately
backingStore.push_back(make_pair(range, pmem));
- // count how many of the memories are to be zero initialized so we
- // can see if some but not all have this parameter set
- uint32_t init_to_zero = 0;
-
// point the memories to their backing store, and if requested,
// initialize the memory range to 0
for (vector<AbstractMemory*>::const_iterator m = _memories.begin();
DPRINTF(BusAddrRanges, "Mapping memory %s to backing store\n",
(*m)->name());
(*m)->setBackingStore(pmem);
-
- // if it should be zero, then go and make it so
- if ((*m)->initToZero()) {
- ++init_to_zero;
- }
- }
-
- if (init_to_zero != 0) {
- if (init_to_zero != _memories.size())
- fatal("Some, but not all memories in range %s are set zero\n",
- range.to_string());
-
- memset(pmem, 0, range.size());
}
}