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diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn
index ce81d87fb13a93b386348d22c32d23313d1ff4f0..a8fd02efe74604da6c5680de371746597139be0b 100644 (file)
--- a/openpower/sv/overview.mdwn
+++ b/openpower/sv/overview.mdwn
@@ -537,7 +537,7 @@ Whilst this overview shows the internals, it does not go into detail on the actu
 
 That said: draft pages for [[sv/setvl]] and [[sv/svp64]] are written up.  The `setvl` instruction is pretty much as would be expected from a Cray style VL  instruction: the only differences being that, firstly, the MAXVL (Macimum Vector Length) has to be spwcified, because it says how many of the *scalar* registers are to be used for a given Vector.  Secondly: within the limit of MAXVL, VL is required to be set to the requested value (by contrast, RVV systems permit the hardware to set arbitrary values of VL).
 
-The other key question is of course: what's the actual instruction format, and what's in it? Bearing in mind that this requires OPF review, the current draft is at the [[sv/svp64]] page, and includes space for all the different modes, the predicates, element width overrides, SUBVL and the register extensions, in 24 bits.  This just about fits into an OoenPOWER v3.1B 64 bit Pregix by birrowing some of the Reserved Encoding space.
+The other key question is of course: what's the actual instruction format, and what's in it? Bearing in mind that this requires OPF review, the current draft is at the [[sv/svp64]] page, and includes space for all the different modes, the predicates, element width overrides, SUBVL and the register extensions, in 24 bits.  This just about fits into an OpenPOWER v3.1B 64 bit Prefix by borrowing some of the Reserved Encoding space.
 
 Further reading is at the main [[SV|sv]] page.