build/xilinx/ise.py: write .v file for post synthesis sim

diff --git a/litex/build/xilinx/ise.py b/litex/build/xilinx/ise.py
index cd3e2d183a4e666a209fd4a7bec497384f7f7a59..0bb19d4988893ce8d1ecba20bfd6cb2fc87f5670 100644 (file)
--- a/litex/build/xilinx/ise.py
+++ b/litex/build/xilinx/ise.py
@@ -108,6 +108,11 @@ def _run_ise(build_name, ise_path, source, mode, ngdbuild_opt,
         ext = "ngc"
         build_script_contents += """
 xst -ifn {build_name}.xst{fail_stmt}
+"""
+
+    # This generates a .v file for post synthesis simulation
+    build_script_contents += """
+netgen -ofmt verilog -w -sim {build_name}.{ext} {build_name}_synth.v
 """
 
     build_script_contents += """