Restore count_outputs, move process check to abc

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index d507a6973468f272c16b2bf9a2626a60f8d65b66..ac64ae86d9621f0148380d6d5033c196de77f055 100644 (file)
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -164,7 +164,7 @@ struct Abc9Pass : public ScriptPass
                                map_cmd << " " << arg << " " << args[++argidx];
                                continue;
                        }
-                       if (arg == "-fast" || /*arg == "-dff" ||*/ arg == "-keepff"
+                       if (arg == "-fast"
                                        /*|| arg == "-nocleanup"*/ || arg == "-showtmp" || arg == "-markgroups"
                                        || arg == "-nomfs") {
                                map_cmd << " " << arg;
@@ -189,6 +189,14 @@ struct Abc9Pass : public ScriptPass
                active_design->selection_stack.emplace_back(false);
 
                for (auto mod : selected_modules) {
+                       if (module->attributes.count(ID(abc9_box_id)))
+                               continue;
+
+                       if (module->processes.size() > 0) {
+                               log("Skipping module %s as it contains processes.\n", log_id(module));
+                               continue;
+                       }
+
                        log_push();
 
                        active_design->selection().select(mod);

diff --git a/passes/techmap/abc9_map.cc b/passes/techmap/abc9_map.cc
index 7d53db5ea3a9b1dac539a692d32fe8ebfee2ace0..83f90a762e30d93dba2ca2d861fc0c060deaaf15 100644 (file)
--- a/passes/techmap/abc9_map.cc
+++ b/passes/techmap/abc9_map.cc
@@ -268,15 +268,14 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
 
        log_push();
 
-       // FIXME:
-       /*int count_outputs = design->scratchpad_get_int("write_xaiger.num_outputs");
+       int count_outputs = design->scratchpad_get_int("write_xaiger.num_outputs");
        log("Extracted %d AND gates and %d wires to a netlist network with %d inputs and %d outputs.\n",
                        design->scratchpad_get_int("write_xaiger.num_ands"),
                        design->scratchpad_get_int("write_xaiger.num_wires"),
                        design->scratchpad_get_int("write_xaiger.num_inputs"),
                        count_outputs);
 
-       if (count_outputs > 0)*/ {
+       if (count_outputs > 0) {
                std::string buffer;
                std::ifstream ifs;
 #if 0
@@ -965,13 +964,8 @@ struct Abc9MapPass : public Pass {
                CellTypes ct(design);
                for (auto module : design->selected_modules())
                {
-                       if (module->attributes.count(ID(abc9_box_id)))
-                               continue;
-
-                       if (module->processes.size() > 0) {
-                               log("Skipping module %s as it contains processes.\n", log_id(module));
-                               continue;
-                       }
+                       if (module->processes.size() > 0)
+                               log_error("Module '%s' has processes!\n", log_id(module));
 
                        assign_map.set(module);