* haifa-sched.c: Follow spelling conventions.
* regclass.c: Likewise.
* regrename.c: Likewise.
* config/fp-bit.c: Likewise.
* config/frv/frv.h: Likewise.
* config/m88k/m88k.c: Likewise.
* config/mcore/mcore.c: Likewise.
* config/rs6000/darwin.h: Likewise.
* config/rs6000/gnu.h: Likewise.
* config/rs6000/linux.h: Likewise.
* config/rs6000/linux64.h: Likewise.
* config/rs6000/rs6000.c: Likewise.
* config/rs6000/rs6000.h: Likewise.
* config/sh/sh.c: Likewise.
* config/sparc/sparc.c: Likewise.
* config/sparc/ultra1_2.md: Likewise.
From-SVN: r57143
+2002-09-14 Kazu Hirata <kazu@cs.umass.edu>
+
+ * haifa-sched.c: Follow spelling conventions.
+ * regclass.c: Likewise.
+ * regrename.c: Likewise.
+ * config/fp-bit.c: Likewise.
+ * config/frv/frv.h: Likewise.
+ * config/m88k/m88k.c: Likewise.
+ * config/mcore/mcore.c: Likewise.
+ * config/rs6000/darwin.h: Likewise.
+ * config/rs6000/gnu.h: Likewise.
+ * config/rs6000/linux.h: Likewise.
+ * config/rs6000/linux64.h: Likewise.
+ * config/rs6000/rs6000.c: Likewise.
+ * config/rs6000/rs6000.h: Likewise.
+ * config/sh/sh.c: Likewise.
+ * config/sparc/sparc.c: Likewise.
+ * config/sparc/ultra1_2.md: Likewise.
+
2002-09-14 Stephane Carrez <stcarrez@nerim.fr>
* config/m68hc11/m68hc11.md ("movdi_internal"): Allow any offsetable
}
else
{
- /* Zero exponent with non zero fraction - it's denormalized,
+ /* Zero exponent with nonzero fraction - it's denormalized,
so there isn't a leading implicit one - we'll shift it so
it gets one. */
dst->normal_exp = exp - EXPBIAS + 1;
}
else
{
- /* Non zero fraction, means nan */
+ /* Nonzero fraction, means nan */
if (fraction & QUIET_NAN)
{
dst->class = CLASS_QNAN;
-------+--------+--------
-inf(1)| a>b(1) | a==b(0)
-------+--------+--------
- So since unordered must be non zero, just line up the columns...
+ So since unordered must be nonzero, just line up the columns...
*/
return b->sign - a->sign;
}
#define PACKING_FLAG_USED_P() \
(optimize && flag_schedule_insns_after_reload && ISSUE_RATE > 1)
-/* If the following macro is defined and non zero and deterministic
+/* If the following macro is defined and nonzero and deterministic
finite state automata are used for pipeline hazard recognition, the
code making resource-constrained software pipelining is on. */
#define RCSP_SOFTWARE_PIPELINING 1
-/* If the following macro is defined and non zero and deterministic
+/* If the following macro is defined and nonzero and deterministic
finite state automata are used for pipeline hazard recognition, we
will try to exchange insns in queue ready to improve the schedule.
The more macro value, the more tries will be made. */
do the move. Otherwise, return 0 and the caller will emit the move
normally.
- SCRATCH if non zero can be used as a scratch register for the move
+ SCRATCH if nonzero can be used as a scratch register for the move
operation. It is provided by a SECONDARY_RELOAD_* macro if needed. */
int
/* Return a legitimate reference for ORIG (either an address or a MEM)
using the register REG. If PIC and the address is already
position-independent, use ORIG. Newly generated position-independent
- addresses go into a reg. This is REG if non zero, otherwise we
+ addresses go into a reg. This is REG if nonzero, otherwise we
allocate register(s) as necessary. If this is called during reload,
and we need a second temp register, then we use SCRATCH, which is
provided via the SECONDARY_INPUT_RELOAD_CLASS mechanism. */
/* Predicates used by the templates. */
-/* Non zero if OP can be source of a simple move operation. */
+/* Nonzero if OP can be source of a simple move operation. */
int
mcore_general_movsrc_operand (op, mode)
return general_operand (op, mode);
}
-/* Non zero if OP can be destination of a simple move operation. */
+/* Nonzero if OP can be destination of a simple move operation. */
int
mcore_general_movdst_operand (op, mode)
return 1;
}
-/* Non zero if OP should be recognized during reload for an ixh/ixw
+/* Nonzero if OP should be recognized during reload for an ixh/ixw
operand. See the ixh/ixw patterns. */
int
: MAX ((COMPUTED), (SPECIFIED)))
/* XXX: Darwin supports neither .quad, or .llong, but it also doesn't
- support 64 bit powerpc either, so this just keeps things happy. */
+ support 64 bit PowerPC either, so this just keeps things happy. */
#define DOUBLE_INT_ASM_OP "\t.quad\t"
/* Get HOST_WIDE_INT and CONST_INT to be 32 bits, for compile time
/* Definitions of target machine for GNU compiler,
- for powerpc machines running GNU.
+ for PowerPC machines running GNU.
Copyright (C) 2001 Free Software Foundation, Inc.
This file is part of GNU CC.
/* Definitions of target machine for GNU compiler,
- for powerpc machines running Linux.
+ for PowerPC machines running Linux.
Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation,
Inc.
Contributed by Michael Meissner (meissner@cygnus.com).
/* Definitions of target machine for GNU compiler,
- for 64 bit powerpc linux.
+ for 64 bit PowerPC linux.
Copyright (C) 2000, 2001, 2002 Free Software Foundation, Inc.
This file is part of GNU CC.
abort ();
}
\f
-/* Target hook for assembling integer objects. The powerpc version has
+/* Target hook for assembling integer objects. The PowerPC version has
to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
is defined. It also needs to handle DI-mode objects on 64-bit
targets. */
/* Disable use of FPRs. */
#define MASK_SOFT_FLOAT 0x00000800
-/* Enable load/store multiple, even on powerpc */
+/* Enable load/store multiple, even on PowerPC */
#define MASK_MULTIPLE 0x00001000
#define MASK_MULTIPLE_SET 0x00002000
return REG_N_SETS (TARGET_SHMEDIA ? PR_MEDIA_REG : PR_REG);
}
-/* This Function returns non zero if the DFA based scheduler interface
+/* This Function returns nonzero if the DFA based scheduler interface
is to be used. At present this is supported for the SH4 only. */
static int
sh_use_dfa_interface()
/* Legitimize PIC addresses. If the address is already position-independent,
we return ORIG. Newly generated position-independent addresses go into a
- reg. This is REG if non zero, otherwise we allocate register(s) as
+ reg. This is REG if nonzero, otherwise we allocate register(s) as
necessary. */
rtx
"us1_fpm + us1_fp_double + us1_slotany, nothing*3")
;; This is actually in theory dangerous, because it is possible
-;; for the chip to prematurely dispatch the dependant instruction
+;; for the chip to prematurely dispatch the dependent instruction
;; in the G stage, resulting in a 9 cycle stall. However I have never
;; been able to trigger this case myself even with hand written code,
;; so it must require some rare complicated pipeline state.
static int issue_rate;
-/* If the following variable value is non zero, the scheduler inserts
+/* If the following variable value is nonzero, the scheduler inserts
bubbles (nop insns). The value of variable affects on scheduler
behavior only if automaton pipeline interface with multipass
scheduling is used and hook dfa_bubble is defined. */
/* Allocate enough space to hold NUM_REGS registers for the tables used for
reg_scan and flow_analysis that are indexed by the register number. If
- NEW_P is non zero, initialize all of the registers, otherwise only
+ NEW_P is nonzero, initialize all of the registers, otherwise only
initialize the new registers allocated. The same table is kept from
function to function, only reallocating it when we need more room. If
- RENUMBER_P is non zero, allocate the reg_renumber array also. */
+ RENUMBER_P is nonzero, allocate the reg_renumber array also. */
void
allocate_reg_info (num_regs, new_p, renumber_p)
return;
/* Do not propagate copies to the stack pointer, as that can leave
- memory accesses with no scheduling dependancy on the stack update. */
+ memory accesses with no scheduling dependency on the stack update. */
if (dr == STACK_POINTER_REGNUM)
return;
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