Be more conservative with printing decimal numbers in verilog backend

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index c691eae600b6b4463703198eab5b8a3377d24ecb..605616b31bc3cf2c1ced359e43cfde30b5354240 100644 (file)
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -163,11 +163,12 @@ void dump_const(FILE *f, const RTLIL::Const &data, int width = -1, int offset =
                                log_assert(i < (int)data.bits.size());
                                if (data.bits[i] != RTLIL::S0 && data.bits[i] != RTLIL::S1)
                                        goto dump_bits;
+                               if (data.bits[i] == RTLIL::S1 && (i - offset) == 31)
+                                       goto dump_bits;
                                if (data.bits[i] == RTLIL::S1)
                                        val |= 1 << (i - offset);
                        }
-                       // fprintf(f, "%s32'sd%u", val < 0 ? "-" : "", abs(val));
-                       fprintf(f, "%d", val);
+                       fprintf(f, "32'%sd%d", set_signed ? "s" : "", val);
                } else {
        dump_bits:
                        fprintf(f, "%d'%sb", width, set_signed ? "s" : "");