did_something = true;
}
}
+
+ if (cell->type == "$alu")
+ {
+ RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
+ RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B"));
+ RTLIL::SigBit sig_ci = assign_map(cell->getPort("\\CI"));
+ RTLIL::SigBit sig_bi = assign_map(cell->getPort("\\BI"));
+ RTLIL::SigSpec sig_x = cell->getPort("\\X");
+ RTLIL::SigSpec sig_y = cell->getPort("\\Y");
+ RTLIL::SigSpec sig_co = cell->getPort("\\CO");
+
+ if (sig_ci.wire || sig_bi.wire)
+ goto next_cell;
+
+ bool sub = (sig_ci == State::S1 && sig_bi == State::S1);
+
+ // If not a subtraction, yet there is a carry or B is inverted
+ // then no optimisation is possible as carry will not be constant
+ if (!sub && (sig_ci != State::S0 || sig_bi != State::S0))
+ goto next_cell;
+
+ int i;
+ for (i = 0; i < GetSize(sig_y); i++) {
+ if (sig_b.at(i, State::Sx) == State::S0 && sig_a.at(i, State::Sx) != State::Sx) {
+ module->connect(sig_x[i], sub ? module->Not(NEW_ID, sig_a[i]).as_bit() : sig_a[i]);
+ module->connect(sig_y[i], sig_a[i]);
+ module->connect(sig_co[i], sub ? State::S1 : State::S0);
+ }
+ else if (!sub && sig_a.at(i, State::Sx) == State::S0 && sig_b.at(i, State::Sx) != State::Sx) {
+ module->connect(sig_x[i], sig_b[i]);
+ module->connect(sig_y[i], sig_b[i]);
+ module->connect(sig_co[i], State::S0);
+ }
+ else
+ break;
+ }
+ if (i > 0) {
+ cover("opt.opt_expr.fine.$alu");
+ cell->setPort("\\A", sig_a.extract_end(i));
+ cell->setPort("\\B", sig_b.extract_end(i));
+ cell->setPort("\\X", sig_x.extract_end(i));
+ cell->setPort("\\Y", sig_y.extract_end(i));
+ cell->setPort("\\CO", sig_co.extract_end(i));
+ cell->fixup_parameters();
+ did_something = true;
+ }
+ }
}
- if (cell->type == "$reduce_xor" || cell->type == "$reduce_xnor" || cell->type == "$shift" || cell->type == "$shiftx" ||
- cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr" ||
- cell->type == "$lt" || cell->type == "$le" || cell->type == "$ge" || cell->type == "$gt" ||
- cell->type == "$neg" || cell->type == "$add" || cell->type == "$sub" ||
- cell->type == "$mul" || cell->type == "$div" || cell->type == "$mod" || cell->type == "$pow")
+ if (cell->type.in("$reduce_xor", "$reduce_xnor", "$shift", "$shiftx", "$shl", "$shr", "$sshl", "$sshr",
+ "$lt", "$le", "$ge", "$gt", "$neg", "$add", "$sub", "$mul", "$div", "$mod", "$pow"))
{
RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
RTLIL::SigSpec sig_b = cell->hasPort("\\B") ? assign_map(cell->getPort("\\B")) : RTLIL::SigSpec();
--- /dev/null
-hierarchy -auto-top
-proc
-design -save gold
+
+ read_verilog <<EOT
+ module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
+ assign o = (i << 4) + j;
+ endmodule
+ EOT
+
-opt_expr -fine
-wreduce
++equiv_opt -assert opt_expr -fine
++design -load postopt
+
-select -assert-count 1 t:$add r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
++select -assert-count 1 t:$add r:A_WIDTH=5 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
+
-design -stash gate
++##########
+
-design -import gold -as gold
-design -import gate -as gate
++# alumacc version of above
++design -reset
++read_verilog <<EOT
++module opt_expr_add_test(input [3:0] i, input [7:0] j, output [8:0] o);
++ assign o = (i << 4) + j;
++endmodule
++EOT
+
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports miter
++alumacc
++equiv_opt -assert opt_expr -fine
++design -load postopt
+
-hierarchy -auto-top
-proc
-design -save gold
++select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
+
+ ##########
+
++design -reset
+ read_verilog <<EOT
+ module opt_expr_add_signed_test(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
+ assign o = (i << 4) + j;
+ endmodule
+ EOT
+
-opt_expr -fine
-wreduce
++equiv_opt -assert opt_expr -fine
++design -load postopt
+
-select -assert-count 1 t:$add r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
++select -assert-count 1 t:$add r:A_WIDTH=5 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
+
-design -stash gate
++##########
+
-design -import gold -as gold
-design -import gate -as gate
++# alumacc version of above
++design -reset
++read_verilog <<EOT
++module opt_expr_add_signed_test(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
++ assign o = (i << 4) + j;
++endmodule
++EOT
+
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports miter
++alumacc
++equiv_opt -assert opt_expr -fine
++design -load postopt
+
-hierarchy -auto-top
-proc
-design -save gold
++select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
+
+ ##########
+
++design -reset
+ read_verilog <<EOT
+ module opt_expr_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o);
+ assign o = j - (i << 4);
+ endmodule
+ EOT
+
-opt_expr -fine
-wreduce
++equiv_opt -assert opt_expr -fine
++design -load postopt
+
-select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
++select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
+
-design -stash gate
++##########
+
-design -import gold -as gold
-design -import gate -as gate
++# alumacc version of above
++design -reset
++read_verilog <<EOT
++module opt_expr_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o);
++ assign o = j - (i << 4);
++endmodule
++EOT
+
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports miter
++alumacc
++equiv_opt -assert opt_expr -fine
++design -load postopt
+
-hierarchy -auto-top
-proc
-design -save gold
++dump
++select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
+
+ ##########
+
++design -reset
+ read_verilog <<EOT
+ module opt_expr_sub_signed_test1(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
+ assign o = j - (i << 4);
+ endmodule
+ EOT
+
-opt_expr -fine
-wreduce
++equiv_opt -assert opt_expr -fine
++design -load postopt
+
-select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
++select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
+
-design -stash gate
++##########
+
-design -import gold -as gold
-design -import gate -as gate
++# alumacc version of above
++design -reset
++read_verilog <<EOT
++module opt_expr_sub_signed_test1(input signed [3:0] i, input signed [7:0] j, output signed [8:0] o);
++ assign o = j - (i << 4);
++endmodule
++EOT
+
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports miter
++alumacc
++equiv_opt -assert opt_expr -fine
++design -load postopt
+
-hierarchy -auto-top
-proc
-design -save gold
++select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=5 r:Y_WIDTH=5 %i %i %i
+
+ ##########
+
++design -reset
+ read_verilog <<EOT
+ module opt_expr_sub_test2(input [3:0] i, input [7:0] j, output [8:0] o);
+ assign o = (i << 4) - j;
+ endmodule
+ EOT
+
-opt_expr -fine
-wreduce
++equiv_opt -assert opt_expr -fine
++design -load postopt
+
-select -assert-count 1 t:$sub r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
++select -assert-count 1 t:$sub r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
+
-design -stash gate
++##########
+
-design -import gold -as gold
-design -import gate -as gate
++# alumacc version of above
++design -reset
++read_verilog <<EOT
++module opt_expr_sub_test2(input [3:0] i, input [7:0] j, output [8:0] o);
++ assign o = (i << 4) - j;
++endmodule
++EOT
+
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports miter
++alumacc
++opt_expr -fine
++equiv_opt -assert opt_expr -fine
++design -load postopt
+
-hierarchy -auto-top
-proc
-design -save gold
-
-opt_expr -fine
++select -assert-count 1 t:$alu r:A_WIDTH=9 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
+
+ ##########
+
++design -reset
+ read_verilog <<EOT
+ module opt_expr_sub_test4(input [3:0] i, output [8:0] o);
+ assign o = 5'b00010 - i;
+ endmodule
+ EOT
+
-design -stash gate
+ wreduce
++equiv_opt -assert opt_expr -fine
++design -load postopt
+
+ select -assert-count 1 t:$sub r:A_WIDTH=2 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
+
-design -import gold -as gold
-design -import gate -as gate
++##########
++
++# alumacc version of above
++design -reset
++read_verilog <<EOT
++module opt_expr_sub_test4(input [3:0] i, output [8:0] o);
++ assign o = 5'b00010 - i;
++endmodule
++EOT
+
-miter -equiv -flatten -make_assert -make_outputs gold gate miter
-sat -verify -prove-asserts -show-ports miter
++wreduce
++alumacc
++equiv_opt -assert opt_expr -fine
++design -load postopt
++
++select -assert-count 1 t:$alu r:A_WIDTH=2 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
++
++###########
++
++design -reset
++read_verilog -icells <<EOT
++module opt_expr_alu_test_ci0_bi0(input [7:0] a, input [3:0] b, output [8:0] x, y, co);
++ \$alu #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(9)) alu (.A(a), .B({b, 4'b0000}), .CI(1'b0), .BI(1'b0), .X(x), .Y(y), .CO(co));
++endmodule
++EOT
++check
++
++equiv_opt -assert opt_expr -fine
++design -load postopt
++select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
++
++###########
++
++design -reset
++read_verilog -icells <<EOT
++module opt_expr_alu_test_ci1_bi1(input [7:0] a, input [3:0] b, output [8:0] x, y, co);
++ \$alu #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(9)) alu (.A(a), .B({b, 4'b0000}), .CI(1'b1), .BI(1'b1), .X(x), .Y(y), .CO(co));
++endmodule
++EOT
++check
++
++equiv_opt opt_expr -fine
++design -load postopt
++select -assert-count 1 t:$alu r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
++
++###########
++
++design -reset
++read_verilog -icells <<EOT
++module opt_expr_alu_test_ci0_bi1(input [7:0] a, input [3:0] b, output [8:0] x, y, co);
++ \$alu #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(8), .B_WIDTH(8), .Y_WIDTH(9)) alu (.A(a), .B({b, 4'b0000}), .CI(1'b0), .BI(1'b1), .X(x), .Y(y), .CO(co));
++endmodule
++EOT
++check
+
++equiv_opt opt_expr -fine
++design -load postopt
++select -assert-count 1 t:$alu r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
projects / yosys.git / commitdiff