must include brackets to stop NEWLINE parsing

diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn
index 3565461ad742e59879b3e8760a968a4e61765ea7..1ee26d7e61ed8037d2e81c06c531743372e2e0dc 100644 (file)
--- a/openpower/isa/fixedload.mdwn
+++ b/openpower/isa/fixedload.mdwn
@@ -358,8 +358,8 @@ X-Form
     b <- (RA|0)
     EA <- b + (RB)
     load_data <- MEM(EA, 4)
-    RT <- [0] * 32 || load_data[24:31] || load_data[16:23]
-             || load_data[8:15] || load_data[0:7]
+    RT <- ([0] * 32 || load_data[24:31] || load_data[16:23]
+                    || load_data[8:15]  || load_data[0:7])
 
 Special Registers Altered:
 
@@ -374,10 +374,10 @@ X-Form
     b <- (RA|0)
     EA <- b + (RB)
     load_data <- MEM(EA, 8)
-    RT <-  load_data[56:63] || load_data[48:55]
-    || load_data[40:47 || load_data[32:39]
-    || load_data[24:31 || load_data[16:23]
-    || load_data[8:15  || load_data[0:7]
+    RT <- (load_data[56:63] || load_data[48:55]
+        || load_data[40:47 || load_data[32:39]
+        || load_data[24:31 || load_data[16:23]
+        || load_data[8:15  || load_data[0:7])
 
 Special Registers Altered:
 

diff --git a/openpower/isa/fixedstore.mdwn b/openpower/isa/fixedstore.mdwn
index 314d71823f45d88fec91375304c372d2a5d4bdc8..c0e9d6f873fba8da6dbe78c7dfef6f97e2a05847 100644 (file)
--- a/openpower/isa/fixedstore.mdwn
+++ b/openpower/isa/fixedstore.mdwn
@@ -258,8 +258,8 @@ X-Form
 
     b <- (RA|0)
     EA <- b + (RB)
-    MEM(EA, 4) <- (RS)[56:63] || (RS)[48:55] || (RS)[40:47]
-                   ||(RS)[32:39]
+    MEM(EA, 4) <- ((RS)[56:63] || (RS)[48:55] || (RS)[40:47]
+                   ||(RS)[32:39])
 
 Special Registers Altered:
 
@@ -273,10 +273,10 @@ X-Form
 
     b <- (RA|0)
     EA <- b + (RB)
-    MEM(EA, 8) <- (RS) [56:63] || (RS)48:55]
-    || (RS)[40:47] || (RS)[32:39]
-    || (RS)[24:31] || (RS)[16:23]
-    || (RS)[8:15]  || (RS)[0:7]
+    MEM(EA, 8) <- ((RS) [56:63] || (RS)48:55]
+                    || (RS)[40:47] || (RS)[32:39]
+                    || (RS)[24:31] || (RS)[16:23]
+                    || (RS)[8:15]  || (RS)[0:7])
 
 Special Registers Altered: