[AArch64] Improve regmove_costs for 128-bit types.

  2014-09-24  Wilco Dijkstra <wdijkstr@arm.com>

  gcc/
    * config/aarch64/aarch64.c (aarch64_register_move_cost): Add register move
    costs for 128-bit types.

From-SVN: r215562

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 1755c0ff55bf76c6cd437b932880f8e7f10333c6..ce6738c852dd55a9cd2fd44e010e876393dd39a3 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2014-09-24  Wilco Dijkstra  <wilco.dijkstra@arm.com>
+
+       * config/aarch64/aarch64.c (aarch64_register_move_cost): Add register
+       move costs for 128-bit types.
+
 2014-09-24  Martin Jambor  <mjambor@suse.cz>
 
        * ipa-prop.c (ipa_edge_duplication_hook): Update controlled_use_count

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 348308109a98b0b0f9e2e70375b273f7d28fd0ee..4e0cba8da740ea2f64ee3ed31354fd29c093032c 100644 (file)
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -5986,6 +5986,27 @@ aarch64_register_move_cost (enum machine_mode mode,
     return aarch64_register_move_cost (mode, from, GENERAL_REGS)
             + aarch64_register_move_cost (mode, GENERAL_REGS, to);
 
+  if (GET_MODE_SIZE (mode) == 16)
+    {
+      /* 128-bit operations on general registers require 2 instructions.  */
+      if (from == GENERAL_REGS && to == GENERAL_REGS)
+       return regmove_cost->GP2GP * 2;
+      else if (from == GENERAL_REGS)
+       return regmove_cost->GP2FP * 2;
+      else if (to == GENERAL_REGS)
+       return regmove_cost->FP2GP * 2;
+
+      /* When AdvSIMD instructions are disabled it is not possible to move
+        a 128-bit value directly between Q registers.  This is handled in
+        secondary reload.  A general register is used as a scratch to move
+        the upper DI value and the lower DI value is moved directly,
+        hence the cost is the sum of three moves. */
+      if (! TARGET_SIMD)
+       return regmove_cost->GP2FP + regmove_cost->FP2GP + regmove_cost->FP2FP;
+
+      return regmove_cost->FP2FP;
+    }
+
   if (from == GENERAL_REGS && to == GENERAL_REGS)
     return regmove_cost->GP2GP;
   else if (from == GENERAL_REGS)
@@ -5993,14 +6014,6 @@ aarch64_register_move_cost (enum machine_mode mode,
   else if (to == GENERAL_REGS)
     return regmove_cost->FP2GP;
 
-  /* When AdvSIMD instructions are disabled it is not possible to move
-     a 128-bit value directly between Q registers.  This is handled in
-     secondary reload.  A general register is used as a scratch to move
-     the upper DI value and the lower DI value is moved directly,
-     hence the cost is the sum of three moves. */
-  if (! TARGET_SIMD && GET_MODE_SIZE (mode) == 16)
-    return regmove_cost->GP2FP + regmove_cost->FP2GP + regmove_cost->FP2FP;
-
   return regmove_cost->FP2FP;
 }