(no commit message)

diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index c5d40949f95f8b2691d628923b855462bf8b606c..f837192e1caa1c541b8ae816b6baff576f507d3d 100644 (file)
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -34,7 +34,9 @@ defined in the Prefix Fields section.
 
 One bit indicates the mode: CR or Int predication.   The two types may not be mixed.
 
-Twin predication uses the same encoding thus allowing either the same register (r3 or r10) to be used for both src and dest, or different regs (one for src, one for dest).
+Integer Twin predication has a second set if 3 bits that uses the same encoding thus allowing either the same register (r3 or r10) to be used for both src and dest, or different regs (one for src, one for dest).
+
+Likewise CR based twin predication has a second set of 3 bits, allowing a different test to be applied.
 
 ### Integer Predication