add ternlog* instruction names as sections

diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn
index d882926718e537b93ce26138fc97f7f69c260cbc..d35c4294b2810c7a51bd2afa39a3fb82a0cf4ea6 100644 (file)
--- a/openpower/sv/bitmanip.mdwn
+++ b/openpower/sv/bitmanip.mdwn
@@ -241,6 +241,8 @@ Similar to FPGA LUTs: for every bit perform a lookup into a table using an 8bit
 
 Like the x86 AVX512F [vpternlogd/vpternlogq](https://www.felixcloutier.com/x86/vpternlogd:vpternlogq) instructions.
 
+## ternlogi
+
 | 0.5|6.10|11.15|16.20| 21..25| 26..30   |31|
 | -- | -- | --- | --- | ----- | -------- |--|
 | NN | RT | RA  | RB  | im0-4 | im5-7 00 |0 |
@@ -251,6 +253,8 @@ Like the x86 AVX512F [vpternlogd/vpternlogq](https://www.felixcloutier.com/x86/v
 
 bits 21..22 may be used to specify a mode, such as treating the whole integer zero/nonzero and putting 1/0 in the result, rather than bitwise test.
 
+## ternlog
+
 a 4 operand variant which becomes more along the lines of an FPGA:
 
 | 0.5|6.10|11.15|16.20|21.25| 26...30  |31|
@@ -264,6 +268,8 @@ a 4 operand variant which becomes more along the lines of an FPGA:
 mode (2 bit) may be used to do inversion of ordering, similar to carryless mul,
 3 modes.
 
+## ternlogv
+
 also, another possible variant involving swizzle and vec4:
 
 | 0.5|6.10|11.15| 16.23 |24.27 | 28.30 |31|
@@ -276,6 +282,8 @@ also, another possible variant involving swizzle and vec4:
         for j in range(3):
              if mask[j]: RT[i+j*8] = res
 
+## ternlogcr
+
 another mode selection would be CRs not Ints. 
 
 | 0.5|6.8 | 9.11|12.14|15|16.23|24.27 | 28.30|31|