Clean up configs.

configs/common/FSConfig.py:
configs/common/SysPaths.py:
configs/example/fs.py:
configs/example/se.py:
tests/configs/o3-timing-mp.py:
tests/configs/o3-timing.py:
    Clean up configs by removing FullO3Config and instead using default values.
src/python/m5/objects/FUPool.py:
    Add in default FUPool.
src/python/m5/objects/O3CPU.py:
    Use defaults better.  Also set checker parameters, and fix up a config bug.

--HG--
extra : convert_revision : 5fd0c000143f4881f10a9a575c3810dc97cb290b

diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 67a1e57356392a519cf68b9a839e537287891792..470dc88671536f2e1d2cf100755bd5071022b356 100644 (file)
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -30,7 +30,6 @@ import m5
 from m5 import makeList
 from m5.objects import *
 from Benchmarks import *
-from FullO3Config import *
 
 class CowIdeDisk(IdeDisk):
     image = CowDiskImage(child=RawDiskImage(read_only=True),

diff --git a/configs/common/SysPaths.py b/configs/common/SysPaths.py
index 2070d11f80f0e9d9177f0c8b64e7ee20ed79eb98..5098c54cececc734f8773fe12a3e598bf57cba9e 100644 (file)
--- a/configs/common/SysPaths.py
+++ b/configs/common/SysPaths.py
@@ -58,7 +58,7 @@ def system():
     if not binary.dir:
         binary.dir = joinpath(system.dir, 'binaries')
     if not disk.dir:
-        disk.dir = joinpath(system.dir, 'disks')
+        disk.dir = joinpath('/n/zamp/z/ktlim/local/clean/linux', 'disks')
     if not script.dir:
         script.dir = joinpath(system.dir, 'boot')
 

diff --git a/configs/example/fs.py b/configs/example/fs.py
index 5edda6e5ff3685e4a6d45dfb888c8a28b8819e48..3d3313fbf5a0d49b99d3302a64dcbd65f790b160 100644 (file)
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -63,8 +63,8 @@ if args:
     sys.exit(1)
 
 if options.detailed:
-    cpu = DetailedO3CPU()
-    cpu2 = DetailedO3CPU()
+    cpu = DerivO3CPU()
+    cpu2 = DerivO3CPU()
     mem_mode = 'timing'
 elif options.timing:
     cpu = TimingSimpleCPU()

diff --git a/configs/example/se.py b/configs/example/se.py
index de8b6c890a3df1540376a3fda351f4db7f13f96d..7b8a52288c0f1a3e10143159159fe315af15c456 100644 (file)
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -34,7 +34,6 @@ import m5
 from m5.objects import *
 import os, optparse, sys
 m5.AddToPath('../common')
-from FullO3Config import *
 
 parser = optparse.OptionParser()
 
@@ -86,7 +85,7 @@ if options.detailed:
 if options.timing:
     cpu = TimingSimpleCPU()
 elif options.detailed:
-    cpu = DetailedO3CPU()
+    cpu = DerivO3CPU()
 else:
     cpu = AtomicSimpleCPU()
 

diff --git a/src/python/m5/objects/FUPool.py b/src/python/m5/objects/FUPool.py
index 4b4be79a6cd3962a14dbcd14318be98113ea0af1..916183bd796faf936256eb761c5491a1a77dfa6b 100644 (file)
--- a/src/python/m5/objects/FUPool.py
+++ b/src/python/m5/objects/FUPool.py
@@ -1,6 +1,12 @@
 from m5.SimObject import SimObject
 from m5.params import *
+from FuncUnit import *
+from FuncUnitConfig import *
 
 class FUPool(SimObject):
     type = 'FUPool'
     FUList = VectorParam.FUDesc("list of FU's for this pool")
+
+class DefaultFUPool(FUPool):
+    FUList = [ IntALU(), IntMultDiv(), FP_ALU(), FP_MultDiv(), ReadPort(),
+               WritePort(), RdWrPort(), IprPort() ]

diff --git a/src/python/m5/objects/FuncUnitConfig.py b/src/python/m5/objects/FuncUnitConfig.py
new file mode 100644 (file)
index 0000000..43d7a4b
--- /dev/null
+++ b/src/python/m5/objects/FuncUnitConfig.py
@@ -0,0 +1,41 @@
+from m5.SimObject import SimObject
+from m5.params import *
+from FuncUnit import *
+
+class IntALU(FUDesc):
+    opList = [ OpDesc(opClass='IntAlu') ]
+    count = 6
+
+class IntMultDiv(FUDesc):
+    opList = [ OpDesc(opClass='IntMult', opLat=3),
+               OpDesc(opClass='IntDiv', opLat=20, issueLat=19) ]
+    count=2
+
+class FP_ALU(FUDesc):
+    opList = [ OpDesc(opClass='FloatAdd', opLat=2),
+               OpDesc(opClass='FloatCmp', opLat=2),
+               OpDesc(opClass='FloatCvt', opLat=2) ]
+    count = 4
+
+class FP_MultDiv(FUDesc):
+    opList = [ OpDesc(opClass='FloatMult', opLat=4),
+               OpDesc(opClass='FloatDiv', opLat=12, issueLat=12),
+               OpDesc(opClass='FloatSqrt', opLat=24, issueLat=24) ]
+    count = 2
+
+class ReadPort(FUDesc):
+    opList = [ OpDesc(opClass='MemRead') ]
+    count = 0
+
+class WritePort(FUDesc):
+    opList = [ OpDesc(opClass='MemWrite') ]
+    count = 0
+
+class RdWrPort(FUDesc):
+    opList = [ OpDesc(opClass='MemRead'), OpDesc(opClass='MemWrite') ]
+    count = 4
+
+class IprPort(FUDesc):
+    opList = [ OpDesc(opClass='IprAccess', opLat = 3, issueLat = 3) ]
+    count = 1
+

diff --git a/src/python/m5/objects/O3CPU.py b/src/python/m5/objects/O3CPU.py
index 59b40c6e8e8096001b9dbcabb8f702421897a3dc..20eef383fe0337dcef299b7b3de88148ce1af474 100644 (file)
--- a/src/python/m5/objects/O3CPU.py
+++ b/src/python/m5/objects/O3CPU.py
@@ -3,6 +3,7 @@ from m5.proxy import *
 from m5 import build_env
 from BaseCPU import BaseCPU
 from Checker import O3Checker
+from FUPool import *
 
 class DerivO3CPU(BaseCPU):
     type = 'DerivO3CPU'
@@ -14,11 +15,13 @@ class DerivO3CPU(BaseCPU):
     if build_env['USE_CHECKER']:
         if not build_env['FULL_SYSTEM']:
             checker = Param.BaseCPU(O3Checker(workload=Parent.workload,
-                                              exitOnError=True,
+                                              exitOnError=False,
+                                              updateOnError=True,
                                               warnOnlyOnLoadError=False),
                                     "checker")
         else:
-            checker = Param.BaseCPU(O3Checker(exitOnError=True, warnOnlyOnLoadError=False), "checker")
+            checker = Param.BaseCPU(O3Checker(exitOnError=False, updateOnError=True,
+                                              warnOnlyOnLoadError=False), "checker")
             checker.itb = Parent.itb
             checker.dtb = Parent.dtb
 
@@ -57,7 +60,7 @@ class DerivO3CPU(BaseCPU):
     issueWidth = Param.Unsigned(8, "Issue width")
     wbWidth = Param.Unsigned(8, "Writeback width")
     wbDepth = Param.Unsigned(1, "Writeback depth")
-    fuPool = Param.FUPool("Functional Unit pool")
+    fuPool = Param.FUPool(DefaultFUPool(), "Functional Unit pool")
 
     iewToCommitDelay = Param.Unsigned(1, "Issue/Execute/Writeback to commit "
                "delay")
@@ -77,7 +80,7 @@ class DerivO3CPU(BaseCPU):
     localHistoryBits = Param.Unsigned(11, "Bits for the local history")
     globalPredictorSize = Param.Unsigned(8192, "Size of global predictor")
     globalCtrBits = Param.Unsigned(2, "Bits per counter")
-    globalHistoryBits = Param.Unsigned(4096, "Bits of history")
+    globalHistoryBits = Param.Unsigned(13, "Bits of history")
     choicePredictorSize = Param.Unsigned(8192, "Size of choice predictor")
     choiceCtrBits = Param.Unsigned(2, "Bits of choice counters")
 

diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py
index 881c23156af663483101aab7ce835bae6120b1ea..09935d574ae8873ecd594acbdb9358a68db0eb1e 100644 (file)
--- a/tests/configs/o3-timing-mp.py
+++ b/tests/configs/o3-timing-mp.py
@@ -29,7 +29,6 @@
 import m5
 from m5.objects import *
 m5.AddToPath('../configs/common')
-from FullO3Config import *
 
 # --------------------
 # Base L1 Cache
@@ -54,7 +53,7 @@ class L2(BaseCache):
     write_buffers = 8
 
 nb_cores = 4
-cpus = [ DetailedO3CPU() for i in xrange(nb_cores) ]
+cpus = [ DerivO3CPU() for i in xrange(nb_cores) ]
 
 # system simulated
 system = System(cpu = cpus, physmem = PhysicalMemory(), membus =

diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py
index 227e1ba2111ef4a6d0e024e74d3d1fc16408f4cb..0dd7be5066721a2bf5f7004a7c9f7fd037f5f163 100644 (file)
--- a/tests/configs/o3-timing.py
+++ b/tests/configs/o3-timing.py
@@ -29,7 +29,6 @@
 import m5
 from m5.objects import *
 m5.AddToPath('../configs/common')
-from FullO3Config import *
 
 class MyCache(BaseCache):
     assoc = 2
@@ -38,7 +37,7 @@ class MyCache(BaseCache):
     mshrs = 10
     tgts_per_mshr = 5
 
-cpu = DetailedO3CPU()
+cpu = DerivO3CPU()
 cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
                               MyCache(size = '2MB'))
 cpu.mem = cpu.dcache