elaborate immediate bits

diff --git a/openpower/sv/bitmanip/grev_gorc_design.mdwn b/openpower/sv/bitmanip/grev_gorc_design.mdwn
index b2e4ee66637f1825ef2dd6810d76577714630ede..6816db81bf97c8c6267f4f158b65f696833aa3dc 100644 (file)
--- a/openpower/sv/bitmanip/grev_gorc_design.mdwn
+++ b/openpower/sv/bitmanip/grev_gorc_design.mdwn
@@ -14,6 +14,6 @@ This gives us our final design:
 
 <img src="../grev_gorc_combination.svg" width="100%" height="100%" />
 
-Notice how this still has an overall circuit latency that is essentially equivalent to grev's latency (or shift/rotate's latency). Also notice how this circuit allows specifying much more than just `grev` or `gorc` instructions. A final layer of XOR gates can be added at the input and output, allowing it to function as a `gandc` instruction too, requiring a total of 6-bits of immediate.
+Notice how this still has an overall circuit latency that is essentially equivalent to grev's latency (or shift/rotate's latency). Also notice how this circuit allows specifying much more than just `grev` or `gorc` instructions. Layers of XOR gates can be added at the input and output, allowing it to function as a `gandc` instruction too, requiring a total of 6-bits of immediate (1 bit for inverting the input, 1 bit for inverting the output, 4 bits for the look-up-tables).
 
 We will also want versions of `grev` that have the shift amount be an immediate (needed for bitwise reverse and byte reversals and other similar instructions.) The immediate-shift-amount version can be specified to always do a `grev` (or maybe only `grev`/`gorc`) operation to save encoding space, since I'd guess it's much more common than any of the other immediate-shift variants.