i965/vs: add support for emitting SHL, SHR, ASR

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h b/src/mesa/drivers/dri/i965/brw_vec4.h
index 5f35de59bb5c755eba9461af783e2462e3409f91..ac1fb46875bc6538a77c45477063c600ef043a48 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -353,6 +353,9 @@ public:
    vec4_instruction *DP3(dst_reg dst, src_reg src0, src_reg src1);
    vec4_instruction *DP4(dst_reg dst, src_reg src0, src_reg src1);
    vec4_instruction *DPH(dst_reg dst, src_reg src0, src_reg src1);
+   vec4_instruction *SHL(dst_reg dst, src_reg src0, src_reg src1);
+   vec4_instruction *SHR(dst_reg dst, src_reg src0, src_reg src1);
+   vec4_instruction *ASR(dst_reg dst, src_reg src0, src_reg src1);
    vec4_instruction *CMP(dst_reg dst, src_reg src0, src_reg src1,
                         uint32_t condition);
    vec4_instruction *IF(src_reg src0, src_reg src1, uint32_t condition);

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 72766a2c29debbe0dfc8c08f9a113851bb0fb964..be5f8f2f99ce763b9394ed25c62ba679927e96ca 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -120,6 +120,9 @@ ALU2(XOR)
 ALU2(DP3)
 ALU2(DP4)
 ALU2(DPH)
+ALU2(SHL)
+ALU2(SHR)
+ALU2(ASR)
 
 /** Gen4 predicated IF. */
 vec4_instruction *
@@ -1324,14 +1327,14 @@ vec4_visitor::visit(ir_expression *ir)
       break;
 
    case ir_binop_lshift:
-      inst = emit(BRW_OPCODE_SHL, result_dst, op[0], op[1]);
+      inst = emit(SHL(result_dst, op[0], op[1]));
       break;
 
    case ir_binop_rshift:
       if (ir->type->base_type == GLSL_TYPE_INT)
-        inst = emit(BRW_OPCODE_ASR, result_dst, op[0], op[1]);
+         inst = emit(ASR(result_dst, op[0], op[1]));
       else
-        inst = emit(BRW_OPCODE_SHR, result_dst, op[0], op[1]);
+         inst = emit(SHR(result_dst, op[0], op[1]));
       break;
 
    case ir_binop_ubo_load: {
@@ -1350,7 +1353,7 @@ vec4_visitor::visit(ir_expression *ir)
       if (const_offset_ir) {
          offset = src_reg(const_offset / 16);
       } else {
-         emit(BRW_OPCODE_SHR, dst_reg(offset), offset, src_reg(4));
+         emit(SHR(dst_reg(offset), offset, src_reg(4)));
       }
 
       vec4_instruction *pull =