README: update nMigen libs paragraph

diff --git a/README.md b/README.md
index 79b55c359733a94b7baa400414d4a16f8414ba94..c50971ba9d36791ea49647d54708c8d265e83de2 100644 (file)
--- a/README.md
+++ b/README.md
@@ -8,7 +8,7 @@ Despite being faster than schematics entry, hardware design with Verilog and VHD
 
 To address those issues, we have developed the *nMigen FHDL*, a library that replaces the event-driven paradigm with the notions of combinatorial and synchronous statements, has arithmetic rules that make integers always behave like mathematical integers, and most importantly allows the design's logic to be constructed by a Python program. This last point enables hardware designers to take advantage of the richness of the Python language—object oriented programming, function parameters, generators, operator overloading, libraries, etc.—to build well organized, reusable and elegant designs.
 
-Other nMigen libraries are built on FHDL and provide various tools such as a system-on-chip interconnect infrastructure, a dataflow programming system, a more traditional high-level synthesizer that compiles Python routines into state machines with datapaths, and a simulator that allows test benches to be written in Python.
+Other nMigen libraries are built on FHDL and provide various tools and logic cores. nMigen also contains a simulator that allows test benches to be written in Python.
 
 See the [doc/](doc/) folder for more technical information.