ARM: Decode the unimplemented data barrier CP15 accesses.

These are CP15DSB (Data Synchronization Barrier), and CP15DMB (Data Memory
Barrier).

diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa
index ace90786f0d78497ddc6ddbf80b1743fa0059fed..e966fe423ccd795fec8a21121006c70e360bd4ad 100644 (file)
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -104,6 +104,12 @@ def format McrMrc15() {{
           case MISCREG_CP15ISB:
             return new WarnUnimplemented(
                     isRead ? "mrc cp15isb" : "mcr cp15isb", machInst);
+          case MISCREG_CP15DSB:
+            return new WarnUnimplemented(
+                    isRead ? "mrc cp15dsb" : "mcr cp15dsb", machInst);
+          case MISCREG_CP15DMB:
+            return new WarnUnimplemented(
+                    isRead ? "mrc cp15dmb" : "mcr cp15dmb", machInst);
           default:
             if (isRead) {
                 return new Mrc15(machInst, rt, (IntRegIndex)miscReg);

diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 4d603c65d851424754e899a184f3c7f0ba40c030..fa4c27bd94b74b546ef33c2d5a728ae80314e87d 100644 (file)
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -89,6 +89,8 @@ namespace ArmISA
         MISCREG_TPIDRURO,
         MISCREG_TPIDRPRW,
         MISCREG_CP15ISB,
+        MISCREG_CP15DSB,
+        MISCREG_CP15DMB,
         MISCREG_CPACR,
         MISCREG_CP15_UNIMP_START,
         MISCREG_CTR = MISCREG_CP15_UNIMP_START,
@@ -138,8 +140,6 @@ namespace ArmISA
         MISCREG_DCISW,
         MISCREG_DCCMVAC,
         MISCREG_MCCSW,
-        MISCREG_CP15DSB,
-        MISCREG_CP15DMB,
         MISCREG_DCCMVAU,
 
         MISCREG_CP15_END,
@@ -160,7 +160,8 @@ namespace ArmISA
         "fpsr", "fpsid", "fpscr", "fpexc",
         "sctlr", "dccisw", "dccimvac",
         "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
-        "cp15isb", "cpacr", "ctr", "tcmtr", "mpuir", "mpidr", "midr",
+        "cp15isb", "cp15dsb", "cp15dmb", "cpacr",
+        "ctr", "tcmtr", "mpuir", "mpidr", "midr",
         "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
         "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
         "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
@@ -169,7 +170,7 @@ namespace ArmISA
         "drbar", "irbar", "drsr", "irsr", "dracr", "iracr",
         "rgnr", "icialluis", "bpiallis", "iciallu", "icimvau",
         "bpiall", "bpimva", "dcimvac", "dcisw", "dccmvac", "mccsw",
-        "cp15dsb", "cp15dmb", "dccmvau",
+        "dccmvau",
         "nop", "raz"
     };