+2007-07-29 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/4834
+ * gas/i386/simd-intel.d: Updated.
+ * gas/i386/simd.d: Likewise.
+ * gas/i386/x86-64-simd-intel.d: Likewise.
+ * gas/i386/x86-64-simd.d: Likewise.
+
+ * gas/i386/simd.s: Add tests for SSE4 instructions.
+ * gas/i386/x86-64-simd.s: Likewise.
+
2007-07-29 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/simd.s: Add tests for cvtss2si/cvtsd2si in Intel
[ ]*[a-f0-9]+: f3 0f 51 00 sqrtss xmm0,DWORD PTR \[eax\]
[ ]*[a-f0-9]+: f2 0f 5c 00 subsd xmm0,QWORD PTR \[eax\]
[ ]*[a-f0-9]+: f3 0f 5c 00 subss xmm0,DWORD PTR \[eax\]
+[ ]*[a-f0-9]+: 66 0f 38 20 00 pmovsxbw xmm0,QWORD PTR \[eax\]
+[ ]*[a-f0-9]+: 66 0f 38 21 00 pmovsxbd xmm0,DWORD PTR \[eax\]
+[ ]*[a-f0-9]+: 66 0f 38 22 00 pmovsxbq xmm0,WORD PTR \[eax\]
+[ ]*[a-f0-9]+: 66 0f 38 23 00 pmovsxwd xmm0,QWORD PTR \[eax\]
+[ ]*[a-f0-9]+: 66 0f 38 24 00 pmovsxwq xmm0,DWORD PTR \[eax\]
+[ ]*[a-f0-9]+: 66 0f 38 25 00 pmovsxdq xmm0,QWORD PTR \[eax\]
+[ ]*[a-f0-9]+: 66 0f 38 30 00 pmovzxbw xmm0,QWORD PTR \[eax\]
+[ ]*[a-f0-9]+: 66 0f 38 31 00 pmovzxbd xmm0,DWORD PTR \[eax\]
+[ ]*[a-f0-9]+: 66 0f 38 32 00 pmovzxbq xmm0,WORD PTR \[eax\]
+[ ]*[a-f0-9]+: 66 0f 38 33 00 pmovzxwd xmm0,QWORD PTR \[eax\]
+[ ]*[a-f0-9]+: 66 0f 38 34 00 pmovzxwq xmm0,DWORD PTR \[eax\]
+[ ]*[a-f0-9]+: 66 0f 38 35 00 pmovzxdq xmm0,QWORD PTR \[eax\]
+[ ]*[a-f0-9]+: 66 0f 3a 21 00 00 insertps xmm0,DWORD PTR \[eax\],0x0
[ ]*[a-f0-9]+: f3 0f 2d 00 cvtss2si eax,DWORD PTR \[eax\]
[ ]*[a-f0-9]+: f2 0f 2d 00 cvtsd2si eax,QWORD PTR \[eax\]
#pass
[ ]*[a-f0-9]+: f3 0f 51 00 sqrtss \(%eax\),%xmm0
[ ]*[a-f0-9]+: f2 0f 5c 00 subsd \(%eax\),%xmm0
[ ]*[a-f0-9]+: f3 0f 5c 00 subss \(%eax\),%xmm0
+[ ]*[a-f0-9]+: 66 0f 38 20 00 pmovsxbw \(%eax\),%xmm0
+[ ]*[a-f0-9]+: 66 0f 38 21 00 pmovsxbd \(%eax\),%xmm0
+[ ]*[a-f0-9]+: 66 0f 38 22 00 pmovsxbq \(%eax\),%xmm0
+[ ]*[a-f0-9]+: 66 0f 38 23 00 pmovsxwd \(%eax\),%xmm0
+[ ]*[a-f0-9]+: 66 0f 38 24 00 pmovsxwq \(%eax\),%xmm0
+[ ]*[a-f0-9]+: 66 0f 38 25 00 pmovsxdq \(%eax\),%xmm0
+[ ]*[a-f0-9]+: 66 0f 38 30 00 pmovzxbw \(%eax\),%xmm0
+[ ]*[a-f0-9]+: 66 0f 38 31 00 pmovzxbd \(%eax\),%xmm0
+[ ]*[a-f0-9]+: 66 0f 38 32 00 pmovzxbq \(%eax\),%xmm0
+[ ]*[a-f0-9]+: 66 0f 38 33 00 pmovzxwd \(%eax\),%xmm0
+[ ]*[a-f0-9]+: 66 0f 38 34 00 pmovzxwq \(%eax\),%xmm0
+[ ]*[a-f0-9]+: 66 0f 38 35 00 pmovzxdq \(%eax\),%xmm0
+[ ]*[a-f0-9]+: 66 0f 3a 21 00 00 insertps \$0x0,\(%eax\),%xmm0
[ ]*[a-f0-9]+: f3 0f 2d 00 cvtss2si \(%eax\),%eax
[ ]*[a-f0-9]+: f2 0f 2d 00 cvtsd2si \(%eax\),%eax
#pass
subsd (%eax),%xmm0
subss (%eax),%xmm0
+ pmovsxbw (%eax),%xmm0
+ pmovsxbd (%eax),%xmm0
+ pmovsxbq (%eax),%xmm0
+ pmovsxwd (%eax),%xmm0
+ pmovsxwq (%eax),%xmm0
+ pmovsxdq (%eax),%xmm0
+ pmovzxbw (%eax),%xmm0
+ pmovzxbd (%eax),%xmm0
+ pmovzxbq (%eax),%xmm0
+ pmovzxwd (%eax),%xmm0
+ pmovzxwq (%eax),%xmm0
+ pmovzxdq (%eax),%xmm0
+ insertps $0x0,(%eax),%xmm0
+
.intel_syntax noprefix
cvtss2si eax,DWORD PTR [eax]
cvtsd2si eax,QWORD PTR [eax]
[ ]*[a-f0-9]+: f3 0f 51 00 sqrtss xmm0,DWORD PTR \[rax\]
[ ]*[a-f0-9]+: f2 0f 5c 00 subsd xmm0,QWORD PTR \[rax\]
[ ]*[a-f0-9]+: f3 0f 5c 00 subss xmm0,DWORD PTR \[rax\]
+[ ]*[a-f0-9]+: 66 0f 38 20 00 pmovsxbw xmm0,QWORD PTR \[rax\]
+[ ]*[a-f0-9]+: 66 0f 38 21 00 pmovsxbd xmm0,DWORD PTR \[rax\]
+[ ]*[a-f0-9]+: 66 0f 38 22 00 pmovsxbq xmm0,WORD PTR \[rax\]
+[ ]*[a-f0-9]+: 66 0f 38 23 00 pmovsxwd xmm0,QWORD PTR \[rax\]
+[ ]*[a-f0-9]+: 66 0f 38 24 00 pmovsxwq xmm0,DWORD PTR \[rax\]
+[ ]*[a-f0-9]+: 66 0f 38 25 00 pmovsxdq xmm0,QWORD PTR \[rax\]
+[ ]*[a-f0-9]+: 66 0f 38 30 00 pmovzxbw xmm0,QWORD PTR \[rax\]
+[ ]*[a-f0-9]+: 66 0f 38 31 00 pmovzxbd xmm0,DWORD PTR \[rax\]
+[ ]*[a-f0-9]+: 66 0f 38 32 00 pmovzxbq xmm0,WORD PTR \[rax\]
+[ ]*[a-f0-9]+: 66 0f 38 33 00 pmovzxwd xmm0,QWORD PTR \[rax\]
+[ ]*[a-f0-9]+: 66 0f 38 34 00 pmovzxwq xmm0,DWORD PTR \[rax\]
+[ ]*[a-f0-9]+: 66 0f 38 35 00 pmovzxdq xmm0,QWORD PTR \[rax\]
+[ ]*[a-f0-9]+: 66 0f 3a 21 00 00 insertps xmm0,DWORD PTR \[rax\],0x0
[ ]*[a-f0-9]+: f3 0f 2d 00 cvtss2si eax,DWORD PTR \[rax\]
[ ]*[a-f0-9]+: f3 48 0f 2d 00 cvtss2si rax,DWORD PTR \[rax\]
[ ]*[a-f0-9]+: f2 0f 2d 00 cvtsd2si eax,QWORD PTR \[rax\]
[ ]*[a-f0-9]+: f3 0f 51 00 sqrtss \(%rax\),%xmm0
[ ]*[a-f0-9]+: f2 0f 5c 00 subsd \(%rax\),%xmm0
[ ]*[a-f0-9]+: f3 0f 5c 00 subss \(%rax\),%xmm0
+[ ]*[a-f0-9]+: 66 0f 38 20 00 pmovsxbw \(%rax\),%xmm0
+[ ]*[a-f0-9]+: 66 0f 38 21 00 pmovsxbd \(%rax\),%xmm0
+[ ]*[a-f0-9]+: 66 0f 38 22 00 pmovsxbq \(%rax\),%xmm0
+[ ]*[a-f0-9]+: 66 0f 38 23 00 pmovsxwd \(%rax\),%xmm0
+[ ]*[a-f0-9]+: 66 0f 38 24 00 pmovsxwq \(%rax\),%xmm0
+[ ]*[a-f0-9]+: 66 0f 38 25 00 pmovsxdq \(%rax\),%xmm0
+[ ]*[a-f0-9]+: 66 0f 38 30 00 pmovzxbw \(%rax\),%xmm0
+[ ]*[a-f0-9]+: 66 0f 38 31 00 pmovzxbd \(%rax\),%xmm0
+[ ]*[a-f0-9]+: 66 0f 38 32 00 pmovzxbq \(%rax\),%xmm0
+[ ]*[a-f0-9]+: 66 0f 38 33 00 pmovzxwd \(%rax\),%xmm0
+[ ]*[a-f0-9]+: 66 0f 38 34 00 pmovzxwq \(%rax\),%xmm0
+[ ]*[a-f0-9]+: 66 0f 38 35 00 pmovzxdq \(%rax\),%xmm0
+[ ]*[a-f0-9]+: 66 0f 3a 21 00 00 insertps \$0x0,\(%rax\),%xmm0
[ ]*[a-f0-9]+: f3 0f 2d 00 cvtss2si \(%rax\),%eax
[ ]*[a-f0-9]+: f3 48 0f 2d 00 cvtss2siq \(%rax\),%rax
[ ]*[a-f0-9]+: f2 0f 2d 00 cvtsd2si \(%rax\),%eax
subsd (%rax),%xmm0
subss (%rax),%xmm0
+ pmovsxbw (%rax),%xmm0
+ pmovsxbd (%rax),%xmm0
+ pmovsxbq (%rax),%xmm0
+ pmovsxwd (%rax),%xmm0
+ pmovsxwq (%rax),%xmm0
+ pmovsxdq (%rax),%xmm0
+ pmovzxbw (%rax),%xmm0
+ pmovzxbd (%rax),%xmm0
+ pmovzxbq (%rax),%xmm0
+ pmovzxwd (%rax),%xmm0
+ pmovzxwq (%rax),%xmm0
+ pmovzxdq (%rax),%xmm0
+ insertps $0x0,(%rax),%xmm0
+
.intel_syntax noprefix
cvtss2si eax,DWORD PTR [rax]
cvtss2si rax,DWORD PTR [rax]
+2007-07-29 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutils/4834
+ * i386-dis.c (EXw): New.
+ (prefix_user_table): Updated to use EXw, EXd and EXq for SSE4
+ instructions when appropriated.
+
2007-07-28 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/4834
#define EM { OP_EM, v_mode }
#define EMd { OP_EM, d_mode }
#define EMx { OP_EM, x_mode }
+#define EXw { OP_EX, w_mode }
#define EXd { OP_EX, d_mode }
#define EXq { OP_EX, q_mode }
#define EXx { OP_EX, x_mode }
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { "pmovsxbw", { XM, EXx } },
+ { "pmovsxbw", { XM, EXq } },
{ "(bad)", { XX } },
},
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { "pmovsxbd", { XM, EXx } },
+ { "pmovsxbd", { XM, EXd } },
{ "(bad)", { XX } },
},
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { "pmovsxbq", { XM, EXx } },
+ { "pmovsxbq", { XM, EXw } },
{ "(bad)", { XX } },
},
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { "pmovsxwd", { XM, EXx } },
+ { "pmovsxwd", { XM, EXq } },
{ "(bad)", { XX } },
},
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { "pmovsxwq", { XM, EXx } },
+ { "pmovsxwq", { XM, EXd } },
{ "(bad)", { XX } },
},
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { "pmovsxdq", { XM, EXx } },
+ { "pmovsxdq", { XM, EXq } },
{ "(bad)", { XX } },
},
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { "pmovzxbw", { XM, EXx } },
+ { "pmovzxbw", { XM, EXq } },
{ "(bad)", { XX } },
},
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { "pmovzxbd", { XM, EXx } },
+ { "pmovzxbd", { XM, EXd } },
{ "(bad)", { XX } },
},
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { "pmovzxbq", { XM, EXx } },
+ { "pmovzxbq", { XM, EXw } },
{ "(bad)", { XX } },
},
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { "pmovzxwd", { XM, EXx } },
+ { "pmovzxwd", { XM, EXq } },
{ "(bad)", { XX } },
},
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { "pmovzxwq", { XM, EXx } },
+ { "pmovzxwq", { XM, EXd } },
{ "(bad)", { XX } },
},
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { "pmovzxdq", { XM, EXx } },
+ { "pmovzxdq", { XM, EXq } },
{ "(bad)", { XX } },
},
{
{ "(bad)", { XX } },
{ "(bad)", { XX } },
- { "insertps", { XM, EXx, Ib } },
+ { "insertps", { XM, EXd, Ib } },
{ "(bad)", { XX } },
},