SVP64-Single para

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index 5556e2701f31953f81205819c5e991935ea874e2..755951aa19cedc80e4369f7b9cefad39c8ea3cf6 100644 (file)
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -190,6 +190,15 @@ The primary options are:
   be saturated (without adding explicit scalar saturated opcodes)
 * Reduction and Prefix-Sum (Fibonnacci Series) Modes
 
+The `SVP64-Single` 24-bit encoding focusses primarily on ensuring that
+all 128 Scalar registers are fully accessible, provides element-width
+overrides, one-bit predication
+and brings Saturation to all existing Scalar operations.
+BF16 and FP16 are thus
+provided in the Scalar Power ISA without one single explicit FP16 or BF16
+32-bit opcode being added.  The downside: such Scalar operations are
+all 64-bit encodings.
+
 \newpage{}
 # Simple-V REMAP subsystem