add SVP64 RM LDST mode enum

diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index 0f0e7490605128852a13f0ad3be4ec30fc2fe9e9..429a1684872174ecf943527d1e47022592c8a9c6 100644 (file)
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -206,6 +206,12 @@ class SVP64sat(Enum):
     SIGNED = 1
     UNSIGNED = 2
 
+@unique
+class SVP64LDSTmode(Enum):
+    NORMAL = 0
+    ELSTRIDE = 1
+    UNITSTRIDE = 2
+
 
 # supported instructions: make sure to keep up-to-date with CSV files
 # just like everything else

diff --git a/src/openpower/decoder/power_svp64_rm.py b/src/openpower/decoder/power_svp64_rm.py
index 981e51a8d20c1d1e002b7bc512dbd8201fe0b9a9..d1d65e309531191c853b23368cad804ccb1c688e 100644 (file)
--- a/src/openpower/decoder/power_svp64_rm.py
+++ b/src/openpower/decoder/power_svp64_rm.py
@@ -41,7 +41,7 @@ https://libre-soc.org/openpower/sv/svp64/
 https://libre-soc.org/openpower/sv/ldst/
 
 LD/ST immed:
-00     str     sz dz   normal mode
+00     els     sz dz   normal mode
 01     inv     CR-bit  Rc=1: ffirst CR sel
 01     inv     els RC1 Rc=0: ffirst z/nonz
 10     N       dz els  sat mode: N=0/1 u/s