parser.add_option("--clock", action="store", type="string", default='1GHz')
parser.add_option("--num-dirs", type="int", default=1)
parser.add_option("--num-l2caches", type="int", default=1)
-parser.add_option("--topology", type="string", default="crossbar",
- help="'crossbar'|'mesh'")
+parser.add_option("--topology", type="string", default="Crossbar",
+ help="check src/mem/ruby/network/topologies for complete set")
parser.add_option("--mesh-rows", type="int", default=1,
help="the number of rows in the mesh topology")
parser.add_option("--garnet-network", type="string", default=none,
+++ /dev/null
-# Copyright (c) 2006-2007 The Regents of The University of Michigan
-# Copyright (c) 2009 Advanced Micro Devices, Inc.
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Brad Beckmann
-
-import math
-import m5
-from m5.objects import *
-from m5.defines import buildEnv
-from m5.util import addToPath
-
-#
-# Note: the L1 Cache latency is only used by the sequencer on fast path hits
-#
-class L1Cache(RubyCache):
- latency = 3
-
-#
-# Note: the L2 Cache latency is not currently used
-#
-class L2Cache(RubyCache):
- latency = 15
-
-def create_system(options, phys_mem, piobus, dma_devices):
-
- if buildEnv['PROTOCOL'] != 'MESI_CMP_directory':
- panic("This script requires the MESI_CMP_directory protocol to be built.")
-
- cpu_sequencers = []
-
- #
- # The ruby network creation expects the list of nodes in the system to be
- # consistent with the NetDest list. Therefore the l1 controller nodes must be
- # listed before the directory nodes and directory nodes before dma nodes, etc.
- #
- l1_cntrl_nodes = []
- l2_cntrl_nodes = []
- dir_cntrl_nodes = []
- dma_cntrl_nodes = []
-
- #
- # Must create the individual controllers before the network to ensure the
- # controller constructors are called before the network constructor
- #
-
- for i in xrange(options.num_cpus):
- #
- # First create the Ruby objects associated with this cpu
- #
- l1i_cache = L1Cache(size = options.l1i_size,
- assoc = options.l1i_assoc)
- l1d_cache = L1Cache(size = options.l1d_size,
- assoc = options.l1d_assoc)
-
- cpu_seq = RubySequencer(version = i,
- icache = l1i_cache,
- dcache = l1d_cache,
- physMemPort = phys_mem.port,
- physmem = phys_mem)
-
- if piobus != None:
- cpu_seq.pio_port = piobus.port
-
- l1_cntrl = L1Cache_Controller(version = i,
- sequencer = cpu_seq,
- L1IcacheMemory = l1i_cache,
- L1DcacheMemory = l1d_cache,
- l2_select_num_bits = \
- math.log(options.num_l2caches, 2))
- #
- # Add controllers and sequencers to the appropriate lists
- #
- cpu_sequencers.append(cpu_seq)
- l1_cntrl_nodes.append(l1_cntrl)
-
- for i in xrange(options.num_l2caches):
- #
- # First create the Ruby objects associated with this cpu
- #
- l2_cache = L2Cache(size = options.l2_size,
- assoc = options.l2_assoc)
-
- l2_cntrl = L2Cache_Controller(version = i,
- L2cacheMemory = l2_cache)
-
- l2_cntrl_nodes.append(l2_cntrl)
-
- phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) + 1
- mem_module_size = phys_mem_size / options.num_dirs
-
- for i in xrange(options.num_dirs):
- #
- # Create the Ruby objects associated with the directory controller
- #
-
- mem_cntrl = RubyMemoryControl(version = i)
-
- dir_size = MemorySize('0B')
- dir_size.value = mem_module_size
-
- dir_cntrl = Directory_Controller(version = i,
- directory = \
- RubyDirectoryMemory(version = i,
- size = dir_size),
- memBuffer = mem_cntrl)
-
- dir_cntrl_nodes.append(dir_cntrl)
-
- for i, dma_device in enumerate(dma_devices):
- #
- # Create the Ruby objects associated with the dma controller
- #
- dma_seq = DMASequencer(version = i,
- physMemPort = phys_mem.port,
- physmem = phys_mem)
-
- dma_cntrl = DMA_Controller(version = i,
- dma_sequencer = dma_seq)
-
- dma_cntrl.dma_sequencer.port = dma_device.dma
- dma_cntrl_nodes.append(dma_cntrl)
-
- all_cntrls = l1_cntrl_nodes + \
- l2_cntrl_nodes + \
- dir_cntrl_nodes + \
- dma_cntrl_nodes
-
- return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
+++ /dev/null
-# Copyright (c) 2006-2007 The Regents of The University of Michigan
-# Copyright (c) 2009 Advanced Micro Devices, Inc.
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Brad Beckmann
-
-import m5
-from m5.objects import *
-from m5.defines import buildEnv
-from m5.util import addToPath
-
-#
-# Note: the cache latency is only used by the sequencer on fast path hits
-#
-class Cache(RubyCache):
- latency = 3
-
-def create_system(options, phys_mem, piobus, dma_devices):
-
- if buildEnv['PROTOCOL'] != 'MI_example':
- panic("This script requires the MI_example protocol to be built.")
-
- cpu_sequencers = []
-
- #
- # The ruby network creation expects the list of nodes in the system to be
- # consistent with the NetDest list. Therefore the l1 controller nodes must be
- # listed before the directory nodes and directory nodes before dma nodes, etc.
- #
- l1_cntrl_nodes = []
- dir_cntrl_nodes = []
- dma_cntrl_nodes = []
-
- #
- # Must create the individual controllers before the network to ensure the
- # controller constructors are called before the network constructor
- #
-
- for i in xrange(options.num_cpus):
- #
- # First create the Ruby objects associated with this cpu
- # Only one cache exists for this protocol, so by default use the L1D
- # config parameters.
- #
- cache = Cache(size = options.l1d_size,
- assoc = options.l1d_assoc)
-
- #
- # Only one unified L1 cache exists. Can cache instructions and data.
- #
- cpu_seq = RubySequencer(version = i,
- icache = cache,
- dcache = cache,
- physMemPort = phys_mem.port,
- physmem = phys_mem)
-
- if piobus != None:
- cpu_seq.pio_port = piobus.port
-
- l1_cntrl = L1Cache_Controller(version = i,
- sequencer = cpu_seq,
- cacheMemory = cache)
- #
- # Add controllers and sequencers to the appropriate lists
- #
- cpu_sequencers.append(cpu_seq)
- l1_cntrl_nodes.append(l1_cntrl)
-
- phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) + 1
- mem_module_size = phys_mem_size / options.num_dirs
-
- for i in xrange(options.num_dirs):
- #
- # Create the Ruby objects associated with the directory controller
- #
-
- mem_cntrl = RubyMemoryControl(version = i)
-
- dir_size = MemorySize('0B')
- dir_size.value = mem_module_size
-
- dir_cntrl = Directory_Controller(version = i,
- directory = \
- RubyDirectoryMemory(version = i,
- size = dir_size,
- use_map = options.use_map,
- map_levels = options.map_levels),
- memBuffer = mem_cntrl)
-
- dir_cntrl_nodes.append(dir_cntrl)
-
- for i, dma_device in enumerate(dma_devices):
- #
- # Create the Ruby objects associated with the dma controller
- #
- dma_seq = DMASequencer(version = i,
- physMemPort = phys_mem.port,
- physmem = phys_mem)
-
- dma_cntrl = DMA_Controller(version = i,
- dma_sequencer = dma_seq)
-
- dma_cntrl.dma_sequencer.port = dma_device.dma
- dma_cntrl_nodes.append(dma_cntrl)
-
- all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
-
- return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
+++ /dev/null
-# Copyright (c) 2006-2007 The Regents of The University of Michigan
-# Copyright (c) 2009 Advanced Micro Devices, Inc.
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Brad Beckmann
-
-import math
-import m5
-from m5.objects import *
-from m5.defines import buildEnv
-from m5.util import addToPath
-
-#
-# Note: the L1 Cache latency is only used by the sequencer on fast path hits
-#
-class L1Cache(RubyCache):
- latency = 3
-
-#
-# Note: the L2 Cache latency is not currently used
-#
-class L2Cache(RubyCache):
- latency = 15
-
-def create_system(options, phys_mem, piobus, dma_devices):
-
- if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory':
- panic("This script requires the MOESI_CMP_directory protocol to be built.")
-
- cpu_sequencers = []
-
- #
- # The ruby network creation expects the list of nodes in the system to be
- # consistent with the NetDest list. Therefore the l1 controller nodes must be
- # listed before the directory nodes and directory nodes before dma nodes, etc.
- #
- l1_cntrl_nodes = []
- l2_cntrl_nodes = []
- dir_cntrl_nodes = []
- dma_cntrl_nodes = []
-
- #
- # Must create the individual controllers before the network to ensure the
- # controller constructors are called before the network constructor
- #
-
- for i in xrange(options.num_cpus):
- #
- # First create the Ruby objects associated with this cpu
- #
- l1i_cache = L1Cache(size = options.l1i_size,
- assoc = options.l1i_assoc)
- l1d_cache = L1Cache(size = options.l1d_size,
- assoc = options.l1d_assoc)
-
- cpu_seq = RubySequencer(version = i,
- icache = l1i_cache,
- dcache = l1d_cache,
- physMemPort = phys_mem.port,
- physmem = phys_mem)
-
- if piobus != None:
- cpu_seq.pio_port = piobus.port
-
- l1_cntrl = L1Cache_Controller(version = i,
- sequencer = cpu_seq,
- L1IcacheMemory = l1i_cache,
- L1DcacheMemory = l1d_cache,
- l2_select_num_bits = \
- math.log(options.num_l2caches, 2))
- #
- # Add controllers and sequencers to the appropriate lists
- #
- cpu_sequencers.append(cpu_seq)
- l1_cntrl_nodes.append(l1_cntrl)
-
- for i in xrange(options.num_l2caches):
- #
- # First create the Ruby objects associated with this cpu
- #
- l2_cache = L2Cache(size = options.l2_size,
- assoc = options.l2_assoc)
-
- l2_cntrl = L2Cache_Controller(version = i,
- L2cacheMemory = l2_cache)
-
- l2_cntrl_nodes.append(l2_cntrl)
-
- phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) + 1
- mem_module_size = phys_mem_size / options.num_dirs
-
- for i in xrange(options.num_dirs):
- #
- # Create the Ruby objects associated with the directory controller
- #
-
- mem_cntrl = RubyMemoryControl(version = i)
-
- dir_size = MemorySize('0B')
- dir_size.value = mem_module_size
-
- dir_cntrl = Directory_Controller(version = i,
- directory = \
- RubyDirectoryMemory(version = i,
- size = dir_size),
- memBuffer = mem_cntrl)
-
- dir_cntrl_nodes.append(dir_cntrl)
-
- for i, dma_device in enumerate(dma_devices):
- #
- # Create the Ruby objects associated with the dma controller
- #
- dma_seq = DMASequencer(version = i,
- physMemPort = phys_mem.port,
- physmem = phys_mem)
-
- dma_cntrl = DMA_Controller(version = i,
- dma_sequencer = dma_seq)
-
- dma_cntrl.dma_sequencer.port = dma_device.dma
- dma_cntrl_nodes.append(dma_cntrl)
-
- all_cntrls = l1_cntrl_nodes + \
- l2_cntrl_nodes + \
- dir_cntrl_nodes + \
- dma_cntrl_nodes
-
- return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
+++ /dev/null
-# Copyright (c) 2006-2007 The Regents of The University of Michigan
-# Copyright (c) 2009 Advanced Micro Devices, Inc.
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Brad Beckmann
-
-import math
-import m5
-from m5.objects import *
-from m5.defines import buildEnv
-from m5.util import addToPath
-
-#
-# Note: the L1 Cache latency is only used by the sequencer on fast path hits
-#
-class L1Cache(RubyCache):
- latency = 3
-
-#
-# Note: the L2 Cache latency is not currently used
-#
-class L2Cache(RubyCache):
- latency = 15
-
-def create_system(options, phys_mem, piobus, dma_devices):
-
- if buildEnv['PROTOCOL'] != 'MOESI_CMP_token':
- panic("This script requires the MOESI_CMP_token protocol to be built.")
-
- #
- # number of tokens that the owner passes to requests so that shared blocks can
- # respond to read requests
- #
- n_tokens = options.num_cpus + 1
-
- cpu_sequencers = []
-
- #
- # The ruby network creation expects the list of nodes in the system to be
- # consistent with the NetDest list. Therefore the l1 controller nodes must be
- # listed before the directory nodes and directory nodes before dma nodes, etc.
- #
- l1_cntrl_nodes = []
- l2_cntrl_nodes = []
- dir_cntrl_nodes = []
- dma_cntrl_nodes = []
-
- #
- # Must create the individual controllers before the network to ensure the
- # controller constructors are called before the network constructor
- #
-
- for i in xrange(options.num_cpus):
- #
- # First create the Ruby objects associated with this cpu
- #
- l1i_cache = L1Cache(size = options.l1i_size,
- assoc = options.l1i_assoc)
- l1d_cache = L1Cache(size = options.l1d_size,
- assoc = options.l1d_assoc)
-
- cpu_seq = RubySequencer(version = i,
- icache = l1i_cache,
- dcache = l1d_cache,
- physMemPort = phys_mem.port,
- physmem = phys_mem)
-
- if piobus != None:
- cpu_seq.pio_port = piobus.port
-
- l1_cntrl = L1Cache_Controller(version = i,
- sequencer = cpu_seq,
- L1IcacheMemory = l1i_cache,
- L1DcacheMemory = l1d_cache,
- l2_select_num_bits = \
- math.log(options.num_l2caches, 2),
- N_tokens = n_tokens)
- #
- # Add controllers and sequencers to the appropriate lists
- #
- cpu_sequencers.append(cpu_seq)
- l1_cntrl_nodes.append(l1_cntrl)
-
- for i in xrange(options.num_l2caches):
- #
- # First create the Ruby objects associated with this cpu
- #
- l2_cache = L2Cache(size = options.l2_size,
- assoc = options.l2_assoc)
-
- l2_cntrl = L2Cache_Controller(version = i,
- L2cacheMemory = l2_cache,
- N_tokens = n_tokens)
-
- l2_cntrl_nodes.append(l2_cntrl)
-
- phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) + 1
- mem_module_size = phys_mem_size / options.num_dirs
-
- for i in xrange(options.num_dirs):
- #
- # Create the Ruby objects associated with the directory controller
- #
-
- mem_cntrl = RubyMemoryControl(version = i)
-
- dir_size = MemorySize('0B')
- dir_size.value = mem_module_size
-
- dir_cntrl = Directory_Controller(version = i,
- directory = \
- RubyDirectoryMemory(version = i,
- size = dir_size),
- memBuffer = mem_cntrl,
- l2_select_num_bits = \
- math.log(options.num_l2caches, 2))
-
- dir_cntrl_nodes.append(dir_cntrl)
-
- for i, dma_device in enumerate(dma_devices):
- #
- # Create the Ruby objects associated with the dma controller
- #
- dma_seq = DMASequencer(version = i,
- physMemPort = phys_mem.port,
- physmem = phys_mem)
-
- dma_cntrl = DMA_Controller(version = i,
- dma_sequencer = dma_seq)
-
- dma_cntrl.dma_sequencer.port = dma_device.dma
- dma_cntrl_nodes.append(dma_cntrl)
-
- all_cntrls = l1_cntrl_nodes + \
- l2_cntrl_nodes + \
- dir_cntrl_nodes + \
- dma_cntrl_nodes
-
- return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
+++ /dev/null
-# Copyright (c) 2006-2007 The Regents of The University of Michigan
-# Copyright (c) 2009 Advanced Micro Devices, Inc.
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Brad Beckmann
-
-import m5
-from m5.objects import *
-from m5.defines import buildEnv
-from m5.util import addToPath
-
-
-#
-# Note: the L1 Cache latency is only used by the sequencer on fast path hits
-#
-class L1Cache(RubyCache):
- latency = 3
-
-#
-# Note: the L2 Cache latency is not currently used
-#
-class L2Cache(RubyCache):
- latency = 15
-
-def create_system(options, phys_mem, piobus, dma_devices):
-
- if buildEnv['PROTOCOL'] != 'MOESI_hammer':
- panic("This script requires the MOESI_hammer protocol to be built.")
-
- cpu_sequencers = []
-
- #
- # The ruby network creation expects the list of nodes in the system to be
- # consistent with the NetDest list. Therefore the l1 controller nodes must be
- # listed before the directory nodes and directory nodes before dma nodes, etc.
- #
- l1_cntrl_nodes = []
- dir_cntrl_nodes = []
- dma_cntrl_nodes = []
-
- #
- # Must create the individual controllers before the network to ensure the
- # controller constructors are called before the network constructor
- #
-
- for i in xrange(options.num_cpus):
- #
- # First create the Ruby objects associated with this cpu
- #
- l1i_cache = L1Cache(size = options.l1i_size,
- assoc = options.l1i_assoc)
- l1d_cache = L1Cache(size = options.l1d_size,
- assoc = options.l1d_assoc)
- l2_cache = L2Cache(size = options.l2_size,
- assoc = options.l2_assoc)
-
- cpu_seq = RubySequencer(version = i,
- icache = l1i_cache,
- dcache = l1d_cache,
- physMemPort = phys_mem.port,
- physmem = phys_mem)
-
- if piobus != None:
- cpu_seq.pio_port = piobus.port
-
- l1_cntrl = L1Cache_Controller(version = i,
- sequencer = cpu_seq,
- L1IcacheMemory = l1i_cache,
- L1DcacheMemory = l1d_cache,
- L2cacheMemory = l2_cache)
- #
- # Add controllers and sequencers to the appropriate lists
- #
- cpu_sequencers.append(cpu_seq)
- l1_cntrl_nodes.append(l1_cntrl)
-
- phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) + 1
- mem_module_size = phys_mem_size / options.num_dirs
-
- for i in xrange(options.num_dirs):
- #
- # Create the Ruby objects associated with the directory controller
- #
-
- mem_cntrl = RubyMemoryControl(version = i)
-
- dir_size = MemorySize('0B')
- dir_size.value = mem_module_size
-
- dir_cntrl = Directory_Controller(version = i,
- directory = \
- RubyDirectoryMemory(version = i,
- size = dir_size,
- use_map = options.use_map,
- map_levels = options.map_levels),
- memBuffer = mem_cntrl)
-
- dir_cntrl_nodes.append(dir_cntrl)
-
- for i, dma_device in enumerate(dma_devices):
- #
- # Create the Ruby objects associated with the dma controller
- #
- dma_seq = DMASequencer(version = i,
- physMemPort = phys_mem.port,
- physmem = phys_mem)
-
- dma_cntrl = DMA_Controller(version = i,
- dma_sequencer = dma_seq)
-
- dma_cntrl.dma_sequencer.port = dma_device.dma
- dma_cntrl_nodes.append(dma_cntrl)
-
- all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
-
- return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
from m5.objects import *
from m5.defines import buildEnv
from m5.util import addToPath
-addToPath('../ruby/networks')
-from MeshDirCorners import *
-
-protocol = buildEnv['PROTOCOL']
-
-exec "import %s" % protocol
def create_system(options, physmem, piobus = None, dma_devices = []):
+ protocol = buildEnv['PROTOCOL']
+ exec "import %s" % protocol
try:
(cpu_sequencers, dir_cntrls, all_cntrls) = \
eval("%s.create_system(options, physmem, piobus, dma_devices)" \
sys.exit(1)
#
- # Important: the topology constructor must be called before the network
- # constructor.
+ # Important: the topology must be created before the network and after the
+ # controllers.
#
- if options.topology == "crossbar":
- net_topology = makeCrossbar(all_cntrls)
- elif options.topology == "mesh":
- #
- # The uniform mesh topology assumes one router per cpu
- #
- net_topology = makeMesh(all_cntrls,
- len(cpu_sequencers),
- options.mesh_rows)
+ exec "import %s" % options.topology
+ try:
+ net_topology = eval("%s.makeTopology(all_cntrls, options)" % options.topology)
+ except:
+ print "Error: could not create topology %s" % options.topology
+ sys.exit(1)
- elif options.topology == "mesh_dir_corner":
- #
- # The uniform mesh topology assumes one router per cpu
- #
- net_topology = makeMeshDirCorners(all_cntrls,
- len(cpu_sequencers),
- options.mesh_rows)
-
if options.garnet_network == "fixed":
network = GarnetNetwork_d(topology = net_topology)
elif options.garnet_network == "flexible":
+++ /dev/null
-# Copyright (c) 2010 Advanced Micro Devices, Inc.
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Authors: Brad Beckmann
-
-from m5.params import *
-from m5.objects import *
-
-#
-# This file contains a special network creation function. This networks is not
-# general and will only work with specific system configurations. The network
-# specified is similar to GEMS old file specified network.
-#
-
-def makeMeshDirCorners(nodes, num_routers, num_rows):
- #
- # First determine which nodes are cache cntrls vs. dirs vs. dma
- #
- cache_nodes = []
- dir_nodes = []
- dma_nodes = []
- for node in nodes:
- if node.type == 'L1Cache_Controller' or \
- node.type == 'L2Cache_Controller':
- cache_nodes.append(node)
- elif node.type == 'Directory_Controller':
- dir_nodes.append(node)
- elif node.type == 'DMA_Controller':
- dma_nodes.append(node)
-
- #
- # Obviously the number or rows must be <= the number of routers and evenly
- # divisible. Also the number of caches must be a multiple of the number of
- # routers and the number of directories must be four.
- #
- assert(num_rows <= num_routers)
- num_columns = int(num_routers / num_rows)
- assert(num_columns * num_rows == num_routers)
- caches_per_router, remainder = divmod(len(cache_nodes), num_routers)
- assert(remainder == 0)
- assert(len(dir_nodes) == 4)
-
- #
- # Connect each cache controller to the appropriate router
- #
- ext_links = []
- for (i, n) in enumerate(cache_nodes):
- cntrl_level, router_id = divmod(i, num_routers)
- assert(cntrl_level < caches_per_router)
- ext_links.append(ExtLink(ext_node=n, int_node=router_id))
-
- #
- # Connect the dir nodes to the corners.
- #
- ext_links.append(ExtLink(ext_node=dir_nodes[0], int_node=0))
- ext_links.append(ExtLink(ext_node=dir_nodes[1], int_node=(num_columns - 1)))
-
- ext_links.append(ExtLink(ext_node=dir_nodes[2],
- int_node=(num_routers - num_columns)))
-
- ext_links.append(ExtLink(ext_node=dir_nodes[3], int_node=(num_routers - 1)))
-
- #
- # Connect the dma nodes to router 0. These should only be DMA nodes.
- #
- for (i, node) in enumerate(dma_nodes):
- assert(node.type == 'DMA_Controller')
- ext_links.append(ExtLink(ext_node=node, int_node=0))
-
- #
- # Create the mesh links. First row (east-west) links then column
- # (north-south) links
- #
- int_links = []
- for row in xrange(num_rows):
- for col in xrange(num_columns):
- if (col + 1 < num_columns):
- east_id = col + (row * num_columns)
- west_id = (col + 1) + (row * num_columns)
- int_links.append(IntLink(node_a=east_id,
- node_b=west_id,
- weight=1))
- for col in xrange(num_columns):
- for row in xrange(num_rows):
- if (row + 1 < num_rows):
- north_id = col + (row * num_columns)
- south_id = col + ((row + 1) * num_columns)
- int_links.append(IntLink(node_a=north_id,
- node_b=south_id,
- weight=2))
-
- return Topology(ext_links=ext_links,
- int_links=int_links,
- num_int_nodes=num_routers)
-
--- /dev/null
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# Copyright (c) 2009 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Brad Beckmann
+
+import math
+import m5
+from m5.objects import *
+from m5.defines import buildEnv
+from m5.util import addToPath
+
+#
+# Note: the L1 Cache latency is only used by the sequencer on fast path hits
+#
+class L1Cache(RubyCache):
+ latency = 3
+
+#
+# Note: the L2 Cache latency is not currently used
+#
+class L2Cache(RubyCache):
+ latency = 15
+
+def create_system(options, phys_mem, piobus, dma_devices):
+
+ if buildEnv['PROTOCOL'] != 'MESI_CMP_directory':
+ panic("This script requires the MESI_CMP_directory protocol to be built.")
+
+ cpu_sequencers = []
+
+ #
+ # The ruby network creation expects the list of nodes in the system to be
+ # consistent with the NetDest list. Therefore the l1 controller nodes must be
+ # listed before the directory nodes and directory nodes before dma nodes, etc.
+ #
+ l1_cntrl_nodes = []
+ l2_cntrl_nodes = []
+ dir_cntrl_nodes = []
+ dma_cntrl_nodes = []
+
+ #
+ # Must create the individual controllers before the network to ensure the
+ # controller constructors are called before the network constructor
+ #
+
+ for i in xrange(options.num_cpus):
+ #
+ # First create the Ruby objects associated with this cpu
+ #
+ l1i_cache = L1Cache(size = options.l1i_size,
+ assoc = options.l1i_assoc)
+ l1d_cache = L1Cache(size = options.l1d_size,
+ assoc = options.l1d_assoc)
+
+ cpu_seq = RubySequencer(version = i,
+ icache = l1i_cache,
+ dcache = l1d_cache,
+ physMemPort = phys_mem.port,
+ physmem = phys_mem)
+
+ if piobus != None:
+ cpu_seq.pio_port = piobus.port
+
+ l1_cntrl = L1Cache_Controller(version = i,
+ sequencer = cpu_seq,
+ L1IcacheMemory = l1i_cache,
+ L1DcacheMemory = l1d_cache,
+ l2_select_num_bits = \
+ math.log(options.num_l2caches, 2))
+ #
+ # Add controllers and sequencers to the appropriate lists
+ #
+ cpu_sequencers.append(cpu_seq)
+ l1_cntrl_nodes.append(l1_cntrl)
+
+ for i in xrange(options.num_l2caches):
+ #
+ # First create the Ruby objects associated with this cpu
+ #
+ l2_cache = L2Cache(size = options.l2_size,
+ assoc = options.l2_assoc)
+
+ l2_cntrl = L2Cache_Controller(version = i,
+ L2cacheMemory = l2_cache)
+
+ l2_cntrl_nodes.append(l2_cntrl)
+
+ phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) + 1
+ mem_module_size = phys_mem_size / options.num_dirs
+
+ for i in xrange(options.num_dirs):
+ #
+ # Create the Ruby objects associated with the directory controller
+ #
+
+ mem_cntrl = RubyMemoryControl(version = i)
+
+ dir_size = MemorySize('0B')
+ dir_size.value = mem_module_size
+
+ dir_cntrl = Directory_Controller(version = i,
+ directory = \
+ RubyDirectoryMemory(version = i,
+ size = dir_size),
+ memBuffer = mem_cntrl)
+
+ dir_cntrl_nodes.append(dir_cntrl)
+
+ for i, dma_device in enumerate(dma_devices):
+ #
+ # Create the Ruby objects associated with the dma controller
+ #
+ dma_seq = DMASequencer(version = i,
+ physMemPort = phys_mem.port,
+ physmem = phys_mem)
+
+ dma_cntrl = DMA_Controller(version = i,
+ dma_sequencer = dma_seq)
+
+ dma_cntrl.dma_sequencer.port = dma_device.dma
+ dma_cntrl_nodes.append(dma_cntrl)
+
+ all_cntrls = l1_cntrl_nodes + \
+ l2_cntrl_nodes + \
+ dir_cntrl_nodes + \
+ dma_cntrl_nodes
+
+ return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
--- /dev/null
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# Copyright (c) 2009 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Brad Beckmann
+
+import m5
+from m5.objects import *
+from m5.defines import buildEnv
+from m5.util import addToPath
+
+#
+# Note: the cache latency is only used by the sequencer on fast path hits
+#
+class Cache(RubyCache):
+ latency = 3
+
+def create_system(options, phys_mem, piobus, dma_devices):
+
+ if buildEnv['PROTOCOL'] != 'MI_example':
+ panic("This script requires the MI_example protocol to be built.")
+
+ cpu_sequencers = []
+
+ #
+ # The ruby network creation expects the list of nodes in the system to be
+ # consistent with the NetDest list. Therefore the l1 controller nodes must be
+ # listed before the directory nodes and directory nodes before dma nodes, etc.
+ #
+ l1_cntrl_nodes = []
+ dir_cntrl_nodes = []
+ dma_cntrl_nodes = []
+
+ #
+ # Must create the individual controllers before the network to ensure the
+ # controller constructors are called before the network constructor
+ #
+
+ for i in xrange(options.num_cpus):
+ #
+ # First create the Ruby objects associated with this cpu
+ # Only one cache exists for this protocol, so by default use the L1D
+ # config parameters.
+ #
+ cache = Cache(size = options.l1d_size,
+ assoc = options.l1d_assoc)
+
+ #
+ # Only one unified L1 cache exists. Can cache instructions and data.
+ #
+ cpu_seq = RubySequencer(version = i,
+ icache = cache,
+ dcache = cache,
+ physMemPort = phys_mem.port,
+ physmem = phys_mem)
+
+ if piobus != None:
+ cpu_seq.pio_port = piobus.port
+
+ l1_cntrl = L1Cache_Controller(version = i,
+ sequencer = cpu_seq,
+ cacheMemory = cache)
+ #
+ # Add controllers and sequencers to the appropriate lists
+ #
+ cpu_sequencers.append(cpu_seq)
+ l1_cntrl_nodes.append(l1_cntrl)
+
+ phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) + 1
+ mem_module_size = phys_mem_size / options.num_dirs
+
+ for i in xrange(options.num_dirs):
+ #
+ # Create the Ruby objects associated with the directory controller
+ #
+
+ mem_cntrl = RubyMemoryControl(version = i)
+
+ dir_size = MemorySize('0B')
+ dir_size.value = mem_module_size
+
+ dir_cntrl = Directory_Controller(version = i,
+ directory = \
+ RubyDirectoryMemory(version = i,
+ size = dir_size,
+ use_map = options.use_map,
+ map_levels = options.map_levels),
+ memBuffer = mem_cntrl)
+
+ dir_cntrl_nodes.append(dir_cntrl)
+
+ for i, dma_device in enumerate(dma_devices):
+ #
+ # Create the Ruby objects associated with the dma controller
+ #
+ dma_seq = DMASequencer(version = i,
+ physMemPort = phys_mem.port,
+ physmem = phys_mem)
+
+ dma_cntrl = DMA_Controller(version = i,
+ dma_sequencer = dma_seq)
+
+ dma_cntrl.dma_sequencer.port = dma_device.dma
+ dma_cntrl_nodes.append(dma_cntrl)
+
+ all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
+
+ return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
--- /dev/null
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# Copyright (c) 2009 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Brad Beckmann
+
+import math
+import m5
+from m5.objects import *
+from m5.defines import buildEnv
+from m5.util import addToPath
+
+#
+# Note: the L1 Cache latency is only used by the sequencer on fast path hits
+#
+class L1Cache(RubyCache):
+ latency = 3
+
+#
+# Note: the L2 Cache latency is not currently used
+#
+class L2Cache(RubyCache):
+ latency = 15
+
+def create_system(options, phys_mem, piobus, dma_devices):
+
+ if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory':
+ panic("This script requires the MOESI_CMP_directory protocol to be built.")
+
+ cpu_sequencers = []
+
+ #
+ # The ruby network creation expects the list of nodes in the system to be
+ # consistent with the NetDest list. Therefore the l1 controller nodes must be
+ # listed before the directory nodes and directory nodes before dma nodes, etc.
+ #
+ l1_cntrl_nodes = []
+ l2_cntrl_nodes = []
+ dir_cntrl_nodes = []
+ dma_cntrl_nodes = []
+
+ #
+ # Must create the individual controllers before the network to ensure the
+ # controller constructors are called before the network constructor
+ #
+
+ for i in xrange(options.num_cpus):
+ #
+ # First create the Ruby objects associated with this cpu
+ #
+ l1i_cache = L1Cache(size = options.l1i_size,
+ assoc = options.l1i_assoc)
+ l1d_cache = L1Cache(size = options.l1d_size,
+ assoc = options.l1d_assoc)
+
+ cpu_seq = RubySequencer(version = i,
+ icache = l1i_cache,
+ dcache = l1d_cache,
+ physMemPort = phys_mem.port,
+ physmem = phys_mem)
+
+ if piobus != None:
+ cpu_seq.pio_port = piobus.port
+
+ l1_cntrl = L1Cache_Controller(version = i,
+ sequencer = cpu_seq,
+ L1IcacheMemory = l1i_cache,
+ L1DcacheMemory = l1d_cache,
+ l2_select_num_bits = \
+ math.log(options.num_l2caches, 2))
+ #
+ # Add controllers and sequencers to the appropriate lists
+ #
+ cpu_sequencers.append(cpu_seq)
+ l1_cntrl_nodes.append(l1_cntrl)
+
+ for i in xrange(options.num_l2caches):
+ #
+ # First create the Ruby objects associated with this cpu
+ #
+ l2_cache = L2Cache(size = options.l2_size,
+ assoc = options.l2_assoc)
+
+ l2_cntrl = L2Cache_Controller(version = i,
+ L2cacheMemory = l2_cache)
+
+ l2_cntrl_nodes.append(l2_cntrl)
+
+ phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) + 1
+ mem_module_size = phys_mem_size / options.num_dirs
+
+ for i in xrange(options.num_dirs):
+ #
+ # Create the Ruby objects associated with the directory controller
+ #
+
+ mem_cntrl = RubyMemoryControl(version = i)
+
+ dir_size = MemorySize('0B')
+ dir_size.value = mem_module_size
+
+ dir_cntrl = Directory_Controller(version = i,
+ directory = \
+ RubyDirectoryMemory(version = i,
+ size = dir_size),
+ memBuffer = mem_cntrl)
+
+ dir_cntrl_nodes.append(dir_cntrl)
+
+ for i, dma_device in enumerate(dma_devices):
+ #
+ # Create the Ruby objects associated with the dma controller
+ #
+ dma_seq = DMASequencer(version = i,
+ physMemPort = phys_mem.port,
+ physmem = phys_mem)
+
+ dma_cntrl = DMA_Controller(version = i,
+ dma_sequencer = dma_seq)
+
+ dma_cntrl.dma_sequencer.port = dma_device.dma
+ dma_cntrl_nodes.append(dma_cntrl)
+
+ all_cntrls = l1_cntrl_nodes + \
+ l2_cntrl_nodes + \
+ dir_cntrl_nodes + \
+ dma_cntrl_nodes
+
+ return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
--- /dev/null
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# Copyright (c) 2009 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Brad Beckmann
+
+import math
+import m5
+from m5.objects import *
+from m5.defines import buildEnv
+from m5.util import addToPath
+
+#
+# Note: the L1 Cache latency is only used by the sequencer on fast path hits
+#
+class L1Cache(RubyCache):
+ latency = 3
+
+#
+# Note: the L2 Cache latency is not currently used
+#
+class L2Cache(RubyCache):
+ latency = 15
+
+def create_system(options, phys_mem, piobus, dma_devices):
+
+ if buildEnv['PROTOCOL'] != 'MOESI_CMP_token':
+ panic("This script requires the MOESI_CMP_token protocol to be built.")
+
+ #
+ # number of tokens that the owner passes to requests so that shared blocks can
+ # respond to read requests
+ #
+ n_tokens = options.num_cpus + 1
+
+ cpu_sequencers = []
+
+ #
+ # The ruby network creation expects the list of nodes in the system to be
+ # consistent with the NetDest list. Therefore the l1 controller nodes must be
+ # listed before the directory nodes and directory nodes before dma nodes, etc.
+ #
+ l1_cntrl_nodes = []
+ l2_cntrl_nodes = []
+ dir_cntrl_nodes = []
+ dma_cntrl_nodes = []
+
+ #
+ # Must create the individual controllers before the network to ensure the
+ # controller constructors are called before the network constructor
+ #
+
+ for i in xrange(options.num_cpus):
+ #
+ # First create the Ruby objects associated with this cpu
+ #
+ l1i_cache = L1Cache(size = options.l1i_size,
+ assoc = options.l1i_assoc)
+ l1d_cache = L1Cache(size = options.l1d_size,
+ assoc = options.l1d_assoc)
+
+ cpu_seq = RubySequencer(version = i,
+ icache = l1i_cache,
+ dcache = l1d_cache,
+ physMemPort = phys_mem.port,
+ physmem = phys_mem)
+
+ if piobus != None:
+ cpu_seq.pio_port = piobus.port
+
+ l1_cntrl = L1Cache_Controller(version = i,
+ sequencer = cpu_seq,
+ L1IcacheMemory = l1i_cache,
+ L1DcacheMemory = l1d_cache,
+ l2_select_num_bits = \
+ math.log(options.num_l2caches, 2),
+ N_tokens = n_tokens)
+ #
+ # Add controllers and sequencers to the appropriate lists
+ #
+ cpu_sequencers.append(cpu_seq)
+ l1_cntrl_nodes.append(l1_cntrl)
+
+ for i in xrange(options.num_l2caches):
+ #
+ # First create the Ruby objects associated with this cpu
+ #
+ l2_cache = L2Cache(size = options.l2_size,
+ assoc = options.l2_assoc)
+
+ l2_cntrl = L2Cache_Controller(version = i,
+ L2cacheMemory = l2_cache,
+ N_tokens = n_tokens)
+
+ l2_cntrl_nodes.append(l2_cntrl)
+
+ phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) + 1
+ mem_module_size = phys_mem_size / options.num_dirs
+
+ for i in xrange(options.num_dirs):
+ #
+ # Create the Ruby objects associated with the directory controller
+ #
+
+ mem_cntrl = RubyMemoryControl(version = i)
+
+ dir_size = MemorySize('0B')
+ dir_size.value = mem_module_size
+
+ dir_cntrl = Directory_Controller(version = i,
+ directory = \
+ RubyDirectoryMemory(version = i,
+ size = dir_size),
+ memBuffer = mem_cntrl,
+ l2_select_num_bits = \
+ math.log(options.num_l2caches, 2))
+
+ dir_cntrl_nodes.append(dir_cntrl)
+
+ for i, dma_device in enumerate(dma_devices):
+ #
+ # Create the Ruby objects associated with the dma controller
+ #
+ dma_seq = DMASequencer(version = i,
+ physMemPort = phys_mem.port,
+ physmem = phys_mem)
+
+ dma_cntrl = DMA_Controller(version = i,
+ dma_sequencer = dma_seq)
+
+ dma_cntrl.dma_sequencer.port = dma_device.dma
+ dma_cntrl_nodes.append(dma_cntrl)
+
+ all_cntrls = l1_cntrl_nodes + \
+ l2_cntrl_nodes + \
+ dir_cntrl_nodes + \
+ dma_cntrl_nodes
+
+ return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
--- /dev/null
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# Copyright (c) 2009 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Brad Beckmann
+
+import m5
+from m5.objects import *
+from m5.defines import buildEnv
+from m5.util import addToPath
+
+
+#
+# Note: the L1 Cache latency is only used by the sequencer on fast path hits
+#
+class L1Cache(RubyCache):
+ latency = 3
+
+#
+# Note: the L2 Cache latency is not currently used
+#
+class L2Cache(RubyCache):
+ latency = 15
+
+def create_system(options, phys_mem, piobus, dma_devices):
+
+ if buildEnv['PROTOCOL'] != 'MOESI_hammer':
+ panic("This script requires the MOESI_hammer protocol to be built.")
+
+ cpu_sequencers = []
+
+ #
+ # The ruby network creation expects the list of nodes in the system to be
+ # consistent with the NetDest list. Therefore the l1 controller nodes must be
+ # listed before the directory nodes and directory nodes before dma nodes, etc.
+ #
+ l1_cntrl_nodes = []
+ dir_cntrl_nodes = []
+ dma_cntrl_nodes = []
+
+ #
+ # Must create the individual controllers before the network to ensure the
+ # controller constructors are called before the network constructor
+ #
+
+ for i in xrange(options.num_cpus):
+ #
+ # First create the Ruby objects associated with this cpu
+ #
+ l1i_cache = L1Cache(size = options.l1i_size,
+ assoc = options.l1i_assoc)
+ l1d_cache = L1Cache(size = options.l1d_size,
+ assoc = options.l1d_assoc)
+ l2_cache = L2Cache(size = options.l2_size,
+ assoc = options.l2_assoc)
+
+ cpu_seq = RubySequencer(version = i,
+ icache = l1i_cache,
+ dcache = l1d_cache,
+ physMemPort = phys_mem.port,
+ physmem = phys_mem)
+
+ if piobus != None:
+ cpu_seq.pio_port = piobus.port
+
+ l1_cntrl = L1Cache_Controller(version = i,
+ sequencer = cpu_seq,
+ L1IcacheMemory = l1i_cache,
+ L1DcacheMemory = l1d_cache,
+ L2cacheMemory = l2_cache)
+ #
+ # Add controllers and sequencers to the appropriate lists
+ #
+ cpu_sequencers.append(cpu_seq)
+ l1_cntrl_nodes.append(l1_cntrl)
+
+ phys_mem_size = long(phys_mem.range.second) - long(phys_mem.range.first) + 1
+ mem_module_size = phys_mem_size / options.num_dirs
+
+ for i in xrange(options.num_dirs):
+ #
+ # Create the Ruby objects associated with the directory controller
+ #
+
+ mem_cntrl = RubyMemoryControl(version = i)
+
+ dir_size = MemorySize('0B')
+ dir_size.value = mem_module_size
+
+ dir_cntrl = Directory_Controller(version = i,
+ directory = \
+ RubyDirectoryMemory(version = i,
+ size = dir_size,
+ use_map = options.use_map,
+ map_levels = options.map_levels),
+ memBuffer = mem_cntrl)
+
+ dir_cntrl_nodes.append(dir_cntrl)
+
+ for i, dma_device in enumerate(dma_devices):
+ #
+ # Create the Ruby objects associated with the dma controller
+ #
+ dma_seq = DMASequencer(version = i,
+ physMemPort = phys_mem.port,
+ physmem = phys_mem)
+
+ dma_cntrl = DMA_Controller(version = i,
+ dma_sequencer = dma_seq)
+
+ dma_cntrl.dma_sequencer.port = dma_device.dma
+ dma_cntrl_nodes.append(dma_cntrl)
+
+ all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes
+
+ return (cpu_sequencers, dir_cntrl_nodes, all_cntrls)
print_config = Param.Bool(False,
"display topology config in the stats file")
-def makeCrossbar(nodes):
- ext_links = [ExtLink(ext_node=n, int_node=i)
- for (i, n) in enumerate(nodes)]
- xbar = len(nodes) # node ID for crossbar switch
- int_links = [IntLink(node_a=i, node_b=xbar) for i in range(len(nodes))]
- return Topology(ext_links=ext_links, int_links=int_links,
- num_int_nodes=len(nodes)+1)
-
-def makeMesh(nodes, num_routers, num_rows):
- #
- # There must be an evenly divisible number of cntrls to routers
- # Also, obviously the number or rows must be <= the number of routers
- #
- cntrls_per_router, remainder = divmod(len(nodes), num_routers)
- assert(num_rows <= num_routers)
- num_columns = int(num_routers / num_rows)
- assert(num_columns * num_rows == num_routers)
-
- #
- # Add all but the remainder nodes to the list of nodes to be uniformly
- # distributed across the network.
- #
- network_nodes = []
- remainder_nodes = []
- for node_index in xrange(len(nodes)):
- if node_index < (len(nodes) - remainder):
- network_nodes.append(nodes[node_index])
- else:
- remainder_nodes.append(nodes[node_index])
-
- #
- # Connect each node to the appropriate router
- #
- ext_links = []
- for (i, n) in enumerate(network_nodes):
- cntrl_level, router_id = divmod(i, num_routers)
- assert(cntrl_level < cntrls_per_router)
- ext_links.append(ExtLink(ext_node=n, int_node=router_id))
-
- #
- # Connect the remainding nodes to router 0. These should only be DMA nodes.
- #
- for (i, node) in enumerate(remainder_nodes):
- assert(node.type == 'DMA_Controller')
- assert(i < remainder)
- ext_links.append(ExtLink(ext_node=node, int_node=0))
-
- #
- # Create the mesh links. First row (east-west) links then column
- # (north-south) links
- #
- int_links = []
- for row in xrange(num_rows):
- for col in xrange(num_columns):
- if (col + 1 < num_columns):
- east_id = col + (row * num_columns)
- west_id = (col + 1) + (row * num_columns)
- int_links.append(IntLink(node_a=east_id,
- node_b=west_id,
- weight=1))
- for col in xrange(num_columns):
- for row in xrange(num_rows):
- if (row + 1 < num_rows):
- north_id = col + (row * num_columns)
- south_id = col + ((row + 1) * num_columns)
- int_links.append(IntLink(node_a=north_id,
- node_b=south_id,
- weight=2))
-
- return Topology(ext_links=ext_links,
- int_links=int_links,
- num_int_nodes=num_routers)
-
class RubyNetwork(SimObject):
type = 'RubyNetwork'
cxx_class = 'Network'
--- /dev/null
+# Copyright (c) 2010 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Steve Reinhardt
+
+from m5.params import *
+from m5.objects import *
+
+def makeTopology(nodes, options):
+ ext_links = [ExtLink(ext_node=n, int_node=i)
+ for (i, n) in enumerate(nodes)]
+ xbar = len(nodes) # node ID for crossbar switch
+ int_links = [IntLink(node_a=i, node_b=xbar) for i in range(len(nodes))]
+ return Topology(ext_links=ext_links, int_links=int_links,
+ num_int_nodes=len(nodes)+1)
+
+
--- /dev/null
+# Copyright (c) 2010 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Brad Beckmann
+
+from m5.params import *
+from m5.objects import *
+
+#
+# Makes a generic mesh assuming an equal number of cache and directory cntrls
+#
+
+def makeTopology(nodes, options):
+
+ num_routers = options.num_cpus
+ num_rows = options.mesh_rows
+
+ #
+ # There must be an evenly divisible number of cntrls to routers
+ # Also, obviously the number or rows must be <= the number of routers
+ #
+ cntrls_per_router, remainder = divmod(len(nodes), num_routers)
+ assert(num_rows <= num_routers)
+ num_columns = int(num_routers / num_rows)
+ assert(num_columns * num_rows == num_routers)
+
+ #
+ # Add all but the remainder nodes to the list of nodes to be uniformly
+ # distributed across the network.
+ #
+ network_nodes = []
+ remainder_nodes = []
+ for node_index in xrange(len(nodes)):
+ if node_index < (len(nodes) - remainder):
+ network_nodes.append(nodes[node_index])
+ else:
+ remainder_nodes.append(nodes[node_index])
+
+ #
+ # Connect each node to the appropriate router
+ #
+ ext_links = []
+ for (i, n) in enumerate(network_nodes):
+ cntrl_level, router_id = divmod(i, num_routers)
+ assert(cntrl_level < cntrls_per_router)
+ ext_links.append(ExtLink(ext_node=n, int_node=router_id))
+
+ #
+ # Connect the remainding nodes to router 0. These should only be DMA nodes.
+ #
+ for (i, node) in enumerate(remainder_nodes):
+ assert(node.type == 'DMA_Controller')
+ assert(i < remainder)
+ ext_links.append(ExtLink(ext_node=node, int_node=0))
+
+ #
+ # Create the mesh links. First row (east-west) links then column
+ # (north-south) links
+ #
+ int_links = []
+ for row in xrange(num_rows):
+ for col in xrange(num_columns):
+ if (col + 1 < num_columns):
+ east_id = col + (row * num_columns)
+ west_id = (col + 1) + (row * num_columns)
+ int_links.append(IntLink(node_a=east_id,
+ node_b=west_id,
+ weight=1))
+ for col in xrange(num_columns):
+ for row in xrange(num_rows):
+ if (row + 1 < num_rows):
+ north_id = col + (row * num_columns)
+ south_id = col + ((row + 1) * num_columns)
+ int_links.append(IntLink(node_a=north_id,
+ node_b=south_id,
+ weight=2))
+
+ return Topology(ext_links=ext_links,
+ int_links=int_links,
+ num_int_nodes=num_routers)
--- /dev/null
+# Copyright (c) 2010 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Brad Beckmann
+
+from m5.params import *
+from m5.objects import *
+
+#
+# This file contains a special network creation function. This networks is not
+# general and will only work with specific system configurations. The network
+# specified is similar to GEMS old file specified network.
+#
+
+def makeTopology(nodes, options):
+
+ num_routers = options.num_cpus
+ num_rows = options.mesh_rows
+
+ #
+ # First determine which nodes are cache cntrls vs. dirs vs. dma
+ #
+ cache_nodes = []
+ dir_nodes = []
+ dma_nodes = []
+ for node in nodes:
+ if node.type == 'L1Cache_Controller' or \
+ node.type == 'L2Cache_Controller':
+ cache_nodes.append(node)
+ elif node.type == 'Directory_Controller':
+ dir_nodes.append(node)
+ elif node.type == 'DMA_Controller':
+ dma_nodes.append(node)
+
+ #
+ # Obviously the number or rows must be <= the number of routers and evenly
+ # divisible. Also the number of caches must be a multiple of the number of
+ # routers and the number of directories must be four.
+ #
+ assert(num_rows <= num_routers)
+ num_columns = int(num_routers / num_rows)
+ assert(num_columns * num_rows == num_routers)
+ caches_per_router, remainder = divmod(len(cache_nodes), num_routers)
+ assert(remainder == 0)
+ assert(len(dir_nodes) == 4)
+
+ #
+ # Connect each cache controller to the appropriate router
+ #
+ ext_links = []
+ for (i, n) in enumerate(cache_nodes):
+ cntrl_level, router_id = divmod(i, num_routers)
+ assert(cntrl_level < caches_per_router)
+ ext_links.append(ExtLink(ext_node=n, int_node=router_id))
+
+ #
+ # Connect the dir nodes to the corners.
+ #
+ ext_links.append(ExtLink(ext_node=dir_nodes[0], int_node=0))
+ ext_links.append(ExtLink(ext_node=dir_nodes[1], int_node=(num_columns - 1)))
+
+ ext_links.append(ExtLink(ext_node=dir_nodes[2],
+ int_node=(num_routers - num_columns)))
+
+ ext_links.append(ExtLink(ext_node=dir_nodes[3], int_node=(num_routers - 1)))
+
+ #
+ # Connect the dma nodes to router 0. These should only be DMA nodes.
+ #
+ for (i, node) in enumerate(dma_nodes):
+ assert(node.type == 'DMA_Controller')
+ ext_links.append(ExtLink(ext_node=node, int_node=0))
+
+ #
+ # Create the mesh links. First row (east-west) links then column
+ # (north-south) links
+ #
+ int_links = []
+ for row in xrange(num_rows):
+ for col in xrange(num_columns):
+ if (col + 1 < num_columns):
+ east_id = col + (row * num_columns)
+ west_id = (col + 1) + (row * num_columns)
+ int_links.append(IntLink(node_a=east_id,
+ node_b=west_id,
+ weight=1))
+ for col in xrange(num_columns):
+ for row in xrange(num_rows):
+ if (row + 1 < num_rows):
+ north_id = col + (row * num_columns)
+ south_id = col + ((row + 1) * num_columns)
+ int_links.append(IntLink(node_a=north_id,
+ node_b=south_id,
+ weight=2))
+
+ return Topology(ext_links=ext_links,
+ int_links=int_links,
+ num_int_nodes=num_routers)
+
--- /dev/null
+# Copyright (c) 2010 Advanced Micro Devices, Inc.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Brad Beckmann
+
+Import('*')
+
+if not env['RUBY']:
+ Return()
+
+PySource('', 'Crossbar.py')
+PySource('', 'Mesh.py')
+PySource('', 'MeshDirCorners.py')
+
projects / gem5.git / commitdiff