* mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for

	the two drem and the two dremu macros.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 6f55be2083adfe95af5427262209286ca48cadc4..26356c4910153a32b3968cc442fac9374fa3c04a 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2008-04-29  Adam Nemet  <anemet@caviumnetworks.com>
+
+       * mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for
+       the two drem and the two dremu macros.
+
 2008-04-28  Adam Nemet  <anemet@caviumnetworks.com>
 
        * mips-opc.c (mips_builtin_opcodes): Mark prefx and c1

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 63bec4f3dff95475111440c800024f544fc74796..1787c9e3571e8844c8ffa263b666f3e590635c92 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -630,11 +630,11 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dneg",    "d,w",     0x0000002e, 0xffe007ff, WR_d|RD_t,              0,              I3      }, /* dsub 0 */
 {"dnegu",   "d,w",     0x0000002f, 0xffe007ff, WR_d|RD_t,              0,              I3      }, /* dsubu 0*/
 {"drem",    "z,s,t",    0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,             I3      },
-{"drem",    "d,v,t",   3,    (int) M_DREM_3,   INSN_MACRO,             0,              I3      },
-{"drem",    "d,v,I",   3,    (int) M_DREM_3I,  INSN_MACRO,             0,              I3      },
+{"drem",    "d,v,t",   0,    (int) M_DREM_3,   INSN_MACRO,             0,              I3      },
+{"drem",    "d,v,I",   0,    (int) M_DREM_3I,  INSN_MACRO,             0,              I3      },
 {"dremu",   "z,s,t",    0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO,      0,             I3      },
-{"dremu",   "d,v,t",   3,    (int) M_DREMU_3,  INSN_MACRO,             0,              I3      },
-{"dremu",   "d,v,I",   3,    (int) M_DREMU_3I, INSN_MACRO,             0,              I3      },
+{"dremu",   "d,v,t",   0,    (int) M_DREMU_3,  INSN_MACRO,             0,              I3      },
+{"dremu",   "d,v,I",   0,    (int) M_DREMU_3I, INSN_MACRO,             0,              I3      },
 {"dret",    "",                0x7000003e, 0xffffffff, 0,                      0,              N5      },
 {"drol",    "d,v,t",   0,    (int) M_DROL,     INSN_MACRO,             0,              I3      },
 {"drol",    "d,v,I",   0,    (int) M_DROL_I,   INSN_MACRO,             0,              I3      },