ARM: Allow access to the RGNR register.

diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index bce76196281d360c9cf024e35e0e555d05336c3b..914ca6242b876d4d792ee20d412b93c4d845000e 100644 (file)
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -104,6 +104,7 @@ namespace ArmISA
         MISCREG_BPIALL,
         MISCREG_MPUIR,
         MISCREG_MIDR,
+        MISCREG_RGNR,
         MISCREG_CP15_UNIMP_START,
         MISCREG_CTR = MISCREG_CP15_UNIMP_START,
         MISCREG_TCMTR,
@@ -136,7 +137,6 @@ namespace ArmISA
         MISCREG_IRSR,
         MISCREG_DRACR,
         MISCREG_IRACR,
-        MISCREG_RGNR,
         MISCREG_DCIMVAC,
         MISCREG_DCISW,
         MISCREG_MCCSW,
@@ -164,14 +164,13 @@ namespace ArmISA
         "clidr", "ccsidr", "csselr",
         "icialluis", "iciallu", "icimvau",
         "bpimva", "bpiallis", "bpiall",
-        "mpuir", "midr", "ctr", "tcmtr", "mpidr",
+        "mpuir", "midr", "rgnr", "ctr", "tcmtr", "mpidr",
         "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
         "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
         "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
         "aidr", "actlr",
         "dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar",
         "drbar", "irbar", "drsr", "irsr", "dracr", "iracr",
-        "rgnr",
         "dcimvac", "dcisw", "mccsw",
         "dccmvau",
         "nop", "raz"