Make R/W tests more intense

diff --git a/gram/simulation/mem_init.txt b/gram/simulation/mem_init.txt
index 23f716eeb5947c7b60a5a862d24d9ad55eeb739d..5762aef1e05097dba4bd9f1eb69f1ffafa53409d 100644 (file)
--- a/gram/simulation/mem_init.txt
+++ b/gram/simulation/mem_init.txt
@@ -1 +1,4 @@
-0 test 12345678FAAFFEEF0A0A0A0AFACECA8C
+0 row0_0 12345678FAAFFEEF0A0A0A0AFACECA8C
+8 row0_8 00000000111111112222222233333333
+10 row0_10 F00DF00D0102030455556666A0A0A0A0
+18 row0_18 C0CAC0CA000CACA0000C0C0AAAAAAAAA

diff --git a/gram/simulation/simsoctb.v b/gram/simulation/simsoctb.v
index af1d349311a16b40319a534f93931ead543531e2..538d3357ba1b8b45fc367ef30fb2af73ce2aba67 100644 (file)
--- a/gram/simulation/simsoctb.v
+++ b/gram/simulation/simsoctb.v
@@ -197,6 +197,7 @@ module simsoctb;
       wishbone_write(32'h00009000 >> 2, 8'h01); // DFII_CONTROL_SEL
       #2000;
 
+      // Read test on provisioned data, row 0, col 0-7
       wishbone_read(32'h10000000 >> 2, tmp);
       assert_equal_32(tmp, 32'hFACECA8C);
       wishbone_read(32'h10000004 >> 2, tmp);
@@ -206,12 +207,49 @@ module simsoctb;
       wishbone_read(32'h1000000C >> 2, tmp);
       assert_equal_32(tmp, 32'h12345678);
 
+      // Read test on provisioned data, row 0, col 8-15
+      wishbone_read(32'h10000010 >> 2, tmp);
+      assert_equal_32(tmp, 32'h33333333);
+      wishbone_read(32'h10000014 >> 2, tmp);
+      assert_equal_32(tmp, 32'h22222222);
+      wishbone_read(32'h10000018 >> 2, tmp);
+      assert_equal_32(tmp, 32'h11111111);
+      wishbone_read(32'h1000001C >> 2, tmp);
+      assert_equal_32(tmp, 32'h00000000);
+
+      // Read test on provisioned data, row 0, col 16-23
+      wishbone_read(32'h10000020 >> 2, tmp);
+      assert_equal_32(tmp, 32'hA0A0A0A0);
+      wishbone_read(32'h10000024 >> 2, tmp);
+      assert_equal_32(tmp, 32'h55556666);
+      wishbone_read(32'h10000028 >> 2, tmp);
+      assert_equal_32(tmp, 32'h01020304);
+      wishbone_read(32'h1000002C >> 2, tmp);
+      assert_equal_32(tmp, 32'hF00DF00D);
+
+      // Read test on provisioned data, row 0, col 24-31
+      wishbone_read(32'h10000030 >> 2, tmp);
+      assert_equal_32(tmp, 32'hAAAAAAAA);
+      wishbone_read(32'h10000034 >> 2, tmp);
+      assert_equal_32(tmp, 32'h000C0C0A);
+      wishbone_read(32'h10000038 >> 2, tmp);
+      assert_equal_32(tmp, 32'h000CACA0);
+      wishbone_read(32'h1000003C >> 2, tmp);
+      assert_equal_32(tmp, 32'hC0CAC0CA);
+
       // Write
       wishbone_write(32'h1000000C >> 2, 32'h00BA0BAB);
       wishbone_write(32'h10000008 >> 2, 32'h13374242);
       wishbone_write(32'h10000004 >> 2, 32'hC0DEC0DE);
       wishbone_write(32'h10000000 >> 2, 32'h01020304);
+
       wishbone_read(32'h10000000 >> 2, tmp);
+      assert_equal_32(tmp, 32'h01020304);
+      wishbone_read(32'h10000004 >> 2, tmp);
+      assert_equal_32(tmp, 32'hC0DEC0DE);
+      wishbone_read(32'h10000008 >> 2, tmp);
+      assert_equal_32(tmp, 32'h13374242);
+      wishbone_read(32'h1000000C >> 2, tmp);
       assert_equal_32(tmp, 32'h00BA0BAB);
 
       $finish;