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//
// Filename : litedram_core.v
// Device :
-// LiteX sha1 : 6932fc51
-// Date : 2022-08-04 21:07:00
+// LiteX sha1 : --------
+// Date : 2022-10-28 19:01:23
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
module litedram_core (
- input wire clk,
- input wire rst,
- output wire pll_locked,
- output wire [15:0] ddram_a,
- output wire [2:0] ddram_ba,
- output wire ddram_ras_n,
- output wire ddram_cas_n,
- output wire ddram_we_n,
- output wire ddram_cs_n,
- output wire [1:0] ddram_dm,
- inout wire [15:0] ddram_dq,
- inout wire [1:0] ddram_dqs_p,
- inout wire [1:0] ddram_dqs_n,
- output wire ddram_clk_p,
- output wire ddram_clk_n,
- output wire ddram_cke,
- output wire ddram_odt,
- output wire ddram_reset_n,
- output wire init_done,
- output wire init_error,
- input wire [29:0] wb_ctrl_adr,
- input wire [31:0] wb_ctrl_dat_w,
- output wire [31:0] wb_ctrl_dat_r,
- input wire [3:0] wb_ctrl_sel,
- input wire wb_ctrl_cyc,
- input wire wb_ctrl_stb,
- output wire wb_ctrl_ack,
- input wire wb_ctrl_we,
- input wire [2:0] wb_ctrl_cti,
- input wire [1:0] wb_ctrl_bte,
- output wire wb_ctrl_err,
- output wire user_clk,
- output wire user_rst,
- input wire user_port_native_0_cmd_valid,
- output wire user_port_native_0_cmd_ready,
- input wire user_port_native_0_cmd_we,
- input wire [25:0] user_port_native_0_cmd_addr,
- input wire user_port_native_0_wdata_valid,
- output wire user_port_native_0_wdata_ready,
- input wire [15:0] user_port_native_0_wdata_we,
- input wire [127:0] user_port_native_0_wdata_data,
- output wire user_port_native_0_rdata_valid,
- input wire user_port_native_0_rdata_ready,
- output wire [127:0] user_port_native_0_rdata_data
+ input wire clk,
+ input wire rst,
+ output wire pll_locked,
+ output wire [15:0] ddram_a,
+ output wire [2:0] ddram_ba,
+ output wire ddram_ras_n,
+ output wire ddram_cas_n,
+ output wire ddram_we_n,
+ output wire ddram_cs_n,
+ output wire [1:0] ddram_dm,
+ inout wire [15:0] ddram_dq,
+ inout wire [1:0] ddram_dqs_p,
+ inout wire [1:0] ddram_dqs_n,
+ output wire ddram_clk_p,
+ output wire ddram_clk_n,
+ output wire ddram_cke,
+ output wire ddram_odt,
+ output wire ddram_reset_n,
+ output wire init_done,
+ output wire init_error,
+ input wire [29:0] wb_ctrl_adr,
+ input wire [31:0] wb_ctrl_dat_w,
+ output wire [31:0] wb_ctrl_dat_r,
+ input wire [3:0] wb_ctrl_sel,
+ input wire wb_ctrl_cyc,
+ input wire wb_ctrl_stb,
+ output wire wb_ctrl_ack,
+ input wire wb_ctrl_we,
+ input wire [2:0] wb_ctrl_cti,
+ input wire [1:0] wb_ctrl_bte,
+ output wire wb_ctrl_err,
+ output wire user_clk,
+ output wire user_rst,
+ input wire user_port_native_0_cmd_valid,
+ output wire user_port_native_0_cmd_ready,
+ input wire user_port_native_0_cmd_we,
+ input wire [25:0] user_port_native_0_cmd_addr,
+ input wire user_port_native_0_wdata_valid,
+ output wire user_port_native_0_wdata_ready,
+ input wire [15:0] user_port_native_0_wdata_we,
+ input wire [127:0] user_port_native_0_wdata_data,
+ output wire user_port_native_0_rdata_valid,
+ input wire user_port_native_0_rdata_ready,
+ output wire [127:0] user_port_native_0_rdata_data
);
// Signals
//------------------------------------------------------------------------------
-reg rst_1 = 1'd0;
-wire sys_clk;
-wire sys_rst;
-wire sys4x_clk;
-wire sys4x_dqs_clk;
-wire iodelay_clk;
-wire iodelay_rst;
-wire reset;
-reg power_down = 1'd0;
-wire locked;
-wire clkin;
-wire clkout0;
-wire clkout_buf0;
-wire clkout1;
-wire clkout_buf1;
-wire clkout2;
-wire clkout_buf2;
-wire clkout3;
-wire clkout_buf3;
-reg [3:0] reset_counter = 4'd15;
-reg ic_reset = 1'd1;
-reg a7ddrphy_rst_storage = 1'd0;
-reg a7ddrphy_rst_re = 1'd0;
-reg [1:0] a7ddrphy_dly_sel_storage = 2'd0;
-reg a7ddrphy_dly_sel_re = 1'd0;
-reg [4:0] a7ddrphy_half_sys8x_taps_storage = 5'd8;
-reg a7ddrphy_half_sys8x_taps_re = 1'd0;
-reg a7ddrphy_wlevel_en_storage = 1'd0;
-reg a7ddrphy_wlevel_en_re = 1'd0;
-reg a7ddrphy_wlevel_strobe_re = 1'd0;
-wire a7ddrphy_wlevel_strobe_r;
-reg a7ddrphy_wlevel_strobe_we = 1'd0;
-reg a7ddrphy_wlevel_strobe_w = 1'd0;
-reg a7ddrphy_rdly_dq_rst_re = 1'd0;
-wire a7ddrphy_rdly_dq_rst_r;
-reg a7ddrphy_rdly_dq_rst_we = 1'd0;
-reg a7ddrphy_rdly_dq_rst_w = 1'd0;
-reg a7ddrphy_rdly_dq_inc_re = 1'd0;
-wire a7ddrphy_rdly_dq_inc_r;
-reg a7ddrphy_rdly_dq_inc_we = 1'd0;
-reg a7ddrphy_rdly_dq_inc_w = 1'd0;
-reg a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
-wire a7ddrphy_rdly_dq_bitslip_rst_r;
-reg a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
-reg a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
-reg a7ddrphy_rdly_dq_bitslip_re = 1'd0;
-wire a7ddrphy_rdly_dq_bitslip_r;
-reg a7ddrphy_rdly_dq_bitslip_we = 1'd0;
-reg a7ddrphy_rdly_dq_bitslip_w = 1'd0;
-reg a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0;
-wire a7ddrphy_wdly_dq_bitslip_rst_r;
-reg a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0;
-reg a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0;
-reg a7ddrphy_wdly_dq_bitslip_re = 1'd0;
-wire a7ddrphy_wdly_dq_bitslip_r;
-reg a7ddrphy_wdly_dq_bitslip_we = 1'd0;
-reg a7ddrphy_wdly_dq_bitslip_w = 1'd0;
-reg [1:0] a7ddrphy_rdphase_storage = 2'd2;
-reg a7ddrphy_rdphase_re = 1'd0;
-reg [1:0] a7ddrphy_wrphase_storage = 2'd3;
-reg a7ddrphy_wrphase_re = 1'd0;
-wire [15:0] a7ddrphy_dfi_p0_address;
-wire [2:0] a7ddrphy_dfi_p0_bank;
-wire a7ddrphy_dfi_p0_cas_n;
-wire a7ddrphy_dfi_p0_cs_n;
-wire a7ddrphy_dfi_p0_ras_n;
-wire a7ddrphy_dfi_p0_we_n;
-wire a7ddrphy_dfi_p0_cke;
-wire a7ddrphy_dfi_p0_odt;
-wire a7ddrphy_dfi_p0_reset_n;
-wire a7ddrphy_dfi_p0_act_n;
-wire [31:0] a7ddrphy_dfi_p0_wrdata;
-wire a7ddrphy_dfi_p0_wrdata_en;
-wire [3:0] a7ddrphy_dfi_p0_wrdata_mask;
-wire a7ddrphy_dfi_p0_rddata_en;
-reg [31:0] a7ddrphy_dfi_p0_rddata = 32'd0;
-wire a7ddrphy_dfi_p0_rddata_valid;
-wire [15:0] a7ddrphy_dfi_p1_address;
-wire [2:0] a7ddrphy_dfi_p1_bank;
-wire a7ddrphy_dfi_p1_cas_n;
-wire a7ddrphy_dfi_p1_cs_n;
-wire a7ddrphy_dfi_p1_ras_n;
-wire a7ddrphy_dfi_p1_we_n;
-wire a7ddrphy_dfi_p1_cke;
-wire a7ddrphy_dfi_p1_odt;
-wire a7ddrphy_dfi_p1_reset_n;
-wire a7ddrphy_dfi_p1_act_n;
-wire [31:0] a7ddrphy_dfi_p1_wrdata;
-wire a7ddrphy_dfi_p1_wrdata_en;
-wire [3:0] a7ddrphy_dfi_p1_wrdata_mask;
-wire a7ddrphy_dfi_p1_rddata_en;
-reg [31:0] a7ddrphy_dfi_p1_rddata = 32'd0;
-wire a7ddrphy_dfi_p1_rddata_valid;
-wire [15:0] a7ddrphy_dfi_p2_address;
-wire [2:0] a7ddrphy_dfi_p2_bank;
-wire a7ddrphy_dfi_p2_cas_n;
-wire a7ddrphy_dfi_p2_cs_n;
-wire a7ddrphy_dfi_p2_ras_n;
-wire a7ddrphy_dfi_p2_we_n;
-wire a7ddrphy_dfi_p2_cke;
-wire a7ddrphy_dfi_p2_odt;
-wire a7ddrphy_dfi_p2_reset_n;
-wire a7ddrphy_dfi_p2_act_n;
-wire [31:0] a7ddrphy_dfi_p2_wrdata;
-wire a7ddrphy_dfi_p2_wrdata_en;
-wire [3:0] a7ddrphy_dfi_p2_wrdata_mask;
-wire a7ddrphy_dfi_p2_rddata_en;
-reg [31:0] a7ddrphy_dfi_p2_rddata = 32'd0;
-wire a7ddrphy_dfi_p2_rddata_valid;
-wire [15:0] a7ddrphy_dfi_p3_address;
-wire [2:0] a7ddrphy_dfi_p3_bank;
-wire a7ddrphy_dfi_p3_cas_n;
-wire a7ddrphy_dfi_p3_cs_n;
-wire a7ddrphy_dfi_p3_ras_n;
-wire a7ddrphy_dfi_p3_we_n;
-wire a7ddrphy_dfi_p3_cke;
-wire a7ddrphy_dfi_p3_odt;
-wire a7ddrphy_dfi_p3_reset_n;
-wire a7ddrphy_dfi_p3_act_n;
-wire [31:0] a7ddrphy_dfi_p3_wrdata;
-wire a7ddrphy_dfi_p3_wrdata_en;
-wire [3:0] a7ddrphy_dfi_p3_wrdata_mask;
-wire a7ddrphy_dfi_p3_rddata_en;
-reg [31:0] a7ddrphy_dfi_p3_rddata = 32'd0;
-wire a7ddrphy_dfi_p3_rddata_valid;
-wire a7ddrphy_sd_clk_se_nodelay;
-wire [2:0] a7ddrphy_pads_ba;
-reg a7ddrphy_dqs_oe = 1'd0;
-wire a7ddrphy_dqs_preamble;
-wire a7ddrphy_dqs_postamble;
-wire a7ddrphy_dqs_oe_delay_tappeddelayline;
-reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
-reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
-reg a7ddrphy_dqspattern0 = 1'd0;
-reg a7ddrphy_dqspattern1 = 1'd0;
-reg [7:0] a7ddrphy_dqspattern_o0 = 8'd0;
-reg [7:0] a7ddrphy_dqspattern_o1 = 8'd0;
-wire a7ddrphy_dqs_o_no_delay0;
-wire a7ddrphy_dqs_t0;
-reg [7:0] a7ddrphy_bitslip00 = 8'd0;
-reg [2:0] a7ddrphy_bitslip0_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip0_r0 = 16'd0;
-wire a7ddrphy0;
-wire a7ddrphy_dqs_o_no_delay1;
-wire a7ddrphy_dqs_t1;
-reg [7:0] a7ddrphy_bitslip10 = 8'd0;
-reg [2:0] a7ddrphy_bitslip1_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip1_r0 = 16'd0;
-wire a7ddrphy1;
-reg [7:0] a7ddrphy_bitslip01 = 8'd0;
-reg [2:0] a7ddrphy_bitslip0_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip0_r1 = 16'd0;
-reg [7:0] a7ddrphy_bitslip11 = 8'd0;
-reg [2:0] a7ddrphy_bitslip1_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip1_r1 = 16'd0;
-wire a7ddrphy_dq_oe;
-wire a7ddrphy_dq_oe_delay_tappeddelayline;
-reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
-reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
-wire a7ddrphy_dq_o_nodelay0;
-wire a7ddrphy_dq_i_nodelay0;
-wire a7ddrphy_dq_i_delayed0;
-wire a7ddrphy_dq_t0;
-reg [7:0] a7ddrphy_bitslip02 = 8'd0;
-reg [2:0] a7ddrphy_bitslip0_value2 = 3'd7;
-reg [15:0] a7ddrphy_bitslip0_r2 = 16'd0;
-wire [7:0] a7ddrphy_bitslip03;
-reg [7:0] a7ddrphy_bitslip04 = 8'd0;
-reg [2:0] a7ddrphy_bitslip0_value3 = 3'd7;
-reg [15:0] a7ddrphy_bitslip0_r3 = 16'd0;
-wire a7ddrphy_dq_o_nodelay1;
-wire a7ddrphy_dq_i_nodelay1;
-wire a7ddrphy_dq_i_delayed1;
-wire a7ddrphy_dq_t1;
-reg [7:0] a7ddrphy_bitslip12 = 8'd0;
-reg [2:0] a7ddrphy_bitslip1_value2 = 3'd7;
-reg [15:0] a7ddrphy_bitslip1_r2 = 16'd0;
-wire [7:0] a7ddrphy_bitslip13;
-reg [7:0] a7ddrphy_bitslip14 = 8'd0;
-reg [2:0] a7ddrphy_bitslip1_value3 = 3'd7;
-reg [15:0] a7ddrphy_bitslip1_r3 = 16'd0;
-wire a7ddrphy_dq_o_nodelay2;
-wire a7ddrphy_dq_i_nodelay2;
-wire a7ddrphy_dq_i_delayed2;
-wire a7ddrphy_dq_t2;
-reg [7:0] a7ddrphy_bitslip20 = 8'd0;
-reg [2:0] a7ddrphy_bitslip2_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip2_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip21;
-reg [7:0] a7ddrphy_bitslip22 = 8'd0;
-reg [2:0] a7ddrphy_bitslip2_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip2_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay3;
-wire a7ddrphy_dq_i_nodelay3;
-wire a7ddrphy_dq_i_delayed3;
-wire a7ddrphy_dq_t3;
-reg [7:0] a7ddrphy_bitslip30 = 8'd0;
-reg [2:0] a7ddrphy_bitslip3_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip3_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip31;
-reg [7:0] a7ddrphy_bitslip32 = 8'd0;
-reg [2:0] a7ddrphy_bitslip3_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip3_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay4;
-wire a7ddrphy_dq_i_nodelay4;
-wire a7ddrphy_dq_i_delayed4;
-wire a7ddrphy_dq_t4;
-reg [7:0] a7ddrphy_bitslip40 = 8'd0;
-reg [2:0] a7ddrphy_bitslip4_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip4_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip41;
-reg [7:0] a7ddrphy_bitslip42 = 8'd0;
-reg [2:0] a7ddrphy_bitslip4_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip4_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay5;
-wire a7ddrphy_dq_i_nodelay5;
-wire a7ddrphy_dq_i_delayed5;
-wire a7ddrphy_dq_t5;
-reg [7:0] a7ddrphy_bitslip50 = 8'd0;
-reg [2:0] a7ddrphy_bitslip5_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip5_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip51;
-reg [7:0] a7ddrphy_bitslip52 = 8'd0;
-reg [2:0] a7ddrphy_bitslip5_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip5_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay6;
-wire a7ddrphy_dq_i_nodelay6;
-wire a7ddrphy_dq_i_delayed6;
-wire a7ddrphy_dq_t6;
-reg [7:0] a7ddrphy_bitslip60 = 8'd0;
-reg [2:0] a7ddrphy_bitslip6_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip6_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip61;
-reg [7:0] a7ddrphy_bitslip62 = 8'd0;
-reg [2:0] a7ddrphy_bitslip6_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip6_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay7;
-wire a7ddrphy_dq_i_nodelay7;
-wire a7ddrphy_dq_i_delayed7;
-wire a7ddrphy_dq_t7;
-reg [7:0] a7ddrphy_bitslip70 = 8'd0;
-reg [2:0] a7ddrphy_bitslip7_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip7_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip71;
-reg [7:0] a7ddrphy_bitslip72 = 8'd0;
-reg [2:0] a7ddrphy_bitslip7_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip7_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay8;
-wire a7ddrphy_dq_i_nodelay8;
-wire a7ddrphy_dq_i_delayed8;
-wire a7ddrphy_dq_t8;
-reg [7:0] a7ddrphy_bitslip80 = 8'd0;
-reg [2:0] a7ddrphy_bitslip8_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip8_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip81;
-reg [7:0] a7ddrphy_bitslip82 = 8'd0;
-reg [2:0] a7ddrphy_bitslip8_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip8_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay9;
-wire a7ddrphy_dq_i_nodelay9;
-wire a7ddrphy_dq_i_delayed9;
-wire a7ddrphy_dq_t9;
-reg [7:0] a7ddrphy_bitslip90 = 8'd0;
-reg [2:0] a7ddrphy_bitslip9_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip9_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip91;
-reg [7:0] a7ddrphy_bitslip92 = 8'd0;
-reg [2:0] a7ddrphy_bitslip9_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip9_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay10;
-wire a7ddrphy_dq_i_nodelay10;
-wire a7ddrphy_dq_i_delayed10;
-wire a7ddrphy_dq_t10;
-reg [7:0] a7ddrphy_bitslip100 = 8'd0;
-reg [2:0] a7ddrphy_bitslip10_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip10_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip101;
-reg [7:0] a7ddrphy_bitslip102 = 8'd0;
-reg [2:0] a7ddrphy_bitslip10_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip10_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay11;
-wire a7ddrphy_dq_i_nodelay11;
-wire a7ddrphy_dq_i_delayed11;
-wire a7ddrphy_dq_t11;
-reg [7:0] a7ddrphy_bitslip110 = 8'd0;
-reg [2:0] a7ddrphy_bitslip11_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip11_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip111;
-reg [7:0] a7ddrphy_bitslip112 = 8'd0;
-reg [2:0] a7ddrphy_bitslip11_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip11_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay12;
-wire a7ddrphy_dq_i_nodelay12;
-wire a7ddrphy_dq_i_delayed12;
-wire a7ddrphy_dq_t12;
-reg [7:0] a7ddrphy_bitslip120 = 8'd0;
-reg [2:0] a7ddrphy_bitslip12_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip12_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip121;
-reg [7:0] a7ddrphy_bitslip122 = 8'd0;
-reg [2:0] a7ddrphy_bitslip12_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip12_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay13;
-wire a7ddrphy_dq_i_nodelay13;
-wire a7ddrphy_dq_i_delayed13;
-wire a7ddrphy_dq_t13;
-reg [7:0] a7ddrphy_bitslip130 = 8'd0;
-reg [2:0] a7ddrphy_bitslip13_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip13_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip131;
-reg [7:0] a7ddrphy_bitslip132 = 8'd0;
-reg [2:0] a7ddrphy_bitslip13_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip13_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay14;
-wire a7ddrphy_dq_i_nodelay14;
-wire a7ddrphy_dq_i_delayed14;
-wire a7ddrphy_dq_t14;
-reg [7:0] a7ddrphy_bitslip140 = 8'd0;
-reg [2:0] a7ddrphy_bitslip14_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip14_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip141;
-reg [7:0] a7ddrphy_bitslip142 = 8'd0;
-reg [2:0] a7ddrphy_bitslip14_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip14_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay15;
-wire a7ddrphy_dq_i_nodelay15;
-wire a7ddrphy_dq_i_delayed15;
-wire a7ddrphy_dq_t15;
-reg [7:0] a7ddrphy_bitslip150 = 8'd0;
-reg [2:0] a7ddrphy_bitslip15_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip15_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip151;
-reg [7:0] a7ddrphy_bitslip152 = 8'd0;
-reg [2:0] a7ddrphy_bitslip15_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip15_r1 = 16'd0;
-reg a7ddrphy_rddata_en_tappeddelayline0 = 1'd0;
-reg a7ddrphy_rddata_en_tappeddelayline1 = 1'd0;
-reg a7ddrphy_rddata_en_tappeddelayline2 = 1'd0;
-reg a7ddrphy_rddata_en_tappeddelayline3 = 1'd0;
-reg a7ddrphy_rddata_en_tappeddelayline4 = 1'd0;
-reg a7ddrphy_rddata_en_tappeddelayline5 = 1'd0;
-reg a7ddrphy_rddata_en_tappeddelayline6 = 1'd0;
-reg a7ddrphy_rddata_en_tappeddelayline7 = 1'd0;
-reg a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
-reg a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
-reg a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
-wire [15:0] litedramcore_slave_p0_address;
-wire [2:0] litedramcore_slave_p0_bank;
-wire litedramcore_slave_p0_cas_n;
-wire litedramcore_slave_p0_cs_n;
-wire litedramcore_slave_p0_ras_n;
-wire litedramcore_slave_p0_we_n;
-wire litedramcore_slave_p0_cke;
-wire litedramcore_slave_p0_odt;
-wire litedramcore_slave_p0_reset_n;
-wire litedramcore_slave_p0_act_n;
-wire [31:0] litedramcore_slave_p0_wrdata;
-wire litedramcore_slave_p0_wrdata_en;
-wire [3:0] litedramcore_slave_p0_wrdata_mask;
-wire litedramcore_slave_p0_rddata_en;
-reg [31:0] litedramcore_slave_p0_rddata = 32'd0;
-reg litedramcore_slave_p0_rddata_valid = 1'd0;
-wire [15:0] litedramcore_slave_p1_address;
-wire [2:0] litedramcore_slave_p1_bank;
-wire litedramcore_slave_p1_cas_n;
-wire litedramcore_slave_p1_cs_n;
-wire litedramcore_slave_p1_ras_n;
-wire litedramcore_slave_p1_we_n;
-wire litedramcore_slave_p1_cke;
-wire litedramcore_slave_p1_odt;
-wire litedramcore_slave_p1_reset_n;
-wire litedramcore_slave_p1_act_n;
-wire [31:0] litedramcore_slave_p1_wrdata;
-wire litedramcore_slave_p1_wrdata_en;
-wire [3:0] litedramcore_slave_p1_wrdata_mask;
-wire litedramcore_slave_p1_rddata_en;
-reg [31:0] litedramcore_slave_p1_rddata = 32'd0;
-reg litedramcore_slave_p1_rddata_valid = 1'd0;
-wire [15:0] litedramcore_slave_p2_address;
-wire [2:0] litedramcore_slave_p2_bank;
-wire litedramcore_slave_p2_cas_n;
-wire litedramcore_slave_p2_cs_n;
-wire litedramcore_slave_p2_ras_n;
-wire litedramcore_slave_p2_we_n;
-wire litedramcore_slave_p2_cke;
-wire litedramcore_slave_p2_odt;
-wire litedramcore_slave_p2_reset_n;
-wire litedramcore_slave_p2_act_n;
-wire [31:0] litedramcore_slave_p2_wrdata;
-wire litedramcore_slave_p2_wrdata_en;
-wire [3:0] litedramcore_slave_p2_wrdata_mask;
-wire litedramcore_slave_p2_rddata_en;
-reg [31:0] litedramcore_slave_p2_rddata = 32'd0;
-reg litedramcore_slave_p2_rddata_valid = 1'd0;
-wire [15:0] litedramcore_slave_p3_address;
-wire [2:0] litedramcore_slave_p3_bank;
-wire litedramcore_slave_p3_cas_n;
-wire litedramcore_slave_p3_cs_n;
-wire litedramcore_slave_p3_ras_n;
-wire litedramcore_slave_p3_we_n;
-wire litedramcore_slave_p3_cke;
-wire litedramcore_slave_p3_odt;
-wire litedramcore_slave_p3_reset_n;
-wire litedramcore_slave_p3_act_n;
-wire [31:0] litedramcore_slave_p3_wrdata;
-wire litedramcore_slave_p3_wrdata_en;
-wire [3:0] litedramcore_slave_p3_wrdata_mask;
-wire litedramcore_slave_p3_rddata_en;
-reg [31:0] litedramcore_slave_p3_rddata = 32'd0;
-reg litedramcore_slave_p3_rddata_valid = 1'd0;
-reg [15:0] litedramcore_master_p0_address = 16'd0;
-reg [2:0] litedramcore_master_p0_bank = 3'd0;
-reg litedramcore_master_p0_cas_n = 1'd1;
-reg litedramcore_master_p0_cs_n = 1'd1;
-reg litedramcore_master_p0_ras_n = 1'd1;
-reg litedramcore_master_p0_we_n = 1'd1;
-reg litedramcore_master_p0_cke = 1'd0;
-reg litedramcore_master_p0_odt = 1'd0;
-reg litedramcore_master_p0_reset_n = 1'd0;
-reg litedramcore_master_p0_act_n = 1'd1;
-reg [31:0] litedramcore_master_p0_wrdata = 32'd0;
-reg litedramcore_master_p0_wrdata_en = 1'd0;
-reg [3:0] litedramcore_master_p0_wrdata_mask = 4'd0;
-reg litedramcore_master_p0_rddata_en = 1'd0;
-wire [31:0] litedramcore_master_p0_rddata;
-wire litedramcore_master_p0_rddata_valid;
-reg [15:0] litedramcore_master_p1_address = 16'd0;
-reg [2:0] litedramcore_master_p1_bank = 3'd0;
-reg litedramcore_master_p1_cas_n = 1'd1;
-reg litedramcore_master_p1_cs_n = 1'd1;
-reg litedramcore_master_p1_ras_n = 1'd1;
-reg litedramcore_master_p1_we_n = 1'd1;
-reg litedramcore_master_p1_cke = 1'd0;
-reg litedramcore_master_p1_odt = 1'd0;
-reg litedramcore_master_p1_reset_n = 1'd0;
-reg litedramcore_master_p1_act_n = 1'd1;
-reg [31:0] litedramcore_master_p1_wrdata = 32'd0;
-reg litedramcore_master_p1_wrdata_en = 1'd0;
-reg [3:0] litedramcore_master_p1_wrdata_mask = 4'd0;
-reg litedramcore_master_p1_rddata_en = 1'd0;
-wire [31:0] litedramcore_master_p1_rddata;
-wire litedramcore_master_p1_rddata_valid;
-reg [15:0] litedramcore_master_p2_address = 16'd0;
-reg [2:0] litedramcore_master_p2_bank = 3'd0;
-reg litedramcore_master_p2_cas_n = 1'd1;
-reg litedramcore_master_p2_cs_n = 1'd1;
-reg litedramcore_master_p2_ras_n = 1'd1;
-reg litedramcore_master_p2_we_n = 1'd1;
-reg litedramcore_master_p2_cke = 1'd0;
-reg litedramcore_master_p2_odt = 1'd0;
-reg litedramcore_master_p2_reset_n = 1'd0;
-reg litedramcore_master_p2_act_n = 1'd1;
-reg [31:0] litedramcore_master_p2_wrdata = 32'd0;
-reg litedramcore_master_p2_wrdata_en = 1'd0;
-reg [3:0] litedramcore_master_p2_wrdata_mask = 4'd0;
-reg litedramcore_master_p2_rddata_en = 1'd0;
-wire [31:0] litedramcore_master_p2_rddata;
-wire litedramcore_master_p2_rddata_valid;
-reg [15:0] litedramcore_master_p3_address = 16'd0;
-reg [2:0] litedramcore_master_p3_bank = 3'd0;
-reg litedramcore_master_p3_cas_n = 1'd1;
-reg litedramcore_master_p3_cs_n = 1'd1;
-reg litedramcore_master_p3_ras_n = 1'd1;
-reg litedramcore_master_p3_we_n = 1'd1;
-reg litedramcore_master_p3_cke = 1'd0;
-reg litedramcore_master_p3_odt = 1'd0;
-reg litedramcore_master_p3_reset_n = 1'd0;
-reg litedramcore_master_p3_act_n = 1'd1;
-reg [31:0] litedramcore_master_p3_wrdata = 32'd0;
-reg litedramcore_master_p3_wrdata_en = 1'd0;
-reg [3:0] litedramcore_master_p3_wrdata_mask = 4'd0;
-reg litedramcore_master_p3_rddata_en = 1'd0;
-wire [31:0] litedramcore_master_p3_rddata;
-wire litedramcore_master_p3_rddata_valid;
-wire [15:0] litedramcore_csr_dfi_p0_address;
-wire [2:0] litedramcore_csr_dfi_p0_bank;
-reg litedramcore_csr_dfi_p0_cas_n = 1'd1;
-reg litedramcore_csr_dfi_p0_cs_n = 1'd1;
-reg litedramcore_csr_dfi_p0_ras_n = 1'd1;
-reg litedramcore_csr_dfi_p0_we_n = 1'd1;
-wire litedramcore_csr_dfi_p0_cke;
-wire litedramcore_csr_dfi_p0_odt;
-wire litedramcore_csr_dfi_p0_reset_n;
-reg litedramcore_csr_dfi_p0_act_n = 1'd1;
-wire [31:0] litedramcore_csr_dfi_p0_wrdata;
-wire litedramcore_csr_dfi_p0_wrdata_en;
-wire [3:0] litedramcore_csr_dfi_p0_wrdata_mask;
-wire litedramcore_csr_dfi_p0_rddata_en;
-reg [31:0] litedramcore_csr_dfi_p0_rddata = 32'd0;
-reg litedramcore_csr_dfi_p0_rddata_valid = 1'd0;
-wire [15:0] litedramcore_csr_dfi_p1_address;
-wire [2:0] litedramcore_csr_dfi_p1_bank;
-reg litedramcore_csr_dfi_p1_cas_n = 1'd1;
-reg litedramcore_csr_dfi_p1_cs_n = 1'd1;
-reg litedramcore_csr_dfi_p1_ras_n = 1'd1;
-reg litedramcore_csr_dfi_p1_we_n = 1'd1;
-wire litedramcore_csr_dfi_p1_cke;
-wire litedramcore_csr_dfi_p1_odt;
-wire litedramcore_csr_dfi_p1_reset_n;
-reg litedramcore_csr_dfi_p1_act_n = 1'd1;
-wire [31:0] litedramcore_csr_dfi_p1_wrdata;
-wire litedramcore_csr_dfi_p1_wrdata_en;
-wire [3:0] litedramcore_csr_dfi_p1_wrdata_mask;
-wire litedramcore_csr_dfi_p1_rddata_en;
-reg [31:0] litedramcore_csr_dfi_p1_rddata = 32'd0;
-reg litedramcore_csr_dfi_p1_rddata_valid = 1'd0;
-wire [15:0] litedramcore_csr_dfi_p2_address;
-wire [2:0] litedramcore_csr_dfi_p2_bank;
-reg litedramcore_csr_dfi_p2_cas_n = 1'd1;
-reg litedramcore_csr_dfi_p2_cs_n = 1'd1;
-reg litedramcore_csr_dfi_p2_ras_n = 1'd1;
-reg litedramcore_csr_dfi_p2_we_n = 1'd1;
-wire litedramcore_csr_dfi_p2_cke;
-wire litedramcore_csr_dfi_p2_odt;
-wire litedramcore_csr_dfi_p2_reset_n;
-reg litedramcore_csr_dfi_p2_act_n = 1'd1;
-wire [31:0] litedramcore_csr_dfi_p2_wrdata;
-wire litedramcore_csr_dfi_p2_wrdata_en;
-wire [3:0] litedramcore_csr_dfi_p2_wrdata_mask;
-wire litedramcore_csr_dfi_p2_rddata_en;
-reg [31:0] litedramcore_csr_dfi_p2_rddata = 32'd0;
-reg litedramcore_csr_dfi_p2_rddata_valid = 1'd0;
-wire [15:0] litedramcore_csr_dfi_p3_address;
-wire [2:0] litedramcore_csr_dfi_p3_bank;
-reg litedramcore_csr_dfi_p3_cas_n = 1'd1;
-reg litedramcore_csr_dfi_p3_cs_n = 1'd1;
-reg litedramcore_csr_dfi_p3_ras_n = 1'd1;
-reg litedramcore_csr_dfi_p3_we_n = 1'd1;
-wire litedramcore_csr_dfi_p3_cke;
-wire litedramcore_csr_dfi_p3_odt;
-wire litedramcore_csr_dfi_p3_reset_n;
-reg litedramcore_csr_dfi_p3_act_n = 1'd1;
-wire [31:0] litedramcore_csr_dfi_p3_wrdata;
-wire litedramcore_csr_dfi_p3_wrdata_en;
-wire [3:0] litedramcore_csr_dfi_p3_wrdata_mask;
-wire litedramcore_csr_dfi_p3_rddata_en;
-reg [31:0] litedramcore_csr_dfi_p3_rddata = 32'd0;
-reg litedramcore_csr_dfi_p3_rddata_valid = 1'd0;
-reg [15:0] litedramcore_ext_dfi_p0_address = 16'd0;
-reg [2:0] litedramcore_ext_dfi_p0_bank = 3'd0;
-reg litedramcore_ext_dfi_p0_cas_n = 1'd1;
-reg litedramcore_ext_dfi_p0_cs_n = 1'd1;
-reg litedramcore_ext_dfi_p0_ras_n = 1'd1;
-reg litedramcore_ext_dfi_p0_we_n = 1'd1;
-reg litedramcore_ext_dfi_p0_cke = 1'd0;
-reg litedramcore_ext_dfi_p0_odt = 1'd0;
-reg litedramcore_ext_dfi_p0_reset_n = 1'd0;
-reg litedramcore_ext_dfi_p0_act_n = 1'd1;
-reg [31:0] litedramcore_ext_dfi_p0_wrdata = 32'd0;
-reg litedramcore_ext_dfi_p0_wrdata_en = 1'd0;
-reg [3:0] litedramcore_ext_dfi_p0_wrdata_mask = 4'd0;
-reg litedramcore_ext_dfi_p0_rddata_en = 1'd0;
-reg [31:0] litedramcore_ext_dfi_p0_rddata = 32'd0;
-reg litedramcore_ext_dfi_p0_rddata_valid = 1'd0;
-reg [15:0] litedramcore_ext_dfi_p1_address = 16'd0;
-reg [2:0] litedramcore_ext_dfi_p1_bank = 3'd0;
-reg litedramcore_ext_dfi_p1_cas_n = 1'd1;
-reg litedramcore_ext_dfi_p1_cs_n = 1'd1;
-reg litedramcore_ext_dfi_p1_ras_n = 1'd1;
-reg litedramcore_ext_dfi_p1_we_n = 1'd1;
-reg litedramcore_ext_dfi_p1_cke = 1'd0;
-reg litedramcore_ext_dfi_p1_odt = 1'd0;
-reg litedramcore_ext_dfi_p1_reset_n = 1'd0;
-reg litedramcore_ext_dfi_p1_act_n = 1'd1;
-reg [31:0] litedramcore_ext_dfi_p1_wrdata = 32'd0;
-reg litedramcore_ext_dfi_p1_wrdata_en = 1'd0;
-reg [3:0] litedramcore_ext_dfi_p1_wrdata_mask = 4'd0;
-reg litedramcore_ext_dfi_p1_rddata_en = 1'd0;
-reg [31:0] litedramcore_ext_dfi_p1_rddata = 32'd0;
-reg litedramcore_ext_dfi_p1_rddata_valid = 1'd0;
-reg [15:0] litedramcore_ext_dfi_p2_address = 16'd0;
-reg [2:0] litedramcore_ext_dfi_p2_bank = 3'd0;
-reg litedramcore_ext_dfi_p2_cas_n = 1'd1;
-reg litedramcore_ext_dfi_p2_cs_n = 1'd1;
-reg litedramcore_ext_dfi_p2_ras_n = 1'd1;
-reg litedramcore_ext_dfi_p2_we_n = 1'd1;
-reg litedramcore_ext_dfi_p2_cke = 1'd0;
-reg litedramcore_ext_dfi_p2_odt = 1'd0;
-reg litedramcore_ext_dfi_p2_reset_n = 1'd0;
-reg litedramcore_ext_dfi_p2_act_n = 1'd1;
-reg [31:0] litedramcore_ext_dfi_p2_wrdata = 32'd0;
-reg litedramcore_ext_dfi_p2_wrdata_en = 1'd0;
-reg [3:0] litedramcore_ext_dfi_p2_wrdata_mask = 4'd0;
-reg litedramcore_ext_dfi_p2_rddata_en = 1'd0;
-reg [31:0] litedramcore_ext_dfi_p2_rddata = 32'd0;
-reg litedramcore_ext_dfi_p2_rddata_valid = 1'd0;
-reg [15:0] litedramcore_ext_dfi_p3_address = 16'd0;
-reg [2:0] litedramcore_ext_dfi_p3_bank = 3'd0;
-reg litedramcore_ext_dfi_p3_cas_n = 1'd1;
-reg litedramcore_ext_dfi_p3_cs_n = 1'd1;
-reg litedramcore_ext_dfi_p3_ras_n = 1'd1;
-reg litedramcore_ext_dfi_p3_we_n = 1'd1;
-reg litedramcore_ext_dfi_p3_cke = 1'd0;
-reg litedramcore_ext_dfi_p3_odt = 1'd0;
-reg litedramcore_ext_dfi_p3_reset_n = 1'd0;
-reg litedramcore_ext_dfi_p3_act_n = 1'd1;
-reg [31:0] litedramcore_ext_dfi_p3_wrdata = 32'd0;
-reg litedramcore_ext_dfi_p3_wrdata_en = 1'd0;
-reg [3:0] litedramcore_ext_dfi_p3_wrdata_mask = 4'd0;
-reg litedramcore_ext_dfi_p3_rddata_en = 1'd0;
-reg [31:0] litedramcore_ext_dfi_p3_rddata = 32'd0;
-reg litedramcore_ext_dfi_p3_rddata_valid = 1'd0;
-reg litedramcore_ext_dfi_sel = 1'd0;
-wire litedramcore_sel;
-wire litedramcore_cke;
-wire litedramcore_odt;
-wire litedramcore_reset_n;
-reg [3:0] litedramcore_storage = 4'd1;
-reg litedramcore_re = 1'd0;
-wire litedramcore_phaseinjector0_csrfield_cs;
-wire litedramcore_phaseinjector0_csrfield_we;
-wire litedramcore_phaseinjector0_csrfield_cas;
-wire litedramcore_phaseinjector0_csrfield_ras;
-wire litedramcore_phaseinjector0_csrfield_wren;
-wire litedramcore_phaseinjector0_csrfield_rden;
-reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0;
-reg litedramcore_phaseinjector0_command_re = 1'd0;
-reg litedramcore_phaseinjector0_command_issue_re = 1'd0;
-wire litedramcore_phaseinjector0_command_issue_r;
-reg litedramcore_phaseinjector0_command_issue_we = 1'd0;
-reg litedramcore_phaseinjector0_command_issue_w = 1'd0;
-reg [15:0] litedramcore_phaseinjector0_address_storage = 16'd0;
-reg litedramcore_phaseinjector0_address_re = 1'd0;
-reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0;
-reg litedramcore_phaseinjector0_baddress_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector0_wrdata_storage = 32'd0;
-reg litedramcore_phaseinjector0_wrdata_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector0_rddata_status = 32'd0;
-wire litedramcore_phaseinjector0_rddata_we;
-reg litedramcore_phaseinjector0_rddata_re = 1'd0;
-wire litedramcore_phaseinjector1_csrfield_cs;
-wire litedramcore_phaseinjector1_csrfield_we;
-wire litedramcore_phaseinjector1_csrfield_cas;
-wire litedramcore_phaseinjector1_csrfield_ras;
-wire litedramcore_phaseinjector1_csrfield_wren;
-wire litedramcore_phaseinjector1_csrfield_rden;
-reg [5:0] litedramcore_phaseinjector1_command_storage = 6'd0;
-reg litedramcore_phaseinjector1_command_re = 1'd0;
-reg litedramcore_phaseinjector1_command_issue_re = 1'd0;
-wire litedramcore_phaseinjector1_command_issue_r;
-reg litedramcore_phaseinjector1_command_issue_we = 1'd0;
-reg litedramcore_phaseinjector1_command_issue_w = 1'd0;
-reg [15:0] litedramcore_phaseinjector1_address_storage = 16'd0;
-reg litedramcore_phaseinjector1_address_re = 1'd0;
-reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0;
-reg litedramcore_phaseinjector1_baddress_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector1_wrdata_storage = 32'd0;
-reg litedramcore_phaseinjector1_wrdata_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector1_rddata_status = 32'd0;
-wire litedramcore_phaseinjector1_rddata_we;
-reg litedramcore_phaseinjector1_rddata_re = 1'd0;
-wire litedramcore_phaseinjector2_csrfield_cs;
-wire litedramcore_phaseinjector2_csrfield_we;
-wire litedramcore_phaseinjector2_csrfield_cas;
-wire litedramcore_phaseinjector2_csrfield_ras;
-wire litedramcore_phaseinjector2_csrfield_wren;
-wire litedramcore_phaseinjector2_csrfield_rden;
-reg [5:0] litedramcore_phaseinjector2_command_storage = 6'd0;
-reg litedramcore_phaseinjector2_command_re = 1'd0;
-reg litedramcore_phaseinjector2_command_issue_re = 1'd0;
-wire litedramcore_phaseinjector2_command_issue_r;
-reg litedramcore_phaseinjector2_command_issue_we = 1'd0;
-reg litedramcore_phaseinjector2_command_issue_w = 1'd0;
-reg [15:0] litedramcore_phaseinjector2_address_storage = 16'd0;
-reg litedramcore_phaseinjector2_address_re = 1'd0;
-reg [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0;
-reg litedramcore_phaseinjector2_baddress_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector2_wrdata_storage = 32'd0;
-reg litedramcore_phaseinjector2_wrdata_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector2_rddata_status = 32'd0;
-wire litedramcore_phaseinjector2_rddata_we;
-reg litedramcore_phaseinjector2_rddata_re = 1'd0;
-wire litedramcore_phaseinjector3_csrfield_cs;
-wire litedramcore_phaseinjector3_csrfield_we;
-wire litedramcore_phaseinjector3_csrfield_cas;
-wire litedramcore_phaseinjector3_csrfield_ras;
-wire litedramcore_phaseinjector3_csrfield_wren;
-wire litedramcore_phaseinjector3_csrfield_rden;
-reg [5:0] litedramcore_phaseinjector3_command_storage = 6'd0;
-reg litedramcore_phaseinjector3_command_re = 1'd0;
-reg litedramcore_phaseinjector3_command_issue_re = 1'd0;
-wire litedramcore_phaseinjector3_command_issue_r;
-reg litedramcore_phaseinjector3_command_issue_we = 1'd0;
-reg litedramcore_phaseinjector3_command_issue_w = 1'd0;
-reg [15:0] litedramcore_phaseinjector3_address_storage = 16'd0;
-reg litedramcore_phaseinjector3_address_re = 1'd0;
-reg [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0;
-reg litedramcore_phaseinjector3_baddress_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector3_wrdata_storage = 32'd0;
-reg litedramcore_phaseinjector3_wrdata_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector3_rddata_status = 32'd0;
-wire litedramcore_phaseinjector3_rddata_we;
-reg litedramcore_phaseinjector3_rddata_re = 1'd0;
-wire litedramcore_interface_bank0_valid;
-wire litedramcore_interface_bank0_ready;
-wire litedramcore_interface_bank0_we;
-wire [22:0] litedramcore_interface_bank0_addr;
-wire litedramcore_interface_bank0_lock;
-wire litedramcore_interface_bank0_wdata_ready;
-wire litedramcore_interface_bank0_rdata_valid;
-wire litedramcore_interface_bank1_valid;
-wire litedramcore_interface_bank1_ready;
-wire litedramcore_interface_bank1_we;
-wire [22:0] litedramcore_interface_bank1_addr;
-wire litedramcore_interface_bank1_lock;
-wire litedramcore_interface_bank1_wdata_ready;
-wire litedramcore_interface_bank1_rdata_valid;
-wire litedramcore_interface_bank2_valid;
-wire litedramcore_interface_bank2_ready;
-wire litedramcore_interface_bank2_we;
-wire [22:0] litedramcore_interface_bank2_addr;
-wire litedramcore_interface_bank2_lock;
-wire litedramcore_interface_bank2_wdata_ready;
-wire litedramcore_interface_bank2_rdata_valid;
-wire litedramcore_interface_bank3_valid;
-wire litedramcore_interface_bank3_ready;
-wire litedramcore_interface_bank3_we;
-wire [22:0] litedramcore_interface_bank3_addr;
-wire litedramcore_interface_bank3_lock;
-wire litedramcore_interface_bank3_wdata_ready;
-wire litedramcore_interface_bank3_rdata_valid;
-wire litedramcore_interface_bank4_valid;
-wire litedramcore_interface_bank4_ready;
-wire litedramcore_interface_bank4_we;
-wire [22:0] litedramcore_interface_bank4_addr;
-wire litedramcore_interface_bank4_lock;
-wire litedramcore_interface_bank4_wdata_ready;
-wire litedramcore_interface_bank4_rdata_valid;
-wire litedramcore_interface_bank5_valid;
-wire litedramcore_interface_bank5_ready;
-wire litedramcore_interface_bank5_we;
-wire [22:0] litedramcore_interface_bank5_addr;
-wire litedramcore_interface_bank5_lock;
-wire litedramcore_interface_bank5_wdata_ready;
-wire litedramcore_interface_bank5_rdata_valid;
-wire litedramcore_interface_bank6_valid;
-wire litedramcore_interface_bank6_ready;
-wire litedramcore_interface_bank6_we;
-wire [22:0] litedramcore_interface_bank6_addr;
-wire litedramcore_interface_bank6_lock;
-wire litedramcore_interface_bank6_wdata_ready;
-wire litedramcore_interface_bank6_rdata_valid;
-wire litedramcore_interface_bank7_valid;
-wire litedramcore_interface_bank7_ready;
-wire litedramcore_interface_bank7_we;
-wire [22:0] litedramcore_interface_bank7_addr;
-wire litedramcore_interface_bank7_lock;
-wire litedramcore_interface_bank7_wdata_ready;
-wire litedramcore_interface_bank7_rdata_valid;
-reg [127:0] litedramcore_interface_wdata = 128'd0;
-reg [15:0] litedramcore_interface_wdata_we = 16'd0;
-wire [127:0] litedramcore_interface_rdata;
-reg [15:0] litedramcore_dfi_p0_address = 16'd0;
-reg [2:0] litedramcore_dfi_p0_bank = 3'd0;
-reg litedramcore_dfi_p0_cas_n = 1'd1;
-reg litedramcore_dfi_p0_cs_n = 1'd1;
-reg litedramcore_dfi_p0_ras_n = 1'd1;
-reg litedramcore_dfi_p0_we_n = 1'd1;
-wire litedramcore_dfi_p0_cke;
-wire litedramcore_dfi_p0_odt;
-wire litedramcore_dfi_p0_reset_n;
-reg litedramcore_dfi_p0_act_n = 1'd1;
-wire [31:0] litedramcore_dfi_p0_wrdata;
-reg litedramcore_dfi_p0_wrdata_en = 1'd0;
-wire [3:0] litedramcore_dfi_p0_wrdata_mask;
-reg litedramcore_dfi_p0_rddata_en = 1'd0;
-wire [31:0] litedramcore_dfi_p0_rddata;
-wire litedramcore_dfi_p0_rddata_valid;
-reg [15:0] litedramcore_dfi_p1_address = 16'd0;
-reg [2:0] litedramcore_dfi_p1_bank = 3'd0;
-reg litedramcore_dfi_p1_cas_n = 1'd1;
-reg litedramcore_dfi_p1_cs_n = 1'd1;
-reg litedramcore_dfi_p1_ras_n = 1'd1;
-reg litedramcore_dfi_p1_we_n = 1'd1;
-wire litedramcore_dfi_p1_cke;
-wire litedramcore_dfi_p1_odt;
-wire litedramcore_dfi_p1_reset_n;
-reg litedramcore_dfi_p1_act_n = 1'd1;
-wire [31:0] litedramcore_dfi_p1_wrdata;
-reg litedramcore_dfi_p1_wrdata_en = 1'd0;
-wire [3:0] litedramcore_dfi_p1_wrdata_mask;
-reg litedramcore_dfi_p1_rddata_en = 1'd0;
-wire [31:0] litedramcore_dfi_p1_rddata;
-wire litedramcore_dfi_p1_rddata_valid;
-reg [15:0] litedramcore_dfi_p2_address = 16'd0;
-reg [2:0] litedramcore_dfi_p2_bank = 3'd0;
-reg litedramcore_dfi_p2_cas_n = 1'd1;
-reg litedramcore_dfi_p2_cs_n = 1'd1;
-reg litedramcore_dfi_p2_ras_n = 1'd1;
-reg litedramcore_dfi_p2_we_n = 1'd1;
-wire litedramcore_dfi_p2_cke;
-wire litedramcore_dfi_p2_odt;
-wire litedramcore_dfi_p2_reset_n;
-reg litedramcore_dfi_p2_act_n = 1'd1;
-wire [31:0] litedramcore_dfi_p2_wrdata;
-reg litedramcore_dfi_p2_wrdata_en = 1'd0;
-wire [3:0] litedramcore_dfi_p2_wrdata_mask;
-reg litedramcore_dfi_p2_rddata_en = 1'd0;
-wire [31:0] litedramcore_dfi_p2_rddata;
-wire litedramcore_dfi_p2_rddata_valid;
-reg [15:0] litedramcore_dfi_p3_address = 16'd0;
-reg [2:0] litedramcore_dfi_p3_bank = 3'd0;
-reg litedramcore_dfi_p3_cas_n = 1'd1;
-reg litedramcore_dfi_p3_cs_n = 1'd1;
-reg litedramcore_dfi_p3_ras_n = 1'd1;
-reg litedramcore_dfi_p3_we_n = 1'd1;
-wire litedramcore_dfi_p3_cke;
-wire litedramcore_dfi_p3_odt;
-wire litedramcore_dfi_p3_reset_n;
-reg litedramcore_dfi_p3_act_n = 1'd1;
-wire [31:0] litedramcore_dfi_p3_wrdata;
-reg litedramcore_dfi_p3_wrdata_en = 1'd0;
-wire [3:0] litedramcore_dfi_p3_wrdata_mask;
-reg litedramcore_dfi_p3_rddata_en = 1'd0;
-wire [31:0] litedramcore_dfi_p3_rddata;
-wire litedramcore_dfi_p3_rddata_valid;
-reg litedramcore_cmd_valid = 1'd0;
-reg litedramcore_cmd_ready = 1'd0;
-reg litedramcore_cmd_last = 1'd0;
-reg [15:0] litedramcore_cmd_payload_a = 16'd0;
-reg [2:0] litedramcore_cmd_payload_ba = 3'd0;
-reg litedramcore_cmd_payload_cas = 1'd0;
-reg litedramcore_cmd_payload_ras = 1'd0;
-reg litedramcore_cmd_payload_we = 1'd0;
-reg litedramcore_cmd_payload_is_read = 1'd0;
-reg litedramcore_cmd_payload_is_write = 1'd0;
-wire litedramcore_wants_refresh;
-wire litedramcore_wants_zqcs;
-wire litedramcore_timer_wait;
-wire litedramcore_timer_done0;
-wire [9:0] litedramcore_timer_count0;
-wire litedramcore_timer_done1;
-reg [9:0] litedramcore_timer_count1 = 10'd781;
-wire litedramcore_postponer_req_i;
-reg litedramcore_postponer_req_o = 1'd0;
-reg litedramcore_postponer_count = 1'd0;
-reg litedramcore_sequencer_start0 = 1'd0;
-wire litedramcore_sequencer_done0;
-wire litedramcore_sequencer_start1;
-reg litedramcore_sequencer_done1 = 1'd0;
-reg [6:0] litedramcore_sequencer_counter = 7'd0;
-reg litedramcore_sequencer_count = 1'd0;
-wire litedramcore_zqcs_timer_wait;
-wire litedramcore_zqcs_timer_done0;
-wire [26:0] litedramcore_zqcs_timer_count0;
-wire litedramcore_zqcs_timer_done1;
-reg [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999;
-reg litedramcore_zqcs_executer_start = 1'd0;
-reg litedramcore_zqcs_executer_done = 1'd0;
-reg [4:0] litedramcore_zqcs_executer_counter = 5'd0;
-wire litedramcore_bankmachine0_req_valid;
-wire litedramcore_bankmachine0_req_ready;
-wire litedramcore_bankmachine0_req_we;
-wire [22:0] litedramcore_bankmachine0_req_addr;
-wire litedramcore_bankmachine0_req_lock;
-reg litedramcore_bankmachine0_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine0_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine0_refresh_req;
-reg litedramcore_bankmachine0_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine0_cmd_valid = 1'd0;
-reg litedramcore_bankmachine0_cmd_ready = 1'd0;
-reg [15:0] litedramcore_bankmachine0_cmd_payload_a = 16'd0;
-wire [2:0] litedramcore_bankmachine0_cmd_payload_ba;
-reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine0_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine0_auto_precharge = 1'd0;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
-wire [22:0] litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
-wire [22:0] litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
-wire [25:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
-wire [25:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-reg [4:0] litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [25:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we;
-wire [25:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr;
-wire [25:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [22:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [22:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine0_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine0_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine0_cmd_buffer_sink_first;
-wire litedramcore_bankmachine0_cmd_buffer_sink_last;
-wire litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
-wire [22:0] litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine0_cmd_buffer_source_ready;
-reg litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
-reg [22:0] litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 23'd0;
-reg [15:0] litedramcore_bankmachine0_row = 16'd0;
-reg litedramcore_bankmachine0_row_opened = 1'd0;
-wire litedramcore_bankmachine0_row_hit;
-reg litedramcore_bankmachine0_row_open = 1'd0;
-reg litedramcore_bankmachine0_row_close = 1'd0;
-reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine0_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine0_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine0_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine0_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine0_trccon_count = 3'd0;
-wire litedramcore_bankmachine0_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine0_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine0_trascon_count = 3'd0;
-wire litedramcore_bankmachine1_req_valid;
-wire litedramcore_bankmachine1_req_ready;
-wire litedramcore_bankmachine1_req_we;
-wire [22:0] litedramcore_bankmachine1_req_addr;
-wire litedramcore_bankmachine1_req_lock;
-reg litedramcore_bankmachine1_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine1_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine1_refresh_req;
-reg litedramcore_bankmachine1_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine1_cmd_valid = 1'd0;
-reg litedramcore_bankmachine1_cmd_ready = 1'd0;
-reg [15:0] litedramcore_bankmachine1_cmd_payload_a = 16'd0;
-wire [2:0] litedramcore_bankmachine1_cmd_payload_ba;
-reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine1_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine1_auto_precharge = 1'd0;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
-wire [22:0] litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
-wire [22:0] litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
-wire [25:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
-wire [25:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-reg [4:0] litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [25:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we;
-wire [25:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr;
-wire [25:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [22:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [22:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine1_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine1_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine1_cmd_buffer_sink_first;
-wire litedramcore_bankmachine1_cmd_buffer_sink_last;
-wire litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
-wire [22:0] litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine1_cmd_buffer_source_ready;
-reg litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
-reg [22:0] litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 23'd0;
-reg [15:0] litedramcore_bankmachine1_row = 16'd0;
-reg litedramcore_bankmachine1_row_opened = 1'd0;
-wire litedramcore_bankmachine1_row_hit;
-reg litedramcore_bankmachine1_row_open = 1'd0;
-reg litedramcore_bankmachine1_row_close = 1'd0;
-reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine1_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine1_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine1_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine1_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine1_trccon_count = 3'd0;
-wire litedramcore_bankmachine1_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine1_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine1_trascon_count = 3'd0;
-wire litedramcore_bankmachine2_req_valid;
-wire litedramcore_bankmachine2_req_ready;
-wire litedramcore_bankmachine2_req_we;
-wire [22:0] litedramcore_bankmachine2_req_addr;
-wire litedramcore_bankmachine2_req_lock;
-reg litedramcore_bankmachine2_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine2_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine2_refresh_req;
-reg litedramcore_bankmachine2_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine2_cmd_valid = 1'd0;
-reg litedramcore_bankmachine2_cmd_ready = 1'd0;
-reg [15:0] litedramcore_bankmachine2_cmd_payload_a = 16'd0;
-wire [2:0] litedramcore_bankmachine2_cmd_payload_ba;
-reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine2_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine2_auto_precharge = 1'd0;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
-wire [22:0] litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
-wire [22:0] litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
-wire [25:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
-wire [25:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-reg [4:0] litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [25:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we;
-wire [25:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr;
-wire [25:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [22:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [22:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine2_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine2_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine2_cmd_buffer_sink_first;
-wire litedramcore_bankmachine2_cmd_buffer_sink_last;
-wire litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
-wire [22:0] litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine2_cmd_buffer_source_ready;
-reg litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
-reg [22:0] litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 23'd0;
-reg [15:0] litedramcore_bankmachine2_row = 16'd0;
-reg litedramcore_bankmachine2_row_opened = 1'd0;
-wire litedramcore_bankmachine2_row_hit;
-reg litedramcore_bankmachine2_row_open = 1'd0;
-reg litedramcore_bankmachine2_row_close = 1'd0;
-reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine2_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine2_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine2_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine2_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine2_trccon_count = 3'd0;
-wire litedramcore_bankmachine2_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine2_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine2_trascon_count = 3'd0;
-wire litedramcore_bankmachine3_req_valid;
-wire litedramcore_bankmachine3_req_ready;
-wire litedramcore_bankmachine3_req_we;
-wire [22:0] litedramcore_bankmachine3_req_addr;
-wire litedramcore_bankmachine3_req_lock;
-reg litedramcore_bankmachine3_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine3_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine3_refresh_req;
-reg litedramcore_bankmachine3_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine3_cmd_valid = 1'd0;
-reg litedramcore_bankmachine3_cmd_ready = 1'd0;
-reg [15:0] litedramcore_bankmachine3_cmd_payload_a = 16'd0;
-wire [2:0] litedramcore_bankmachine3_cmd_payload_ba;
-reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine3_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine3_auto_precharge = 1'd0;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
-wire [22:0] litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
-wire [22:0] litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
-wire [25:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
-wire [25:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-reg [4:0] litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [25:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we;
-wire [25:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr;
-wire [25:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [22:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [22:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine3_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine3_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine3_cmd_buffer_sink_first;
-wire litedramcore_bankmachine3_cmd_buffer_sink_last;
-wire litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
-wire [22:0] litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine3_cmd_buffer_source_ready;
-reg litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
-reg [22:0] litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 23'd0;
-reg [15:0] litedramcore_bankmachine3_row = 16'd0;
-reg litedramcore_bankmachine3_row_opened = 1'd0;
-wire litedramcore_bankmachine3_row_hit;
-reg litedramcore_bankmachine3_row_open = 1'd0;
-reg litedramcore_bankmachine3_row_close = 1'd0;
-reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine3_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine3_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine3_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine3_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine3_trccon_count = 3'd0;
-wire litedramcore_bankmachine3_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine3_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine3_trascon_count = 3'd0;
-wire litedramcore_bankmachine4_req_valid;
-wire litedramcore_bankmachine4_req_ready;
-wire litedramcore_bankmachine4_req_we;
-wire [22:0] litedramcore_bankmachine4_req_addr;
-wire litedramcore_bankmachine4_req_lock;
-reg litedramcore_bankmachine4_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine4_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine4_refresh_req;
-reg litedramcore_bankmachine4_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine4_cmd_valid = 1'd0;
-reg litedramcore_bankmachine4_cmd_ready = 1'd0;
-reg [15:0] litedramcore_bankmachine4_cmd_payload_a = 16'd0;
-wire [2:0] litedramcore_bankmachine4_cmd_payload_ba;
-reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine4_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine4_auto_precharge = 1'd0;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
-wire [22:0] litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
-wire [22:0] litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
-wire [25:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
-wire [25:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-reg [4:0] litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [25:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we;
-wire [25:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr;
-wire [25:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [22:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [22:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine4_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine4_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine4_cmd_buffer_sink_first;
-wire litedramcore_bankmachine4_cmd_buffer_sink_last;
-wire litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
-wire [22:0] litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine4_cmd_buffer_source_ready;
-reg litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
-reg [22:0] litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 23'd0;
-reg [15:0] litedramcore_bankmachine4_row = 16'd0;
-reg litedramcore_bankmachine4_row_opened = 1'd0;
-wire litedramcore_bankmachine4_row_hit;
-reg litedramcore_bankmachine4_row_open = 1'd0;
-reg litedramcore_bankmachine4_row_close = 1'd0;
-reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine4_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine4_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine4_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine4_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine4_trccon_count = 3'd0;
-wire litedramcore_bankmachine4_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine4_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine4_trascon_count = 3'd0;
-wire litedramcore_bankmachine5_req_valid;
-wire litedramcore_bankmachine5_req_ready;
-wire litedramcore_bankmachine5_req_we;
-wire [22:0] litedramcore_bankmachine5_req_addr;
-wire litedramcore_bankmachine5_req_lock;
-reg litedramcore_bankmachine5_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine5_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine5_refresh_req;
-reg litedramcore_bankmachine5_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine5_cmd_valid = 1'd0;
-reg litedramcore_bankmachine5_cmd_ready = 1'd0;
-reg [15:0] litedramcore_bankmachine5_cmd_payload_a = 16'd0;
-wire [2:0] litedramcore_bankmachine5_cmd_payload_ba;
-reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine5_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine5_auto_precharge = 1'd0;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
-wire [22:0] litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
-wire [22:0] litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
-wire [25:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
-wire [25:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-reg [4:0] litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [25:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we;
-wire [25:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr;
-wire [25:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [22:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [22:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine5_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine5_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine5_cmd_buffer_sink_first;
-wire litedramcore_bankmachine5_cmd_buffer_sink_last;
-wire litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
-wire [22:0] litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine5_cmd_buffer_source_ready;
-reg litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
-reg [22:0] litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 23'd0;
-reg [15:0] litedramcore_bankmachine5_row = 16'd0;
-reg litedramcore_bankmachine5_row_opened = 1'd0;
-wire litedramcore_bankmachine5_row_hit;
-reg litedramcore_bankmachine5_row_open = 1'd0;
-reg litedramcore_bankmachine5_row_close = 1'd0;
-reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine5_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine5_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine5_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine5_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine5_trccon_count = 3'd0;
-wire litedramcore_bankmachine5_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine5_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine5_trascon_count = 3'd0;
-wire litedramcore_bankmachine6_req_valid;
-wire litedramcore_bankmachine6_req_ready;
-wire litedramcore_bankmachine6_req_we;
-wire [22:0] litedramcore_bankmachine6_req_addr;
-wire litedramcore_bankmachine6_req_lock;
-reg litedramcore_bankmachine6_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine6_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine6_refresh_req;
-reg litedramcore_bankmachine6_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine6_cmd_valid = 1'd0;
-reg litedramcore_bankmachine6_cmd_ready = 1'd0;
-reg [15:0] litedramcore_bankmachine6_cmd_payload_a = 16'd0;
-wire [2:0] litedramcore_bankmachine6_cmd_payload_ba;
-reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine6_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine6_auto_precharge = 1'd0;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
-wire [22:0] litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
-wire [22:0] litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
-wire [25:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
-wire [25:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-reg [4:0] litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [25:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we;
-wire [25:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr;
-wire [25:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [22:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [22:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine6_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine6_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine6_cmd_buffer_sink_first;
-wire litedramcore_bankmachine6_cmd_buffer_sink_last;
-wire litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
-wire [22:0] litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine6_cmd_buffer_source_ready;
-reg litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
-reg [22:0] litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 23'd0;
-reg [15:0] litedramcore_bankmachine6_row = 16'd0;
-reg litedramcore_bankmachine6_row_opened = 1'd0;
-wire litedramcore_bankmachine6_row_hit;
-reg litedramcore_bankmachine6_row_open = 1'd0;
-reg litedramcore_bankmachine6_row_close = 1'd0;
-reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine6_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine6_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine6_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine6_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine6_trccon_count = 3'd0;
-wire litedramcore_bankmachine6_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine6_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine6_trascon_count = 3'd0;
-wire litedramcore_bankmachine7_req_valid;
-wire litedramcore_bankmachine7_req_ready;
-wire litedramcore_bankmachine7_req_we;
-wire [22:0] litedramcore_bankmachine7_req_addr;
-wire litedramcore_bankmachine7_req_lock;
-reg litedramcore_bankmachine7_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine7_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine7_refresh_req;
-reg litedramcore_bankmachine7_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine7_cmd_valid = 1'd0;
-reg litedramcore_bankmachine7_cmd_ready = 1'd0;
-reg [15:0] litedramcore_bankmachine7_cmd_payload_a = 16'd0;
-wire [2:0] litedramcore_bankmachine7_cmd_payload_ba;
-reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine7_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine7_auto_precharge = 1'd0;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
-wire [22:0] litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
-wire [22:0] litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
-wire [25:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
-wire [25:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-reg [4:0] litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [25:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we;
-wire [25:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr;
-wire [25:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [22:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [22:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine7_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine7_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine7_cmd_buffer_sink_first;
-wire litedramcore_bankmachine7_cmd_buffer_sink_last;
-wire litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
-wire [22:0] litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine7_cmd_buffer_source_ready;
-reg litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
-reg [22:0] litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 23'd0;
-reg [15:0] litedramcore_bankmachine7_row = 16'd0;
-reg litedramcore_bankmachine7_row_opened = 1'd0;
-wire litedramcore_bankmachine7_row_hit;
-reg litedramcore_bankmachine7_row_open = 1'd0;
-reg litedramcore_bankmachine7_row_close = 1'd0;
-reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine7_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine7_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine7_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine7_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine7_trccon_count = 3'd0;
-wire litedramcore_bankmachine7_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine7_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine7_trascon_count = 3'd0;
-wire litedramcore_ras_allowed;
-wire litedramcore_cas_allowed;
-wire [1:0] litedramcore_rdcmdphase;
-wire [1:0] litedramcore_wrcmdphase;
-reg litedramcore_choose_cmd_want_reads = 1'd0;
-reg litedramcore_choose_cmd_want_writes = 1'd0;
-reg litedramcore_choose_cmd_want_cmds = 1'd0;
-reg litedramcore_choose_cmd_want_activates = 1'd0;
-wire litedramcore_choose_cmd_cmd_valid;
-reg litedramcore_choose_cmd_cmd_ready = 1'd0;
-wire [15:0] litedramcore_choose_cmd_cmd_payload_a;
-wire [2:0] litedramcore_choose_cmd_cmd_payload_ba;
-reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
-reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
-reg litedramcore_choose_cmd_cmd_payload_we = 1'd0;
-wire litedramcore_choose_cmd_cmd_payload_is_cmd;
-wire litedramcore_choose_cmd_cmd_payload_is_read;
-wire litedramcore_choose_cmd_cmd_payload_is_write;
-reg [7:0] litedramcore_choose_cmd_valids = 8'd0;
-wire [7:0] litedramcore_choose_cmd_request;
-reg [2:0] litedramcore_choose_cmd_grant = 3'd0;
-wire litedramcore_choose_cmd_ce;
-reg litedramcore_choose_req_want_reads = 1'd0;
-reg litedramcore_choose_req_want_writes = 1'd0;
-reg litedramcore_choose_req_want_cmds = 1'd0;
-reg litedramcore_choose_req_want_activates = 1'd0;
-wire litedramcore_choose_req_cmd_valid;
-reg litedramcore_choose_req_cmd_ready = 1'd0;
-wire [15:0] litedramcore_choose_req_cmd_payload_a;
-wire [2:0] litedramcore_choose_req_cmd_payload_ba;
-reg litedramcore_choose_req_cmd_payload_cas = 1'd0;
-reg litedramcore_choose_req_cmd_payload_ras = 1'd0;
-reg litedramcore_choose_req_cmd_payload_we = 1'd0;
-wire litedramcore_choose_req_cmd_payload_is_cmd;
-wire litedramcore_choose_req_cmd_payload_is_read;
-wire litedramcore_choose_req_cmd_payload_is_write;
-reg [7:0] litedramcore_choose_req_valids = 8'd0;
-wire [7:0] litedramcore_choose_req_request;
-reg [2:0] litedramcore_choose_req_grant = 3'd0;
-wire litedramcore_choose_req_ce;
-reg [15:0] litedramcore_nop_a = 16'd0;
-reg [2:0] litedramcore_nop_ba = 3'd0;
-reg [1:0] litedramcore_steerer_sel0 = 2'd0;
-reg [1:0] litedramcore_steerer_sel1 = 2'd0;
-reg [1:0] litedramcore_steerer_sel2 = 2'd0;
-reg [1:0] litedramcore_steerer_sel3 = 2'd0;
-reg litedramcore_steerer0 = 1'd1;
-reg litedramcore_steerer1 = 1'd1;
-reg litedramcore_steerer2 = 1'd1;
-reg litedramcore_steerer3 = 1'd1;
-reg litedramcore_steerer4 = 1'd1;
-reg litedramcore_steerer5 = 1'd1;
-reg litedramcore_steerer6 = 1'd1;
-reg litedramcore_steerer7 = 1'd1;
-wire litedramcore_trrdcon_valid;
-(* dont_touch = "true" *) reg litedramcore_trrdcon_ready = 1'd0;
-reg litedramcore_trrdcon_count = 1'd0;
-wire litedramcore_tfawcon_valid;
-(* dont_touch = "true" *) reg litedramcore_tfawcon_ready = 1'd1;
-wire [2:0] litedramcore_tfawcon_count;
-reg [4:0] litedramcore_tfawcon_window = 5'd0;
-wire litedramcore_tccdcon_valid;
-(* dont_touch = "true" *) reg litedramcore_tccdcon_ready = 1'd0;
-reg litedramcore_tccdcon_count = 1'd0;
-wire litedramcore_twtrcon_valid;
-(* dont_touch = "true" *) reg litedramcore_twtrcon_ready = 1'd0;
-reg [2:0] litedramcore_twtrcon_count = 3'd0;
-wire litedramcore_read_available;
-wire litedramcore_write_available;
-reg litedramcore_en0 = 1'd0;
-wire litedramcore_max_time0;
-reg [4:0] litedramcore_time0 = 5'd0;
-reg litedramcore_en1 = 1'd0;
-wire litedramcore_max_time1;
-reg [3:0] litedramcore_time1 = 4'd0;
-wire litedramcore_go_to_refresh;
-reg init_done_storage = 1'd0;
-reg init_done_re = 1'd0;
-reg init_error_storage = 1'd0;
-reg init_error_re = 1'd0;
-wire [29:0] wb_bus_adr;
-wire [31:0] wb_bus_dat_w;
-wire [31:0] wb_bus_dat_r;
-wire [3:0] wb_bus_sel;
-wire wb_bus_cyc;
-wire wb_bus_stb;
-wire wb_bus_ack;
-wire wb_bus_we;
-wire [2:0] wb_bus_cti;
-wire [1:0] wb_bus_bte;
-wire wb_bus_err;
-wire user_enable;
-wire user_port_cmd_valid;
-wire user_port_cmd_ready;
-wire user_port_cmd_payload_we;
-wire [25:0] user_port_cmd_payload_addr;
-wire user_port_wdata_valid;
-wire user_port_wdata_ready;
-wire [127:0] user_port_wdata_payload_data;
-wire [15:0] user_port_wdata_payload_we;
-wire user_port_rdata_valid;
-wire user_port_rdata_ready;
-wire [127:0] user_port_rdata_payload_data;
-reg [13:0] litedramcore_adr = 14'd0;
-reg litedramcore_we = 1'd0;
-reg [31:0] litedramcore_dat_w = 32'd0;
-wire [31:0] litedramcore_dat_r;
-wire [29:0] litedramcore_wishbone_adr;
-wire [31:0] litedramcore_wishbone_dat_w;
-reg [31:0] litedramcore_wishbone_dat_r = 32'd0;
-wire [3:0] litedramcore_wishbone_sel;
-wire litedramcore_wishbone_cyc;
-wire litedramcore_wishbone_stb;
-reg litedramcore_wishbone_ack = 1'd0;
-wire litedramcore_wishbone_we;
-wire [2:0] litedramcore_wishbone_cti;
-wire [1:0] litedramcore_wishbone_bte;
-reg litedramcore_wishbone_err = 1'd0;
-wire [13:0] interface0_bank_bus_adr;
-wire interface0_bank_bus_we;
-wire [31:0] interface0_bank_bus_dat_w;
-reg [31:0] interface0_bank_bus_dat_r = 32'd0;
-reg csrbank0_init_done0_re = 1'd0;
-wire csrbank0_init_done0_r;
-reg csrbank0_init_done0_we = 1'd0;
-wire csrbank0_init_done0_w;
-reg csrbank0_init_error0_re = 1'd0;
-wire csrbank0_init_error0_r;
-reg csrbank0_init_error0_we = 1'd0;
-wire csrbank0_init_error0_w;
-wire csrbank0_sel;
-wire [13:0] interface1_bank_bus_adr;
-wire interface1_bank_bus_we;
-wire [31:0] interface1_bank_bus_dat_w;
-reg [31:0] interface1_bank_bus_dat_r = 32'd0;
-reg csrbank1_rst0_re = 1'd0;
-wire csrbank1_rst0_r;
-reg csrbank1_rst0_we = 1'd0;
-wire csrbank1_rst0_w;
-reg csrbank1_dly_sel0_re = 1'd0;
-wire [1:0] csrbank1_dly_sel0_r;
-reg csrbank1_dly_sel0_we = 1'd0;
-wire [1:0] csrbank1_dly_sel0_w;
-reg csrbank1_half_sys8x_taps0_re = 1'd0;
-wire [4:0] csrbank1_half_sys8x_taps0_r;
-reg csrbank1_half_sys8x_taps0_we = 1'd0;
-wire [4:0] csrbank1_half_sys8x_taps0_w;
-reg csrbank1_wlevel_en0_re = 1'd0;
-wire csrbank1_wlevel_en0_r;
-reg csrbank1_wlevel_en0_we = 1'd0;
-wire csrbank1_wlevel_en0_w;
-reg csrbank1_rdphase0_re = 1'd0;
-wire [1:0] csrbank1_rdphase0_r;
-reg csrbank1_rdphase0_we = 1'd0;
-wire [1:0] csrbank1_rdphase0_w;
-reg csrbank1_wrphase0_re = 1'd0;
-wire [1:0] csrbank1_wrphase0_r;
-reg csrbank1_wrphase0_we = 1'd0;
-wire [1:0] csrbank1_wrphase0_w;
-wire csrbank1_sel;
-wire [13:0] interface2_bank_bus_adr;
-wire interface2_bank_bus_we;
-wire [31:0] interface2_bank_bus_dat_w;
-reg [31:0] interface2_bank_bus_dat_r = 32'd0;
-reg csrbank2_dfii_control0_re = 1'd0;
-wire [3:0] csrbank2_dfii_control0_r;
-reg csrbank2_dfii_control0_we = 1'd0;
-wire [3:0] csrbank2_dfii_control0_w;
-reg csrbank2_dfii_pi0_command0_re = 1'd0;
-wire [5:0] csrbank2_dfii_pi0_command0_r;
-reg csrbank2_dfii_pi0_command0_we = 1'd0;
-wire [5:0] csrbank2_dfii_pi0_command0_w;
-reg csrbank2_dfii_pi0_address0_re = 1'd0;
-wire [15:0] csrbank2_dfii_pi0_address0_r;
-reg csrbank2_dfii_pi0_address0_we = 1'd0;
-wire [15:0] csrbank2_dfii_pi0_address0_w;
-reg csrbank2_dfii_pi0_baddress0_re = 1'd0;
-wire [2:0] csrbank2_dfii_pi0_baddress0_r;
-reg csrbank2_dfii_pi0_baddress0_we = 1'd0;
-wire [2:0] csrbank2_dfii_pi0_baddress0_w;
-reg csrbank2_dfii_pi0_wrdata0_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi0_wrdata0_r;
-reg csrbank2_dfii_pi0_wrdata0_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi0_wrdata0_w;
-reg csrbank2_dfii_pi0_rddata_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi0_rddata_r;
-reg csrbank2_dfii_pi0_rddata_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi0_rddata_w;
-reg csrbank2_dfii_pi1_command0_re = 1'd0;
-wire [5:0] csrbank2_dfii_pi1_command0_r;
-reg csrbank2_dfii_pi1_command0_we = 1'd0;
-wire [5:0] csrbank2_dfii_pi1_command0_w;
-reg csrbank2_dfii_pi1_address0_re = 1'd0;
-wire [15:0] csrbank2_dfii_pi1_address0_r;
-reg csrbank2_dfii_pi1_address0_we = 1'd0;
-wire [15:0] csrbank2_dfii_pi1_address0_w;
-reg csrbank2_dfii_pi1_baddress0_re = 1'd0;
-wire [2:0] csrbank2_dfii_pi1_baddress0_r;
-reg csrbank2_dfii_pi1_baddress0_we = 1'd0;
-wire [2:0] csrbank2_dfii_pi1_baddress0_w;
-reg csrbank2_dfii_pi1_wrdata0_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi1_wrdata0_r;
-reg csrbank2_dfii_pi1_wrdata0_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi1_wrdata0_w;
-reg csrbank2_dfii_pi1_rddata_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi1_rddata_r;
-reg csrbank2_dfii_pi1_rddata_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi1_rddata_w;
-reg csrbank2_dfii_pi2_command0_re = 1'd0;
-wire [5:0] csrbank2_dfii_pi2_command0_r;
-reg csrbank2_dfii_pi2_command0_we = 1'd0;
-wire [5:0] csrbank2_dfii_pi2_command0_w;
-reg csrbank2_dfii_pi2_address0_re = 1'd0;
-wire [15:0] csrbank2_dfii_pi2_address0_r;
-reg csrbank2_dfii_pi2_address0_we = 1'd0;
-wire [15:0] csrbank2_dfii_pi2_address0_w;
-reg csrbank2_dfii_pi2_baddress0_re = 1'd0;
-wire [2:0] csrbank2_dfii_pi2_baddress0_r;
-reg csrbank2_dfii_pi2_baddress0_we = 1'd0;
-wire [2:0] csrbank2_dfii_pi2_baddress0_w;
-reg csrbank2_dfii_pi2_wrdata0_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi2_wrdata0_r;
-reg csrbank2_dfii_pi2_wrdata0_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi2_wrdata0_w;
-reg csrbank2_dfii_pi2_rddata_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi2_rddata_r;
-reg csrbank2_dfii_pi2_rddata_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi2_rddata_w;
-reg csrbank2_dfii_pi3_command0_re = 1'd0;
-wire [5:0] csrbank2_dfii_pi3_command0_r;
-reg csrbank2_dfii_pi3_command0_we = 1'd0;
-wire [5:0] csrbank2_dfii_pi3_command0_w;
-reg csrbank2_dfii_pi3_address0_re = 1'd0;
-wire [15:0] csrbank2_dfii_pi3_address0_r;
-reg csrbank2_dfii_pi3_address0_we = 1'd0;
-wire [15:0] csrbank2_dfii_pi3_address0_w;
-reg csrbank2_dfii_pi3_baddress0_re = 1'd0;
-wire [2:0] csrbank2_dfii_pi3_baddress0_r;
-reg csrbank2_dfii_pi3_baddress0_we = 1'd0;
-wire [2:0] csrbank2_dfii_pi3_baddress0_w;
-reg csrbank2_dfii_pi3_wrdata0_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi3_wrdata0_r;
-reg csrbank2_dfii_pi3_wrdata0_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi3_wrdata0_w;
-reg csrbank2_dfii_pi3_rddata_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi3_rddata_r;
-reg csrbank2_dfii_pi3_rddata_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi3_rddata_w;
-wire csrbank2_sel;
-wire [13:0] csr_interconnect_adr;
-wire csr_interconnect_we;
-wire [31:0] csr_interconnect_dat_w;
-wire [31:0] csr_interconnect_dat_r;
-wire litedramcore_reset0;
-wire litedramcore_reset1;
-wire litedramcore_reset2;
-wire litedramcore_reset3;
-wire litedramcore_reset4;
-wire litedramcore_reset5;
-wire litedramcore_reset6;
-wire litedramcore_reset7;
-wire litedramcore_pll_fb;
-reg [1:0] litedramcore_refresher_state = 2'd0;
-reg [1:0] litedramcore_refresher_next_state = 2'd0;
-reg [3:0] litedramcore_bankmachine0_state = 4'd0;
-reg [3:0] litedramcore_bankmachine0_next_state = 4'd0;
-reg [3:0] litedramcore_bankmachine1_state = 4'd0;
-reg [3:0] litedramcore_bankmachine1_next_state = 4'd0;
-reg [3:0] litedramcore_bankmachine2_state = 4'd0;
-reg [3:0] litedramcore_bankmachine2_next_state = 4'd0;
-reg [3:0] litedramcore_bankmachine3_state = 4'd0;
-reg [3:0] litedramcore_bankmachine3_next_state = 4'd0;
-reg [3:0] litedramcore_bankmachine4_state = 4'd0;
-reg [3:0] litedramcore_bankmachine4_next_state = 4'd0;
-reg [3:0] litedramcore_bankmachine5_state = 4'd0;
-reg [3:0] litedramcore_bankmachine5_next_state = 4'd0;
-reg [3:0] litedramcore_bankmachine6_state = 4'd0;
-reg [3:0] litedramcore_bankmachine6_next_state = 4'd0;
-reg [3:0] litedramcore_bankmachine7_state = 4'd0;
-reg [3:0] litedramcore_bankmachine7_next_state = 4'd0;
-reg [3:0] litedramcore_multiplexer_state = 4'd0;
-reg [3:0] litedramcore_multiplexer_next_state = 4'd0;
-wire litedramcore_roundrobin0_request;
-wire litedramcore_roundrobin0_grant;
-wire litedramcore_roundrobin0_ce;
-wire litedramcore_roundrobin1_request;
-wire litedramcore_roundrobin1_grant;
-wire litedramcore_roundrobin1_ce;
-wire litedramcore_roundrobin2_request;
-wire litedramcore_roundrobin2_grant;
-wire litedramcore_roundrobin2_ce;
-wire litedramcore_roundrobin3_request;
-wire litedramcore_roundrobin3_grant;
-wire litedramcore_roundrobin3_ce;
-wire litedramcore_roundrobin4_request;
-wire litedramcore_roundrobin4_grant;
-wire litedramcore_roundrobin4_ce;
-wire litedramcore_roundrobin5_request;
-wire litedramcore_roundrobin5_grant;
-wire litedramcore_roundrobin5_ce;
-wire litedramcore_roundrobin6_request;
-wire litedramcore_roundrobin6_grant;
-wire litedramcore_roundrobin6_ce;
-wire litedramcore_roundrobin7_request;
-wire litedramcore_roundrobin7_grant;
-wire litedramcore_roundrobin7_ce;
-reg litedramcore_locked0 = 1'd0;
-reg litedramcore_locked1 = 1'd0;
-reg litedramcore_locked2 = 1'd0;
-reg litedramcore_locked3 = 1'd0;
-reg litedramcore_locked4 = 1'd0;
-reg litedramcore_locked5 = 1'd0;
-reg litedramcore_locked6 = 1'd0;
-reg litedramcore_locked7 = 1'd0;
-reg litedramcore_new_master_wdata_ready0 = 1'd0;
-reg litedramcore_new_master_wdata_ready1 = 1'd0;
-reg litedramcore_new_master_rdata_valid0 = 1'd0;
-reg litedramcore_new_master_rdata_valid1 = 1'd0;
-reg litedramcore_new_master_rdata_valid2 = 1'd0;
-reg litedramcore_new_master_rdata_valid3 = 1'd0;
-reg litedramcore_new_master_rdata_valid4 = 1'd0;
-reg litedramcore_new_master_rdata_valid5 = 1'd0;
-reg litedramcore_new_master_rdata_valid6 = 1'd0;
-reg litedramcore_new_master_rdata_valid7 = 1'd0;
-reg litedramcore_new_master_rdata_valid8 = 1'd0;
-reg [1:0] litedramcore_state = 2'd0;
-reg [1:0] litedramcore_next_state = 2'd0;
-reg [31:0] litedramcore_dat_w_next_value0 = 32'd0;
-reg litedramcore_dat_w_next_value_ce0 = 1'd0;
-reg [13:0] litedramcore_adr_next_value1 = 14'd0;
-reg litedramcore_adr_next_value_ce1 = 1'd0;
-reg litedramcore_we_next_value2 = 1'd0;
-reg litedramcore_we_next_value_ce2 = 1'd0;
-reg rhs_array_muxed0 = 1'd0;
-reg [15:0] rhs_array_muxed1 = 16'd0;
-reg [2:0] rhs_array_muxed2 = 3'd0;
-reg rhs_array_muxed3 = 1'd0;
-reg rhs_array_muxed4 = 1'd0;
-reg rhs_array_muxed5 = 1'd0;
-reg t_array_muxed0 = 1'd0;
-reg t_array_muxed1 = 1'd0;
-reg t_array_muxed2 = 1'd0;
-reg rhs_array_muxed6 = 1'd0;
-reg [15:0] rhs_array_muxed7 = 16'd0;
-reg [2:0] rhs_array_muxed8 = 3'd0;
-reg rhs_array_muxed9 = 1'd0;
-reg rhs_array_muxed10 = 1'd0;
-reg rhs_array_muxed11 = 1'd0;
-reg t_array_muxed3 = 1'd0;
-reg t_array_muxed4 = 1'd0;
-reg t_array_muxed5 = 1'd0;
-reg [22:0] rhs_array_muxed12 = 23'd0;
-reg rhs_array_muxed13 = 1'd0;
-reg rhs_array_muxed14 = 1'd0;
-reg [22:0] rhs_array_muxed15 = 23'd0;
-reg rhs_array_muxed16 = 1'd0;
-reg rhs_array_muxed17 = 1'd0;
-reg [22:0] rhs_array_muxed18 = 23'd0;
-reg rhs_array_muxed19 = 1'd0;
-reg rhs_array_muxed20 = 1'd0;
-reg [22:0] rhs_array_muxed21 = 23'd0;
-reg rhs_array_muxed22 = 1'd0;
-reg rhs_array_muxed23 = 1'd0;
-reg [22:0] rhs_array_muxed24 = 23'd0;
-reg rhs_array_muxed25 = 1'd0;
-reg rhs_array_muxed26 = 1'd0;
-reg [22:0] rhs_array_muxed27 = 23'd0;
-reg rhs_array_muxed28 = 1'd0;
-reg rhs_array_muxed29 = 1'd0;
-reg [22:0] rhs_array_muxed30 = 23'd0;
-reg rhs_array_muxed31 = 1'd0;
-reg rhs_array_muxed32 = 1'd0;
-reg [22:0] rhs_array_muxed33 = 23'd0;
-reg rhs_array_muxed34 = 1'd0;
-reg rhs_array_muxed35 = 1'd0;
-reg [2:0] array_muxed0 = 3'd0;
-reg [15:0] array_muxed1 = 16'd0;
-reg array_muxed2 = 1'd0;
-reg array_muxed3 = 1'd0;
-reg array_muxed4 = 1'd0;
-reg array_muxed5 = 1'd0;
-reg array_muxed6 = 1'd0;
-reg [2:0] array_muxed7 = 3'd0;
-reg [15:0] array_muxed8 = 16'd0;
-reg array_muxed9 = 1'd0;
-reg array_muxed10 = 1'd0;
-reg array_muxed11 = 1'd0;
-reg array_muxed12 = 1'd0;
-reg array_muxed13 = 1'd0;
-reg [2:0] array_muxed14 = 3'd0;
-reg [15:0] array_muxed15 = 16'd0;
-reg array_muxed16 = 1'd0;
-reg array_muxed17 = 1'd0;
-reg array_muxed18 = 1'd0;
-reg array_muxed19 = 1'd0;
-reg array_muxed20 = 1'd0;
-reg [2:0] array_muxed21 = 3'd0;
-reg [15:0] array_muxed22 = 16'd0;
-reg array_muxed23 = 1'd0;
-reg array_muxed24 = 1'd0;
-reg array_muxed25 = 1'd0;
-reg array_muxed26 = 1'd0;
-reg array_muxed27 = 1'd0;
-wire xilinxasyncresetsynchronizerimpl0;
-wire xilinxasyncresetsynchronizerimpl0_rst_meta;
-wire xilinxasyncresetsynchronizerimpl1;
-wire xilinxasyncresetsynchronizerimpl1_rst_meta;
-wire xilinxasyncresetsynchronizerimpl2;
-wire xilinxasyncresetsynchronizerimpl2_rst_meta;
-wire xilinxasyncresetsynchronizerimpl2_expr;
-wire xilinxasyncresetsynchronizerimpl3;
-wire xilinxasyncresetsynchronizerimpl3_rst_meta;
-wire xilinxasyncresetsynchronizerimpl3_expr;
+reg rst_1 = 1'd0;
+wire sys_clk;
+wire sys_rst;
+wire sys4x_clk;
+wire sys4x_dqs_clk;
+wire iodelay_clk;
+wire iodelay_rst;
+wire reset;
+reg power_down = 1'd0;
+wire locked;
+wire clkin;
+wire clkout0;
+wire clkout_buf0;
+wire clkout1;
+wire clkout_buf1;
+wire clkout2;
+wire clkout_buf2;
+wire clkout3;
+wire clkout_buf3;
+reg [3:0] reset_counter = 4'd15;
+reg ic_reset = 1'd1;
+reg a7ddrphy_rst_storage = 1'd0;
+reg a7ddrphy_rst_re = 1'd0;
+reg [1:0] a7ddrphy_dly_sel_storage = 2'd0;
+reg a7ddrphy_dly_sel_re = 1'd0;
+reg [4:0] a7ddrphy_half_sys8x_taps_storage = 5'd8;
+reg a7ddrphy_half_sys8x_taps_re = 1'd0;
+reg a7ddrphy_wlevel_en_storage = 1'd0;
+reg a7ddrphy_wlevel_en_re = 1'd0;
+reg a7ddrphy_wlevel_strobe_re = 1'd0;
+wire a7ddrphy_wlevel_strobe_r;
+reg a7ddrphy_wlevel_strobe_we = 1'd0;
+reg a7ddrphy_wlevel_strobe_w = 1'd0;
+reg a7ddrphy_rdly_dq_rst_re = 1'd0;
+wire a7ddrphy_rdly_dq_rst_r;
+reg a7ddrphy_rdly_dq_rst_we = 1'd0;
+reg a7ddrphy_rdly_dq_rst_w = 1'd0;
+reg a7ddrphy_rdly_dq_inc_re = 1'd0;
+wire a7ddrphy_rdly_dq_inc_r;
+reg a7ddrphy_rdly_dq_inc_we = 1'd0;
+reg a7ddrphy_rdly_dq_inc_w = 1'd0;
+reg a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
+wire a7ddrphy_rdly_dq_bitslip_rst_r;
+reg a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
+reg a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
+reg a7ddrphy_rdly_dq_bitslip_re = 1'd0;
+wire a7ddrphy_rdly_dq_bitslip_r;
+reg a7ddrphy_rdly_dq_bitslip_we = 1'd0;
+reg a7ddrphy_rdly_dq_bitslip_w = 1'd0;
+reg a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0;
+wire a7ddrphy_wdly_dq_bitslip_rst_r;
+reg a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0;
+reg a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0;
+reg a7ddrphy_wdly_dq_bitslip_re = 1'd0;
+wire a7ddrphy_wdly_dq_bitslip_r;
+reg a7ddrphy_wdly_dq_bitslip_we = 1'd0;
+reg a7ddrphy_wdly_dq_bitslip_w = 1'd0;
+reg [1:0] a7ddrphy_rdphase_storage = 2'd2;
+reg a7ddrphy_rdphase_re = 1'd0;
+reg [1:0] a7ddrphy_wrphase_storage = 2'd3;
+reg a7ddrphy_wrphase_re = 1'd0;
+wire [15:0] a7ddrphy_dfi_p0_address;
+wire [2:0] a7ddrphy_dfi_p0_bank;
+wire a7ddrphy_dfi_p0_cas_n;
+wire a7ddrphy_dfi_p0_cs_n;
+wire a7ddrphy_dfi_p0_ras_n;
+wire a7ddrphy_dfi_p0_we_n;
+wire a7ddrphy_dfi_p0_cke;
+wire a7ddrphy_dfi_p0_odt;
+wire a7ddrphy_dfi_p0_reset_n;
+wire a7ddrphy_dfi_p0_act_n;
+wire [31:0] a7ddrphy_dfi_p0_wrdata;
+wire a7ddrphy_dfi_p0_wrdata_en;
+wire [3:0] a7ddrphy_dfi_p0_wrdata_mask;
+wire a7ddrphy_dfi_p0_rddata_en;
+reg [31:0] a7ddrphy_dfi_p0_rddata = 32'd0;
+wire a7ddrphy_dfi_p0_rddata_valid;
+wire [15:0] a7ddrphy_dfi_p1_address;
+wire [2:0] a7ddrphy_dfi_p1_bank;
+wire a7ddrphy_dfi_p1_cas_n;
+wire a7ddrphy_dfi_p1_cs_n;
+wire a7ddrphy_dfi_p1_ras_n;
+wire a7ddrphy_dfi_p1_we_n;
+wire a7ddrphy_dfi_p1_cke;
+wire a7ddrphy_dfi_p1_odt;
+wire a7ddrphy_dfi_p1_reset_n;
+wire a7ddrphy_dfi_p1_act_n;
+wire [31:0] a7ddrphy_dfi_p1_wrdata;
+wire a7ddrphy_dfi_p1_wrdata_en;
+wire [3:0] a7ddrphy_dfi_p1_wrdata_mask;
+wire a7ddrphy_dfi_p1_rddata_en;
+reg [31:0] a7ddrphy_dfi_p1_rddata = 32'd0;
+wire a7ddrphy_dfi_p1_rddata_valid;
+wire [15:0] a7ddrphy_dfi_p2_address;
+wire [2:0] a7ddrphy_dfi_p2_bank;
+wire a7ddrphy_dfi_p2_cas_n;
+wire a7ddrphy_dfi_p2_cs_n;
+wire a7ddrphy_dfi_p2_ras_n;
+wire a7ddrphy_dfi_p2_we_n;
+wire a7ddrphy_dfi_p2_cke;
+wire a7ddrphy_dfi_p2_odt;
+wire a7ddrphy_dfi_p2_reset_n;
+wire a7ddrphy_dfi_p2_act_n;
+wire [31:0] a7ddrphy_dfi_p2_wrdata;
+wire a7ddrphy_dfi_p2_wrdata_en;
+wire [3:0] a7ddrphy_dfi_p2_wrdata_mask;
+wire a7ddrphy_dfi_p2_rddata_en;
+reg [31:0] a7ddrphy_dfi_p2_rddata = 32'd0;
+wire a7ddrphy_dfi_p2_rddata_valid;
+wire [15:0] a7ddrphy_dfi_p3_address;
+wire [2:0] a7ddrphy_dfi_p3_bank;
+wire a7ddrphy_dfi_p3_cas_n;
+wire a7ddrphy_dfi_p3_cs_n;
+wire a7ddrphy_dfi_p3_ras_n;
+wire a7ddrphy_dfi_p3_we_n;
+wire a7ddrphy_dfi_p3_cke;
+wire a7ddrphy_dfi_p3_odt;
+wire a7ddrphy_dfi_p3_reset_n;
+wire a7ddrphy_dfi_p3_act_n;
+wire [31:0] a7ddrphy_dfi_p3_wrdata;
+wire a7ddrphy_dfi_p3_wrdata_en;
+wire [3:0] a7ddrphy_dfi_p3_wrdata_mask;
+wire a7ddrphy_dfi_p3_rddata_en;
+reg [31:0] a7ddrphy_dfi_p3_rddata = 32'd0;
+wire a7ddrphy_dfi_p3_rddata_valid;
+wire a7ddrphy_sd_clk_se_nodelay;
+wire [2:0] a7ddrphy_pads_ba;
+reg a7ddrphy_dqs_oe = 1'd0;
+wire a7ddrphy_dqs_preamble;
+wire a7ddrphy_dqs_postamble;
+wire a7ddrphy_dqs_oe_delay_tappeddelayline;
+reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
+reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
+reg a7ddrphy_dqspattern0 = 1'd0;
+reg a7ddrphy_dqspattern1 = 1'd0;
+reg [7:0] a7ddrphy_dqspattern_o0 = 8'd0;
+reg [7:0] a7ddrphy_dqspattern_o1 = 8'd0;
+wire a7ddrphy_dqs_o_no_delay0;
+wire a7ddrphy_dqs_t0;
+reg [7:0] a7ddrphy_bitslip00 = 8'd0;
+reg [2:0] a7ddrphy_bitslip0_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip0_r0 = 16'd0;
+wire a7ddrphy0;
+wire a7ddrphy_dqs_o_no_delay1;
+wire a7ddrphy_dqs_t1;
+reg [7:0] a7ddrphy_bitslip10 = 8'd0;
+reg [2:0] a7ddrphy_bitslip1_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip1_r0 = 16'd0;
+wire a7ddrphy1;
+reg [7:0] a7ddrphy_bitslip01 = 8'd0;
+reg [2:0] a7ddrphy_bitslip0_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip0_r1 = 16'd0;
+reg [7:0] a7ddrphy_bitslip11 = 8'd0;
+reg [2:0] a7ddrphy_bitslip1_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip1_r1 = 16'd0;
+wire a7ddrphy_dq_oe;
+wire a7ddrphy_dq_oe_delay_tappeddelayline;
+reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
+reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
+wire a7ddrphy_dq_o_nodelay0;
+wire a7ddrphy_dq_i_nodelay0;
+wire a7ddrphy_dq_i_delayed0;
+wire a7ddrphy_dq_t0;
+reg [7:0] a7ddrphy_bitslip02 = 8'd0;
+reg [2:0] a7ddrphy_bitslip0_value2 = 3'd7;
+reg [15:0] a7ddrphy_bitslip0_r2 = 16'd0;
+wire [7:0] a7ddrphy_bitslip03;
+reg [7:0] a7ddrphy_bitslip04 = 8'd0;
+reg [2:0] a7ddrphy_bitslip0_value3 = 3'd7;
+reg [15:0] a7ddrphy_bitslip0_r3 = 16'd0;
+wire a7ddrphy_dq_o_nodelay1;
+wire a7ddrphy_dq_i_nodelay1;
+wire a7ddrphy_dq_i_delayed1;
+wire a7ddrphy_dq_t1;
+reg [7:0] a7ddrphy_bitslip12 = 8'd0;
+reg [2:0] a7ddrphy_bitslip1_value2 = 3'd7;
+reg [15:0] a7ddrphy_bitslip1_r2 = 16'd0;
+wire [7:0] a7ddrphy_bitslip13;
+reg [7:0] a7ddrphy_bitslip14 = 8'd0;
+reg [2:0] a7ddrphy_bitslip1_value3 = 3'd7;
+reg [15:0] a7ddrphy_bitslip1_r3 = 16'd0;
+wire a7ddrphy_dq_o_nodelay2;
+wire a7ddrphy_dq_i_nodelay2;
+wire a7ddrphy_dq_i_delayed2;
+wire a7ddrphy_dq_t2;
+reg [7:0] a7ddrphy_bitslip20 = 8'd0;
+reg [2:0] a7ddrphy_bitslip2_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip2_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip21;
+reg [7:0] a7ddrphy_bitslip22 = 8'd0;
+reg [2:0] a7ddrphy_bitslip2_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip2_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay3;
+wire a7ddrphy_dq_i_nodelay3;
+wire a7ddrphy_dq_i_delayed3;
+wire a7ddrphy_dq_t3;
+reg [7:0] a7ddrphy_bitslip30 = 8'd0;
+reg [2:0] a7ddrphy_bitslip3_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip3_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip31;
+reg [7:0] a7ddrphy_bitslip32 = 8'd0;
+reg [2:0] a7ddrphy_bitslip3_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip3_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay4;
+wire a7ddrphy_dq_i_nodelay4;
+wire a7ddrphy_dq_i_delayed4;
+wire a7ddrphy_dq_t4;
+reg [7:0] a7ddrphy_bitslip40 = 8'd0;
+reg [2:0] a7ddrphy_bitslip4_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip4_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip41;
+reg [7:0] a7ddrphy_bitslip42 = 8'd0;
+reg [2:0] a7ddrphy_bitslip4_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip4_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay5;
+wire a7ddrphy_dq_i_nodelay5;
+wire a7ddrphy_dq_i_delayed5;
+wire a7ddrphy_dq_t5;
+reg [7:0] a7ddrphy_bitslip50 = 8'd0;
+reg [2:0] a7ddrphy_bitslip5_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip5_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip51;
+reg [7:0] a7ddrphy_bitslip52 = 8'd0;
+reg [2:0] a7ddrphy_bitslip5_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip5_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay6;
+wire a7ddrphy_dq_i_nodelay6;
+wire a7ddrphy_dq_i_delayed6;
+wire a7ddrphy_dq_t6;
+reg [7:0] a7ddrphy_bitslip60 = 8'd0;
+reg [2:0] a7ddrphy_bitslip6_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip6_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip61;
+reg [7:0] a7ddrphy_bitslip62 = 8'd0;
+reg [2:0] a7ddrphy_bitslip6_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip6_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay7;
+wire a7ddrphy_dq_i_nodelay7;
+wire a7ddrphy_dq_i_delayed7;
+wire a7ddrphy_dq_t7;
+reg [7:0] a7ddrphy_bitslip70 = 8'd0;
+reg [2:0] a7ddrphy_bitslip7_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip7_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip71;
+reg [7:0] a7ddrphy_bitslip72 = 8'd0;
+reg [2:0] a7ddrphy_bitslip7_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip7_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay8;
+wire a7ddrphy_dq_i_nodelay8;
+wire a7ddrphy_dq_i_delayed8;
+wire a7ddrphy_dq_t8;
+reg [7:0] a7ddrphy_bitslip80 = 8'd0;
+reg [2:0] a7ddrphy_bitslip8_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip8_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip81;
+reg [7:0] a7ddrphy_bitslip82 = 8'd0;
+reg [2:0] a7ddrphy_bitslip8_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip8_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay9;
+wire a7ddrphy_dq_i_nodelay9;
+wire a7ddrphy_dq_i_delayed9;
+wire a7ddrphy_dq_t9;
+reg [7:0] a7ddrphy_bitslip90 = 8'd0;
+reg [2:0] a7ddrphy_bitslip9_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip9_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip91;
+reg [7:0] a7ddrphy_bitslip92 = 8'd0;
+reg [2:0] a7ddrphy_bitslip9_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip9_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay10;
+wire a7ddrphy_dq_i_nodelay10;
+wire a7ddrphy_dq_i_delayed10;
+wire a7ddrphy_dq_t10;
+reg [7:0] a7ddrphy_bitslip100 = 8'd0;
+reg [2:0] a7ddrphy_bitslip10_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip10_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip101;
+reg [7:0] a7ddrphy_bitslip102 = 8'd0;
+reg [2:0] a7ddrphy_bitslip10_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip10_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay11;
+wire a7ddrphy_dq_i_nodelay11;
+wire a7ddrphy_dq_i_delayed11;
+wire a7ddrphy_dq_t11;
+reg [7:0] a7ddrphy_bitslip110 = 8'd0;
+reg [2:0] a7ddrphy_bitslip11_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip11_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip111;
+reg [7:0] a7ddrphy_bitslip112 = 8'd0;
+reg [2:0] a7ddrphy_bitslip11_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip11_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay12;
+wire a7ddrphy_dq_i_nodelay12;
+wire a7ddrphy_dq_i_delayed12;
+wire a7ddrphy_dq_t12;
+reg [7:0] a7ddrphy_bitslip120 = 8'd0;
+reg [2:0] a7ddrphy_bitslip12_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip12_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip121;
+reg [7:0] a7ddrphy_bitslip122 = 8'd0;
+reg [2:0] a7ddrphy_bitslip12_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip12_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay13;
+wire a7ddrphy_dq_i_nodelay13;
+wire a7ddrphy_dq_i_delayed13;
+wire a7ddrphy_dq_t13;
+reg [7:0] a7ddrphy_bitslip130 = 8'd0;
+reg [2:0] a7ddrphy_bitslip13_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip13_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip131;
+reg [7:0] a7ddrphy_bitslip132 = 8'd0;
+reg [2:0] a7ddrphy_bitslip13_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip13_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay14;
+wire a7ddrphy_dq_i_nodelay14;
+wire a7ddrphy_dq_i_delayed14;
+wire a7ddrphy_dq_t14;
+reg [7:0] a7ddrphy_bitslip140 = 8'd0;
+reg [2:0] a7ddrphy_bitslip14_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip14_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip141;
+reg [7:0] a7ddrphy_bitslip142 = 8'd0;
+reg [2:0] a7ddrphy_bitslip14_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip14_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay15;
+wire a7ddrphy_dq_i_nodelay15;
+wire a7ddrphy_dq_i_delayed15;
+wire a7ddrphy_dq_t15;
+reg [7:0] a7ddrphy_bitslip150 = 8'd0;
+reg [2:0] a7ddrphy_bitslip15_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip15_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip151;
+reg [7:0] a7ddrphy_bitslip152 = 8'd0;
+reg [2:0] a7ddrphy_bitslip15_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip15_r1 = 16'd0;
+reg a7ddrphy_rddata_en_tappeddelayline0 = 1'd0;
+reg a7ddrphy_rddata_en_tappeddelayline1 = 1'd0;
+reg a7ddrphy_rddata_en_tappeddelayline2 = 1'd0;
+reg a7ddrphy_rddata_en_tappeddelayline3 = 1'd0;
+reg a7ddrphy_rddata_en_tappeddelayline4 = 1'd0;
+reg a7ddrphy_rddata_en_tappeddelayline5 = 1'd0;
+reg a7ddrphy_rddata_en_tappeddelayline6 = 1'd0;
+reg a7ddrphy_rddata_en_tappeddelayline7 = 1'd0;
+reg a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
+reg a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
+reg a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
+wire [15:0] litedramcore_slave_p0_address;
+wire [2:0] litedramcore_slave_p0_bank;
+wire litedramcore_slave_p0_cas_n;
+wire litedramcore_slave_p0_cs_n;
+wire litedramcore_slave_p0_ras_n;
+wire litedramcore_slave_p0_we_n;
+wire litedramcore_slave_p0_cke;
+wire litedramcore_slave_p0_odt;
+wire litedramcore_slave_p0_reset_n;
+wire litedramcore_slave_p0_act_n;
+wire [31:0] litedramcore_slave_p0_wrdata;
+wire litedramcore_slave_p0_wrdata_en;
+wire [3:0] litedramcore_slave_p0_wrdata_mask;
+wire litedramcore_slave_p0_rddata_en;
+reg [31:0] litedramcore_slave_p0_rddata = 32'd0;
+reg litedramcore_slave_p0_rddata_valid = 1'd0;
+wire [15:0] litedramcore_slave_p1_address;
+wire [2:0] litedramcore_slave_p1_bank;
+wire litedramcore_slave_p1_cas_n;
+wire litedramcore_slave_p1_cs_n;
+wire litedramcore_slave_p1_ras_n;
+wire litedramcore_slave_p1_we_n;
+wire litedramcore_slave_p1_cke;
+wire litedramcore_slave_p1_odt;
+wire litedramcore_slave_p1_reset_n;
+wire litedramcore_slave_p1_act_n;
+wire [31:0] litedramcore_slave_p1_wrdata;
+wire litedramcore_slave_p1_wrdata_en;
+wire [3:0] litedramcore_slave_p1_wrdata_mask;
+wire litedramcore_slave_p1_rddata_en;
+reg [31:0] litedramcore_slave_p1_rddata = 32'd0;
+reg litedramcore_slave_p1_rddata_valid = 1'd0;
+wire [15:0] litedramcore_slave_p2_address;
+wire [2:0] litedramcore_slave_p2_bank;
+wire litedramcore_slave_p2_cas_n;
+wire litedramcore_slave_p2_cs_n;
+wire litedramcore_slave_p2_ras_n;
+wire litedramcore_slave_p2_we_n;
+wire litedramcore_slave_p2_cke;
+wire litedramcore_slave_p2_odt;
+wire litedramcore_slave_p2_reset_n;
+wire litedramcore_slave_p2_act_n;
+wire [31:0] litedramcore_slave_p2_wrdata;
+wire litedramcore_slave_p2_wrdata_en;
+wire [3:0] litedramcore_slave_p2_wrdata_mask;
+wire litedramcore_slave_p2_rddata_en;
+reg [31:0] litedramcore_slave_p2_rddata = 32'd0;
+reg litedramcore_slave_p2_rddata_valid = 1'd0;
+wire [15:0] litedramcore_slave_p3_address;
+wire [2:0] litedramcore_slave_p3_bank;
+wire litedramcore_slave_p3_cas_n;
+wire litedramcore_slave_p3_cs_n;
+wire litedramcore_slave_p3_ras_n;
+wire litedramcore_slave_p3_we_n;
+wire litedramcore_slave_p3_cke;
+wire litedramcore_slave_p3_odt;
+wire litedramcore_slave_p3_reset_n;
+wire litedramcore_slave_p3_act_n;
+wire [31:0] litedramcore_slave_p3_wrdata;
+wire litedramcore_slave_p3_wrdata_en;
+wire [3:0] litedramcore_slave_p3_wrdata_mask;
+wire litedramcore_slave_p3_rddata_en;
+reg [31:0] litedramcore_slave_p3_rddata = 32'd0;
+reg litedramcore_slave_p3_rddata_valid = 1'd0;
+reg [15:0] litedramcore_master_p0_address = 16'd0;
+reg [2:0] litedramcore_master_p0_bank = 3'd0;
+reg litedramcore_master_p0_cas_n = 1'd1;
+reg litedramcore_master_p0_cs_n = 1'd1;
+reg litedramcore_master_p0_ras_n = 1'd1;
+reg litedramcore_master_p0_we_n = 1'd1;
+reg litedramcore_master_p0_cke = 1'd0;
+reg litedramcore_master_p0_odt = 1'd0;
+reg litedramcore_master_p0_reset_n = 1'd0;
+reg litedramcore_master_p0_act_n = 1'd1;
+reg [31:0] litedramcore_master_p0_wrdata = 32'd0;
+reg litedramcore_master_p0_wrdata_en = 1'd0;
+reg [3:0] litedramcore_master_p0_wrdata_mask = 4'd0;
+reg litedramcore_master_p0_rddata_en = 1'd0;
+wire [31:0] litedramcore_master_p0_rddata;
+wire litedramcore_master_p0_rddata_valid;
+reg [15:0] litedramcore_master_p1_address = 16'd0;
+reg [2:0] litedramcore_master_p1_bank = 3'd0;
+reg litedramcore_master_p1_cas_n = 1'd1;
+reg litedramcore_master_p1_cs_n = 1'd1;
+reg litedramcore_master_p1_ras_n = 1'd1;
+reg litedramcore_master_p1_we_n = 1'd1;
+reg litedramcore_master_p1_cke = 1'd0;
+reg litedramcore_master_p1_odt = 1'd0;
+reg litedramcore_master_p1_reset_n = 1'd0;
+reg litedramcore_master_p1_act_n = 1'd1;
+reg [31:0] litedramcore_master_p1_wrdata = 32'd0;
+reg litedramcore_master_p1_wrdata_en = 1'd0;
+reg [3:0] litedramcore_master_p1_wrdata_mask = 4'd0;
+reg litedramcore_master_p1_rddata_en = 1'd0;
+wire [31:0] litedramcore_master_p1_rddata;
+wire litedramcore_master_p1_rddata_valid;
+reg [15:0] litedramcore_master_p2_address = 16'd0;
+reg [2:0] litedramcore_master_p2_bank = 3'd0;
+reg litedramcore_master_p2_cas_n = 1'd1;
+reg litedramcore_master_p2_cs_n = 1'd1;
+reg litedramcore_master_p2_ras_n = 1'd1;
+reg litedramcore_master_p2_we_n = 1'd1;
+reg litedramcore_master_p2_cke = 1'd0;
+reg litedramcore_master_p2_odt = 1'd0;
+reg litedramcore_master_p2_reset_n = 1'd0;
+reg litedramcore_master_p2_act_n = 1'd1;
+reg [31:0] litedramcore_master_p2_wrdata = 32'd0;
+reg litedramcore_master_p2_wrdata_en = 1'd0;
+reg [3:0] litedramcore_master_p2_wrdata_mask = 4'd0;
+reg litedramcore_master_p2_rddata_en = 1'd0;
+wire [31:0] litedramcore_master_p2_rddata;
+wire litedramcore_master_p2_rddata_valid;
+reg [15:0] litedramcore_master_p3_address = 16'd0;
+reg [2:0] litedramcore_master_p3_bank = 3'd0;
+reg litedramcore_master_p3_cas_n = 1'd1;
+reg litedramcore_master_p3_cs_n = 1'd1;
+reg litedramcore_master_p3_ras_n = 1'd1;
+reg litedramcore_master_p3_we_n = 1'd1;
+reg litedramcore_master_p3_cke = 1'd0;
+reg litedramcore_master_p3_odt = 1'd0;
+reg litedramcore_master_p3_reset_n = 1'd0;
+reg litedramcore_master_p3_act_n = 1'd1;
+reg [31:0] litedramcore_master_p3_wrdata = 32'd0;
+reg litedramcore_master_p3_wrdata_en = 1'd0;
+reg [3:0] litedramcore_master_p3_wrdata_mask = 4'd0;
+reg litedramcore_master_p3_rddata_en = 1'd0;
+wire [31:0] litedramcore_master_p3_rddata;
+wire litedramcore_master_p3_rddata_valid;
+wire [15:0] litedramcore_csr_dfi_p0_address;
+wire [2:0] litedramcore_csr_dfi_p0_bank;
+reg litedramcore_csr_dfi_p0_cas_n = 1'd1;
+reg litedramcore_csr_dfi_p0_cs_n = 1'd1;
+reg litedramcore_csr_dfi_p0_ras_n = 1'd1;
+reg litedramcore_csr_dfi_p0_we_n = 1'd1;
+wire litedramcore_csr_dfi_p0_cke;
+wire litedramcore_csr_dfi_p0_odt;
+wire litedramcore_csr_dfi_p0_reset_n;
+reg litedramcore_csr_dfi_p0_act_n = 1'd1;
+wire [31:0] litedramcore_csr_dfi_p0_wrdata;
+wire litedramcore_csr_dfi_p0_wrdata_en;
+wire [3:0] litedramcore_csr_dfi_p0_wrdata_mask;
+wire litedramcore_csr_dfi_p0_rddata_en;
+reg [31:0] litedramcore_csr_dfi_p0_rddata = 32'd0;
+reg litedramcore_csr_dfi_p0_rddata_valid = 1'd0;
+wire [15:0] litedramcore_csr_dfi_p1_address;
+wire [2:0] litedramcore_csr_dfi_p1_bank;
+reg litedramcore_csr_dfi_p1_cas_n = 1'd1;
+reg litedramcore_csr_dfi_p1_cs_n = 1'd1;
+reg litedramcore_csr_dfi_p1_ras_n = 1'd1;
+reg litedramcore_csr_dfi_p1_we_n = 1'd1;
+wire litedramcore_csr_dfi_p1_cke;
+wire litedramcore_csr_dfi_p1_odt;
+wire litedramcore_csr_dfi_p1_reset_n;
+reg litedramcore_csr_dfi_p1_act_n = 1'd1;
+wire [31:0] litedramcore_csr_dfi_p1_wrdata;
+wire litedramcore_csr_dfi_p1_wrdata_en;
+wire [3:0] litedramcore_csr_dfi_p1_wrdata_mask;
+wire litedramcore_csr_dfi_p1_rddata_en;
+reg [31:0] litedramcore_csr_dfi_p1_rddata = 32'd0;
+reg litedramcore_csr_dfi_p1_rddata_valid = 1'd0;
+wire [15:0] litedramcore_csr_dfi_p2_address;
+wire [2:0] litedramcore_csr_dfi_p2_bank;
+reg litedramcore_csr_dfi_p2_cas_n = 1'd1;
+reg litedramcore_csr_dfi_p2_cs_n = 1'd1;
+reg litedramcore_csr_dfi_p2_ras_n = 1'd1;
+reg litedramcore_csr_dfi_p2_we_n = 1'd1;
+wire litedramcore_csr_dfi_p2_cke;
+wire litedramcore_csr_dfi_p2_odt;
+wire litedramcore_csr_dfi_p2_reset_n;
+reg litedramcore_csr_dfi_p2_act_n = 1'd1;
+wire [31:0] litedramcore_csr_dfi_p2_wrdata;
+wire litedramcore_csr_dfi_p2_wrdata_en;
+wire [3:0] litedramcore_csr_dfi_p2_wrdata_mask;
+wire litedramcore_csr_dfi_p2_rddata_en;
+reg [31:0] litedramcore_csr_dfi_p2_rddata = 32'd0;
+reg litedramcore_csr_dfi_p2_rddata_valid = 1'd0;
+wire [15:0] litedramcore_csr_dfi_p3_address;
+wire [2:0] litedramcore_csr_dfi_p3_bank;
+reg litedramcore_csr_dfi_p3_cas_n = 1'd1;
+reg litedramcore_csr_dfi_p3_cs_n = 1'd1;
+reg litedramcore_csr_dfi_p3_ras_n = 1'd1;
+reg litedramcore_csr_dfi_p3_we_n = 1'd1;
+wire litedramcore_csr_dfi_p3_cke;
+wire litedramcore_csr_dfi_p3_odt;
+wire litedramcore_csr_dfi_p3_reset_n;
+reg litedramcore_csr_dfi_p3_act_n = 1'd1;
+wire [31:0] litedramcore_csr_dfi_p3_wrdata;
+wire litedramcore_csr_dfi_p3_wrdata_en;
+wire [3:0] litedramcore_csr_dfi_p3_wrdata_mask;
+wire litedramcore_csr_dfi_p3_rddata_en;
+reg [31:0] litedramcore_csr_dfi_p3_rddata = 32'd0;
+reg litedramcore_csr_dfi_p3_rddata_valid = 1'd0;
+reg [15:0] litedramcore_ext_dfi_p0_address = 16'd0;
+reg [2:0] litedramcore_ext_dfi_p0_bank = 3'd0;
+reg litedramcore_ext_dfi_p0_cas_n = 1'd1;
+reg litedramcore_ext_dfi_p0_cs_n = 1'd1;
+reg litedramcore_ext_dfi_p0_ras_n = 1'd1;
+reg litedramcore_ext_dfi_p0_we_n = 1'd1;
+reg litedramcore_ext_dfi_p0_cke = 1'd0;
+reg litedramcore_ext_dfi_p0_odt = 1'd0;
+reg litedramcore_ext_dfi_p0_reset_n = 1'd0;
+reg litedramcore_ext_dfi_p0_act_n = 1'd1;
+reg [31:0] litedramcore_ext_dfi_p0_wrdata = 32'd0;
+reg litedramcore_ext_dfi_p0_wrdata_en = 1'd0;
+reg [3:0] litedramcore_ext_dfi_p0_wrdata_mask = 4'd0;
+reg litedramcore_ext_dfi_p0_rddata_en = 1'd0;
+reg [31:0] litedramcore_ext_dfi_p0_rddata = 32'd0;
+reg litedramcore_ext_dfi_p0_rddata_valid = 1'd0;
+reg [15:0] litedramcore_ext_dfi_p1_address = 16'd0;
+reg [2:0] litedramcore_ext_dfi_p1_bank = 3'd0;
+reg litedramcore_ext_dfi_p1_cas_n = 1'd1;
+reg litedramcore_ext_dfi_p1_cs_n = 1'd1;
+reg litedramcore_ext_dfi_p1_ras_n = 1'd1;
+reg litedramcore_ext_dfi_p1_we_n = 1'd1;
+reg litedramcore_ext_dfi_p1_cke = 1'd0;
+reg litedramcore_ext_dfi_p1_odt = 1'd0;
+reg litedramcore_ext_dfi_p1_reset_n = 1'd0;
+reg litedramcore_ext_dfi_p1_act_n = 1'd1;
+reg [31:0] litedramcore_ext_dfi_p1_wrdata = 32'd0;
+reg litedramcore_ext_dfi_p1_wrdata_en = 1'd0;
+reg [3:0] litedramcore_ext_dfi_p1_wrdata_mask = 4'd0;
+reg litedramcore_ext_dfi_p1_rddata_en = 1'd0;
+reg [31:0] litedramcore_ext_dfi_p1_rddata = 32'd0;
+reg litedramcore_ext_dfi_p1_rddata_valid = 1'd0;
+reg [15:0] litedramcore_ext_dfi_p2_address = 16'd0;
+reg [2:0] litedramcore_ext_dfi_p2_bank = 3'd0;
+reg litedramcore_ext_dfi_p2_cas_n = 1'd1;
+reg litedramcore_ext_dfi_p2_cs_n = 1'd1;
+reg litedramcore_ext_dfi_p2_ras_n = 1'd1;
+reg litedramcore_ext_dfi_p2_we_n = 1'd1;
+reg litedramcore_ext_dfi_p2_cke = 1'd0;
+reg litedramcore_ext_dfi_p2_odt = 1'd0;
+reg litedramcore_ext_dfi_p2_reset_n = 1'd0;
+reg litedramcore_ext_dfi_p2_act_n = 1'd1;
+reg [31:0] litedramcore_ext_dfi_p2_wrdata = 32'd0;
+reg litedramcore_ext_dfi_p2_wrdata_en = 1'd0;
+reg [3:0] litedramcore_ext_dfi_p2_wrdata_mask = 4'd0;
+reg litedramcore_ext_dfi_p2_rddata_en = 1'd0;
+reg [31:0] litedramcore_ext_dfi_p2_rddata = 32'd0;
+reg litedramcore_ext_dfi_p2_rddata_valid = 1'd0;
+reg [15:0] litedramcore_ext_dfi_p3_address = 16'd0;
+reg [2:0] litedramcore_ext_dfi_p3_bank = 3'd0;
+reg litedramcore_ext_dfi_p3_cas_n = 1'd1;
+reg litedramcore_ext_dfi_p3_cs_n = 1'd1;
+reg litedramcore_ext_dfi_p3_ras_n = 1'd1;
+reg litedramcore_ext_dfi_p3_we_n = 1'd1;
+reg litedramcore_ext_dfi_p3_cke = 1'd0;
+reg litedramcore_ext_dfi_p3_odt = 1'd0;
+reg litedramcore_ext_dfi_p3_reset_n = 1'd0;
+reg litedramcore_ext_dfi_p3_act_n = 1'd1;
+reg [31:0] litedramcore_ext_dfi_p3_wrdata = 32'd0;
+reg litedramcore_ext_dfi_p3_wrdata_en = 1'd0;
+reg [3:0] litedramcore_ext_dfi_p3_wrdata_mask = 4'd0;
+reg litedramcore_ext_dfi_p3_rddata_en = 1'd0;
+reg [31:0] litedramcore_ext_dfi_p3_rddata = 32'd0;
+reg litedramcore_ext_dfi_p3_rddata_valid = 1'd0;
+reg litedramcore_ext_dfi_sel = 1'd0;
+wire litedramcore_sel;
+wire litedramcore_cke;
+wire litedramcore_odt;
+wire litedramcore_reset_n;
+reg [3:0] litedramcore_storage = 4'd1;
+reg litedramcore_re = 1'd0;
+wire litedramcore_phaseinjector0_csrfield_cs;
+wire litedramcore_phaseinjector0_csrfield_we;
+wire litedramcore_phaseinjector0_csrfield_cas;
+wire litedramcore_phaseinjector0_csrfield_ras;
+wire litedramcore_phaseinjector0_csrfield_wren;
+wire litedramcore_phaseinjector0_csrfield_rden;
+reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0;
+reg litedramcore_phaseinjector0_command_re = 1'd0;
+reg litedramcore_phaseinjector0_command_issue_re = 1'd0;
+wire litedramcore_phaseinjector0_command_issue_r;
+reg litedramcore_phaseinjector0_command_issue_we = 1'd0;
+reg litedramcore_phaseinjector0_command_issue_w = 1'd0;
+reg [15:0] litedramcore_phaseinjector0_address_storage = 16'd0;
+reg litedramcore_phaseinjector0_address_re = 1'd0;
+reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0;
+reg litedramcore_phaseinjector0_baddress_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector0_wrdata_storage = 32'd0;
+reg litedramcore_phaseinjector0_wrdata_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector0_rddata_status = 32'd0;
+wire litedramcore_phaseinjector0_rddata_we;
+reg litedramcore_phaseinjector0_rddata_re = 1'd0;
+wire litedramcore_phaseinjector1_csrfield_cs;
+wire litedramcore_phaseinjector1_csrfield_we;
+wire litedramcore_phaseinjector1_csrfield_cas;
+wire litedramcore_phaseinjector1_csrfield_ras;
+wire litedramcore_phaseinjector1_csrfield_wren;
+wire litedramcore_phaseinjector1_csrfield_rden;
+reg [5:0] litedramcore_phaseinjector1_command_storage = 6'd0;
+reg litedramcore_phaseinjector1_command_re = 1'd0;
+reg litedramcore_phaseinjector1_command_issue_re = 1'd0;
+wire litedramcore_phaseinjector1_command_issue_r;
+reg litedramcore_phaseinjector1_command_issue_we = 1'd0;
+reg litedramcore_phaseinjector1_command_issue_w = 1'd0;
+reg [15:0] litedramcore_phaseinjector1_address_storage = 16'd0;
+reg litedramcore_phaseinjector1_address_re = 1'd0;
+reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0;
+reg litedramcore_phaseinjector1_baddress_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector1_wrdata_storage = 32'd0;
+reg litedramcore_phaseinjector1_wrdata_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector1_rddata_status = 32'd0;
+wire litedramcore_phaseinjector1_rddata_we;
+reg litedramcore_phaseinjector1_rddata_re = 1'd0;
+wire litedramcore_phaseinjector2_csrfield_cs;
+wire litedramcore_phaseinjector2_csrfield_we;
+wire litedramcore_phaseinjector2_csrfield_cas;
+wire litedramcore_phaseinjector2_csrfield_ras;
+wire litedramcore_phaseinjector2_csrfield_wren;
+wire litedramcore_phaseinjector2_csrfield_rden;
+reg [5:0] litedramcore_phaseinjector2_command_storage = 6'd0;
+reg litedramcore_phaseinjector2_command_re = 1'd0;
+reg litedramcore_phaseinjector2_command_issue_re = 1'd0;
+wire litedramcore_phaseinjector2_command_issue_r;
+reg litedramcore_phaseinjector2_command_issue_we = 1'd0;
+reg litedramcore_phaseinjector2_command_issue_w = 1'd0;
+reg [15:0] litedramcore_phaseinjector2_address_storage = 16'd0;
+reg litedramcore_phaseinjector2_address_re = 1'd0;
+reg [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0;
+reg litedramcore_phaseinjector2_baddress_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector2_wrdata_storage = 32'd0;
+reg litedramcore_phaseinjector2_wrdata_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector2_rddata_status = 32'd0;
+wire litedramcore_phaseinjector2_rddata_we;
+reg litedramcore_phaseinjector2_rddata_re = 1'd0;
+wire litedramcore_phaseinjector3_csrfield_cs;
+wire litedramcore_phaseinjector3_csrfield_we;
+wire litedramcore_phaseinjector3_csrfield_cas;
+wire litedramcore_phaseinjector3_csrfield_ras;
+wire litedramcore_phaseinjector3_csrfield_wren;
+wire litedramcore_phaseinjector3_csrfield_rden;
+reg [5:0] litedramcore_phaseinjector3_command_storage = 6'd0;
+reg litedramcore_phaseinjector3_command_re = 1'd0;
+reg litedramcore_phaseinjector3_command_issue_re = 1'd0;
+wire litedramcore_phaseinjector3_command_issue_r;
+reg litedramcore_phaseinjector3_command_issue_we = 1'd0;
+reg litedramcore_phaseinjector3_command_issue_w = 1'd0;
+reg [15:0] litedramcore_phaseinjector3_address_storage = 16'd0;
+reg litedramcore_phaseinjector3_address_re = 1'd0;
+reg [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0;
+reg litedramcore_phaseinjector3_baddress_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector3_wrdata_storage = 32'd0;
+reg litedramcore_phaseinjector3_wrdata_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector3_rddata_status = 32'd0;
+wire litedramcore_phaseinjector3_rddata_we;
+reg litedramcore_phaseinjector3_rddata_re = 1'd0;
+wire litedramcore_interface_bank0_valid;
+wire litedramcore_interface_bank0_ready;
+wire litedramcore_interface_bank0_we;
+wire [22:0] litedramcore_interface_bank0_addr;
+wire litedramcore_interface_bank0_lock;
+wire litedramcore_interface_bank0_wdata_ready;
+wire litedramcore_interface_bank0_rdata_valid;
+wire litedramcore_interface_bank1_valid;
+wire litedramcore_interface_bank1_ready;
+wire litedramcore_interface_bank1_we;
+wire [22:0] litedramcore_interface_bank1_addr;
+wire litedramcore_interface_bank1_lock;
+wire litedramcore_interface_bank1_wdata_ready;
+wire litedramcore_interface_bank1_rdata_valid;
+wire litedramcore_interface_bank2_valid;
+wire litedramcore_interface_bank2_ready;
+wire litedramcore_interface_bank2_we;
+wire [22:0] litedramcore_interface_bank2_addr;
+wire litedramcore_interface_bank2_lock;
+wire litedramcore_interface_bank2_wdata_ready;
+wire litedramcore_interface_bank2_rdata_valid;
+wire litedramcore_interface_bank3_valid;
+wire litedramcore_interface_bank3_ready;
+wire litedramcore_interface_bank3_we;
+wire [22:0] litedramcore_interface_bank3_addr;
+wire litedramcore_interface_bank3_lock;
+wire litedramcore_interface_bank3_wdata_ready;
+wire litedramcore_interface_bank3_rdata_valid;
+wire litedramcore_interface_bank4_valid;
+wire litedramcore_interface_bank4_ready;
+wire litedramcore_interface_bank4_we;
+wire [22:0] litedramcore_interface_bank4_addr;
+wire litedramcore_interface_bank4_lock;
+wire litedramcore_interface_bank4_wdata_ready;
+wire litedramcore_interface_bank4_rdata_valid;
+wire litedramcore_interface_bank5_valid;
+wire litedramcore_interface_bank5_ready;
+wire litedramcore_interface_bank5_we;
+wire [22:0] litedramcore_interface_bank5_addr;
+wire litedramcore_interface_bank5_lock;
+wire litedramcore_interface_bank5_wdata_ready;
+wire litedramcore_interface_bank5_rdata_valid;
+wire litedramcore_interface_bank6_valid;
+wire litedramcore_interface_bank6_ready;
+wire litedramcore_interface_bank6_we;
+wire [22:0] litedramcore_interface_bank6_addr;
+wire litedramcore_interface_bank6_lock;
+wire litedramcore_interface_bank6_wdata_ready;
+wire litedramcore_interface_bank6_rdata_valid;
+wire litedramcore_interface_bank7_valid;
+wire litedramcore_interface_bank7_ready;
+wire litedramcore_interface_bank7_we;
+wire [22:0] litedramcore_interface_bank7_addr;
+wire litedramcore_interface_bank7_lock;
+wire litedramcore_interface_bank7_wdata_ready;
+wire litedramcore_interface_bank7_rdata_valid;
+reg [127:0] litedramcore_interface_wdata = 128'd0;
+reg [15:0] litedramcore_interface_wdata_we = 16'd0;
+wire [127:0] litedramcore_interface_rdata;
+reg [15:0] litedramcore_dfi_p0_address = 16'd0;
+reg [2:0] litedramcore_dfi_p0_bank = 3'd0;
+reg litedramcore_dfi_p0_cas_n = 1'd1;
+reg litedramcore_dfi_p0_cs_n = 1'd1;
+reg litedramcore_dfi_p0_ras_n = 1'd1;
+reg litedramcore_dfi_p0_we_n = 1'd1;
+wire litedramcore_dfi_p0_cke;
+wire litedramcore_dfi_p0_odt;
+wire litedramcore_dfi_p0_reset_n;
+reg litedramcore_dfi_p0_act_n = 1'd1;
+wire [31:0] litedramcore_dfi_p0_wrdata;
+reg litedramcore_dfi_p0_wrdata_en = 1'd0;
+wire [3:0] litedramcore_dfi_p0_wrdata_mask;
+reg litedramcore_dfi_p0_rddata_en = 1'd0;
+wire [31:0] litedramcore_dfi_p0_rddata;
+wire litedramcore_dfi_p0_rddata_valid;
+reg [15:0] litedramcore_dfi_p1_address = 16'd0;
+reg [2:0] litedramcore_dfi_p1_bank = 3'd0;
+reg litedramcore_dfi_p1_cas_n = 1'd1;
+reg litedramcore_dfi_p1_cs_n = 1'd1;
+reg litedramcore_dfi_p1_ras_n = 1'd1;
+reg litedramcore_dfi_p1_we_n = 1'd1;
+wire litedramcore_dfi_p1_cke;
+wire litedramcore_dfi_p1_odt;
+wire litedramcore_dfi_p1_reset_n;
+reg litedramcore_dfi_p1_act_n = 1'd1;
+wire [31:0] litedramcore_dfi_p1_wrdata;
+reg litedramcore_dfi_p1_wrdata_en = 1'd0;
+wire [3:0] litedramcore_dfi_p1_wrdata_mask;
+reg litedramcore_dfi_p1_rddata_en = 1'd0;
+wire [31:0] litedramcore_dfi_p1_rddata;
+wire litedramcore_dfi_p1_rddata_valid;
+reg [15:0] litedramcore_dfi_p2_address = 16'd0;
+reg [2:0] litedramcore_dfi_p2_bank = 3'd0;
+reg litedramcore_dfi_p2_cas_n = 1'd1;
+reg litedramcore_dfi_p2_cs_n = 1'd1;
+reg litedramcore_dfi_p2_ras_n = 1'd1;
+reg litedramcore_dfi_p2_we_n = 1'd1;
+wire litedramcore_dfi_p2_cke;
+wire litedramcore_dfi_p2_odt;
+wire litedramcore_dfi_p2_reset_n;
+reg litedramcore_dfi_p2_act_n = 1'd1;
+wire [31:0] litedramcore_dfi_p2_wrdata;
+reg litedramcore_dfi_p2_wrdata_en = 1'd0;
+wire [3:0] litedramcore_dfi_p2_wrdata_mask;
+reg litedramcore_dfi_p2_rddata_en = 1'd0;
+wire [31:0] litedramcore_dfi_p2_rddata;
+wire litedramcore_dfi_p2_rddata_valid;
+reg [15:0] litedramcore_dfi_p3_address = 16'd0;
+reg [2:0] litedramcore_dfi_p3_bank = 3'd0;
+reg litedramcore_dfi_p3_cas_n = 1'd1;
+reg litedramcore_dfi_p3_cs_n = 1'd1;
+reg litedramcore_dfi_p3_ras_n = 1'd1;
+reg litedramcore_dfi_p3_we_n = 1'd1;
+wire litedramcore_dfi_p3_cke;
+wire litedramcore_dfi_p3_odt;
+wire litedramcore_dfi_p3_reset_n;
+reg litedramcore_dfi_p3_act_n = 1'd1;
+wire [31:0] litedramcore_dfi_p3_wrdata;
+reg litedramcore_dfi_p3_wrdata_en = 1'd0;
+wire [3:0] litedramcore_dfi_p3_wrdata_mask;
+reg litedramcore_dfi_p3_rddata_en = 1'd0;
+wire [31:0] litedramcore_dfi_p3_rddata;
+wire litedramcore_dfi_p3_rddata_valid;
+reg litedramcore_cmd_valid = 1'd0;
+reg litedramcore_cmd_ready = 1'd0;
+reg litedramcore_cmd_last = 1'd0;
+reg [15:0] litedramcore_cmd_payload_a = 16'd0;
+reg [2:0] litedramcore_cmd_payload_ba = 3'd0;
+reg litedramcore_cmd_payload_cas = 1'd0;
+reg litedramcore_cmd_payload_ras = 1'd0;
+reg litedramcore_cmd_payload_we = 1'd0;
+reg litedramcore_cmd_payload_is_read = 1'd0;
+reg litedramcore_cmd_payload_is_write = 1'd0;
+wire litedramcore_wants_refresh;
+wire litedramcore_wants_zqcs;
+wire litedramcore_timer_wait;
+wire litedramcore_timer_done0;
+wire [9:0] litedramcore_timer_count0;
+wire litedramcore_timer_done1;
+reg [9:0] litedramcore_timer_count1 = 10'd781;
+wire litedramcore_postponer_req_i;
+reg litedramcore_postponer_req_o = 1'd0;
+reg litedramcore_postponer_count = 1'd0;
+reg litedramcore_sequencer_start0 = 1'd0;
+wire litedramcore_sequencer_done0;
+wire litedramcore_sequencer_start1;
+reg litedramcore_sequencer_done1 = 1'd0;
+reg [6:0] litedramcore_sequencer_counter = 7'd0;
+reg litedramcore_sequencer_count = 1'd0;
+wire litedramcore_zqcs_timer_wait;
+wire litedramcore_zqcs_timer_done0;
+wire [26:0] litedramcore_zqcs_timer_count0;
+wire litedramcore_zqcs_timer_done1;
+reg [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999;
+reg litedramcore_zqcs_executer_start = 1'd0;
+reg litedramcore_zqcs_executer_done = 1'd0;
+reg [4:0] litedramcore_zqcs_executer_counter = 5'd0;
+wire litedramcore_bankmachine0_req_valid;
+wire litedramcore_bankmachine0_req_ready;
+wire litedramcore_bankmachine0_req_we;
+wire [22:0] litedramcore_bankmachine0_req_addr;
+wire litedramcore_bankmachine0_req_lock;
+reg litedramcore_bankmachine0_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine0_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine0_refresh_req;
+reg litedramcore_bankmachine0_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine0_cmd_valid = 1'd0;
+reg litedramcore_bankmachine0_cmd_ready = 1'd0;
+reg [15:0] litedramcore_bankmachine0_cmd_payload_a = 16'd0;
+wire [2:0] litedramcore_bankmachine0_cmd_payload_ba;
+reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine0_auto_precharge = 1'd0;
+wire litedramcore_bankmachine0_sink_valid;
+wire litedramcore_bankmachine0_sink_ready;
+reg litedramcore_bankmachine0_sink_first = 1'd0;
+reg litedramcore_bankmachine0_sink_last = 1'd0;
+wire litedramcore_bankmachine0_sink_payload_we;
+wire [22:0] litedramcore_bankmachine0_sink_payload_addr;
+wire litedramcore_bankmachine0_source_valid;
+wire litedramcore_bankmachine0_source_ready;
+wire litedramcore_bankmachine0_source_first;
+wire litedramcore_bankmachine0_source_last;
+wire litedramcore_bankmachine0_source_payload_we;
+wire [22:0] litedramcore_bankmachine0_source_payload_addr;
+wire litedramcore_bankmachine0_syncfifo0_we;
+wire litedramcore_bankmachine0_syncfifo0_writable;
+wire litedramcore_bankmachine0_syncfifo0_re;
+wire litedramcore_bankmachine0_syncfifo0_readable;
+wire [25:0] litedramcore_bankmachine0_syncfifo0_din;
+wire [25:0] litedramcore_bankmachine0_syncfifo0_dout;
+reg [4:0] litedramcore_bankmachine0_level = 5'd0;
+reg litedramcore_bankmachine0_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine0_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine0_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine0_wrport_adr = 4'd0;
+wire [25:0] litedramcore_bankmachine0_wrport_dat_r;
+wire litedramcore_bankmachine0_wrport_we;
+wire [25:0] litedramcore_bankmachine0_wrport_dat_w;
+wire litedramcore_bankmachine0_do_read;
+wire [3:0] litedramcore_bankmachine0_rdport_adr;
+wire [25:0] litedramcore_bankmachine0_rdport_dat_r;
+wire litedramcore_bankmachine0_fifo_in_payload_we;
+wire [22:0] litedramcore_bankmachine0_fifo_in_payload_addr;
+wire litedramcore_bankmachine0_fifo_in_first;
+wire litedramcore_bankmachine0_fifo_in_last;
+wire litedramcore_bankmachine0_fifo_out_payload_we;
+wire [22:0] litedramcore_bankmachine0_fifo_out_payload_addr;
+wire litedramcore_bankmachine0_fifo_out_first;
+wire litedramcore_bankmachine0_fifo_out_last;
+wire litedramcore_bankmachine0_sink_sink_valid;
+wire litedramcore_bankmachine0_sink_sink_ready;
+wire litedramcore_bankmachine0_sink_sink_first;
+wire litedramcore_bankmachine0_sink_sink_last;
+wire litedramcore_bankmachine0_sink_sink_payload_we;
+wire [22:0] litedramcore_bankmachine0_sink_sink_payload_addr;
+wire litedramcore_bankmachine0_source_source_valid;
+wire litedramcore_bankmachine0_source_source_ready;
+wire litedramcore_bankmachine0_source_source_first;
+wire litedramcore_bankmachine0_source_source_last;
+wire litedramcore_bankmachine0_source_source_payload_we;
+wire [22:0] litedramcore_bankmachine0_source_source_payload_addr;
+wire litedramcore_bankmachine0_pipe_valid_sink_valid;
+wire litedramcore_bankmachine0_pipe_valid_sink_ready;
+wire litedramcore_bankmachine0_pipe_valid_sink_first;
+wire litedramcore_bankmachine0_pipe_valid_sink_last;
+wire litedramcore_bankmachine0_pipe_valid_sink_payload_we;
+wire [22:0] litedramcore_bankmachine0_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine0_pipe_valid_source_ready;
+reg litedramcore_bankmachine0_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine0_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0;
+reg [22:0] litedramcore_bankmachine0_pipe_valid_source_payload_addr = 23'd0;
+reg [15:0] litedramcore_bankmachine0_row = 16'd0;
+reg litedramcore_bankmachine0_row_opened = 1'd0;
+wire litedramcore_bankmachine0_row_hit;
+reg litedramcore_bankmachine0_row_open = 1'd0;
+reg litedramcore_bankmachine0_row_close = 1'd0;
+reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine0_twtpcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine0_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine0_trccon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine0_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine0_trccon_count = 3'd0;
+wire litedramcore_bankmachine0_trascon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine0_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine0_trascon_count = 3'd0;
+wire litedramcore_bankmachine1_req_valid;
+wire litedramcore_bankmachine1_req_ready;
+wire litedramcore_bankmachine1_req_we;
+wire [22:0] litedramcore_bankmachine1_req_addr;
+wire litedramcore_bankmachine1_req_lock;
+reg litedramcore_bankmachine1_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine1_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine1_refresh_req;
+reg litedramcore_bankmachine1_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine1_cmd_valid = 1'd0;
+reg litedramcore_bankmachine1_cmd_ready = 1'd0;
+reg [15:0] litedramcore_bankmachine1_cmd_payload_a = 16'd0;
+wire [2:0] litedramcore_bankmachine1_cmd_payload_ba;
+reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine1_auto_precharge = 1'd0;
+wire litedramcore_bankmachine1_sink_valid;
+wire litedramcore_bankmachine1_sink_ready;
+reg litedramcore_bankmachine1_sink_first = 1'd0;
+reg litedramcore_bankmachine1_sink_last = 1'd0;
+wire litedramcore_bankmachine1_sink_payload_we;
+wire [22:0] litedramcore_bankmachine1_sink_payload_addr;
+wire litedramcore_bankmachine1_source_valid;
+wire litedramcore_bankmachine1_source_ready;
+wire litedramcore_bankmachine1_source_first;
+wire litedramcore_bankmachine1_source_last;
+wire litedramcore_bankmachine1_source_payload_we;
+wire [22:0] litedramcore_bankmachine1_source_payload_addr;
+wire litedramcore_bankmachine1_syncfifo1_we;
+wire litedramcore_bankmachine1_syncfifo1_writable;
+wire litedramcore_bankmachine1_syncfifo1_re;
+wire litedramcore_bankmachine1_syncfifo1_readable;
+wire [25:0] litedramcore_bankmachine1_syncfifo1_din;
+wire [25:0] litedramcore_bankmachine1_syncfifo1_dout;
+reg [4:0] litedramcore_bankmachine1_level = 5'd0;
+reg litedramcore_bankmachine1_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine1_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine1_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine1_wrport_adr = 4'd0;
+wire [25:0] litedramcore_bankmachine1_wrport_dat_r;
+wire litedramcore_bankmachine1_wrport_we;
+wire [25:0] litedramcore_bankmachine1_wrport_dat_w;
+wire litedramcore_bankmachine1_do_read;
+wire [3:0] litedramcore_bankmachine1_rdport_adr;
+wire [25:0] litedramcore_bankmachine1_rdport_dat_r;
+wire litedramcore_bankmachine1_fifo_in_payload_we;
+wire [22:0] litedramcore_bankmachine1_fifo_in_payload_addr;
+wire litedramcore_bankmachine1_fifo_in_first;
+wire litedramcore_bankmachine1_fifo_in_last;
+wire litedramcore_bankmachine1_fifo_out_payload_we;
+wire [22:0] litedramcore_bankmachine1_fifo_out_payload_addr;
+wire litedramcore_bankmachine1_fifo_out_first;
+wire litedramcore_bankmachine1_fifo_out_last;
+wire litedramcore_bankmachine1_sink_sink_valid;
+wire litedramcore_bankmachine1_sink_sink_ready;
+wire litedramcore_bankmachine1_sink_sink_first;
+wire litedramcore_bankmachine1_sink_sink_last;
+wire litedramcore_bankmachine1_sink_sink_payload_we;
+wire [22:0] litedramcore_bankmachine1_sink_sink_payload_addr;
+wire litedramcore_bankmachine1_source_source_valid;
+wire litedramcore_bankmachine1_source_source_ready;
+wire litedramcore_bankmachine1_source_source_first;
+wire litedramcore_bankmachine1_source_source_last;
+wire litedramcore_bankmachine1_source_source_payload_we;
+wire [22:0] litedramcore_bankmachine1_source_source_payload_addr;
+wire litedramcore_bankmachine1_pipe_valid_sink_valid;
+wire litedramcore_bankmachine1_pipe_valid_sink_ready;
+wire litedramcore_bankmachine1_pipe_valid_sink_first;
+wire litedramcore_bankmachine1_pipe_valid_sink_last;
+wire litedramcore_bankmachine1_pipe_valid_sink_payload_we;
+wire [22:0] litedramcore_bankmachine1_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine1_pipe_valid_source_ready;
+reg litedramcore_bankmachine1_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine1_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0;
+reg [22:0] litedramcore_bankmachine1_pipe_valid_source_payload_addr = 23'd0;
+reg [15:0] litedramcore_bankmachine1_row = 16'd0;
+reg litedramcore_bankmachine1_row_opened = 1'd0;
+wire litedramcore_bankmachine1_row_hit;
+reg litedramcore_bankmachine1_row_open = 1'd0;
+reg litedramcore_bankmachine1_row_close = 1'd0;
+reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine1_twtpcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine1_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine1_trccon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine1_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine1_trccon_count = 3'd0;
+wire litedramcore_bankmachine1_trascon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine1_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine1_trascon_count = 3'd0;
+wire litedramcore_bankmachine2_req_valid;
+wire litedramcore_bankmachine2_req_ready;
+wire litedramcore_bankmachine2_req_we;
+wire [22:0] litedramcore_bankmachine2_req_addr;
+wire litedramcore_bankmachine2_req_lock;
+reg litedramcore_bankmachine2_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine2_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine2_refresh_req;
+reg litedramcore_bankmachine2_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine2_cmd_valid = 1'd0;
+reg litedramcore_bankmachine2_cmd_ready = 1'd0;
+reg [15:0] litedramcore_bankmachine2_cmd_payload_a = 16'd0;
+wire [2:0] litedramcore_bankmachine2_cmd_payload_ba;
+reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine2_auto_precharge = 1'd0;
+wire litedramcore_bankmachine2_sink_valid;
+wire litedramcore_bankmachine2_sink_ready;
+reg litedramcore_bankmachine2_sink_first = 1'd0;
+reg litedramcore_bankmachine2_sink_last = 1'd0;
+wire litedramcore_bankmachine2_sink_payload_we;
+wire [22:0] litedramcore_bankmachine2_sink_payload_addr;
+wire litedramcore_bankmachine2_source_valid;
+wire litedramcore_bankmachine2_source_ready;
+wire litedramcore_bankmachine2_source_first;
+wire litedramcore_bankmachine2_source_last;
+wire litedramcore_bankmachine2_source_payload_we;
+wire [22:0] litedramcore_bankmachine2_source_payload_addr;
+wire litedramcore_bankmachine2_syncfifo2_we;
+wire litedramcore_bankmachine2_syncfifo2_writable;
+wire litedramcore_bankmachine2_syncfifo2_re;
+wire litedramcore_bankmachine2_syncfifo2_readable;
+wire [25:0] litedramcore_bankmachine2_syncfifo2_din;
+wire [25:0] litedramcore_bankmachine2_syncfifo2_dout;
+reg [4:0] litedramcore_bankmachine2_level = 5'd0;
+reg litedramcore_bankmachine2_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine2_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine2_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine2_wrport_adr = 4'd0;
+wire [25:0] litedramcore_bankmachine2_wrport_dat_r;
+wire litedramcore_bankmachine2_wrport_we;
+wire [25:0] litedramcore_bankmachine2_wrport_dat_w;
+wire litedramcore_bankmachine2_do_read;
+wire [3:0] litedramcore_bankmachine2_rdport_adr;
+wire [25:0] litedramcore_bankmachine2_rdport_dat_r;
+wire litedramcore_bankmachine2_fifo_in_payload_we;
+wire [22:0] litedramcore_bankmachine2_fifo_in_payload_addr;
+wire litedramcore_bankmachine2_fifo_in_first;
+wire litedramcore_bankmachine2_fifo_in_last;
+wire litedramcore_bankmachine2_fifo_out_payload_we;
+wire [22:0] litedramcore_bankmachine2_fifo_out_payload_addr;
+wire litedramcore_bankmachine2_fifo_out_first;
+wire litedramcore_bankmachine2_fifo_out_last;
+wire litedramcore_bankmachine2_sink_sink_valid;
+wire litedramcore_bankmachine2_sink_sink_ready;
+wire litedramcore_bankmachine2_sink_sink_first;
+wire litedramcore_bankmachine2_sink_sink_last;
+wire litedramcore_bankmachine2_sink_sink_payload_we;
+wire [22:0] litedramcore_bankmachine2_sink_sink_payload_addr;
+wire litedramcore_bankmachine2_source_source_valid;
+wire litedramcore_bankmachine2_source_source_ready;
+wire litedramcore_bankmachine2_source_source_first;
+wire litedramcore_bankmachine2_source_source_last;
+wire litedramcore_bankmachine2_source_source_payload_we;
+wire [22:0] litedramcore_bankmachine2_source_source_payload_addr;
+wire litedramcore_bankmachine2_pipe_valid_sink_valid;
+wire litedramcore_bankmachine2_pipe_valid_sink_ready;
+wire litedramcore_bankmachine2_pipe_valid_sink_first;
+wire litedramcore_bankmachine2_pipe_valid_sink_last;
+wire litedramcore_bankmachine2_pipe_valid_sink_payload_we;
+wire [22:0] litedramcore_bankmachine2_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine2_pipe_valid_source_ready;
+reg litedramcore_bankmachine2_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine2_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0;
+reg [22:0] litedramcore_bankmachine2_pipe_valid_source_payload_addr = 23'd0;
+reg [15:0] litedramcore_bankmachine2_row = 16'd0;
+reg litedramcore_bankmachine2_row_opened = 1'd0;
+wire litedramcore_bankmachine2_row_hit;
+reg litedramcore_bankmachine2_row_open = 1'd0;
+reg litedramcore_bankmachine2_row_close = 1'd0;
+reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine2_twtpcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine2_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine2_trccon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine2_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine2_trccon_count = 3'd0;
+wire litedramcore_bankmachine2_trascon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine2_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine2_trascon_count = 3'd0;
+wire litedramcore_bankmachine3_req_valid;
+wire litedramcore_bankmachine3_req_ready;
+wire litedramcore_bankmachine3_req_we;
+wire [22:0] litedramcore_bankmachine3_req_addr;
+wire litedramcore_bankmachine3_req_lock;
+reg litedramcore_bankmachine3_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine3_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine3_refresh_req;
+reg litedramcore_bankmachine3_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine3_cmd_valid = 1'd0;
+reg litedramcore_bankmachine3_cmd_ready = 1'd0;
+reg [15:0] litedramcore_bankmachine3_cmd_payload_a = 16'd0;
+wire [2:0] litedramcore_bankmachine3_cmd_payload_ba;
+reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine3_auto_precharge = 1'd0;
+wire litedramcore_bankmachine3_sink_valid;
+wire litedramcore_bankmachine3_sink_ready;
+reg litedramcore_bankmachine3_sink_first = 1'd0;
+reg litedramcore_bankmachine3_sink_last = 1'd0;
+wire litedramcore_bankmachine3_sink_payload_we;
+wire [22:0] litedramcore_bankmachine3_sink_payload_addr;
+wire litedramcore_bankmachine3_source_valid;
+wire litedramcore_bankmachine3_source_ready;
+wire litedramcore_bankmachine3_source_first;
+wire litedramcore_bankmachine3_source_last;
+wire litedramcore_bankmachine3_source_payload_we;
+wire [22:0] litedramcore_bankmachine3_source_payload_addr;
+wire litedramcore_bankmachine3_syncfifo3_we;
+wire litedramcore_bankmachine3_syncfifo3_writable;
+wire litedramcore_bankmachine3_syncfifo3_re;
+wire litedramcore_bankmachine3_syncfifo3_readable;
+wire [25:0] litedramcore_bankmachine3_syncfifo3_din;
+wire [25:0] litedramcore_bankmachine3_syncfifo3_dout;
+reg [4:0] litedramcore_bankmachine3_level = 5'd0;
+reg litedramcore_bankmachine3_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine3_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine3_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine3_wrport_adr = 4'd0;
+wire [25:0] litedramcore_bankmachine3_wrport_dat_r;
+wire litedramcore_bankmachine3_wrport_we;
+wire [25:0] litedramcore_bankmachine3_wrport_dat_w;
+wire litedramcore_bankmachine3_do_read;
+wire [3:0] litedramcore_bankmachine3_rdport_adr;
+wire [25:0] litedramcore_bankmachine3_rdport_dat_r;
+wire litedramcore_bankmachine3_fifo_in_payload_we;
+wire [22:0] litedramcore_bankmachine3_fifo_in_payload_addr;
+wire litedramcore_bankmachine3_fifo_in_first;
+wire litedramcore_bankmachine3_fifo_in_last;
+wire litedramcore_bankmachine3_fifo_out_payload_we;
+wire [22:0] litedramcore_bankmachine3_fifo_out_payload_addr;
+wire litedramcore_bankmachine3_fifo_out_first;
+wire litedramcore_bankmachine3_fifo_out_last;
+wire litedramcore_bankmachine3_sink_sink_valid;
+wire litedramcore_bankmachine3_sink_sink_ready;
+wire litedramcore_bankmachine3_sink_sink_first;
+wire litedramcore_bankmachine3_sink_sink_last;
+wire litedramcore_bankmachine3_sink_sink_payload_we;
+wire [22:0] litedramcore_bankmachine3_sink_sink_payload_addr;
+wire litedramcore_bankmachine3_source_source_valid;
+wire litedramcore_bankmachine3_source_source_ready;
+wire litedramcore_bankmachine3_source_source_first;
+wire litedramcore_bankmachine3_source_source_last;
+wire litedramcore_bankmachine3_source_source_payload_we;
+wire [22:0] litedramcore_bankmachine3_source_source_payload_addr;
+wire litedramcore_bankmachine3_pipe_valid_sink_valid;
+wire litedramcore_bankmachine3_pipe_valid_sink_ready;
+wire litedramcore_bankmachine3_pipe_valid_sink_first;
+wire litedramcore_bankmachine3_pipe_valid_sink_last;
+wire litedramcore_bankmachine3_pipe_valid_sink_payload_we;
+wire [22:0] litedramcore_bankmachine3_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine3_pipe_valid_source_ready;
+reg litedramcore_bankmachine3_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine3_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0;
+reg [22:0] litedramcore_bankmachine3_pipe_valid_source_payload_addr = 23'd0;
+reg [15:0] litedramcore_bankmachine3_row = 16'd0;
+reg litedramcore_bankmachine3_row_opened = 1'd0;
+wire litedramcore_bankmachine3_row_hit;
+reg litedramcore_bankmachine3_row_open = 1'd0;
+reg litedramcore_bankmachine3_row_close = 1'd0;
+reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine3_twtpcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine3_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine3_trccon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine3_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine3_trccon_count = 3'd0;
+wire litedramcore_bankmachine3_trascon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine3_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine3_trascon_count = 3'd0;
+wire litedramcore_bankmachine4_req_valid;
+wire litedramcore_bankmachine4_req_ready;
+wire litedramcore_bankmachine4_req_we;
+wire [22:0] litedramcore_bankmachine4_req_addr;
+wire litedramcore_bankmachine4_req_lock;
+reg litedramcore_bankmachine4_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine4_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine4_refresh_req;
+reg litedramcore_bankmachine4_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine4_cmd_valid = 1'd0;
+reg litedramcore_bankmachine4_cmd_ready = 1'd0;
+reg [15:0] litedramcore_bankmachine4_cmd_payload_a = 16'd0;
+wire [2:0] litedramcore_bankmachine4_cmd_payload_ba;
+reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine4_auto_precharge = 1'd0;
+wire litedramcore_bankmachine4_sink_valid;
+wire litedramcore_bankmachine4_sink_ready;
+reg litedramcore_bankmachine4_sink_first = 1'd0;
+reg litedramcore_bankmachine4_sink_last = 1'd0;
+wire litedramcore_bankmachine4_sink_payload_we;
+wire [22:0] litedramcore_bankmachine4_sink_payload_addr;
+wire litedramcore_bankmachine4_source_valid;
+wire litedramcore_bankmachine4_source_ready;
+wire litedramcore_bankmachine4_source_first;
+wire litedramcore_bankmachine4_source_last;
+wire litedramcore_bankmachine4_source_payload_we;
+wire [22:0] litedramcore_bankmachine4_source_payload_addr;
+wire litedramcore_bankmachine4_syncfifo4_we;
+wire litedramcore_bankmachine4_syncfifo4_writable;
+wire litedramcore_bankmachine4_syncfifo4_re;
+wire litedramcore_bankmachine4_syncfifo4_readable;
+wire [25:0] litedramcore_bankmachine4_syncfifo4_din;
+wire [25:0] litedramcore_bankmachine4_syncfifo4_dout;
+reg [4:0] litedramcore_bankmachine4_level = 5'd0;
+reg litedramcore_bankmachine4_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine4_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine4_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine4_wrport_adr = 4'd0;
+wire [25:0] litedramcore_bankmachine4_wrport_dat_r;
+wire litedramcore_bankmachine4_wrport_we;
+wire [25:0] litedramcore_bankmachine4_wrport_dat_w;
+wire litedramcore_bankmachine4_do_read;
+wire [3:0] litedramcore_bankmachine4_rdport_adr;
+wire [25:0] litedramcore_bankmachine4_rdport_dat_r;
+wire litedramcore_bankmachine4_fifo_in_payload_we;
+wire [22:0] litedramcore_bankmachine4_fifo_in_payload_addr;
+wire litedramcore_bankmachine4_fifo_in_first;
+wire litedramcore_bankmachine4_fifo_in_last;
+wire litedramcore_bankmachine4_fifo_out_payload_we;
+wire [22:0] litedramcore_bankmachine4_fifo_out_payload_addr;
+wire litedramcore_bankmachine4_fifo_out_first;
+wire litedramcore_bankmachine4_fifo_out_last;
+wire litedramcore_bankmachine4_sink_sink_valid;
+wire litedramcore_bankmachine4_sink_sink_ready;
+wire litedramcore_bankmachine4_sink_sink_first;
+wire litedramcore_bankmachine4_sink_sink_last;
+wire litedramcore_bankmachine4_sink_sink_payload_we;
+wire [22:0] litedramcore_bankmachine4_sink_sink_payload_addr;
+wire litedramcore_bankmachine4_source_source_valid;
+wire litedramcore_bankmachine4_source_source_ready;
+wire litedramcore_bankmachine4_source_source_first;
+wire litedramcore_bankmachine4_source_source_last;
+wire litedramcore_bankmachine4_source_source_payload_we;
+wire [22:0] litedramcore_bankmachine4_source_source_payload_addr;
+wire litedramcore_bankmachine4_pipe_valid_sink_valid;
+wire litedramcore_bankmachine4_pipe_valid_sink_ready;
+wire litedramcore_bankmachine4_pipe_valid_sink_first;
+wire litedramcore_bankmachine4_pipe_valid_sink_last;
+wire litedramcore_bankmachine4_pipe_valid_sink_payload_we;
+wire [22:0] litedramcore_bankmachine4_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine4_pipe_valid_source_ready;
+reg litedramcore_bankmachine4_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine4_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0;
+reg [22:0] litedramcore_bankmachine4_pipe_valid_source_payload_addr = 23'd0;
+reg [15:0] litedramcore_bankmachine4_row = 16'd0;
+reg litedramcore_bankmachine4_row_opened = 1'd0;
+wire litedramcore_bankmachine4_row_hit;
+reg litedramcore_bankmachine4_row_open = 1'd0;
+reg litedramcore_bankmachine4_row_close = 1'd0;
+reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine4_twtpcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine4_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine4_trccon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine4_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine4_trccon_count = 3'd0;
+wire litedramcore_bankmachine4_trascon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine4_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine4_trascon_count = 3'd0;
+wire litedramcore_bankmachine5_req_valid;
+wire litedramcore_bankmachine5_req_ready;
+wire litedramcore_bankmachine5_req_we;
+wire [22:0] litedramcore_bankmachine5_req_addr;
+wire litedramcore_bankmachine5_req_lock;
+reg litedramcore_bankmachine5_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine5_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine5_refresh_req;
+reg litedramcore_bankmachine5_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine5_cmd_valid = 1'd0;
+reg litedramcore_bankmachine5_cmd_ready = 1'd0;
+reg [15:0] litedramcore_bankmachine5_cmd_payload_a = 16'd0;
+wire [2:0] litedramcore_bankmachine5_cmd_payload_ba;
+reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine5_auto_precharge = 1'd0;
+wire litedramcore_bankmachine5_sink_valid;
+wire litedramcore_bankmachine5_sink_ready;
+reg litedramcore_bankmachine5_sink_first = 1'd0;
+reg litedramcore_bankmachine5_sink_last = 1'd0;
+wire litedramcore_bankmachine5_sink_payload_we;
+wire [22:0] litedramcore_bankmachine5_sink_payload_addr;
+wire litedramcore_bankmachine5_source_valid;
+wire litedramcore_bankmachine5_source_ready;
+wire litedramcore_bankmachine5_source_first;
+wire litedramcore_bankmachine5_source_last;
+wire litedramcore_bankmachine5_source_payload_we;
+wire [22:0] litedramcore_bankmachine5_source_payload_addr;
+wire litedramcore_bankmachine5_syncfifo5_we;
+wire litedramcore_bankmachine5_syncfifo5_writable;
+wire litedramcore_bankmachine5_syncfifo5_re;
+wire litedramcore_bankmachine5_syncfifo5_readable;
+wire [25:0] litedramcore_bankmachine5_syncfifo5_din;
+wire [25:0] litedramcore_bankmachine5_syncfifo5_dout;
+reg [4:0] litedramcore_bankmachine5_level = 5'd0;
+reg litedramcore_bankmachine5_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine5_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine5_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine5_wrport_adr = 4'd0;
+wire [25:0] litedramcore_bankmachine5_wrport_dat_r;
+wire litedramcore_bankmachine5_wrport_we;
+wire [25:0] litedramcore_bankmachine5_wrport_dat_w;
+wire litedramcore_bankmachine5_do_read;
+wire [3:0] litedramcore_bankmachine5_rdport_adr;
+wire [25:0] litedramcore_bankmachine5_rdport_dat_r;
+wire litedramcore_bankmachine5_fifo_in_payload_we;
+wire [22:0] litedramcore_bankmachine5_fifo_in_payload_addr;
+wire litedramcore_bankmachine5_fifo_in_first;
+wire litedramcore_bankmachine5_fifo_in_last;
+wire litedramcore_bankmachine5_fifo_out_payload_we;
+wire [22:0] litedramcore_bankmachine5_fifo_out_payload_addr;
+wire litedramcore_bankmachine5_fifo_out_first;
+wire litedramcore_bankmachine5_fifo_out_last;
+wire litedramcore_bankmachine5_sink_sink_valid;
+wire litedramcore_bankmachine5_sink_sink_ready;
+wire litedramcore_bankmachine5_sink_sink_first;
+wire litedramcore_bankmachine5_sink_sink_last;
+wire litedramcore_bankmachine5_sink_sink_payload_we;
+wire [22:0] litedramcore_bankmachine5_sink_sink_payload_addr;
+wire litedramcore_bankmachine5_source_source_valid;
+wire litedramcore_bankmachine5_source_source_ready;
+wire litedramcore_bankmachine5_source_source_first;
+wire litedramcore_bankmachine5_source_source_last;
+wire litedramcore_bankmachine5_source_source_payload_we;
+wire [22:0] litedramcore_bankmachine5_source_source_payload_addr;
+wire litedramcore_bankmachine5_pipe_valid_sink_valid;
+wire litedramcore_bankmachine5_pipe_valid_sink_ready;
+wire litedramcore_bankmachine5_pipe_valid_sink_first;
+wire litedramcore_bankmachine5_pipe_valid_sink_last;
+wire litedramcore_bankmachine5_pipe_valid_sink_payload_we;
+wire [22:0] litedramcore_bankmachine5_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine5_pipe_valid_source_ready;
+reg litedramcore_bankmachine5_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine5_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0;
+reg [22:0] litedramcore_bankmachine5_pipe_valid_source_payload_addr = 23'd0;
+reg [15:0] litedramcore_bankmachine5_row = 16'd0;
+reg litedramcore_bankmachine5_row_opened = 1'd0;
+wire litedramcore_bankmachine5_row_hit;
+reg litedramcore_bankmachine5_row_open = 1'd0;
+reg litedramcore_bankmachine5_row_close = 1'd0;
+reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine5_twtpcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine5_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine5_trccon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine5_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine5_trccon_count = 3'd0;
+wire litedramcore_bankmachine5_trascon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine5_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine5_trascon_count = 3'd0;
+wire litedramcore_bankmachine6_req_valid;
+wire litedramcore_bankmachine6_req_ready;
+wire litedramcore_bankmachine6_req_we;
+wire [22:0] litedramcore_bankmachine6_req_addr;
+wire litedramcore_bankmachine6_req_lock;
+reg litedramcore_bankmachine6_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine6_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine6_refresh_req;
+reg litedramcore_bankmachine6_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine6_cmd_valid = 1'd0;
+reg litedramcore_bankmachine6_cmd_ready = 1'd0;
+reg [15:0] litedramcore_bankmachine6_cmd_payload_a = 16'd0;
+wire [2:0] litedramcore_bankmachine6_cmd_payload_ba;
+reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine6_auto_precharge = 1'd0;
+wire litedramcore_bankmachine6_sink_valid;
+wire litedramcore_bankmachine6_sink_ready;
+reg litedramcore_bankmachine6_sink_first = 1'd0;
+reg litedramcore_bankmachine6_sink_last = 1'd0;
+wire litedramcore_bankmachine6_sink_payload_we;
+wire [22:0] litedramcore_bankmachine6_sink_payload_addr;
+wire litedramcore_bankmachine6_source_valid;
+wire litedramcore_bankmachine6_source_ready;
+wire litedramcore_bankmachine6_source_first;
+wire litedramcore_bankmachine6_source_last;
+wire litedramcore_bankmachine6_source_payload_we;
+wire [22:0] litedramcore_bankmachine6_source_payload_addr;
+wire litedramcore_bankmachine6_syncfifo6_we;
+wire litedramcore_bankmachine6_syncfifo6_writable;
+wire litedramcore_bankmachine6_syncfifo6_re;
+wire litedramcore_bankmachine6_syncfifo6_readable;
+wire [25:0] litedramcore_bankmachine6_syncfifo6_din;
+wire [25:0] litedramcore_bankmachine6_syncfifo6_dout;
+reg [4:0] litedramcore_bankmachine6_level = 5'd0;
+reg litedramcore_bankmachine6_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine6_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine6_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine6_wrport_adr = 4'd0;
+wire [25:0] litedramcore_bankmachine6_wrport_dat_r;
+wire litedramcore_bankmachine6_wrport_we;
+wire [25:0] litedramcore_bankmachine6_wrport_dat_w;
+wire litedramcore_bankmachine6_do_read;
+wire [3:0] litedramcore_bankmachine6_rdport_adr;
+wire [25:0] litedramcore_bankmachine6_rdport_dat_r;
+wire litedramcore_bankmachine6_fifo_in_payload_we;
+wire [22:0] litedramcore_bankmachine6_fifo_in_payload_addr;
+wire litedramcore_bankmachine6_fifo_in_first;
+wire litedramcore_bankmachine6_fifo_in_last;
+wire litedramcore_bankmachine6_fifo_out_payload_we;
+wire [22:0] litedramcore_bankmachine6_fifo_out_payload_addr;
+wire litedramcore_bankmachine6_fifo_out_first;
+wire litedramcore_bankmachine6_fifo_out_last;
+wire litedramcore_bankmachine6_sink_sink_valid;
+wire litedramcore_bankmachine6_sink_sink_ready;
+wire litedramcore_bankmachine6_sink_sink_first;
+wire litedramcore_bankmachine6_sink_sink_last;
+wire litedramcore_bankmachine6_sink_sink_payload_we;
+wire [22:0] litedramcore_bankmachine6_sink_sink_payload_addr;
+wire litedramcore_bankmachine6_source_source_valid;
+wire litedramcore_bankmachine6_source_source_ready;
+wire litedramcore_bankmachine6_source_source_first;
+wire litedramcore_bankmachine6_source_source_last;
+wire litedramcore_bankmachine6_source_source_payload_we;
+wire [22:0] litedramcore_bankmachine6_source_source_payload_addr;
+wire litedramcore_bankmachine6_pipe_valid_sink_valid;
+wire litedramcore_bankmachine6_pipe_valid_sink_ready;
+wire litedramcore_bankmachine6_pipe_valid_sink_first;
+wire litedramcore_bankmachine6_pipe_valid_sink_last;
+wire litedramcore_bankmachine6_pipe_valid_sink_payload_we;
+wire [22:0] litedramcore_bankmachine6_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine6_pipe_valid_source_ready;
+reg litedramcore_bankmachine6_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine6_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0;
+reg [22:0] litedramcore_bankmachine6_pipe_valid_source_payload_addr = 23'd0;
+reg [15:0] litedramcore_bankmachine6_row = 16'd0;
+reg litedramcore_bankmachine6_row_opened = 1'd0;
+wire litedramcore_bankmachine6_row_hit;
+reg litedramcore_bankmachine6_row_open = 1'd0;
+reg litedramcore_bankmachine6_row_close = 1'd0;
+reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine6_twtpcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine6_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine6_trccon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine6_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine6_trccon_count = 3'd0;
+wire litedramcore_bankmachine6_trascon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine6_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine6_trascon_count = 3'd0;
+wire litedramcore_bankmachine7_req_valid;
+wire litedramcore_bankmachine7_req_ready;
+wire litedramcore_bankmachine7_req_we;
+wire [22:0] litedramcore_bankmachine7_req_addr;
+wire litedramcore_bankmachine7_req_lock;
+reg litedramcore_bankmachine7_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine7_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine7_refresh_req;
+reg litedramcore_bankmachine7_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine7_cmd_valid = 1'd0;
+reg litedramcore_bankmachine7_cmd_ready = 1'd0;
+reg [15:0] litedramcore_bankmachine7_cmd_payload_a = 16'd0;
+wire [2:0] litedramcore_bankmachine7_cmd_payload_ba;
+reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine7_auto_precharge = 1'd0;
+wire litedramcore_bankmachine7_sink_valid;
+wire litedramcore_bankmachine7_sink_ready;
+reg litedramcore_bankmachine7_sink_first = 1'd0;
+reg litedramcore_bankmachine7_sink_last = 1'd0;
+wire litedramcore_bankmachine7_sink_payload_we;
+wire [22:0] litedramcore_bankmachine7_sink_payload_addr;
+wire litedramcore_bankmachine7_source_valid;
+wire litedramcore_bankmachine7_source_ready;
+wire litedramcore_bankmachine7_source_first;
+wire litedramcore_bankmachine7_source_last;
+wire litedramcore_bankmachine7_source_payload_we;
+wire [22:0] litedramcore_bankmachine7_source_payload_addr;
+wire litedramcore_bankmachine7_syncfifo7_we;
+wire litedramcore_bankmachine7_syncfifo7_writable;
+wire litedramcore_bankmachine7_syncfifo7_re;
+wire litedramcore_bankmachine7_syncfifo7_readable;
+wire [25:0] litedramcore_bankmachine7_syncfifo7_din;
+wire [25:0] litedramcore_bankmachine7_syncfifo7_dout;
+reg [4:0] litedramcore_bankmachine7_level = 5'd0;
+reg litedramcore_bankmachine7_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine7_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine7_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine7_wrport_adr = 4'd0;
+wire [25:0] litedramcore_bankmachine7_wrport_dat_r;
+wire litedramcore_bankmachine7_wrport_we;
+wire [25:0] litedramcore_bankmachine7_wrport_dat_w;
+wire litedramcore_bankmachine7_do_read;
+wire [3:0] litedramcore_bankmachine7_rdport_adr;
+wire [25:0] litedramcore_bankmachine7_rdport_dat_r;
+wire litedramcore_bankmachine7_fifo_in_payload_we;
+wire [22:0] litedramcore_bankmachine7_fifo_in_payload_addr;
+wire litedramcore_bankmachine7_fifo_in_first;
+wire litedramcore_bankmachine7_fifo_in_last;
+wire litedramcore_bankmachine7_fifo_out_payload_we;
+wire [22:0] litedramcore_bankmachine7_fifo_out_payload_addr;
+wire litedramcore_bankmachine7_fifo_out_first;
+wire litedramcore_bankmachine7_fifo_out_last;
+wire litedramcore_bankmachine7_sink_sink_valid;
+wire litedramcore_bankmachine7_sink_sink_ready;
+wire litedramcore_bankmachine7_sink_sink_first;
+wire litedramcore_bankmachine7_sink_sink_last;
+wire litedramcore_bankmachine7_sink_sink_payload_we;
+wire [22:0] litedramcore_bankmachine7_sink_sink_payload_addr;
+wire litedramcore_bankmachine7_source_source_valid;
+wire litedramcore_bankmachine7_source_source_ready;
+wire litedramcore_bankmachine7_source_source_first;
+wire litedramcore_bankmachine7_source_source_last;
+wire litedramcore_bankmachine7_source_source_payload_we;
+wire [22:0] litedramcore_bankmachine7_source_source_payload_addr;
+wire litedramcore_bankmachine7_pipe_valid_sink_valid;
+wire litedramcore_bankmachine7_pipe_valid_sink_ready;
+wire litedramcore_bankmachine7_pipe_valid_sink_first;
+wire litedramcore_bankmachine7_pipe_valid_sink_last;
+wire litedramcore_bankmachine7_pipe_valid_sink_payload_we;
+wire [22:0] litedramcore_bankmachine7_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine7_pipe_valid_source_ready;
+reg litedramcore_bankmachine7_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine7_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0;
+reg [22:0] litedramcore_bankmachine7_pipe_valid_source_payload_addr = 23'd0;
+reg [15:0] litedramcore_bankmachine7_row = 16'd0;
+reg litedramcore_bankmachine7_row_opened = 1'd0;
+wire litedramcore_bankmachine7_row_hit;
+reg litedramcore_bankmachine7_row_open = 1'd0;
+reg litedramcore_bankmachine7_row_close = 1'd0;
+reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine7_twtpcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine7_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine7_trccon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine7_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine7_trccon_count = 3'd0;
+wire litedramcore_bankmachine7_trascon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine7_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine7_trascon_count = 3'd0;
+wire litedramcore_ras_allowed;
+wire litedramcore_cas_allowed;
+wire [1:0] litedramcore_rdcmdphase;
+wire [1:0] litedramcore_wrcmdphase;
+reg litedramcore_choose_cmd_want_reads = 1'd0;
+reg litedramcore_choose_cmd_want_writes = 1'd0;
+reg litedramcore_choose_cmd_want_cmds = 1'd0;
+reg litedramcore_choose_cmd_want_activates = 1'd0;
+wire litedramcore_choose_cmd_cmd_valid;
+reg litedramcore_choose_cmd_cmd_ready = 1'd0;
+wire [15:0] litedramcore_choose_cmd_cmd_payload_a;
+wire [2:0] litedramcore_choose_cmd_cmd_payload_ba;
+reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
+reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
+reg litedramcore_choose_cmd_cmd_payload_we = 1'd0;
+wire litedramcore_choose_cmd_cmd_payload_is_cmd;
+wire litedramcore_choose_cmd_cmd_payload_is_read;
+wire litedramcore_choose_cmd_cmd_payload_is_write;
+reg [7:0] litedramcore_choose_cmd_valids = 8'd0;
+wire [7:0] litedramcore_choose_cmd_request;
+reg [2:0] litedramcore_choose_cmd_grant = 3'd0;
+wire litedramcore_choose_cmd_ce;
+reg litedramcore_choose_req_want_reads = 1'd0;
+reg litedramcore_choose_req_want_writes = 1'd0;
+reg litedramcore_choose_req_want_cmds = 1'd0;
+reg litedramcore_choose_req_want_activates = 1'd0;
+wire litedramcore_choose_req_cmd_valid;
+reg litedramcore_choose_req_cmd_ready = 1'd0;
+wire [15:0] litedramcore_choose_req_cmd_payload_a;
+wire [2:0] litedramcore_choose_req_cmd_payload_ba;
+reg litedramcore_choose_req_cmd_payload_cas = 1'd0;
+reg litedramcore_choose_req_cmd_payload_ras = 1'd0;
+reg litedramcore_choose_req_cmd_payload_we = 1'd0;
+wire litedramcore_choose_req_cmd_payload_is_cmd;
+wire litedramcore_choose_req_cmd_payload_is_read;
+wire litedramcore_choose_req_cmd_payload_is_write;
+reg [7:0] litedramcore_choose_req_valids = 8'd0;
+wire [7:0] litedramcore_choose_req_request;
+reg [2:0] litedramcore_choose_req_grant = 3'd0;
+wire litedramcore_choose_req_ce;
+reg [15:0] litedramcore_nop_a = 16'd0;
+reg [2:0] litedramcore_nop_ba = 3'd0;
+reg [1:0] litedramcore_steerer_sel0 = 2'd0;
+reg [1:0] litedramcore_steerer_sel1 = 2'd0;
+reg [1:0] litedramcore_steerer_sel2 = 2'd0;
+reg [1:0] litedramcore_steerer_sel3 = 2'd0;
+reg litedramcore_steerer0 = 1'd1;
+reg litedramcore_steerer1 = 1'd1;
+reg litedramcore_steerer2 = 1'd1;
+reg litedramcore_steerer3 = 1'd1;
+reg litedramcore_steerer4 = 1'd1;
+reg litedramcore_steerer5 = 1'd1;
+reg litedramcore_steerer6 = 1'd1;
+reg litedramcore_steerer7 = 1'd1;
+wire litedramcore_trrdcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_trrdcon_ready = 1'd0;
+reg litedramcore_trrdcon_count = 1'd0;
+wire litedramcore_tfawcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_tfawcon_ready = 1'd1;
+wire [2:0] litedramcore_tfawcon_count;
+reg [4:0] litedramcore_tfawcon_window = 5'd0;
+wire litedramcore_tccdcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_tccdcon_ready = 1'd0;
+reg litedramcore_tccdcon_count = 1'd0;
+wire litedramcore_twtrcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_twtrcon_ready = 1'd0;
+reg [2:0] litedramcore_twtrcon_count = 3'd0;
+wire litedramcore_read_available;
+wire litedramcore_write_available;
+reg litedramcore_en0 = 1'd0;
+wire litedramcore_max_time0;
+reg [4:0] litedramcore_time0 = 5'd0;
+reg litedramcore_en1 = 1'd0;
+wire litedramcore_max_time1;
+reg [3:0] litedramcore_time1 = 4'd0;
+wire litedramcore_go_to_refresh;
+reg init_done_storage = 1'd0;
+reg init_done_re = 1'd0;
+reg init_error_storage = 1'd0;
+reg init_error_re = 1'd0;
+wire [29:0] wb_bus_adr;
+wire [31:0] wb_bus_dat_w;
+wire [31:0] wb_bus_dat_r;
+wire [3:0] wb_bus_sel;
+wire wb_bus_cyc;
+wire wb_bus_stb;
+wire wb_bus_ack;
+wire wb_bus_we;
+wire [2:0] wb_bus_cti;
+wire [1:0] wb_bus_bte;
+wire wb_bus_err;
+wire user_enable;
+wire user_port_cmd_valid;
+wire user_port_cmd_ready;
+wire user_port_cmd_payload_we;
+wire [25:0] user_port_cmd_payload_addr;
+wire user_port_wdata_valid;
+wire user_port_wdata_ready;
+wire [127:0] user_port_wdata_payload_data;
+wire [15:0] user_port_wdata_payload_we;
+wire user_port_rdata_valid;
+wire user_port_rdata_ready;
+wire [127:0] user_port_rdata_payload_data;
+reg [13:0] litedramcore_adr = 14'd0;
+reg litedramcore_we = 1'd0;
+reg [31:0] litedramcore_dat_w = 32'd0;
+wire [31:0] litedramcore_dat_r;
+wire [29:0] litedramcore_wishbone_adr;
+wire [31:0] litedramcore_wishbone_dat_w;
+reg [31:0] litedramcore_wishbone_dat_r = 32'd0;
+wire [3:0] litedramcore_wishbone_sel;
+wire litedramcore_wishbone_cyc;
+wire litedramcore_wishbone_stb;
+reg litedramcore_wishbone_ack = 1'd0;
+wire litedramcore_wishbone_we;
+wire [2:0] litedramcore_wishbone_cti;
+wire [1:0] litedramcore_wishbone_bte;
+reg litedramcore_wishbone_err = 1'd0;
+wire [13:0] interface0_bank_bus_adr;
+wire interface0_bank_bus_we;
+wire [31:0] interface0_bank_bus_dat_w;
+reg [31:0] interface0_bank_bus_dat_r = 32'd0;
+reg csrbank0_init_done0_re = 1'd0;
+wire csrbank0_init_done0_r;
+reg csrbank0_init_done0_we = 1'd0;
+wire csrbank0_init_done0_w;
+reg csrbank0_init_error0_re = 1'd0;
+wire csrbank0_init_error0_r;
+reg csrbank0_init_error0_we = 1'd0;
+wire csrbank0_init_error0_w;
+wire csrbank0_sel;
+wire [13:0] interface1_bank_bus_adr;
+wire interface1_bank_bus_we;
+wire [31:0] interface1_bank_bus_dat_w;
+reg [31:0] interface1_bank_bus_dat_r = 32'd0;
+reg csrbank1_rst0_re = 1'd0;
+wire csrbank1_rst0_r;
+reg csrbank1_rst0_we = 1'd0;
+wire csrbank1_rst0_w;
+reg csrbank1_dly_sel0_re = 1'd0;
+wire [1:0] csrbank1_dly_sel0_r;
+reg csrbank1_dly_sel0_we = 1'd0;
+wire [1:0] csrbank1_dly_sel0_w;
+reg csrbank1_half_sys8x_taps0_re = 1'd0;
+wire [4:0] csrbank1_half_sys8x_taps0_r;
+reg csrbank1_half_sys8x_taps0_we = 1'd0;
+wire [4:0] csrbank1_half_sys8x_taps0_w;
+reg csrbank1_wlevel_en0_re = 1'd0;
+wire csrbank1_wlevel_en0_r;
+reg csrbank1_wlevel_en0_we = 1'd0;
+wire csrbank1_wlevel_en0_w;
+reg csrbank1_rdphase0_re = 1'd0;
+wire [1:0] csrbank1_rdphase0_r;
+reg csrbank1_rdphase0_we = 1'd0;
+wire [1:0] csrbank1_rdphase0_w;
+reg csrbank1_wrphase0_re = 1'd0;
+wire [1:0] csrbank1_wrphase0_r;
+reg csrbank1_wrphase0_we = 1'd0;
+wire [1:0] csrbank1_wrphase0_w;
+wire csrbank1_sel;
+wire [13:0] interface2_bank_bus_adr;
+wire interface2_bank_bus_we;
+wire [31:0] interface2_bank_bus_dat_w;
+reg [31:0] interface2_bank_bus_dat_r = 32'd0;
+reg csrbank2_dfii_control0_re = 1'd0;
+wire [3:0] csrbank2_dfii_control0_r;
+reg csrbank2_dfii_control0_we = 1'd0;
+wire [3:0] csrbank2_dfii_control0_w;
+reg csrbank2_dfii_pi0_command0_re = 1'd0;
+wire [5:0] csrbank2_dfii_pi0_command0_r;
+reg csrbank2_dfii_pi0_command0_we = 1'd0;
+wire [5:0] csrbank2_dfii_pi0_command0_w;
+reg csrbank2_dfii_pi0_address0_re = 1'd0;
+wire [15:0] csrbank2_dfii_pi0_address0_r;
+reg csrbank2_dfii_pi0_address0_we = 1'd0;
+wire [15:0] csrbank2_dfii_pi0_address0_w;
+reg csrbank2_dfii_pi0_baddress0_re = 1'd0;
+wire [2:0] csrbank2_dfii_pi0_baddress0_r;
+reg csrbank2_dfii_pi0_baddress0_we = 1'd0;
+wire [2:0] csrbank2_dfii_pi0_baddress0_w;
+reg csrbank2_dfii_pi0_wrdata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_wrdata0_r;
+reg csrbank2_dfii_pi0_wrdata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_wrdata0_w;
+reg csrbank2_dfii_pi0_rddata_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_rddata_r;
+reg csrbank2_dfii_pi0_rddata_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_rddata_w;
+reg csrbank2_dfii_pi1_command0_re = 1'd0;
+wire [5:0] csrbank2_dfii_pi1_command0_r;
+reg csrbank2_dfii_pi1_command0_we = 1'd0;
+wire [5:0] csrbank2_dfii_pi1_command0_w;
+reg csrbank2_dfii_pi1_address0_re = 1'd0;
+wire [15:0] csrbank2_dfii_pi1_address0_r;
+reg csrbank2_dfii_pi1_address0_we = 1'd0;
+wire [15:0] csrbank2_dfii_pi1_address0_w;
+reg csrbank2_dfii_pi1_baddress0_re = 1'd0;
+wire [2:0] csrbank2_dfii_pi1_baddress0_r;
+reg csrbank2_dfii_pi1_baddress0_we = 1'd0;
+wire [2:0] csrbank2_dfii_pi1_baddress0_w;
+reg csrbank2_dfii_pi1_wrdata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_wrdata0_r;
+reg csrbank2_dfii_pi1_wrdata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_wrdata0_w;
+reg csrbank2_dfii_pi1_rddata_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_rddata_r;
+reg csrbank2_dfii_pi1_rddata_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_rddata_w;
+reg csrbank2_dfii_pi2_command0_re = 1'd0;
+wire [5:0] csrbank2_dfii_pi2_command0_r;
+reg csrbank2_dfii_pi2_command0_we = 1'd0;
+wire [5:0] csrbank2_dfii_pi2_command0_w;
+reg csrbank2_dfii_pi2_address0_re = 1'd0;
+wire [15:0] csrbank2_dfii_pi2_address0_r;
+reg csrbank2_dfii_pi2_address0_we = 1'd0;
+wire [15:0] csrbank2_dfii_pi2_address0_w;
+reg csrbank2_dfii_pi2_baddress0_re = 1'd0;
+wire [2:0] csrbank2_dfii_pi2_baddress0_r;
+reg csrbank2_dfii_pi2_baddress0_we = 1'd0;
+wire [2:0] csrbank2_dfii_pi2_baddress0_w;
+reg csrbank2_dfii_pi2_wrdata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_wrdata0_r;
+reg csrbank2_dfii_pi2_wrdata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_wrdata0_w;
+reg csrbank2_dfii_pi2_rddata_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_rddata_r;
+reg csrbank2_dfii_pi2_rddata_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_rddata_w;
+reg csrbank2_dfii_pi3_command0_re = 1'd0;
+wire [5:0] csrbank2_dfii_pi3_command0_r;
+reg csrbank2_dfii_pi3_command0_we = 1'd0;
+wire [5:0] csrbank2_dfii_pi3_command0_w;
+reg csrbank2_dfii_pi3_address0_re = 1'd0;
+wire [15:0] csrbank2_dfii_pi3_address0_r;
+reg csrbank2_dfii_pi3_address0_we = 1'd0;
+wire [15:0] csrbank2_dfii_pi3_address0_w;
+reg csrbank2_dfii_pi3_baddress0_re = 1'd0;
+wire [2:0] csrbank2_dfii_pi3_baddress0_r;
+reg csrbank2_dfii_pi3_baddress0_we = 1'd0;
+wire [2:0] csrbank2_dfii_pi3_baddress0_w;
+reg csrbank2_dfii_pi3_wrdata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_wrdata0_r;
+reg csrbank2_dfii_pi3_wrdata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_wrdata0_w;
+reg csrbank2_dfii_pi3_rddata_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_rddata_r;
+reg csrbank2_dfii_pi3_rddata_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_rddata_w;
+wire csrbank2_sel;
+wire [13:0] csr_interconnect_adr;
+wire csr_interconnect_we;
+wire [31:0] csr_interconnect_dat_w;
+wire [31:0] csr_interconnect_dat_r;
+wire litedramcore_reset0;
+wire litedramcore_reset1;
+wire litedramcore_reset2;
+wire litedramcore_reset3;
+wire litedramcore_reset4;
+wire litedramcore_reset5;
+wire litedramcore_reset6;
+wire litedramcore_reset7;
+wire litedramcore_pll_fb;
+reg [1:0] litedramcore_refresher_state = 2'd0;
+reg [1:0] litedramcore_refresher_next_state = 2'd0;
+reg [3:0] litedramcore_bankmachine0_state = 4'd0;
+reg [3:0] litedramcore_bankmachine0_next_state = 4'd0;
+reg [3:0] litedramcore_bankmachine1_state = 4'd0;
+reg [3:0] litedramcore_bankmachine1_next_state = 4'd0;
+reg [3:0] litedramcore_bankmachine2_state = 4'd0;
+reg [3:0] litedramcore_bankmachine2_next_state = 4'd0;
+reg [3:0] litedramcore_bankmachine3_state = 4'd0;
+reg [3:0] litedramcore_bankmachine3_next_state = 4'd0;
+reg [3:0] litedramcore_bankmachine4_state = 4'd0;
+reg [3:0] litedramcore_bankmachine4_next_state = 4'd0;
+reg [3:0] litedramcore_bankmachine5_state = 4'd0;
+reg [3:0] litedramcore_bankmachine5_next_state = 4'd0;
+reg [3:0] litedramcore_bankmachine6_state = 4'd0;
+reg [3:0] litedramcore_bankmachine6_next_state = 4'd0;
+reg [3:0] litedramcore_bankmachine7_state = 4'd0;
+reg [3:0] litedramcore_bankmachine7_next_state = 4'd0;
+reg [3:0] litedramcore_multiplexer_state = 4'd0;
+reg [3:0] litedramcore_multiplexer_next_state = 4'd0;
+wire litedramcore_roundrobin0_request;
+wire litedramcore_roundrobin0_grant;
+wire litedramcore_roundrobin0_ce;
+wire litedramcore_roundrobin1_request;
+wire litedramcore_roundrobin1_grant;
+wire litedramcore_roundrobin1_ce;
+wire litedramcore_roundrobin2_request;
+wire litedramcore_roundrobin2_grant;
+wire litedramcore_roundrobin2_ce;
+wire litedramcore_roundrobin3_request;
+wire litedramcore_roundrobin3_grant;
+wire litedramcore_roundrobin3_ce;
+wire litedramcore_roundrobin4_request;
+wire litedramcore_roundrobin4_grant;
+wire litedramcore_roundrobin4_ce;
+wire litedramcore_roundrobin5_request;
+wire litedramcore_roundrobin5_grant;
+wire litedramcore_roundrobin5_ce;
+wire litedramcore_roundrobin6_request;
+wire litedramcore_roundrobin6_grant;
+wire litedramcore_roundrobin6_ce;
+wire litedramcore_roundrobin7_request;
+wire litedramcore_roundrobin7_grant;
+wire litedramcore_roundrobin7_ce;
+reg litedramcore_locked0 = 1'd0;
+reg litedramcore_locked1 = 1'd0;
+reg litedramcore_locked2 = 1'd0;
+reg litedramcore_locked3 = 1'd0;
+reg litedramcore_locked4 = 1'd0;
+reg litedramcore_locked5 = 1'd0;
+reg litedramcore_locked6 = 1'd0;
+reg litedramcore_locked7 = 1'd0;
+reg litedramcore_new_master_wdata_ready0 = 1'd0;
+reg litedramcore_new_master_wdata_ready1 = 1'd0;
+reg litedramcore_new_master_rdata_valid0 = 1'd0;
+reg litedramcore_new_master_rdata_valid1 = 1'd0;
+reg litedramcore_new_master_rdata_valid2 = 1'd0;
+reg litedramcore_new_master_rdata_valid3 = 1'd0;
+reg litedramcore_new_master_rdata_valid4 = 1'd0;
+reg litedramcore_new_master_rdata_valid5 = 1'd0;
+reg litedramcore_new_master_rdata_valid6 = 1'd0;
+reg litedramcore_new_master_rdata_valid7 = 1'd0;
+reg litedramcore_new_master_rdata_valid8 = 1'd0;
+reg [1:0] litedramcore_state = 2'd0;
+reg [1:0] litedramcore_next_state = 2'd0;
+reg [31:0] litedramcore_dat_w_next_value0 = 32'd0;
+reg litedramcore_dat_w_next_value_ce0 = 1'd0;
+reg [13:0] litedramcore_adr_next_value1 = 14'd0;
+reg litedramcore_adr_next_value_ce1 = 1'd0;
+reg litedramcore_we_next_value2 = 1'd0;
+reg litedramcore_we_next_value_ce2 = 1'd0;
+reg rhs_array_muxed0 = 1'd0;
+reg [15:0] rhs_array_muxed1 = 16'd0;
+reg [2:0] rhs_array_muxed2 = 3'd0;
+reg rhs_array_muxed3 = 1'd0;
+reg rhs_array_muxed4 = 1'd0;
+reg rhs_array_muxed5 = 1'd0;
+reg t_array_muxed0 = 1'd0;
+reg t_array_muxed1 = 1'd0;
+reg t_array_muxed2 = 1'd0;
+reg rhs_array_muxed6 = 1'd0;
+reg [15:0] rhs_array_muxed7 = 16'd0;
+reg [2:0] rhs_array_muxed8 = 3'd0;
+reg rhs_array_muxed9 = 1'd0;
+reg rhs_array_muxed10 = 1'd0;
+reg rhs_array_muxed11 = 1'd0;
+reg t_array_muxed3 = 1'd0;
+reg t_array_muxed4 = 1'd0;
+reg t_array_muxed5 = 1'd0;
+reg [22:0] rhs_array_muxed12 = 23'd0;
+reg rhs_array_muxed13 = 1'd0;
+reg rhs_array_muxed14 = 1'd0;
+reg [22:0] rhs_array_muxed15 = 23'd0;
+reg rhs_array_muxed16 = 1'd0;
+reg rhs_array_muxed17 = 1'd0;
+reg [22:0] rhs_array_muxed18 = 23'd0;
+reg rhs_array_muxed19 = 1'd0;
+reg rhs_array_muxed20 = 1'd0;
+reg [22:0] rhs_array_muxed21 = 23'd0;
+reg rhs_array_muxed22 = 1'd0;
+reg rhs_array_muxed23 = 1'd0;
+reg [22:0] rhs_array_muxed24 = 23'd0;
+reg rhs_array_muxed25 = 1'd0;
+reg rhs_array_muxed26 = 1'd0;
+reg [22:0] rhs_array_muxed27 = 23'd0;
+reg rhs_array_muxed28 = 1'd0;
+reg rhs_array_muxed29 = 1'd0;
+reg [22:0] rhs_array_muxed30 = 23'd0;
+reg rhs_array_muxed31 = 1'd0;
+reg rhs_array_muxed32 = 1'd0;
+reg [22:0] rhs_array_muxed33 = 23'd0;
+reg rhs_array_muxed34 = 1'd0;
+reg rhs_array_muxed35 = 1'd0;
+reg [2:0] array_muxed0 = 3'd0;
+reg [15:0] array_muxed1 = 16'd0;
+reg array_muxed2 = 1'd0;
+reg array_muxed3 = 1'd0;
+reg array_muxed4 = 1'd0;
+reg array_muxed5 = 1'd0;
+reg array_muxed6 = 1'd0;
+reg [2:0] array_muxed7 = 3'd0;
+reg [15:0] array_muxed8 = 16'd0;
+reg array_muxed9 = 1'd0;
+reg array_muxed10 = 1'd0;
+reg array_muxed11 = 1'd0;
+reg array_muxed12 = 1'd0;
+reg array_muxed13 = 1'd0;
+reg [2:0] array_muxed14 = 3'd0;
+reg [15:0] array_muxed15 = 16'd0;
+reg array_muxed16 = 1'd0;
+reg array_muxed17 = 1'd0;
+reg array_muxed18 = 1'd0;
+reg array_muxed19 = 1'd0;
+reg array_muxed20 = 1'd0;
+reg [2:0] array_muxed21 = 3'd0;
+reg [15:0] array_muxed22 = 16'd0;
+reg array_muxed23 = 1'd0;
+reg array_muxed24 = 1'd0;
+reg array_muxed25 = 1'd0;
+reg array_muxed26 = 1'd0;
+reg array_muxed27 = 1'd0;
+wire xilinxasyncresetsynchronizerimpl0;
+wire xilinxasyncresetsynchronizerimpl0_rst_meta;
+wire xilinxasyncresetsynchronizerimpl1;
+wire xilinxasyncresetsynchronizerimpl1_rst_meta;
+wire xilinxasyncresetsynchronizerimpl2;
+wire xilinxasyncresetsynchronizerimpl2_rst_meta;
+wire xilinxasyncresetsynchronizerimpl2_expr;
+wire xilinxasyncresetsynchronizerimpl3;
+wire xilinxasyncresetsynchronizerimpl3_rst_meta;
+wire xilinxasyncresetsynchronizerimpl3_expr;
//------------------------------------------------------------------------------
// Combinatorial Logic
assign a7ddrphy_dqs_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dqs_oe) | a7ddrphy_dqs_postamble);
assign a7ddrphy_dq_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dq_oe) | a7ddrphy_dqs_postamble);
always @(*) begin
- a7ddrphy_dfi_p0_rddata <= 32'd0;
- a7ddrphy_dfi_p0_rddata[0] <= a7ddrphy_bitslip04[0];
- a7ddrphy_dfi_p0_rddata[16] <= a7ddrphy_bitslip04[1];
- a7ddrphy_dfi_p0_rddata[1] <= a7ddrphy_bitslip14[0];
- a7ddrphy_dfi_p0_rddata[17] <= a7ddrphy_bitslip14[1];
- a7ddrphy_dfi_p0_rddata[2] <= a7ddrphy_bitslip22[0];
- a7ddrphy_dfi_p0_rddata[18] <= a7ddrphy_bitslip22[1];
- a7ddrphy_dfi_p0_rddata[3] <= a7ddrphy_bitslip32[0];
- a7ddrphy_dfi_p0_rddata[19] <= a7ddrphy_bitslip32[1];
- a7ddrphy_dfi_p0_rddata[4] <= a7ddrphy_bitslip42[0];
- a7ddrphy_dfi_p0_rddata[20] <= a7ddrphy_bitslip42[1];
- a7ddrphy_dfi_p0_rddata[5] <= a7ddrphy_bitslip52[0];
- a7ddrphy_dfi_p0_rddata[21] <= a7ddrphy_bitslip52[1];
- a7ddrphy_dfi_p0_rddata[6] <= a7ddrphy_bitslip62[0];
- a7ddrphy_dfi_p0_rddata[22] <= a7ddrphy_bitslip62[1];
- a7ddrphy_dfi_p0_rddata[7] <= a7ddrphy_bitslip72[0];
- a7ddrphy_dfi_p0_rddata[23] <= a7ddrphy_bitslip72[1];
- a7ddrphy_dfi_p0_rddata[8] <= a7ddrphy_bitslip82[0];
- a7ddrphy_dfi_p0_rddata[24] <= a7ddrphy_bitslip82[1];
- a7ddrphy_dfi_p0_rddata[9] <= a7ddrphy_bitslip92[0];
- a7ddrphy_dfi_p0_rddata[25] <= a7ddrphy_bitslip92[1];
- a7ddrphy_dfi_p0_rddata[10] <= a7ddrphy_bitslip102[0];
- a7ddrphy_dfi_p0_rddata[26] <= a7ddrphy_bitslip102[1];
- a7ddrphy_dfi_p0_rddata[11] <= a7ddrphy_bitslip112[0];
- a7ddrphy_dfi_p0_rddata[27] <= a7ddrphy_bitslip112[1];
- a7ddrphy_dfi_p0_rddata[12] <= a7ddrphy_bitslip122[0];
- a7ddrphy_dfi_p0_rddata[28] <= a7ddrphy_bitslip122[1];
- a7ddrphy_dfi_p0_rddata[13] <= a7ddrphy_bitslip132[0];
- a7ddrphy_dfi_p0_rddata[29] <= a7ddrphy_bitslip132[1];
- a7ddrphy_dfi_p0_rddata[14] <= a7ddrphy_bitslip142[0];
- a7ddrphy_dfi_p0_rddata[30] <= a7ddrphy_bitslip142[1];
- a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip152[0];
- a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip152[1];
-end
-always @(*) begin
- a7ddrphy_dfi_p1_rddata <= 32'd0;
- a7ddrphy_dfi_p1_rddata[0] <= a7ddrphy_bitslip04[2];
- a7ddrphy_dfi_p1_rddata[16] <= a7ddrphy_bitslip04[3];
- a7ddrphy_dfi_p1_rddata[1] <= a7ddrphy_bitslip14[2];
- a7ddrphy_dfi_p1_rddata[17] <= a7ddrphy_bitslip14[3];
- a7ddrphy_dfi_p1_rddata[2] <= a7ddrphy_bitslip22[2];
- a7ddrphy_dfi_p1_rddata[18] <= a7ddrphy_bitslip22[3];
- a7ddrphy_dfi_p1_rddata[3] <= a7ddrphy_bitslip32[2];
- a7ddrphy_dfi_p1_rddata[19] <= a7ddrphy_bitslip32[3];
- a7ddrphy_dfi_p1_rddata[4] <= a7ddrphy_bitslip42[2];
- a7ddrphy_dfi_p1_rddata[20] <= a7ddrphy_bitslip42[3];
- a7ddrphy_dfi_p1_rddata[5] <= a7ddrphy_bitslip52[2];
- a7ddrphy_dfi_p1_rddata[21] <= a7ddrphy_bitslip52[3];
- a7ddrphy_dfi_p1_rddata[6] <= a7ddrphy_bitslip62[2];
- a7ddrphy_dfi_p1_rddata[22] <= a7ddrphy_bitslip62[3];
- a7ddrphy_dfi_p1_rddata[7] <= a7ddrphy_bitslip72[2];
- a7ddrphy_dfi_p1_rddata[23] <= a7ddrphy_bitslip72[3];
- a7ddrphy_dfi_p1_rddata[8] <= a7ddrphy_bitslip82[2];
- a7ddrphy_dfi_p1_rddata[24] <= a7ddrphy_bitslip82[3];
- a7ddrphy_dfi_p1_rddata[9] <= a7ddrphy_bitslip92[2];
- a7ddrphy_dfi_p1_rddata[25] <= a7ddrphy_bitslip92[3];
- a7ddrphy_dfi_p1_rddata[10] <= a7ddrphy_bitslip102[2];
- a7ddrphy_dfi_p1_rddata[26] <= a7ddrphy_bitslip102[3];
- a7ddrphy_dfi_p1_rddata[11] <= a7ddrphy_bitslip112[2];
- a7ddrphy_dfi_p1_rddata[27] <= a7ddrphy_bitslip112[3];
- a7ddrphy_dfi_p1_rddata[12] <= a7ddrphy_bitslip122[2];
- a7ddrphy_dfi_p1_rddata[28] <= a7ddrphy_bitslip122[3];
- a7ddrphy_dfi_p1_rddata[13] <= a7ddrphy_bitslip132[2];
- a7ddrphy_dfi_p1_rddata[29] <= a7ddrphy_bitslip132[3];
- a7ddrphy_dfi_p1_rddata[14] <= a7ddrphy_bitslip142[2];
- a7ddrphy_dfi_p1_rddata[30] <= a7ddrphy_bitslip142[3];
- a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip152[2];
- a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip152[3];
-end
-always @(*) begin
- a7ddrphy_dfi_p2_rddata <= 32'd0;
- a7ddrphy_dfi_p2_rddata[0] <= a7ddrphy_bitslip04[4];
- a7ddrphy_dfi_p2_rddata[16] <= a7ddrphy_bitslip04[5];
- a7ddrphy_dfi_p2_rddata[1] <= a7ddrphy_bitslip14[4];
- a7ddrphy_dfi_p2_rddata[17] <= a7ddrphy_bitslip14[5];
- a7ddrphy_dfi_p2_rddata[2] <= a7ddrphy_bitslip22[4];
- a7ddrphy_dfi_p2_rddata[18] <= a7ddrphy_bitslip22[5];
- a7ddrphy_dfi_p2_rddata[3] <= a7ddrphy_bitslip32[4];
- a7ddrphy_dfi_p2_rddata[19] <= a7ddrphy_bitslip32[5];
- a7ddrphy_dfi_p2_rddata[4] <= a7ddrphy_bitslip42[4];
- a7ddrphy_dfi_p2_rddata[20] <= a7ddrphy_bitslip42[5];
- a7ddrphy_dfi_p2_rddata[5] <= a7ddrphy_bitslip52[4];
- a7ddrphy_dfi_p2_rddata[21] <= a7ddrphy_bitslip52[5];
- a7ddrphy_dfi_p2_rddata[6] <= a7ddrphy_bitslip62[4];
- a7ddrphy_dfi_p2_rddata[22] <= a7ddrphy_bitslip62[5];
- a7ddrphy_dfi_p2_rddata[7] <= a7ddrphy_bitslip72[4];
- a7ddrphy_dfi_p2_rddata[23] <= a7ddrphy_bitslip72[5];
- a7ddrphy_dfi_p2_rddata[8] <= a7ddrphy_bitslip82[4];
- a7ddrphy_dfi_p2_rddata[24] <= a7ddrphy_bitslip82[5];
- a7ddrphy_dfi_p2_rddata[9] <= a7ddrphy_bitslip92[4];
- a7ddrphy_dfi_p2_rddata[25] <= a7ddrphy_bitslip92[5];
- a7ddrphy_dfi_p2_rddata[10] <= a7ddrphy_bitslip102[4];
- a7ddrphy_dfi_p2_rddata[26] <= a7ddrphy_bitslip102[5];
- a7ddrphy_dfi_p2_rddata[11] <= a7ddrphy_bitslip112[4];
- a7ddrphy_dfi_p2_rddata[27] <= a7ddrphy_bitslip112[5];
- a7ddrphy_dfi_p2_rddata[12] <= a7ddrphy_bitslip122[4];
- a7ddrphy_dfi_p2_rddata[28] <= a7ddrphy_bitslip122[5];
- a7ddrphy_dfi_p2_rddata[13] <= a7ddrphy_bitslip132[4];
- a7ddrphy_dfi_p2_rddata[29] <= a7ddrphy_bitslip132[5];
- a7ddrphy_dfi_p2_rddata[14] <= a7ddrphy_bitslip142[4];
- a7ddrphy_dfi_p2_rddata[30] <= a7ddrphy_bitslip142[5];
- a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip152[4];
- a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip152[5];
-end
-always @(*) begin
- a7ddrphy_dfi_p3_rddata <= 32'd0;
- a7ddrphy_dfi_p3_rddata[0] <= a7ddrphy_bitslip04[6];
- a7ddrphy_dfi_p3_rddata[16] <= a7ddrphy_bitslip04[7];
- a7ddrphy_dfi_p3_rddata[1] <= a7ddrphy_bitslip14[6];
- a7ddrphy_dfi_p3_rddata[17] <= a7ddrphy_bitslip14[7];
- a7ddrphy_dfi_p3_rddata[2] <= a7ddrphy_bitslip22[6];
- a7ddrphy_dfi_p3_rddata[18] <= a7ddrphy_bitslip22[7];
- a7ddrphy_dfi_p3_rddata[3] <= a7ddrphy_bitslip32[6];
- a7ddrphy_dfi_p3_rddata[19] <= a7ddrphy_bitslip32[7];
- a7ddrphy_dfi_p3_rddata[4] <= a7ddrphy_bitslip42[6];
- a7ddrphy_dfi_p3_rddata[20] <= a7ddrphy_bitslip42[7];
- a7ddrphy_dfi_p3_rddata[5] <= a7ddrphy_bitslip52[6];
- a7ddrphy_dfi_p3_rddata[21] <= a7ddrphy_bitslip52[7];
- a7ddrphy_dfi_p3_rddata[6] <= a7ddrphy_bitslip62[6];
- a7ddrphy_dfi_p3_rddata[22] <= a7ddrphy_bitslip62[7];
- a7ddrphy_dfi_p3_rddata[7] <= a7ddrphy_bitslip72[6];
- a7ddrphy_dfi_p3_rddata[23] <= a7ddrphy_bitslip72[7];
- a7ddrphy_dfi_p3_rddata[8] <= a7ddrphy_bitslip82[6];
- a7ddrphy_dfi_p3_rddata[24] <= a7ddrphy_bitslip82[7];
- a7ddrphy_dfi_p3_rddata[9] <= a7ddrphy_bitslip92[6];
- a7ddrphy_dfi_p3_rddata[25] <= a7ddrphy_bitslip92[7];
- a7ddrphy_dfi_p3_rddata[10] <= a7ddrphy_bitslip102[6];
- a7ddrphy_dfi_p3_rddata[26] <= a7ddrphy_bitslip102[7];
- a7ddrphy_dfi_p3_rddata[11] <= a7ddrphy_bitslip112[6];
- a7ddrphy_dfi_p3_rddata[27] <= a7ddrphy_bitslip112[7];
- a7ddrphy_dfi_p3_rddata[12] <= a7ddrphy_bitslip122[6];
- a7ddrphy_dfi_p3_rddata[28] <= a7ddrphy_bitslip122[7];
- a7ddrphy_dfi_p3_rddata[13] <= a7ddrphy_bitslip132[6];
- a7ddrphy_dfi_p3_rddata[29] <= a7ddrphy_bitslip132[7];
- a7ddrphy_dfi_p3_rddata[14] <= a7ddrphy_bitslip142[6];
- a7ddrphy_dfi_p3_rddata[30] <= a7ddrphy_bitslip142[7];
- a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip152[6];
- a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip152[7];
+ a7ddrphy_dfi_p0_rddata <= 32'd0;
+ a7ddrphy_dfi_p0_rddata[0] <= a7ddrphy_bitslip04[0];
+ a7ddrphy_dfi_p0_rddata[16] <= a7ddrphy_bitslip04[1];
+ a7ddrphy_dfi_p0_rddata[1] <= a7ddrphy_bitslip14[0];
+ a7ddrphy_dfi_p0_rddata[17] <= a7ddrphy_bitslip14[1];
+ a7ddrphy_dfi_p0_rddata[2] <= a7ddrphy_bitslip22[0];
+ a7ddrphy_dfi_p0_rddata[18] <= a7ddrphy_bitslip22[1];
+ a7ddrphy_dfi_p0_rddata[3] <= a7ddrphy_bitslip32[0];
+ a7ddrphy_dfi_p0_rddata[19] <= a7ddrphy_bitslip32[1];
+ a7ddrphy_dfi_p0_rddata[4] <= a7ddrphy_bitslip42[0];
+ a7ddrphy_dfi_p0_rddata[20] <= a7ddrphy_bitslip42[1];
+ a7ddrphy_dfi_p0_rddata[5] <= a7ddrphy_bitslip52[0];
+ a7ddrphy_dfi_p0_rddata[21] <= a7ddrphy_bitslip52[1];
+ a7ddrphy_dfi_p0_rddata[6] <= a7ddrphy_bitslip62[0];
+ a7ddrphy_dfi_p0_rddata[22] <= a7ddrphy_bitslip62[1];
+ a7ddrphy_dfi_p0_rddata[7] <= a7ddrphy_bitslip72[0];
+ a7ddrphy_dfi_p0_rddata[23] <= a7ddrphy_bitslip72[1];
+ a7ddrphy_dfi_p0_rddata[8] <= a7ddrphy_bitslip82[0];
+ a7ddrphy_dfi_p0_rddata[24] <= a7ddrphy_bitslip82[1];
+ a7ddrphy_dfi_p0_rddata[9] <= a7ddrphy_bitslip92[0];
+ a7ddrphy_dfi_p0_rddata[25] <= a7ddrphy_bitslip92[1];
+ a7ddrphy_dfi_p0_rddata[10] <= a7ddrphy_bitslip102[0];
+ a7ddrphy_dfi_p0_rddata[26] <= a7ddrphy_bitslip102[1];
+ a7ddrphy_dfi_p0_rddata[11] <= a7ddrphy_bitslip112[0];
+ a7ddrphy_dfi_p0_rddata[27] <= a7ddrphy_bitslip112[1];
+ a7ddrphy_dfi_p0_rddata[12] <= a7ddrphy_bitslip122[0];
+ a7ddrphy_dfi_p0_rddata[28] <= a7ddrphy_bitslip122[1];
+ a7ddrphy_dfi_p0_rddata[13] <= a7ddrphy_bitslip132[0];
+ a7ddrphy_dfi_p0_rddata[29] <= a7ddrphy_bitslip132[1];
+ a7ddrphy_dfi_p0_rddata[14] <= a7ddrphy_bitslip142[0];
+ a7ddrphy_dfi_p0_rddata[30] <= a7ddrphy_bitslip142[1];
+ a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip152[0];
+ a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip152[1];
+end
+always @(*) begin
+ a7ddrphy_dfi_p1_rddata <= 32'd0;
+ a7ddrphy_dfi_p1_rddata[0] <= a7ddrphy_bitslip04[2];
+ a7ddrphy_dfi_p1_rddata[16] <= a7ddrphy_bitslip04[3];
+ a7ddrphy_dfi_p1_rddata[1] <= a7ddrphy_bitslip14[2];
+ a7ddrphy_dfi_p1_rddata[17] <= a7ddrphy_bitslip14[3];
+ a7ddrphy_dfi_p1_rddata[2] <= a7ddrphy_bitslip22[2];
+ a7ddrphy_dfi_p1_rddata[18] <= a7ddrphy_bitslip22[3];
+ a7ddrphy_dfi_p1_rddata[3] <= a7ddrphy_bitslip32[2];
+ a7ddrphy_dfi_p1_rddata[19] <= a7ddrphy_bitslip32[3];
+ a7ddrphy_dfi_p1_rddata[4] <= a7ddrphy_bitslip42[2];
+ a7ddrphy_dfi_p1_rddata[20] <= a7ddrphy_bitslip42[3];
+ a7ddrphy_dfi_p1_rddata[5] <= a7ddrphy_bitslip52[2];
+ a7ddrphy_dfi_p1_rddata[21] <= a7ddrphy_bitslip52[3];
+ a7ddrphy_dfi_p1_rddata[6] <= a7ddrphy_bitslip62[2];
+ a7ddrphy_dfi_p1_rddata[22] <= a7ddrphy_bitslip62[3];
+ a7ddrphy_dfi_p1_rddata[7] <= a7ddrphy_bitslip72[2];
+ a7ddrphy_dfi_p1_rddata[23] <= a7ddrphy_bitslip72[3];
+ a7ddrphy_dfi_p1_rddata[8] <= a7ddrphy_bitslip82[2];
+ a7ddrphy_dfi_p1_rddata[24] <= a7ddrphy_bitslip82[3];
+ a7ddrphy_dfi_p1_rddata[9] <= a7ddrphy_bitslip92[2];
+ a7ddrphy_dfi_p1_rddata[25] <= a7ddrphy_bitslip92[3];
+ a7ddrphy_dfi_p1_rddata[10] <= a7ddrphy_bitslip102[2];
+ a7ddrphy_dfi_p1_rddata[26] <= a7ddrphy_bitslip102[3];
+ a7ddrphy_dfi_p1_rddata[11] <= a7ddrphy_bitslip112[2];
+ a7ddrphy_dfi_p1_rddata[27] <= a7ddrphy_bitslip112[3];
+ a7ddrphy_dfi_p1_rddata[12] <= a7ddrphy_bitslip122[2];
+ a7ddrphy_dfi_p1_rddata[28] <= a7ddrphy_bitslip122[3];
+ a7ddrphy_dfi_p1_rddata[13] <= a7ddrphy_bitslip132[2];
+ a7ddrphy_dfi_p1_rddata[29] <= a7ddrphy_bitslip132[3];
+ a7ddrphy_dfi_p1_rddata[14] <= a7ddrphy_bitslip142[2];
+ a7ddrphy_dfi_p1_rddata[30] <= a7ddrphy_bitslip142[3];
+ a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip152[2];
+ a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip152[3];
+end
+always @(*) begin
+ a7ddrphy_dfi_p2_rddata <= 32'd0;
+ a7ddrphy_dfi_p2_rddata[0] <= a7ddrphy_bitslip04[4];
+ a7ddrphy_dfi_p2_rddata[16] <= a7ddrphy_bitslip04[5];
+ a7ddrphy_dfi_p2_rddata[1] <= a7ddrphy_bitslip14[4];
+ a7ddrphy_dfi_p2_rddata[17] <= a7ddrphy_bitslip14[5];
+ a7ddrphy_dfi_p2_rddata[2] <= a7ddrphy_bitslip22[4];
+ a7ddrphy_dfi_p2_rddata[18] <= a7ddrphy_bitslip22[5];
+ a7ddrphy_dfi_p2_rddata[3] <= a7ddrphy_bitslip32[4];
+ a7ddrphy_dfi_p2_rddata[19] <= a7ddrphy_bitslip32[5];
+ a7ddrphy_dfi_p2_rddata[4] <= a7ddrphy_bitslip42[4];
+ a7ddrphy_dfi_p2_rddata[20] <= a7ddrphy_bitslip42[5];
+ a7ddrphy_dfi_p2_rddata[5] <= a7ddrphy_bitslip52[4];
+ a7ddrphy_dfi_p2_rddata[21] <= a7ddrphy_bitslip52[5];
+ a7ddrphy_dfi_p2_rddata[6] <= a7ddrphy_bitslip62[4];
+ a7ddrphy_dfi_p2_rddata[22] <= a7ddrphy_bitslip62[5];
+ a7ddrphy_dfi_p2_rddata[7] <= a7ddrphy_bitslip72[4];
+ a7ddrphy_dfi_p2_rddata[23] <= a7ddrphy_bitslip72[5];
+ a7ddrphy_dfi_p2_rddata[8] <= a7ddrphy_bitslip82[4];
+ a7ddrphy_dfi_p2_rddata[24] <= a7ddrphy_bitslip82[5];
+ a7ddrphy_dfi_p2_rddata[9] <= a7ddrphy_bitslip92[4];
+ a7ddrphy_dfi_p2_rddata[25] <= a7ddrphy_bitslip92[5];
+ a7ddrphy_dfi_p2_rddata[10] <= a7ddrphy_bitslip102[4];
+ a7ddrphy_dfi_p2_rddata[26] <= a7ddrphy_bitslip102[5];
+ a7ddrphy_dfi_p2_rddata[11] <= a7ddrphy_bitslip112[4];
+ a7ddrphy_dfi_p2_rddata[27] <= a7ddrphy_bitslip112[5];
+ a7ddrphy_dfi_p2_rddata[12] <= a7ddrphy_bitslip122[4];
+ a7ddrphy_dfi_p2_rddata[28] <= a7ddrphy_bitslip122[5];
+ a7ddrphy_dfi_p2_rddata[13] <= a7ddrphy_bitslip132[4];
+ a7ddrphy_dfi_p2_rddata[29] <= a7ddrphy_bitslip132[5];
+ a7ddrphy_dfi_p2_rddata[14] <= a7ddrphy_bitslip142[4];
+ a7ddrphy_dfi_p2_rddata[30] <= a7ddrphy_bitslip142[5];
+ a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip152[4];
+ a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip152[5];
+end
+always @(*) begin
+ a7ddrphy_dfi_p3_rddata <= 32'd0;
+ a7ddrphy_dfi_p3_rddata[0] <= a7ddrphy_bitslip04[6];
+ a7ddrphy_dfi_p3_rddata[16] <= a7ddrphy_bitslip04[7];
+ a7ddrphy_dfi_p3_rddata[1] <= a7ddrphy_bitslip14[6];
+ a7ddrphy_dfi_p3_rddata[17] <= a7ddrphy_bitslip14[7];
+ a7ddrphy_dfi_p3_rddata[2] <= a7ddrphy_bitslip22[6];
+ a7ddrphy_dfi_p3_rddata[18] <= a7ddrphy_bitslip22[7];
+ a7ddrphy_dfi_p3_rddata[3] <= a7ddrphy_bitslip32[6];
+ a7ddrphy_dfi_p3_rddata[19] <= a7ddrphy_bitslip32[7];
+ a7ddrphy_dfi_p3_rddata[4] <= a7ddrphy_bitslip42[6];
+ a7ddrphy_dfi_p3_rddata[20] <= a7ddrphy_bitslip42[7];
+ a7ddrphy_dfi_p3_rddata[5] <= a7ddrphy_bitslip52[6];
+ a7ddrphy_dfi_p3_rddata[21] <= a7ddrphy_bitslip52[7];
+ a7ddrphy_dfi_p3_rddata[6] <= a7ddrphy_bitslip62[6];
+ a7ddrphy_dfi_p3_rddata[22] <= a7ddrphy_bitslip62[7];
+ a7ddrphy_dfi_p3_rddata[7] <= a7ddrphy_bitslip72[6];
+ a7ddrphy_dfi_p3_rddata[23] <= a7ddrphy_bitslip72[7];
+ a7ddrphy_dfi_p3_rddata[8] <= a7ddrphy_bitslip82[6];
+ a7ddrphy_dfi_p3_rddata[24] <= a7ddrphy_bitslip82[7];
+ a7ddrphy_dfi_p3_rddata[9] <= a7ddrphy_bitslip92[6];
+ a7ddrphy_dfi_p3_rddata[25] <= a7ddrphy_bitslip92[7];
+ a7ddrphy_dfi_p3_rddata[10] <= a7ddrphy_bitslip102[6];
+ a7ddrphy_dfi_p3_rddata[26] <= a7ddrphy_bitslip102[7];
+ a7ddrphy_dfi_p3_rddata[11] <= a7ddrphy_bitslip112[6];
+ a7ddrphy_dfi_p3_rddata[27] <= a7ddrphy_bitslip112[7];
+ a7ddrphy_dfi_p3_rddata[12] <= a7ddrphy_bitslip122[6];
+ a7ddrphy_dfi_p3_rddata[28] <= a7ddrphy_bitslip122[7];
+ a7ddrphy_dfi_p3_rddata[13] <= a7ddrphy_bitslip132[6];
+ a7ddrphy_dfi_p3_rddata[29] <= a7ddrphy_bitslip132[7];
+ a7ddrphy_dfi_p3_rddata[14] <= a7ddrphy_bitslip142[6];
+ a7ddrphy_dfi_p3_rddata[30] <= a7ddrphy_bitslip142[7];
+ a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip152[6];
+ a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip152[7];
end
assign a7ddrphy_dfi_p0_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage);
assign a7ddrphy_dfi_p1_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage);
assign a7ddrphy_dfi_p3_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage);
assign a7ddrphy_dq_oe = a7ddrphy_wrdata_en_tappeddelayline1;
always @(*) begin
- a7ddrphy_dqs_oe <= 1'd0;
- if (a7ddrphy_wlevel_en_storage) begin
- a7ddrphy_dqs_oe <= 1'd1;
- end else begin
- a7ddrphy_dqs_oe <= a7ddrphy_dq_oe;
- end
+ a7ddrphy_dqs_oe <= 1'd0;
+ if (a7ddrphy_wlevel_en_storage) begin
+ a7ddrphy_dqs_oe <= 1'd1;
+ end else begin
+ a7ddrphy_dqs_oe <= a7ddrphy_dq_oe;
+ end
end
assign a7ddrphy_dqs_preamble = (a7ddrphy_wrdata_en_tappeddelayline0 & (~a7ddrphy_wrdata_en_tappeddelayline1));
assign a7ddrphy_dqs_postamble = (a7ddrphy_wrdata_en_tappeddelayline2 & (~a7ddrphy_wrdata_en_tappeddelayline1));
always @(*) begin
- a7ddrphy_dqspattern_o0 <= 8'd0;
- a7ddrphy_dqspattern_o0 <= 7'd85;
- if (a7ddrphy_dqspattern0) begin
- a7ddrphy_dqspattern_o0 <= 5'd21;
- end
- if (a7ddrphy_dqspattern1) begin
- a7ddrphy_dqspattern_o0 <= 7'd84;
- end
- if (a7ddrphy_wlevel_en_storage) begin
- a7ddrphy_dqspattern_o0 <= 1'd0;
- if (a7ddrphy_wlevel_strobe_re) begin
- a7ddrphy_dqspattern_o0 <= 1'd1;
- end
- end
-end
-always @(*) begin
- a7ddrphy_bitslip00 <= 8'd0;
- case (a7ddrphy_bitslip0_value0)
- 1'd0: begin
- a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip10 <= 8'd0;
- case (a7ddrphy_bitslip1_value0)
- 1'd0: begin
- a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip01 <= 8'd0;
- case (a7ddrphy_bitslip0_value1)
- 1'd0: begin
- a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip11 <= 8'd0;
- case (a7ddrphy_bitslip1_value1)
- 1'd0: begin
- a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip02 <= 8'd0;
- case (a7ddrphy_bitslip0_value2)
- 1'd0: begin
- a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip04 <= 8'd0;
- case (a7ddrphy_bitslip0_value3)
- 1'd0: begin
- a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip12 <= 8'd0;
- case (a7ddrphy_bitslip1_value2)
- 1'd0: begin
- a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip14 <= 8'd0;
- case (a7ddrphy_bitslip1_value3)
- 1'd0: begin
- a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip20 <= 8'd0;
- case (a7ddrphy_bitslip2_value0)
- 1'd0: begin
- a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip22 <= 8'd0;
- case (a7ddrphy_bitslip2_value1)
- 1'd0: begin
- a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip30 <= 8'd0;
- case (a7ddrphy_bitslip3_value0)
- 1'd0: begin
- a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip32 <= 8'd0;
- case (a7ddrphy_bitslip3_value1)
- 1'd0: begin
- a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip40 <= 8'd0;
- case (a7ddrphy_bitslip4_value0)
- 1'd0: begin
- a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip42 <= 8'd0;
- case (a7ddrphy_bitslip4_value1)
- 1'd0: begin
- a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip50 <= 8'd0;
- case (a7ddrphy_bitslip5_value0)
- 1'd0: begin
- a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip52 <= 8'd0;
- case (a7ddrphy_bitslip5_value1)
- 1'd0: begin
- a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip60 <= 8'd0;
- case (a7ddrphy_bitslip6_value0)
- 1'd0: begin
- a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip62 <= 8'd0;
- case (a7ddrphy_bitslip6_value1)
- 1'd0: begin
- a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip70 <= 8'd0;
- case (a7ddrphy_bitslip7_value0)
- 1'd0: begin
- a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip72 <= 8'd0;
- case (a7ddrphy_bitslip7_value1)
- 1'd0: begin
- a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip80 <= 8'd0;
- case (a7ddrphy_bitslip8_value0)
- 1'd0: begin
- a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip82 <= 8'd0;
- case (a7ddrphy_bitslip8_value1)
- 1'd0: begin
- a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip90 <= 8'd0;
- case (a7ddrphy_bitslip9_value0)
- 1'd0: begin
- a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip92 <= 8'd0;
- case (a7ddrphy_bitslip9_value1)
- 1'd0: begin
- a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip100 <= 8'd0;
- case (a7ddrphy_bitslip10_value0)
- 1'd0: begin
- a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip102 <= 8'd0;
- case (a7ddrphy_bitslip10_value1)
- 1'd0: begin
- a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip110 <= 8'd0;
- case (a7ddrphy_bitslip11_value0)
- 1'd0: begin
- a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip112 <= 8'd0;
- case (a7ddrphy_bitslip11_value1)
- 1'd0: begin
- a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip120 <= 8'd0;
- case (a7ddrphy_bitslip12_value0)
- 1'd0: begin
- a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip122 <= 8'd0;
- case (a7ddrphy_bitslip12_value1)
- 1'd0: begin
- a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip130 <= 8'd0;
- case (a7ddrphy_bitslip13_value0)
- 1'd0: begin
- a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip132 <= 8'd0;
- case (a7ddrphy_bitslip13_value1)
- 1'd0: begin
- a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip140 <= 8'd0;
- case (a7ddrphy_bitslip14_value0)
- 1'd0: begin
- a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip142 <= 8'd0;
- case (a7ddrphy_bitslip14_value1)
- 1'd0: begin
- a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip150 <= 8'd0;
- case (a7ddrphy_bitslip15_value0)
- 1'd0: begin
- a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip152 <= 8'd0;
- case (a7ddrphy_bitslip15_value1)
- 1'd0: begin
- a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[15:8];
- end
- endcase
+ a7ddrphy_dqspattern_o0 <= 8'd0;
+ a7ddrphy_dqspattern_o0 <= 7'd85;
+ if (a7ddrphy_dqspattern0) begin
+ a7ddrphy_dqspattern_o0 <= 5'd21;
+ end
+ if (a7ddrphy_dqspattern1) begin
+ a7ddrphy_dqspattern_o0 <= 7'd84;
+ end
+ if (a7ddrphy_wlevel_en_storage) begin
+ a7ddrphy_dqspattern_o0 <= 1'd0;
+ if (a7ddrphy_wlevel_strobe_re) begin
+ a7ddrphy_dqspattern_o0 <= 1'd1;
+ end
+ end
+end
+always @(*) begin
+ a7ddrphy_bitslip00 <= 8'd0;
+ case (a7ddrphy_bitslip0_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip10 <= 8'd0;
+ case (a7ddrphy_bitslip1_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip01 <= 8'd0;
+ case (a7ddrphy_bitslip0_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip11 <= 8'd0;
+ case (a7ddrphy_bitslip1_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip02 <= 8'd0;
+ case (a7ddrphy_bitslip0_value2)
+ 1'd0: begin
+ a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip04 <= 8'd0;
+ case (a7ddrphy_bitslip0_value3)
+ 1'd0: begin
+ a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip12 <= 8'd0;
+ case (a7ddrphy_bitslip1_value2)
+ 1'd0: begin
+ a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip14 <= 8'd0;
+ case (a7ddrphy_bitslip1_value3)
+ 1'd0: begin
+ a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip20 <= 8'd0;
+ case (a7ddrphy_bitslip2_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip22 <= 8'd0;
+ case (a7ddrphy_bitslip2_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip30 <= 8'd0;
+ case (a7ddrphy_bitslip3_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip32 <= 8'd0;
+ case (a7ddrphy_bitslip3_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip40 <= 8'd0;
+ case (a7ddrphy_bitslip4_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip42 <= 8'd0;
+ case (a7ddrphy_bitslip4_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip50 <= 8'd0;
+ case (a7ddrphy_bitslip5_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip52 <= 8'd0;
+ case (a7ddrphy_bitslip5_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip60 <= 8'd0;
+ case (a7ddrphy_bitslip6_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip62 <= 8'd0;
+ case (a7ddrphy_bitslip6_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip70 <= 8'd0;
+ case (a7ddrphy_bitslip7_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip72 <= 8'd0;
+ case (a7ddrphy_bitslip7_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip80 <= 8'd0;
+ case (a7ddrphy_bitslip8_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip82 <= 8'd0;
+ case (a7ddrphy_bitslip8_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip90 <= 8'd0;
+ case (a7ddrphy_bitslip9_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip92 <= 8'd0;
+ case (a7ddrphy_bitslip9_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip100 <= 8'd0;
+ case (a7ddrphy_bitslip10_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip102 <= 8'd0;
+ case (a7ddrphy_bitslip10_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip110 <= 8'd0;
+ case (a7ddrphy_bitslip11_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip112 <= 8'd0;
+ case (a7ddrphy_bitslip11_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip120 <= 8'd0;
+ case (a7ddrphy_bitslip12_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip122 <= 8'd0;
+ case (a7ddrphy_bitslip12_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip130 <= 8'd0;
+ case (a7ddrphy_bitslip13_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip132 <= 8'd0;
+ case (a7ddrphy_bitslip13_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip140 <= 8'd0;
+ case (a7ddrphy_bitslip14_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip142 <= 8'd0;
+ case (a7ddrphy_bitslip14_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip150 <= 8'd0;
+ case (a7ddrphy_bitslip15_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip152 <= 8'd0;
+ case (a7ddrphy_bitslip15_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[15:8];
+ end
+ endcase
end
assign a7ddrphy_dfi_p0_address = litedramcore_master_p0_address;
assign a7ddrphy_dfi_p0_bank = litedramcore_master_p0_bank;
assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata;
assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid;
always @(*) begin
- litedramcore_master_p3_ras_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_ras_n <= litedramcore_ext_dfi_p3_ras_n;
- end else begin
- litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n;
- end
- end else begin
- litedramcore_master_p3_ras_n <= litedramcore_csr_dfi_p3_ras_n;
- end
-end
-always @(*) begin
- litedramcore_master_p3_we_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_we_n <= litedramcore_ext_dfi_p3_we_n;
- end else begin
- litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n;
- end
- end else begin
- litedramcore_master_p3_we_n <= litedramcore_csr_dfi_p3_we_n;
- end
-end
-always @(*) begin
- litedramcore_master_p3_cke <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_cke <= litedramcore_ext_dfi_p3_cke;
- end else begin
- litedramcore_master_p3_cke <= litedramcore_slave_p3_cke;
- end
- end else begin
- litedramcore_master_p3_cke <= litedramcore_csr_dfi_p3_cke;
- end
-end
-always @(*) begin
- litedramcore_master_p3_odt <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_odt <= litedramcore_ext_dfi_p3_odt;
- end else begin
- litedramcore_master_p3_odt <= litedramcore_slave_p3_odt;
- end
- end else begin
- litedramcore_master_p3_odt <= litedramcore_csr_dfi_p3_odt;
- end
-end
-always @(*) begin
- litedramcore_master_p3_reset_n <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_reset_n <= litedramcore_ext_dfi_p3_reset_n;
- end else begin
- litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n;
- end
- end else begin
- litedramcore_master_p3_reset_n <= litedramcore_csr_dfi_p3_reset_n;
- end
-end
-always @(*) begin
- litedramcore_master_p3_act_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_act_n <= litedramcore_ext_dfi_p3_act_n;
- end else begin
- litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n;
- end
- end else begin
- litedramcore_master_p3_act_n <= litedramcore_csr_dfi_p3_act_n;
- end
-end
-always @(*) begin
- litedramcore_master_p3_wrdata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_wrdata <= litedramcore_ext_dfi_p3_wrdata;
- end else begin
- litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata;
- end
- end else begin
- litedramcore_master_p3_wrdata <= litedramcore_csr_dfi_p3_wrdata;
- end
-end
-always @(*) begin
- litedramcore_master_p3_wrdata_en <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_wrdata_en <= litedramcore_ext_dfi_p3_wrdata_en;
- end else begin
- litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en;
- end
- end else begin
- litedramcore_master_p3_wrdata_en <= litedramcore_csr_dfi_p3_wrdata_en;
- end
-end
-always @(*) begin
- litedramcore_master_p3_wrdata_mask <= 4'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_wrdata_mask <= litedramcore_ext_dfi_p3_wrdata_mask;
- end else begin
- litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask;
- end
- end else begin
- litedramcore_master_p3_wrdata_mask <= litedramcore_csr_dfi_p3_wrdata_mask;
- end
-end
-always @(*) begin
- litedramcore_master_p3_rddata_en <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_rddata_en <= litedramcore_ext_dfi_p3_rddata_en;
- end else begin
- litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en;
- end
- end else begin
- litedramcore_master_p3_rddata_en <= litedramcore_csr_dfi_p3_rddata_en;
- end
-end
-always @(*) begin
- litedramcore_csr_dfi_p0_rddata <= 32'd0;
- if (litedramcore_sel) begin
- end else begin
- litedramcore_csr_dfi_p0_rddata <= litedramcore_master_p0_rddata;
- end
-end
-always @(*) begin
- litedramcore_csr_dfi_p0_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- end else begin
- litedramcore_csr_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
- end
-end
-always @(*) begin
- litedramcore_csr_dfi_p1_rddata <= 32'd0;
- if (litedramcore_sel) begin
- end else begin
- litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata;
- end
-end
-always @(*) begin
- litedramcore_csr_dfi_p1_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- end else begin
- litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
- end
-end
-always @(*) begin
- litedramcore_csr_dfi_p2_rddata <= 32'd0;
- if (litedramcore_sel) begin
- end else begin
- litedramcore_csr_dfi_p2_rddata <= litedramcore_master_p2_rddata;
- end
-end
-always @(*) begin
- litedramcore_csr_dfi_p2_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- end else begin
- litedramcore_csr_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
- end
-end
-always @(*) begin
- litedramcore_csr_dfi_p3_rddata <= 32'd0;
- if (litedramcore_sel) begin
- end else begin
- litedramcore_csr_dfi_p3_rddata <= litedramcore_master_p3_rddata;
- end
-end
-always @(*) begin
- litedramcore_csr_dfi_p3_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- end else begin
- litedramcore_csr_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
- end
-end
-always @(*) begin
- litedramcore_ext_dfi_p0_rddata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_ext_dfi_p0_rddata <= litedramcore_master_p0_rddata;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_ext_dfi_p0_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_ext_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_ext_dfi_p1_rddata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_ext_dfi_p1_rddata <= litedramcore_master_p1_rddata;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_ext_dfi_p1_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_ext_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_ext_dfi_p2_rddata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_ext_dfi_p2_rddata <= litedramcore_master_p2_rddata;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_ext_dfi_p2_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_ext_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_slave_p0_rddata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- end else begin
- litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata;
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_slave_p0_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- end else begin
- litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_ext_dfi_p3_rddata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_ext_dfi_p3_rddata <= litedramcore_master_p3_rddata;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_ext_dfi_p3_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_ext_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_slave_p1_rddata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- end else begin
- litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata;
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_slave_p1_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- end else begin
- litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_slave_p2_rddata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- end else begin
- litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata;
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_slave_p2_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- end else begin
- litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_slave_p3_rddata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- end else begin
- litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata;
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_slave_p3_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- end else begin
- litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_master_p0_address <= 16'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_address <= litedramcore_ext_dfi_p0_address;
- end else begin
- litedramcore_master_p0_address <= litedramcore_slave_p0_address;
- end
- end else begin
- litedramcore_master_p0_address <= litedramcore_csr_dfi_p0_address;
- end
-end
-always @(*) begin
- litedramcore_master_p0_bank <= 3'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_bank <= litedramcore_ext_dfi_p0_bank;
- end else begin
- litedramcore_master_p0_bank <= litedramcore_slave_p0_bank;
- end
- end else begin
- litedramcore_master_p0_bank <= litedramcore_csr_dfi_p0_bank;
- end
-end
-always @(*) begin
- litedramcore_master_p0_cas_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_cas_n <= litedramcore_ext_dfi_p0_cas_n;
- end else begin
- litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n;
- end
- end else begin
- litedramcore_master_p0_cas_n <= litedramcore_csr_dfi_p0_cas_n;
- end
-end
-always @(*) begin
- litedramcore_master_p0_cs_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n;
- end else begin
- litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n;
- end
- end else begin
- litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n;
- end
-end
-always @(*) begin
- litedramcore_master_p0_ras_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n;
- end else begin
- litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n;
- end
- end else begin
- litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n;
- end
-end
-always @(*) begin
- litedramcore_master_p0_we_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n;
- end else begin
- litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n;
- end
- end else begin
- litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n;
- end
-end
-always @(*) begin
- litedramcore_master_p0_cke <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_cke <= litedramcore_ext_dfi_p0_cke;
- end else begin
- litedramcore_master_p0_cke <= litedramcore_slave_p0_cke;
- end
- end else begin
- litedramcore_master_p0_cke <= litedramcore_csr_dfi_p0_cke;
- end
-end
-always @(*) begin
- litedramcore_master_p0_odt <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_odt <= litedramcore_ext_dfi_p0_odt;
- end else begin
- litedramcore_master_p0_odt <= litedramcore_slave_p0_odt;
- end
- end else begin
- litedramcore_master_p0_odt <= litedramcore_csr_dfi_p0_odt;
- end
-end
-always @(*) begin
- litedramcore_master_p0_reset_n <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_reset_n <= litedramcore_ext_dfi_p0_reset_n;
- end else begin
- litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n;
- end
- end else begin
- litedramcore_master_p0_reset_n <= litedramcore_csr_dfi_p0_reset_n;
- end
-end
-always @(*) begin
- litedramcore_master_p0_act_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_act_n <= litedramcore_ext_dfi_p0_act_n;
- end else begin
- litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n;
- end
- end else begin
- litedramcore_master_p0_act_n <= litedramcore_csr_dfi_p0_act_n;
- end
-end
-always @(*) begin
- litedramcore_master_p0_wrdata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_wrdata <= litedramcore_ext_dfi_p0_wrdata;
- end else begin
- litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata;
- end
- end else begin
- litedramcore_master_p0_wrdata <= litedramcore_csr_dfi_p0_wrdata;
- end
-end
-always @(*) begin
- litedramcore_master_p0_wrdata_en <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_wrdata_en <= litedramcore_ext_dfi_p0_wrdata_en;
- end else begin
- litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en;
- end
- end else begin
- litedramcore_master_p0_wrdata_en <= litedramcore_csr_dfi_p0_wrdata_en;
- end
-end
-always @(*) begin
- litedramcore_master_p0_wrdata_mask <= 4'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_wrdata_mask <= litedramcore_ext_dfi_p0_wrdata_mask;
- end else begin
- litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask;
- end
- end else begin
- litedramcore_master_p0_wrdata_mask <= litedramcore_csr_dfi_p0_wrdata_mask;
- end
-end
-always @(*) begin
- litedramcore_master_p0_rddata_en <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_rddata_en <= litedramcore_ext_dfi_p0_rddata_en;
- end else begin
- litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en;
- end
- end else begin
- litedramcore_master_p0_rddata_en <= litedramcore_csr_dfi_p0_rddata_en;
- end
-end
-always @(*) begin
- litedramcore_master_p1_address <= 16'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_address <= litedramcore_ext_dfi_p1_address;
- end else begin
- litedramcore_master_p1_address <= litedramcore_slave_p1_address;
- end
- end else begin
- litedramcore_master_p1_address <= litedramcore_csr_dfi_p1_address;
- end
-end
-always @(*) begin
- litedramcore_master_p1_bank <= 3'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_bank <= litedramcore_ext_dfi_p1_bank;
- end else begin
- litedramcore_master_p1_bank <= litedramcore_slave_p1_bank;
- end
- end else begin
- litedramcore_master_p1_bank <= litedramcore_csr_dfi_p1_bank;
- end
-end
-always @(*) begin
- litedramcore_master_p1_cas_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_cas_n <= litedramcore_ext_dfi_p1_cas_n;
- end else begin
- litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n;
- end
- end else begin
- litedramcore_master_p1_cas_n <= litedramcore_csr_dfi_p1_cas_n;
- end
-end
-always @(*) begin
- litedramcore_master_p1_cs_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_cs_n <= litedramcore_ext_dfi_p1_cs_n;
- end else begin
- litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n;
- end
- end else begin
- litedramcore_master_p1_cs_n <= litedramcore_csr_dfi_p1_cs_n;
- end
-end
-always @(*) begin
- litedramcore_master_p1_ras_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_ras_n <= litedramcore_ext_dfi_p1_ras_n;
- end else begin
- litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n;
- end
- end else begin
- litedramcore_master_p1_ras_n <= litedramcore_csr_dfi_p1_ras_n;
- end
-end
-always @(*) begin
- litedramcore_master_p1_we_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_we_n <= litedramcore_ext_dfi_p1_we_n;
- end else begin
- litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n;
- end
- end else begin
- litedramcore_master_p1_we_n <= litedramcore_csr_dfi_p1_we_n;
- end
-end
-always @(*) begin
- litedramcore_master_p1_cke <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_cke <= litedramcore_ext_dfi_p1_cke;
- end else begin
- litedramcore_master_p1_cke <= litedramcore_slave_p1_cke;
- end
- end else begin
- litedramcore_master_p1_cke <= litedramcore_csr_dfi_p1_cke;
- end
-end
-always @(*) begin
- litedramcore_master_p1_odt <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_odt <= litedramcore_ext_dfi_p1_odt;
- end else begin
- litedramcore_master_p1_odt <= litedramcore_slave_p1_odt;
- end
- end else begin
- litedramcore_master_p1_odt <= litedramcore_csr_dfi_p1_odt;
- end
-end
-always @(*) begin
- litedramcore_master_p1_reset_n <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_reset_n <= litedramcore_ext_dfi_p1_reset_n;
- end else begin
- litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n;
- end
- end else begin
- litedramcore_master_p1_reset_n <= litedramcore_csr_dfi_p1_reset_n;
- end
-end
-always @(*) begin
- litedramcore_master_p1_act_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_act_n <= litedramcore_ext_dfi_p1_act_n;
- end else begin
- litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n;
- end
- end else begin
- litedramcore_master_p1_act_n <= litedramcore_csr_dfi_p1_act_n;
- end
-end
-always @(*) begin
- litedramcore_master_p1_wrdata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_wrdata <= litedramcore_ext_dfi_p1_wrdata;
- end else begin
- litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata;
- end
- end else begin
- litedramcore_master_p1_wrdata <= litedramcore_csr_dfi_p1_wrdata;
- end
-end
-always @(*) begin
- litedramcore_master_p1_wrdata_en <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_wrdata_en <= litedramcore_ext_dfi_p1_wrdata_en;
- end else begin
- litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en;
- end
- end else begin
- litedramcore_master_p1_wrdata_en <= litedramcore_csr_dfi_p1_wrdata_en;
- end
-end
-always @(*) begin
- litedramcore_master_p1_wrdata_mask <= 4'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_wrdata_mask <= litedramcore_ext_dfi_p1_wrdata_mask;
- end else begin
- litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask;
- end
- end else begin
- litedramcore_master_p1_wrdata_mask <= litedramcore_csr_dfi_p1_wrdata_mask;
- end
-end
-always @(*) begin
- litedramcore_master_p1_rddata_en <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_rddata_en <= litedramcore_ext_dfi_p1_rddata_en;
- end else begin
- litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en;
- end
- end else begin
- litedramcore_master_p1_rddata_en <= litedramcore_csr_dfi_p1_rddata_en;
- end
-end
-always @(*) begin
- litedramcore_master_p2_address <= 16'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_address <= litedramcore_ext_dfi_p2_address;
- end else begin
- litedramcore_master_p2_address <= litedramcore_slave_p2_address;
- end
- end else begin
- litedramcore_master_p2_address <= litedramcore_csr_dfi_p2_address;
- end
-end
-always @(*) begin
- litedramcore_master_p2_bank <= 3'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_bank <= litedramcore_ext_dfi_p2_bank;
- end else begin
- litedramcore_master_p2_bank <= litedramcore_slave_p2_bank;
- end
- end else begin
- litedramcore_master_p2_bank <= litedramcore_csr_dfi_p2_bank;
- end
-end
-always @(*) begin
- litedramcore_master_p2_cas_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_cas_n <= litedramcore_ext_dfi_p2_cas_n;
- end else begin
- litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n;
- end
- end else begin
- litedramcore_master_p2_cas_n <= litedramcore_csr_dfi_p2_cas_n;
- end
-end
-always @(*) begin
- litedramcore_master_p2_cs_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_cs_n <= litedramcore_ext_dfi_p2_cs_n;
- end else begin
- litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n;
- end
- end else begin
- litedramcore_master_p2_cs_n <= litedramcore_csr_dfi_p2_cs_n;
- end
-end
-always @(*) begin
- litedramcore_master_p2_ras_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_ras_n <= litedramcore_ext_dfi_p2_ras_n;
- end else begin
- litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n;
- end
- end else begin
- litedramcore_master_p2_ras_n <= litedramcore_csr_dfi_p2_ras_n;
- end
-end
-always @(*) begin
- litedramcore_master_p2_we_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_we_n <= litedramcore_ext_dfi_p2_we_n;
- end else begin
- litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n;
- end
- end else begin
- litedramcore_master_p2_we_n <= litedramcore_csr_dfi_p2_we_n;
- end
-end
-always @(*) begin
- litedramcore_master_p2_cke <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_cke <= litedramcore_ext_dfi_p2_cke;
- end else begin
- litedramcore_master_p2_cke <= litedramcore_slave_p2_cke;
- end
- end else begin
- litedramcore_master_p2_cke <= litedramcore_csr_dfi_p2_cke;
- end
-end
-always @(*) begin
- litedramcore_master_p2_odt <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_odt <= litedramcore_ext_dfi_p2_odt;
- end else begin
- litedramcore_master_p2_odt <= litedramcore_slave_p2_odt;
- end
- end else begin
- litedramcore_master_p2_odt <= litedramcore_csr_dfi_p2_odt;
- end
-end
-always @(*) begin
- litedramcore_master_p2_reset_n <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_reset_n <= litedramcore_ext_dfi_p2_reset_n;
- end else begin
- litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n;
- end
- end else begin
- litedramcore_master_p2_reset_n <= litedramcore_csr_dfi_p2_reset_n;
- end
-end
-always @(*) begin
- litedramcore_master_p2_act_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_act_n <= litedramcore_ext_dfi_p2_act_n;
- end else begin
- litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n;
- end
- end else begin
- litedramcore_master_p2_act_n <= litedramcore_csr_dfi_p2_act_n;
- end
-end
-always @(*) begin
- litedramcore_master_p2_wrdata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_wrdata <= litedramcore_ext_dfi_p2_wrdata;
- end else begin
- litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata;
- end
- end else begin
- litedramcore_master_p2_wrdata <= litedramcore_csr_dfi_p2_wrdata;
- end
-end
-always @(*) begin
- litedramcore_master_p2_wrdata_en <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_wrdata_en <= litedramcore_ext_dfi_p2_wrdata_en;
- end else begin
- litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en;
- end
- end else begin
- litedramcore_master_p2_wrdata_en <= litedramcore_csr_dfi_p2_wrdata_en;
- end
-end
-always @(*) begin
- litedramcore_master_p2_wrdata_mask <= 4'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_wrdata_mask <= litedramcore_ext_dfi_p2_wrdata_mask;
- end else begin
- litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask;
- end
- end else begin
- litedramcore_master_p2_wrdata_mask <= litedramcore_csr_dfi_p2_wrdata_mask;
- end
-end
-always @(*) begin
- litedramcore_master_p2_rddata_en <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_rddata_en <= litedramcore_ext_dfi_p2_rddata_en;
- end else begin
- litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en;
- end
- end else begin
- litedramcore_master_p2_rddata_en <= litedramcore_csr_dfi_p2_rddata_en;
- end
-end
-always @(*) begin
- litedramcore_master_p3_address <= 16'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_address <= litedramcore_ext_dfi_p3_address;
- end else begin
- litedramcore_master_p3_address <= litedramcore_slave_p3_address;
- end
- end else begin
- litedramcore_master_p3_address <= litedramcore_csr_dfi_p3_address;
- end
-end
-always @(*) begin
- litedramcore_master_p3_bank <= 3'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_bank <= litedramcore_ext_dfi_p3_bank;
- end else begin
- litedramcore_master_p3_bank <= litedramcore_slave_p3_bank;
- end
- end else begin
- litedramcore_master_p3_bank <= litedramcore_csr_dfi_p3_bank;
- end
-end
-always @(*) begin
- litedramcore_master_p3_cas_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_cas_n <= litedramcore_ext_dfi_p3_cas_n;
- end else begin
- litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n;
- end
- end else begin
- litedramcore_master_p3_cas_n <= litedramcore_csr_dfi_p3_cas_n;
- end
-end
-always @(*) begin
- litedramcore_master_p3_cs_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_cs_n <= litedramcore_ext_dfi_p3_cs_n;
- end else begin
- litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n;
- end
- end else begin
- litedramcore_master_p3_cs_n <= litedramcore_csr_dfi_p3_cs_n;
- end
+ litedramcore_master_p3_ras_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_ras_n <= litedramcore_ext_dfi_p3_ras_n;
+ end else begin
+ litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n;
+ end
+ end else begin
+ litedramcore_master_p3_ras_n <= litedramcore_csr_dfi_p3_ras_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_we_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_we_n <= litedramcore_ext_dfi_p3_we_n;
+ end else begin
+ litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n;
+ end
+ end else begin
+ litedramcore_master_p3_we_n <= litedramcore_csr_dfi_p3_we_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_cke <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_cke <= litedramcore_ext_dfi_p3_cke;
+ end else begin
+ litedramcore_master_p3_cke <= litedramcore_slave_p3_cke;
+ end
+ end else begin
+ litedramcore_master_p3_cke <= litedramcore_csr_dfi_p3_cke;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_odt <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_odt <= litedramcore_ext_dfi_p3_odt;
+ end else begin
+ litedramcore_master_p3_odt <= litedramcore_slave_p3_odt;
+ end
+ end else begin
+ litedramcore_master_p3_odt <= litedramcore_csr_dfi_p3_odt;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_reset_n <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_reset_n <= litedramcore_ext_dfi_p3_reset_n;
+ end else begin
+ litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n;
+ end
+ end else begin
+ litedramcore_master_p3_reset_n <= litedramcore_csr_dfi_p3_reset_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_act_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_act_n <= litedramcore_ext_dfi_p3_act_n;
+ end else begin
+ litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n;
+ end
+ end else begin
+ litedramcore_master_p3_act_n <= litedramcore_csr_dfi_p3_act_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_wrdata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_wrdata <= litedramcore_ext_dfi_p3_wrdata;
+ end else begin
+ litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata;
+ end
+ end else begin
+ litedramcore_master_p3_wrdata <= litedramcore_csr_dfi_p3_wrdata;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_wrdata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_wrdata_en <= litedramcore_ext_dfi_p3_wrdata_en;
+ end else begin
+ litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en;
+ end
+ end else begin
+ litedramcore_master_p3_wrdata_en <= litedramcore_csr_dfi_p3_wrdata_en;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_wrdata_mask <= 4'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_wrdata_mask <= litedramcore_ext_dfi_p3_wrdata_mask;
+ end else begin
+ litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask;
+ end
+ end else begin
+ litedramcore_master_p3_wrdata_mask <= litedramcore_csr_dfi_p3_wrdata_mask;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_rddata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_rddata_en <= litedramcore_ext_dfi_p3_rddata_en;
+ end else begin
+ litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en;
+ end
+ end else begin
+ litedramcore_master_p3_rddata_en <= litedramcore_csr_dfi_p3_rddata_en;
+ end
+end
+always @(*) begin
+ litedramcore_csr_dfi_p0_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_csr_dfi_p0_rddata <= litedramcore_master_p0_rddata;
+ end
+end
+always @(*) begin
+ litedramcore_csr_dfi_p0_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_csr_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+ end
+end
+always @(*) begin
+ litedramcore_csr_dfi_p1_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata;
+ end
+end
+always @(*) begin
+ litedramcore_csr_dfi_p1_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+ end
+end
+always @(*) begin
+ litedramcore_csr_dfi_p2_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_csr_dfi_p2_rddata <= litedramcore_master_p2_rddata;
+ end
+end
+always @(*) begin
+ litedramcore_csr_dfi_p2_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_csr_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+ end
+end
+always @(*) begin
+ litedramcore_csr_dfi_p3_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_csr_dfi_p3_rddata <= litedramcore_master_p3_rddata;
+ end
+end
+always @(*) begin
+ litedramcore_csr_dfi_p3_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_csr_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+ end
+end
+always @(*) begin
+ litedramcore_ext_dfi_p0_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_ext_dfi_p0_rddata <= litedramcore_master_p0_rddata;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_ext_dfi_p0_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_ext_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_ext_dfi_p1_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_ext_dfi_p1_rddata <= litedramcore_master_p1_rddata;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_ext_dfi_p1_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_ext_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_ext_dfi_p2_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_ext_dfi_p2_rddata <= litedramcore_master_p2_rddata;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_ext_dfi_p2_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_ext_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p0_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ end else begin
+ litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p0_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ end else begin
+ litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_ext_dfi_p3_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_ext_dfi_p3_rddata <= litedramcore_master_p3_rddata;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_ext_dfi_p3_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_ext_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p1_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ end else begin
+ litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p1_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ end else begin
+ litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p2_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ end else begin
+ litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p2_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ end else begin
+ litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p3_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ end else begin
+ litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p3_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ end else begin
+ litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_address <= 16'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_address <= litedramcore_ext_dfi_p0_address;
+ end else begin
+ litedramcore_master_p0_address <= litedramcore_slave_p0_address;
+ end
+ end else begin
+ litedramcore_master_p0_address <= litedramcore_csr_dfi_p0_address;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_bank <= 3'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_bank <= litedramcore_ext_dfi_p0_bank;
+ end else begin
+ litedramcore_master_p0_bank <= litedramcore_slave_p0_bank;
+ end
+ end else begin
+ litedramcore_master_p0_bank <= litedramcore_csr_dfi_p0_bank;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_cas_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_cas_n <= litedramcore_ext_dfi_p0_cas_n;
+ end else begin
+ litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n;
+ end
+ end else begin
+ litedramcore_master_p0_cas_n <= litedramcore_csr_dfi_p0_cas_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_cs_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n;
+ end else begin
+ litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n;
+ end
+ end else begin
+ litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_ras_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n;
+ end else begin
+ litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n;
+ end
+ end else begin
+ litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_we_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n;
+ end else begin
+ litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n;
+ end
+ end else begin
+ litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_cke <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_cke <= litedramcore_ext_dfi_p0_cke;
+ end else begin
+ litedramcore_master_p0_cke <= litedramcore_slave_p0_cke;
+ end
+ end else begin
+ litedramcore_master_p0_cke <= litedramcore_csr_dfi_p0_cke;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_odt <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_odt <= litedramcore_ext_dfi_p0_odt;
+ end else begin
+ litedramcore_master_p0_odt <= litedramcore_slave_p0_odt;
+ end
+ end else begin
+ litedramcore_master_p0_odt <= litedramcore_csr_dfi_p0_odt;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_reset_n <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_reset_n <= litedramcore_ext_dfi_p0_reset_n;
+ end else begin
+ litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n;
+ end
+ end else begin
+ litedramcore_master_p0_reset_n <= litedramcore_csr_dfi_p0_reset_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_act_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_act_n <= litedramcore_ext_dfi_p0_act_n;
+ end else begin
+ litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n;
+ end
+ end else begin
+ litedramcore_master_p0_act_n <= litedramcore_csr_dfi_p0_act_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_wrdata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_wrdata <= litedramcore_ext_dfi_p0_wrdata;
+ end else begin
+ litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata;
+ end
+ end else begin
+ litedramcore_master_p0_wrdata <= litedramcore_csr_dfi_p0_wrdata;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_wrdata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_wrdata_en <= litedramcore_ext_dfi_p0_wrdata_en;
+ end else begin
+ litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en;
+ end
+ end else begin
+ litedramcore_master_p0_wrdata_en <= litedramcore_csr_dfi_p0_wrdata_en;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_wrdata_mask <= 4'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_wrdata_mask <= litedramcore_ext_dfi_p0_wrdata_mask;
+ end else begin
+ litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask;
+ end
+ end else begin
+ litedramcore_master_p0_wrdata_mask <= litedramcore_csr_dfi_p0_wrdata_mask;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_rddata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_rddata_en <= litedramcore_ext_dfi_p0_rddata_en;
+ end else begin
+ litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en;
+ end
+ end else begin
+ litedramcore_master_p0_rddata_en <= litedramcore_csr_dfi_p0_rddata_en;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_address <= 16'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_address <= litedramcore_ext_dfi_p1_address;
+ end else begin
+ litedramcore_master_p1_address <= litedramcore_slave_p1_address;
+ end
+ end else begin
+ litedramcore_master_p1_address <= litedramcore_csr_dfi_p1_address;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_bank <= 3'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_bank <= litedramcore_ext_dfi_p1_bank;
+ end else begin
+ litedramcore_master_p1_bank <= litedramcore_slave_p1_bank;
+ end
+ end else begin
+ litedramcore_master_p1_bank <= litedramcore_csr_dfi_p1_bank;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_cas_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_cas_n <= litedramcore_ext_dfi_p1_cas_n;
+ end else begin
+ litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n;
+ end
+ end else begin
+ litedramcore_master_p1_cas_n <= litedramcore_csr_dfi_p1_cas_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_cs_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_cs_n <= litedramcore_ext_dfi_p1_cs_n;
+ end else begin
+ litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n;
+ end
+ end else begin
+ litedramcore_master_p1_cs_n <= litedramcore_csr_dfi_p1_cs_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_ras_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_ras_n <= litedramcore_ext_dfi_p1_ras_n;
+ end else begin
+ litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n;
+ end
+ end else begin
+ litedramcore_master_p1_ras_n <= litedramcore_csr_dfi_p1_ras_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_we_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_we_n <= litedramcore_ext_dfi_p1_we_n;
+ end else begin
+ litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n;
+ end
+ end else begin
+ litedramcore_master_p1_we_n <= litedramcore_csr_dfi_p1_we_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_cke <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_cke <= litedramcore_ext_dfi_p1_cke;
+ end else begin
+ litedramcore_master_p1_cke <= litedramcore_slave_p1_cke;
+ end
+ end else begin
+ litedramcore_master_p1_cke <= litedramcore_csr_dfi_p1_cke;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_odt <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_odt <= litedramcore_ext_dfi_p1_odt;
+ end else begin
+ litedramcore_master_p1_odt <= litedramcore_slave_p1_odt;
+ end
+ end else begin
+ litedramcore_master_p1_odt <= litedramcore_csr_dfi_p1_odt;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_reset_n <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_reset_n <= litedramcore_ext_dfi_p1_reset_n;
+ end else begin
+ litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n;
+ end
+ end else begin
+ litedramcore_master_p1_reset_n <= litedramcore_csr_dfi_p1_reset_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_act_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_act_n <= litedramcore_ext_dfi_p1_act_n;
+ end else begin
+ litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n;
+ end
+ end else begin
+ litedramcore_master_p1_act_n <= litedramcore_csr_dfi_p1_act_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_wrdata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_wrdata <= litedramcore_ext_dfi_p1_wrdata;
+ end else begin
+ litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata;
+ end
+ end else begin
+ litedramcore_master_p1_wrdata <= litedramcore_csr_dfi_p1_wrdata;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_wrdata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_wrdata_en <= litedramcore_ext_dfi_p1_wrdata_en;
+ end else begin
+ litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en;
+ end
+ end else begin
+ litedramcore_master_p1_wrdata_en <= litedramcore_csr_dfi_p1_wrdata_en;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_wrdata_mask <= 4'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_wrdata_mask <= litedramcore_ext_dfi_p1_wrdata_mask;
+ end else begin
+ litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask;
+ end
+ end else begin
+ litedramcore_master_p1_wrdata_mask <= litedramcore_csr_dfi_p1_wrdata_mask;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_rddata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_rddata_en <= litedramcore_ext_dfi_p1_rddata_en;
+ end else begin
+ litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en;
+ end
+ end else begin
+ litedramcore_master_p1_rddata_en <= litedramcore_csr_dfi_p1_rddata_en;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_address <= 16'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_address <= litedramcore_ext_dfi_p2_address;
+ end else begin
+ litedramcore_master_p2_address <= litedramcore_slave_p2_address;
+ end
+ end else begin
+ litedramcore_master_p2_address <= litedramcore_csr_dfi_p2_address;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_bank <= 3'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_bank <= litedramcore_ext_dfi_p2_bank;
+ end else begin
+ litedramcore_master_p2_bank <= litedramcore_slave_p2_bank;
+ end
+ end else begin
+ litedramcore_master_p2_bank <= litedramcore_csr_dfi_p2_bank;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_cas_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_cas_n <= litedramcore_ext_dfi_p2_cas_n;
+ end else begin
+ litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n;
+ end
+ end else begin
+ litedramcore_master_p2_cas_n <= litedramcore_csr_dfi_p2_cas_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_cs_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_cs_n <= litedramcore_ext_dfi_p2_cs_n;
+ end else begin
+ litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n;
+ end
+ end else begin
+ litedramcore_master_p2_cs_n <= litedramcore_csr_dfi_p2_cs_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_ras_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_ras_n <= litedramcore_ext_dfi_p2_ras_n;
+ end else begin
+ litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n;
+ end
+ end else begin
+ litedramcore_master_p2_ras_n <= litedramcore_csr_dfi_p2_ras_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_we_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_we_n <= litedramcore_ext_dfi_p2_we_n;
+ end else begin
+ litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n;
+ end
+ end else begin
+ litedramcore_master_p2_we_n <= litedramcore_csr_dfi_p2_we_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_cke <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_cke <= litedramcore_ext_dfi_p2_cke;
+ end else begin
+ litedramcore_master_p2_cke <= litedramcore_slave_p2_cke;
+ end
+ end else begin
+ litedramcore_master_p2_cke <= litedramcore_csr_dfi_p2_cke;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_odt <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_odt <= litedramcore_ext_dfi_p2_odt;
+ end else begin
+ litedramcore_master_p2_odt <= litedramcore_slave_p2_odt;
+ end
+ end else begin
+ litedramcore_master_p2_odt <= litedramcore_csr_dfi_p2_odt;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_reset_n <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_reset_n <= litedramcore_ext_dfi_p2_reset_n;
+ end else begin
+ litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n;
+ end
+ end else begin
+ litedramcore_master_p2_reset_n <= litedramcore_csr_dfi_p2_reset_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_act_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_act_n <= litedramcore_ext_dfi_p2_act_n;
+ end else begin
+ litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n;
+ end
+ end else begin
+ litedramcore_master_p2_act_n <= litedramcore_csr_dfi_p2_act_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_wrdata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_wrdata <= litedramcore_ext_dfi_p2_wrdata;
+ end else begin
+ litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata;
+ end
+ end else begin
+ litedramcore_master_p2_wrdata <= litedramcore_csr_dfi_p2_wrdata;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_wrdata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_wrdata_en <= litedramcore_ext_dfi_p2_wrdata_en;
+ end else begin
+ litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en;
+ end
+ end else begin
+ litedramcore_master_p2_wrdata_en <= litedramcore_csr_dfi_p2_wrdata_en;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_wrdata_mask <= 4'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_wrdata_mask <= litedramcore_ext_dfi_p2_wrdata_mask;
+ end else begin
+ litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask;
+ end
+ end else begin
+ litedramcore_master_p2_wrdata_mask <= litedramcore_csr_dfi_p2_wrdata_mask;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_rddata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_rddata_en <= litedramcore_ext_dfi_p2_rddata_en;
+ end else begin
+ litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en;
+ end
+ end else begin
+ litedramcore_master_p2_rddata_en <= litedramcore_csr_dfi_p2_rddata_en;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_address <= 16'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_address <= litedramcore_ext_dfi_p3_address;
+ end else begin
+ litedramcore_master_p3_address <= litedramcore_slave_p3_address;
+ end
+ end else begin
+ litedramcore_master_p3_address <= litedramcore_csr_dfi_p3_address;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_bank <= 3'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_bank <= litedramcore_ext_dfi_p3_bank;
+ end else begin
+ litedramcore_master_p3_bank <= litedramcore_slave_p3_bank;
+ end
+ end else begin
+ litedramcore_master_p3_bank <= litedramcore_csr_dfi_p3_bank;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_cas_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_cas_n <= litedramcore_ext_dfi_p3_cas_n;
+ end else begin
+ litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n;
+ end
+ end else begin
+ litedramcore_master_p3_cas_n <= litedramcore_csr_dfi_p3_cas_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_cs_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_cs_n <= litedramcore_ext_dfi_p3_cs_n;
+ end else begin
+ litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n;
+ end
+ end else begin
+ litedramcore_master_p3_cs_n <= litedramcore_csr_dfi_p3_cs_n;
+ end
end
assign litedramcore_csr_dfi_p0_cke = litedramcore_cke;
assign litedramcore_csr_dfi_p1_cke = litedramcore_cke;
assign litedramcore_csr_dfi_p2_reset_n = litedramcore_reset_n;
assign litedramcore_csr_dfi_p3_reset_n = litedramcore_reset_n;
always @(*) begin
- litedramcore_csr_dfi_p0_cas_n <= 1'd1;
- if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_csr_dfi_p0_cas_n <= (~litedramcore_phaseinjector0_csrfield_cas);
- end else begin
- litedramcore_csr_dfi_p0_cas_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p0_cas_n <= 1'd1;
+ if (litedramcore_phaseinjector0_command_issue_re) begin
+ litedramcore_csr_dfi_p0_cas_n <= (~litedramcore_phaseinjector0_csrfield_cas);
+ end else begin
+ litedramcore_csr_dfi_p0_cas_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p0_cs_n <= 1'd1;
- if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}};
- end else begin
- litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}};
- end
+ litedramcore_csr_dfi_p0_cs_n <= 1'd1;
+ if (litedramcore_phaseinjector0_command_issue_re) begin
+ litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}};
+ end else begin
+ litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}};
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p0_ras_n <= 1'd1;
- if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_csr_dfi_p0_ras_n <= (~litedramcore_phaseinjector0_csrfield_ras);
- end else begin
- litedramcore_csr_dfi_p0_ras_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p0_ras_n <= 1'd1;
+ if (litedramcore_phaseinjector0_command_issue_re) begin
+ litedramcore_csr_dfi_p0_ras_n <= (~litedramcore_phaseinjector0_csrfield_ras);
+ end else begin
+ litedramcore_csr_dfi_p0_ras_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p0_we_n <= 1'd1;
- if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we);
- end else begin
- litedramcore_csr_dfi_p0_we_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p0_we_n <= 1'd1;
+ if (litedramcore_phaseinjector0_command_issue_re) begin
+ litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we);
+ end else begin
+ litedramcore_csr_dfi_p0_we_n <= 1'd1;
+ end
end
assign litedramcore_csr_dfi_p0_address = litedramcore_phaseinjector0_address_storage;
assign litedramcore_csr_dfi_p0_bank = litedramcore_phaseinjector0_baddress_storage;
assign litedramcore_csr_dfi_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage;
assign litedramcore_csr_dfi_p0_wrdata_mask = 1'd0;
always @(*) begin
- litedramcore_csr_dfi_p1_cas_n <= 1'd1;
- if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_csr_dfi_p1_cas_n <= (~litedramcore_phaseinjector1_csrfield_cas);
- end else begin
- litedramcore_csr_dfi_p1_cas_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p1_cas_n <= 1'd1;
+ if (litedramcore_phaseinjector1_command_issue_re) begin
+ litedramcore_csr_dfi_p1_cas_n <= (~litedramcore_phaseinjector1_csrfield_cas);
+ end else begin
+ litedramcore_csr_dfi_p1_cas_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p1_cs_n <= 1'd1;
- if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}};
- end else begin
- litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}};
- end
+ litedramcore_csr_dfi_p1_cs_n <= 1'd1;
+ if (litedramcore_phaseinjector1_command_issue_re) begin
+ litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}};
+ end else begin
+ litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}};
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p1_ras_n <= 1'd1;
- if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_csr_dfi_p1_ras_n <= (~litedramcore_phaseinjector1_csrfield_ras);
- end else begin
- litedramcore_csr_dfi_p1_ras_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p1_ras_n <= 1'd1;
+ if (litedramcore_phaseinjector1_command_issue_re) begin
+ litedramcore_csr_dfi_p1_ras_n <= (~litedramcore_phaseinjector1_csrfield_ras);
+ end else begin
+ litedramcore_csr_dfi_p1_ras_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p1_we_n <= 1'd1;
- if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we);
- end else begin
- litedramcore_csr_dfi_p1_we_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p1_we_n <= 1'd1;
+ if (litedramcore_phaseinjector1_command_issue_re) begin
+ litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we);
+ end else begin
+ litedramcore_csr_dfi_p1_we_n <= 1'd1;
+ end
end
assign litedramcore_csr_dfi_p1_address = litedramcore_phaseinjector1_address_storage;
assign litedramcore_csr_dfi_p1_bank = litedramcore_phaseinjector1_baddress_storage;
assign litedramcore_csr_dfi_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage;
assign litedramcore_csr_dfi_p1_wrdata_mask = 1'd0;
always @(*) begin
- litedramcore_csr_dfi_p2_cas_n <= 1'd1;
- if (litedramcore_phaseinjector2_command_issue_re) begin
- litedramcore_csr_dfi_p2_cas_n <= (~litedramcore_phaseinjector2_csrfield_cas);
- end else begin
- litedramcore_csr_dfi_p2_cas_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p2_cas_n <= 1'd1;
+ if (litedramcore_phaseinjector2_command_issue_re) begin
+ litedramcore_csr_dfi_p2_cas_n <= (~litedramcore_phaseinjector2_csrfield_cas);
+ end else begin
+ litedramcore_csr_dfi_p2_cas_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p2_cs_n <= 1'd1;
- if (litedramcore_phaseinjector2_command_issue_re) begin
- litedramcore_csr_dfi_p2_cs_n <= {1{(~litedramcore_phaseinjector2_csrfield_cs)}};
- end else begin
- litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}};
- end
+ litedramcore_csr_dfi_p2_cs_n <= 1'd1;
+ if (litedramcore_phaseinjector2_command_issue_re) begin
+ litedramcore_csr_dfi_p2_cs_n <= {1{(~litedramcore_phaseinjector2_csrfield_cs)}};
+ end else begin
+ litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}};
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p2_ras_n <= 1'd1;
- if (litedramcore_phaseinjector2_command_issue_re) begin
- litedramcore_csr_dfi_p2_ras_n <= (~litedramcore_phaseinjector2_csrfield_ras);
- end else begin
- litedramcore_csr_dfi_p2_ras_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p2_ras_n <= 1'd1;
+ if (litedramcore_phaseinjector2_command_issue_re) begin
+ litedramcore_csr_dfi_p2_ras_n <= (~litedramcore_phaseinjector2_csrfield_ras);
+ end else begin
+ litedramcore_csr_dfi_p2_ras_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p2_we_n <= 1'd1;
- if (litedramcore_phaseinjector2_command_issue_re) begin
- litedramcore_csr_dfi_p2_we_n <= (~litedramcore_phaseinjector2_csrfield_we);
- end else begin
- litedramcore_csr_dfi_p2_we_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p2_we_n <= 1'd1;
+ if (litedramcore_phaseinjector2_command_issue_re) begin
+ litedramcore_csr_dfi_p2_we_n <= (~litedramcore_phaseinjector2_csrfield_we);
+ end else begin
+ litedramcore_csr_dfi_p2_we_n <= 1'd1;
+ end
end
assign litedramcore_csr_dfi_p2_address = litedramcore_phaseinjector2_address_storage;
assign litedramcore_csr_dfi_p2_bank = litedramcore_phaseinjector2_baddress_storage;
assign litedramcore_csr_dfi_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage;
assign litedramcore_csr_dfi_p2_wrdata_mask = 1'd0;
always @(*) begin
- litedramcore_csr_dfi_p3_cas_n <= 1'd1;
- if (litedramcore_phaseinjector3_command_issue_re) begin
- litedramcore_csr_dfi_p3_cas_n <= (~litedramcore_phaseinjector3_csrfield_cas);
- end else begin
- litedramcore_csr_dfi_p3_cas_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p3_cas_n <= 1'd1;
+ if (litedramcore_phaseinjector3_command_issue_re) begin
+ litedramcore_csr_dfi_p3_cas_n <= (~litedramcore_phaseinjector3_csrfield_cas);
+ end else begin
+ litedramcore_csr_dfi_p3_cas_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p3_cs_n <= 1'd1;
- if (litedramcore_phaseinjector3_command_issue_re) begin
- litedramcore_csr_dfi_p3_cs_n <= {1{(~litedramcore_phaseinjector3_csrfield_cs)}};
- end else begin
- litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}};
- end
+ litedramcore_csr_dfi_p3_cs_n <= 1'd1;
+ if (litedramcore_phaseinjector3_command_issue_re) begin
+ litedramcore_csr_dfi_p3_cs_n <= {1{(~litedramcore_phaseinjector3_csrfield_cs)}};
+ end else begin
+ litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}};
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p3_ras_n <= 1'd1;
- if (litedramcore_phaseinjector3_command_issue_re) begin
- litedramcore_csr_dfi_p3_ras_n <= (~litedramcore_phaseinjector3_csrfield_ras);
- end else begin
- litedramcore_csr_dfi_p3_ras_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p3_ras_n <= 1'd1;
+ if (litedramcore_phaseinjector3_command_issue_re) begin
+ litedramcore_csr_dfi_p3_ras_n <= (~litedramcore_phaseinjector3_csrfield_ras);
+ end else begin
+ litedramcore_csr_dfi_p3_ras_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p3_we_n <= 1'd1;
- if (litedramcore_phaseinjector3_command_issue_re) begin
- litedramcore_csr_dfi_p3_we_n <= (~litedramcore_phaseinjector3_csrfield_we);
- end else begin
- litedramcore_csr_dfi_p3_we_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p3_we_n <= 1'd1;
+ if (litedramcore_phaseinjector3_command_issue_re) begin
+ litedramcore_csr_dfi_p3_we_n <= (~litedramcore_phaseinjector3_csrfield_we);
+ end else begin
+ litedramcore_csr_dfi_p3_we_n <= 1'd1;
+ end
end
assign litedramcore_csr_dfi_p3_address = litedramcore_phaseinjector3_address_storage;
assign litedramcore_csr_dfi_p3_bank = litedramcore_phaseinjector3_baddress_storage;
assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1;
assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1;
always @(*) begin
- litedramcore_refresher_next_state <= 2'd0;
- litedramcore_refresher_next_state <= litedramcore_refresher_state;
- case (litedramcore_refresher_state)
- 1'd1: begin
- if (litedramcore_cmd_ready) begin
- litedramcore_refresher_next_state <= 2'd2;
- end
- end
- 2'd2: begin
- if (litedramcore_sequencer_done0) begin
- if (litedramcore_wants_zqcs) begin
- litedramcore_refresher_next_state <= 2'd3;
- end else begin
- litedramcore_refresher_next_state <= 1'd0;
- end
- end
- end
- 2'd3: begin
- if (litedramcore_zqcs_executer_done) begin
- litedramcore_refresher_next_state <= 1'd0;
- end
- end
- default: begin
- if (1'd1) begin
- if (litedramcore_wants_refresh) begin
- litedramcore_refresher_next_state <= 1'd1;
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_cmd_valid <= 1'd0;
- case (litedramcore_refresher_state)
- 1'd1: begin
- litedramcore_cmd_valid <= 1'd1;
- end
- 2'd2: begin
- litedramcore_cmd_valid <= 1'd1;
- if (litedramcore_sequencer_done0) begin
- if (litedramcore_wants_zqcs) begin
- end else begin
- litedramcore_cmd_valid <= 1'd0;
- end
- end
- end
- 2'd3: begin
- litedramcore_cmd_valid <= 1'd1;
- if (litedramcore_zqcs_executer_done) begin
- litedramcore_cmd_valid <= 1'd0;
- end
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_zqcs_executer_start <= 1'd0;
- case (litedramcore_refresher_state)
- 1'd1: begin
- end
- 2'd2: begin
- if (litedramcore_sequencer_done0) begin
- if (litedramcore_wants_zqcs) begin
- litedramcore_zqcs_executer_start <= 1'd1;
- end else begin
- end
- end
- end
- 2'd3: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_cmd_last <= 1'd0;
- case (litedramcore_refresher_state)
- 1'd1: begin
- end
- 2'd2: begin
- if (litedramcore_sequencer_done0) begin
- if (litedramcore_wants_zqcs) begin
- end else begin
- litedramcore_cmd_last <= 1'd1;
- end
- end
- end
- 2'd3: begin
- if (litedramcore_zqcs_executer_done) begin
- litedramcore_cmd_last <= 1'd1;
- end
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_sequencer_start0 <= 1'd0;
- case (litedramcore_refresher_state)
- 1'd1: begin
- if (litedramcore_cmd_ready) begin
- litedramcore_sequencer_start0 <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- default: begin
- end
- endcase
-end
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine0_req_valid;
-assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine0_req_we;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine0_req_addr;
-assign litedramcore_bankmachine0_cmd_buffer_sink_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine0_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine0_cmd_buffer_sink_first = litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine0_cmd_buffer_sink_last = litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine0_cmd_buffer_sink_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine0_cmd_buffer_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid);
-assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine0_cmd_buffer_source_valid);
-assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_cmd_buffer_source_payload_addr[22:7]);
+ litedramcore_refresher_next_state <= 2'd0;
+ litedramcore_refresher_next_state <= litedramcore_refresher_state;
+ case (litedramcore_refresher_state)
+ 1'd1: begin
+ if (litedramcore_cmd_ready) begin
+ litedramcore_refresher_next_state <= 2'd2;
+ end
+ end
+ 2'd2: begin
+ if (litedramcore_sequencer_done0) begin
+ if (litedramcore_wants_zqcs) begin
+ litedramcore_refresher_next_state <= 2'd3;
+ end else begin
+ litedramcore_refresher_next_state <= 1'd0;
+ end
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_zqcs_executer_done) begin
+ litedramcore_refresher_next_state <= 1'd0;
+ end
+ end
+ default: begin
+ if (1'd1) begin
+ if (litedramcore_wants_refresh) begin
+ litedramcore_refresher_next_state <= 1'd1;
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_cmd_valid <= 1'd0;
+ case (litedramcore_refresher_state)
+ 1'd1: begin
+ litedramcore_cmd_valid <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_cmd_valid <= 1'd1;
+ if (litedramcore_sequencer_done0) begin
+ if (litedramcore_wants_zqcs) begin
+ end else begin
+ litedramcore_cmd_valid <= 1'd0;
+ end
+ end
+ end
+ 2'd3: begin
+ litedramcore_cmd_valid <= 1'd1;
+ if (litedramcore_zqcs_executer_done) begin
+ litedramcore_cmd_valid <= 1'd0;
+ end
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_zqcs_executer_start <= 1'd0;
+ case (litedramcore_refresher_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ if (litedramcore_sequencer_done0) begin
+ if (litedramcore_wants_zqcs) begin
+ litedramcore_zqcs_executer_start <= 1'd1;
+ end else begin
+ end
+ end
+ end
+ 2'd3: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_cmd_last <= 1'd0;
+ case (litedramcore_refresher_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ if (litedramcore_sequencer_done0) begin
+ if (litedramcore_wants_zqcs) begin
+ end else begin
+ litedramcore_cmd_last <= 1'd1;
+ end
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_zqcs_executer_done) begin
+ litedramcore_cmd_last <= 1'd1;
+ end
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_sequencer_start0 <= 1'd0;
+ case (litedramcore_refresher_state)
+ 1'd1: begin
+ if (litedramcore_cmd_ready) begin
+ litedramcore_sequencer_start0 <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ default: begin
+ end
+ endcase
+end
+assign litedramcore_bankmachine0_sink_valid = litedramcore_bankmachine0_req_valid;
+assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_sink_ready;
+assign litedramcore_bankmachine0_sink_payload_we = litedramcore_bankmachine0_req_we;
+assign litedramcore_bankmachine0_sink_payload_addr = litedramcore_bankmachine0_req_addr;
+assign litedramcore_bankmachine0_sink_sink_valid = litedramcore_bankmachine0_source_valid;
+assign litedramcore_bankmachine0_source_ready = litedramcore_bankmachine0_sink_sink_ready;
+assign litedramcore_bankmachine0_sink_sink_first = litedramcore_bankmachine0_source_first;
+assign litedramcore_bankmachine0_sink_sink_last = litedramcore_bankmachine0_source_last;
+assign litedramcore_bankmachine0_sink_sink_payload_we = litedramcore_bankmachine0_source_payload_we;
+assign litedramcore_bankmachine0_sink_sink_payload_addr = litedramcore_bankmachine0_source_payload_addr;
+assign litedramcore_bankmachine0_source_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid);
+assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_source_valid | litedramcore_bankmachine0_source_source_valid);
+assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_source_source_payload_addr[22:7]);
assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
always @(*) begin
- litedramcore_bankmachine0_cmd_payload_a <= 16'd0;
- if (litedramcore_bankmachine0_row_col_n_addr_sel) begin
- litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[22:7];
- end else begin
- litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine0_cmd_payload_a <= 16'd0;
+ if (litedramcore_bankmachine0_row_col_n_addr_sel) begin
+ litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_source_source_payload_addr[22:7];
+ end else begin
+ litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write);
assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
always @(*) begin
- litedramcore_bankmachine0_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine0_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[22:7] != litedramcore_bankmachine0_cmd_buffer_source_payload_addr[22:7])) begin
- litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine0_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | litedramcore_bankmachine0_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re);
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine0_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine0_next_state <= 4'd0;
- litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- if (litedramcore_bankmachine0_cmd_ready) begin
- litedramcore_bankmachine0_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- if (litedramcore_bankmachine0_cmd_ready) begin
- litedramcore_bankmachine0_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine0_refresh_req)) begin
- litedramcore_bankmachine0_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine0_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine0_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine0_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine0_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- litedramcore_bankmachine0_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin
- litedramcore_bankmachine0_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine0_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine0_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine0_twtpcon_ready) begin
- litedramcore_bankmachine0_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- litedramcore_bankmachine0_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_row_open <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_row_close <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- litedramcore_bankmachine0_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine0_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine0_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine1_req_valid;
-assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine1_req_we;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine1_req_addr;
-assign litedramcore_bankmachine1_cmd_buffer_sink_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine1_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine1_cmd_buffer_sink_first = litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine1_cmd_buffer_sink_last = litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine1_cmd_buffer_sink_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine1_cmd_buffer_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid);
-assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine1_cmd_buffer_source_valid);
-assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_cmd_buffer_source_payload_addr[22:7]);
+ litedramcore_bankmachine0_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine0_source_valid & litedramcore_bankmachine0_source_source_valid)) begin
+ if ((litedramcore_bankmachine0_source_payload_addr[22:7] != litedramcore_bankmachine0_source_source_payload_addr[22:7])) begin
+ litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine0_syncfifo0_din = {litedramcore_bankmachine0_fifo_in_last, litedramcore_bankmachine0_fifo_in_first, litedramcore_bankmachine0_fifo_in_payload_addr, litedramcore_bankmachine0_fifo_in_payload_we};
+assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout;
+assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout;
+assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout;
+assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout;
+assign litedramcore_bankmachine0_sink_ready = litedramcore_bankmachine0_syncfifo0_writable;
+assign litedramcore_bankmachine0_syncfifo0_we = litedramcore_bankmachine0_sink_valid;
+assign litedramcore_bankmachine0_fifo_in_first = litedramcore_bankmachine0_sink_first;
+assign litedramcore_bankmachine0_fifo_in_last = litedramcore_bankmachine0_sink_last;
+assign litedramcore_bankmachine0_fifo_in_payload_we = litedramcore_bankmachine0_sink_payload_we;
+assign litedramcore_bankmachine0_fifo_in_payload_addr = litedramcore_bankmachine0_sink_payload_addr;
+assign litedramcore_bankmachine0_source_valid = litedramcore_bankmachine0_syncfifo0_readable;
+assign litedramcore_bankmachine0_source_first = litedramcore_bankmachine0_fifo_out_first;
+assign litedramcore_bankmachine0_source_last = litedramcore_bankmachine0_fifo_out_last;
+assign litedramcore_bankmachine0_source_payload_we = litedramcore_bankmachine0_fifo_out_payload_we;
+assign litedramcore_bankmachine0_source_payload_addr = litedramcore_bankmachine0_fifo_out_payload_addr;
+assign litedramcore_bankmachine0_syncfifo0_re = litedramcore_bankmachine0_source_ready;
+always @(*) begin
+ litedramcore_bankmachine0_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine0_replace) begin
+ litedramcore_bankmachine0_wrport_adr <= (litedramcore_bankmachine0_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine0_wrport_adr <= litedramcore_bankmachine0_produce;
+ end
+end
+assign litedramcore_bankmachine0_wrport_dat_w = litedramcore_bankmachine0_syncfifo0_din;
+assign litedramcore_bankmachine0_wrport_we = (litedramcore_bankmachine0_syncfifo0_we & (litedramcore_bankmachine0_syncfifo0_writable | litedramcore_bankmachine0_replace));
+assign litedramcore_bankmachine0_do_read = (litedramcore_bankmachine0_syncfifo0_readable & litedramcore_bankmachine0_syncfifo0_re);
+assign litedramcore_bankmachine0_rdport_adr = litedramcore_bankmachine0_consume;
+assign litedramcore_bankmachine0_syncfifo0_dout = litedramcore_bankmachine0_rdport_dat_r;
+assign litedramcore_bankmachine0_syncfifo0_writable = (litedramcore_bankmachine0_level != 5'd16);
+assign litedramcore_bankmachine0_syncfifo0_readable = (litedramcore_bankmachine0_level != 1'd0);
+assign litedramcore_bankmachine0_pipe_valid_sink_ready = ((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready);
+assign litedramcore_bankmachine0_pipe_valid_sink_valid = litedramcore_bankmachine0_sink_sink_valid;
+assign litedramcore_bankmachine0_sink_sink_ready = litedramcore_bankmachine0_pipe_valid_sink_ready;
+assign litedramcore_bankmachine0_pipe_valid_sink_first = litedramcore_bankmachine0_sink_sink_first;
+assign litedramcore_bankmachine0_pipe_valid_sink_last = litedramcore_bankmachine0_sink_sink_last;
+assign litedramcore_bankmachine0_pipe_valid_sink_payload_we = litedramcore_bankmachine0_sink_sink_payload_we;
+assign litedramcore_bankmachine0_pipe_valid_sink_payload_addr = litedramcore_bankmachine0_sink_sink_payload_addr;
+assign litedramcore_bankmachine0_source_source_valid = litedramcore_bankmachine0_pipe_valid_source_valid;
+assign litedramcore_bankmachine0_pipe_valid_source_ready = litedramcore_bankmachine0_source_source_ready;
+assign litedramcore_bankmachine0_source_source_first = litedramcore_bankmachine0_pipe_valid_source_first;
+assign litedramcore_bankmachine0_source_source_last = litedramcore_bankmachine0_pipe_valid_source_last;
+assign litedramcore_bankmachine0_source_source_payload_we = litedramcore_bankmachine0_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine0_source_source_payload_addr = litedramcore_bankmachine0_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine0_next_state <= 4'd0;
+ litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ if (litedramcore_bankmachine0_cmd_ready) begin
+ litedramcore_bankmachine0_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ if (litedramcore_bankmachine0_cmd_ready) begin
+ litedramcore_bankmachine0_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine0_refresh_req)) begin
+ litedramcore_bankmachine0_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine0_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine0_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine0_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine0_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ litedramcore_bankmachine0_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin
+ litedramcore_bankmachine0_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine0_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine0_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if (litedramcore_bankmachine0_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if (litedramcore_bankmachine0_source_source_payload_we) begin
+ litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if (litedramcore_bankmachine0_source_source_payload_we) begin
+ litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if (litedramcore_bankmachine0_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine0_twtpcon_ready) begin
+ litedramcore_bankmachine0_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_row_open <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ litedramcore_bankmachine0_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_row_close <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ litedramcore_bankmachine0_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine0_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine0_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if (litedramcore_bankmachine0_source_source_payload_we) begin
+ litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+assign litedramcore_bankmachine1_sink_valid = litedramcore_bankmachine1_req_valid;
+assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_sink_ready;
+assign litedramcore_bankmachine1_sink_payload_we = litedramcore_bankmachine1_req_we;
+assign litedramcore_bankmachine1_sink_payload_addr = litedramcore_bankmachine1_req_addr;
+assign litedramcore_bankmachine1_sink_sink_valid = litedramcore_bankmachine1_source_valid;
+assign litedramcore_bankmachine1_source_ready = litedramcore_bankmachine1_sink_sink_ready;
+assign litedramcore_bankmachine1_sink_sink_first = litedramcore_bankmachine1_source_first;
+assign litedramcore_bankmachine1_sink_sink_last = litedramcore_bankmachine1_source_last;
+assign litedramcore_bankmachine1_sink_sink_payload_we = litedramcore_bankmachine1_source_payload_we;
+assign litedramcore_bankmachine1_sink_sink_payload_addr = litedramcore_bankmachine1_source_payload_addr;
+assign litedramcore_bankmachine1_source_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid);
+assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_source_valid | litedramcore_bankmachine1_source_source_valid);
+assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_source_source_payload_addr[22:7]);
assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
always @(*) begin
- litedramcore_bankmachine1_cmd_payload_a <= 16'd0;
- if (litedramcore_bankmachine1_row_col_n_addr_sel) begin
- litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[22:7];
- end else begin
- litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine1_cmd_payload_a <= 16'd0;
+ if (litedramcore_bankmachine1_row_col_n_addr_sel) begin
+ litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_source_source_payload_addr[22:7];
+ end else begin
+ litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write);
assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
always @(*) begin
- litedramcore_bankmachine1_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine1_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[22:7] != litedramcore_bankmachine1_cmd_buffer_source_payload_addr[22:7])) begin
- litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine1_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | litedramcore_bankmachine1_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re);
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine1_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine1_next_state <= 4'd0;
- litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- if (litedramcore_bankmachine1_cmd_ready) begin
- litedramcore_bankmachine1_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- if (litedramcore_bankmachine1_cmd_ready) begin
- litedramcore_bankmachine1_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine1_refresh_req)) begin
- litedramcore_bankmachine1_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine1_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine1_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine1_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine1_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- litedramcore_bankmachine1_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin
- litedramcore_bankmachine1_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine1_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine1_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine1_twtpcon_ready) begin
- litedramcore_bankmachine1_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_row_open <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_row_close <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- litedramcore_bankmachine1_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine1_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine1_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine2_req_valid;
-assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine2_req_we;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine2_req_addr;
-assign litedramcore_bankmachine2_cmd_buffer_sink_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine2_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine2_cmd_buffer_sink_first = litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine2_cmd_buffer_sink_last = litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine2_cmd_buffer_sink_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine2_cmd_buffer_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid);
-assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine2_cmd_buffer_source_valid);
-assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_cmd_buffer_source_payload_addr[22:7]);
+ litedramcore_bankmachine1_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine1_source_valid & litedramcore_bankmachine1_source_source_valid)) begin
+ if ((litedramcore_bankmachine1_source_payload_addr[22:7] != litedramcore_bankmachine1_source_source_payload_addr[22:7])) begin
+ litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine1_syncfifo1_din = {litedramcore_bankmachine1_fifo_in_last, litedramcore_bankmachine1_fifo_in_first, litedramcore_bankmachine1_fifo_in_payload_addr, litedramcore_bankmachine1_fifo_in_payload_we};
+assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout;
+assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout;
+assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout;
+assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout;
+assign litedramcore_bankmachine1_sink_ready = litedramcore_bankmachine1_syncfifo1_writable;
+assign litedramcore_bankmachine1_syncfifo1_we = litedramcore_bankmachine1_sink_valid;
+assign litedramcore_bankmachine1_fifo_in_first = litedramcore_bankmachine1_sink_first;
+assign litedramcore_bankmachine1_fifo_in_last = litedramcore_bankmachine1_sink_last;
+assign litedramcore_bankmachine1_fifo_in_payload_we = litedramcore_bankmachine1_sink_payload_we;
+assign litedramcore_bankmachine1_fifo_in_payload_addr = litedramcore_bankmachine1_sink_payload_addr;
+assign litedramcore_bankmachine1_source_valid = litedramcore_bankmachine1_syncfifo1_readable;
+assign litedramcore_bankmachine1_source_first = litedramcore_bankmachine1_fifo_out_first;
+assign litedramcore_bankmachine1_source_last = litedramcore_bankmachine1_fifo_out_last;
+assign litedramcore_bankmachine1_source_payload_we = litedramcore_bankmachine1_fifo_out_payload_we;
+assign litedramcore_bankmachine1_source_payload_addr = litedramcore_bankmachine1_fifo_out_payload_addr;
+assign litedramcore_bankmachine1_syncfifo1_re = litedramcore_bankmachine1_source_ready;
+always @(*) begin
+ litedramcore_bankmachine1_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine1_replace) begin
+ litedramcore_bankmachine1_wrport_adr <= (litedramcore_bankmachine1_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine1_wrport_adr <= litedramcore_bankmachine1_produce;
+ end
+end
+assign litedramcore_bankmachine1_wrport_dat_w = litedramcore_bankmachine1_syncfifo1_din;
+assign litedramcore_bankmachine1_wrport_we = (litedramcore_bankmachine1_syncfifo1_we & (litedramcore_bankmachine1_syncfifo1_writable | litedramcore_bankmachine1_replace));
+assign litedramcore_bankmachine1_do_read = (litedramcore_bankmachine1_syncfifo1_readable & litedramcore_bankmachine1_syncfifo1_re);
+assign litedramcore_bankmachine1_rdport_adr = litedramcore_bankmachine1_consume;
+assign litedramcore_bankmachine1_syncfifo1_dout = litedramcore_bankmachine1_rdport_dat_r;
+assign litedramcore_bankmachine1_syncfifo1_writable = (litedramcore_bankmachine1_level != 5'd16);
+assign litedramcore_bankmachine1_syncfifo1_readable = (litedramcore_bankmachine1_level != 1'd0);
+assign litedramcore_bankmachine1_pipe_valid_sink_ready = ((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready);
+assign litedramcore_bankmachine1_pipe_valid_sink_valid = litedramcore_bankmachine1_sink_sink_valid;
+assign litedramcore_bankmachine1_sink_sink_ready = litedramcore_bankmachine1_pipe_valid_sink_ready;
+assign litedramcore_bankmachine1_pipe_valid_sink_first = litedramcore_bankmachine1_sink_sink_first;
+assign litedramcore_bankmachine1_pipe_valid_sink_last = litedramcore_bankmachine1_sink_sink_last;
+assign litedramcore_bankmachine1_pipe_valid_sink_payload_we = litedramcore_bankmachine1_sink_sink_payload_we;
+assign litedramcore_bankmachine1_pipe_valid_sink_payload_addr = litedramcore_bankmachine1_sink_sink_payload_addr;
+assign litedramcore_bankmachine1_source_source_valid = litedramcore_bankmachine1_pipe_valid_source_valid;
+assign litedramcore_bankmachine1_pipe_valid_source_ready = litedramcore_bankmachine1_source_source_ready;
+assign litedramcore_bankmachine1_source_source_first = litedramcore_bankmachine1_pipe_valid_source_first;
+assign litedramcore_bankmachine1_source_source_last = litedramcore_bankmachine1_pipe_valid_source_last;
+assign litedramcore_bankmachine1_source_source_payload_we = litedramcore_bankmachine1_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine1_source_source_payload_addr = litedramcore_bankmachine1_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine1_next_state <= 4'd0;
+ litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ if (litedramcore_bankmachine1_cmd_ready) begin
+ litedramcore_bankmachine1_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ if (litedramcore_bankmachine1_cmd_ready) begin
+ litedramcore_bankmachine1_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine1_refresh_req)) begin
+ litedramcore_bankmachine1_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine1_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine1_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine1_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine1_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ litedramcore_bankmachine1_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin
+ litedramcore_bankmachine1_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine1_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine1_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine1_twtpcon_ready) begin
+ litedramcore_bankmachine1_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_row_open <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ litedramcore_bankmachine1_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_row_close <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ litedramcore_bankmachine1_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine1_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine1_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if (litedramcore_bankmachine1_source_source_payload_we) begin
+ litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if (litedramcore_bankmachine1_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if (litedramcore_bankmachine1_source_source_payload_we) begin
+ litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if (litedramcore_bankmachine1_source_source_payload_we) begin
+ litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if (litedramcore_bankmachine1_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+assign litedramcore_bankmachine2_sink_valid = litedramcore_bankmachine2_req_valid;
+assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_sink_ready;
+assign litedramcore_bankmachine2_sink_payload_we = litedramcore_bankmachine2_req_we;
+assign litedramcore_bankmachine2_sink_payload_addr = litedramcore_bankmachine2_req_addr;
+assign litedramcore_bankmachine2_sink_sink_valid = litedramcore_bankmachine2_source_valid;
+assign litedramcore_bankmachine2_source_ready = litedramcore_bankmachine2_sink_sink_ready;
+assign litedramcore_bankmachine2_sink_sink_first = litedramcore_bankmachine2_source_first;
+assign litedramcore_bankmachine2_sink_sink_last = litedramcore_bankmachine2_source_last;
+assign litedramcore_bankmachine2_sink_sink_payload_we = litedramcore_bankmachine2_source_payload_we;
+assign litedramcore_bankmachine2_sink_sink_payload_addr = litedramcore_bankmachine2_source_payload_addr;
+assign litedramcore_bankmachine2_source_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid);
+assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_source_valid | litedramcore_bankmachine2_source_source_valid);
+assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_source_source_payload_addr[22:7]);
assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
always @(*) begin
- litedramcore_bankmachine2_cmd_payload_a <= 16'd0;
- if (litedramcore_bankmachine2_row_col_n_addr_sel) begin
- litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[22:7];
- end else begin
- litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine2_cmd_payload_a <= 16'd0;
+ if (litedramcore_bankmachine2_row_col_n_addr_sel) begin
+ litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_source_source_payload_addr[22:7];
+ end else begin
+ litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write);
assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
always @(*) begin
- litedramcore_bankmachine2_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine2_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[22:7] != litedramcore_bankmachine2_cmd_buffer_source_payload_addr[22:7])) begin
- litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine2_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | litedramcore_bankmachine2_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re);
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine2_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine2_next_state <= 4'd0;
- litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- if (litedramcore_bankmachine2_cmd_ready) begin
- litedramcore_bankmachine2_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- if (litedramcore_bankmachine2_cmd_ready) begin
- litedramcore_bankmachine2_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine2_refresh_req)) begin
- litedramcore_bankmachine2_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine2_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine2_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine2_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine2_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- litedramcore_bankmachine2_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin
- litedramcore_bankmachine2_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine2_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine2_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine2_twtpcon_ready) begin
- litedramcore_bankmachine2_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- litedramcore_bankmachine2_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_row_open <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_row_close <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- litedramcore_bankmachine2_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine2_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine2_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine3_req_valid;
-assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine3_req_we;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine3_req_addr;
-assign litedramcore_bankmachine3_cmd_buffer_sink_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine3_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine3_cmd_buffer_sink_first = litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine3_cmd_buffer_sink_last = litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine3_cmd_buffer_sink_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine3_cmd_buffer_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid);
-assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine3_cmd_buffer_source_valid);
-assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_cmd_buffer_source_payload_addr[22:7]);
+ litedramcore_bankmachine2_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine2_source_valid & litedramcore_bankmachine2_source_source_valid)) begin
+ if ((litedramcore_bankmachine2_source_payload_addr[22:7] != litedramcore_bankmachine2_source_source_payload_addr[22:7])) begin
+ litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine2_syncfifo2_din = {litedramcore_bankmachine2_fifo_in_last, litedramcore_bankmachine2_fifo_in_first, litedramcore_bankmachine2_fifo_in_payload_addr, litedramcore_bankmachine2_fifo_in_payload_we};
+assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout;
+assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout;
+assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout;
+assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout;
+assign litedramcore_bankmachine2_sink_ready = litedramcore_bankmachine2_syncfifo2_writable;
+assign litedramcore_bankmachine2_syncfifo2_we = litedramcore_bankmachine2_sink_valid;
+assign litedramcore_bankmachine2_fifo_in_first = litedramcore_bankmachine2_sink_first;
+assign litedramcore_bankmachine2_fifo_in_last = litedramcore_bankmachine2_sink_last;
+assign litedramcore_bankmachine2_fifo_in_payload_we = litedramcore_bankmachine2_sink_payload_we;
+assign litedramcore_bankmachine2_fifo_in_payload_addr = litedramcore_bankmachine2_sink_payload_addr;
+assign litedramcore_bankmachine2_source_valid = litedramcore_bankmachine2_syncfifo2_readable;
+assign litedramcore_bankmachine2_source_first = litedramcore_bankmachine2_fifo_out_first;
+assign litedramcore_bankmachine2_source_last = litedramcore_bankmachine2_fifo_out_last;
+assign litedramcore_bankmachine2_source_payload_we = litedramcore_bankmachine2_fifo_out_payload_we;
+assign litedramcore_bankmachine2_source_payload_addr = litedramcore_bankmachine2_fifo_out_payload_addr;
+assign litedramcore_bankmachine2_syncfifo2_re = litedramcore_bankmachine2_source_ready;
+always @(*) begin
+ litedramcore_bankmachine2_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine2_replace) begin
+ litedramcore_bankmachine2_wrport_adr <= (litedramcore_bankmachine2_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine2_wrport_adr <= litedramcore_bankmachine2_produce;
+ end
+end
+assign litedramcore_bankmachine2_wrport_dat_w = litedramcore_bankmachine2_syncfifo2_din;
+assign litedramcore_bankmachine2_wrport_we = (litedramcore_bankmachine2_syncfifo2_we & (litedramcore_bankmachine2_syncfifo2_writable | litedramcore_bankmachine2_replace));
+assign litedramcore_bankmachine2_do_read = (litedramcore_bankmachine2_syncfifo2_readable & litedramcore_bankmachine2_syncfifo2_re);
+assign litedramcore_bankmachine2_rdport_adr = litedramcore_bankmachine2_consume;
+assign litedramcore_bankmachine2_syncfifo2_dout = litedramcore_bankmachine2_rdport_dat_r;
+assign litedramcore_bankmachine2_syncfifo2_writable = (litedramcore_bankmachine2_level != 5'd16);
+assign litedramcore_bankmachine2_syncfifo2_readable = (litedramcore_bankmachine2_level != 1'd0);
+assign litedramcore_bankmachine2_pipe_valid_sink_ready = ((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready);
+assign litedramcore_bankmachine2_pipe_valid_sink_valid = litedramcore_bankmachine2_sink_sink_valid;
+assign litedramcore_bankmachine2_sink_sink_ready = litedramcore_bankmachine2_pipe_valid_sink_ready;
+assign litedramcore_bankmachine2_pipe_valid_sink_first = litedramcore_bankmachine2_sink_sink_first;
+assign litedramcore_bankmachine2_pipe_valid_sink_last = litedramcore_bankmachine2_sink_sink_last;
+assign litedramcore_bankmachine2_pipe_valid_sink_payload_we = litedramcore_bankmachine2_sink_sink_payload_we;
+assign litedramcore_bankmachine2_pipe_valid_sink_payload_addr = litedramcore_bankmachine2_sink_sink_payload_addr;
+assign litedramcore_bankmachine2_source_source_valid = litedramcore_bankmachine2_pipe_valid_source_valid;
+assign litedramcore_bankmachine2_pipe_valid_source_ready = litedramcore_bankmachine2_source_source_ready;
+assign litedramcore_bankmachine2_source_source_first = litedramcore_bankmachine2_pipe_valid_source_first;
+assign litedramcore_bankmachine2_source_source_last = litedramcore_bankmachine2_pipe_valid_source_last;
+assign litedramcore_bankmachine2_source_source_payload_we = litedramcore_bankmachine2_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine2_source_source_payload_addr = litedramcore_bankmachine2_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine2_next_state <= 4'd0;
+ litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ if (litedramcore_bankmachine2_cmd_ready) begin
+ litedramcore_bankmachine2_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ if (litedramcore_bankmachine2_cmd_ready) begin
+ litedramcore_bankmachine2_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine2_refresh_req)) begin
+ litedramcore_bankmachine2_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine2_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine2_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine2_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine2_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ litedramcore_bankmachine2_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin
+ litedramcore_bankmachine2_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine2_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine2_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if (litedramcore_bankmachine2_source_source_payload_we) begin
+ litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if (litedramcore_bankmachine2_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if (litedramcore_bankmachine2_source_source_payload_we) begin
+ litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if (litedramcore_bankmachine2_source_source_payload_we) begin
+ litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if (litedramcore_bankmachine2_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine2_twtpcon_ready) begin
+ litedramcore_bankmachine2_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_row_open <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ litedramcore_bankmachine2_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_row_close <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ litedramcore_bankmachine2_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine2_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine2_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+assign litedramcore_bankmachine3_sink_valid = litedramcore_bankmachine3_req_valid;
+assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_sink_ready;
+assign litedramcore_bankmachine3_sink_payload_we = litedramcore_bankmachine3_req_we;
+assign litedramcore_bankmachine3_sink_payload_addr = litedramcore_bankmachine3_req_addr;
+assign litedramcore_bankmachine3_sink_sink_valid = litedramcore_bankmachine3_source_valid;
+assign litedramcore_bankmachine3_source_ready = litedramcore_bankmachine3_sink_sink_ready;
+assign litedramcore_bankmachine3_sink_sink_first = litedramcore_bankmachine3_source_first;
+assign litedramcore_bankmachine3_sink_sink_last = litedramcore_bankmachine3_source_last;
+assign litedramcore_bankmachine3_sink_sink_payload_we = litedramcore_bankmachine3_source_payload_we;
+assign litedramcore_bankmachine3_sink_sink_payload_addr = litedramcore_bankmachine3_source_payload_addr;
+assign litedramcore_bankmachine3_source_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid);
+assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_source_valid | litedramcore_bankmachine3_source_source_valid);
+assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_source_source_payload_addr[22:7]);
assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
always @(*) begin
- litedramcore_bankmachine3_cmd_payload_a <= 16'd0;
- if (litedramcore_bankmachine3_row_col_n_addr_sel) begin
- litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[22:7];
- end else begin
- litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine3_cmd_payload_a <= 16'd0;
+ if (litedramcore_bankmachine3_row_col_n_addr_sel) begin
+ litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_source_source_payload_addr[22:7];
+ end else begin
+ litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write);
assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
always @(*) begin
- litedramcore_bankmachine3_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine3_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[22:7] != litedramcore_bankmachine3_cmd_buffer_source_payload_addr[22:7])) begin
- litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine3_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | litedramcore_bankmachine3_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re);
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine3_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine3_next_state <= 4'd0;
- litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- if (litedramcore_bankmachine3_cmd_ready) begin
- litedramcore_bankmachine3_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- if (litedramcore_bankmachine3_cmd_ready) begin
- litedramcore_bankmachine3_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine3_refresh_req)) begin
- litedramcore_bankmachine3_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine3_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine3_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine3_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine3_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- litedramcore_bankmachine3_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin
- litedramcore_bankmachine3_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine3_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine3_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine3_twtpcon_ready) begin
- litedramcore_bankmachine3_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- litedramcore_bankmachine3_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_row_open <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_row_close <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- litedramcore_bankmachine3_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine3_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine3_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine4_req_valid;
-assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine4_req_we;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine4_req_addr;
-assign litedramcore_bankmachine4_cmd_buffer_sink_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine4_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine4_cmd_buffer_sink_first = litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine4_cmd_buffer_sink_last = litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine4_cmd_buffer_sink_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine4_cmd_buffer_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid);
-assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine4_cmd_buffer_source_valid);
-assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_cmd_buffer_source_payload_addr[22:7]);
+ litedramcore_bankmachine3_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine3_source_valid & litedramcore_bankmachine3_source_source_valid)) begin
+ if ((litedramcore_bankmachine3_source_payload_addr[22:7] != litedramcore_bankmachine3_source_source_payload_addr[22:7])) begin
+ litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine3_syncfifo3_din = {litedramcore_bankmachine3_fifo_in_last, litedramcore_bankmachine3_fifo_in_first, litedramcore_bankmachine3_fifo_in_payload_addr, litedramcore_bankmachine3_fifo_in_payload_we};
+assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout;
+assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout;
+assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout;
+assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout;
+assign litedramcore_bankmachine3_sink_ready = litedramcore_bankmachine3_syncfifo3_writable;
+assign litedramcore_bankmachine3_syncfifo3_we = litedramcore_bankmachine3_sink_valid;
+assign litedramcore_bankmachine3_fifo_in_first = litedramcore_bankmachine3_sink_first;
+assign litedramcore_bankmachine3_fifo_in_last = litedramcore_bankmachine3_sink_last;
+assign litedramcore_bankmachine3_fifo_in_payload_we = litedramcore_bankmachine3_sink_payload_we;
+assign litedramcore_bankmachine3_fifo_in_payload_addr = litedramcore_bankmachine3_sink_payload_addr;
+assign litedramcore_bankmachine3_source_valid = litedramcore_bankmachine3_syncfifo3_readable;
+assign litedramcore_bankmachine3_source_first = litedramcore_bankmachine3_fifo_out_first;
+assign litedramcore_bankmachine3_source_last = litedramcore_bankmachine3_fifo_out_last;
+assign litedramcore_bankmachine3_source_payload_we = litedramcore_bankmachine3_fifo_out_payload_we;
+assign litedramcore_bankmachine3_source_payload_addr = litedramcore_bankmachine3_fifo_out_payload_addr;
+assign litedramcore_bankmachine3_syncfifo3_re = litedramcore_bankmachine3_source_ready;
+always @(*) begin
+ litedramcore_bankmachine3_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine3_replace) begin
+ litedramcore_bankmachine3_wrport_adr <= (litedramcore_bankmachine3_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine3_wrport_adr <= litedramcore_bankmachine3_produce;
+ end
+end
+assign litedramcore_bankmachine3_wrport_dat_w = litedramcore_bankmachine3_syncfifo3_din;
+assign litedramcore_bankmachine3_wrport_we = (litedramcore_bankmachine3_syncfifo3_we & (litedramcore_bankmachine3_syncfifo3_writable | litedramcore_bankmachine3_replace));
+assign litedramcore_bankmachine3_do_read = (litedramcore_bankmachine3_syncfifo3_readable & litedramcore_bankmachine3_syncfifo3_re);
+assign litedramcore_bankmachine3_rdport_adr = litedramcore_bankmachine3_consume;
+assign litedramcore_bankmachine3_syncfifo3_dout = litedramcore_bankmachine3_rdport_dat_r;
+assign litedramcore_bankmachine3_syncfifo3_writable = (litedramcore_bankmachine3_level != 5'd16);
+assign litedramcore_bankmachine3_syncfifo3_readable = (litedramcore_bankmachine3_level != 1'd0);
+assign litedramcore_bankmachine3_pipe_valid_sink_ready = ((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready);
+assign litedramcore_bankmachine3_pipe_valid_sink_valid = litedramcore_bankmachine3_sink_sink_valid;
+assign litedramcore_bankmachine3_sink_sink_ready = litedramcore_bankmachine3_pipe_valid_sink_ready;
+assign litedramcore_bankmachine3_pipe_valid_sink_first = litedramcore_bankmachine3_sink_sink_first;
+assign litedramcore_bankmachine3_pipe_valid_sink_last = litedramcore_bankmachine3_sink_sink_last;
+assign litedramcore_bankmachine3_pipe_valid_sink_payload_we = litedramcore_bankmachine3_sink_sink_payload_we;
+assign litedramcore_bankmachine3_pipe_valid_sink_payload_addr = litedramcore_bankmachine3_sink_sink_payload_addr;
+assign litedramcore_bankmachine3_source_source_valid = litedramcore_bankmachine3_pipe_valid_source_valid;
+assign litedramcore_bankmachine3_pipe_valid_source_ready = litedramcore_bankmachine3_source_source_ready;
+assign litedramcore_bankmachine3_source_source_first = litedramcore_bankmachine3_pipe_valid_source_first;
+assign litedramcore_bankmachine3_source_source_last = litedramcore_bankmachine3_pipe_valid_source_last;
+assign litedramcore_bankmachine3_source_source_payload_we = litedramcore_bankmachine3_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine3_source_source_payload_addr = litedramcore_bankmachine3_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine3_next_state <= 4'd0;
+ litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ if (litedramcore_bankmachine3_cmd_ready) begin
+ litedramcore_bankmachine3_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ if (litedramcore_bankmachine3_cmd_ready) begin
+ litedramcore_bankmachine3_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine3_refresh_req)) begin
+ litedramcore_bankmachine3_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine3_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine3_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine3_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine3_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ litedramcore_bankmachine3_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin
+ litedramcore_bankmachine3_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine3_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine3_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if (litedramcore_bankmachine3_source_source_payload_we) begin
+ litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if (litedramcore_bankmachine3_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if (litedramcore_bankmachine3_source_source_payload_we) begin
+ litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if (litedramcore_bankmachine3_source_source_payload_we) begin
+ litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if (litedramcore_bankmachine3_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine3_twtpcon_ready) begin
+ litedramcore_bankmachine3_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_row_open <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ litedramcore_bankmachine3_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_row_close <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ litedramcore_bankmachine3_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine3_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine3_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+assign litedramcore_bankmachine4_sink_valid = litedramcore_bankmachine4_req_valid;
+assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_sink_ready;
+assign litedramcore_bankmachine4_sink_payload_we = litedramcore_bankmachine4_req_we;
+assign litedramcore_bankmachine4_sink_payload_addr = litedramcore_bankmachine4_req_addr;
+assign litedramcore_bankmachine4_sink_sink_valid = litedramcore_bankmachine4_source_valid;
+assign litedramcore_bankmachine4_source_ready = litedramcore_bankmachine4_sink_sink_ready;
+assign litedramcore_bankmachine4_sink_sink_first = litedramcore_bankmachine4_source_first;
+assign litedramcore_bankmachine4_sink_sink_last = litedramcore_bankmachine4_source_last;
+assign litedramcore_bankmachine4_sink_sink_payload_we = litedramcore_bankmachine4_source_payload_we;
+assign litedramcore_bankmachine4_sink_sink_payload_addr = litedramcore_bankmachine4_source_payload_addr;
+assign litedramcore_bankmachine4_source_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid);
+assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_source_valid | litedramcore_bankmachine4_source_source_valid);
+assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_source_source_payload_addr[22:7]);
assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
always @(*) begin
- litedramcore_bankmachine4_cmd_payload_a <= 16'd0;
- if (litedramcore_bankmachine4_row_col_n_addr_sel) begin
- litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[22:7];
- end else begin
- litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine4_cmd_payload_a <= 16'd0;
+ if (litedramcore_bankmachine4_row_col_n_addr_sel) begin
+ litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_source_source_payload_addr[22:7];
+ end else begin
+ litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write);
assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
always @(*) begin
- litedramcore_bankmachine4_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine4_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[22:7] != litedramcore_bankmachine4_cmd_buffer_source_payload_addr[22:7])) begin
- litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine4_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | litedramcore_bankmachine4_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re);
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine4_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine4_next_state <= 4'd0;
- litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- if (litedramcore_bankmachine4_cmd_ready) begin
- litedramcore_bankmachine4_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- if (litedramcore_bankmachine4_cmd_ready) begin
- litedramcore_bankmachine4_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine4_refresh_req)) begin
- litedramcore_bankmachine4_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine4_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine4_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine4_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine4_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- litedramcore_bankmachine4_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin
- litedramcore_bankmachine4_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine4_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine4_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine4_twtpcon_ready) begin
- litedramcore_bankmachine4_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- litedramcore_bankmachine4_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_row_open <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_row_close <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- litedramcore_bankmachine4_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine4_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine4_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine5_req_valid;
-assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine5_req_we;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine5_req_addr;
-assign litedramcore_bankmachine5_cmd_buffer_sink_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine5_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine5_cmd_buffer_sink_first = litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine5_cmd_buffer_sink_last = litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine5_cmd_buffer_sink_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine5_cmd_buffer_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid);
-assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine5_cmd_buffer_source_valid);
-assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_cmd_buffer_source_payload_addr[22:7]);
+ litedramcore_bankmachine4_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine4_source_valid & litedramcore_bankmachine4_source_source_valid)) begin
+ if ((litedramcore_bankmachine4_source_payload_addr[22:7] != litedramcore_bankmachine4_source_source_payload_addr[22:7])) begin
+ litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine4_syncfifo4_din = {litedramcore_bankmachine4_fifo_in_last, litedramcore_bankmachine4_fifo_in_first, litedramcore_bankmachine4_fifo_in_payload_addr, litedramcore_bankmachine4_fifo_in_payload_we};
+assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout;
+assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout;
+assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout;
+assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout;
+assign litedramcore_bankmachine4_sink_ready = litedramcore_bankmachine4_syncfifo4_writable;
+assign litedramcore_bankmachine4_syncfifo4_we = litedramcore_bankmachine4_sink_valid;
+assign litedramcore_bankmachine4_fifo_in_first = litedramcore_bankmachine4_sink_first;
+assign litedramcore_bankmachine4_fifo_in_last = litedramcore_bankmachine4_sink_last;
+assign litedramcore_bankmachine4_fifo_in_payload_we = litedramcore_bankmachine4_sink_payload_we;
+assign litedramcore_bankmachine4_fifo_in_payload_addr = litedramcore_bankmachine4_sink_payload_addr;
+assign litedramcore_bankmachine4_source_valid = litedramcore_bankmachine4_syncfifo4_readable;
+assign litedramcore_bankmachine4_source_first = litedramcore_bankmachine4_fifo_out_first;
+assign litedramcore_bankmachine4_source_last = litedramcore_bankmachine4_fifo_out_last;
+assign litedramcore_bankmachine4_source_payload_we = litedramcore_bankmachine4_fifo_out_payload_we;
+assign litedramcore_bankmachine4_source_payload_addr = litedramcore_bankmachine4_fifo_out_payload_addr;
+assign litedramcore_bankmachine4_syncfifo4_re = litedramcore_bankmachine4_source_ready;
+always @(*) begin
+ litedramcore_bankmachine4_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine4_replace) begin
+ litedramcore_bankmachine4_wrport_adr <= (litedramcore_bankmachine4_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine4_wrport_adr <= litedramcore_bankmachine4_produce;
+ end
+end
+assign litedramcore_bankmachine4_wrport_dat_w = litedramcore_bankmachine4_syncfifo4_din;
+assign litedramcore_bankmachine4_wrport_we = (litedramcore_bankmachine4_syncfifo4_we & (litedramcore_bankmachine4_syncfifo4_writable | litedramcore_bankmachine4_replace));
+assign litedramcore_bankmachine4_do_read = (litedramcore_bankmachine4_syncfifo4_readable & litedramcore_bankmachine4_syncfifo4_re);
+assign litedramcore_bankmachine4_rdport_adr = litedramcore_bankmachine4_consume;
+assign litedramcore_bankmachine4_syncfifo4_dout = litedramcore_bankmachine4_rdport_dat_r;
+assign litedramcore_bankmachine4_syncfifo4_writable = (litedramcore_bankmachine4_level != 5'd16);
+assign litedramcore_bankmachine4_syncfifo4_readable = (litedramcore_bankmachine4_level != 1'd0);
+assign litedramcore_bankmachine4_pipe_valid_sink_ready = ((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready);
+assign litedramcore_bankmachine4_pipe_valid_sink_valid = litedramcore_bankmachine4_sink_sink_valid;
+assign litedramcore_bankmachine4_sink_sink_ready = litedramcore_bankmachine4_pipe_valid_sink_ready;
+assign litedramcore_bankmachine4_pipe_valid_sink_first = litedramcore_bankmachine4_sink_sink_first;
+assign litedramcore_bankmachine4_pipe_valid_sink_last = litedramcore_bankmachine4_sink_sink_last;
+assign litedramcore_bankmachine4_pipe_valid_sink_payload_we = litedramcore_bankmachine4_sink_sink_payload_we;
+assign litedramcore_bankmachine4_pipe_valid_sink_payload_addr = litedramcore_bankmachine4_sink_sink_payload_addr;
+assign litedramcore_bankmachine4_source_source_valid = litedramcore_bankmachine4_pipe_valid_source_valid;
+assign litedramcore_bankmachine4_pipe_valid_source_ready = litedramcore_bankmachine4_source_source_ready;
+assign litedramcore_bankmachine4_source_source_first = litedramcore_bankmachine4_pipe_valid_source_first;
+assign litedramcore_bankmachine4_source_source_last = litedramcore_bankmachine4_pipe_valid_source_last;
+assign litedramcore_bankmachine4_source_source_payload_we = litedramcore_bankmachine4_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine4_source_source_payload_addr = litedramcore_bankmachine4_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine4_next_state <= 4'd0;
+ litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ if (litedramcore_bankmachine4_cmd_ready) begin
+ litedramcore_bankmachine4_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ if (litedramcore_bankmachine4_cmd_ready) begin
+ litedramcore_bankmachine4_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine4_refresh_req)) begin
+ litedramcore_bankmachine4_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine4_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine4_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine4_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine4_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ litedramcore_bankmachine4_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin
+ litedramcore_bankmachine4_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine4_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine4_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if (litedramcore_bankmachine4_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if (litedramcore_bankmachine4_source_source_payload_we) begin
+ litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if (litedramcore_bankmachine4_source_source_payload_we) begin
+ litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if (litedramcore_bankmachine4_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine4_twtpcon_ready) begin
+ litedramcore_bankmachine4_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_row_open <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ litedramcore_bankmachine4_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ litedramcore_bankmachine4_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ litedramcore_bankmachine4_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_row_close <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ litedramcore_bankmachine4_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine4_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine4_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if (litedramcore_bankmachine4_source_source_payload_we) begin
+ litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+assign litedramcore_bankmachine5_sink_valid = litedramcore_bankmachine5_req_valid;
+assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_sink_ready;
+assign litedramcore_bankmachine5_sink_payload_we = litedramcore_bankmachine5_req_we;
+assign litedramcore_bankmachine5_sink_payload_addr = litedramcore_bankmachine5_req_addr;
+assign litedramcore_bankmachine5_sink_sink_valid = litedramcore_bankmachine5_source_valid;
+assign litedramcore_bankmachine5_source_ready = litedramcore_bankmachine5_sink_sink_ready;
+assign litedramcore_bankmachine5_sink_sink_first = litedramcore_bankmachine5_source_first;
+assign litedramcore_bankmachine5_sink_sink_last = litedramcore_bankmachine5_source_last;
+assign litedramcore_bankmachine5_sink_sink_payload_we = litedramcore_bankmachine5_source_payload_we;
+assign litedramcore_bankmachine5_sink_sink_payload_addr = litedramcore_bankmachine5_source_payload_addr;
+assign litedramcore_bankmachine5_source_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid);
+assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_source_valid | litedramcore_bankmachine5_source_source_valid);
+assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_source_source_payload_addr[22:7]);
assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
always @(*) begin
- litedramcore_bankmachine5_cmd_payload_a <= 16'd0;
- if (litedramcore_bankmachine5_row_col_n_addr_sel) begin
- litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[22:7];
- end else begin
- litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine5_cmd_payload_a <= 16'd0;
+ if (litedramcore_bankmachine5_row_col_n_addr_sel) begin
+ litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_source_source_payload_addr[22:7];
+ end else begin
+ litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write);
assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
always @(*) begin
- litedramcore_bankmachine5_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine5_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[22:7] != litedramcore_bankmachine5_cmd_buffer_source_payload_addr[22:7])) begin
- litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine5_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | litedramcore_bankmachine5_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re);
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine5_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine5_next_state <= 4'd0;
- litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- if (litedramcore_bankmachine5_cmd_ready) begin
- litedramcore_bankmachine5_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- if (litedramcore_bankmachine5_cmd_ready) begin
- litedramcore_bankmachine5_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine5_refresh_req)) begin
- litedramcore_bankmachine5_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine5_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine5_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine5_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine5_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- litedramcore_bankmachine5_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin
- litedramcore_bankmachine5_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine5_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine5_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine5_twtpcon_ready) begin
- litedramcore_bankmachine5_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_row_open <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_row_close <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- litedramcore_bankmachine5_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine5_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine5_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine6_req_valid;
-assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine6_req_we;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine6_req_addr;
-assign litedramcore_bankmachine6_cmd_buffer_sink_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine6_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine6_cmd_buffer_sink_first = litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine6_cmd_buffer_sink_last = litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine6_cmd_buffer_sink_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine6_cmd_buffer_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid);
-assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine6_cmd_buffer_source_valid);
-assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_cmd_buffer_source_payload_addr[22:7]);
+ litedramcore_bankmachine5_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine5_source_valid & litedramcore_bankmachine5_source_source_valid)) begin
+ if ((litedramcore_bankmachine5_source_payload_addr[22:7] != litedramcore_bankmachine5_source_source_payload_addr[22:7])) begin
+ litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine5_syncfifo5_din = {litedramcore_bankmachine5_fifo_in_last, litedramcore_bankmachine5_fifo_in_first, litedramcore_bankmachine5_fifo_in_payload_addr, litedramcore_bankmachine5_fifo_in_payload_we};
+assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout;
+assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout;
+assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout;
+assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout;
+assign litedramcore_bankmachine5_sink_ready = litedramcore_bankmachine5_syncfifo5_writable;
+assign litedramcore_bankmachine5_syncfifo5_we = litedramcore_bankmachine5_sink_valid;
+assign litedramcore_bankmachine5_fifo_in_first = litedramcore_bankmachine5_sink_first;
+assign litedramcore_bankmachine5_fifo_in_last = litedramcore_bankmachine5_sink_last;
+assign litedramcore_bankmachine5_fifo_in_payload_we = litedramcore_bankmachine5_sink_payload_we;
+assign litedramcore_bankmachine5_fifo_in_payload_addr = litedramcore_bankmachine5_sink_payload_addr;
+assign litedramcore_bankmachine5_source_valid = litedramcore_bankmachine5_syncfifo5_readable;
+assign litedramcore_bankmachine5_source_first = litedramcore_bankmachine5_fifo_out_first;
+assign litedramcore_bankmachine5_source_last = litedramcore_bankmachine5_fifo_out_last;
+assign litedramcore_bankmachine5_source_payload_we = litedramcore_bankmachine5_fifo_out_payload_we;
+assign litedramcore_bankmachine5_source_payload_addr = litedramcore_bankmachine5_fifo_out_payload_addr;
+assign litedramcore_bankmachine5_syncfifo5_re = litedramcore_bankmachine5_source_ready;
+always @(*) begin
+ litedramcore_bankmachine5_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine5_replace) begin
+ litedramcore_bankmachine5_wrport_adr <= (litedramcore_bankmachine5_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine5_wrport_adr <= litedramcore_bankmachine5_produce;
+ end
+end
+assign litedramcore_bankmachine5_wrport_dat_w = litedramcore_bankmachine5_syncfifo5_din;
+assign litedramcore_bankmachine5_wrport_we = (litedramcore_bankmachine5_syncfifo5_we & (litedramcore_bankmachine5_syncfifo5_writable | litedramcore_bankmachine5_replace));
+assign litedramcore_bankmachine5_do_read = (litedramcore_bankmachine5_syncfifo5_readable & litedramcore_bankmachine5_syncfifo5_re);
+assign litedramcore_bankmachine5_rdport_adr = litedramcore_bankmachine5_consume;
+assign litedramcore_bankmachine5_syncfifo5_dout = litedramcore_bankmachine5_rdport_dat_r;
+assign litedramcore_bankmachine5_syncfifo5_writable = (litedramcore_bankmachine5_level != 5'd16);
+assign litedramcore_bankmachine5_syncfifo5_readable = (litedramcore_bankmachine5_level != 1'd0);
+assign litedramcore_bankmachine5_pipe_valid_sink_ready = ((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready);
+assign litedramcore_bankmachine5_pipe_valid_sink_valid = litedramcore_bankmachine5_sink_sink_valid;
+assign litedramcore_bankmachine5_sink_sink_ready = litedramcore_bankmachine5_pipe_valid_sink_ready;
+assign litedramcore_bankmachine5_pipe_valid_sink_first = litedramcore_bankmachine5_sink_sink_first;
+assign litedramcore_bankmachine5_pipe_valid_sink_last = litedramcore_bankmachine5_sink_sink_last;
+assign litedramcore_bankmachine5_pipe_valid_sink_payload_we = litedramcore_bankmachine5_sink_sink_payload_we;
+assign litedramcore_bankmachine5_pipe_valid_sink_payload_addr = litedramcore_bankmachine5_sink_sink_payload_addr;
+assign litedramcore_bankmachine5_source_source_valid = litedramcore_bankmachine5_pipe_valid_source_valid;
+assign litedramcore_bankmachine5_pipe_valid_source_ready = litedramcore_bankmachine5_source_source_ready;
+assign litedramcore_bankmachine5_source_source_first = litedramcore_bankmachine5_pipe_valid_source_first;
+assign litedramcore_bankmachine5_source_source_last = litedramcore_bankmachine5_pipe_valid_source_last;
+assign litedramcore_bankmachine5_source_source_payload_we = litedramcore_bankmachine5_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine5_source_source_payload_addr = litedramcore_bankmachine5_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine5_next_state <= 4'd0;
+ litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ if (litedramcore_bankmachine5_cmd_ready) begin
+ litedramcore_bankmachine5_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ if (litedramcore_bankmachine5_cmd_ready) begin
+ litedramcore_bankmachine5_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine5_refresh_req)) begin
+ litedramcore_bankmachine5_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine5_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine5_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine5_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine5_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ litedramcore_bankmachine5_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin
+ litedramcore_bankmachine5_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine5_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine5_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine5_twtpcon_ready) begin
+ litedramcore_bankmachine5_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_row_open <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_row_close <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ litedramcore_bankmachine5_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine5_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine5_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if (litedramcore_bankmachine5_source_source_payload_we) begin
+ litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if (litedramcore_bankmachine5_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if (litedramcore_bankmachine5_source_source_payload_we) begin
+ litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if (litedramcore_bankmachine5_source_source_payload_we) begin
+ litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if (litedramcore_bankmachine5_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+assign litedramcore_bankmachine6_sink_valid = litedramcore_bankmachine6_req_valid;
+assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_sink_ready;
+assign litedramcore_bankmachine6_sink_payload_we = litedramcore_bankmachine6_req_we;
+assign litedramcore_bankmachine6_sink_payload_addr = litedramcore_bankmachine6_req_addr;
+assign litedramcore_bankmachine6_sink_sink_valid = litedramcore_bankmachine6_source_valid;
+assign litedramcore_bankmachine6_source_ready = litedramcore_bankmachine6_sink_sink_ready;
+assign litedramcore_bankmachine6_sink_sink_first = litedramcore_bankmachine6_source_first;
+assign litedramcore_bankmachine6_sink_sink_last = litedramcore_bankmachine6_source_last;
+assign litedramcore_bankmachine6_sink_sink_payload_we = litedramcore_bankmachine6_source_payload_we;
+assign litedramcore_bankmachine6_sink_sink_payload_addr = litedramcore_bankmachine6_source_payload_addr;
+assign litedramcore_bankmachine6_source_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid);
+assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_source_valid | litedramcore_bankmachine6_source_source_valid);
+assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_source_source_payload_addr[22:7]);
assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
always @(*) begin
- litedramcore_bankmachine6_cmd_payload_a <= 16'd0;
- if (litedramcore_bankmachine6_row_col_n_addr_sel) begin
- litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[22:7];
- end else begin
- litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine6_cmd_payload_a <= 16'd0;
+ if (litedramcore_bankmachine6_row_col_n_addr_sel) begin
+ litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_source_source_payload_addr[22:7];
+ end else begin
+ litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write);
assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
always @(*) begin
- litedramcore_bankmachine6_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine6_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[22:7] != litedramcore_bankmachine6_cmd_buffer_source_payload_addr[22:7])) begin
- litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine6_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | litedramcore_bankmachine6_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re);
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine6_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine6_next_state <= 4'd0;
- litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- if (litedramcore_bankmachine6_cmd_ready) begin
- litedramcore_bankmachine6_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- if (litedramcore_bankmachine6_cmd_ready) begin
- litedramcore_bankmachine6_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine6_refresh_req)) begin
- litedramcore_bankmachine6_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine6_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine6_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine6_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine6_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- litedramcore_bankmachine6_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin
- litedramcore_bankmachine6_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine6_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine6_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine6_twtpcon_ready) begin
- litedramcore_bankmachine6_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- litedramcore_bankmachine6_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_row_open <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_row_close <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- litedramcore_bankmachine6_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine6_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine6_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine7_req_valid;
-assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine7_req_we;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine7_req_addr;
-assign litedramcore_bankmachine7_cmd_buffer_sink_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine7_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine7_cmd_buffer_sink_first = litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine7_cmd_buffer_sink_last = litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine7_cmd_buffer_sink_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine7_cmd_buffer_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid);
-assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine7_cmd_buffer_source_valid);
-assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_cmd_buffer_source_payload_addr[22:7]);
+ litedramcore_bankmachine6_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine6_source_valid & litedramcore_bankmachine6_source_source_valid)) begin
+ if ((litedramcore_bankmachine6_source_payload_addr[22:7] != litedramcore_bankmachine6_source_source_payload_addr[22:7])) begin
+ litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine6_syncfifo6_din = {litedramcore_bankmachine6_fifo_in_last, litedramcore_bankmachine6_fifo_in_first, litedramcore_bankmachine6_fifo_in_payload_addr, litedramcore_bankmachine6_fifo_in_payload_we};
+assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout;
+assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout;
+assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout;
+assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout;
+assign litedramcore_bankmachine6_sink_ready = litedramcore_bankmachine6_syncfifo6_writable;
+assign litedramcore_bankmachine6_syncfifo6_we = litedramcore_bankmachine6_sink_valid;
+assign litedramcore_bankmachine6_fifo_in_first = litedramcore_bankmachine6_sink_first;
+assign litedramcore_bankmachine6_fifo_in_last = litedramcore_bankmachine6_sink_last;
+assign litedramcore_bankmachine6_fifo_in_payload_we = litedramcore_bankmachine6_sink_payload_we;
+assign litedramcore_bankmachine6_fifo_in_payload_addr = litedramcore_bankmachine6_sink_payload_addr;
+assign litedramcore_bankmachine6_source_valid = litedramcore_bankmachine6_syncfifo6_readable;
+assign litedramcore_bankmachine6_source_first = litedramcore_bankmachine6_fifo_out_first;
+assign litedramcore_bankmachine6_source_last = litedramcore_bankmachine6_fifo_out_last;
+assign litedramcore_bankmachine6_source_payload_we = litedramcore_bankmachine6_fifo_out_payload_we;
+assign litedramcore_bankmachine6_source_payload_addr = litedramcore_bankmachine6_fifo_out_payload_addr;
+assign litedramcore_bankmachine6_syncfifo6_re = litedramcore_bankmachine6_source_ready;
+always @(*) begin
+ litedramcore_bankmachine6_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine6_replace) begin
+ litedramcore_bankmachine6_wrport_adr <= (litedramcore_bankmachine6_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine6_wrport_adr <= litedramcore_bankmachine6_produce;
+ end
+end
+assign litedramcore_bankmachine6_wrport_dat_w = litedramcore_bankmachine6_syncfifo6_din;
+assign litedramcore_bankmachine6_wrport_we = (litedramcore_bankmachine6_syncfifo6_we & (litedramcore_bankmachine6_syncfifo6_writable | litedramcore_bankmachine6_replace));
+assign litedramcore_bankmachine6_do_read = (litedramcore_bankmachine6_syncfifo6_readable & litedramcore_bankmachine6_syncfifo6_re);
+assign litedramcore_bankmachine6_rdport_adr = litedramcore_bankmachine6_consume;
+assign litedramcore_bankmachine6_syncfifo6_dout = litedramcore_bankmachine6_rdport_dat_r;
+assign litedramcore_bankmachine6_syncfifo6_writable = (litedramcore_bankmachine6_level != 5'd16);
+assign litedramcore_bankmachine6_syncfifo6_readable = (litedramcore_bankmachine6_level != 1'd0);
+assign litedramcore_bankmachine6_pipe_valid_sink_ready = ((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready);
+assign litedramcore_bankmachine6_pipe_valid_sink_valid = litedramcore_bankmachine6_sink_sink_valid;
+assign litedramcore_bankmachine6_sink_sink_ready = litedramcore_bankmachine6_pipe_valid_sink_ready;
+assign litedramcore_bankmachine6_pipe_valid_sink_first = litedramcore_bankmachine6_sink_sink_first;
+assign litedramcore_bankmachine6_pipe_valid_sink_last = litedramcore_bankmachine6_sink_sink_last;
+assign litedramcore_bankmachine6_pipe_valid_sink_payload_we = litedramcore_bankmachine6_sink_sink_payload_we;
+assign litedramcore_bankmachine6_pipe_valid_sink_payload_addr = litedramcore_bankmachine6_sink_sink_payload_addr;
+assign litedramcore_bankmachine6_source_source_valid = litedramcore_bankmachine6_pipe_valid_source_valid;
+assign litedramcore_bankmachine6_pipe_valid_source_ready = litedramcore_bankmachine6_source_source_ready;
+assign litedramcore_bankmachine6_source_source_first = litedramcore_bankmachine6_pipe_valid_source_first;
+assign litedramcore_bankmachine6_source_source_last = litedramcore_bankmachine6_pipe_valid_source_last;
+assign litedramcore_bankmachine6_source_source_payload_we = litedramcore_bankmachine6_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine6_source_source_payload_addr = litedramcore_bankmachine6_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine6_next_state <= 4'd0;
+ litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ if (litedramcore_bankmachine6_cmd_ready) begin
+ litedramcore_bankmachine6_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ if (litedramcore_bankmachine6_cmd_ready) begin
+ litedramcore_bankmachine6_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine6_refresh_req)) begin
+ litedramcore_bankmachine6_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine6_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine6_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine6_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine6_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ litedramcore_bankmachine6_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin
+ litedramcore_bankmachine6_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine6_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine6_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if (litedramcore_bankmachine6_source_source_payload_we) begin
+ litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if (litedramcore_bankmachine6_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if (litedramcore_bankmachine6_source_source_payload_we) begin
+ litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if (litedramcore_bankmachine6_source_source_payload_we) begin
+ litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if (litedramcore_bankmachine6_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine6_twtpcon_ready) begin
+ litedramcore_bankmachine6_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_row_open <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ litedramcore_bankmachine6_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_row_close <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ litedramcore_bankmachine6_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine6_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine6_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+assign litedramcore_bankmachine7_sink_valid = litedramcore_bankmachine7_req_valid;
+assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_sink_ready;
+assign litedramcore_bankmachine7_sink_payload_we = litedramcore_bankmachine7_req_we;
+assign litedramcore_bankmachine7_sink_payload_addr = litedramcore_bankmachine7_req_addr;
+assign litedramcore_bankmachine7_sink_sink_valid = litedramcore_bankmachine7_source_valid;
+assign litedramcore_bankmachine7_source_ready = litedramcore_bankmachine7_sink_sink_ready;
+assign litedramcore_bankmachine7_sink_sink_first = litedramcore_bankmachine7_source_first;
+assign litedramcore_bankmachine7_sink_sink_last = litedramcore_bankmachine7_source_last;
+assign litedramcore_bankmachine7_sink_sink_payload_we = litedramcore_bankmachine7_source_payload_we;
+assign litedramcore_bankmachine7_sink_sink_payload_addr = litedramcore_bankmachine7_source_payload_addr;
+assign litedramcore_bankmachine7_source_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid);
+assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_source_valid | litedramcore_bankmachine7_source_source_valid);
+assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_source_source_payload_addr[22:7]);
assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
always @(*) begin
- litedramcore_bankmachine7_cmd_payload_a <= 16'd0;
- if (litedramcore_bankmachine7_row_col_n_addr_sel) begin
- litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[22:7];
- end else begin
- litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine7_cmd_payload_a <= 16'd0;
+ if (litedramcore_bankmachine7_row_col_n_addr_sel) begin
+ litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_source_source_payload_addr[22:7];
+ end else begin
+ litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write);
assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
always @(*) begin
- litedramcore_bankmachine7_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine7_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[22:7] != litedramcore_bankmachine7_cmd_buffer_source_payload_addr[22:7])) begin
- litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine7_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | litedramcore_bankmachine7_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re);
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine7_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine7_next_state <= 4'd0;
- litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- if (litedramcore_bankmachine7_cmd_ready) begin
- litedramcore_bankmachine7_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- if (litedramcore_bankmachine7_cmd_ready) begin
- litedramcore_bankmachine7_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine7_refresh_req)) begin
- litedramcore_bankmachine7_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine7_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine7_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine7_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine7_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- litedramcore_bankmachine7_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin
- litedramcore_bankmachine7_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine7_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine7_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine7_twtpcon_ready) begin
- litedramcore_bankmachine7_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- litedramcore_bankmachine7_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_row_open <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_row_close <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- litedramcore_bankmachine7_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine7_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine7_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
+ litedramcore_bankmachine7_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine7_source_valid & litedramcore_bankmachine7_source_source_valid)) begin
+ if ((litedramcore_bankmachine7_source_payload_addr[22:7] != litedramcore_bankmachine7_source_source_payload_addr[22:7])) begin
+ litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine7_syncfifo7_din = {litedramcore_bankmachine7_fifo_in_last, litedramcore_bankmachine7_fifo_in_first, litedramcore_bankmachine7_fifo_in_payload_addr, litedramcore_bankmachine7_fifo_in_payload_we};
+assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout;
+assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout;
+assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout;
+assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout;
+assign litedramcore_bankmachine7_sink_ready = litedramcore_bankmachine7_syncfifo7_writable;
+assign litedramcore_bankmachine7_syncfifo7_we = litedramcore_bankmachine7_sink_valid;
+assign litedramcore_bankmachine7_fifo_in_first = litedramcore_bankmachine7_sink_first;
+assign litedramcore_bankmachine7_fifo_in_last = litedramcore_bankmachine7_sink_last;
+assign litedramcore_bankmachine7_fifo_in_payload_we = litedramcore_bankmachine7_sink_payload_we;
+assign litedramcore_bankmachine7_fifo_in_payload_addr = litedramcore_bankmachine7_sink_payload_addr;
+assign litedramcore_bankmachine7_source_valid = litedramcore_bankmachine7_syncfifo7_readable;
+assign litedramcore_bankmachine7_source_first = litedramcore_bankmachine7_fifo_out_first;
+assign litedramcore_bankmachine7_source_last = litedramcore_bankmachine7_fifo_out_last;
+assign litedramcore_bankmachine7_source_payload_we = litedramcore_bankmachine7_fifo_out_payload_we;
+assign litedramcore_bankmachine7_source_payload_addr = litedramcore_bankmachine7_fifo_out_payload_addr;
+assign litedramcore_bankmachine7_syncfifo7_re = litedramcore_bankmachine7_source_ready;
+always @(*) begin
+ litedramcore_bankmachine7_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine7_replace) begin
+ litedramcore_bankmachine7_wrport_adr <= (litedramcore_bankmachine7_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine7_wrport_adr <= litedramcore_bankmachine7_produce;
+ end
+end
+assign litedramcore_bankmachine7_wrport_dat_w = litedramcore_bankmachine7_syncfifo7_din;
+assign litedramcore_bankmachine7_wrport_we = (litedramcore_bankmachine7_syncfifo7_we & (litedramcore_bankmachine7_syncfifo7_writable | litedramcore_bankmachine7_replace));
+assign litedramcore_bankmachine7_do_read = (litedramcore_bankmachine7_syncfifo7_readable & litedramcore_bankmachine7_syncfifo7_re);
+assign litedramcore_bankmachine7_rdport_adr = litedramcore_bankmachine7_consume;
+assign litedramcore_bankmachine7_syncfifo7_dout = litedramcore_bankmachine7_rdport_dat_r;
+assign litedramcore_bankmachine7_syncfifo7_writable = (litedramcore_bankmachine7_level != 5'd16);
+assign litedramcore_bankmachine7_syncfifo7_readable = (litedramcore_bankmachine7_level != 1'd0);
+assign litedramcore_bankmachine7_pipe_valid_sink_ready = ((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready);
+assign litedramcore_bankmachine7_pipe_valid_sink_valid = litedramcore_bankmachine7_sink_sink_valid;
+assign litedramcore_bankmachine7_sink_sink_ready = litedramcore_bankmachine7_pipe_valid_sink_ready;
+assign litedramcore_bankmachine7_pipe_valid_sink_first = litedramcore_bankmachine7_sink_sink_first;
+assign litedramcore_bankmachine7_pipe_valid_sink_last = litedramcore_bankmachine7_sink_sink_last;
+assign litedramcore_bankmachine7_pipe_valid_sink_payload_we = litedramcore_bankmachine7_sink_sink_payload_we;
+assign litedramcore_bankmachine7_pipe_valid_sink_payload_addr = litedramcore_bankmachine7_sink_sink_payload_addr;
+assign litedramcore_bankmachine7_source_source_valid = litedramcore_bankmachine7_pipe_valid_source_valid;
+assign litedramcore_bankmachine7_pipe_valid_source_ready = litedramcore_bankmachine7_source_source_ready;
+assign litedramcore_bankmachine7_source_source_first = litedramcore_bankmachine7_pipe_valid_source_first;
+assign litedramcore_bankmachine7_source_source_last = litedramcore_bankmachine7_pipe_valid_source_last;
+assign litedramcore_bankmachine7_source_source_payload_we = litedramcore_bankmachine7_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine7_source_source_payload_addr = litedramcore_bankmachine7_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine7_next_state <= 4'd0;
+ litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ if (litedramcore_bankmachine7_cmd_ready) begin
+ litedramcore_bankmachine7_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ if (litedramcore_bankmachine7_cmd_ready) begin
+ litedramcore_bankmachine7_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine7_refresh_req)) begin
+ litedramcore_bankmachine7_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine7_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine7_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine7_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine7_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ litedramcore_bankmachine7_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin
+ litedramcore_bankmachine7_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine7_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine7_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if (litedramcore_bankmachine7_source_source_payload_we) begin
+ litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if (litedramcore_bankmachine7_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if (litedramcore_bankmachine7_source_source_payload_we) begin
+ litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if (litedramcore_bankmachine7_source_source_payload_we) begin
+ litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if (litedramcore_bankmachine7_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine7_twtpcon_ready) begin
+ litedramcore_bankmachine7_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_row_open <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ litedramcore_bankmachine7_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_row_close <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ litedramcore_bankmachine7_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine7_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine7_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
end
assign litedramcore_rdcmdphase = (a7ddrphy_rdphase_storage - 1'd1);
assign litedramcore_wrcmdphase = (a7ddrphy_wrphase_storage - 1'd1);
assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
always @(*) begin
- litedramcore_choose_cmd_valids <= 8'd0;
- litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids <= 8'd0;
+ litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
end
assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids;
assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0;
assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4;
assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5;
always @(*) begin
- litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
- if (litedramcore_choose_cmd_cmd_valid) begin
- litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0;
- end
+ litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
+ if (litedramcore_choose_cmd_cmd_valid) begin
+ litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0;
+ end
end
always @(*) begin
- litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
- if (litedramcore_choose_cmd_cmd_valid) begin
- litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1;
- end
+ litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
+ if (litedramcore_choose_cmd_cmd_valid) begin
+ litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1;
+ end
end
always @(*) begin
- litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
- if (litedramcore_choose_cmd_cmd_valid) begin
- litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2;
- end
+ litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
+ if (litedramcore_choose_cmd_cmd_valid) begin
+ litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2;
+ end
end
always @(*) begin
- litedramcore_bankmachine0_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin
- litedramcore_bankmachine0_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin
- litedramcore_bankmachine0_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine0_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin
+ litedramcore_bankmachine0_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin
+ litedramcore_bankmachine0_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_bankmachine1_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin
- litedramcore_bankmachine1_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin
- litedramcore_bankmachine1_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine1_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin
+ litedramcore_bankmachine1_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin
+ litedramcore_bankmachine1_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_bankmachine2_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin
- litedramcore_bankmachine2_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin
- litedramcore_bankmachine2_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine2_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin
+ litedramcore_bankmachine2_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin
+ litedramcore_bankmachine2_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_bankmachine3_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin
- litedramcore_bankmachine3_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin
- litedramcore_bankmachine3_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine3_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin
+ litedramcore_bankmachine3_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin
+ litedramcore_bankmachine3_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_bankmachine4_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin
- litedramcore_bankmachine4_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin
- litedramcore_bankmachine4_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine4_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin
+ litedramcore_bankmachine4_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin
+ litedramcore_bankmachine4_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_bankmachine5_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin
- litedramcore_bankmachine5_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin
- litedramcore_bankmachine5_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine5_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin
+ litedramcore_bankmachine5_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin
+ litedramcore_bankmachine5_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_bankmachine6_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin
- litedramcore_bankmachine6_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin
- litedramcore_bankmachine6_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine6_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin
+ litedramcore_bankmachine6_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin
+ litedramcore_bankmachine6_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_bankmachine7_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin
- litedramcore_bankmachine7_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin
- litedramcore_bankmachine7_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine7_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin
+ litedramcore_bankmachine7_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin
+ litedramcore_bankmachine7_cmd_ready <= 1'd1;
+ end
end
assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid));
always @(*) begin
- litedramcore_choose_req_valids <= 8'd0;
- litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids <= 8'd0;
+ litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
end
assign litedramcore_choose_req_request = litedramcore_choose_req_valids;
assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6;
assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10;
assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11;
always @(*) begin
- litedramcore_choose_req_cmd_payload_cas <= 1'd0;
- if (litedramcore_choose_req_cmd_valid) begin
- litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3;
- end
+ litedramcore_choose_req_cmd_payload_cas <= 1'd0;
+ if (litedramcore_choose_req_cmd_valid) begin
+ litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3;
+ end
end
always @(*) begin
- litedramcore_choose_req_cmd_payload_ras <= 1'd0;
- if (litedramcore_choose_req_cmd_valid) begin
- litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4;
- end
+ litedramcore_choose_req_cmd_payload_ras <= 1'd0;
+ if (litedramcore_choose_req_cmd_valid) begin
+ litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4;
+ end
end
always @(*) begin
- litedramcore_choose_req_cmd_payload_we <= 1'd0;
- if (litedramcore_choose_req_cmd_valid) begin
- litedramcore_choose_req_cmd_payload_we <= t_array_muxed5;
- end
+ litedramcore_choose_req_cmd_payload_we <= 1'd0;
+ if (litedramcore_choose_req_cmd_valid) begin
+ litedramcore_choose_req_cmd_payload_we <= t_array_muxed5;
+ end
end
assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid));
assign litedramcore_dfi_p0_reset_n = 1'd1;
assign litedramcore_dfi_p3_odt = {1{litedramcore_steerer7}};
assign litedramcore_tfawcon_count = ((((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]) + litedramcore_tfawcon_window[3]) + litedramcore_tfawcon_window[4]);
always @(*) begin
- litedramcore_multiplexer_next_state <= 4'd0;
- litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- if (litedramcore_read_available) begin
- if (((~litedramcore_write_available) | litedramcore_max_time1)) begin
- litedramcore_multiplexer_next_state <= 2'd3;
- end
- end
- if (litedramcore_go_to_refresh) begin
- litedramcore_multiplexer_next_state <= 2'd2;
- end
- end
- 2'd2: begin
- if (litedramcore_cmd_last) begin
- litedramcore_multiplexer_next_state <= 1'd0;
- end
- end
- 2'd3: begin
- if (litedramcore_twtrcon_ready) begin
- litedramcore_multiplexer_next_state <= 1'd0;
- end
- end
- 3'd4: begin
- litedramcore_multiplexer_next_state <= 3'd5;
- end
- 3'd5: begin
- litedramcore_multiplexer_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_multiplexer_next_state <= 3'd7;
- end
- 3'd7: begin
- litedramcore_multiplexer_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_multiplexer_next_state <= 4'd9;
- end
- 4'd9: begin
- litedramcore_multiplexer_next_state <= 4'd10;
- end
- 4'd10: begin
- litedramcore_multiplexer_next_state <= 1'd1;
- end
- default: begin
- if (litedramcore_write_available) begin
- if (((~litedramcore_read_available) | litedramcore_max_time0)) begin
- litedramcore_multiplexer_next_state <= 3'd4;
- end
- end
- if (litedramcore_go_to_refresh) begin
- litedramcore_multiplexer_next_state <= 2'd2;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_steerer_sel0 <= 2'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- litedramcore_steerer_sel0 <= 1'd0;
- if ((a7ddrphy_wrphase_storage == 1'd0)) begin
- litedramcore_steerer_sel0 <= 2'd2;
- end
- if ((litedramcore_wrcmdphase == 1'd0)) begin
- litedramcore_steerer_sel0 <= 1'd1;
- end
- end
- 2'd2: begin
- litedramcore_steerer_sel0 <= 2'd3;
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- litedramcore_steerer_sel0 <= 1'd0;
- if ((a7ddrphy_rdphase_storage == 1'd0)) begin
- litedramcore_steerer_sel0 <= 2'd2;
- end
- if ((litedramcore_rdcmdphase == 1'd0)) begin
- litedramcore_steerer_sel0 <= 1'd1;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_cmd_ready <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- end
- 2'd2: begin
- litedramcore_cmd_ready <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_steerer_sel1 <= 2'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- litedramcore_steerer_sel1 <= 1'd0;
- if ((a7ddrphy_wrphase_storage == 1'd1)) begin
- litedramcore_steerer_sel1 <= 2'd2;
- end
- if ((litedramcore_wrcmdphase == 1'd1)) begin
- litedramcore_steerer_sel1 <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- litedramcore_steerer_sel1 <= 1'd0;
- if ((a7ddrphy_rdphase_storage == 1'd1)) begin
- litedramcore_steerer_sel1 <= 2'd2;
- end
- if ((litedramcore_rdcmdphase == 1'd1)) begin
- litedramcore_steerer_sel1 <= 1'd1;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_steerer_sel2 <= 2'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- litedramcore_steerer_sel2 <= 1'd0;
- if ((a7ddrphy_wrphase_storage == 2'd2)) begin
- litedramcore_steerer_sel2 <= 2'd2;
- end
- if ((litedramcore_wrcmdphase == 2'd2)) begin
- litedramcore_steerer_sel2 <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- litedramcore_steerer_sel2 <= 1'd0;
- if ((a7ddrphy_rdphase_storage == 2'd2)) begin
- litedramcore_steerer_sel2 <= 2'd2;
- end
- if ((litedramcore_rdcmdphase == 2'd2)) begin
- litedramcore_steerer_sel2 <= 1'd1;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_choose_cmd_want_activates <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_steerer_sel3 <= 2'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- litedramcore_steerer_sel3 <= 1'd0;
- if ((a7ddrphy_wrphase_storage == 2'd3)) begin
- litedramcore_steerer_sel3 <= 2'd2;
- end
- if ((litedramcore_wrcmdphase == 2'd3)) begin
- litedramcore_steerer_sel3 <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- litedramcore_steerer_sel3 <= 1'd0;
- if ((a7ddrphy_rdphase_storage == 2'd3)) begin
- litedramcore_steerer_sel3 <= 2'd2;
- end
- if ((litedramcore_rdcmdphase == 2'd3)) begin
- litedramcore_steerer_sel3 <= 1'd1;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_en0 <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- litedramcore_en0 <= 1'd1;
- end
- endcase
-end
-always @(*) begin
- litedramcore_choose_cmd_cmd_ready <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_choose_req_want_reads <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- litedramcore_choose_req_want_reads <= 1'd1;
- end
- endcase
-end
-always @(*) begin
- litedramcore_en1 <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- litedramcore_en1 <= 1'd1;
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_choose_req_want_writes <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- litedramcore_choose_req_want_writes <= 1'd1;
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_choose_req_cmd_ready <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- if (1'd0) begin
- litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
- end else begin
- litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- if (1'd0) begin
- litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
- end else begin
- litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
- end
- end
- endcase
+ litedramcore_multiplexer_next_state <= 4'd0;
+ litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ if (litedramcore_read_available) begin
+ if (((~litedramcore_write_available) | litedramcore_max_time1)) begin
+ litedramcore_multiplexer_next_state <= 2'd3;
+ end
+ end
+ if (litedramcore_go_to_refresh) begin
+ litedramcore_multiplexer_next_state <= 2'd2;
+ end
+ end
+ 2'd2: begin
+ if (litedramcore_cmd_last) begin
+ litedramcore_multiplexer_next_state <= 1'd0;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_twtrcon_ready) begin
+ litedramcore_multiplexer_next_state <= 1'd0;
+ end
+ end
+ 3'd4: begin
+ litedramcore_multiplexer_next_state <= 3'd5;
+ end
+ 3'd5: begin
+ litedramcore_multiplexer_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_multiplexer_next_state <= 3'd7;
+ end
+ 3'd7: begin
+ litedramcore_multiplexer_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_multiplexer_next_state <= 4'd9;
+ end
+ 4'd9: begin
+ litedramcore_multiplexer_next_state <= 4'd10;
+ end
+ 4'd10: begin
+ litedramcore_multiplexer_next_state <= 1'd1;
+ end
+ default: begin
+ if (litedramcore_write_available) begin
+ if (((~litedramcore_read_available) | litedramcore_max_time0)) begin
+ litedramcore_multiplexer_next_state <= 3'd4;
+ end
+ end
+ if (litedramcore_go_to_refresh) begin
+ litedramcore_multiplexer_next_state <= 2'd2;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_steerer_sel0 <= 2'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ litedramcore_steerer_sel0 <= 1'd0;
+ if ((a7ddrphy_wrphase_storage == 1'd0)) begin
+ litedramcore_steerer_sel0 <= 2'd2;
+ end
+ if ((litedramcore_wrcmdphase == 1'd0)) begin
+ litedramcore_steerer_sel0 <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ litedramcore_steerer_sel0 <= 2'd3;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ litedramcore_steerer_sel0 <= 1'd0;
+ if ((a7ddrphy_rdphase_storage == 1'd0)) begin
+ litedramcore_steerer_sel0 <= 2'd2;
+ end
+ if ((litedramcore_rdcmdphase == 1'd0)) begin
+ litedramcore_steerer_sel0 <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_cmd_ready <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ litedramcore_cmd_ready <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_steerer_sel1 <= 2'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ litedramcore_steerer_sel1 <= 1'd0;
+ if ((a7ddrphy_wrphase_storage == 1'd1)) begin
+ litedramcore_steerer_sel1 <= 2'd2;
+ end
+ if ((litedramcore_wrcmdphase == 1'd1)) begin
+ litedramcore_steerer_sel1 <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ litedramcore_steerer_sel1 <= 1'd0;
+ if ((a7ddrphy_rdphase_storage == 1'd1)) begin
+ litedramcore_steerer_sel1 <= 2'd2;
+ end
+ if ((litedramcore_rdcmdphase == 1'd1)) begin
+ litedramcore_steerer_sel1 <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_steerer_sel2 <= 2'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ litedramcore_steerer_sel2 <= 1'd0;
+ if ((a7ddrphy_wrphase_storage == 2'd2)) begin
+ litedramcore_steerer_sel2 <= 2'd2;
+ end
+ if ((litedramcore_wrcmdphase == 2'd2)) begin
+ litedramcore_steerer_sel2 <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ litedramcore_steerer_sel2 <= 1'd0;
+ if ((a7ddrphy_rdphase_storage == 2'd2)) begin
+ litedramcore_steerer_sel2 <= 2'd2;
+ end
+ if ((litedramcore_rdcmdphase == 2'd2)) begin
+ litedramcore_steerer_sel2 <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_choose_cmd_want_activates <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ if (1'd0) begin
+ end else begin
+ litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ if (1'd0) begin
+ end else begin
+ litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_steerer_sel3 <= 2'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ litedramcore_steerer_sel3 <= 1'd0;
+ if ((a7ddrphy_wrphase_storage == 2'd3)) begin
+ litedramcore_steerer_sel3 <= 2'd2;
+ end
+ if ((litedramcore_wrcmdphase == 2'd3)) begin
+ litedramcore_steerer_sel3 <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ litedramcore_steerer_sel3 <= 1'd0;
+ if ((a7ddrphy_rdphase_storage == 2'd3)) begin
+ litedramcore_steerer_sel3 <= 2'd2;
+ end
+ if ((litedramcore_rdcmdphase == 2'd3)) begin
+ litedramcore_steerer_sel3 <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_en0 <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ litedramcore_en0 <= 1'd1;
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_choose_cmd_cmd_ready <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ if (1'd0) begin
+ end else begin
+ litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ if (1'd0) begin
+ end else begin
+ litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_choose_req_want_reads <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ litedramcore_choose_req_want_reads <= 1'd1;
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_choose_req_want_writes <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ litedramcore_choose_req_want_writes <= 1'd1;
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_en1 <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ litedramcore_en1 <= 1'd1;
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_choose_req_cmd_ready <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ if (1'd0) begin
+ litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+ end else begin
+ litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ if (1'd0) begin
+ litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+ end else begin
+ litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+ end
+ end
+ endcase
end
assign litedramcore_roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
assign litedramcore_roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock));
assign user_port_wdata_ready = litedramcore_new_master_wdata_ready1;
assign user_port_rdata_valid = litedramcore_new_master_rdata_valid8;
always @(*) begin
- litedramcore_interface_wdata <= 128'd0;
- case ({litedramcore_new_master_wdata_ready1})
- 1'd1: begin
- litedramcore_interface_wdata <= user_port_wdata_payload_data;
- end
- default: begin
- litedramcore_interface_wdata <= 1'd0;
- end
- endcase
-end
-always @(*) begin
- litedramcore_interface_wdata_we <= 16'd0;
- case ({litedramcore_new_master_wdata_ready1})
- 1'd1: begin
- litedramcore_interface_wdata_we <= user_port_wdata_payload_we;
- end
- default: begin
- litedramcore_interface_wdata_we <= 1'd0;
- end
- endcase
+ litedramcore_interface_wdata <= 128'd0;
+ case ({litedramcore_new_master_wdata_ready1})
+ 1'd1: begin
+ litedramcore_interface_wdata <= user_port_wdata_payload_data;
+ end
+ default: begin
+ litedramcore_interface_wdata <= 1'd0;
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_interface_wdata_we <= 16'd0;
+ case ({litedramcore_new_master_wdata_ready1})
+ 1'd1: begin
+ litedramcore_interface_wdata_we <= user_port_wdata_payload_we;
+ end
+ default: begin
+ litedramcore_interface_wdata_we <= 1'd0;
+ end
+ endcase
end
assign user_port_rdata_payload_data = litedramcore_interface_rdata;
assign litedramcore_roundrobin0_grant = 1'd0;
assign litedramcore_roundrobin6_grant = 1'd0;
assign litedramcore_roundrobin7_grant = 1'd0;
always @(*) begin
- litedramcore_next_state <= 2'd0;
- litedramcore_next_state <= litedramcore_state;
- case (litedramcore_state)
- 1'd1: begin
- litedramcore_next_state <= 2'd2;
- end
- 2'd2: begin
- litedramcore_next_state <= 1'd0;
- end
- default: begin
- if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_next_state <= 1'd1;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_adr_next_value1 <= 14'd0;
- case (litedramcore_state)
- 1'd1: begin
- litedramcore_adr_next_value1 <= 1'd0;
- end
- 2'd2: begin
- end
- default: begin
- if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_adr_next_value1 <= litedramcore_wishbone_adr;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_adr_next_value_ce1 <= 1'd0;
- case (litedramcore_state)
- 1'd1: begin
- litedramcore_adr_next_value_ce1 <= 1'd1;
- end
- 2'd2: begin
- end
- default: begin
- if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_adr_next_value_ce1 <= 1'd1;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_wishbone_dat_r <= 32'd0;
- case (litedramcore_state)
- 1'd1: begin
- end
- 2'd2: begin
- litedramcore_wishbone_dat_r <= litedramcore_dat_r;
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_we_next_value2 <= 1'd0;
- case (litedramcore_state)
- 1'd1: begin
- litedramcore_we_next_value2 <= 1'd0;
- end
- 2'd2: begin
- end
- default: begin
- if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_we_next_value_ce2 <= 1'd0;
- case (litedramcore_state)
- 1'd1: begin
- litedramcore_we_next_value_ce2 <= 1'd1;
- end
- 2'd2: begin
- end
- default: begin
- if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_we_next_value_ce2 <= 1'd1;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_wishbone_ack <= 1'd0;
- case (litedramcore_state)
- 1'd1: begin
- end
- 2'd2: begin
- litedramcore_wishbone_ack <= 1'd1;
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_dat_w_next_value0 <= 32'd0;
- case (litedramcore_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- default: begin
- litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w;
- end
- endcase
-end
-always @(*) begin
- litedramcore_dat_w_next_value_ce0 <= 1'd0;
- case (litedramcore_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- default: begin
- litedramcore_dat_w_next_value_ce0 <= 1'd1;
- end
- endcase
+ litedramcore_next_state <= 2'd0;
+ litedramcore_next_state <= litedramcore_state;
+ case (litedramcore_state)
+ 1'd1: begin
+ litedramcore_next_state <= 2'd2;
+ end
+ 2'd2: begin
+ litedramcore_next_state <= 1'd0;
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_next_state <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_adr_next_value1 <= 14'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ litedramcore_adr_next_value1 <= 1'd0;
+ end
+ 2'd2: begin
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_adr_next_value1 <= litedramcore_wishbone_adr;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_adr_next_value_ce1 <= 1'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ litedramcore_adr_next_value_ce1 <= 1'd1;
+ end
+ 2'd2: begin
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_adr_next_value_ce1 <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_wishbone_dat_r <= 32'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ litedramcore_wishbone_dat_r <= litedramcore_dat_r;
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_we_next_value2 <= 1'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ litedramcore_we_next_value2 <= 1'd0;
+ end
+ 2'd2: begin
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_we_next_value_ce2 <= 1'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ litedramcore_we_next_value_ce2 <= 1'd1;
+ end
+ 2'd2: begin
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_we_next_value_ce2 <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_wishbone_ack <= 1'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ litedramcore_wishbone_ack <= 1'd1;
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_dat_w_next_value0 <= 32'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ default: begin
+ litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w;
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_dat_w_next_value_ce0 <= 1'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ default: begin
+ litedramcore_dat_w_next_value_ce0 <= 1'd1;
+ end
+ endcase
end
assign litedramcore_wishbone_adr = wb_bus_adr;
assign litedramcore_wishbone_dat_w = wb_bus_dat_w;
assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0);
assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
always @(*) begin
- csrbank0_init_done0_we <= 1'd0;
- if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
- csrbank0_init_done0_we <= (~interface0_bank_bus_we);
- end
+ csrbank0_init_done0_we <= 1'd0;
+ if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank0_init_done0_we <= (~interface0_bank_bus_we);
+ end
end
always @(*) begin
- csrbank0_init_done0_re <= 1'd0;
- if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
- csrbank0_init_done0_re <= interface0_bank_bus_we;
- end
+ csrbank0_init_done0_re <= 1'd0;
+ if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank0_init_done0_re <= interface0_bank_bus_we;
+ end
end
assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0];
always @(*) begin
- csrbank0_init_error0_we <= 1'd0;
- if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
- csrbank0_init_error0_we <= (~interface0_bank_bus_we);
- end
+ csrbank0_init_error0_we <= 1'd0;
+ if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
+ csrbank0_init_error0_we <= (~interface0_bank_bus_we);
+ end
end
always @(*) begin
- csrbank0_init_error0_re <= 1'd0;
- if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
- csrbank0_init_error0_re <= interface0_bank_bus_we;
- end
+ csrbank0_init_error0_re <= 1'd0;
+ if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
+ csrbank0_init_error0_re <= interface0_bank_bus_we;
+ end
end
assign csrbank0_init_done0_w = init_done_storage;
assign csrbank0_init_error0_w = init_error_storage;
assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1);
assign csrbank1_rst0_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- csrbank1_rst0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
- csrbank1_rst0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_rst0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank1_rst0_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- csrbank1_rst0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
- csrbank1_rst0_re <= interface1_bank_bus_we;
- end
+ csrbank1_rst0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank1_rst0_re <= interface1_bank_bus_we;
+ end
end
assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0];
always @(*) begin
- csrbank1_dly_sel0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
- csrbank1_dly_sel0_re <= interface1_bank_bus_we;
- end
+ csrbank1_dly_sel0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
+ csrbank1_dly_sel0_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- csrbank1_dly_sel0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
- csrbank1_dly_sel0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_dly_sel0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
+ csrbank1_dly_sel0_we <= (~interface1_bank_bus_we);
+ end
end
assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0];
always @(*) begin
- csrbank1_half_sys8x_taps0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
- csrbank1_half_sys8x_taps0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_half_sys8x_taps0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
+ csrbank1_half_sys8x_taps0_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- csrbank1_half_sys8x_taps0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
- csrbank1_half_sys8x_taps0_re <= interface1_bank_bus_we;
- end
+ csrbank1_half_sys8x_taps0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
+ csrbank1_half_sys8x_taps0_re <= interface1_bank_bus_we;
+ end
end
assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- csrbank1_wlevel_en0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
- csrbank1_wlevel_en0_re <= interface1_bank_bus_we;
- end
+ csrbank1_wlevel_en0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
+ csrbank1_wlevel_en0_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- csrbank1_wlevel_en0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
- csrbank1_wlevel_en0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_wlevel_en0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
+ csrbank1_wlevel_en0_we <= (~interface1_bank_bus_we);
+ end
end
assign a7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- a7ddrphy_wlevel_strobe_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
- a7ddrphy_wlevel_strobe_re <= interface1_bank_bus_we;
- end
+ a7ddrphy_wlevel_strobe_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
+ a7ddrphy_wlevel_strobe_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- a7ddrphy_wlevel_strobe_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
- a7ddrphy_wlevel_strobe_we <= (~interface1_bank_bus_we);
- end
+ a7ddrphy_wlevel_strobe_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
+ a7ddrphy_wlevel_strobe_we <= (~interface1_bank_bus_we);
+ end
end
assign a7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- a7ddrphy_rdly_dq_rst_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
- a7ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we;
- end
+ a7ddrphy_rdly_dq_rst_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
+ a7ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- a7ddrphy_rdly_dq_rst_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
- a7ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we);
- end
+ a7ddrphy_rdly_dq_rst_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
+ a7ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we);
+ end
end
assign a7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- a7ddrphy_rdly_dq_inc_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
- a7ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we;
- end
+ a7ddrphy_rdly_dq_inc_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
+ a7ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- a7ddrphy_rdly_dq_inc_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
- a7ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we);
- end
+ a7ddrphy_rdly_dq_inc_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
+ a7ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we);
+ end
end
assign a7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
- a7ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
- end
+ a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
+ a7ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
- a7ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
- end
+ a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
+ a7ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
+ end
end
assign a7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- a7ddrphy_rdly_dq_bitslip_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
- a7ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we);
- end
+ a7ddrphy_rdly_dq_bitslip_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
+ a7ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- a7ddrphy_rdly_dq_bitslip_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
- a7ddrphy_rdly_dq_bitslip_re <= interface1_bank_bus_we;
- end
+ a7ddrphy_rdly_dq_bitslip_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
+ a7ddrphy_rdly_dq_bitslip_re <= interface1_bank_bus_we;
+ end
end
assign a7ddrphy_wdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
- a7ddrphy_wdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
- end
+ a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
+ a7ddrphy_wdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
- a7ddrphy_wdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
- end
+ a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
+ a7ddrphy_wdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
+ end
end
assign a7ddrphy_wdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- a7ddrphy_wdly_dq_bitslip_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
- a7ddrphy_wdly_dq_bitslip_we <= (~interface1_bank_bus_we);
- end
+ a7ddrphy_wdly_dq_bitslip_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
+ a7ddrphy_wdly_dq_bitslip_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- a7ddrphy_wdly_dq_bitslip_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
- a7ddrphy_wdly_dq_bitslip_re <= interface1_bank_bus_we;
- end
+ a7ddrphy_wdly_dq_bitslip_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
+ a7ddrphy_wdly_dq_bitslip_re <= interface1_bank_bus_we;
+ end
end
assign csrbank1_rdphase0_r = interface1_bank_bus_dat_w[1:0];
always @(*) begin
- csrbank1_rdphase0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
- csrbank1_rdphase0_re <= interface1_bank_bus_we;
- end
+ csrbank1_rdphase0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
+ csrbank1_rdphase0_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- csrbank1_rdphase0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
- csrbank1_rdphase0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_rdphase0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
+ csrbank1_rdphase0_we <= (~interface1_bank_bus_we);
+ end
end
assign csrbank1_wrphase0_r = interface1_bank_bus_dat_w[1:0];
always @(*) begin
- csrbank1_wrphase0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
- csrbank1_wrphase0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_wrphase0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
+ csrbank1_wrphase0_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- csrbank1_wrphase0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
- csrbank1_wrphase0_re <= interface1_bank_bus_we;
- end
+ csrbank1_wrphase0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
+ csrbank1_wrphase0_re <= interface1_bank_bus_we;
+ end
end
assign csrbank1_rst0_w = a7ddrphy_rst_storage;
assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0];
assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2);
assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0];
always @(*) begin
- csrbank2_dfii_control0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
- csrbank2_dfii_control0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_control0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank2_dfii_control0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_control0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
- csrbank2_dfii_control0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_control0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank2_dfii_control0_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0];
always @(*) begin
- csrbank2_dfii_pi0_command0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
- csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi0_command0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
+ csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi0_command0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
- csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi0_command0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
+ csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we;
+ end
end
assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0];
always @(*) begin
- litedramcore_phaseinjector0_command_issue_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
- litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we);
- end
+ litedramcore_phaseinjector0_command_issue_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
+ litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- litedramcore_phaseinjector0_command_issue_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
- litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we;
- end
+ litedramcore_phaseinjector0_command_issue_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
+ litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[15:0];
always @(*) begin
- csrbank2_dfii_pi0_address0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
- csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi0_address0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
+ csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi0_address0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
- csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi0_address0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
+ csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0];
always @(*) begin
- csrbank2_dfii_pi0_baddress0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
- csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi0_baddress0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
+ csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi0_baddress0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
- csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi0_baddress0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
+ csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
- csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
+ csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
- csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
+ csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi0_rddata_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi0_rddata_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
- csrbank2_dfii_pi0_rddata_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi0_rddata_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
+ csrbank2_dfii_pi0_rddata_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi0_rddata_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
- csrbank2_dfii_pi0_rddata_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi0_rddata_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
+ csrbank2_dfii_pi0_rddata_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0];
always @(*) begin
- csrbank2_dfii_pi1_command0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
- csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi1_command0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
+ csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi1_command0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
- csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi1_command0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
+ csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we;
+ end
end
assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0];
always @(*) begin
- litedramcore_phaseinjector1_command_issue_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
- litedramcore_phaseinjector1_command_issue_re <= interface2_bank_bus_we;
- end
+ litedramcore_phaseinjector1_command_issue_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
+ litedramcore_phaseinjector1_command_issue_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- litedramcore_phaseinjector1_command_issue_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
- litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we);
- end
+ litedramcore_phaseinjector1_command_issue_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
+ litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[15:0];
always @(*) begin
- csrbank2_dfii_pi1_address0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
- csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi1_address0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
+ csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi1_address0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
- csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi1_address0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
+ csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0];
always @(*) begin
- csrbank2_dfii_pi1_baddress0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
- csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi1_baddress0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
+ csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi1_baddress0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
- csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi1_baddress0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
+ csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
- csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
+ csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
- csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
+ csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi1_rddata_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi1_rddata_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
- csrbank2_dfii_pi1_rddata_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi1_rddata_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
+ csrbank2_dfii_pi1_rddata_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi1_rddata_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
- csrbank2_dfii_pi1_rddata_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi1_rddata_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
+ csrbank2_dfii_pi1_rddata_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0];
always @(*) begin
- csrbank2_dfii_pi2_command0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
- csrbank2_dfii_pi2_command0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi2_command0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
+ csrbank2_dfii_pi2_command0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi2_command0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
- csrbank2_dfii_pi2_command0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi2_command0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
+ csrbank2_dfii_pi2_command0_we <= (~interface2_bank_bus_we);
+ end
end
assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0];
always @(*) begin
- litedramcore_phaseinjector2_command_issue_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
- litedramcore_phaseinjector2_command_issue_we <= (~interface2_bank_bus_we);
- end
+ litedramcore_phaseinjector2_command_issue_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
+ litedramcore_phaseinjector2_command_issue_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- litedramcore_phaseinjector2_command_issue_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
- litedramcore_phaseinjector2_command_issue_re <= interface2_bank_bus_we;
- end
+ litedramcore_phaseinjector2_command_issue_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
+ litedramcore_phaseinjector2_command_issue_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[15:0];
always @(*) begin
- csrbank2_dfii_pi2_address0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
- csrbank2_dfii_pi2_address0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi2_address0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
+ csrbank2_dfii_pi2_address0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi2_address0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
- csrbank2_dfii_pi2_address0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi2_address0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
+ csrbank2_dfii_pi2_address0_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0];
always @(*) begin
- csrbank2_dfii_pi2_baddress0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
- csrbank2_dfii_pi2_baddress0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi2_baddress0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
+ csrbank2_dfii_pi2_baddress0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi2_baddress0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
- csrbank2_dfii_pi2_baddress0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi2_baddress0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
+ csrbank2_dfii_pi2_baddress0_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
- csrbank2_dfii_pi2_wrdata0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
+ csrbank2_dfii_pi2_wrdata0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
- csrbank2_dfii_pi2_wrdata0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
+ csrbank2_dfii_pi2_wrdata0_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi2_rddata_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi2_rddata_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
- csrbank2_dfii_pi2_rddata_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi2_rddata_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
+ csrbank2_dfii_pi2_rddata_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi2_rddata_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
- csrbank2_dfii_pi2_rddata_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi2_rddata_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
+ csrbank2_dfii_pi2_rddata_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0];
always @(*) begin
- csrbank2_dfii_pi3_command0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin
- csrbank2_dfii_pi3_command0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi3_command0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin
+ csrbank2_dfii_pi3_command0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi3_command0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin
- csrbank2_dfii_pi3_command0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi3_command0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin
+ csrbank2_dfii_pi3_command0_we <= (~interface2_bank_bus_we);
+ end
end
assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0];
always @(*) begin
- litedramcore_phaseinjector3_command_issue_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin
- litedramcore_phaseinjector3_command_issue_re <= interface2_bank_bus_we;
- end
+ litedramcore_phaseinjector3_command_issue_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin
+ litedramcore_phaseinjector3_command_issue_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- litedramcore_phaseinjector3_command_issue_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin
- litedramcore_phaseinjector3_command_issue_we <= (~interface2_bank_bus_we);
- end
+ litedramcore_phaseinjector3_command_issue_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin
+ litedramcore_phaseinjector3_command_issue_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[15:0];
always @(*) begin
- csrbank2_dfii_pi3_address0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin
- csrbank2_dfii_pi3_address0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi3_address0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin
+ csrbank2_dfii_pi3_address0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi3_address0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin
- csrbank2_dfii_pi3_address0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi3_address0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin
+ csrbank2_dfii_pi3_address0_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0];
always @(*) begin
- csrbank2_dfii_pi3_baddress0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin
- csrbank2_dfii_pi3_baddress0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi3_baddress0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin
+ csrbank2_dfii_pi3_baddress0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi3_baddress0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin
- csrbank2_dfii_pi3_baddress0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi3_baddress0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin
+ csrbank2_dfii_pi3_baddress0_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi3_wrdata0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin
- csrbank2_dfii_pi3_wrdata0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi3_wrdata0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin
+ csrbank2_dfii_pi3_wrdata0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin
- csrbank2_dfii_pi3_wrdata0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin
+ csrbank2_dfii_pi3_wrdata0_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi3_rddata_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi3_rddata_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin
- csrbank2_dfii_pi3_rddata_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi3_rddata_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin
+ csrbank2_dfii_pi3_rddata_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi3_rddata_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin
- csrbank2_dfii_pi3_rddata_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi3_rddata_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin
+ csrbank2_dfii_pi3_rddata_re <= interface2_bank_bus_we;
+ end
end
assign litedramcore_sel = litedramcore_storage[0];
assign litedramcore_cke = litedramcore_storage[1];
assign interface2_bank_bus_dat_w = csr_interconnect_dat_w;
assign csr_interconnect_dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r);
always @(*) begin
- rhs_array_muxed0 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0];
- end
- 1'd1: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1];
- end
- 2'd2: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2];
- end
- 2'd3: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3];
- end
- 3'd4: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4];
- end
- 3'd5: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5];
- end
- 3'd6: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6];
- end
- default: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7];
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed1 <= 16'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a;
- end
- 1'd1: begin
- rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a;
- end
- 2'd2: begin
- rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a;
- end
- 2'd3: begin
- rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a;
- end
- 3'd4: begin
- rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a;
- end
- 3'd5: begin
- rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a;
- end
- 3'd6: begin
- rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a;
- end
- default: begin
- rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed2 <= 3'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba;
- end
- 1'd1: begin
- rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba;
- end
- 2'd2: begin
- rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba;
- end
- 2'd3: begin
- rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba;
- end
- 3'd4: begin
- rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba;
- end
- 3'd5: begin
- rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba;
- end
- 3'd6: begin
- rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba;
- end
- default: begin
- rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed3 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read;
- end
- 1'd1: begin
- rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read;
- end
- 2'd2: begin
- rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read;
- end
- 2'd3: begin
- rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read;
- end
- 3'd4: begin
- rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read;
- end
- 3'd5: begin
- rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read;
- end
- 3'd6: begin
- rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read;
- end
- default: begin
- rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed4 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write;
- end
- 1'd1: begin
- rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write;
- end
- 2'd2: begin
- rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write;
- end
- 2'd3: begin
- rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write;
- end
- 3'd4: begin
- rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write;
- end
- 3'd5: begin
- rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write;
- end
- 3'd6: begin
- rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write;
- end
- default: begin
- rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed5 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
- end
- 1'd1: begin
- rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
- end
- 2'd2: begin
- rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
- end
- 2'd3: begin
- rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
- end
- 3'd4: begin
- rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
- end
- 3'd5: begin
- rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
- end
- 3'd6: begin
- rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
- end
- default: begin
- rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
- end
- endcase
-end
-always @(*) begin
- t_array_muxed0 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas;
- end
- 1'd1: begin
- t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas;
- end
- 2'd2: begin
- t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas;
- end
- 2'd3: begin
- t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas;
- end
- 3'd4: begin
- t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas;
- end
- 3'd5: begin
- t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas;
- end
- 3'd6: begin
- t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas;
- end
- default: begin
- t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas;
- end
- endcase
-end
-always @(*) begin
- t_array_muxed1 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras;
- end
- 1'd1: begin
- t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras;
- end
- 2'd2: begin
- t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras;
- end
- 2'd3: begin
- t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras;
- end
- 3'd4: begin
- t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras;
- end
- 3'd5: begin
- t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras;
- end
- 3'd6: begin
- t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras;
- end
- default: begin
- t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras;
- end
- endcase
-end
-always @(*) begin
- t_array_muxed2 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we;
- end
- 1'd1: begin
- t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we;
- end
- 2'd2: begin
- t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we;
- end
- 2'd3: begin
- t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we;
- end
- 3'd4: begin
- t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we;
- end
- 3'd5: begin
- t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we;
- end
- 3'd6: begin
- t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we;
- end
- default: begin
- t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed6 <= 1'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[0];
- end
- 1'd1: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[1];
- end
- 2'd2: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[2];
- end
- 2'd3: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[3];
- end
- 3'd4: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[4];
- end
- 3'd5: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[5];
- end
- 3'd6: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[6];
- end
- default: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[7];
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed7 <= 16'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a;
- end
- 1'd1: begin
- rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a;
- end
- 2'd2: begin
- rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a;
- end
- 2'd3: begin
- rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a;
- end
- 3'd4: begin
- rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a;
- end
- 3'd5: begin
- rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a;
- end
- 3'd6: begin
- rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a;
- end
- default: begin
- rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed8 <= 3'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba;
- end
- 1'd1: begin
- rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba;
- end
- 2'd2: begin
- rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba;
- end
- 2'd3: begin
- rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba;
- end
- 3'd4: begin
- rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba;
- end
- 3'd5: begin
- rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba;
- end
- 3'd6: begin
- rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba;
- end
- default: begin
- rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed9 <= 1'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read;
- end
- 1'd1: begin
- rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read;
- end
- 2'd2: begin
- rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read;
- end
- 2'd3: begin
- rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read;
- end
- 3'd4: begin
- rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read;
- end
- 3'd5: begin
- rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read;
- end
- 3'd6: begin
- rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read;
- end
- default: begin
- rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed10 <= 1'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write;
- end
- 1'd1: begin
- rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write;
- end
- 2'd2: begin
- rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write;
- end
- 2'd3: begin
- rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write;
- end
- 3'd4: begin
- rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write;
- end
- 3'd5: begin
- rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write;
- end
- 3'd6: begin
- rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write;
- end
- default: begin
- rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed11 <= 1'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
- end
- 1'd1: begin
- rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
- end
- 2'd2: begin
- rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
- end
- 2'd3: begin
- rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
- end
- 3'd4: begin
- rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
- end
- 3'd5: begin
- rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
- end
- 3'd6: begin
- rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
- end
- default: begin
- rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
- end
- endcase
-end
-always @(*) begin
- t_array_muxed3 <= 1'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas;
- end
- 1'd1: begin
- t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas;
- end
- 2'd2: begin
- t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas;
- end
- 2'd3: begin
- t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas;
- end
- 3'd4: begin
- t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas;
- end
- 3'd5: begin
- t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas;
- end
- 3'd6: begin
- t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas;
- end
- default: begin
- t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas;
- end
- endcase
-end
-always @(*) begin
- t_array_muxed4 <= 1'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras;
- end
- 1'd1: begin
- t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras;
- end
- 2'd2: begin
- t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras;
- end
- 2'd3: begin
- t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras;
- end
- 3'd4: begin
- t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras;
- end
- 3'd5: begin
- t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras;
- end
- 3'd6: begin
- t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras;
- end
- default: begin
- t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras;
- end
- endcase
-end
-always @(*) begin
- t_array_muxed5 <= 1'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we;
- end
- 1'd1: begin
- t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we;
- end
- 2'd2: begin
- t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we;
- end
- 2'd3: begin
- t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we;
- end
- 3'd4: begin
- t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we;
- end
- 3'd5: begin
- t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we;
- end
- 3'd6: begin
- t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we;
- end
- default: begin
- t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed12 <= 23'd0;
- case (litedramcore_roundrobin0_grant)
- default: begin
- rhs_array_muxed12 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed13 <= 1'd0;
- case (litedramcore_roundrobin0_grant)
- default: begin
- rhs_array_muxed13 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed14 <= 1'd0;
- case (litedramcore_roundrobin0_grant)
- default: begin
- rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed15 <= 23'd0;
- case (litedramcore_roundrobin1_grant)
- default: begin
- rhs_array_muxed15 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed16 <= 1'd0;
- case (litedramcore_roundrobin1_grant)
- default: begin
- rhs_array_muxed16 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed17 <= 1'd0;
- case (litedramcore_roundrobin1_grant)
- default: begin
- rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed18 <= 23'd0;
- case (litedramcore_roundrobin2_grant)
- default: begin
- rhs_array_muxed18 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed19 <= 1'd0;
- case (litedramcore_roundrobin2_grant)
- default: begin
- rhs_array_muxed19 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed20 <= 1'd0;
- case (litedramcore_roundrobin2_grant)
- default: begin
- rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed21 <= 23'd0;
- case (litedramcore_roundrobin3_grant)
- default: begin
- rhs_array_muxed21 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed22 <= 1'd0;
- case (litedramcore_roundrobin3_grant)
- default: begin
- rhs_array_muxed22 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed23 <= 1'd0;
- case (litedramcore_roundrobin3_grant)
- default: begin
- rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
+ rhs_array_muxed0 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0];
+ end
+ 1'd1: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1];
+ end
+ 2'd2: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2];
+ end
+ 2'd3: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3];
+ end
+ 3'd4: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4];
+ end
+ 3'd5: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5];
+ end
+ 3'd6: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6];
+ end
+ default: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7];
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed1 <= 16'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a;
+ end
+ 1'd1: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a;
+ end
+ 2'd2: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a;
+ end
+ 2'd3: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a;
+ end
+ 3'd4: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a;
+ end
+ 3'd5: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a;
+ end
+ 3'd6: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a;
+ end
+ default: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed2 <= 3'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba;
+ end
+ 1'd1: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba;
+ end
+ 2'd2: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba;
+ end
+ 2'd3: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba;
+ end
+ 3'd4: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba;
+ end
+ 3'd5: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba;
+ end
+ 3'd6: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba;
+ end
+ default: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed3 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read;
+ end
+ 1'd1: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read;
+ end
+ 2'd2: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read;
+ end
+ 2'd3: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read;
+ end
+ 3'd4: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read;
+ end
+ 3'd5: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read;
+ end
+ 3'd6: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read;
+ end
+ default: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed4 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write;
+ end
+ 1'd1: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write;
+ end
+ 2'd2: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write;
+ end
+ 2'd3: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write;
+ end
+ 3'd4: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write;
+ end
+ 3'd5: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write;
+ end
+ 3'd6: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write;
+ end
+ default: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed5 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
+ end
+ 1'd1: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
+ end
+ 2'd2: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
+ end
+ 2'd3: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
+ end
+ 3'd4: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
+ end
+ 3'd5: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
+ end
+ 3'd6: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
+ end
+ default: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed0 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas;
+ end
+ 1'd1: begin
+ t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas;
+ end
+ 2'd2: begin
+ t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas;
+ end
+ 2'd3: begin
+ t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas;
+ end
+ 3'd4: begin
+ t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas;
+ end
+ 3'd5: begin
+ t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas;
+ end
+ 3'd6: begin
+ t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas;
+ end
+ default: begin
+ t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed1 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras;
+ end
+ 1'd1: begin
+ t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras;
+ end
+ 2'd2: begin
+ t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras;
+ end
+ 2'd3: begin
+ t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras;
+ end
+ 3'd4: begin
+ t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras;
+ end
+ 3'd5: begin
+ t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras;
+ end
+ 3'd6: begin
+ t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras;
+ end
+ default: begin
+ t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed2 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we;
+ end
+ 1'd1: begin
+ t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we;
+ end
+ 2'd2: begin
+ t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we;
+ end
+ 2'd3: begin
+ t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we;
+ end
+ 3'd4: begin
+ t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we;
+ end
+ 3'd5: begin
+ t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we;
+ end
+ 3'd6: begin
+ t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we;
+ end
+ default: begin
+ t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed6 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[0];
+ end
+ 1'd1: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[1];
+ end
+ 2'd2: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[2];
+ end
+ 2'd3: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[3];
+ end
+ 3'd4: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[4];
+ end
+ 3'd5: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[5];
+ end
+ 3'd6: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[6];
+ end
+ default: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[7];
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed7 <= 16'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a;
+ end
+ 1'd1: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a;
+ end
+ 2'd2: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a;
+ end
+ 2'd3: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a;
+ end
+ 3'd4: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a;
+ end
+ 3'd5: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a;
+ end
+ 3'd6: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a;
+ end
+ default: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed8 <= 3'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba;
+ end
+ 1'd1: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba;
+ end
+ 2'd2: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba;
+ end
+ 2'd3: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba;
+ end
+ 3'd4: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba;
+ end
+ 3'd5: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba;
+ end
+ 3'd6: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba;
+ end
+ default: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed9 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read;
+ end
+ 1'd1: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read;
+ end
+ 2'd2: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read;
+ end
+ 2'd3: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read;
+ end
+ 3'd4: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read;
+ end
+ 3'd5: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read;
+ end
+ 3'd6: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read;
+ end
+ default: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed10 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write;
+ end
+ 1'd1: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write;
+ end
+ 2'd2: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write;
+ end
+ 2'd3: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write;
+ end
+ 3'd4: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write;
+ end
+ 3'd5: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write;
+ end
+ 3'd6: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write;
+ end
+ default: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed11 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
+ end
+ 1'd1: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
+ end
+ 2'd2: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
+ end
+ 2'd3: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
+ end
+ 3'd4: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
+ end
+ 3'd5: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
+ end
+ 3'd6: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
+ end
+ default: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed3 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas;
+ end
+ 1'd1: begin
+ t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas;
+ end
+ 2'd2: begin
+ t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas;
+ end
+ 2'd3: begin
+ t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas;
+ end
+ 3'd4: begin
+ t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas;
+ end
+ 3'd5: begin
+ t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas;
+ end
+ 3'd6: begin
+ t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas;
+ end
+ default: begin
+ t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed4 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras;
+ end
+ 1'd1: begin
+ t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras;
+ end
+ 2'd2: begin
+ t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras;
+ end
+ 2'd3: begin
+ t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras;
+ end
+ 3'd4: begin
+ t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras;
+ end
+ 3'd5: begin
+ t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras;
+ end
+ 3'd6: begin
+ t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras;
+ end
+ default: begin
+ t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed5 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we;
+ end
+ 1'd1: begin
+ t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we;
+ end
+ 2'd2: begin
+ t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we;
+ end
+ 2'd3: begin
+ t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we;
+ end
+ 3'd4: begin
+ t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we;
+ end
+ 3'd5: begin
+ t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we;
+ end
+ 3'd6: begin
+ t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we;
+ end
+ default: begin
+ t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed12 <= 23'd0;
+ case (litedramcore_roundrobin0_grant)
+ default: begin
+ rhs_array_muxed12 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed13 <= 1'd0;
+ case (litedramcore_roundrobin0_grant)
+ default: begin
+ rhs_array_muxed13 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed14 <= 1'd0;
+ case (litedramcore_roundrobin0_grant)
+ default: begin
+ rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed15 <= 23'd0;
+ case (litedramcore_roundrobin1_grant)
+ default: begin
+ rhs_array_muxed15 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed16 <= 1'd0;
+ case (litedramcore_roundrobin1_grant)
+ default: begin
+ rhs_array_muxed16 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed17 <= 1'd0;
+ case (litedramcore_roundrobin1_grant)
+ default: begin
+ rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed18 <= 23'd0;
+ case (litedramcore_roundrobin2_grant)
+ default: begin
+ rhs_array_muxed18 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed19 <= 1'd0;
+ case (litedramcore_roundrobin2_grant)
+ default: begin
+ rhs_array_muxed19 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed20 <= 1'd0;
+ case (litedramcore_roundrobin2_grant)
+ default: begin
+ rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed21 <= 23'd0;
+ case (litedramcore_roundrobin3_grant)
+ default: begin
+ rhs_array_muxed21 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed22 <= 1'd0;
+ case (litedramcore_roundrobin3_grant)
+ default: begin
+ rhs_array_muxed22 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed23 <= 1'd0;
+ case (litedramcore_roundrobin3_grant)
+ default: begin
+ rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
end
always @(*) begin
- rhs_array_muxed24 <= 23'd0;
- case (litedramcore_roundrobin4_grant)
- default: begin
- rhs_array_muxed24 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed25 <= 1'd0;
- case (litedramcore_roundrobin4_grant)
- default: begin
- rhs_array_muxed25 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed26 <= 1'd0;
- case (litedramcore_roundrobin4_grant)
- default: begin
- rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed27 <= 23'd0;
- case (litedramcore_roundrobin5_grant)
- default: begin
- rhs_array_muxed27 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed28 <= 1'd0;
- case (litedramcore_roundrobin5_grant)
- default: begin
- rhs_array_muxed28 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed29 <= 1'd0;
- case (litedramcore_roundrobin5_grant)
- default: begin
- rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed30 <= 23'd0;
- case (litedramcore_roundrobin6_grant)
- default: begin
- rhs_array_muxed30 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed31 <= 1'd0;
- case (litedramcore_roundrobin6_grant)
- default: begin
- rhs_array_muxed31 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed32 <= 1'd0;
- case (litedramcore_roundrobin6_grant)
- default: begin
- rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed33 <= 23'd0;
- case (litedramcore_roundrobin7_grant)
- default: begin
- rhs_array_muxed33 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed34 <= 1'd0;
- case (litedramcore_roundrobin7_grant)
- default: begin
- rhs_array_muxed34 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed35 <= 1'd0;
- case (litedramcore_roundrobin7_grant)
- default: begin
- rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- array_muxed0 <= 3'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed0 <= litedramcore_nop_ba[2:0];
- end
- 1'd1: begin
- array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
- end
- 2'd2: begin
- array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0];
- end
- default: begin
- array_muxed0 <= litedramcore_cmd_payload_ba[2:0];
- end
- endcase
-end
-always @(*) begin
- array_muxed1 <= 16'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed1 <= litedramcore_nop_a;
- end
- 1'd1: begin
- array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a;
- end
- 2'd2: begin
- array_muxed1 <= litedramcore_choose_req_cmd_payload_a;
- end
- default: begin
- array_muxed1 <= litedramcore_cmd_payload_a;
- end
- endcase
-end
-always @(*) begin
- array_muxed2 <= 1'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed2 <= 1'd0;
- end
- 1'd1: begin
- array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
- end
- 2'd2: begin
- array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
- end
- default: begin
- array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
- end
- endcase
-end
-always @(*) begin
- array_muxed3 <= 1'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed3 <= 1'd0;
- end
- 1'd1: begin
- array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
- end
- 2'd2: begin
- array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
- end
- default: begin
- array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
- end
- endcase
-end
-always @(*) begin
- array_muxed4 <= 1'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed4 <= 1'd0;
- end
- 1'd1: begin
- array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
- end
- 2'd2: begin
- array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
- end
- default: begin
- array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
- end
- endcase
-end
-always @(*) begin
- array_muxed5 <= 1'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed5 <= 1'd0;
- end
- 1'd1: begin
- array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
- end
- 2'd2: begin
- array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
- end
- default: begin
- array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
- end
- endcase
-end
-always @(*) begin
- array_muxed6 <= 1'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed6 <= 1'd0;
- end
- 1'd1: begin
- array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
- end
- 2'd2: begin
- array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
- end
- default: begin
- array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
- end
- endcase
-end
-always @(*) begin
- array_muxed7 <= 3'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed7 <= litedramcore_nop_ba[2:0];
- end
- 1'd1: begin
- array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
- end
- 2'd2: begin
- array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0];
- end
- default: begin
- array_muxed7 <= litedramcore_cmd_payload_ba[2:0];
- end
- endcase
-end
-always @(*) begin
- array_muxed8 <= 16'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed8 <= litedramcore_nop_a;
- end
- 1'd1: begin
- array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a;
- end
- 2'd2: begin
- array_muxed8 <= litedramcore_choose_req_cmd_payload_a;
- end
- default: begin
- array_muxed8 <= litedramcore_cmd_payload_a;
- end
- endcase
-end
-always @(*) begin
- array_muxed9 <= 1'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed9 <= 1'd0;
- end
- 1'd1: begin
- array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
- end
- 2'd2: begin
- array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
- end
- default: begin
- array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
- end
- endcase
-end
-always @(*) begin
- array_muxed10 <= 1'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed10 <= 1'd0;
- end
- 1'd1: begin
- array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
- end
- 2'd2: begin
- array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
- end
- default: begin
- array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
- end
- endcase
-end
-always @(*) begin
- array_muxed11 <= 1'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed11 <= 1'd0;
- end
- 1'd1: begin
- array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
- end
- 2'd2: begin
- array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
- end
- default: begin
- array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
- end
- endcase
-end
-always @(*) begin
- array_muxed12 <= 1'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed12 <= 1'd0;
- end
- 1'd1: begin
- array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
- end
- 2'd2: begin
- array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
- end
- default: begin
- array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
- end
- endcase
-end
-always @(*) begin
- array_muxed13 <= 1'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed13 <= 1'd0;
- end
- 1'd1: begin
- array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
- end
- 2'd2: begin
- array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
- end
- default: begin
- array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
- end
- endcase
-end
-always @(*) begin
- array_muxed14 <= 3'd0;
- case (litedramcore_steerer_sel2)
- 1'd0: begin
- array_muxed14 <= litedramcore_nop_ba[2:0];
- end
- 1'd1: begin
- array_muxed14 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
- end
- 2'd2: begin
- array_muxed14 <= litedramcore_choose_req_cmd_payload_ba[2:0];
- end
- default: begin
- array_muxed14 <= litedramcore_cmd_payload_ba[2:0];
- end
- endcase
-end
-always @(*) begin
- array_muxed15 <= 16'd0;
- case (litedramcore_steerer_sel2)
- 1'd0: begin
- array_muxed15 <= litedramcore_nop_a;
- end
- 1'd1: begin
- array_muxed15 <= litedramcore_choose_cmd_cmd_payload_a;
- end
- 2'd2: begin
- array_muxed15 <= litedramcore_choose_req_cmd_payload_a;
- end
- default: begin
- array_muxed15 <= litedramcore_cmd_payload_a;
- end
- endcase
-end
-always @(*) begin
- array_muxed16 <= 1'd0;
- case (litedramcore_steerer_sel2)
- 1'd0: begin
- array_muxed16 <= 1'd0;
- end
- 1'd1: begin
- array_muxed16 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
- end
- 2'd2: begin
- array_muxed16 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
- end
- default: begin
- array_muxed16 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
- end
- endcase
-end
-always @(*) begin
- array_muxed17 <= 1'd0;
- case (litedramcore_steerer_sel2)
- 1'd0: begin
- array_muxed17 <= 1'd0;
- end
- 1'd1: begin
- array_muxed17 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
- end
- 2'd2: begin
- array_muxed17 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
- end
- default: begin
- array_muxed17 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
- end
- endcase
-end
-always @(*) begin
- array_muxed18 <= 1'd0;
- case (litedramcore_steerer_sel2)
- 1'd0: begin
- array_muxed18 <= 1'd0;
- end
- 1'd1: begin
- array_muxed18 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
- end
- 2'd2: begin
- array_muxed18 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
- end
- default: begin
- array_muxed18 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
- end
- endcase
-end
-always @(*) begin
- array_muxed19 <= 1'd0;
- case (litedramcore_steerer_sel2)
- 1'd0: begin
- array_muxed19 <= 1'd0;
- end
- 1'd1: begin
- array_muxed19 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
- end
- 2'd2: begin
- array_muxed19 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
- end
- default: begin
- array_muxed19 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
- end
- endcase
-end
-always @(*) begin
- array_muxed20 <= 1'd0;
- case (litedramcore_steerer_sel2)
- 1'd0: begin
- array_muxed20 <= 1'd0;
- end
- 1'd1: begin
- array_muxed20 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
- end
- 2'd2: begin
- array_muxed20 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
- end
- default: begin
- array_muxed20 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
- end
- endcase
-end
-always @(*) begin
- array_muxed21 <= 3'd0;
- case (litedramcore_steerer_sel3)
- 1'd0: begin
- array_muxed21 <= litedramcore_nop_ba[2:0];
- end
- 1'd1: begin
- array_muxed21 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
- end
- 2'd2: begin
- array_muxed21 <= litedramcore_choose_req_cmd_payload_ba[2:0];
- end
- default: begin
- array_muxed21 <= litedramcore_cmd_payload_ba[2:0];
- end
- endcase
-end
-always @(*) begin
- array_muxed22 <= 16'd0;
- case (litedramcore_steerer_sel3)
- 1'd0: begin
- array_muxed22 <= litedramcore_nop_a;
- end
- 1'd1: begin
- array_muxed22 <= litedramcore_choose_cmd_cmd_payload_a;
- end
- 2'd2: begin
- array_muxed22 <= litedramcore_choose_req_cmd_payload_a;
- end
- default: begin
- array_muxed22 <= litedramcore_cmd_payload_a;
- end
- endcase
-end
-always @(*) begin
- array_muxed23 <= 1'd0;
- case (litedramcore_steerer_sel3)
- 1'd0: begin
- array_muxed23 <= 1'd0;
- end
- 1'd1: begin
- array_muxed23 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
- end
- 2'd2: begin
- array_muxed23 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
- end
- default: begin
- array_muxed23 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
- end
- endcase
-end
-always @(*) begin
- array_muxed24 <= 1'd0;
- case (litedramcore_steerer_sel3)
- 1'd0: begin
- array_muxed24 <= 1'd0;
- end
- 1'd1: begin
- array_muxed24 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
- end
- 2'd2: begin
- array_muxed24 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
- end
- default: begin
- array_muxed24 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
- end
- endcase
-end
-always @(*) begin
- array_muxed25 <= 1'd0;
- case (litedramcore_steerer_sel3)
- 1'd0: begin
- array_muxed25 <= 1'd0;
- end
- 1'd1: begin
- array_muxed25 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
- end
- 2'd2: begin
- array_muxed25 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
- end
- default: begin
- array_muxed25 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
- end
- endcase
-end
-always @(*) begin
- array_muxed26 <= 1'd0;
- case (litedramcore_steerer_sel3)
- 1'd0: begin
- array_muxed26 <= 1'd0;
- end
- 1'd1: begin
- array_muxed26 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
- end
- 2'd2: begin
- array_muxed26 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
- end
- default: begin
- array_muxed26 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
- end
- endcase
-end
-always @(*) begin
- array_muxed27 <= 1'd0;
- case (litedramcore_steerer_sel3)
- 1'd0: begin
- array_muxed27 <= 1'd0;
- end
- 1'd1: begin
- array_muxed27 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
- end
- 2'd2: begin
- array_muxed27 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
- end
- default: begin
- array_muxed27 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
- end
- endcase
+ rhs_array_muxed24 <= 23'd0;
+ case (litedramcore_roundrobin4_grant)
+ default: begin
+ rhs_array_muxed24 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed25 <= 1'd0;
+ case (litedramcore_roundrobin4_grant)
+ default: begin
+ rhs_array_muxed25 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed26 <= 1'd0;
+ case (litedramcore_roundrobin4_grant)
+ default: begin
+ rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed27 <= 23'd0;
+ case (litedramcore_roundrobin5_grant)
+ default: begin
+ rhs_array_muxed27 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed28 <= 1'd0;
+ case (litedramcore_roundrobin5_grant)
+ default: begin
+ rhs_array_muxed28 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed29 <= 1'd0;
+ case (litedramcore_roundrobin5_grant)
+ default: begin
+ rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed30 <= 23'd0;
+ case (litedramcore_roundrobin6_grant)
+ default: begin
+ rhs_array_muxed30 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed31 <= 1'd0;
+ case (litedramcore_roundrobin6_grant)
+ default: begin
+ rhs_array_muxed31 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed32 <= 1'd0;
+ case (litedramcore_roundrobin6_grant)
+ default: begin
+ rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed33 <= 23'd0;
+ case (litedramcore_roundrobin7_grant)
+ default: begin
+ rhs_array_muxed33 <= {user_port_cmd_payload_addr[25:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed34 <= 1'd0;
+ case (litedramcore_roundrobin7_grant)
+ default: begin
+ rhs_array_muxed34 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed35 <= 1'd0;
+ case (litedramcore_roundrobin7_grant)
+ default: begin
+ rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed0 <= 3'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed0 <= litedramcore_nop_ba[2:0];
+ end
+ 1'd1: begin
+ array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+ end
+ 2'd2: begin
+ array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+ end
+ default: begin
+ array_muxed0 <= litedramcore_cmd_payload_ba[2:0];
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed1 <= 16'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed1 <= litedramcore_nop_a;
+ end
+ 1'd1: begin
+ array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a;
+ end
+ 2'd2: begin
+ array_muxed1 <= litedramcore_choose_req_cmd_payload_a;
+ end
+ default: begin
+ array_muxed1 <= litedramcore_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed2 <= 1'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed2 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+ end
+ 2'd2: begin
+ array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+ end
+ default: begin
+ array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed3 <= 1'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed3 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+ end
+ 2'd2: begin
+ array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+ end
+ default: begin
+ array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed4 <= 1'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed4 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+ end
+ 2'd2: begin
+ array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+ end
+ default: begin
+ array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed5 <= 1'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed5 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+ end
+ 2'd2: begin
+ array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+ end
+ default: begin
+ array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed6 <= 1'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed6 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+ end
+ 2'd2: begin
+ array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+ end
+ default: begin
+ array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed7 <= 3'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed7 <= litedramcore_nop_ba[2:0];
+ end
+ 1'd1: begin
+ array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+ end
+ 2'd2: begin
+ array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+ end
+ default: begin
+ array_muxed7 <= litedramcore_cmd_payload_ba[2:0];
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed8 <= 16'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed8 <= litedramcore_nop_a;
+ end
+ 1'd1: begin
+ array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a;
+ end
+ 2'd2: begin
+ array_muxed8 <= litedramcore_choose_req_cmd_payload_a;
+ end
+ default: begin
+ array_muxed8 <= litedramcore_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed9 <= 1'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed9 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+ end
+ 2'd2: begin
+ array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+ end
+ default: begin
+ array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed10 <= 1'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed10 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+ end
+ 2'd2: begin
+ array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+ end
+ default: begin
+ array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed11 <= 1'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed11 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+ end
+ 2'd2: begin
+ array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+ end
+ default: begin
+ array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed12 <= 1'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed12 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+ end
+ 2'd2: begin
+ array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+ end
+ default: begin
+ array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed13 <= 1'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed13 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+ end
+ 2'd2: begin
+ array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+ end
+ default: begin
+ array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed14 <= 3'd0;
+ case (litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed14 <= litedramcore_nop_ba[2:0];
+ end
+ 1'd1: begin
+ array_muxed14 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+ end
+ 2'd2: begin
+ array_muxed14 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+ end
+ default: begin
+ array_muxed14 <= litedramcore_cmd_payload_ba[2:0];
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed15 <= 16'd0;
+ case (litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed15 <= litedramcore_nop_a;
+ end
+ 1'd1: begin
+ array_muxed15 <= litedramcore_choose_cmd_cmd_payload_a;
+ end
+ 2'd2: begin
+ array_muxed15 <= litedramcore_choose_req_cmd_payload_a;
+ end
+ default: begin
+ array_muxed15 <= litedramcore_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed16 <= 1'd0;
+ case (litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed16 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed16 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+ end
+ 2'd2: begin
+ array_muxed16 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+ end
+ default: begin
+ array_muxed16 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed17 <= 1'd0;
+ case (litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed17 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed17 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+ end
+ 2'd2: begin
+ array_muxed17 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+ end
+ default: begin
+ array_muxed17 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed18 <= 1'd0;
+ case (litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed18 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed18 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+ end
+ 2'd2: begin
+ array_muxed18 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+ end
+ default: begin
+ array_muxed18 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed19 <= 1'd0;
+ case (litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed19 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed19 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+ end
+ 2'd2: begin
+ array_muxed19 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+ end
+ default: begin
+ array_muxed19 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed20 <= 1'd0;
+ case (litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed20 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed20 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+ end
+ 2'd2: begin
+ array_muxed20 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+ end
+ default: begin
+ array_muxed20 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed21 <= 3'd0;
+ case (litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed21 <= litedramcore_nop_ba[2:0];
+ end
+ 1'd1: begin
+ array_muxed21 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+ end
+ 2'd2: begin
+ array_muxed21 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+ end
+ default: begin
+ array_muxed21 <= litedramcore_cmd_payload_ba[2:0];
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed22 <= 16'd0;
+ case (litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed22 <= litedramcore_nop_a;
+ end
+ 1'd1: begin
+ array_muxed22 <= litedramcore_choose_cmd_cmd_payload_a;
+ end
+ 2'd2: begin
+ array_muxed22 <= litedramcore_choose_req_cmd_payload_a;
+ end
+ default: begin
+ array_muxed22 <= litedramcore_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed23 <= 1'd0;
+ case (litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed23 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed23 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+ end
+ 2'd2: begin
+ array_muxed23 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+ end
+ default: begin
+ array_muxed23 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed24 <= 1'd0;
+ case (litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed24 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed24 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+ end
+ 2'd2: begin
+ array_muxed24 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+ end
+ default: begin
+ array_muxed24 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed25 <= 1'd0;
+ case (litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed25 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed25 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+ end
+ 2'd2: begin
+ array_muxed25 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+ end
+ default: begin
+ array_muxed25 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed26 <= 1'd0;
+ case (litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed26 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed26 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+ end
+ 2'd2: begin
+ array_muxed26 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+ end
+ default: begin
+ array_muxed26 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed27 <= 1'd0;
+ case (litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed27 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed27 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+ end
+ 2'd2: begin
+ array_muxed27 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+ end
+ default: begin
+ array_muxed27 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+ end
+ endcase
end
assign xilinxasyncresetsynchronizerimpl0 = (~locked);
assign xilinxasyncresetsynchronizerimpl1 = (~locked);
//------------------------------------------------------------------------------
always @(posedge iodelay_clk) begin
- if ((reset_counter != 1'd0)) begin
- reset_counter <= (reset_counter - 1'd1);
- end else begin
- ic_reset <= 1'd0;
- end
- if (iodelay_rst) begin
- reset_counter <= 4'd15;
- ic_reset <= 1'd1;
- end
+ if ((reset_counter != 1'd0)) begin
+ reset_counter <= (reset_counter - 1'd1);
+ end else begin
+ ic_reset <= 1'd0;
+ end
+ if (iodelay_rst) begin
+ reset_counter <= 4'd15;
+ ic_reset <= 1'd1;
+ end
end
always @(posedge sys_clk) begin
- a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dqs_oe_delay_tappeddelayline;
- a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0;
- a7ddrphy_dqspattern_o1 <= a7ddrphy_dqspattern_o0;
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip0_value0 <= (a7ddrphy_bitslip0_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip0_value0 <= 3'd7;
- end
- a7ddrphy_bitslip0_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip0_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip1_value0 <= (a7ddrphy_bitslip1_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip1_value0 <= 3'd7;
- end
- a7ddrphy_bitslip1_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip1_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip0_value1 <= (a7ddrphy_bitslip0_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip0_value1 <= 3'd7;
- end
- a7ddrphy_bitslip0_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[2], a7ddrphy_dfi_p3_wrdata_mask[0], a7ddrphy_dfi_p2_wrdata_mask[2], a7ddrphy_dfi_p2_wrdata_mask[0], a7ddrphy_dfi_p1_wrdata_mask[2], a7ddrphy_dfi_p1_wrdata_mask[0], a7ddrphy_dfi_p0_wrdata_mask[2], a7ddrphy_dfi_p0_wrdata_mask[0]}, a7ddrphy_bitslip0_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip1_value1 <= (a7ddrphy_bitslip1_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip1_value1 <= 3'd7;
- end
- a7ddrphy_bitslip1_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[3], a7ddrphy_dfi_p3_wrdata_mask[1], a7ddrphy_dfi_p2_wrdata_mask[3], a7ddrphy_dfi_p2_wrdata_mask[1], a7ddrphy_dfi_p1_wrdata_mask[3], a7ddrphy_dfi_p1_wrdata_mask[1], a7ddrphy_dfi_p0_wrdata_mask[3], a7ddrphy_dfi_p0_wrdata_mask[1]}, a7ddrphy_bitslip1_r1[15:8]};
- a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dq_oe_delay_tappeddelayline;
- a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0;
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip0_value2 <= (a7ddrphy_bitslip0_value2 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip0_value2 <= 3'd7;
- end
- a7ddrphy_bitslip0_r2 <= {{a7ddrphy_dfi_p3_wrdata[16], a7ddrphy_dfi_p3_wrdata[0], a7ddrphy_dfi_p2_wrdata[16], a7ddrphy_dfi_p2_wrdata[0], a7ddrphy_dfi_p1_wrdata[16], a7ddrphy_dfi_p1_wrdata[0], a7ddrphy_dfi_p0_wrdata[16], a7ddrphy_dfi_p0_wrdata[0]}, a7ddrphy_bitslip0_r2[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip0_value3 <= (a7ddrphy_bitslip0_value3 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip0_value3 <= 3'd7;
- end
- a7ddrphy_bitslip0_r3 <= {a7ddrphy_bitslip03, a7ddrphy_bitslip0_r3[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip1_value2 <= (a7ddrphy_bitslip1_value2 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip1_value2 <= 3'd7;
- end
- a7ddrphy_bitslip1_r2 <= {{a7ddrphy_dfi_p3_wrdata[17], a7ddrphy_dfi_p3_wrdata[1], a7ddrphy_dfi_p2_wrdata[17], a7ddrphy_dfi_p2_wrdata[1], a7ddrphy_dfi_p1_wrdata[17], a7ddrphy_dfi_p1_wrdata[1], a7ddrphy_dfi_p0_wrdata[17], a7ddrphy_dfi_p0_wrdata[1]}, a7ddrphy_bitslip1_r2[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip1_value3 <= (a7ddrphy_bitslip1_value3 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip1_value3 <= 3'd7;
- end
- a7ddrphy_bitslip1_r3 <= {a7ddrphy_bitslip13, a7ddrphy_bitslip1_r3[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip2_value0 <= (a7ddrphy_bitslip2_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip2_value0 <= 3'd7;
- end
- a7ddrphy_bitslip2_r0 <= {{a7ddrphy_dfi_p3_wrdata[18], a7ddrphy_dfi_p3_wrdata[2], a7ddrphy_dfi_p2_wrdata[18], a7ddrphy_dfi_p2_wrdata[2], a7ddrphy_dfi_p1_wrdata[18], a7ddrphy_dfi_p1_wrdata[2], a7ddrphy_dfi_p0_wrdata[18], a7ddrphy_dfi_p0_wrdata[2]}, a7ddrphy_bitslip2_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip2_value1 <= (a7ddrphy_bitslip2_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip2_value1 <= 3'd7;
- end
- a7ddrphy_bitslip2_r1 <= {a7ddrphy_bitslip21, a7ddrphy_bitslip2_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip3_value0 <= (a7ddrphy_bitslip3_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip3_value0 <= 3'd7;
- end
- a7ddrphy_bitslip3_r0 <= {{a7ddrphy_dfi_p3_wrdata[19], a7ddrphy_dfi_p3_wrdata[3], a7ddrphy_dfi_p2_wrdata[19], a7ddrphy_dfi_p2_wrdata[3], a7ddrphy_dfi_p1_wrdata[19], a7ddrphy_dfi_p1_wrdata[3], a7ddrphy_dfi_p0_wrdata[19], a7ddrphy_dfi_p0_wrdata[3]}, a7ddrphy_bitslip3_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip3_value1 <= (a7ddrphy_bitslip3_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip3_value1 <= 3'd7;
- end
- a7ddrphy_bitslip3_r1 <= {a7ddrphy_bitslip31, a7ddrphy_bitslip3_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip4_value0 <= (a7ddrphy_bitslip4_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip4_value0 <= 3'd7;
- end
- a7ddrphy_bitslip4_r0 <= {{a7ddrphy_dfi_p3_wrdata[20], a7ddrphy_dfi_p3_wrdata[4], a7ddrphy_dfi_p2_wrdata[20], a7ddrphy_dfi_p2_wrdata[4], a7ddrphy_dfi_p1_wrdata[20], a7ddrphy_dfi_p1_wrdata[4], a7ddrphy_dfi_p0_wrdata[20], a7ddrphy_dfi_p0_wrdata[4]}, a7ddrphy_bitslip4_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip4_value1 <= (a7ddrphy_bitslip4_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip4_value1 <= 3'd7;
- end
- a7ddrphy_bitslip4_r1 <= {a7ddrphy_bitslip41, a7ddrphy_bitslip4_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip5_value0 <= (a7ddrphy_bitslip5_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip5_value0 <= 3'd7;
- end
- a7ddrphy_bitslip5_r0 <= {{a7ddrphy_dfi_p3_wrdata[21], a7ddrphy_dfi_p3_wrdata[5], a7ddrphy_dfi_p2_wrdata[21], a7ddrphy_dfi_p2_wrdata[5], a7ddrphy_dfi_p1_wrdata[21], a7ddrphy_dfi_p1_wrdata[5], a7ddrphy_dfi_p0_wrdata[21], a7ddrphy_dfi_p0_wrdata[5]}, a7ddrphy_bitslip5_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip5_value1 <= (a7ddrphy_bitslip5_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip5_value1 <= 3'd7;
- end
- a7ddrphy_bitslip5_r1 <= {a7ddrphy_bitslip51, a7ddrphy_bitslip5_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip6_value0 <= (a7ddrphy_bitslip6_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip6_value0 <= 3'd7;
- end
- a7ddrphy_bitslip6_r0 <= {{a7ddrphy_dfi_p3_wrdata[22], a7ddrphy_dfi_p3_wrdata[6], a7ddrphy_dfi_p2_wrdata[22], a7ddrphy_dfi_p2_wrdata[6], a7ddrphy_dfi_p1_wrdata[22], a7ddrphy_dfi_p1_wrdata[6], a7ddrphy_dfi_p0_wrdata[22], a7ddrphy_dfi_p0_wrdata[6]}, a7ddrphy_bitslip6_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip6_value1 <= (a7ddrphy_bitslip6_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip6_value1 <= 3'd7;
- end
- a7ddrphy_bitslip6_r1 <= {a7ddrphy_bitslip61, a7ddrphy_bitslip6_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip7_value0 <= (a7ddrphy_bitslip7_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip7_value0 <= 3'd7;
- end
- a7ddrphy_bitslip7_r0 <= {{a7ddrphy_dfi_p3_wrdata[23], a7ddrphy_dfi_p3_wrdata[7], a7ddrphy_dfi_p2_wrdata[23], a7ddrphy_dfi_p2_wrdata[7], a7ddrphy_dfi_p1_wrdata[23], a7ddrphy_dfi_p1_wrdata[7], a7ddrphy_dfi_p0_wrdata[23], a7ddrphy_dfi_p0_wrdata[7]}, a7ddrphy_bitslip7_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip7_value1 <= (a7ddrphy_bitslip7_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip7_value1 <= 3'd7;
- end
- a7ddrphy_bitslip7_r1 <= {a7ddrphy_bitslip71, a7ddrphy_bitslip7_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip8_value0 <= (a7ddrphy_bitslip8_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip8_value0 <= 3'd7;
- end
- a7ddrphy_bitslip8_r0 <= {{a7ddrphy_dfi_p3_wrdata[24], a7ddrphy_dfi_p3_wrdata[8], a7ddrphy_dfi_p2_wrdata[24], a7ddrphy_dfi_p2_wrdata[8], a7ddrphy_dfi_p1_wrdata[24], a7ddrphy_dfi_p1_wrdata[8], a7ddrphy_dfi_p0_wrdata[24], a7ddrphy_dfi_p0_wrdata[8]}, a7ddrphy_bitslip8_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip8_value1 <= (a7ddrphy_bitslip8_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip8_value1 <= 3'd7;
- end
- a7ddrphy_bitslip8_r1 <= {a7ddrphy_bitslip81, a7ddrphy_bitslip8_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip9_value0 <= (a7ddrphy_bitslip9_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip9_value0 <= 3'd7;
- end
- a7ddrphy_bitslip9_r0 <= {{a7ddrphy_dfi_p3_wrdata[25], a7ddrphy_dfi_p3_wrdata[9], a7ddrphy_dfi_p2_wrdata[25], a7ddrphy_dfi_p2_wrdata[9], a7ddrphy_dfi_p1_wrdata[25], a7ddrphy_dfi_p1_wrdata[9], a7ddrphy_dfi_p0_wrdata[25], a7ddrphy_dfi_p0_wrdata[9]}, a7ddrphy_bitslip9_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip9_value1 <= (a7ddrphy_bitslip9_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip9_value1 <= 3'd7;
- end
- a7ddrphy_bitslip9_r1 <= {a7ddrphy_bitslip91, a7ddrphy_bitslip9_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip10_value0 <= (a7ddrphy_bitslip10_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip10_value0 <= 3'd7;
- end
- a7ddrphy_bitslip10_r0 <= {{a7ddrphy_dfi_p3_wrdata[26], a7ddrphy_dfi_p3_wrdata[10], a7ddrphy_dfi_p2_wrdata[26], a7ddrphy_dfi_p2_wrdata[10], a7ddrphy_dfi_p1_wrdata[26], a7ddrphy_dfi_p1_wrdata[10], a7ddrphy_dfi_p0_wrdata[26], a7ddrphy_dfi_p0_wrdata[10]}, a7ddrphy_bitslip10_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip10_value1 <= (a7ddrphy_bitslip10_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip10_value1 <= 3'd7;
- end
- a7ddrphy_bitslip10_r1 <= {a7ddrphy_bitslip101, a7ddrphy_bitslip10_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip11_value0 <= (a7ddrphy_bitslip11_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip11_value0 <= 3'd7;
- end
- a7ddrphy_bitslip11_r0 <= {{a7ddrphy_dfi_p3_wrdata[27], a7ddrphy_dfi_p3_wrdata[11], a7ddrphy_dfi_p2_wrdata[27], a7ddrphy_dfi_p2_wrdata[11], a7ddrphy_dfi_p1_wrdata[27], a7ddrphy_dfi_p1_wrdata[11], a7ddrphy_dfi_p0_wrdata[27], a7ddrphy_dfi_p0_wrdata[11]}, a7ddrphy_bitslip11_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip11_value1 <= (a7ddrphy_bitslip11_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip11_value1 <= 3'd7;
- end
- a7ddrphy_bitslip11_r1 <= {a7ddrphy_bitslip111, a7ddrphy_bitslip11_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip12_value0 <= (a7ddrphy_bitslip12_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip12_value0 <= 3'd7;
- end
- a7ddrphy_bitslip12_r0 <= {{a7ddrphy_dfi_p3_wrdata[28], a7ddrphy_dfi_p3_wrdata[12], a7ddrphy_dfi_p2_wrdata[28], a7ddrphy_dfi_p2_wrdata[12], a7ddrphy_dfi_p1_wrdata[28], a7ddrphy_dfi_p1_wrdata[12], a7ddrphy_dfi_p0_wrdata[28], a7ddrphy_dfi_p0_wrdata[12]}, a7ddrphy_bitslip12_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip12_value1 <= (a7ddrphy_bitslip12_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip12_value1 <= 3'd7;
- end
- a7ddrphy_bitslip12_r1 <= {a7ddrphy_bitslip121, a7ddrphy_bitslip12_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip13_value0 <= (a7ddrphy_bitslip13_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip13_value0 <= 3'd7;
- end
- a7ddrphy_bitslip13_r0 <= {{a7ddrphy_dfi_p3_wrdata[29], a7ddrphy_dfi_p3_wrdata[13], a7ddrphy_dfi_p2_wrdata[29], a7ddrphy_dfi_p2_wrdata[13], a7ddrphy_dfi_p1_wrdata[29], a7ddrphy_dfi_p1_wrdata[13], a7ddrphy_dfi_p0_wrdata[29], a7ddrphy_dfi_p0_wrdata[13]}, a7ddrphy_bitslip13_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip13_value1 <= (a7ddrphy_bitslip13_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip13_value1 <= 3'd7;
- end
- a7ddrphy_bitslip13_r1 <= {a7ddrphy_bitslip131, a7ddrphy_bitslip13_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip14_value0 <= (a7ddrphy_bitslip14_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip14_value0 <= 3'd7;
- end
- a7ddrphy_bitslip14_r0 <= {{a7ddrphy_dfi_p3_wrdata[30], a7ddrphy_dfi_p3_wrdata[14], a7ddrphy_dfi_p2_wrdata[30], a7ddrphy_dfi_p2_wrdata[14], a7ddrphy_dfi_p1_wrdata[30], a7ddrphy_dfi_p1_wrdata[14], a7ddrphy_dfi_p0_wrdata[30], a7ddrphy_dfi_p0_wrdata[14]}, a7ddrphy_bitslip14_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip14_value1 <= (a7ddrphy_bitslip14_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip14_value1 <= 3'd7;
- end
- a7ddrphy_bitslip14_r1 <= {a7ddrphy_bitslip141, a7ddrphy_bitslip14_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip15_value0 <= (a7ddrphy_bitslip15_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip15_value0 <= 3'd7;
- end
- a7ddrphy_bitslip15_r0 <= {{a7ddrphy_dfi_p3_wrdata[31], a7ddrphy_dfi_p3_wrdata[15], a7ddrphy_dfi_p2_wrdata[31], a7ddrphy_dfi_p2_wrdata[15], a7ddrphy_dfi_p1_wrdata[31], a7ddrphy_dfi_p1_wrdata[15], a7ddrphy_dfi_p0_wrdata[31], a7ddrphy_dfi_p0_wrdata[15]}, a7ddrphy_bitslip15_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip15_value1 <= (a7ddrphy_bitslip15_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip15_value1 <= 3'd7;
- end
- a7ddrphy_bitslip15_r1 <= {a7ddrphy_bitslip151, a7ddrphy_bitslip15_r1[15:8]};
- a7ddrphy_rddata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_rddata_en | a7ddrphy_dfi_p1_rddata_en) | a7ddrphy_dfi_p2_rddata_en) | a7ddrphy_dfi_p3_rddata_en);
- a7ddrphy_rddata_en_tappeddelayline1 <= a7ddrphy_rddata_en_tappeddelayline0;
- a7ddrphy_rddata_en_tappeddelayline2 <= a7ddrphy_rddata_en_tappeddelayline1;
- a7ddrphy_rddata_en_tappeddelayline3 <= a7ddrphy_rddata_en_tappeddelayline2;
- a7ddrphy_rddata_en_tappeddelayline4 <= a7ddrphy_rddata_en_tappeddelayline3;
- a7ddrphy_rddata_en_tappeddelayline5 <= a7ddrphy_rddata_en_tappeddelayline4;
- a7ddrphy_rddata_en_tappeddelayline6 <= a7ddrphy_rddata_en_tappeddelayline5;
- a7ddrphy_rddata_en_tappeddelayline7 <= a7ddrphy_rddata_en_tappeddelayline6;
- a7ddrphy_wrdata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_wrdata_en | a7ddrphy_dfi_p1_wrdata_en) | a7ddrphy_dfi_p2_wrdata_en) | a7ddrphy_dfi_p3_wrdata_en);
- a7ddrphy_wrdata_en_tappeddelayline1 <= a7ddrphy_wrdata_en_tappeddelayline0;
- a7ddrphy_wrdata_en_tappeddelayline2 <= a7ddrphy_wrdata_en_tappeddelayline1;
- if (litedramcore_csr_dfi_p0_rddata_valid) begin
- litedramcore_phaseinjector0_rddata_status <= litedramcore_csr_dfi_p0_rddata;
- end
- if (litedramcore_csr_dfi_p1_rddata_valid) begin
- litedramcore_phaseinjector1_rddata_status <= litedramcore_csr_dfi_p1_rddata;
- end
- if (litedramcore_csr_dfi_p2_rddata_valid) begin
- litedramcore_phaseinjector2_rddata_status <= litedramcore_csr_dfi_p2_rddata;
- end
- if (litedramcore_csr_dfi_p3_rddata_valid) begin
- litedramcore_phaseinjector3_rddata_status <= litedramcore_csr_dfi_p3_rddata;
- end
- if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin
- litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1);
- end else begin
- litedramcore_timer_count1 <= 10'd781;
- end
- litedramcore_postponer_req_o <= 1'd0;
- if (litedramcore_postponer_req_i) begin
- litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1);
- if ((litedramcore_postponer_count == 1'd0)) begin
- litedramcore_postponer_count <= 1'd0;
- litedramcore_postponer_req_o <= 1'd1;
- end
- end
- if (litedramcore_sequencer_start0) begin
- litedramcore_sequencer_count <= 1'd0;
- end else begin
- if (litedramcore_sequencer_done1) begin
- if ((litedramcore_sequencer_count != 1'd0)) begin
- litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1);
- end
- end
- end
- litedramcore_cmd_payload_a <= 1'd0;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd0;
- litedramcore_cmd_payload_we <= 1'd0;
- litedramcore_sequencer_done1 <= 1'd0;
- if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin
- litedramcore_cmd_payload_a <= 11'd1024;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd1;
- litedramcore_cmd_payload_we <= 1'd1;
- end
- if ((litedramcore_sequencer_counter == 2'd3)) begin
- litedramcore_cmd_payload_a <= 11'd1024;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd1;
- litedramcore_cmd_payload_ras <= 1'd1;
- litedramcore_cmd_payload_we <= 1'd0;
- end
- if ((litedramcore_sequencer_counter == 7'd73)) begin
- litedramcore_cmd_payload_a <= 1'd0;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd0;
- litedramcore_cmd_payload_we <= 1'd0;
- litedramcore_sequencer_done1 <= 1'd1;
- end
- if ((litedramcore_sequencer_counter == 7'd73)) begin
- litedramcore_sequencer_counter <= 1'd0;
- end else begin
- if ((litedramcore_sequencer_counter != 1'd0)) begin
- litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1);
- end else begin
- if (litedramcore_sequencer_start1) begin
- litedramcore_sequencer_counter <= 1'd1;
- end
- end
- end
- if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin
- litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1);
- end else begin
- litedramcore_zqcs_timer_count1 <= 27'd99999999;
- end
- litedramcore_zqcs_executer_done <= 1'd0;
- if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin
- litedramcore_cmd_payload_a <= 11'd1024;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd1;
- litedramcore_cmd_payload_we <= 1'd1;
- end
- if ((litedramcore_zqcs_executer_counter == 2'd3)) begin
- litedramcore_cmd_payload_a <= 1'd0;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd0;
- litedramcore_cmd_payload_we <= 1'd1;
- end
- if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
- litedramcore_cmd_payload_a <= 1'd0;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd0;
- litedramcore_cmd_payload_we <= 1'd0;
- litedramcore_zqcs_executer_done <= 1'd1;
- end
- if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
- litedramcore_zqcs_executer_counter <= 1'd0;
- end else begin
- if ((litedramcore_zqcs_executer_counter != 1'd0)) begin
- litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1);
- end else begin
- if (litedramcore_zqcs_executer_start) begin
- litedramcore_zqcs_executer_counter <= 1'd1;
- end
- end
- end
- litedramcore_refresher_state <= litedramcore_refresher_next_state;
- if (litedramcore_bankmachine0_row_close) begin
- litedramcore_bankmachine0_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine0_row_open) begin
- litedramcore_bankmachine0_row_opened <= 1'd1;
- litedramcore_bankmachine0_row <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[22:7];
- end
- end
- if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine0_cmd_buffer_source_valid <= litedramcore_bankmachine0_cmd_buffer_sink_valid;
- litedramcore_bankmachine0_cmd_buffer_source_first <= litedramcore_bankmachine0_cmd_buffer_sink_first;
- litedramcore_bankmachine0_cmd_buffer_source_last <= litedramcore_bankmachine0_cmd_buffer_sink_last;
- litedramcore_bankmachine0_cmd_buffer_source_payload_we <= litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine0_twtpcon_valid) begin
- litedramcore_bankmachine0_twtpcon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine0_twtpcon_ready)) begin
- litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine0_trccon_valid) begin
- litedramcore_bankmachine0_trccon_count <= 3'd6;
- if (1'd0) begin
- litedramcore_bankmachine0_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine0_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine0_trccon_ready)) begin
- litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1);
- if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin
- litedramcore_bankmachine0_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine0_trascon_valid) begin
- litedramcore_bankmachine0_trascon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_bankmachine0_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine0_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1);
- if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin
- litedramcore_bankmachine0_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state;
- if (litedramcore_bankmachine1_row_close) begin
- litedramcore_bankmachine1_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine1_row_open) begin
- litedramcore_bankmachine1_row_opened <= 1'd1;
- litedramcore_bankmachine1_row <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[22:7];
- end
- end
- if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine1_cmd_buffer_source_valid <= litedramcore_bankmachine1_cmd_buffer_sink_valid;
- litedramcore_bankmachine1_cmd_buffer_source_first <= litedramcore_bankmachine1_cmd_buffer_sink_first;
- litedramcore_bankmachine1_cmd_buffer_source_last <= litedramcore_bankmachine1_cmd_buffer_sink_last;
- litedramcore_bankmachine1_cmd_buffer_source_payload_we <= litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine1_twtpcon_valid) begin
- litedramcore_bankmachine1_twtpcon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine1_twtpcon_ready)) begin
- litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine1_trccon_valid) begin
- litedramcore_bankmachine1_trccon_count <= 3'd6;
- if (1'd0) begin
- litedramcore_bankmachine1_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine1_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine1_trccon_ready)) begin
- litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1);
- if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin
- litedramcore_bankmachine1_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine1_trascon_valid) begin
- litedramcore_bankmachine1_trascon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_bankmachine1_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine1_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1);
- if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin
- litedramcore_bankmachine1_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state;
- if (litedramcore_bankmachine2_row_close) begin
- litedramcore_bankmachine2_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine2_row_open) begin
- litedramcore_bankmachine2_row_opened <= 1'd1;
- litedramcore_bankmachine2_row <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[22:7];
- end
- end
- if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine2_cmd_buffer_source_valid <= litedramcore_bankmachine2_cmd_buffer_sink_valid;
- litedramcore_bankmachine2_cmd_buffer_source_first <= litedramcore_bankmachine2_cmd_buffer_sink_first;
- litedramcore_bankmachine2_cmd_buffer_source_last <= litedramcore_bankmachine2_cmd_buffer_sink_last;
- litedramcore_bankmachine2_cmd_buffer_source_payload_we <= litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine2_twtpcon_valid) begin
- litedramcore_bankmachine2_twtpcon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine2_twtpcon_ready)) begin
- litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine2_trccon_valid) begin
- litedramcore_bankmachine2_trccon_count <= 3'd6;
- if (1'd0) begin
- litedramcore_bankmachine2_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine2_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine2_trccon_ready)) begin
- litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1);
- if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin
- litedramcore_bankmachine2_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine2_trascon_valid) begin
- litedramcore_bankmachine2_trascon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_bankmachine2_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine2_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1);
- if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin
- litedramcore_bankmachine2_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state;
- if (litedramcore_bankmachine3_row_close) begin
- litedramcore_bankmachine3_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine3_row_open) begin
- litedramcore_bankmachine3_row_opened <= 1'd1;
- litedramcore_bankmachine3_row <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[22:7];
- end
- end
- if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine3_cmd_buffer_source_valid <= litedramcore_bankmachine3_cmd_buffer_sink_valid;
- litedramcore_bankmachine3_cmd_buffer_source_first <= litedramcore_bankmachine3_cmd_buffer_sink_first;
- litedramcore_bankmachine3_cmd_buffer_source_last <= litedramcore_bankmachine3_cmd_buffer_sink_last;
- litedramcore_bankmachine3_cmd_buffer_source_payload_we <= litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine3_twtpcon_valid) begin
- litedramcore_bankmachine3_twtpcon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine3_twtpcon_ready)) begin
- litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine3_trccon_valid) begin
- litedramcore_bankmachine3_trccon_count <= 3'd6;
- if (1'd0) begin
- litedramcore_bankmachine3_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine3_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine3_trccon_ready)) begin
- litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1);
- if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin
- litedramcore_bankmachine3_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine3_trascon_valid) begin
- litedramcore_bankmachine3_trascon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_bankmachine3_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine3_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1);
- if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin
- litedramcore_bankmachine3_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state;
- if (litedramcore_bankmachine4_row_close) begin
- litedramcore_bankmachine4_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine4_row_open) begin
- litedramcore_bankmachine4_row_opened <= 1'd1;
- litedramcore_bankmachine4_row <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[22:7];
- end
- end
- if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine4_cmd_buffer_source_valid <= litedramcore_bankmachine4_cmd_buffer_sink_valid;
- litedramcore_bankmachine4_cmd_buffer_source_first <= litedramcore_bankmachine4_cmd_buffer_sink_first;
- litedramcore_bankmachine4_cmd_buffer_source_last <= litedramcore_bankmachine4_cmd_buffer_sink_last;
- litedramcore_bankmachine4_cmd_buffer_source_payload_we <= litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine4_twtpcon_valid) begin
- litedramcore_bankmachine4_twtpcon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine4_twtpcon_ready)) begin
- litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine4_trccon_valid) begin
- litedramcore_bankmachine4_trccon_count <= 3'd6;
- if (1'd0) begin
- litedramcore_bankmachine4_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine4_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine4_trccon_ready)) begin
- litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1);
- if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin
- litedramcore_bankmachine4_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine4_trascon_valid) begin
- litedramcore_bankmachine4_trascon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_bankmachine4_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine4_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1);
- if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin
- litedramcore_bankmachine4_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state;
- if (litedramcore_bankmachine5_row_close) begin
- litedramcore_bankmachine5_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine5_row_open) begin
- litedramcore_bankmachine5_row_opened <= 1'd1;
- litedramcore_bankmachine5_row <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[22:7];
- end
- end
- if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine5_cmd_buffer_source_valid <= litedramcore_bankmachine5_cmd_buffer_sink_valid;
- litedramcore_bankmachine5_cmd_buffer_source_first <= litedramcore_bankmachine5_cmd_buffer_sink_first;
- litedramcore_bankmachine5_cmd_buffer_source_last <= litedramcore_bankmachine5_cmd_buffer_sink_last;
- litedramcore_bankmachine5_cmd_buffer_source_payload_we <= litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine5_twtpcon_valid) begin
- litedramcore_bankmachine5_twtpcon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine5_twtpcon_ready)) begin
- litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine5_trccon_valid) begin
- litedramcore_bankmachine5_trccon_count <= 3'd6;
- if (1'd0) begin
- litedramcore_bankmachine5_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine5_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine5_trccon_ready)) begin
- litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1);
- if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin
- litedramcore_bankmachine5_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine5_trascon_valid) begin
- litedramcore_bankmachine5_trascon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_bankmachine5_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine5_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1);
- if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin
- litedramcore_bankmachine5_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state;
- if (litedramcore_bankmachine6_row_close) begin
- litedramcore_bankmachine6_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine6_row_open) begin
- litedramcore_bankmachine6_row_opened <= 1'd1;
- litedramcore_bankmachine6_row <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[22:7];
- end
- end
- if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine6_cmd_buffer_source_valid <= litedramcore_bankmachine6_cmd_buffer_sink_valid;
- litedramcore_bankmachine6_cmd_buffer_source_first <= litedramcore_bankmachine6_cmd_buffer_sink_first;
- litedramcore_bankmachine6_cmd_buffer_source_last <= litedramcore_bankmachine6_cmd_buffer_sink_last;
- litedramcore_bankmachine6_cmd_buffer_source_payload_we <= litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine6_twtpcon_valid) begin
- litedramcore_bankmachine6_twtpcon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine6_twtpcon_ready)) begin
- litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine6_trccon_valid) begin
- litedramcore_bankmachine6_trccon_count <= 3'd6;
- if (1'd0) begin
- litedramcore_bankmachine6_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine6_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine6_trccon_ready)) begin
- litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1);
- if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin
- litedramcore_bankmachine6_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine6_trascon_valid) begin
- litedramcore_bankmachine6_trascon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_bankmachine6_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine6_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1);
- if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin
- litedramcore_bankmachine6_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state;
- if (litedramcore_bankmachine7_row_close) begin
- litedramcore_bankmachine7_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine7_row_open) begin
- litedramcore_bankmachine7_row_opened <= 1'd1;
- litedramcore_bankmachine7_row <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[22:7];
- end
- end
- if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine7_cmd_buffer_source_valid <= litedramcore_bankmachine7_cmd_buffer_sink_valid;
- litedramcore_bankmachine7_cmd_buffer_source_first <= litedramcore_bankmachine7_cmd_buffer_sink_first;
- litedramcore_bankmachine7_cmd_buffer_source_last <= litedramcore_bankmachine7_cmd_buffer_sink_last;
- litedramcore_bankmachine7_cmd_buffer_source_payload_we <= litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine7_twtpcon_valid) begin
- litedramcore_bankmachine7_twtpcon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine7_twtpcon_ready)) begin
- litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine7_trccon_valid) begin
- litedramcore_bankmachine7_trccon_count <= 3'd6;
- if (1'd0) begin
- litedramcore_bankmachine7_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine7_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine7_trccon_ready)) begin
- litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1);
- if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin
- litedramcore_bankmachine7_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine7_trascon_valid) begin
- litedramcore_bankmachine7_trascon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_bankmachine7_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine7_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1);
- if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin
- litedramcore_bankmachine7_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state;
- if ((~litedramcore_en0)) begin
- litedramcore_time0 <= 5'd31;
- end else begin
- if ((~litedramcore_max_time0)) begin
- litedramcore_time0 <= (litedramcore_time0 - 1'd1);
- end
- end
- if ((~litedramcore_en1)) begin
- litedramcore_time1 <= 4'd15;
- end else begin
- if ((~litedramcore_max_time1)) begin
- litedramcore_time1 <= (litedramcore_time1 - 1'd1);
- end
- end
- if (litedramcore_choose_cmd_ce) begin
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
- end
- end
- end
- end
- end
- end
- end
- end
- 1'd1: begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
- end
- end
- end
- end
- end
- end
- end
- end
- 2'd2: begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
- end
- end
- end
- end
- end
- end
- end
- end
- 2'd3: begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd4: begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd5: begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd6: begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd7: begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
- end
- end
- end
- end
- end
- end
- end
- end
- endcase
- end
- if (litedramcore_choose_req_ce) begin
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
- end
- end
- end
- end
- end
- end
- end
- end
- 1'd1: begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
- end
- end
- end
- end
- end
- end
- end
- end
- 2'd2: begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
- end
- end
- end
- end
- end
- end
- end
- end
- 2'd3: begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd4: begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd5: begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd6: begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd7: begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
- end
- end
- end
- end
- end
- end
- end
- end
- endcase
- end
- litedramcore_dfi_p0_cs_n <= 1'd0;
- litedramcore_dfi_p0_bank <= array_muxed0;
- litedramcore_dfi_p0_address <= array_muxed1;
- litedramcore_dfi_p0_cas_n <= (~array_muxed2);
- litedramcore_dfi_p0_ras_n <= (~array_muxed3);
- litedramcore_dfi_p0_we_n <= (~array_muxed4);
- litedramcore_dfi_p0_rddata_en <= array_muxed5;
- litedramcore_dfi_p0_wrdata_en <= array_muxed6;
- litedramcore_dfi_p1_cs_n <= 1'd0;
- litedramcore_dfi_p1_bank <= array_muxed7;
- litedramcore_dfi_p1_address <= array_muxed8;
- litedramcore_dfi_p1_cas_n <= (~array_muxed9);
- litedramcore_dfi_p1_ras_n <= (~array_muxed10);
- litedramcore_dfi_p1_we_n <= (~array_muxed11);
- litedramcore_dfi_p1_rddata_en <= array_muxed12;
- litedramcore_dfi_p1_wrdata_en <= array_muxed13;
- litedramcore_dfi_p2_cs_n <= 1'd0;
- litedramcore_dfi_p2_bank <= array_muxed14;
- litedramcore_dfi_p2_address <= array_muxed15;
- litedramcore_dfi_p2_cas_n <= (~array_muxed16);
- litedramcore_dfi_p2_ras_n <= (~array_muxed17);
- litedramcore_dfi_p2_we_n <= (~array_muxed18);
- litedramcore_dfi_p2_rddata_en <= array_muxed19;
- litedramcore_dfi_p2_wrdata_en <= array_muxed20;
- litedramcore_dfi_p3_cs_n <= 1'd0;
- litedramcore_dfi_p3_bank <= array_muxed21;
- litedramcore_dfi_p3_address <= array_muxed22;
- litedramcore_dfi_p3_cas_n <= (~array_muxed23);
- litedramcore_dfi_p3_ras_n <= (~array_muxed24);
- litedramcore_dfi_p3_we_n <= (~array_muxed25);
- litedramcore_dfi_p3_rddata_en <= array_muxed26;
- litedramcore_dfi_p3_wrdata_en <= array_muxed27;
- if (litedramcore_trrdcon_valid) begin
- litedramcore_trrdcon_count <= 1'd1;
- if (1'd0) begin
- litedramcore_trrdcon_ready <= 1'd1;
- end else begin
- litedramcore_trrdcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_trrdcon_ready)) begin
- litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1);
- if ((litedramcore_trrdcon_count == 1'd1)) begin
- litedramcore_trrdcon_ready <= 1'd1;
- end
- end
- end
- litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid};
- if ((litedramcore_tfawcon_count < 3'd4)) begin
- if ((litedramcore_tfawcon_count == 2'd3)) begin
- litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid);
- end else begin
- litedramcore_tfawcon_ready <= 1'd1;
- end
- end
- if (litedramcore_tccdcon_valid) begin
- litedramcore_tccdcon_count <= 1'd0;
- if (1'd1) begin
- litedramcore_tccdcon_ready <= 1'd1;
- end else begin
- litedramcore_tccdcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_tccdcon_ready)) begin
- litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1);
- if ((litedramcore_tccdcon_count == 1'd1)) begin
- litedramcore_tccdcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_twtrcon_valid) begin
- litedramcore_twtrcon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_twtrcon_ready <= 1'd1;
- end else begin
- litedramcore_twtrcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_twtrcon_ready)) begin
- litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1);
- if ((litedramcore_twtrcon_count == 1'd1)) begin
- litedramcore_twtrcon_ready <= 1'd1;
- end
- end
- end
- litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state;
- litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready));
- litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0;
- litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid));
- litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0;
- litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1;
- litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2;
- litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3;
- litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4;
- litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5;
- litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6;
- litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7;
- litedramcore_state <= litedramcore_next_state;
- if (litedramcore_dat_w_next_value_ce0) begin
- litedramcore_dat_w <= litedramcore_dat_w_next_value0;
- end
- if (litedramcore_adr_next_value_ce1) begin
- litedramcore_adr <= litedramcore_adr_next_value1;
- end
- if (litedramcore_we_next_value_ce2) begin
- litedramcore_we <= litedramcore_we_next_value2;
- end
- interface0_bank_bus_dat_r <= 1'd0;
- if (csrbank0_sel) begin
- case (interface0_bank_bus_adr[8:0])
- 1'd0: begin
- interface0_bank_bus_dat_r <= csrbank0_init_done0_w;
- end
- 1'd1: begin
- interface0_bank_bus_dat_r <= csrbank0_init_error0_w;
- end
- endcase
- end
- if (csrbank0_init_done0_re) begin
- init_done_storage <= csrbank0_init_done0_r;
- end
- init_done_re <= csrbank0_init_done0_re;
- if (csrbank0_init_error0_re) begin
- init_error_storage <= csrbank0_init_error0_r;
- end
- init_error_re <= csrbank0_init_error0_re;
- interface1_bank_bus_dat_r <= 1'd0;
- if (csrbank1_sel) begin
- case (interface1_bank_bus_adr[8:0])
- 1'd0: begin
- interface1_bank_bus_dat_r <= csrbank1_rst0_w;
- end
- 1'd1: begin
- interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w;
- end
- 2'd2: begin
- interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w;
- end
- 2'd3: begin
- interface1_bank_bus_dat_r <= csrbank1_wlevel_en0_w;
- end
- 3'd4: begin
- interface1_bank_bus_dat_r <= a7ddrphy_wlevel_strobe_w;
- end
- 3'd5: begin
- interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_rst_w;
- end
- 3'd6: begin
- interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_inc_w;
- end
- 3'd7: begin
- interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_rst_w;
- end
- 4'd8: begin
- interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_w;
- end
- 4'd9: begin
- interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_rst_w;
- end
- 4'd10: begin
- interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_w;
- end
- 4'd11: begin
- interface1_bank_bus_dat_r <= csrbank1_rdphase0_w;
- end
- 4'd12: begin
- interface1_bank_bus_dat_r <= csrbank1_wrphase0_w;
- end
- endcase
- end
- if (csrbank1_rst0_re) begin
- a7ddrphy_rst_storage <= csrbank1_rst0_r;
- end
- a7ddrphy_rst_re <= csrbank1_rst0_re;
- if (csrbank1_dly_sel0_re) begin
- a7ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r;
- end
- a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re;
- if (csrbank1_half_sys8x_taps0_re) begin
- a7ddrphy_half_sys8x_taps_storage[4:0] <= csrbank1_half_sys8x_taps0_r;
- end
- a7ddrphy_half_sys8x_taps_re <= csrbank1_half_sys8x_taps0_re;
- if (csrbank1_wlevel_en0_re) begin
- a7ddrphy_wlevel_en_storage <= csrbank1_wlevel_en0_r;
- end
- a7ddrphy_wlevel_en_re <= csrbank1_wlevel_en0_re;
- if (csrbank1_rdphase0_re) begin
- a7ddrphy_rdphase_storage[1:0] <= csrbank1_rdphase0_r;
- end
- a7ddrphy_rdphase_re <= csrbank1_rdphase0_re;
- if (csrbank1_wrphase0_re) begin
- a7ddrphy_wrphase_storage[1:0] <= csrbank1_wrphase0_r;
- end
- a7ddrphy_wrphase_re <= csrbank1_wrphase0_re;
- interface2_bank_bus_dat_r <= 1'd0;
- if (csrbank2_sel) begin
- case (interface2_bank_bus_adr[8:0])
- 1'd0: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w;
- end
- 1'd1: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w;
- end
- 2'd2: begin
- interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w;
- end
- 2'd3: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w;
- end
- 3'd4: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w;
- end
- 3'd5: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w;
- end
- 3'd6: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata_w;
- end
- 3'd7: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w;
- end
- 4'd8: begin
- interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w;
- end
- 4'd9: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w;
- end
- 4'd10: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w;
- end
- 4'd11: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w;
- end
- 4'd12: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata_w;
- end
- 4'd13: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w;
- end
- 4'd14: begin
- interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w;
- end
- 4'd15: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w;
- end
- 5'd16: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w;
- end
- 5'd17: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w;
- end
- 5'd18: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata_w;
- end
- 5'd19: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w;
- end
- 5'd20: begin
- interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w;
- end
- 5'd21: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w;
- end
- 5'd22: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w;
- end
- 5'd23: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w;
- end
- 5'd24: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata_w;
- end
- endcase
- end
- if (csrbank2_dfii_control0_re) begin
- litedramcore_storage[3:0] <= csrbank2_dfii_control0_r;
- end
- litedramcore_re <= csrbank2_dfii_control0_re;
- if (csrbank2_dfii_pi0_command0_re) begin
- litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r;
- end
- litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re;
- if (csrbank2_dfii_pi0_address0_re) begin
- litedramcore_phaseinjector0_address_storage[15:0] <= csrbank2_dfii_pi0_address0_r;
- end
- litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re;
- if (csrbank2_dfii_pi0_baddress0_re) begin
- litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r;
- end
- litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re;
- if (csrbank2_dfii_pi0_wrdata0_re) begin
- litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r;
- end
- litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re;
- litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata_re;
- if (csrbank2_dfii_pi1_command0_re) begin
- litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r;
- end
- litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re;
- if (csrbank2_dfii_pi1_address0_re) begin
- litedramcore_phaseinjector1_address_storage[15:0] <= csrbank2_dfii_pi1_address0_r;
- end
- litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re;
- if (csrbank2_dfii_pi1_baddress0_re) begin
- litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r;
- end
- litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re;
- if (csrbank2_dfii_pi1_wrdata0_re) begin
- litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r;
- end
- litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re;
- litedramcore_phaseinjector1_rddata_re <= csrbank2_dfii_pi1_rddata_re;
- if (csrbank2_dfii_pi2_command0_re) begin
- litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r;
- end
- litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re;
- if (csrbank2_dfii_pi2_address0_re) begin
- litedramcore_phaseinjector2_address_storage[15:0] <= csrbank2_dfii_pi2_address0_r;
- end
- litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re;
- if (csrbank2_dfii_pi2_baddress0_re) begin
- litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r;
- end
- litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re;
- if (csrbank2_dfii_pi2_wrdata0_re) begin
- litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r;
- end
- litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re;
- litedramcore_phaseinjector2_rddata_re <= csrbank2_dfii_pi2_rddata_re;
- if (csrbank2_dfii_pi3_command0_re) begin
- litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r;
- end
- litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re;
- if (csrbank2_dfii_pi3_address0_re) begin
- litedramcore_phaseinjector3_address_storage[15:0] <= csrbank2_dfii_pi3_address0_r;
- end
- litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re;
- if (csrbank2_dfii_pi3_baddress0_re) begin
- litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r;
- end
- litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re;
- if (csrbank2_dfii_pi3_wrdata0_re) begin
- litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r;
- end
- litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re;
- litedramcore_phaseinjector3_rddata_re <= csrbank2_dfii_pi3_rddata_re;
- if (sys_rst) begin
- a7ddrphy_rst_storage <= 1'd0;
- a7ddrphy_rst_re <= 1'd0;
- a7ddrphy_dly_sel_storage <= 2'd0;
- a7ddrphy_dly_sel_re <= 1'd0;
- a7ddrphy_half_sys8x_taps_storage <= 5'd8;
- a7ddrphy_half_sys8x_taps_re <= 1'd0;
- a7ddrphy_wlevel_en_storage <= 1'd0;
- a7ddrphy_wlevel_en_re <= 1'd0;
- a7ddrphy_rdphase_storage <= 2'd2;
- a7ddrphy_rdphase_re <= 1'd0;
- a7ddrphy_wrphase_storage <= 2'd3;
- a7ddrphy_wrphase_re <= 1'd0;
- a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
- a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
- a7ddrphy_dqspattern_o1 <= 8'd0;
- a7ddrphy_bitslip0_value0 <= 3'd7;
- a7ddrphy_bitslip1_value0 <= 3'd7;
- a7ddrphy_bitslip0_value1 <= 3'd7;
- a7ddrphy_bitslip1_value1 <= 3'd7;
- a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
- a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
- a7ddrphy_bitslip0_value2 <= 3'd7;
- a7ddrphy_bitslip0_value3 <= 3'd7;
- a7ddrphy_bitslip1_value2 <= 3'd7;
- a7ddrphy_bitslip1_value3 <= 3'd7;
- a7ddrphy_bitslip2_value0 <= 3'd7;
- a7ddrphy_bitslip2_value1 <= 3'd7;
- a7ddrphy_bitslip3_value0 <= 3'd7;
- a7ddrphy_bitslip3_value1 <= 3'd7;
- a7ddrphy_bitslip4_value0 <= 3'd7;
- a7ddrphy_bitslip4_value1 <= 3'd7;
- a7ddrphy_bitslip5_value0 <= 3'd7;
- a7ddrphy_bitslip5_value1 <= 3'd7;
- a7ddrphy_bitslip6_value0 <= 3'd7;
- a7ddrphy_bitslip6_value1 <= 3'd7;
- a7ddrphy_bitslip7_value0 <= 3'd7;
- a7ddrphy_bitslip7_value1 <= 3'd7;
- a7ddrphy_bitslip8_value0 <= 3'd7;
- a7ddrphy_bitslip8_value1 <= 3'd7;
- a7ddrphy_bitslip9_value0 <= 3'd7;
- a7ddrphy_bitslip9_value1 <= 3'd7;
- a7ddrphy_bitslip10_value0 <= 3'd7;
- a7ddrphy_bitslip10_value1 <= 3'd7;
- a7ddrphy_bitslip11_value0 <= 3'd7;
- a7ddrphy_bitslip11_value1 <= 3'd7;
- a7ddrphy_bitslip12_value0 <= 3'd7;
- a7ddrphy_bitslip12_value1 <= 3'd7;
- a7ddrphy_bitslip13_value0 <= 3'd7;
- a7ddrphy_bitslip13_value1 <= 3'd7;
- a7ddrphy_bitslip14_value0 <= 3'd7;
- a7ddrphy_bitslip14_value1 <= 3'd7;
- a7ddrphy_bitslip15_value0 <= 3'd7;
- a7ddrphy_bitslip15_value1 <= 3'd7;
- a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0;
- a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0;
- a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0;
- a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0;
- a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0;
- a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0;
- a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0;
- a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0;
- a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0;
- a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0;
- a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0;
- litedramcore_storage <= 4'd1;
- litedramcore_re <= 1'd0;
- litedramcore_phaseinjector0_command_storage <= 6'd0;
- litedramcore_phaseinjector0_command_re <= 1'd0;
- litedramcore_phaseinjector0_address_re <= 1'd0;
- litedramcore_phaseinjector0_baddress_re <= 1'd0;
- litedramcore_phaseinjector0_wrdata_re <= 1'd0;
- litedramcore_phaseinjector0_rddata_status <= 32'd0;
- litedramcore_phaseinjector0_rddata_re <= 1'd0;
- litedramcore_phaseinjector1_command_storage <= 6'd0;
- litedramcore_phaseinjector1_command_re <= 1'd0;
- litedramcore_phaseinjector1_address_re <= 1'd0;
- litedramcore_phaseinjector1_baddress_re <= 1'd0;
- litedramcore_phaseinjector1_wrdata_re <= 1'd0;
- litedramcore_phaseinjector1_rddata_status <= 32'd0;
- litedramcore_phaseinjector1_rddata_re <= 1'd0;
- litedramcore_phaseinjector2_command_storage <= 6'd0;
- litedramcore_phaseinjector2_command_re <= 1'd0;
- litedramcore_phaseinjector2_address_re <= 1'd0;
- litedramcore_phaseinjector2_baddress_re <= 1'd0;
- litedramcore_phaseinjector2_wrdata_re <= 1'd0;
- litedramcore_phaseinjector2_rddata_status <= 32'd0;
- litedramcore_phaseinjector2_rddata_re <= 1'd0;
- litedramcore_phaseinjector3_command_storage <= 6'd0;
- litedramcore_phaseinjector3_command_re <= 1'd0;
- litedramcore_phaseinjector3_address_re <= 1'd0;
- litedramcore_phaseinjector3_baddress_re <= 1'd0;
- litedramcore_phaseinjector3_wrdata_re <= 1'd0;
- litedramcore_phaseinjector3_rddata_status <= 32'd0;
- litedramcore_phaseinjector3_rddata_re <= 1'd0;
- litedramcore_dfi_p0_address <= 16'd0;
- litedramcore_dfi_p0_bank <= 3'd0;
- litedramcore_dfi_p0_cas_n <= 1'd1;
- litedramcore_dfi_p0_cs_n <= 1'd1;
- litedramcore_dfi_p0_ras_n <= 1'd1;
- litedramcore_dfi_p0_we_n <= 1'd1;
- litedramcore_dfi_p0_wrdata_en <= 1'd0;
- litedramcore_dfi_p0_rddata_en <= 1'd0;
- litedramcore_dfi_p1_address <= 16'd0;
- litedramcore_dfi_p1_bank <= 3'd0;
- litedramcore_dfi_p1_cas_n <= 1'd1;
- litedramcore_dfi_p1_cs_n <= 1'd1;
- litedramcore_dfi_p1_ras_n <= 1'd1;
- litedramcore_dfi_p1_we_n <= 1'd1;
- litedramcore_dfi_p1_wrdata_en <= 1'd0;
- litedramcore_dfi_p1_rddata_en <= 1'd0;
- litedramcore_dfi_p2_address <= 16'd0;
- litedramcore_dfi_p2_bank <= 3'd0;
- litedramcore_dfi_p2_cas_n <= 1'd1;
- litedramcore_dfi_p2_cs_n <= 1'd1;
- litedramcore_dfi_p2_ras_n <= 1'd1;
- litedramcore_dfi_p2_we_n <= 1'd1;
- litedramcore_dfi_p2_wrdata_en <= 1'd0;
- litedramcore_dfi_p2_rddata_en <= 1'd0;
- litedramcore_dfi_p3_address <= 16'd0;
- litedramcore_dfi_p3_bank <= 3'd0;
- litedramcore_dfi_p3_cas_n <= 1'd1;
- litedramcore_dfi_p3_cs_n <= 1'd1;
- litedramcore_dfi_p3_ras_n <= 1'd1;
- litedramcore_dfi_p3_we_n <= 1'd1;
- litedramcore_dfi_p3_wrdata_en <= 1'd0;
- litedramcore_dfi_p3_rddata_en <= 1'd0;
- litedramcore_cmd_payload_a <= 16'd0;
- litedramcore_cmd_payload_ba <= 3'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd0;
- litedramcore_cmd_payload_we <= 1'd0;
- litedramcore_timer_count1 <= 10'd781;
- litedramcore_postponer_req_o <= 1'd0;
- litedramcore_postponer_count <= 1'd0;
- litedramcore_sequencer_done1 <= 1'd0;
- litedramcore_sequencer_counter <= 7'd0;
- litedramcore_sequencer_count <= 1'd0;
- litedramcore_zqcs_timer_count1 <= 27'd99999999;
- litedramcore_zqcs_executer_done <= 1'd0;
- litedramcore_zqcs_executer_counter <= 5'd0;
- litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine0_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= 23'd0;
- litedramcore_bankmachine0_row <= 16'd0;
- litedramcore_bankmachine0_row_opened <= 1'd0;
- litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine0_twtpcon_count <= 3'd0;
- litedramcore_bankmachine0_trccon_ready <= 1'd0;
- litedramcore_bankmachine0_trccon_count <= 3'd0;
- litedramcore_bankmachine0_trascon_ready <= 1'd0;
- litedramcore_bankmachine0_trascon_count <= 3'd0;
- litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine1_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= 23'd0;
- litedramcore_bankmachine1_row <= 16'd0;
- litedramcore_bankmachine1_row_opened <= 1'd0;
- litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine1_twtpcon_count <= 3'd0;
- litedramcore_bankmachine1_trccon_ready <= 1'd0;
- litedramcore_bankmachine1_trccon_count <= 3'd0;
- litedramcore_bankmachine1_trascon_ready <= 1'd0;
- litedramcore_bankmachine1_trascon_count <= 3'd0;
- litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine2_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= 23'd0;
- litedramcore_bankmachine2_row <= 16'd0;
- litedramcore_bankmachine2_row_opened <= 1'd0;
- litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine2_twtpcon_count <= 3'd0;
- litedramcore_bankmachine2_trccon_ready <= 1'd0;
- litedramcore_bankmachine2_trccon_count <= 3'd0;
- litedramcore_bankmachine2_trascon_ready <= 1'd0;
- litedramcore_bankmachine2_trascon_count <= 3'd0;
- litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine3_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= 23'd0;
- litedramcore_bankmachine3_row <= 16'd0;
- litedramcore_bankmachine3_row_opened <= 1'd0;
- litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine3_twtpcon_count <= 3'd0;
- litedramcore_bankmachine3_trccon_ready <= 1'd0;
- litedramcore_bankmachine3_trccon_count <= 3'd0;
- litedramcore_bankmachine3_trascon_ready <= 1'd0;
- litedramcore_bankmachine3_trascon_count <= 3'd0;
- litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine4_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= 23'd0;
- litedramcore_bankmachine4_row <= 16'd0;
- litedramcore_bankmachine4_row_opened <= 1'd0;
- litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine4_twtpcon_count <= 3'd0;
- litedramcore_bankmachine4_trccon_ready <= 1'd0;
- litedramcore_bankmachine4_trccon_count <= 3'd0;
- litedramcore_bankmachine4_trascon_ready <= 1'd0;
- litedramcore_bankmachine4_trascon_count <= 3'd0;
- litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine5_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= 23'd0;
- litedramcore_bankmachine5_row <= 16'd0;
- litedramcore_bankmachine5_row_opened <= 1'd0;
- litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine5_twtpcon_count <= 3'd0;
- litedramcore_bankmachine5_trccon_ready <= 1'd0;
- litedramcore_bankmachine5_trccon_count <= 3'd0;
- litedramcore_bankmachine5_trascon_ready <= 1'd0;
- litedramcore_bankmachine5_trascon_count <= 3'd0;
- litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine6_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= 23'd0;
- litedramcore_bankmachine6_row <= 16'd0;
- litedramcore_bankmachine6_row_opened <= 1'd0;
- litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine6_twtpcon_count <= 3'd0;
- litedramcore_bankmachine6_trccon_ready <= 1'd0;
- litedramcore_bankmachine6_trccon_count <= 3'd0;
- litedramcore_bankmachine6_trascon_ready <= 1'd0;
- litedramcore_bankmachine6_trascon_count <= 3'd0;
- litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine7_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= 23'd0;
- litedramcore_bankmachine7_row <= 16'd0;
- litedramcore_bankmachine7_row_opened <= 1'd0;
- litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine7_twtpcon_count <= 3'd0;
- litedramcore_bankmachine7_trccon_ready <= 1'd0;
- litedramcore_bankmachine7_trccon_count <= 3'd0;
- litedramcore_bankmachine7_trascon_ready <= 1'd0;
- litedramcore_bankmachine7_trascon_count <= 3'd0;
- litedramcore_choose_cmd_grant <= 3'd0;
- litedramcore_choose_req_grant <= 3'd0;
- litedramcore_trrdcon_ready <= 1'd0;
- litedramcore_trrdcon_count <= 1'd0;
- litedramcore_tfawcon_ready <= 1'd1;
- litedramcore_tfawcon_window <= 5'd0;
- litedramcore_tccdcon_ready <= 1'd0;
- litedramcore_tccdcon_count <= 1'd0;
- litedramcore_twtrcon_ready <= 1'd0;
- litedramcore_twtrcon_count <= 3'd0;
- litedramcore_time0 <= 5'd0;
- litedramcore_time1 <= 4'd0;
- init_done_storage <= 1'd0;
- init_done_re <= 1'd0;
- init_error_storage <= 1'd0;
- init_error_re <= 1'd0;
- litedramcore_we <= 1'd0;
- litedramcore_refresher_state <= 2'd0;
- litedramcore_bankmachine0_state <= 4'd0;
- litedramcore_bankmachine1_state <= 4'd0;
- litedramcore_bankmachine2_state <= 4'd0;
- litedramcore_bankmachine3_state <= 4'd0;
- litedramcore_bankmachine4_state <= 4'd0;
- litedramcore_bankmachine5_state <= 4'd0;
- litedramcore_bankmachine6_state <= 4'd0;
- litedramcore_bankmachine7_state <= 4'd0;
- litedramcore_multiplexer_state <= 4'd0;
- litedramcore_new_master_wdata_ready0 <= 1'd0;
- litedramcore_new_master_wdata_ready1 <= 1'd0;
- litedramcore_new_master_rdata_valid0 <= 1'd0;
- litedramcore_new_master_rdata_valid1 <= 1'd0;
- litedramcore_new_master_rdata_valid2 <= 1'd0;
- litedramcore_new_master_rdata_valid3 <= 1'd0;
- litedramcore_new_master_rdata_valid4 <= 1'd0;
- litedramcore_new_master_rdata_valid5 <= 1'd0;
- litedramcore_new_master_rdata_valid6 <= 1'd0;
- litedramcore_new_master_rdata_valid7 <= 1'd0;
- litedramcore_new_master_rdata_valid8 <= 1'd0;
- litedramcore_state <= 2'd0;
- end
+ a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dqs_oe_delay_tappeddelayline;
+ a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0;
+ a7ddrphy_dqspattern_o1 <= a7ddrphy_dqspattern_o0;
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip0_value0 <= (a7ddrphy_bitslip0_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip0_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip0_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip0_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip1_value0 <= (a7ddrphy_bitslip1_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip1_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip1_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip1_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip0_value1 <= (a7ddrphy_bitslip0_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip0_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip0_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[2], a7ddrphy_dfi_p3_wrdata_mask[0], a7ddrphy_dfi_p2_wrdata_mask[2], a7ddrphy_dfi_p2_wrdata_mask[0], a7ddrphy_dfi_p1_wrdata_mask[2], a7ddrphy_dfi_p1_wrdata_mask[0], a7ddrphy_dfi_p0_wrdata_mask[2], a7ddrphy_dfi_p0_wrdata_mask[0]}, a7ddrphy_bitslip0_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip1_value1 <= (a7ddrphy_bitslip1_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip1_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip1_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[3], a7ddrphy_dfi_p3_wrdata_mask[1], a7ddrphy_dfi_p2_wrdata_mask[3], a7ddrphy_dfi_p2_wrdata_mask[1], a7ddrphy_dfi_p1_wrdata_mask[3], a7ddrphy_dfi_p1_wrdata_mask[1], a7ddrphy_dfi_p0_wrdata_mask[3], a7ddrphy_dfi_p0_wrdata_mask[1]}, a7ddrphy_bitslip1_r1[15:8]};
+ a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dq_oe_delay_tappeddelayline;
+ a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0;
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip0_value2 <= (a7ddrphy_bitslip0_value2 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip0_value2 <= 3'd7;
+ end
+ a7ddrphy_bitslip0_r2 <= {{a7ddrphy_dfi_p3_wrdata[16], a7ddrphy_dfi_p3_wrdata[0], a7ddrphy_dfi_p2_wrdata[16], a7ddrphy_dfi_p2_wrdata[0], a7ddrphy_dfi_p1_wrdata[16], a7ddrphy_dfi_p1_wrdata[0], a7ddrphy_dfi_p0_wrdata[16], a7ddrphy_dfi_p0_wrdata[0]}, a7ddrphy_bitslip0_r2[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip0_value3 <= (a7ddrphy_bitslip0_value3 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip0_value3 <= 3'd7;
+ end
+ a7ddrphy_bitslip0_r3 <= {a7ddrphy_bitslip03, a7ddrphy_bitslip0_r3[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip1_value2 <= (a7ddrphy_bitslip1_value2 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip1_value2 <= 3'd7;
+ end
+ a7ddrphy_bitslip1_r2 <= {{a7ddrphy_dfi_p3_wrdata[17], a7ddrphy_dfi_p3_wrdata[1], a7ddrphy_dfi_p2_wrdata[17], a7ddrphy_dfi_p2_wrdata[1], a7ddrphy_dfi_p1_wrdata[17], a7ddrphy_dfi_p1_wrdata[1], a7ddrphy_dfi_p0_wrdata[17], a7ddrphy_dfi_p0_wrdata[1]}, a7ddrphy_bitslip1_r2[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip1_value3 <= (a7ddrphy_bitslip1_value3 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip1_value3 <= 3'd7;
+ end
+ a7ddrphy_bitslip1_r3 <= {a7ddrphy_bitslip13, a7ddrphy_bitslip1_r3[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip2_value0 <= (a7ddrphy_bitslip2_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip2_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip2_r0 <= {{a7ddrphy_dfi_p3_wrdata[18], a7ddrphy_dfi_p3_wrdata[2], a7ddrphy_dfi_p2_wrdata[18], a7ddrphy_dfi_p2_wrdata[2], a7ddrphy_dfi_p1_wrdata[18], a7ddrphy_dfi_p1_wrdata[2], a7ddrphy_dfi_p0_wrdata[18], a7ddrphy_dfi_p0_wrdata[2]}, a7ddrphy_bitslip2_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip2_value1 <= (a7ddrphy_bitslip2_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip2_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip2_r1 <= {a7ddrphy_bitslip21, a7ddrphy_bitslip2_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip3_value0 <= (a7ddrphy_bitslip3_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip3_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip3_r0 <= {{a7ddrphy_dfi_p3_wrdata[19], a7ddrphy_dfi_p3_wrdata[3], a7ddrphy_dfi_p2_wrdata[19], a7ddrphy_dfi_p2_wrdata[3], a7ddrphy_dfi_p1_wrdata[19], a7ddrphy_dfi_p1_wrdata[3], a7ddrphy_dfi_p0_wrdata[19], a7ddrphy_dfi_p0_wrdata[3]}, a7ddrphy_bitslip3_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip3_value1 <= (a7ddrphy_bitslip3_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip3_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip3_r1 <= {a7ddrphy_bitslip31, a7ddrphy_bitslip3_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip4_value0 <= (a7ddrphy_bitslip4_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip4_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip4_r0 <= {{a7ddrphy_dfi_p3_wrdata[20], a7ddrphy_dfi_p3_wrdata[4], a7ddrphy_dfi_p2_wrdata[20], a7ddrphy_dfi_p2_wrdata[4], a7ddrphy_dfi_p1_wrdata[20], a7ddrphy_dfi_p1_wrdata[4], a7ddrphy_dfi_p0_wrdata[20], a7ddrphy_dfi_p0_wrdata[4]}, a7ddrphy_bitslip4_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip4_value1 <= (a7ddrphy_bitslip4_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip4_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip4_r1 <= {a7ddrphy_bitslip41, a7ddrphy_bitslip4_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip5_value0 <= (a7ddrphy_bitslip5_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip5_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip5_r0 <= {{a7ddrphy_dfi_p3_wrdata[21], a7ddrphy_dfi_p3_wrdata[5], a7ddrphy_dfi_p2_wrdata[21], a7ddrphy_dfi_p2_wrdata[5], a7ddrphy_dfi_p1_wrdata[21], a7ddrphy_dfi_p1_wrdata[5], a7ddrphy_dfi_p0_wrdata[21], a7ddrphy_dfi_p0_wrdata[5]}, a7ddrphy_bitslip5_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip5_value1 <= (a7ddrphy_bitslip5_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip5_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip5_r1 <= {a7ddrphy_bitslip51, a7ddrphy_bitslip5_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip6_value0 <= (a7ddrphy_bitslip6_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip6_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip6_r0 <= {{a7ddrphy_dfi_p3_wrdata[22], a7ddrphy_dfi_p3_wrdata[6], a7ddrphy_dfi_p2_wrdata[22], a7ddrphy_dfi_p2_wrdata[6], a7ddrphy_dfi_p1_wrdata[22], a7ddrphy_dfi_p1_wrdata[6], a7ddrphy_dfi_p0_wrdata[22], a7ddrphy_dfi_p0_wrdata[6]}, a7ddrphy_bitslip6_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip6_value1 <= (a7ddrphy_bitslip6_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip6_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip6_r1 <= {a7ddrphy_bitslip61, a7ddrphy_bitslip6_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip7_value0 <= (a7ddrphy_bitslip7_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip7_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip7_r0 <= {{a7ddrphy_dfi_p3_wrdata[23], a7ddrphy_dfi_p3_wrdata[7], a7ddrphy_dfi_p2_wrdata[23], a7ddrphy_dfi_p2_wrdata[7], a7ddrphy_dfi_p1_wrdata[23], a7ddrphy_dfi_p1_wrdata[7], a7ddrphy_dfi_p0_wrdata[23], a7ddrphy_dfi_p0_wrdata[7]}, a7ddrphy_bitslip7_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip7_value1 <= (a7ddrphy_bitslip7_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip7_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip7_r1 <= {a7ddrphy_bitslip71, a7ddrphy_bitslip7_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip8_value0 <= (a7ddrphy_bitslip8_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip8_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip8_r0 <= {{a7ddrphy_dfi_p3_wrdata[24], a7ddrphy_dfi_p3_wrdata[8], a7ddrphy_dfi_p2_wrdata[24], a7ddrphy_dfi_p2_wrdata[8], a7ddrphy_dfi_p1_wrdata[24], a7ddrphy_dfi_p1_wrdata[8], a7ddrphy_dfi_p0_wrdata[24], a7ddrphy_dfi_p0_wrdata[8]}, a7ddrphy_bitslip8_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip8_value1 <= (a7ddrphy_bitslip8_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip8_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip8_r1 <= {a7ddrphy_bitslip81, a7ddrphy_bitslip8_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip9_value0 <= (a7ddrphy_bitslip9_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip9_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip9_r0 <= {{a7ddrphy_dfi_p3_wrdata[25], a7ddrphy_dfi_p3_wrdata[9], a7ddrphy_dfi_p2_wrdata[25], a7ddrphy_dfi_p2_wrdata[9], a7ddrphy_dfi_p1_wrdata[25], a7ddrphy_dfi_p1_wrdata[9], a7ddrphy_dfi_p0_wrdata[25], a7ddrphy_dfi_p0_wrdata[9]}, a7ddrphy_bitslip9_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip9_value1 <= (a7ddrphy_bitslip9_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip9_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip9_r1 <= {a7ddrphy_bitslip91, a7ddrphy_bitslip9_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip10_value0 <= (a7ddrphy_bitslip10_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip10_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip10_r0 <= {{a7ddrphy_dfi_p3_wrdata[26], a7ddrphy_dfi_p3_wrdata[10], a7ddrphy_dfi_p2_wrdata[26], a7ddrphy_dfi_p2_wrdata[10], a7ddrphy_dfi_p1_wrdata[26], a7ddrphy_dfi_p1_wrdata[10], a7ddrphy_dfi_p0_wrdata[26], a7ddrphy_dfi_p0_wrdata[10]}, a7ddrphy_bitslip10_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip10_value1 <= (a7ddrphy_bitslip10_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip10_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip10_r1 <= {a7ddrphy_bitslip101, a7ddrphy_bitslip10_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip11_value0 <= (a7ddrphy_bitslip11_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip11_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip11_r0 <= {{a7ddrphy_dfi_p3_wrdata[27], a7ddrphy_dfi_p3_wrdata[11], a7ddrphy_dfi_p2_wrdata[27], a7ddrphy_dfi_p2_wrdata[11], a7ddrphy_dfi_p1_wrdata[27], a7ddrphy_dfi_p1_wrdata[11], a7ddrphy_dfi_p0_wrdata[27], a7ddrphy_dfi_p0_wrdata[11]}, a7ddrphy_bitslip11_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip11_value1 <= (a7ddrphy_bitslip11_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip11_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip11_r1 <= {a7ddrphy_bitslip111, a7ddrphy_bitslip11_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip12_value0 <= (a7ddrphy_bitslip12_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip12_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip12_r0 <= {{a7ddrphy_dfi_p3_wrdata[28], a7ddrphy_dfi_p3_wrdata[12], a7ddrphy_dfi_p2_wrdata[28], a7ddrphy_dfi_p2_wrdata[12], a7ddrphy_dfi_p1_wrdata[28], a7ddrphy_dfi_p1_wrdata[12], a7ddrphy_dfi_p0_wrdata[28], a7ddrphy_dfi_p0_wrdata[12]}, a7ddrphy_bitslip12_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip12_value1 <= (a7ddrphy_bitslip12_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip12_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip12_r1 <= {a7ddrphy_bitslip121, a7ddrphy_bitslip12_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip13_value0 <= (a7ddrphy_bitslip13_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip13_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip13_r0 <= {{a7ddrphy_dfi_p3_wrdata[29], a7ddrphy_dfi_p3_wrdata[13], a7ddrphy_dfi_p2_wrdata[29], a7ddrphy_dfi_p2_wrdata[13], a7ddrphy_dfi_p1_wrdata[29], a7ddrphy_dfi_p1_wrdata[13], a7ddrphy_dfi_p0_wrdata[29], a7ddrphy_dfi_p0_wrdata[13]}, a7ddrphy_bitslip13_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip13_value1 <= (a7ddrphy_bitslip13_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip13_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip13_r1 <= {a7ddrphy_bitslip131, a7ddrphy_bitslip13_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip14_value0 <= (a7ddrphy_bitslip14_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip14_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip14_r0 <= {{a7ddrphy_dfi_p3_wrdata[30], a7ddrphy_dfi_p3_wrdata[14], a7ddrphy_dfi_p2_wrdata[30], a7ddrphy_dfi_p2_wrdata[14], a7ddrphy_dfi_p1_wrdata[30], a7ddrphy_dfi_p1_wrdata[14], a7ddrphy_dfi_p0_wrdata[30], a7ddrphy_dfi_p0_wrdata[14]}, a7ddrphy_bitslip14_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip14_value1 <= (a7ddrphy_bitslip14_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip14_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip14_r1 <= {a7ddrphy_bitslip141, a7ddrphy_bitslip14_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip15_value0 <= (a7ddrphy_bitslip15_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip15_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip15_r0 <= {{a7ddrphy_dfi_p3_wrdata[31], a7ddrphy_dfi_p3_wrdata[15], a7ddrphy_dfi_p2_wrdata[31], a7ddrphy_dfi_p2_wrdata[15], a7ddrphy_dfi_p1_wrdata[31], a7ddrphy_dfi_p1_wrdata[15], a7ddrphy_dfi_p0_wrdata[31], a7ddrphy_dfi_p0_wrdata[15]}, a7ddrphy_bitslip15_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip15_value1 <= (a7ddrphy_bitslip15_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip15_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip15_r1 <= {a7ddrphy_bitslip151, a7ddrphy_bitslip15_r1[15:8]};
+ a7ddrphy_rddata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_rddata_en | a7ddrphy_dfi_p1_rddata_en) | a7ddrphy_dfi_p2_rddata_en) | a7ddrphy_dfi_p3_rddata_en);
+ a7ddrphy_rddata_en_tappeddelayline1 <= a7ddrphy_rddata_en_tappeddelayline0;
+ a7ddrphy_rddata_en_tappeddelayline2 <= a7ddrphy_rddata_en_tappeddelayline1;
+ a7ddrphy_rddata_en_tappeddelayline3 <= a7ddrphy_rddata_en_tappeddelayline2;
+ a7ddrphy_rddata_en_tappeddelayline4 <= a7ddrphy_rddata_en_tappeddelayline3;
+ a7ddrphy_rddata_en_tappeddelayline5 <= a7ddrphy_rddata_en_tappeddelayline4;
+ a7ddrphy_rddata_en_tappeddelayline6 <= a7ddrphy_rddata_en_tappeddelayline5;
+ a7ddrphy_rddata_en_tappeddelayline7 <= a7ddrphy_rddata_en_tappeddelayline6;
+ a7ddrphy_wrdata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_wrdata_en | a7ddrphy_dfi_p1_wrdata_en) | a7ddrphy_dfi_p2_wrdata_en) | a7ddrphy_dfi_p3_wrdata_en);
+ a7ddrphy_wrdata_en_tappeddelayline1 <= a7ddrphy_wrdata_en_tappeddelayline0;
+ a7ddrphy_wrdata_en_tappeddelayline2 <= a7ddrphy_wrdata_en_tappeddelayline1;
+ if (litedramcore_csr_dfi_p0_rddata_valid) begin
+ litedramcore_phaseinjector0_rddata_status <= litedramcore_csr_dfi_p0_rddata;
+ end
+ if (litedramcore_csr_dfi_p1_rddata_valid) begin
+ litedramcore_phaseinjector1_rddata_status <= litedramcore_csr_dfi_p1_rddata;
+ end
+ if (litedramcore_csr_dfi_p2_rddata_valid) begin
+ litedramcore_phaseinjector2_rddata_status <= litedramcore_csr_dfi_p2_rddata;
+ end
+ if (litedramcore_csr_dfi_p3_rddata_valid) begin
+ litedramcore_phaseinjector3_rddata_status <= litedramcore_csr_dfi_p3_rddata;
+ end
+ if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin
+ litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1);
+ end else begin
+ litedramcore_timer_count1 <= 10'd781;
+ end
+ litedramcore_postponer_req_o <= 1'd0;
+ if (litedramcore_postponer_req_i) begin
+ litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1);
+ if ((litedramcore_postponer_count == 1'd0)) begin
+ litedramcore_postponer_count <= 1'd0;
+ litedramcore_postponer_req_o <= 1'd1;
+ end
+ end
+ if (litedramcore_sequencer_start0) begin
+ litedramcore_sequencer_count <= 1'd0;
+ end else begin
+ if (litedramcore_sequencer_done1) begin
+ if ((litedramcore_sequencer_count != 1'd0)) begin
+ litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1);
+ end
+ end
+ end
+ litedramcore_cmd_payload_a <= 1'd0;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd0;
+ litedramcore_cmd_payload_we <= 1'd0;
+ litedramcore_sequencer_done1 <= 1'd0;
+ if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin
+ litedramcore_cmd_payload_a <= 11'd1024;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd1;
+ litedramcore_cmd_payload_we <= 1'd1;
+ end
+ if ((litedramcore_sequencer_counter == 2'd3)) begin
+ litedramcore_cmd_payload_a <= 11'd1024;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd1;
+ litedramcore_cmd_payload_ras <= 1'd1;
+ litedramcore_cmd_payload_we <= 1'd0;
+ end
+ if ((litedramcore_sequencer_counter == 7'd73)) begin
+ litedramcore_cmd_payload_a <= 1'd0;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd0;
+ litedramcore_cmd_payload_we <= 1'd0;
+ litedramcore_sequencer_done1 <= 1'd1;
+ end
+ if ((litedramcore_sequencer_counter == 7'd73)) begin
+ litedramcore_sequencer_counter <= 1'd0;
+ end else begin
+ if ((litedramcore_sequencer_counter != 1'd0)) begin
+ litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1);
+ end else begin
+ if (litedramcore_sequencer_start1) begin
+ litedramcore_sequencer_counter <= 1'd1;
+ end
+ end
+ end
+ if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin
+ litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1);
+ end else begin
+ litedramcore_zqcs_timer_count1 <= 27'd99999999;
+ end
+ litedramcore_zqcs_executer_done <= 1'd0;
+ if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin
+ litedramcore_cmd_payload_a <= 11'd1024;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd1;
+ litedramcore_cmd_payload_we <= 1'd1;
+ end
+ if ((litedramcore_zqcs_executer_counter == 2'd3)) begin
+ litedramcore_cmd_payload_a <= 1'd0;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd0;
+ litedramcore_cmd_payload_we <= 1'd1;
+ end
+ if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
+ litedramcore_cmd_payload_a <= 1'd0;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd0;
+ litedramcore_cmd_payload_we <= 1'd0;
+ litedramcore_zqcs_executer_done <= 1'd1;
+ end
+ if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
+ litedramcore_zqcs_executer_counter <= 1'd0;
+ end else begin
+ if ((litedramcore_zqcs_executer_counter != 1'd0)) begin
+ litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1);
+ end else begin
+ if (litedramcore_zqcs_executer_start) begin
+ litedramcore_zqcs_executer_counter <= 1'd1;
+ end
+ end
+ end
+ litedramcore_refresher_state <= litedramcore_refresher_next_state;
+ if (litedramcore_bankmachine0_row_close) begin
+ litedramcore_bankmachine0_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine0_row_open) begin
+ litedramcore_bankmachine0_row_opened <= 1'd1;
+ litedramcore_bankmachine0_row <= litedramcore_bankmachine0_source_source_payload_addr[22:7];
+ end
+ end
+ if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin
+ litedramcore_bankmachine0_produce <= (litedramcore_bankmachine0_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine0_do_read) begin
+ litedramcore_bankmachine0_consume <= (litedramcore_bankmachine0_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin
+ if ((~litedramcore_bankmachine0_do_read)) begin
+ litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine0_do_read) begin
+ litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine0_pipe_valid_source_valid <= litedramcore_bankmachine0_pipe_valid_sink_valid;
+ litedramcore_bankmachine0_pipe_valid_source_first <= litedramcore_bankmachine0_pipe_valid_sink_first;
+ litedramcore_bankmachine0_pipe_valid_source_last <= litedramcore_bankmachine0_pipe_valid_sink_last;
+ litedramcore_bankmachine0_pipe_valid_source_payload_we <= litedramcore_bankmachine0_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine0_pipe_valid_source_payload_addr <= litedramcore_bankmachine0_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine0_twtpcon_valid) begin
+ litedramcore_bankmachine0_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine0_twtpcon_ready)) begin
+ litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine0_trccon_valid) begin
+ litedramcore_bankmachine0_trccon_count <= 3'd6;
+ if (1'd0) begin
+ litedramcore_bankmachine0_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine0_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine0_trccon_ready)) begin
+ litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine0_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine0_trascon_valid) begin
+ litedramcore_bankmachine0_trascon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_bankmachine0_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine0_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine0_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state;
+ if (litedramcore_bankmachine1_row_close) begin
+ litedramcore_bankmachine1_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine1_row_open) begin
+ litedramcore_bankmachine1_row_opened <= 1'd1;
+ litedramcore_bankmachine1_row <= litedramcore_bankmachine1_source_source_payload_addr[22:7];
+ end
+ end
+ if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin
+ litedramcore_bankmachine1_produce <= (litedramcore_bankmachine1_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine1_do_read) begin
+ litedramcore_bankmachine1_consume <= (litedramcore_bankmachine1_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin
+ if ((~litedramcore_bankmachine1_do_read)) begin
+ litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine1_do_read) begin
+ litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine1_pipe_valid_source_valid <= litedramcore_bankmachine1_pipe_valid_sink_valid;
+ litedramcore_bankmachine1_pipe_valid_source_first <= litedramcore_bankmachine1_pipe_valid_sink_first;
+ litedramcore_bankmachine1_pipe_valid_source_last <= litedramcore_bankmachine1_pipe_valid_sink_last;
+ litedramcore_bankmachine1_pipe_valid_source_payload_we <= litedramcore_bankmachine1_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine1_pipe_valid_source_payload_addr <= litedramcore_bankmachine1_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine1_twtpcon_valid) begin
+ litedramcore_bankmachine1_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine1_twtpcon_ready)) begin
+ litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine1_trccon_valid) begin
+ litedramcore_bankmachine1_trccon_count <= 3'd6;
+ if (1'd0) begin
+ litedramcore_bankmachine1_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine1_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine1_trccon_ready)) begin
+ litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine1_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine1_trascon_valid) begin
+ litedramcore_bankmachine1_trascon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_bankmachine1_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine1_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine1_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state;
+ if (litedramcore_bankmachine2_row_close) begin
+ litedramcore_bankmachine2_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine2_row_open) begin
+ litedramcore_bankmachine2_row_opened <= 1'd1;
+ litedramcore_bankmachine2_row <= litedramcore_bankmachine2_source_source_payload_addr[22:7];
+ end
+ end
+ if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin
+ litedramcore_bankmachine2_produce <= (litedramcore_bankmachine2_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine2_do_read) begin
+ litedramcore_bankmachine2_consume <= (litedramcore_bankmachine2_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin
+ if ((~litedramcore_bankmachine2_do_read)) begin
+ litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine2_do_read) begin
+ litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine2_pipe_valid_source_valid <= litedramcore_bankmachine2_pipe_valid_sink_valid;
+ litedramcore_bankmachine2_pipe_valid_source_first <= litedramcore_bankmachine2_pipe_valid_sink_first;
+ litedramcore_bankmachine2_pipe_valid_source_last <= litedramcore_bankmachine2_pipe_valid_sink_last;
+ litedramcore_bankmachine2_pipe_valid_source_payload_we <= litedramcore_bankmachine2_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine2_pipe_valid_source_payload_addr <= litedramcore_bankmachine2_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine2_twtpcon_valid) begin
+ litedramcore_bankmachine2_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine2_twtpcon_ready)) begin
+ litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine2_trccon_valid) begin
+ litedramcore_bankmachine2_trccon_count <= 3'd6;
+ if (1'd0) begin
+ litedramcore_bankmachine2_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine2_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine2_trccon_ready)) begin
+ litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine2_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine2_trascon_valid) begin
+ litedramcore_bankmachine2_trascon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_bankmachine2_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine2_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine2_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state;
+ if (litedramcore_bankmachine3_row_close) begin
+ litedramcore_bankmachine3_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine3_row_open) begin
+ litedramcore_bankmachine3_row_opened <= 1'd1;
+ litedramcore_bankmachine3_row <= litedramcore_bankmachine3_source_source_payload_addr[22:7];
+ end
+ end
+ if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin
+ litedramcore_bankmachine3_produce <= (litedramcore_bankmachine3_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine3_do_read) begin
+ litedramcore_bankmachine3_consume <= (litedramcore_bankmachine3_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin
+ if ((~litedramcore_bankmachine3_do_read)) begin
+ litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine3_do_read) begin
+ litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine3_pipe_valid_source_valid <= litedramcore_bankmachine3_pipe_valid_sink_valid;
+ litedramcore_bankmachine3_pipe_valid_source_first <= litedramcore_bankmachine3_pipe_valid_sink_first;
+ litedramcore_bankmachine3_pipe_valid_source_last <= litedramcore_bankmachine3_pipe_valid_sink_last;
+ litedramcore_bankmachine3_pipe_valid_source_payload_we <= litedramcore_bankmachine3_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine3_pipe_valid_source_payload_addr <= litedramcore_bankmachine3_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine3_twtpcon_valid) begin
+ litedramcore_bankmachine3_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine3_twtpcon_ready)) begin
+ litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine3_trccon_valid) begin
+ litedramcore_bankmachine3_trccon_count <= 3'd6;
+ if (1'd0) begin
+ litedramcore_bankmachine3_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine3_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine3_trccon_ready)) begin
+ litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine3_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine3_trascon_valid) begin
+ litedramcore_bankmachine3_trascon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_bankmachine3_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine3_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine3_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state;
+ if (litedramcore_bankmachine4_row_close) begin
+ litedramcore_bankmachine4_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine4_row_open) begin
+ litedramcore_bankmachine4_row_opened <= 1'd1;
+ litedramcore_bankmachine4_row <= litedramcore_bankmachine4_source_source_payload_addr[22:7];
+ end
+ end
+ if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin
+ litedramcore_bankmachine4_produce <= (litedramcore_bankmachine4_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine4_do_read) begin
+ litedramcore_bankmachine4_consume <= (litedramcore_bankmachine4_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin
+ if ((~litedramcore_bankmachine4_do_read)) begin
+ litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine4_do_read) begin
+ litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine4_pipe_valid_source_valid <= litedramcore_bankmachine4_pipe_valid_sink_valid;
+ litedramcore_bankmachine4_pipe_valid_source_first <= litedramcore_bankmachine4_pipe_valid_sink_first;
+ litedramcore_bankmachine4_pipe_valid_source_last <= litedramcore_bankmachine4_pipe_valid_sink_last;
+ litedramcore_bankmachine4_pipe_valid_source_payload_we <= litedramcore_bankmachine4_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine4_pipe_valid_source_payload_addr <= litedramcore_bankmachine4_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine4_twtpcon_valid) begin
+ litedramcore_bankmachine4_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine4_twtpcon_ready)) begin
+ litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine4_trccon_valid) begin
+ litedramcore_bankmachine4_trccon_count <= 3'd6;
+ if (1'd0) begin
+ litedramcore_bankmachine4_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine4_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine4_trccon_ready)) begin
+ litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine4_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine4_trascon_valid) begin
+ litedramcore_bankmachine4_trascon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_bankmachine4_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine4_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine4_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state;
+ if (litedramcore_bankmachine5_row_close) begin
+ litedramcore_bankmachine5_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine5_row_open) begin
+ litedramcore_bankmachine5_row_opened <= 1'd1;
+ litedramcore_bankmachine5_row <= litedramcore_bankmachine5_source_source_payload_addr[22:7];
+ end
+ end
+ if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin
+ litedramcore_bankmachine5_produce <= (litedramcore_bankmachine5_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine5_do_read) begin
+ litedramcore_bankmachine5_consume <= (litedramcore_bankmachine5_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin
+ if ((~litedramcore_bankmachine5_do_read)) begin
+ litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine5_do_read) begin
+ litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine5_pipe_valid_source_valid <= litedramcore_bankmachine5_pipe_valid_sink_valid;
+ litedramcore_bankmachine5_pipe_valid_source_first <= litedramcore_bankmachine5_pipe_valid_sink_first;
+ litedramcore_bankmachine5_pipe_valid_source_last <= litedramcore_bankmachine5_pipe_valid_sink_last;
+ litedramcore_bankmachine5_pipe_valid_source_payload_we <= litedramcore_bankmachine5_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine5_pipe_valid_source_payload_addr <= litedramcore_bankmachine5_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine5_twtpcon_valid) begin
+ litedramcore_bankmachine5_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine5_twtpcon_ready)) begin
+ litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine5_trccon_valid) begin
+ litedramcore_bankmachine5_trccon_count <= 3'd6;
+ if (1'd0) begin
+ litedramcore_bankmachine5_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine5_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine5_trccon_ready)) begin
+ litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine5_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine5_trascon_valid) begin
+ litedramcore_bankmachine5_trascon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_bankmachine5_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine5_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine5_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state;
+ if (litedramcore_bankmachine6_row_close) begin
+ litedramcore_bankmachine6_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine6_row_open) begin
+ litedramcore_bankmachine6_row_opened <= 1'd1;
+ litedramcore_bankmachine6_row <= litedramcore_bankmachine6_source_source_payload_addr[22:7];
+ end
+ end
+ if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin
+ litedramcore_bankmachine6_produce <= (litedramcore_bankmachine6_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine6_do_read) begin
+ litedramcore_bankmachine6_consume <= (litedramcore_bankmachine6_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin
+ if ((~litedramcore_bankmachine6_do_read)) begin
+ litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine6_do_read) begin
+ litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine6_pipe_valid_source_valid <= litedramcore_bankmachine6_pipe_valid_sink_valid;
+ litedramcore_bankmachine6_pipe_valid_source_first <= litedramcore_bankmachine6_pipe_valid_sink_first;
+ litedramcore_bankmachine6_pipe_valid_source_last <= litedramcore_bankmachine6_pipe_valid_sink_last;
+ litedramcore_bankmachine6_pipe_valid_source_payload_we <= litedramcore_bankmachine6_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine6_pipe_valid_source_payload_addr <= litedramcore_bankmachine6_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine6_twtpcon_valid) begin
+ litedramcore_bankmachine6_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine6_twtpcon_ready)) begin
+ litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine6_trccon_valid) begin
+ litedramcore_bankmachine6_trccon_count <= 3'd6;
+ if (1'd0) begin
+ litedramcore_bankmachine6_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine6_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine6_trccon_ready)) begin
+ litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine6_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine6_trascon_valid) begin
+ litedramcore_bankmachine6_trascon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_bankmachine6_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine6_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine6_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state;
+ if (litedramcore_bankmachine7_row_close) begin
+ litedramcore_bankmachine7_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine7_row_open) begin
+ litedramcore_bankmachine7_row_opened <= 1'd1;
+ litedramcore_bankmachine7_row <= litedramcore_bankmachine7_source_source_payload_addr[22:7];
+ end
+ end
+ if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin
+ litedramcore_bankmachine7_produce <= (litedramcore_bankmachine7_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine7_do_read) begin
+ litedramcore_bankmachine7_consume <= (litedramcore_bankmachine7_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin
+ if ((~litedramcore_bankmachine7_do_read)) begin
+ litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine7_do_read) begin
+ litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine7_pipe_valid_source_valid <= litedramcore_bankmachine7_pipe_valid_sink_valid;
+ litedramcore_bankmachine7_pipe_valid_source_first <= litedramcore_bankmachine7_pipe_valid_sink_first;
+ litedramcore_bankmachine7_pipe_valid_source_last <= litedramcore_bankmachine7_pipe_valid_sink_last;
+ litedramcore_bankmachine7_pipe_valid_source_payload_we <= litedramcore_bankmachine7_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine7_pipe_valid_source_payload_addr <= litedramcore_bankmachine7_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine7_twtpcon_valid) begin
+ litedramcore_bankmachine7_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine7_twtpcon_ready)) begin
+ litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine7_trccon_valid) begin
+ litedramcore_bankmachine7_trccon_count <= 3'd6;
+ if (1'd0) begin
+ litedramcore_bankmachine7_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine7_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine7_trccon_ready)) begin
+ litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine7_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine7_trascon_valid) begin
+ litedramcore_bankmachine7_trascon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_bankmachine7_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine7_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine7_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state;
+ if ((~litedramcore_en0)) begin
+ litedramcore_time0 <= 5'd31;
+ end else begin
+ if ((~litedramcore_max_time0)) begin
+ litedramcore_time0 <= (litedramcore_time0 - 1'd1);
+ end
+ end
+ if ((~litedramcore_en1)) begin
+ litedramcore_time1 <= 4'd15;
+ end else begin
+ if ((~litedramcore_max_time1)) begin
+ litedramcore_time1 <= (litedramcore_time1 - 1'd1);
+ end
+ end
+ if (litedramcore_choose_cmd_ce) begin
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 1'd1: begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 2'd2: begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd4: begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd5: begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd6: begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd7: begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ endcase
+ end
+ if (litedramcore_choose_req_ce) begin
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 1'd1: begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 2'd2: begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd4: begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd5: begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd6: begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd7: begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ endcase
+ end
+ litedramcore_dfi_p0_cs_n <= 1'd0;
+ litedramcore_dfi_p0_bank <= array_muxed0;
+ litedramcore_dfi_p0_address <= array_muxed1;
+ litedramcore_dfi_p0_cas_n <= (~array_muxed2);
+ litedramcore_dfi_p0_ras_n <= (~array_muxed3);
+ litedramcore_dfi_p0_we_n <= (~array_muxed4);
+ litedramcore_dfi_p0_rddata_en <= array_muxed5;
+ litedramcore_dfi_p0_wrdata_en <= array_muxed6;
+ litedramcore_dfi_p1_cs_n <= 1'd0;
+ litedramcore_dfi_p1_bank <= array_muxed7;
+ litedramcore_dfi_p1_address <= array_muxed8;
+ litedramcore_dfi_p1_cas_n <= (~array_muxed9);
+ litedramcore_dfi_p1_ras_n <= (~array_muxed10);
+ litedramcore_dfi_p1_we_n <= (~array_muxed11);
+ litedramcore_dfi_p1_rddata_en <= array_muxed12;
+ litedramcore_dfi_p1_wrdata_en <= array_muxed13;
+ litedramcore_dfi_p2_cs_n <= 1'd0;
+ litedramcore_dfi_p2_bank <= array_muxed14;
+ litedramcore_dfi_p2_address <= array_muxed15;
+ litedramcore_dfi_p2_cas_n <= (~array_muxed16);
+ litedramcore_dfi_p2_ras_n <= (~array_muxed17);
+ litedramcore_dfi_p2_we_n <= (~array_muxed18);
+ litedramcore_dfi_p2_rddata_en <= array_muxed19;
+ litedramcore_dfi_p2_wrdata_en <= array_muxed20;
+ litedramcore_dfi_p3_cs_n <= 1'd0;
+ litedramcore_dfi_p3_bank <= array_muxed21;
+ litedramcore_dfi_p3_address <= array_muxed22;
+ litedramcore_dfi_p3_cas_n <= (~array_muxed23);
+ litedramcore_dfi_p3_ras_n <= (~array_muxed24);
+ litedramcore_dfi_p3_we_n <= (~array_muxed25);
+ litedramcore_dfi_p3_rddata_en <= array_muxed26;
+ litedramcore_dfi_p3_wrdata_en <= array_muxed27;
+ if (litedramcore_trrdcon_valid) begin
+ litedramcore_trrdcon_count <= 1'd1;
+ if (1'd0) begin
+ litedramcore_trrdcon_ready <= 1'd1;
+ end else begin
+ litedramcore_trrdcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_trrdcon_ready)) begin
+ litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1);
+ if ((litedramcore_trrdcon_count == 1'd1)) begin
+ litedramcore_trrdcon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid};
+ if ((litedramcore_tfawcon_count < 3'd4)) begin
+ if ((litedramcore_tfawcon_count == 2'd3)) begin
+ litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid);
+ end else begin
+ litedramcore_tfawcon_ready <= 1'd1;
+ end
+ end
+ if (litedramcore_tccdcon_valid) begin
+ litedramcore_tccdcon_count <= 1'd0;
+ if (1'd1) begin
+ litedramcore_tccdcon_ready <= 1'd1;
+ end else begin
+ litedramcore_tccdcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_tccdcon_ready)) begin
+ litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1);
+ if ((litedramcore_tccdcon_count == 1'd1)) begin
+ litedramcore_tccdcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_twtrcon_valid) begin
+ litedramcore_twtrcon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_twtrcon_ready <= 1'd1;
+ end else begin
+ litedramcore_twtrcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_twtrcon_ready)) begin
+ litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1);
+ if ((litedramcore_twtrcon_count == 1'd1)) begin
+ litedramcore_twtrcon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state;
+ litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready));
+ litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0;
+ litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid));
+ litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0;
+ litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1;
+ litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2;
+ litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3;
+ litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4;
+ litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5;
+ litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6;
+ litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7;
+ litedramcore_state <= litedramcore_next_state;
+ if (litedramcore_dat_w_next_value_ce0) begin
+ litedramcore_dat_w <= litedramcore_dat_w_next_value0;
+ end
+ if (litedramcore_adr_next_value_ce1) begin
+ litedramcore_adr <= litedramcore_adr_next_value1;
+ end
+ if (litedramcore_we_next_value_ce2) begin
+ litedramcore_we <= litedramcore_we_next_value2;
+ end
+ interface0_bank_bus_dat_r <= 1'd0;
+ if (csrbank0_sel) begin
+ case (interface0_bank_bus_adr[8:0])
+ 1'd0: begin
+ interface0_bank_bus_dat_r <= csrbank0_init_done0_w;
+ end
+ 1'd1: begin
+ interface0_bank_bus_dat_r <= csrbank0_init_error0_w;
+ end
+ endcase
+ end
+ if (csrbank0_init_done0_re) begin
+ init_done_storage <= csrbank0_init_done0_r;
+ end
+ init_done_re <= csrbank0_init_done0_re;
+ if (csrbank0_init_error0_re) begin
+ init_error_storage <= csrbank0_init_error0_r;
+ end
+ init_error_re <= csrbank0_init_error0_re;
+ interface1_bank_bus_dat_r <= 1'd0;
+ if (csrbank1_sel) begin
+ case (interface1_bank_bus_adr[8:0])
+ 1'd0: begin
+ interface1_bank_bus_dat_r <= csrbank1_rst0_w;
+ end
+ 1'd1: begin
+ interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w;
+ end
+ 2'd2: begin
+ interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w;
+ end
+ 2'd3: begin
+ interface1_bank_bus_dat_r <= csrbank1_wlevel_en0_w;
+ end
+ 3'd4: begin
+ interface1_bank_bus_dat_r <= a7ddrphy_wlevel_strobe_w;
+ end
+ 3'd5: begin
+ interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_rst_w;
+ end
+ 3'd6: begin
+ interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_inc_w;
+ end
+ 3'd7: begin
+ interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_rst_w;
+ end
+ 4'd8: begin
+ interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_w;
+ end
+ 4'd9: begin
+ interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_rst_w;
+ end
+ 4'd10: begin
+ interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_w;
+ end
+ 4'd11: begin
+ interface1_bank_bus_dat_r <= csrbank1_rdphase0_w;
+ end
+ 4'd12: begin
+ interface1_bank_bus_dat_r <= csrbank1_wrphase0_w;
+ end
+ endcase
+ end
+ if (csrbank1_rst0_re) begin
+ a7ddrphy_rst_storage <= csrbank1_rst0_r;
+ end
+ a7ddrphy_rst_re <= csrbank1_rst0_re;
+ if (csrbank1_dly_sel0_re) begin
+ a7ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r;
+ end
+ a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re;
+ if (csrbank1_half_sys8x_taps0_re) begin
+ a7ddrphy_half_sys8x_taps_storage[4:0] <= csrbank1_half_sys8x_taps0_r;
+ end
+ a7ddrphy_half_sys8x_taps_re <= csrbank1_half_sys8x_taps0_re;
+ if (csrbank1_wlevel_en0_re) begin
+ a7ddrphy_wlevel_en_storage <= csrbank1_wlevel_en0_r;
+ end
+ a7ddrphy_wlevel_en_re <= csrbank1_wlevel_en0_re;
+ if (csrbank1_rdphase0_re) begin
+ a7ddrphy_rdphase_storage[1:0] <= csrbank1_rdphase0_r;
+ end
+ a7ddrphy_rdphase_re <= csrbank1_rdphase0_re;
+ if (csrbank1_wrphase0_re) begin
+ a7ddrphy_wrphase_storage[1:0] <= csrbank1_wrphase0_r;
+ end
+ a7ddrphy_wrphase_re <= csrbank1_wrphase0_re;
+ interface2_bank_bus_dat_r <= 1'd0;
+ if (csrbank2_sel) begin
+ case (interface2_bank_bus_adr[8:0])
+ 1'd0: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w;
+ end
+ 1'd1: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w;
+ end
+ 2'd2: begin
+ interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w;
+ end
+ 2'd3: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w;
+ end
+ 3'd4: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w;
+ end
+ 3'd5: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w;
+ end
+ 3'd6: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata_w;
+ end
+ 3'd7: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w;
+ end
+ 4'd8: begin
+ interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w;
+ end
+ 4'd9: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w;
+ end
+ 4'd10: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w;
+ end
+ 4'd11: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w;
+ end
+ 4'd12: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata_w;
+ end
+ 4'd13: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w;
+ end
+ 4'd14: begin
+ interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w;
+ end
+ 4'd15: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w;
+ end
+ 5'd16: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w;
+ end
+ 5'd17: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w;
+ end
+ 5'd18: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata_w;
+ end
+ 5'd19: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w;
+ end
+ 5'd20: begin
+ interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w;
+ end
+ 5'd21: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w;
+ end
+ 5'd22: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w;
+ end
+ 5'd23: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w;
+ end
+ 5'd24: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata_w;
+ end
+ endcase
+ end
+ if (csrbank2_dfii_control0_re) begin
+ litedramcore_storage[3:0] <= csrbank2_dfii_control0_r;
+ end
+ litedramcore_re <= csrbank2_dfii_control0_re;
+ if (csrbank2_dfii_pi0_command0_re) begin
+ litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r;
+ end
+ litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re;
+ if (csrbank2_dfii_pi0_address0_re) begin
+ litedramcore_phaseinjector0_address_storage[15:0] <= csrbank2_dfii_pi0_address0_r;
+ end
+ litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re;
+ if (csrbank2_dfii_pi0_baddress0_re) begin
+ litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r;
+ end
+ litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re;
+ if (csrbank2_dfii_pi0_wrdata0_re) begin
+ litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r;
+ end
+ litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re;
+ litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata_re;
+ if (csrbank2_dfii_pi1_command0_re) begin
+ litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r;
+ end
+ litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re;
+ if (csrbank2_dfii_pi1_address0_re) begin
+ litedramcore_phaseinjector1_address_storage[15:0] <= csrbank2_dfii_pi1_address0_r;
+ end
+ litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re;
+ if (csrbank2_dfii_pi1_baddress0_re) begin
+ litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r;
+ end
+ litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re;
+ if (csrbank2_dfii_pi1_wrdata0_re) begin
+ litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r;
+ end
+ litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re;
+ litedramcore_phaseinjector1_rddata_re <= csrbank2_dfii_pi1_rddata_re;
+ if (csrbank2_dfii_pi2_command0_re) begin
+ litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r;
+ end
+ litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re;
+ if (csrbank2_dfii_pi2_address0_re) begin
+ litedramcore_phaseinjector2_address_storage[15:0] <= csrbank2_dfii_pi2_address0_r;
+ end
+ litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re;
+ if (csrbank2_dfii_pi2_baddress0_re) begin
+ litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r;
+ end
+ litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re;
+ if (csrbank2_dfii_pi2_wrdata0_re) begin
+ litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r;
+ end
+ litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re;
+ litedramcore_phaseinjector2_rddata_re <= csrbank2_dfii_pi2_rddata_re;
+ if (csrbank2_dfii_pi3_command0_re) begin
+ litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r;
+ end
+ litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re;
+ if (csrbank2_dfii_pi3_address0_re) begin
+ litedramcore_phaseinjector3_address_storage[15:0] <= csrbank2_dfii_pi3_address0_r;
+ end
+ litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re;
+ if (csrbank2_dfii_pi3_baddress0_re) begin
+ litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r;
+ end
+ litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re;
+ if (csrbank2_dfii_pi3_wrdata0_re) begin
+ litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r;
+ end
+ litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re;
+ litedramcore_phaseinjector3_rddata_re <= csrbank2_dfii_pi3_rddata_re;
+ if (sys_rst) begin
+ a7ddrphy_rst_storage <= 1'd0;
+ a7ddrphy_rst_re <= 1'd0;
+ a7ddrphy_dly_sel_storage <= 2'd0;
+ a7ddrphy_dly_sel_re <= 1'd0;
+ a7ddrphy_half_sys8x_taps_storage <= 5'd8;
+ a7ddrphy_half_sys8x_taps_re <= 1'd0;
+ a7ddrphy_wlevel_en_storage <= 1'd0;
+ a7ddrphy_wlevel_en_re <= 1'd0;
+ a7ddrphy_rdphase_storage <= 2'd2;
+ a7ddrphy_rdphase_re <= 1'd0;
+ a7ddrphy_wrphase_storage <= 2'd3;
+ a7ddrphy_wrphase_re <= 1'd0;
+ a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
+ a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
+ a7ddrphy_dqspattern_o1 <= 8'd0;
+ a7ddrphy_bitslip0_value0 <= 3'd7;
+ a7ddrphy_bitslip1_value0 <= 3'd7;
+ a7ddrphy_bitslip0_value1 <= 3'd7;
+ a7ddrphy_bitslip1_value1 <= 3'd7;
+ a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
+ a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
+ a7ddrphy_bitslip0_value2 <= 3'd7;
+ a7ddrphy_bitslip0_value3 <= 3'd7;
+ a7ddrphy_bitslip1_value2 <= 3'd7;
+ a7ddrphy_bitslip1_value3 <= 3'd7;
+ a7ddrphy_bitslip2_value0 <= 3'd7;
+ a7ddrphy_bitslip2_value1 <= 3'd7;
+ a7ddrphy_bitslip3_value0 <= 3'd7;
+ a7ddrphy_bitslip3_value1 <= 3'd7;
+ a7ddrphy_bitslip4_value0 <= 3'd7;
+ a7ddrphy_bitslip4_value1 <= 3'd7;
+ a7ddrphy_bitslip5_value0 <= 3'd7;
+ a7ddrphy_bitslip5_value1 <= 3'd7;
+ a7ddrphy_bitslip6_value0 <= 3'd7;
+ a7ddrphy_bitslip6_value1 <= 3'd7;
+ a7ddrphy_bitslip7_value0 <= 3'd7;
+ a7ddrphy_bitslip7_value1 <= 3'd7;
+ a7ddrphy_bitslip8_value0 <= 3'd7;
+ a7ddrphy_bitslip8_value1 <= 3'd7;
+ a7ddrphy_bitslip9_value0 <= 3'd7;
+ a7ddrphy_bitslip9_value1 <= 3'd7;
+ a7ddrphy_bitslip10_value0 <= 3'd7;
+ a7ddrphy_bitslip10_value1 <= 3'd7;
+ a7ddrphy_bitslip11_value0 <= 3'd7;
+ a7ddrphy_bitslip11_value1 <= 3'd7;
+ a7ddrphy_bitslip12_value0 <= 3'd7;
+ a7ddrphy_bitslip12_value1 <= 3'd7;
+ a7ddrphy_bitslip13_value0 <= 3'd7;
+ a7ddrphy_bitslip13_value1 <= 3'd7;
+ a7ddrphy_bitslip14_value0 <= 3'd7;
+ a7ddrphy_bitslip14_value1 <= 3'd7;
+ a7ddrphy_bitslip15_value0 <= 3'd7;
+ a7ddrphy_bitslip15_value1 <= 3'd7;
+ a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0;
+ a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0;
+ a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0;
+ a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0;
+ a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0;
+ a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0;
+ a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0;
+ a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0;
+ a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0;
+ a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0;
+ a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0;
+ litedramcore_storage <= 4'd1;
+ litedramcore_re <= 1'd0;
+ litedramcore_phaseinjector0_command_storage <= 6'd0;
+ litedramcore_phaseinjector0_command_re <= 1'd0;
+ litedramcore_phaseinjector0_address_re <= 1'd0;
+ litedramcore_phaseinjector0_baddress_re <= 1'd0;
+ litedramcore_phaseinjector0_wrdata_re <= 1'd0;
+ litedramcore_phaseinjector0_rddata_status <= 32'd0;
+ litedramcore_phaseinjector0_rddata_re <= 1'd0;
+ litedramcore_phaseinjector1_command_storage <= 6'd0;
+ litedramcore_phaseinjector1_command_re <= 1'd0;
+ litedramcore_phaseinjector1_address_re <= 1'd0;
+ litedramcore_phaseinjector1_baddress_re <= 1'd0;
+ litedramcore_phaseinjector1_wrdata_re <= 1'd0;
+ litedramcore_phaseinjector1_rddata_status <= 32'd0;
+ litedramcore_phaseinjector1_rddata_re <= 1'd0;
+ litedramcore_phaseinjector2_command_storage <= 6'd0;
+ litedramcore_phaseinjector2_command_re <= 1'd0;
+ litedramcore_phaseinjector2_address_re <= 1'd0;
+ litedramcore_phaseinjector2_baddress_re <= 1'd0;
+ litedramcore_phaseinjector2_wrdata_re <= 1'd0;
+ litedramcore_phaseinjector2_rddata_status <= 32'd0;
+ litedramcore_phaseinjector2_rddata_re <= 1'd0;
+ litedramcore_phaseinjector3_command_storage <= 6'd0;
+ litedramcore_phaseinjector3_command_re <= 1'd0;
+ litedramcore_phaseinjector3_address_re <= 1'd0;
+ litedramcore_phaseinjector3_baddress_re <= 1'd0;
+ litedramcore_phaseinjector3_wrdata_re <= 1'd0;
+ litedramcore_phaseinjector3_rddata_status <= 32'd0;
+ litedramcore_phaseinjector3_rddata_re <= 1'd0;
+ litedramcore_dfi_p0_address <= 16'd0;
+ litedramcore_dfi_p0_bank <= 3'd0;
+ litedramcore_dfi_p0_cas_n <= 1'd1;
+ litedramcore_dfi_p0_cs_n <= 1'd1;
+ litedramcore_dfi_p0_ras_n <= 1'd1;
+ litedramcore_dfi_p0_we_n <= 1'd1;
+ litedramcore_dfi_p0_wrdata_en <= 1'd0;
+ litedramcore_dfi_p0_rddata_en <= 1'd0;
+ litedramcore_dfi_p1_address <= 16'd0;
+ litedramcore_dfi_p1_bank <= 3'd0;
+ litedramcore_dfi_p1_cas_n <= 1'd1;
+ litedramcore_dfi_p1_cs_n <= 1'd1;
+ litedramcore_dfi_p1_ras_n <= 1'd1;
+ litedramcore_dfi_p1_we_n <= 1'd1;
+ litedramcore_dfi_p1_wrdata_en <= 1'd0;
+ litedramcore_dfi_p1_rddata_en <= 1'd0;
+ litedramcore_dfi_p2_address <= 16'd0;
+ litedramcore_dfi_p2_bank <= 3'd0;
+ litedramcore_dfi_p2_cas_n <= 1'd1;
+ litedramcore_dfi_p2_cs_n <= 1'd1;
+ litedramcore_dfi_p2_ras_n <= 1'd1;
+ litedramcore_dfi_p2_we_n <= 1'd1;
+ litedramcore_dfi_p2_wrdata_en <= 1'd0;
+ litedramcore_dfi_p2_rddata_en <= 1'd0;
+ litedramcore_dfi_p3_address <= 16'd0;
+ litedramcore_dfi_p3_bank <= 3'd0;
+ litedramcore_dfi_p3_cas_n <= 1'd1;
+ litedramcore_dfi_p3_cs_n <= 1'd1;
+ litedramcore_dfi_p3_ras_n <= 1'd1;
+ litedramcore_dfi_p3_we_n <= 1'd1;
+ litedramcore_dfi_p3_wrdata_en <= 1'd0;
+ litedramcore_dfi_p3_rddata_en <= 1'd0;
+ litedramcore_cmd_payload_a <= 16'd0;
+ litedramcore_cmd_payload_ba <= 3'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd0;
+ litedramcore_cmd_payload_we <= 1'd0;
+ litedramcore_timer_count1 <= 10'd781;
+ litedramcore_postponer_req_o <= 1'd0;
+ litedramcore_postponer_count <= 1'd0;
+ litedramcore_sequencer_done1 <= 1'd0;
+ litedramcore_sequencer_counter <= 7'd0;
+ litedramcore_sequencer_count <= 1'd0;
+ litedramcore_zqcs_timer_count1 <= 27'd99999999;
+ litedramcore_zqcs_executer_done <= 1'd0;
+ litedramcore_zqcs_executer_counter <= 5'd0;
+ litedramcore_bankmachine0_level <= 5'd0;
+ litedramcore_bankmachine0_produce <= 4'd0;
+ litedramcore_bankmachine0_consume <= 4'd0;
+ litedramcore_bankmachine0_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine0_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine0_pipe_valid_source_payload_addr <= 23'd0;
+ litedramcore_bankmachine0_row <= 16'd0;
+ litedramcore_bankmachine0_row_opened <= 1'd0;
+ litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine0_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine0_trccon_ready <= 1'd0;
+ litedramcore_bankmachine0_trccon_count <= 3'd0;
+ litedramcore_bankmachine0_trascon_ready <= 1'd0;
+ litedramcore_bankmachine0_trascon_count <= 3'd0;
+ litedramcore_bankmachine1_level <= 5'd0;
+ litedramcore_bankmachine1_produce <= 4'd0;
+ litedramcore_bankmachine1_consume <= 4'd0;
+ litedramcore_bankmachine1_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine1_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine1_pipe_valid_source_payload_addr <= 23'd0;
+ litedramcore_bankmachine1_row <= 16'd0;
+ litedramcore_bankmachine1_row_opened <= 1'd0;
+ litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine1_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine1_trccon_ready <= 1'd0;
+ litedramcore_bankmachine1_trccon_count <= 3'd0;
+ litedramcore_bankmachine1_trascon_ready <= 1'd0;
+ litedramcore_bankmachine1_trascon_count <= 3'd0;
+ litedramcore_bankmachine2_level <= 5'd0;
+ litedramcore_bankmachine2_produce <= 4'd0;
+ litedramcore_bankmachine2_consume <= 4'd0;
+ litedramcore_bankmachine2_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine2_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine2_pipe_valid_source_payload_addr <= 23'd0;
+ litedramcore_bankmachine2_row <= 16'd0;
+ litedramcore_bankmachine2_row_opened <= 1'd0;
+ litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine2_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine2_trccon_ready <= 1'd0;
+ litedramcore_bankmachine2_trccon_count <= 3'd0;
+ litedramcore_bankmachine2_trascon_ready <= 1'd0;
+ litedramcore_bankmachine2_trascon_count <= 3'd0;
+ litedramcore_bankmachine3_level <= 5'd0;
+ litedramcore_bankmachine3_produce <= 4'd0;
+ litedramcore_bankmachine3_consume <= 4'd0;
+ litedramcore_bankmachine3_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine3_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine3_pipe_valid_source_payload_addr <= 23'd0;
+ litedramcore_bankmachine3_row <= 16'd0;
+ litedramcore_bankmachine3_row_opened <= 1'd0;
+ litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine3_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine3_trccon_ready <= 1'd0;
+ litedramcore_bankmachine3_trccon_count <= 3'd0;
+ litedramcore_bankmachine3_trascon_ready <= 1'd0;
+ litedramcore_bankmachine3_trascon_count <= 3'd0;
+ litedramcore_bankmachine4_level <= 5'd0;
+ litedramcore_bankmachine4_produce <= 4'd0;
+ litedramcore_bankmachine4_consume <= 4'd0;
+ litedramcore_bankmachine4_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine4_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine4_pipe_valid_source_payload_addr <= 23'd0;
+ litedramcore_bankmachine4_row <= 16'd0;
+ litedramcore_bankmachine4_row_opened <= 1'd0;
+ litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine4_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine4_trccon_ready <= 1'd0;
+ litedramcore_bankmachine4_trccon_count <= 3'd0;
+ litedramcore_bankmachine4_trascon_ready <= 1'd0;
+ litedramcore_bankmachine4_trascon_count <= 3'd0;
+ litedramcore_bankmachine5_level <= 5'd0;
+ litedramcore_bankmachine5_produce <= 4'd0;
+ litedramcore_bankmachine5_consume <= 4'd0;
+ litedramcore_bankmachine5_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine5_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine5_pipe_valid_source_payload_addr <= 23'd0;
+ litedramcore_bankmachine5_row <= 16'd0;
+ litedramcore_bankmachine5_row_opened <= 1'd0;
+ litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine5_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine5_trccon_ready <= 1'd0;
+ litedramcore_bankmachine5_trccon_count <= 3'd0;
+ litedramcore_bankmachine5_trascon_ready <= 1'd0;
+ litedramcore_bankmachine5_trascon_count <= 3'd0;
+ litedramcore_bankmachine6_level <= 5'd0;
+ litedramcore_bankmachine6_produce <= 4'd0;
+ litedramcore_bankmachine6_consume <= 4'd0;
+ litedramcore_bankmachine6_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine6_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine6_pipe_valid_source_payload_addr <= 23'd0;
+ litedramcore_bankmachine6_row <= 16'd0;
+ litedramcore_bankmachine6_row_opened <= 1'd0;
+ litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine6_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine6_trccon_ready <= 1'd0;
+ litedramcore_bankmachine6_trccon_count <= 3'd0;
+ litedramcore_bankmachine6_trascon_ready <= 1'd0;
+ litedramcore_bankmachine6_trascon_count <= 3'd0;
+ litedramcore_bankmachine7_level <= 5'd0;
+ litedramcore_bankmachine7_produce <= 4'd0;
+ litedramcore_bankmachine7_consume <= 4'd0;
+ litedramcore_bankmachine7_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine7_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine7_pipe_valid_source_payload_addr <= 23'd0;
+ litedramcore_bankmachine7_row <= 16'd0;
+ litedramcore_bankmachine7_row_opened <= 1'd0;
+ litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine7_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine7_trccon_ready <= 1'd0;
+ litedramcore_bankmachine7_trccon_count <= 3'd0;
+ litedramcore_bankmachine7_trascon_ready <= 1'd0;
+ litedramcore_bankmachine7_trascon_count <= 3'd0;
+ litedramcore_choose_cmd_grant <= 3'd0;
+ litedramcore_choose_req_grant <= 3'd0;
+ litedramcore_trrdcon_ready <= 1'd0;
+ litedramcore_trrdcon_count <= 1'd0;
+ litedramcore_tfawcon_ready <= 1'd1;
+ litedramcore_tfawcon_window <= 5'd0;
+ litedramcore_tccdcon_ready <= 1'd0;
+ litedramcore_tccdcon_count <= 1'd0;
+ litedramcore_twtrcon_ready <= 1'd0;
+ litedramcore_twtrcon_count <= 3'd0;
+ litedramcore_time0 <= 5'd0;
+ litedramcore_time1 <= 4'd0;
+ init_done_storage <= 1'd0;
+ init_done_re <= 1'd0;
+ init_error_storage <= 1'd0;
+ init_error_re <= 1'd0;
+ litedramcore_we <= 1'd0;
+ litedramcore_refresher_state <= 2'd0;
+ litedramcore_bankmachine0_state <= 4'd0;
+ litedramcore_bankmachine1_state <= 4'd0;
+ litedramcore_bankmachine2_state <= 4'd0;
+ litedramcore_bankmachine3_state <= 4'd0;
+ litedramcore_bankmachine4_state <= 4'd0;
+ litedramcore_bankmachine5_state <= 4'd0;
+ litedramcore_bankmachine6_state <= 4'd0;
+ litedramcore_bankmachine7_state <= 4'd0;
+ litedramcore_multiplexer_state <= 4'd0;
+ litedramcore_new_master_wdata_ready0 <= 1'd0;
+ litedramcore_new_master_wdata_ready1 <= 1'd0;
+ litedramcore_new_master_rdata_valid0 <= 1'd0;
+ litedramcore_new_master_rdata_valid1 <= 1'd0;
+ litedramcore_new_master_rdata_valid2 <= 1'd0;
+ litedramcore_new_master_rdata_valid3 <= 1'd0;
+ litedramcore_new_master_rdata_valid4 <= 1'd0;
+ litedramcore_new_master_rdata_valid5 <= 1'd0;
+ litedramcore_new_master_rdata_valid6 <= 1'd0;
+ litedramcore_new_master_rdata_valid7 <= 1'd0;
+ litedramcore_new_master_rdata_valid8 <= 1'd0;
+ litedramcore_state <= 2'd0;
+ end
end
reg [25:0] storage[0:15];
reg [25:0] storage_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we)
- storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
- storage_dat0 <= storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine0_wrport_we)
+ storage[litedramcore_bankmachine0_wrport_adr] <= litedramcore_bankmachine0_wrport_dat_w;
+ storage_dat0 <= storage[litedramcore_bankmachine0_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = storage_dat0;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine0_wrport_dat_r = storage_dat0;
+assign litedramcore_bankmachine0_rdport_dat_r = storage[litedramcore_bankmachine0_rdport_adr];
//------------------------------------------------------------------------------
reg [25:0] storage_1[0:15];
reg [25:0] storage_1_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we)
- storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
- storage_1_dat0 <= storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine1_wrport_we)
+ storage_1[litedramcore_bankmachine1_wrport_adr] <= litedramcore_bankmachine1_wrport_dat_w;
+ storage_1_dat0 <= storage_1[litedramcore_bankmachine1_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = storage_1_dat0;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine1_wrport_dat_r = storage_1_dat0;
+assign litedramcore_bankmachine1_rdport_dat_r = storage_1[litedramcore_bankmachine1_rdport_adr];
//------------------------------------------------------------------------------
reg [25:0] storage_2[0:15];
reg [25:0] storage_2_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we)
- storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
- storage_2_dat0 <= storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine2_wrport_we)
+ storage_2[litedramcore_bankmachine2_wrport_adr] <= litedramcore_bankmachine2_wrport_dat_w;
+ storage_2_dat0 <= storage_2[litedramcore_bankmachine2_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = storage_2_dat0;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine2_wrport_dat_r = storage_2_dat0;
+assign litedramcore_bankmachine2_rdport_dat_r = storage_2[litedramcore_bankmachine2_rdport_adr];
//------------------------------------------------------------------------------
reg [25:0] storage_3[0:15];
reg [25:0] storage_3_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we)
- storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
- storage_3_dat0 <= storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine3_wrport_we)
+ storage_3[litedramcore_bankmachine3_wrport_adr] <= litedramcore_bankmachine3_wrport_dat_w;
+ storage_3_dat0 <= storage_3[litedramcore_bankmachine3_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = storage_3_dat0;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine3_wrport_dat_r = storage_3_dat0;
+assign litedramcore_bankmachine3_rdport_dat_r = storage_3[litedramcore_bankmachine3_rdport_adr];
//------------------------------------------------------------------------------
reg [25:0] storage_4[0:15];
reg [25:0] storage_4_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we)
- storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
- storage_4_dat0 <= storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine4_wrport_we)
+ storage_4[litedramcore_bankmachine4_wrport_adr] <= litedramcore_bankmachine4_wrport_dat_w;
+ storage_4_dat0 <= storage_4[litedramcore_bankmachine4_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = storage_4_dat0;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine4_wrport_dat_r = storage_4_dat0;
+assign litedramcore_bankmachine4_rdport_dat_r = storage_4[litedramcore_bankmachine4_rdport_adr];
//------------------------------------------------------------------------------
reg [25:0] storage_5[0:15];
reg [25:0] storage_5_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we)
- storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
- storage_5_dat0 <= storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine5_wrport_we)
+ storage_5[litedramcore_bankmachine5_wrport_adr] <= litedramcore_bankmachine5_wrport_dat_w;
+ storage_5_dat0 <= storage_5[litedramcore_bankmachine5_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = storage_5_dat0;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine5_wrport_dat_r = storage_5_dat0;
+assign litedramcore_bankmachine5_rdport_dat_r = storage_5[litedramcore_bankmachine5_rdport_adr];
//------------------------------------------------------------------------------
reg [25:0] storage_6[0:15];
reg [25:0] storage_6_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we)
- storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
- storage_6_dat0 <= storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine6_wrport_we)
+ storage_6[litedramcore_bankmachine6_wrport_adr] <= litedramcore_bankmachine6_wrport_dat_w;
+ storage_6_dat0 <= storage_6[litedramcore_bankmachine6_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = storage_6_dat0;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine6_wrport_dat_r = storage_6_dat0;
+assign litedramcore_bankmachine6_rdport_dat_r = storage_6[litedramcore_bankmachine6_rdport_adr];
//------------------------------------------------------------------------------
reg [25:0] storage_7[0:15];
reg [25:0] storage_7_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we)
- storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
- storage_7_dat0 <= storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine7_wrport_we)
+ storage_7[litedramcore_bankmachine7_wrport_adr] <= litedramcore_bankmachine7_wrport_dat_w;
+ storage_7_dat0 <= storage_7[litedramcore_bankmachine7_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = storage_7_dat0;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine7_wrport_dat_r = storage_7_dat0;
+assign litedramcore_bankmachine7_rdport_dat_r = storage_7[litedramcore_bankmachine7_rdport_adr];
FDCE FDCE(
.LOCKED(locked)
);
-(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
+(* ars_ff1 = "true", async_reg = "true" *)
+FDPE #(
.INIT(1'd1)
) FDPE (
.C(iodelay_clk),
.Q(xilinxasyncresetsynchronizerimpl0_rst_meta)
);
-(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
+(* ars_ff2 = "true", async_reg = "true" *)
+FDPE #(
.INIT(1'd1)
) FDPE_1 (
.C(iodelay_clk),
.Q(iodelay_rst)
);
-(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
+(* ars_ff1 = "true", async_reg = "true" *)
+FDPE #(
.INIT(1'd1)
) FDPE_2 (
.C(sys_clk),
.Q(xilinxasyncresetsynchronizerimpl1_rst_meta)
);
-(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
+(* ars_ff2 = "true", async_reg = "true" *)
+FDPE #(
.INIT(1'd1)
) FDPE_3 (
.C(sys_clk),
.Q(sys_rst)
);
-(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
+(* ars_ff1 = "true", async_reg = "true" *)
+FDPE #(
.INIT(1'd1)
) FDPE_4 (
.C(sys4x_clk),
.Q(xilinxasyncresetsynchronizerimpl2_rst_meta)
);
-(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
+(* ars_ff2 = "true", async_reg = "true" *)
+FDPE #(
.INIT(1'd1)
) FDPE_5 (
.C(sys4x_clk),
.Q(xilinxasyncresetsynchronizerimpl2_expr)
);
-(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
+(* ars_ff1 = "true", async_reg = "true" *)
+FDPE #(
.INIT(1'd1)
) FDPE_6 (
.C(sys4x_dqs_clk),
.Q(xilinxasyncresetsynchronizerimpl3_rst_meta)
);
-(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
+(* ars_ff2 = "true", async_reg = "true" *)
+FDPE #(
.INIT(1'd1)
) FDPE_7 (
.C(sys4x_dqs_clk),
endmodule
// -----------------------------------------------------------------------------
-// Auto-Generated by LiteX on 2022-08-04 21:07:00.
+// Auto-Generated by LiteX on 2022-10-28 19:01:23.
//------------------------------------------------------------------------------
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//
// Filename : litedram_core.v
// Device :
-// LiteX sha1 : 6932fc51
-// Date : 2022-08-04 21:06:55
+// LiteX sha1 : --------
+// Date : 2022-10-28 19:01:18
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
module litedram_core (
- input wire clk,
- input wire rst,
- output wire pll_locked,
- output wire [13:0] ddram_a,
- output wire [2:0] ddram_ba,
- output wire ddram_ras_n,
- output wire ddram_cas_n,
- output wire ddram_we_n,
- output wire ddram_cs_n,
- output wire [1:0] ddram_dm,
- inout wire [15:0] ddram_dq,
- inout wire [1:0] ddram_dqs_p,
- inout wire [1:0] ddram_dqs_n,
- output wire ddram_clk_p,
- output wire ddram_clk_n,
- output wire ddram_cke,
- output wire ddram_odt,
- output wire ddram_reset_n,
- output wire init_done,
- output wire init_error,
- input wire [29:0] wb_ctrl_adr,
- input wire [31:0] wb_ctrl_dat_w,
- output wire [31:0] wb_ctrl_dat_r,
- input wire [3:0] wb_ctrl_sel,
- input wire wb_ctrl_cyc,
- input wire wb_ctrl_stb,
- output wire wb_ctrl_ack,
- input wire wb_ctrl_we,
- input wire [2:0] wb_ctrl_cti,
- input wire [1:0] wb_ctrl_bte,
- output wire wb_ctrl_err,
- output wire user_clk,
- output wire user_rst,
- input wire user_port_native_0_cmd_valid,
- output wire user_port_native_0_cmd_ready,
- input wire user_port_native_0_cmd_we,
- input wire [23:0] user_port_native_0_cmd_addr,
- input wire user_port_native_0_wdata_valid,
- output wire user_port_native_0_wdata_ready,
- input wire [15:0] user_port_native_0_wdata_we,
- input wire [127:0] user_port_native_0_wdata_data,
- output wire user_port_native_0_rdata_valid,
- input wire user_port_native_0_rdata_ready,
- output wire [127:0] user_port_native_0_rdata_data
+ input wire clk,
+ input wire rst,
+ output wire pll_locked,
+ output wire [13:0] ddram_a,
+ output wire [2:0] ddram_ba,
+ output wire ddram_ras_n,
+ output wire ddram_cas_n,
+ output wire ddram_we_n,
+ output wire ddram_cs_n,
+ output wire [1:0] ddram_dm,
+ inout wire [15:0] ddram_dq,
+ inout wire [1:0] ddram_dqs_p,
+ inout wire [1:0] ddram_dqs_n,
+ output wire ddram_clk_p,
+ output wire ddram_clk_n,
+ output wire ddram_cke,
+ output wire ddram_odt,
+ output wire ddram_reset_n,
+ output wire init_done,
+ output wire init_error,
+ input wire [29:0] wb_ctrl_adr,
+ input wire [31:0] wb_ctrl_dat_w,
+ output wire [31:0] wb_ctrl_dat_r,
+ input wire [3:0] wb_ctrl_sel,
+ input wire wb_ctrl_cyc,
+ input wire wb_ctrl_stb,
+ output wire wb_ctrl_ack,
+ input wire wb_ctrl_we,
+ input wire [2:0] wb_ctrl_cti,
+ input wire [1:0] wb_ctrl_bte,
+ output wire wb_ctrl_err,
+ output wire user_clk,
+ output wire user_rst,
+ input wire user_port_native_0_cmd_valid,
+ output wire user_port_native_0_cmd_ready,
+ input wire user_port_native_0_cmd_we,
+ input wire [23:0] user_port_native_0_cmd_addr,
+ input wire user_port_native_0_wdata_valid,
+ output wire user_port_native_0_wdata_ready,
+ input wire [15:0] user_port_native_0_wdata_we,
+ input wire [127:0] user_port_native_0_wdata_data,
+ output wire user_port_native_0_rdata_valid,
+ input wire user_port_native_0_rdata_ready,
+ output wire [127:0] user_port_native_0_rdata_data
);
// Signals
//------------------------------------------------------------------------------
-reg rst_1 = 1'd0;
-wire sys_clk;
-wire sys_rst;
-wire sys4x_clk;
-wire sys4x_dqs_clk;
-wire iodelay_clk;
-wire iodelay_rst;
-wire reset;
-reg power_down = 1'd0;
-wire locked;
-wire clkin;
-wire clkout0;
-wire clkout_buf0;
-wire clkout1;
-wire clkout_buf1;
-wire clkout2;
-wire clkout_buf2;
-wire clkout3;
-wire clkout_buf3;
-reg [3:0] reset_counter = 4'd15;
-reg ic_reset = 1'd1;
-reg a7ddrphy_rst_storage = 1'd0;
-reg a7ddrphy_rst_re = 1'd0;
-reg [1:0] a7ddrphy_dly_sel_storage = 2'd0;
-reg a7ddrphy_dly_sel_re = 1'd0;
-reg [4:0] a7ddrphy_half_sys8x_taps_storage = 5'd8;
-reg a7ddrphy_half_sys8x_taps_re = 1'd0;
-reg a7ddrphy_wlevel_en_storage = 1'd0;
-reg a7ddrphy_wlevel_en_re = 1'd0;
-reg a7ddrphy_wlevel_strobe_re = 1'd0;
-wire a7ddrphy_wlevel_strobe_r;
-reg a7ddrphy_wlevel_strobe_we = 1'd0;
-reg a7ddrphy_wlevel_strobe_w = 1'd0;
-reg a7ddrphy_rdly_dq_rst_re = 1'd0;
-wire a7ddrphy_rdly_dq_rst_r;
-reg a7ddrphy_rdly_dq_rst_we = 1'd0;
-reg a7ddrphy_rdly_dq_rst_w = 1'd0;
-reg a7ddrphy_rdly_dq_inc_re = 1'd0;
-wire a7ddrphy_rdly_dq_inc_r;
-reg a7ddrphy_rdly_dq_inc_we = 1'd0;
-reg a7ddrphy_rdly_dq_inc_w = 1'd0;
-reg a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
-wire a7ddrphy_rdly_dq_bitslip_rst_r;
-reg a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
-reg a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
-reg a7ddrphy_rdly_dq_bitslip_re = 1'd0;
-wire a7ddrphy_rdly_dq_bitslip_r;
-reg a7ddrphy_rdly_dq_bitslip_we = 1'd0;
-reg a7ddrphy_rdly_dq_bitslip_w = 1'd0;
-reg a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0;
-wire a7ddrphy_wdly_dq_bitslip_rst_r;
-reg a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0;
-reg a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0;
-reg a7ddrphy_wdly_dq_bitslip_re = 1'd0;
-wire a7ddrphy_wdly_dq_bitslip_r;
-reg a7ddrphy_wdly_dq_bitslip_we = 1'd0;
-reg a7ddrphy_wdly_dq_bitslip_w = 1'd0;
-reg [1:0] a7ddrphy_rdphase_storage = 2'd2;
-reg a7ddrphy_rdphase_re = 1'd0;
-reg [1:0] a7ddrphy_wrphase_storage = 2'd3;
-reg a7ddrphy_wrphase_re = 1'd0;
-wire [13:0] a7ddrphy_dfi_p0_address;
-wire [2:0] a7ddrphy_dfi_p0_bank;
-wire a7ddrphy_dfi_p0_cas_n;
-wire a7ddrphy_dfi_p0_cs_n;
-wire a7ddrphy_dfi_p0_ras_n;
-wire a7ddrphy_dfi_p0_we_n;
-wire a7ddrphy_dfi_p0_cke;
-wire a7ddrphy_dfi_p0_odt;
-wire a7ddrphy_dfi_p0_reset_n;
-wire a7ddrphy_dfi_p0_act_n;
-wire [31:0] a7ddrphy_dfi_p0_wrdata;
-wire a7ddrphy_dfi_p0_wrdata_en;
-wire [3:0] a7ddrphy_dfi_p0_wrdata_mask;
-wire a7ddrphy_dfi_p0_rddata_en;
-reg [31:0] a7ddrphy_dfi_p0_rddata = 32'd0;
-wire a7ddrphy_dfi_p0_rddata_valid;
-wire [13:0] a7ddrphy_dfi_p1_address;
-wire [2:0] a7ddrphy_dfi_p1_bank;
-wire a7ddrphy_dfi_p1_cas_n;
-wire a7ddrphy_dfi_p1_cs_n;
-wire a7ddrphy_dfi_p1_ras_n;
-wire a7ddrphy_dfi_p1_we_n;
-wire a7ddrphy_dfi_p1_cke;
-wire a7ddrphy_dfi_p1_odt;
-wire a7ddrphy_dfi_p1_reset_n;
-wire a7ddrphy_dfi_p1_act_n;
-wire [31:0] a7ddrphy_dfi_p1_wrdata;
-wire a7ddrphy_dfi_p1_wrdata_en;
-wire [3:0] a7ddrphy_dfi_p1_wrdata_mask;
-wire a7ddrphy_dfi_p1_rddata_en;
-reg [31:0] a7ddrphy_dfi_p1_rddata = 32'd0;
-wire a7ddrphy_dfi_p1_rddata_valid;
-wire [13:0] a7ddrphy_dfi_p2_address;
-wire [2:0] a7ddrphy_dfi_p2_bank;
-wire a7ddrphy_dfi_p2_cas_n;
-wire a7ddrphy_dfi_p2_cs_n;
-wire a7ddrphy_dfi_p2_ras_n;
-wire a7ddrphy_dfi_p2_we_n;
-wire a7ddrphy_dfi_p2_cke;
-wire a7ddrphy_dfi_p2_odt;
-wire a7ddrphy_dfi_p2_reset_n;
-wire a7ddrphy_dfi_p2_act_n;
-wire [31:0] a7ddrphy_dfi_p2_wrdata;
-wire a7ddrphy_dfi_p2_wrdata_en;
-wire [3:0] a7ddrphy_dfi_p2_wrdata_mask;
-wire a7ddrphy_dfi_p2_rddata_en;
-reg [31:0] a7ddrphy_dfi_p2_rddata = 32'd0;
-wire a7ddrphy_dfi_p2_rddata_valid;
-wire [13:0] a7ddrphy_dfi_p3_address;
-wire [2:0] a7ddrphy_dfi_p3_bank;
-wire a7ddrphy_dfi_p3_cas_n;
-wire a7ddrphy_dfi_p3_cs_n;
-wire a7ddrphy_dfi_p3_ras_n;
-wire a7ddrphy_dfi_p3_we_n;
-wire a7ddrphy_dfi_p3_cke;
-wire a7ddrphy_dfi_p3_odt;
-wire a7ddrphy_dfi_p3_reset_n;
-wire a7ddrphy_dfi_p3_act_n;
-wire [31:0] a7ddrphy_dfi_p3_wrdata;
-wire a7ddrphy_dfi_p3_wrdata_en;
-wire [3:0] a7ddrphy_dfi_p3_wrdata_mask;
-wire a7ddrphy_dfi_p3_rddata_en;
-reg [31:0] a7ddrphy_dfi_p3_rddata = 32'd0;
-wire a7ddrphy_dfi_p3_rddata_valid;
-wire a7ddrphy_sd_clk_se_nodelay;
-wire [2:0] a7ddrphy_pads_ba;
-reg a7ddrphy_dqs_oe = 1'd0;
-wire a7ddrphy_dqs_preamble;
-wire a7ddrphy_dqs_postamble;
-wire a7ddrphy_dqs_oe_delay_tappeddelayline;
-reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
-reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
-reg a7ddrphy_dqspattern0 = 1'd0;
-reg a7ddrphy_dqspattern1 = 1'd0;
-reg [7:0] a7ddrphy_dqspattern_o0 = 8'd0;
-reg [7:0] a7ddrphy_dqspattern_o1 = 8'd0;
-wire a7ddrphy_dqs_o_no_delay0;
-wire a7ddrphy_dqs_t0;
-reg [7:0] a7ddrphy_bitslip00 = 8'd0;
-reg [2:0] a7ddrphy_bitslip0_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip0_r0 = 16'd0;
-wire a7ddrphy0;
-wire a7ddrphy_dqs_o_no_delay1;
-wire a7ddrphy_dqs_t1;
-reg [7:0] a7ddrphy_bitslip10 = 8'd0;
-reg [2:0] a7ddrphy_bitslip1_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip1_r0 = 16'd0;
-wire a7ddrphy1;
-reg [7:0] a7ddrphy_bitslip01 = 8'd0;
-reg [2:0] a7ddrphy_bitslip0_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip0_r1 = 16'd0;
-reg [7:0] a7ddrphy_bitslip11 = 8'd0;
-reg [2:0] a7ddrphy_bitslip1_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip1_r1 = 16'd0;
-wire a7ddrphy_dq_oe;
-wire a7ddrphy_dq_oe_delay_tappeddelayline;
-reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
-reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
-wire a7ddrphy_dq_o_nodelay0;
-wire a7ddrphy_dq_i_nodelay0;
-wire a7ddrphy_dq_i_delayed0;
-wire a7ddrphy_dq_t0;
-reg [7:0] a7ddrphy_bitslip02 = 8'd0;
-reg [2:0] a7ddrphy_bitslip0_value2 = 3'd7;
-reg [15:0] a7ddrphy_bitslip0_r2 = 16'd0;
-wire [7:0] a7ddrphy_bitslip03;
-reg [7:0] a7ddrphy_bitslip04 = 8'd0;
-reg [2:0] a7ddrphy_bitslip0_value3 = 3'd7;
-reg [15:0] a7ddrphy_bitslip0_r3 = 16'd0;
-wire a7ddrphy_dq_o_nodelay1;
-wire a7ddrphy_dq_i_nodelay1;
-wire a7ddrphy_dq_i_delayed1;
-wire a7ddrphy_dq_t1;
-reg [7:0] a7ddrphy_bitslip12 = 8'd0;
-reg [2:0] a7ddrphy_bitslip1_value2 = 3'd7;
-reg [15:0] a7ddrphy_bitslip1_r2 = 16'd0;
-wire [7:0] a7ddrphy_bitslip13;
-reg [7:0] a7ddrphy_bitslip14 = 8'd0;
-reg [2:0] a7ddrphy_bitslip1_value3 = 3'd7;
-reg [15:0] a7ddrphy_bitslip1_r3 = 16'd0;
-wire a7ddrphy_dq_o_nodelay2;
-wire a7ddrphy_dq_i_nodelay2;
-wire a7ddrphy_dq_i_delayed2;
-wire a7ddrphy_dq_t2;
-reg [7:0] a7ddrphy_bitslip20 = 8'd0;
-reg [2:0] a7ddrphy_bitslip2_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip2_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip21;
-reg [7:0] a7ddrphy_bitslip22 = 8'd0;
-reg [2:0] a7ddrphy_bitslip2_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip2_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay3;
-wire a7ddrphy_dq_i_nodelay3;
-wire a7ddrphy_dq_i_delayed3;
-wire a7ddrphy_dq_t3;
-reg [7:0] a7ddrphy_bitslip30 = 8'd0;
-reg [2:0] a7ddrphy_bitslip3_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip3_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip31;
-reg [7:0] a7ddrphy_bitslip32 = 8'd0;
-reg [2:0] a7ddrphy_bitslip3_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip3_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay4;
-wire a7ddrphy_dq_i_nodelay4;
-wire a7ddrphy_dq_i_delayed4;
-wire a7ddrphy_dq_t4;
-reg [7:0] a7ddrphy_bitslip40 = 8'd0;
-reg [2:0] a7ddrphy_bitslip4_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip4_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip41;
-reg [7:0] a7ddrphy_bitslip42 = 8'd0;
-reg [2:0] a7ddrphy_bitslip4_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip4_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay5;
-wire a7ddrphy_dq_i_nodelay5;
-wire a7ddrphy_dq_i_delayed5;
-wire a7ddrphy_dq_t5;
-reg [7:0] a7ddrphy_bitslip50 = 8'd0;
-reg [2:0] a7ddrphy_bitslip5_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip5_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip51;
-reg [7:0] a7ddrphy_bitslip52 = 8'd0;
-reg [2:0] a7ddrphy_bitslip5_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip5_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay6;
-wire a7ddrphy_dq_i_nodelay6;
-wire a7ddrphy_dq_i_delayed6;
-wire a7ddrphy_dq_t6;
-reg [7:0] a7ddrphy_bitslip60 = 8'd0;
-reg [2:0] a7ddrphy_bitslip6_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip6_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip61;
-reg [7:0] a7ddrphy_bitslip62 = 8'd0;
-reg [2:0] a7ddrphy_bitslip6_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip6_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay7;
-wire a7ddrphy_dq_i_nodelay7;
-wire a7ddrphy_dq_i_delayed7;
-wire a7ddrphy_dq_t7;
-reg [7:0] a7ddrphy_bitslip70 = 8'd0;
-reg [2:0] a7ddrphy_bitslip7_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip7_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip71;
-reg [7:0] a7ddrphy_bitslip72 = 8'd0;
-reg [2:0] a7ddrphy_bitslip7_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip7_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay8;
-wire a7ddrphy_dq_i_nodelay8;
-wire a7ddrphy_dq_i_delayed8;
-wire a7ddrphy_dq_t8;
-reg [7:0] a7ddrphy_bitslip80 = 8'd0;
-reg [2:0] a7ddrphy_bitslip8_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip8_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip81;
-reg [7:0] a7ddrphy_bitslip82 = 8'd0;
-reg [2:0] a7ddrphy_bitslip8_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip8_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay9;
-wire a7ddrphy_dq_i_nodelay9;
-wire a7ddrphy_dq_i_delayed9;
-wire a7ddrphy_dq_t9;
-reg [7:0] a7ddrphy_bitslip90 = 8'd0;
-reg [2:0] a7ddrphy_bitslip9_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip9_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip91;
-reg [7:0] a7ddrphy_bitslip92 = 8'd0;
-reg [2:0] a7ddrphy_bitslip9_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip9_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay10;
-wire a7ddrphy_dq_i_nodelay10;
-wire a7ddrphy_dq_i_delayed10;
-wire a7ddrphy_dq_t10;
-reg [7:0] a7ddrphy_bitslip100 = 8'd0;
-reg [2:0] a7ddrphy_bitslip10_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip10_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip101;
-reg [7:0] a7ddrphy_bitslip102 = 8'd0;
-reg [2:0] a7ddrphy_bitslip10_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip10_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay11;
-wire a7ddrphy_dq_i_nodelay11;
-wire a7ddrphy_dq_i_delayed11;
-wire a7ddrphy_dq_t11;
-reg [7:0] a7ddrphy_bitslip110 = 8'd0;
-reg [2:0] a7ddrphy_bitslip11_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip11_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip111;
-reg [7:0] a7ddrphy_bitslip112 = 8'd0;
-reg [2:0] a7ddrphy_bitslip11_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip11_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay12;
-wire a7ddrphy_dq_i_nodelay12;
-wire a7ddrphy_dq_i_delayed12;
-wire a7ddrphy_dq_t12;
-reg [7:0] a7ddrphy_bitslip120 = 8'd0;
-reg [2:0] a7ddrphy_bitslip12_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip12_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip121;
-reg [7:0] a7ddrphy_bitslip122 = 8'd0;
-reg [2:0] a7ddrphy_bitslip12_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip12_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay13;
-wire a7ddrphy_dq_i_nodelay13;
-wire a7ddrphy_dq_i_delayed13;
-wire a7ddrphy_dq_t13;
-reg [7:0] a7ddrphy_bitslip130 = 8'd0;
-reg [2:0] a7ddrphy_bitslip13_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip13_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip131;
-reg [7:0] a7ddrphy_bitslip132 = 8'd0;
-reg [2:0] a7ddrphy_bitslip13_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip13_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay14;
-wire a7ddrphy_dq_i_nodelay14;
-wire a7ddrphy_dq_i_delayed14;
-wire a7ddrphy_dq_t14;
-reg [7:0] a7ddrphy_bitslip140 = 8'd0;
-reg [2:0] a7ddrphy_bitslip14_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip14_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip141;
-reg [7:0] a7ddrphy_bitslip142 = 8'd0;
-reg [2:0] a7ddrphy_bitslip14_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip14_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay15;
-wire a7ddrphy_dq_i_nodelay15;
-wire a7ddrphy_dq_i_delayed15;
-wire a7ddrphy_dq_t15;
-reg [7:0] a7ddrphy_bitslip150 = 8'd0;
-reg [2:0] a7ddrphy_bitslip15_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip15_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip151;
-reg [7:0] a7ddrphy_bitslip152 = 8'd0;
-reg [2:0] a7ddrphy_bitslip15_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip15_r1 = 16'd0;
-reg a7ddrphy_rddata_en_tappeddelayline0 = 1'd0;
-reg a7ddrphy_rddata_en_tappeddelayline1 = 1'd0;
-reg a7ddrphy_rddata_en_tappeddelayline2 = 1'd0;
-reg a7ddrphy_rddata_en_tappeddelayline3 = 1'd0;
-reg a7ddrphy_rddata_en_tappeddelayline4 = 1'd0;
-reg a7ddrphy_rddata_en_tappeddelayline5 = 1'd0;
-reg a7ddrphy_rddata_en_tappeddelayline6 = 1'd0;
-reg a7ddrphy_rddata_en_tappeddelayline7 = 1'd0;
-reg a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
-reg a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
-reg a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
-wire [13:0] litedramcore_slave_p0_address;
-wire [2:0] litedramcore_slave_p0_bank;
-wire litedramcore_slave_p0_cas_n;
-wire litedramcore_slave_p0_cs_n;
-wire litedramcore_slave_p0_ras_n;
-wire litedramcore_slave_p0_we_n;
-wire litedramcore_slave_p0_cke;
-wire litedramcore_slave_p0_odt;
-wire litedramcore_slave_p0_reset_n;
-wire litedramcore_slave_p0_act_n;
-wire [31:0] litedramcore_slave_p0_wrdata;
-wire litedramcore_slave_p0_wrdata_en;
-wire [3:0] litedramcore_slave_p0_wrdata_mask;
-wire litedramcore_slave_p0_rddata_en;
-reg [31:0] litedramcore_slave_p0_rddata = 32'd0;
-reg litedramcore_slave_p0_rddata_valid = 1'd0;
-wire [13:0] litedramcore_slave_p1_address;
-wire [2:0] litedramcore_slave_p1_bank;
-wire litedramcore_slave_p1_cas_n;
-wire litedramcore_slave_p1_cs_n;
-wire litedramcore_slave_p1_ras_n;
-wire litedramcore_slave_p1_we_n;
-wire litedramcore_slave_p1_cke;
-wire litedramcore_slave_p1_odt;
-wire litedramcore_slave_p1_reset_n;
-wire litedramcore_slave_p1_act_n;
-wire [31:0] litedramcore_slave_p1_wrdata;
-wire litedramcore_slave_p1_wrdata_en;
-wire [3:0] litedramcore_slave_p1_wrdata_mask;
-wire litedramcore_slave_p1_rddata_en;
-reg [31:0] litedramcore_slave_p1_rddata = 32'd0;
-reg litedramcore_slave_p1_rddata_valid = 1'd0;
-wire [13:0] litedramcore_slave_p2_address;
-wire [2:0] litedramcore_slave_p2_bank;
-wire litedramcore_slave_p2_cas_n;
-wire litedramcore_slave_p2_cs_n;
-wire litedramcore_slave_p2_ras_n;
-wire litedramcore_slave_p2_we_n;
-wire litedramcore_slave_p2_cke;
-wire litedramcore_slave_p2_odt;
-wire litedramcore_slave_p2_reset_n;
-wire litedramcore_slave_p2_act_n;
-wire [31:0] litedramcore_slave_p2_wrdata;
-wire litedramcore_slave_p2_wrdata_en;
-wire [3:0] litedramcore_slave_p2_wrdata_mask;
-wire litedramcore_slave_p2_rddata_en;
-reg [31:0] litedramcore_slave_p2_rddata = 32'd0;
-reg litedramcore_slave_p2_rddata_valid = 1'd0;
-wire [13:0] litedramcore_slave_p3_address;
-wire [2:0] litedramcore_slave_p3_bank;
-wire litedramcore_slave_p3_cas_n;
-wire litedramcore_slave_p3_cs_n;
-wire litedramcore_slave_p3_ras_n;
-wire litedramcore_slave_p3_we_n;
-wire litedramcore_slave_p3_cke;
-wire litedramcore_slave_p3_odt;
-wire litedramcore_slave_p3_reset_n;
-wire litedramcore_slave_p3_act_n;
-wire [31:0] litedramcore_slave_p3_wrdata;
-wire litedramcore_slave_p3_wrdata_en;
-wire [3:0] litedramcore_slave_p3_wrdata_mask;
-wire litedramcore_slave_p3_rddata_en;
-reg [31:0] litedramcore_slave_p3_rddata = 32'd0;
-reg litedramcore_slave_p3_rddata_valid = 1'd0;
-reg [13:0] litedramcore_master_p0_address = 14'd0;
-reg [2:0] litedramcore_master_p0_bank = 3'd0;
-reg litedramcore_master_p0_cas_n = 1'd1;
-reg litedramcore_master_p0_cs_n = 1'd1;
-reg litedramcore_master_p0_ras_n = 1'd1;
-reg litedramcore_master_p0_we_n = 1'd1;
-reg litedramcore_master_p0_cke = 1'd0;
-reg litedramcore_master_p0_odt = 1'd0;
-reg litedramcore_master_p0_reset_n = 1'd0;
-reg litedramcore_master_p0_act_n = 1'd1;
-reg [31:0] litedramcore_master_p0_wrdata = 32'd0;
-reg litedramcore_master_p0_wrdata_en = 1'd0;
-reg [3:0] litedramcore_master_p0_wrdata_mask = 4'd0;
-reg litedramcore_master_p0_rddata_en = 1'd0;
-wire [31:0] litedramcore_master_p0_rddata;
-wire litedramcore_master_p0_rddata_valid;
-reg [13:0] litedramcore_master_p1_address = 14'd0;
-reg [2:0] litedramcore_master_p1_bank = 3'd0;
-reg litedramcore_master_p1_cas_n = 1'd1;
-reg litedramcore_master_p1_cs_n = 1'd1;
-reg litedramcore_master_p1_ras_n = 1'd1;
-reg litedramcore_master_p1_we_n = 1'd1;
-reg litedramcore_master_p1_cke = 1'd0;
-reg litedramcore_master_p1_odt = 1'd0;
-reg litedramcore_master_p1_reset_n = 1'd0;
-reg litedramcore_master_p1_act_n = 1'd1;
-reg [31:0] litedramcore_master_p1_wrdata = 32'd0;
-reg litedramcore_master_p1_wrdata_en = 1'd0;
-reg [3:0] litedramcore_master_p1_wrdata_mask = 4'd0;
-reg litedramcore_master_p1_rddata_en = 1'd0;
-wire [31:0] litedramcore_master_p1_rddata;
-wire litedramcore_master_p1_rddata_valid;
-reg [13:0] litedramcore_master_p2_address = 14'd0;
-reg [2:0] litedramcore_master_p2_bank = 3'd0;
-reg litedramcore_master_p2_cas_n = 1'd1;
-reg litedramcore_master_p2_cs_n = 1'd1;
-reg litedramcore_master_p2_ras_n = 1'd1;
-reg litedramcore_master_p2_we_n = 1'd1;
-reg litedramcore_master_p2_cke = 1'd0;
-reg litedramcore_master_p2_odt = 1'd0;
-reg litedramcore_master_p2_reset_n = 1'd0;
-reg litedramcore_master_p2_act_n = 1'd1;
-reg [31:0] litedramcore_master_p2_wrdata = 32'd0;
-reg litedramcore_master_p2_wrdata_en = 1'd0;
-reg [3:0] litedramcore_master_p2_wrdata_mask = 4'd0;
-reg litedramcore_master_p2_rddata_en = 1'd0;
-wire [31:0] litedramcore_master_p2_rddata;
-wire litedramcore_master_p2_rddata_valid;
-reg [13:0] litedramcore_master_p3_address = 14'd0;
-reg [2:0] litedramcore_master_p3_bank = 3'd0;
-reg litedramcore_master_p3_cas_n = 1'd1;
-reg litedramcore_master_p3_cs_n = 1'd1;
-reg litedramcore_master_p3_ras_n = 1'd1;
-reg litedramcore_master_p3_we_n = 1'd1;
-reg litedramcore_master_p3_cke = 1'd0;
-reg litedramcore_master_p3_odt = 1'd0;
-reg litedramcore_master_p3_reset_n = 1'd0;
-reg litedramcore_master_p3_act_n = 1'd1;
-reg [31:0] litedramcore_master_p3_wrdata = 32'd0;
-reg litedramcore_master_p3_wrdata_en = 1'd0;
-reg [3:0] litedramcore_master_p3_wrdata_mask = 4'd0;
-reg litedramcore_master_p3_rddata_en = 1'd0;
-wire [31:0] litedramcore_master_p3_rddata;
-wire litedramcore_master_p3_rddata_valid;
-wire [13:0] litedramcore_csr_dfi_p0_address;
-wire [2:0] litedramcore_csr_dfi_p0_bank;
-reg litedramcore_csr_dfi_p0_cas_n = 1'd1;
-reg litedramcore_csr_dfi_p0_cs_n = 1'd1;
-reg litedramcore_csr_dfi_p0_ras_n = 1'd1;
-reg litedramcore_csr_dfi_p0_we_n = 1'd1;
-wire litedramcore_csr_dfi_p0_cke;
-wire litedramcore_csr_dfi_p0_odt;
-wire litedramcore_csr_dfi_p0_reset_n;
-reg litedramcore_csr_dfi_p0_act_n = 1'd1;
-wire [31:0] litedramcore_csr_dfi_p0_wrdata;
-wire litedramcore_csr_dfi_p0_wrdata_en;
-wire [3:0] litedramcore_csr_dfi_p0_wrdata_mask;
-wire litedramcore_csr_dfi_p0_rddata_en;
-reg [31:0] litedramcore_csr_dfi_p0_rddata = 32'd0;
-reg litedramcore_csr_dfi_p0_rddata_valid = 1'd0;
-wire [13:0] litedramcore_csr_dfi_p1_address;
-wire [2:0] litedramcore_csr_dfi_p1_bank;
-reg litedramcore_csr_dfi_p1_cas_n = 1'd1;
-reg litedramcore_csr_dfi_p1_cs_n = 1'd1;
-reg litedramcore_csr_dfi_p1_ras_n = 1'd1;
-reg litedramcore_csr_dfi_p1_we_n = 1'd1;
-wire litedramcore_csr_dfi_p1_cke;
-wire litedramcore_csr_dfi_p1_odt;
-wire litedramcore_csr_dfi_p1_reset_n;
-reg litedramcore_csr_dfi_p1_act_n = 1'd1;
-wire [31:0] litedramcore_csr_dfi_p1_wrdata;
-wire litedramcore_csr_dfi_p1_wrdata_en;
-wire [3:0] litedramcore_csr_dfi_p1_wrdata_mask;
-wire litedramcore_csr_dfi_p1_rddata_en;
-reg [31:0] litedramcore_csr_dfi_p1_rddata = 32'd0;
-reg litedramcore_csr_dfi_p1_rddata_valid = 1'd0;
-wire [13:0] litedramcore_csr_dfi_p2_address;
-wire [2:0] litedramcore_csr_dfi_p2_bank;
-reg litedramcore_csr_dfi_p2_cas_n = 1'd1;
-reg litedramcore_csr_dfi_p2_cs_n = 1'd1;
-reg litedramcore_csr_dfi_p2_ras_n = 1'd1;
-reg litedramcore_csr_dfi_p2_we_n = 1'd1;
-wire litedramcore_csr_dfi_p2_cke;
-wire litedramcore_csr_dfi_p2_odt;
-wire litedramcore_csr_dfi_p2_reset_n;
-reg litedramcore_csr_dfi_p2_act_n = 1'd1;
-wire [31:0] litedramcore_csr_dfi_p2_wrdata;
-wire litedramcore_csr_dfi_p2_wrdata_en;
-wire [3:0] litedramcore_csr_dfi_p2_wrdata_mask;
-wire litedramcore_csr_dfi_p2_rddata_en;
-reg [31:0] litedramcore_csr_dfi_p2_rddata = 32'd0;
-reg litedramcore_csr_dfi_p2_rddata_valid = 1'd0;
-wire [13:0] litedramcore_csr_dfi_p3_address;
-wire [2:0] litedramcore_csr_dfi_p3_bank;
-reg litedramcore_csr_dfi_p3_cas_n = 1'd1;
-reg litedramcore_csr_dfi_p3_cs_n = 1'd1;
-reg litedramcore_csr_dfi_p3_ras_n = 1'd1;
-reg litedramcore_csr_dfi_p3_we_n = 1'd1;
-wire litedramcore_csr_dfi_p3_cke;
-wire litedramcore_csr_dfi_p3_odt;
-wire litedramcore_csr_dfi_p3_reset_n;
-reg litedramcore_csr_dfi_p3_act_n = 1'd1;
-wire [31:0] litedramcore_csr_dfi_p3_wrdata;
-wire litedramcore_csr_dfi_p3_wrdata_en;
-wire [3:0] litedramcore_csr_dfi_p3_wrdata_mask;
-wire litedramcore_csr_dfi_p3_rddata_en;
-reg [31:0] litedramcore_csr_dfi_p3_rddata = 32'd0;
-reg litedramcore_csr_dfi_p3_rddata_valid = 1'd0;
-reg [13:0] litedramcore_ext_dfi_p0_address = 14'd0;
-reg [2:0] litedramcore_ext_dfi_p0_bank = 3'd0;
-reg litedramcore_ext_dfi_p0_cas_n = 1'd1;
-reg litedramcore_ext_dfi_p0_cs_n = 1'd1;
-reg litedramcore_ext_dfi_p0_ras_n = 1'd1;
-reg litedramcore_ext_dfi_p0_we_n = 1'd1;
-reg litedramcore_ext_dfi_p0_cke = 1'd0;
-reg litedramcore_ext_dfi_p0_odt = 1'd0;
-reg litedramcore_ext_dfi_p0_reset_n = 1'd0;
-reg litedramcore_ext_dfi_p0_act_n = 1'd1;
-reg [31:0] litedramcore_ext_dfi_p0_wrdata = 32'd0;
-reg litedramcore_ext_dfi_p0_wrdata_en = 1'd0;
-reg [3:0] litedramcore_ext_dfi_p0_wrdata_mask = 4'd0;
-reg litedramcore_ext_dfi_p0_rddata_en = 1'd0;
-reg [31:0] litedramcore_ext_dfi_p0_rddata = 32'd0;
-reg litedramcore_ext_dfi_p0_rddata_valid = 1'd0;
-reg [13:0] litedramcore_ext_dfi_p1_address = 14'd0;
-reg [2:0] litedramcore_ext_dfi_p1_bank = 3'd0;
-reg litedramcore_ext_dfi_p1_cas_n = 1'd1;
-reg litedramcore_ext_dfi_p1_cs_n = 1'd1;
-reg litedramcore_ext_dfi_p1_ras_n = 1'd1;
-reg litedramcore_ext_dfi_p1_we_n = 1'd1;
-reg litedramcore_ext_dfi_p1_cke = 1'd0;
-reg litedramcore_ext_dfi_p1_odt = 1'd0;
-reg litedramcore_ext_dfi_p1_reset_n = 1'd0;
-reg litedramcore_ext_dfi_p1_act_n = 1'd1;
-reg [31:0] litedramcore_ext_dfi_p1_wrdata = 32'd0;
-reg litedramcore_ext_dfi_p1_wrdata_en = 1'd0;
-reg [3:0] litedramcore_ext_dfi_p1_wrdata_mask = 4'd0;
-reg litedramcore_ext_dfi_p1_rddata_en = 1'd0;
-reg [31:0] litedramcore_ext_dfi_p1_rddata = 32'd0;
-reg litedramcore_ext_dfi_p1_rddata_valid = 1'd0;
-reg [13:0] litedramcore_ext_dfi_p2_address = 14'd0;
-reg [2:0] litedramcore_ext_dfi_p2_bank = 3'd0;
-reg litedramcore_ext_dfi_p2_cas_n = 1'd1;
-reg litedramcore_ext_dfi_p2_cs_n = 1'd1;
-reg litedramcore_ext_dfi_p2_ras_n = 1'd1;
-reg litedramcore_ext_dfi_p2_we_n = 1'd1;
-reg litedramcore_ext_dfi_p2_cke = 1'd0;
-reg litedramcore_ext_dfi_p2_odt = 1'd0;
-reg litedramcore_ext_dfi_p2_reset_n = 1'd0;
-reg litedramcore_ext_dfi_p2_act_n = 1'd1;
-reg [31:0] litedramcore_ext_dfi_p2_wrdata = 32'd0;
-reg litedramcore_ext_dfi_p2_wrdata_en = 1'd0;
-reg [3:0] litedramcore_ext_dfi_p2_wrdata_mask = 4'd0;
-reg litedramcore_ext_dfi_p2_rddata_en = 1'd0;
-reg [31:0] litedramcore_ext_dfi_p2_rddata = 32'd0;
-reg litedramcore_ext_dfi_p2_rddata_valid = 1'd0;
-reg [13:0] litedramcore_ext_dfi_p3_address = 14'd0;
-reg [2:0] litedramcore_ext_dfi_p3_bank = 3'd0;
-reg litedramcore_ext_dfi_p3_cas_n = 1'd1;
-reg litedramcore_ext_dfi_p3_cs_n = 1'd1;
-reg litedramcore_ext_dfi_p3_ras_n = 1'd1;
-reg litedramcore_ext_dfi_p3_we_n = 1'd1;
-reg litedramcore_ext_dfi_p3_cke = 1'd0;
-reg litedramcore_ext_dfi_p3_odt = 1'd0;
-reg litedramcore_ext_dfi_p3_reset_n = 1'd0;
-reg litedramcore_ext_dfi_p3_act_n = 1'd1;
-reg [31:0] litedramcore_ext_dfi_p3_wrdata = 32'd0;
-reg litedramcore_ext_dfi_p3_wrdata_en = 1'd0;
-reg [3:0] litedramcore_ext_dfi_p3_wrdata_mask = 4'd0;
-reg litedramcore_ext_dfi_p3_rddata_en = 1'd0;
-reg [31:0] litedramcore_ext_dfi_p3_rddata = 32'd0;
-reg litedramcore_ext_dfi_p3_rddata_valid = 1'd0;
-reg litedramcore_ext_dfi_sel = 1'd0;
-wire litedramcore_sel;
-wire litedramcore_cke;
-wire litedramcore_odt;
-wire litedramcore_reset_n;
-reg [3:0] litedramcore_storage = 4'd1;
-reg litedramcore_re = 1'd0;
-wire litedramcore_phaseinjector0_csrfield_cs;
-wire litedramcore_phaseinjector0_csrfield_we;
-wire litedramcore_phaseinjector0_csrfield_cas;
-wire litedramcore_phaseinjector0_csrfield_ras;
-wire litedramcore_phaseinjector0_csrfield_wren;
-wire litedramcore_phaseinjector0_csrfield_rden;
-reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0;
-reg litedramcore_phaseinjector0_command_re = 1'd0;
-reg litedramcore_phaseinjector0_command_issue_re = 1'd0;
-wire litedramcore_phaseinjector0_command_issue_r;
-reg litedramcore_phaseinjector0_command_issue_we = 1'd0;
-reg litedramcore_phaseinjector0_command_issue_w = 1'd0;
-reg [13:0] litedramcore_phaseinjector0_address_storage = 14'd0;
-reg litedramcore_phaseinjector0_address_re = 1'd0;
-reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0;
-reg litedramcore_phaseinjector0_baddress_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector0_wrdata_storage = 32'd0;
-reg litedramcore_phaseinjector0_wrdata_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector0_rddata_status = 32'd0;
-wire litedramcore_phaseinjector0_rddata_we;
-reg litedramcore_phaseinjector0_rddata_re = 1'd0;
-wire litedramcore_phaseinjector1_csrfield_cs;
-wire litedramcore_phaseinjector1_csrfield_we;
-wire litedramcore_phaseinjector1_csrfield_cas;
-wire litedramcore_phaseinjector1_csrfield_ras;
-wire litedramcore_phaseinjector1_csrfield_wren;
-wire litedramcore_phaseinjector1_csrfield_rden;
-reg [5:0] litedramcore_phaseinjector1_command_storage = 6'd0;
-reg litedramcore_phaseinjector1_command_re = 1'd0;
-reg litedramcore_phaseinjector1_command_issue_re = 1'd0;
-wire litedramcore_phaseinjector1_command_issue_r;
-reg litedramcore_phaseinjector1_command_issue_we = 1'd0;
-reg litedramcore_phaseinjector1_command_issue_w = 1'd0;
-reg [13:0] litedramcore_phaseinjector1_address_storage = 14'd0;
-reg litedramcore_phaseinjector1_address_re = 1'd0;
-reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0;
-reg litedramcore_phaseinjector1_baddress_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector1_wrdata_storage = 32'd0;
-reg litedramcore_phaseinjector1_wrdata_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector1_rddata_status = 32'd0;
-wire litedramcore_phaseinjector1_rddata_we;
-reg litedramcore_phaseinjector1_rddata_re = 1'd0;
-wire litedramcore_phaseinjector2_csrfield_cs;
-wire litedramcore_phaseinjector2_csrfield_we;
-wire litedramcore_phaseinjector2_csrfield_cas;
-wire litedramcore_phaseinjector2_csrfield_ras;
-wire litedramcore_phaseinjector2_csrfield_wren;
-wire litedramcore_phaseinjector2_csrfield_rden;
-reg [5:0] litedramcore_phaseinjector2_command_storage = 6'd0;
-reg litedramcore_phaseinjector2_command_re = 1'd0;
-reg litedramcore_phaseinjector2_command_issue_re = 1'd0;
-wire litedramcore_phaseinjector2_command_issue_r;
-reg litedramcore_phaseinjector2_command_issue_we = 1'd0;
-reg litedramcore_phaseinjector2_command_issue_w = 1'd0;
-reg [13:0] litedramcore_phaseinjector2_address_storage = 14'd0;
-reg litedramcore_phaseinjector2_address_re = 1'd0;
-reg [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0;
-reg litedramcore_phaseinjector2_baddress_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector2_wrdata_storage = 32'd0;
-reg litedramcore_phaseinjector2_wrdata_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector2_rddata_status = 32'd0;
-wire litedramcore_phaseinjector2_rddata_we;
-reg litedramcore_phaseinjector2_rddata_re = 1'd0;
-wire litedramcore_phaseinjector3_csrfield_cs;
-wire litedramcore_phaseinjector3_csrfield_we;
-wire litedramcore_phaseinjector3_csrfield_cas;
-wire litedramcore_phaseinjector3_csrfield_ras;
-wire litedramcore_phaseinjector3_csrfield_wren;
-wire litedramcore_phaseinjector3_csrfield_rden;
-reg [5:0] litedramcore_phaseinjector3_command_storage = 6'd0;
-reg litedramcore_phaseinjector3_command_re = 1'd0;
-reg litedramcore_phaseinjector3_command_issue_re = 1'd0;
-wire litedramcore_phaseinjector3_command_issue_r;
-reg litedramcore_phaseinjector3_command_issue_we = 1'd0;
-reg litedramcore_phaseinjector3_command_issue_w = 1'd0;
-reg [13:0] litedramcore_phaseinjector3_address_storage = 14'd0;
-reg litedramcore_phaseinjector3_address_re = 1'd0;
-reg [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0;
-reg litedramcore_phaseinjector3_baddress_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector3_wrdata_storage = 32'd0;
-reg litedramcore_phaseinjector3_wrdata_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector3_rddata_status = 32'd0;
-wire litedramcore_phaseinjector3_rddata_we;
-reg litedramcore_phaseinjector3_rddata_re = 1'd0;
-wire litedramcore_interface_bank0_valid;
-wire litedramcore_interface_bank0_ready;
-wire litedramcore_interface_bank0_we;
-wire [20:0] litedramcore_interface_bank0_addr;
-wire litedramcore_interface_bank0_lock;
-wire litedramcore_interface_bank0_wdata_ready;
-wire litedramcore_interface_bank0_rdata_valid;
-wire litedramcore_interface_bank1_valid;
-wire litedramcore_interface_bank1_ready;
-wire litedramcore_interface_bank1_we;
-wire [20:0] litedramcore_interface_bank1_addr;
-wire litedramcore_interface_bank1_lock;
-wire litedramcore_interface_bank1_wdata_ready;
-wire litedramcore_interface_bank1_rdata_valid;
-wire litedramcore_interface_bank2_valid;
-wire litedramcore_interface_bank2_ready;
-wire litedramcore_interface_bank2_we;
-wire [20:0] litedramcore_interface_bank2_addr;
-wire litedramcore_interface_bank2_lock;
-wire litedramcore_interface_bank2_wdata_ready;
-wire litedramcore_interface_bank2_rdata_valid;
-wire litedramcore_interface_bank3_valid;
-wire litedramcore_interface_bank3_ready;
-wire litedramcore_interface_bank3_we;
-wire [20:0] litedramcore_interface_bank3_addr;
-wire litedramcore_interface_bank3_lock;
-wire litedramcore_interface_bank3_wdata_ready;
-wire litedramcore_interface_bank3_rdata_valid;
-wire litedramcore_interface_bank4_valid;
-wire litedramcore_interface_bank4_ready;
-wire litedramcore_interface_bank4_we;
-wire [20:0] litedramcore_interface_bank4_addr;
-wire litedramcore_interface_bank4_lock;
-wire litedramcore_interface_bank4_wdata_ready;
-wire litedramcore_interface_bank4_rdata_valid;
-wire litedramcore_interface_bank5_valid;
-wire litedramcore_interface_bank5_ready;
-wire litedramcore_interface_bank5_we;
-wire [20:0] litedramcore_interface_bank5_addr;
-wire litedramcore_interface_bank5_lock;
-wire litedramcore_interface_bank5_wdata_ready;
-wire litedramcore_interface_bank5_rdata_valid;
-wire litedramcore_interface_bank6_valid;
-wire litedramcore_interface_bank6_ready;
-wire litedramcore_interface_bank6_we;
-wire [20:0] litedramcore_interface_bank6_addr;
-wire litedramcore_interface_bank6_lock;
-wire litedramcore_interface_bank6_wdata_ready;
-wire litedramcore_interface_bank6_rdata_valid;
-wire litedramcore_interface_bank7_valid;
-wire litedramcore_interface_bank7_ready;
-wire litedramcore_interface_bank7_we;
-wire [20:0] litedramcore_interface_bank7_addr;
-wire litedramcore_interface_bank7_lock;
-wire litedramcore_interface_bank7_wdata_ready;
-wire litedramcore_interface_bank7_rdata_valid;
-reg [127:0] litedramcore_interface_wdata = 128'd0;
-reg [15:0] litedramcore_interface_wdata_we = 16'd0;
-wire [127:0] litedramcore_interface_rdata;
-reg [13:0] litedramcore_dfi_p0_address = 14'd0;
-reg [2:0] litedramcore_dfi_p0_bank = 3'd0;
-reg litedramcore_dfi_p0_cas_n = 1'd1;
-reg litedramcore_dfi_p0_cs_n = 1'd1;
-reg litedramcore_dfi_p0_ras_n = 1'd1;
-reg litedramcore_dfi_p0_we_n = 1'd1;
-wire litedramcore_dfi_p0_cke;
-wire litedramcore_dfi_p0_odt;
-wire litedramcore_dfi_p0_reset_n;
-reg litedramcore_dfi_p0_act_n = 1'd1;
-wire [31:0] litedramcore_dfi_p0_wrdata;
-reg litedramcore_dfi_p0_wrdata_en = 1'd0;
-wire [3:0] litedramcore_dfi_p0_wrdata_mask;
-reg litedramcore_dfi_p0_rddata_en = 1'd0;
-wire [31:0] litedramcore_dfi_p0_rddata;
-wire litedramcore_dfi_p0_rddata_valid;
-reg [13:0] litedramcore_dfi_p1_address = 14'd0;
-reg [2:0] litedramcore_dfi_p1_bank = 3'd0;
-reg litedramcore_dfi_p1_cas_n = 1'd1;
-reg litedramcore_dfi_p1_cs_n = 1'd1;
-reg litedramcore_dfi_p1_ras_n = 1'd1;
-reg litedramcore_dfi_p1_we_n = 1'd1;
-wire litedramcore_dfi_p1_cke;
-wire litedramcore_dfi_p1_odt;
-wire litedramcore_dfi_p1_reset_n;
-reg litedramcore_dfi_p1_act_n = 1'd1;
-wire [31:0] litedramcore_dfi_p1_wrdata;
-reg litedramcore_dfi_p1_wrdata_en = 1'd0;
-wire [3:0] litedramcore_dfi_p1_wrdata_mask;
-reg litedramcore_dfi_p1_rddata_en = 1'd0;
-wire [31:0] litedramcore_dfi_p1_rddata;
-wire litedramcore_dfi_p1_rddata_valid;
-reg [13:0] litedramcore_dfi_p2_address = 14'd0;
-reg [2:0] litedramcore_dfi_p2_bank = 3'd0;
-reg litedramcore_dfi_p2_cas_n = 1'd1;
-reg litedramcore_dfi_p2_cs_n = 1'd1;
-reg litedramcore_dfi_p2_ras_n = 1'd1;
-reg litedramcore_dfi_p2_we_n = 1'd1;
-wire litedramcore_dfi_p2_cke;
-wire litedramcore_dfi_p2_odt;
-wire litedramcore_dfi_p2_reset_n;
-reg litedramcore_dfi_p2_act_n = 1'd1;
-wire [31:0] litedramcore_dfi_p2_wrdata;
-reg litedramcore_dfi_p2_wrdata_en = 1'd0;
-wire [3:0] litedramcore_dfi_p2_wrdata_mask;
-reg litedramcore_dfi_p2_rddata_en = 1'd0;
-wire [31:0] litedramcore_dfi_p2_rddata;
-wire litedramcore_dfi_p2_rddata_valid;
-reg [13:0] litedramcore_dfi_p3_address = 14'd0;
-reg [2:0] litedramcore_dfi_p3_bank = 3'd0;
-reg litedramcore_dfi_p3_cas_n = 1'd1;
-reg litedramcore_dfi_p3_cs_n = 1'd1;
-reg litedramcore_dfi_p3_ras_n = 1'd1;
-reg litedramcore_dfi_p3_we_n = 1'd1;
-wire litedramcore_dfi_p3_cke;
-wire litedramcore_dfi_p3_odt;
-wire litedramcore_dfi_p3_reset_n;
-reg litedramcore_dfi_p3_act_n = 1'd1;
-wire [31:0] litedramcore_dfi_p3_wrdata;
-reg litedramcore_dfi_p3_wrdata_en = 1'd0;
-wire [3:0] litedramcore_dfi_p3_wrdata_mask;
-reg litedramcore_dfi_p3_rddata_en = 1'd0;
-wire [31:0] litedramcore_dfi_p3_rddata;
-wire litedramcore_dfi_p3_rddata_valid;
-reg litedramcore_cmd_valid = 1'd0;
-reg litedramcore_cmd_ready = 1'd0;
-reg litedramcore_cmd_last = 1'd0;
-reg [13:0] litedramcore_cmd_payload_a = 14'd0;
-reg [2:0] litedramcore_cmd_payload_ba = 3'd0;
-reg litedramcore_cmd_payload_cas = 1'd0;
-reg litedramcore_cmd_payload_ras = 1'd0;
-reg litedramcore_cmd_payload_we = 1'd0;
-reg litedramcore_cmd_payload_is_read = 1'd0;
-reg litedramcore_cmd_payload_is_write = 1'd0;
-wire litedramcore_wants_refresh;
-wire litedramcore_wants_zqcs;
-wire litedramcore_timer_wait;
-wire litedramcore_timer_done0;
-wire [9:0] litedramcore_timer_count0;
-wire litedramcore_timer_done1;
-reg [9:0] litedramcore_timer_count1 = 10'd781;
-wire litedramcore_postponer_req_i;
-reg litedramcore_postponer_req_o = 1'd0;
-reg litedramcore_postponer_count = 1'd0;
-reg litedramcore_sequencer_start0 = 1'd0;
-wire litedramcore_sequencer_done0;
-wire litedramcore_sequencer_start1;
-reg litedramcore_sequencer_done1 = 1'd0;
-reg [5:0] litedramcore_sequencer_counter = 6'd0;
-reg litedramcore_sequencer_count = 1'd0;
-wire litedramcore_zqcs_timer_wait;
-wire litedramcore_zqcs_timer_done0;
-wire [26:0] litedramcore_zqcs_timer_count0;
-wire litedramcore_zqcs_timer_done1;
-reg [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999;
-reg litedramcore_zqcs_executer_start = 1'd0;
-reg litedramcore_zqcs_executer_done = 1'd0;
-reg [4:0] litedramcore_zqcs_executer_counter = 5'd0;
-wire litedramcore_bankmachine0_req_valid;
-wire litedramcore_bankmachine0_req_ready;
-wire litedramcore_bankmachine0_req_we;
-wire [20:0] litedramcore_bankmachine0_req_addr;
-wire litedramcore_bankmachine0_req_lock;
-reg litedramcore_bankmachine0_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine0_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine0_refresh_req;
-reg litedramcore_bankmachine0_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine0_cmd_valid = 1'd0;
-reg litedramcore_bankmachine0_cmd_ready = 1'd0;
-reg [13:0] litedramcore_bankmachine0_cmd_payload_a = 14'd0;
-wire [2:0] litedramcore_bankmachine0_cmd_payload_ba;
-reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine0_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine0_auto_precharge = 1'd0;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
-wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
-wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-reg [4:0] litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we;
-wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine0_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine0_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine0_cmd_buffer_sink_first;
-wire litedramcore_bankmachine0_cmd_buffer_sink_last;
-wire litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
-wire [20:0] litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine0_cmd_buffer_source_ready;
-reg litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] litedramcore_bankmachine0_row = 14'd0;
-reg litedramcore_bankmachine0_row_opened = 1'd0;
-wire litedramcore_bankmachine0_row_hit;
-reg litedramcore_bankmachine0_row_open = 1'd0;
-reg litedramcore_bankmachine0_row_close = 1'd0;
-reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine0_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine0_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine0_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine0_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine0_trccon_count = 3'd0;
-wire litedramcore_bankmachine0_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine0_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine0_trascon_count = 3'd0;
-wire litedramcore_bankmachine1_req_valid;
-wire litedramcore_bankmachine1_req_ready;
-wire litedramcore_bankmachine1_req_we;
-wire [20:0] litedramcore_bankmachine1_req_addr;
-wire litedramcore_bankmachine1_req_lock;
-reg litedramcore_bankmachine1_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine1_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine1_refresh_req;
-reg litedramcore_bankmachine1_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine1_cmd_valid = 1'd0;
-reg litedramcore_bankmachine1_cmd_ready = 1'd0;
-reg [13:0] litedramcore_bankmachine1_cmd_payload_a = 14'd0;
-wire [2:0] litedramcore_bankmachine1_cmd_payload_ba;
-reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine1_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine1_auto_precharge = 1'd0;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
-wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
-wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-reg [4:0] litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we;
-wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine1_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine1_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine1_cmd_buffer_sink_first;
-wire litedramcore_bankmachine1_cmd_buffer_sink_last;
-wire litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
-wire [20:0] litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine1_cmd_buffer_source_ready;
-reg litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] litedramcore_bankmachine1_row = 14'd0;
-reg litedramcore_bankmachine1_row_opened = 1'd0;
-wire litedramcore_bankmachine1_row_hit;
-reg litedramcore_bankmachine1_row_open = 1'd0;
-reg litedramcore_bankmachine1_row_close = 1'd0;
-reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine1_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine1_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine1_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine1_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine1_trccon_count = 3'd0;
-wire litedramcore_bankmachine1_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine1_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine1_trascon_count = 3'd0;
-wire litedramcore_bankmachine2_req_valid;
-wire litedramcore_bankmachine2_req_ready;
-wire litedramcore_bankmachine2_req_we;
-wire [20:0] litedramcore_bankmachine2_req_addr;
-wire litedramcore_bankmachine2_req_lock;
-reg litedramcore_bankmachine2_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine2_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine2_refresh_req;
-reg litedramcore_bankmachine2_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine2_cmd_valid = 1'd0;
-reg litedramcore_bankmachine2_cmd_ready = 1'd0;
-reg [13:0] litedramcore_bankmachine2_cmd_payload_a = 14'd0;
-wire [2:0] litedramcore_bankmachine2_cmd_payload_ba;
-reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine2_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine2_auto_precharge = 1'd0;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
-wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
-wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-reg [4:0] litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we;
-wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine2_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine2_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine2_cmd_buffer_sink_first;
-wire litedramcore_bankmachine2_cmd_buffer_sink_last;
-wire litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
-wire [20:0] litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine2_cmd_buffer_source_ready;
-reg litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] litedramcore_bankmachine2_row = 14'd0;
-reg litedramcore_bankmachine2_row_opened = 1'd0;
-wire litedramcore_bankmachine2_row_hit;
-reg litedramcore_bankmachine2_row_open = 1'd0;
-reg litedramcore_bankmachine2_row_close = 1'd0;
-reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine2_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine2_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine2_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine2_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine2_trccon_count = 3'd0;
-wire litedramcore_bankmachine2_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine2_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine2_trascon_count = 3'd0;
-wire litedramcore_bankmachine3_req_valid;
-wire litedramcore_bankmachine3_req_ready;
-wire litedramcore_bankmachine3_req_we;
-wire [20:0] litedramcore_bankmachine3_req_addr;
-wire litedramcore_bankmachine3_req_lock;
-reg litedramcore_bankmachine3_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine3_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine3_refresh_req;
-reg litedramcore_bankmachine3_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine3_cmd_valid = 1'd0;
-reg litedramcore_bankmachine3_cmd_ready = 1'd0;
-reg [13:0] litedramcore_bankmachine3_cmd_payload_a = 14'd0;
-wire [2:0] litedramcore_bankmachine3_cmd_payload_ba;
-reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine3_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine3_auto_precharge = 1'd0;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
-wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
-wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-reg [4:0] litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we;
-wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine3_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine3_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine3_cmd_buffer_sink_first;
-wire litedramcore_bankmachine3_cmd_buffer_sink_last;
-wire litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
-wire [20:0] litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine3_cmd_buffer_source_ready;
-reg litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] litedramcore_bankmachine3_row = 14'd0;
-reg litedramcore_bankmachine3_row_opened = 1'd0;
-wire litedramcore_bankmachine3_row_hit;
-reg litedramcore_bankmachine3_row_open = 1'd0;
-reg litedramcore_bankmachine3_row_close = 1'd0;
-reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine3_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine3_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine3_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine3_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine3_trccon_count = 3'd0;
-wire litedramcore_bankmachine3_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine3_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine3_trascon_count = 3'd0;
-wire litedramcore_bankmachine4_req_valid;
-wire litedramcore_bankmachine4_req_ready;
-wire litedramcore_bankmachine4_req_we;
-wire [20:0] litedramcore_bankmachine4_req_addr;
-wire litedramcore_bankmachine4_req_lock;
-reg litedramcore_bankmachine4_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine4_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine4_refresh_req;
-reg litedramcore_bankmachine4_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine4_cmd_valid = 1'd0;
-reg litedramcore_bankmachine4_cmd_ready = 1'd0;
-reg [13:0] litedramcore_bankmachine4_cmd_payload_a = 14'd0;
-wire [2:0] litedramcore_bankmachine4_cmd_payload_ba;
-reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine4_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine4_auto_precharge = 1'd0;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
-wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
-wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-reg [4:0] litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we;
-wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine4_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine4_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine4_cmd_buffer_sink_first;
-wire litedramcore_bankmachine4_cmd_buffer_sink_last;
-wire litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
-wire [20:0] litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine4_cmd_buffer_source_ready;
-reg litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] litedramcore_bankmachine4_row = 14'd0;
-reg litedramcore_bankmachine4_row_opened = 1'd0;
-wire litedramcore_bankmachine4_row_hit;
-reg litedramcore_bankmachine4_row_open = 1'd0;
-reg litedramcore_bankmachine4_row_close = 1'd0;
-reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine4_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine4_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine4_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine4_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine4_trccon_count = 3'd0;
-wire litedramcore_bankmachine4_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine4_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine4_trascon_count = 3'd0;
-wire litedramcore_bankmachine5_req_valid;
-wire litedramcore_bankmachine5_req_ready;
-wire litedramcore_bankmachine5_req_we;
-wire [20:0] litedramcore_bankmachine5_req_addr;
-wire litedramcore_bankmachine5_req_lock;
-reg litedramcore_bankmachine5_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine5_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine5_refresh_req;
-reg litedramcore_bankmachine5_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine5_cmd_valid = 1'd0;
-reg litedramcore_bankmachine5_cmd_ready = 1'd0;
-reg [13:0] litedramcore_bankmachine5_cmd_payload_a = 14'd0;
-wire [2:0] litedramcore_bankmachine5_cmd_payload_ba;
-reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine5_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine5_auto_precharge = 1'd0;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
-wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
-wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-reg [4:0] litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we;
-wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine5_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine5_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine5_cmd_buffer_sink_first;
-wire litedramcore_bankmachine5_cmd_buffer_sink_last;
-wire litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
-wire [20:0] litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine5_cmd_buffer_source_ready;
-reg litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] litedramcore_bankmachine5_row = 14'd0;
-reg litedramcore_bankmachine5_row_opened = 1'd0;
-wire litedramcore_bankmachine5_row_hit;
-reg litedramcore_bankmachine5_row_open = 1'd0;
-reg litedramcore_bankmachine5_row_close = 1'd0;
-reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine5_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine5_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine5_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine5_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine5_trccon_count = 3'd0;
-wire litedramcore_bankmachine5_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine5_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine5_trascon_count = 3'd0;
-wire litedramcore_bankmachine6_req_valid;
-wire litedramcore_bankmachine6_req_ready;
-wire litedramcore_bankmachine6_req_we;
-wire [20:0] litedramcore_bankmachine6_req_addr;
-wire litedramcore_bankmachine6_req_lock;
-reg litedramcore_bankmachine6_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine6_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine6_refresh_req;
-reg litedramcore_bankmachine6_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine6_cmd_valid = 1'd0;
-reg litedramcore_bankmachine6_cmd_ready = 1'd0;
-reg [13:0] litedramcore_bankmachine6_cmd_payload_a = 14'd0;
-wire [2:0] litedramcore_bankmachine6_cmd_payload_ba;
-reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine6_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine6_auto_precharge = 1'd0;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
-wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
-wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-reg [4:0] litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we;
-wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine6_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine6_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine6_cmd_buffer_sink_first;
-wire litedramcore_bankmachine6_cmd_buffer_sink_last;
-wire litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
-wire [20:0] litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine6_cmd_buffer_source_ready;
-reg litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] litedramcore_bankmachine6_row = 14'd0;
-reg litedramcore_bankmachine6_row_opened = 1'd0;
-wire litedramcore_bankmachine6_row_hit;
-reg litedramcore_bankmachine6_row_open = 1'd0;
-reg litedramcore_bankmachine6_row_close = 1'd0;
-reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine6_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine6_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine6_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine6_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine6_trccon_count = 3'd0;
-wire litedramcore_bankmachine6_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine6_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine6_trascon_count = 3'd0;
-wire litedramcore_bankmachine7_req_valid;
-wire litedramcore_bankmachine7_req_ready;
-wire litedramcore_bankmachine7_req_we;
-wire [20:0] litedramcore_bankmachine7_req_addr;
-wire litedramcore_bankmachine7_req_lock;
-reg litedramcore_bankmachine7_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine7_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine7_refresh_req;
-reg litedramcore_bankmachine7_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine7_cmd_valid = 1'd0;
-reg litedramcore_bankmachine7_cmd_ready = 1'd0;
-reg [13:0] litedramcore_bankmachine7_cmd_payload_a = 14'd0;
-wire [2:0] litedramcore_bankmachine7_cmd_payload_ba;
-reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine7_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine7_auto_precharge = 1'd0;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
-wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
-wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-reg [4:0] litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we;
-wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine7_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine7_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine7_cmd_buffer_sink_first;
-wire litedramcore_bankmachine7_cmd_buffer_sink_last;
-wire litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
-wire [20:0] litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine7_cmd_buffer_source_ready;
-reg litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] litedramcore_bankmachine7_row = 14'd0;
-reg litedramcore_bankmachine7_row_opened = 1'd0;
-wire litedramcore_bankmachine7_row_hit;
-reg litedramcore_bankmachine7_row_open = 1'd0;
-reg litedramcore_bankmachine7_row_close = 1'd0;
-reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine7_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine7_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine7_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine7_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine7_trccon_count = 3'd0;
-wire litedramcore_bankmachine7_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine7_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine7_trascon_count = 3'd0;
-wire litedramcore_ras_allowed;
-wire litedramcore_cas_allowed;
-wire [1:0] litedramcore_rdcmdphase;
-wire [1:0] litedramcore_wrcmdphase;
-reg litedramcore_choose_cmd_want_reads = 1'd0;
-reg litedramcore_choose_cmd_want_writes = 1'd0;
-reg litedramcore_choose_cmd_want_cmds = 1'd0;
-reg litedramcore_choose_cmd_want_activates = 1'd0;
-wire litedramcore_choose_cmd_cmd_valid;
-reg litedramcore_choose_cmd_cmd_ready = 1'd0;
-wire [13:0] litedramcore_choose_cmd_cmd_payload_a;
-wire [2:0] litedramcore_choose_cmd_cmd_payload_ba;
-reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
-reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
-reg litedramcore_choose_cmd_cmd_payload_we = 1'd0;
-wire litedramcore_choose_cmd_cmd_payload_is_cmd;
-wire litedramcore_choose_cmd_cmd_payload_is_read;
-wire litedramcore_choose_cmd_cmd_payload_is_write;
-reg [7:0] litedramcore_choose_cmd_valids = 8'd0;
-wire [7:0] litedramcore_choose_cmd_request;
-reg [2:0] litedramcore_choose_cmd_grant = 3'd0;
-wire litedramcore_choose_cmd_ce;
-reg litedramcore_choose_req_want_reads = 1'd0;
-reg litedramcore_choose_req_want_writes = 1'd0;
-reg litedramcore_choose_req_want_cmds = 1'd0;
-reg litedramcore_choose_req_want_activates = 1'd0;
-wire litedramcore_choose_req_cmd_valid;
-reg litedramcore_choose_req_cmd_ready = 1'd0;
-wire [13:0] litedramcore_choose_req_cmd_payload_a;
-wire [2:0] litedramcore_choose_req_cmd_payload_ba;
-reg litedramcore_choose_req_cmd_payload_cas = 1'd0;
-reg litedramcore_choose_req_cmd_payload_ras = 1'd0;
-reg litedramcore_choose_req_cmd_payload_we = 1'd0;
-wire litedramcore_choose_req_cmd_payload_is_cmd;
-wire litedramcore_choose_req_cmd_payload_is_read;
-wire litedramcore_choose_req_cmd_payload_is_write;
-reg [7:0] litedramcore_choose_req_valids = 8'd0;
-wire [7:0] litedramcore_choose_req_request;
-reg [2:0] litedramcore_choose_req_grant = 3'd0;
-wire litedramcore_choose_req_ce;
-reg [13:0] litedramcore_nop_a = 14'd0;
-reg [2:0] litedramcore_nop_ba = 3'd0;
-reg [1:0] litedramcore_steerer_sel0 = 2'd0;
-reg [1:0] litedramcore_steerer_sel1 = 2'd0;
-reg [1:0] litedramcore_steerer_sel2 = 2'd0;
-reg [1:0] litedramcore_steerer_sel3 = 2'd0;
-reg litedramcore_steerer0 = 1'd1;
-reg litedramcore_steerer1 = 1'd1;
-reg litedramcore_steerer2 = 1'd1;
-reg litedramcore_steerer3 = 1'd1;
-reg litedramcore_steerer4 = 1'd1;
-reg litedramcore_steerer5 = 1'd1;
-reg litedramcore_steerer6 = 1'd1;
-reg litedramcore_steerer7 = 1'd1;
-wire litedramcore_trrdcon_valid;
-(* dont_touch = "true" *) reg litedramcore_trrdcon_ready = 1'd0;
-reg litedramcore_trrdcon_count = 1'd0;
-wire litedramcore_tfawcon_valid;
-(* dont_touch = "true" *) reg litedramcore_tfawcon_ready = 1'd1;
-wire [2:0] litedramcore_tfawcon_count;
-reg [4:0] litedramcore_tfawcon_window = 5'd0;
-wire litedramcore_tccdcon_valid;
-(* dont_touch = "true" *) reg litedramcore_tccdcon_ready = 1'd0;
-reg litedramcore_tccdcon_count = 1'd0;
-wire litedramcore_twtrcon_valid;
-(* dont_touch = "true" *) reg litedramcore_twtrcon_ready = 1'd0;
-reg [2:0] litedramcore_twtrcon_count = 3'd0;
-wire litedramcore_read_available;
-wire litedramcore_write_available;
-reg litedramcore_en0 = 1'd0;
-wire litedramcore_max_time0;
-reg [4:0] litedramcore_time0 = 5'd0;
-reg litedramcore_en1 = 1'd0;
-wire litedramcore_max_time1;
-reg [3:0] litedramcore_time1 = 4'd0;
-wire litedramcore_go_to_refresh;
-reg init_done_storage = 1'd0;
-reg init_done_re = 1'd0;
-reg init_error_storage = 1'd0;
-reg init_error_re = 1'd0;
-wire [29:0] wb_bus_adr;
-wire [31:0] wb_bus_dat_w;
-wire [31:0] wb_bus_dat_r;
-wire [3:0] wb_bus_sel;
-wire wb_bus_cyc;
-wire wb_bus_stb;
-wire wb_bus_ack;
-wire wb_bus_we;
-wire [2:0] wb_bus_cti;
-wire [1:0] wb_bus_bte;
-wire wb_bus_err;
-wire user_enable;
-wire user_port_cmd_valid;
-wire user_port_cmd_ready;
-wire user_port_cmd_payload_we;
-wire [23:0] user_port_cmd_payload_addr;
-wire user_port_wdata_valid;
-wire user_port_wdata_ready;
-wire [127:0] user_port_wdata_payload_data;
-wire [15:0] user_port_wdata_payload_we;
-wire user_port_rdata_valid;
-wire user_port_rdata_ready;
-wire [127:0] user_port_rdata_payload_data;
-reg [13:0] litedramcore_adr = 14'd0;
-reg litedramcore_we = 1'd0;
-reg [31:0] litedramcore_dat_w = 32'd0;
-wire [31:0] litedramcore_dat_r;
-wire [29:0] litedramcore_wishbone_adr;
-wire [31:0] litedramcore_wishbone_dat_w;
-reg [31:0] litedramcore_wishbone_dat_r = 32'd0;
-wire [3:0] litedramcore_wishbone_sel;
-wire litedramcore_wishbone_cyc;
-wire litedramcore_wishbone_stb;
-reg litedramcore_wishbone_ack = 1'd0;
-wire litedramcore_wishbone_we;
-wire [2:0] litedramcore_wishbone_cti;
-wire [1:0] litedramcore_wishbone_bte;
-reg litedramcore_wishbone_err = 1'd0;
-wire [13:0] interface0_bank_bus_adr;
-wire interface0_bank_bus_we;
-wire [31:0] interface0_bank_bus_dat_w;
-reg [31:0] interface0_bank_bus_dat_r = 32'd0;
-reg csrbank0_init_done0_re = 1'd0;
-wire csrbank0_init_done0_r;
-reg csrbank0_init_done0_we = 1'd0;
-wire csrbank0_init_done0_w;
-reg csrbank0_init_error0_re = 1'd0;
-wire csrbank0_init_error0_r;
-reg csrbank0_init_error0_we = 1'd0;
-wire csrbank0_init_error0_w;
-wire csrbank0_sel;
-wire [13:0] interface1_bank_bus_adr;
-wire interface1_bank_bus_we;
-wire [31:0] interface1_bank_bus_dat_w;
-reg [31:0] interface1_bank_bus_dat_r = 32'd0;
-reg csrbank1_rst0_re = 1'd0;
-wire csrbank1_rst0_r;
-reg csrbank1_rst0_we = 1'd0;
-wire csrbank1_rst0_w;
-reg csrbank1_dly_sel0_re = 1'd0;
-wire [1:0] csrbank1_dly_sel0_r;
-reg csrbank1_dly_sel0_we = 1'd0;
-wire [1:0] csrbank1_dly_sel0_w;
-reg csrbank1_half_sys8x_taps0_re = 1'd0;
-wire [4:0] csrbank1_half_sys8x_taps0_r;
-reg csrbank1_half_sys8x_taps0_we = 1'd0;
-wire [4:0] csrbank1_half_sys8x_taps0_w;
-reg csrbank1_wlevel_en0_re = 1'd0;
-wire csrbank1_wlevel_en0_r;
-reg csrbank1_wlevel_en0_we = 1'd0;
-wire csrbank1_wlevel_en0_w;
-reg csrbank1_rdphase0_re = 1'd0;
-wire [1:0] csrbank1_rdphase0_r;
-reg csrbank1_rdphase0_we = 1'd0;
-wire [1:0] csrbank1_rdphase0_w;
-reg csrbank1_wrphase0_re = 1'd0;
-wire [1:0] csrbank1_wrphase0_r;
-reg csrbank1_wrphase0_we = 1'd0;
-wire [1:0] csrbank1_wrphase0_w;
-wire csrbank1_sel;
-wire [13:0] interface2_bank_bus_adr;
-wire interface2_bank_bus_we;
-wire [31:0] interface2_bank_bus_dat_w;
-reg [31:0] interface2_bank_bus_dat_r = 32'd0;
-reg csrbank2_dfii_control0_re = 1'd0;
-wire [3:0] csrbank2_dfii_control0_r;
-reg csrbank2_dfii_control0_we = 1'd0;
-wire [3:0] csrbank2_dfii_control0_w;
-reg csrbank2_dfii_pi0_command0_re = 1'd0;
-wire [5:0] csrbank2_dfii_pi0_command0_r;
-reg csrbank2_dfii_pi0_command0_we = 1'd0;
-wire [5:0] csrbank2_dfii_pi0_command0_w;
-reg csrbank2_dfii_pi0_address0_re = 1'd0;
-wire [13:0] csrbank2_dfii_pi0_address0_r;
-reg csrbank2_dfii_pi0_address0_we = 1'd0;
-wire [13:0] csrbank2_dfii_pi0_address0_w;
-reg csrbank2_dfii_pi0_baddress0_re = 1'd0;
-wire [2:0] csrbank2_dfii_pi0_baddress0_r;
-reg csrbank2_dfii_pi0_baddress0_we = 1'd0;
-wire [2:0] csrbank2_dfii_pi0_baddress0_w;
-reg csrbank2_dfii_pi0_wrdata0_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi0_wrdata0_r;
-reg csrbank2_dfii_pi0_wrdata0_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi0_wrdata0_w;
-reg csrbank2_dfii_pi0_rddata_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi0_rddata_r;
-reg csrbank2_dfii_pi0_rddata_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi0_rddata_w;
-reg csrbank2_dfii_pi1_command0_re = 1'd0;
-wire [5:0] csrbank2_dfii_pi1_command0_r;
-reg csrbank2_dfii_pi1_command0_we = 1'd0;
-wire [5:0] csrbank2_dfii_pi1_command0_w;
-reg csrbank2_dfii_pi1_address0_re = 1'd0;
-wire [13:0] csrbank2_dfii_pi1_address0_r;
-reg csrbank2_dfii_pi1_address0_we = 1'd0;
-wire [13:0] csrbank2_dfii_pi1_address0_w;
-reg csrbank2_dfii_pi1_baddress0_re = 1'd0;
-wire [2:0] csrbank2_dfii_pi1_baddress0_r;
-reg csrbank2_dfii_pi1_baddress0_we = 1'd0;
-wire [2:0] csrbank2_dfii_pi1_baddress0_w;
-reg csrbank2_dfii_pi1_wrdata0_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi1_wrdata0_r;
-reg csrbank2_dfii_pi1_wrdata0_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi1_wrdata0_w;
-reg csrbank2_dfii_pi1_rddata_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi1_rddata_r;
-reg csrbank2_dfii_pi1_rddata_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi1_rddata_w;
-reg csrbank2_dfii_pi2_command0_re = 1'd0;
-wire [5:0] csrbank2_dfii_pi2_command0_r;
-reg csrbank2_dfii_pi2_command0_we = 1'd0;
-wire [5:0] csrbank2_dfii_pi2_command0_w;
-reg csrbank2_dfii_pi2_address0_re = 1'd0;
-wire [13:0] csrbank2_dfii_pi2_address0_r;
-reg csrbank2_dfii_pi2_address0_we = 1'd0;
-wire [13:0] csrbank2_dfii_pi2_address0_w;
-reg csrbank2_dfii_pi2_baddress0_re = 1'd0;
-wire [2:0] csrbank2_dfii_pi2_baddress0_r;
-reg csrbank2_dfii_pi2_baddress0_we = 1'd0;
-wire [2:0] csrbank2_dfii_pi2_baddress0_w;
-reg csrbank2_dfii_pi2_wrdata0_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi2_wrdata0_r;
-reg csrbank2_dfii_pi2_wrdata0_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi2_wrdata0_w;
-reg csrbank2_dfii_pi2_rddata_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi2_rddata_r;
-reg csrbank2_dfii_pi2_rddata_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi2_rddata_w;
-reg csrbank2_dfii_pi3_command0_re = 1'd0;
-wire [5:0] csrbank2_dfii_pi3_command0_r;
-reg csrbank2_dfii_pi3_command0_we = 1'd0;
-wire [5:0] csrbank2_dfii_pi3_command0_w;
-reg csrbank2_dfii_pi3_address0_re = 1'd0;
-wire [13:0] csrbank2_dfii_pi3_address0_r;
-reg csrbank2_dfii_pi3_address0_we = 1'd0;
-wire [13:0] csrbank2_dfii_pi3_address0_w;
-reg csrbank2_dfii_pi3_baddress0_re = 1'd0;
-wire [2:0] csrbank2_dfii_pi3_baddress0_r;
-reg csrbank2_dfii_pi3_baddress0_we = 1'd0;
-wire [2:0] csrbank2_dfii_pi3_baddress0_w;
-reg csrbank2_dfii_pi3_wrdata0_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi3_wrdata0_r;
-reg csrbank2_dfii_pi3_wrdata0_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi3_wrdata0_w;
-reg csrbank2_dfii_pi3_rddata_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi3_rddata_r;
-reg csrbank2_dfii_pi3_rddata_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi3_rddata_w;
-wire csrbank2_sel;
-wire [13:0] csr_interconnect_adr;
-wire csr_interconnect_we;
-wire [31:0] csr_interconnect_dat_w;
-wire [31:0] csr_interconnect_dat_r;
-wire litedramcore_reset0;
-wire litedramcore_reset1;
-wire litedramcore_reset2;
-wire litedramcore_reset3;
-wire litedramcore_reset4;
-wire litedramcore_reset5;
-wire litedramcore_reset6;
-wire litedramcore_reset7;
-wire litedramcore_pll_fb;
-reg [1:0] litedramcore_refresher_state = 2'd0;
-reg [1:0] litedramcore_refresher_next_state = 2'd0;
-reg [3:0] litedramcore_bankmachine0_state = 4'd0;
-reg [3:0] litedramcore_bankmachine0_next_state = 4'd0;
-reg [3:0] litedramcore_bankmachine1_state = 4'd0;
-reg [3:0] litedramcore_bankmachine1_next_state = 4'd0;
-reg [3:0] litedramcore_bankmachine2_state = 4'd0;
-reg [3:0] litedramcore_bankmachine2_next_state = 4'd0;
-reg [3:0] litedramcore_bankmachine3_state = 4'd0;
-reg [3:0] litedramcore_bankmachine3_next_state = 4'd0;
-reg [3:0] litedramcore_bankmachine4_state = 4'd0;
-reg [3:0] litedramcore_bankmachine4_next_state = 4'd0;
-reg [3:0] litedramcore_bankmachine5_state = 4'd0;
-reg [3:0] litedramcore_bankmachine5_next_state = 4'd0;
-reg [3:0] litedramcore_bankmachine6_state = 4'd0;
-reg [3:0] litedramcore_bankmachine6_next_state = 4'd0;
-reg [3:0] litedramcore_bankmachine7_state = 4'd0;
-reg [3:0] litedramcore_bankmachine7_next_state = 4'd0;
-reg [3:0] litedramcore_multiplexer_state = 4'd0;
-reg [3:0] litedramcore_multiplexer_next_state = 4'd0;
-wire litedramcore_roundrobin0_request;
-wire litedramcore_roundrobin0_grant;
-wire litedramcore_roundrobin0_ce;
-wire litedramcore_roundrobin1_request;
-wire litedramcore_roundrobin1_grant;
-wire litedramcore_roundrobin1_ce;
-wire litedramcore_roundrobin2_request;
-wire litedramcore_roundrobin2_grant;
-wire litedramcore_roundrobin2_ce;
-wire litedramcore_roundrobin3_request;
-wire litedramcore_roundrobin3_grant;
-wire litedramcore_roundrobin3_ce;
-wire litedramcore_roundrobin4_request;
-wire litedramcore_roundrobin4_grant;
-wire litedramcore_roundrobin4_ce;
-wire litedramcore_roundrobin5_request;
-wire litedramcore_roundrobin5_grant;
-wire litedramcore_roundrobin5_ce;
-wire litedramcore_roundrobin6_request;
-wire litedramcore_roundrobin6_grant;
-wire litedramcore_roundrobin6_ce;
-wire litedramcore_roundrobin7_request;
-wire litedramcore_roundrobin7_grant;
-wire litedramcore_roundrobin7_ce;
-reg litedramcore_locked0 = 1'd0;
-reg litedramcore_locked1 = 1'd0;
-reg litedramcore_locked2 = 1'd0;
-reg litedramcore_locked3 = 1'd0;
-reg litedramcore_locked4 = 1'd0;
-reg litedramcore_locked5 = 1'd0;
-reg litedramcore_locked6 = 1'd0;
-reg litedramcore_locked7 = 1'd0;
-reg litedramcore_new_master_wdata_ready0 = 1'd0;
-reg litedramcore_new_master_wdata_ready1 = 1'd0;
-reg litedramcore_new_master_rdata_valid0 = 1'd0;
-reg litedramcore_new_master_rdata_valid1 = 1'd0;
-reg litedramcore_new_master_rdata_valid2 = 1'd0;
-reg litedramcore_new_master_rdata_valid3 = 1'd0;
-reg litedramcore_new_master_rdata_valid4 = 1'd0;
-reg litedramcore_new_master_rdata_valid5 = 1'd0;
-reg litedramcore_new_master_rdata_valid6 = 1'd0;
-reg litedramcore_new_master_rdata_valid7 = 1'd0;
-reg litedramcore_new_master_rdata_valid8 = 1'd0;
-reg [1:0] litedramcore_state = 2'd0;
-reg [1:0] litedramcore_next_state = 2'd0;
-reg [31:0] litedramcore_dat_w_next_value0 = 32'd0;
-reg litedramcore_dat_w_next_value_ce0 = 1'd0;
-reg [13:0] litedramcore_adr_next_value1 = 14'd0;
-reg litedramcore_adr_next_value_ce1 = 1'd0;
-reg litedramcore_we_next_value2 = 1'd0;
-reg litedramcore_we_next_value_ce2 = 1'd0;
-reg rhs_array_muxed0 = 1'd0;
-reg [13:0] rhs_array_muxed1 = 14'd0;
-reg [2:0] rhs_array_muxed2 = 3'd0;
-reg rhs_array_muxed3 = 1'd0;
-reg rhs_array_muxed4 = 1'd0;
-reg rhs_array_muxed5 = 1'd0;
-reg t_array_muxed0 = 1'd0;
-reg t_array_muxed1 = 1'd0;
-reg t_array_muxed2 = 1'd0;
-reg rhs_array_muxed6 = 1'd0;
-reg [13:0] rhs_array_muxed7 = 14'd0;
-reg [2:0] rhs_array_muxed8 = 3'd0;
-reg rhs_array_muxed9 = 1'd0;
-reg rhs_array_muxed10 = 1'd0;
-reg rhs_array_muxed11 = 1'd0;
-reg t_array_muxed3 = 1'd0;
-reg t_array_muxed4 = 1'd0;
-reg t_array_muxed5 = 1'd0;
-reg [20:0] rhs_array_muxed12 = 21'd0;
-reg rhs_array_muxed13 = 1'd0;
-reg rhs_array_muxed14 = 1'd0;
-reg [20:0] rhs_array_muxed15 = 21'd0;
-reg rhs_array_muxed16 = 1'd0;
-reg rhs_array_muxed17 = 1'd0;
-reg [20:0] rhs_array_muxed18 = 21'd0;
-reg rhs_array_muxed19 = 1'd0;
-reg rhs_array_muxed20 = 1'd0;
-reg [20:0] rhs_array_muxed21 = 21'd0;
-reg rhs_array_muxed22 = 1'd0;
-reg rhs_array_muxed23 = 1'd0;
-reg [20:0] rhs_array_muxed24 = 21'd0;
-reg rhs_array_muxed25 = 1'd0;
-reg rhs_array_muxed26 = 1'd0;
-reg [20:0] rhs_array_muxed27 = 21'd0;
-reg rhs_array_muxed28 = 1'd0;
-reg rhs_array_muxed29 = 1'd0;
-reg [20:0] rhs_array_muxed30 = 21'd0;
-reg rhs_array_muxed31 = 1'd0;
-reg rhs_array_muxed32 = 1'd0;
-reg [20:0] rhs_array_muxed33 = 21'd0;
-reg rhs_array_muxed34 = 1'd0;
-reg rhs_array_muxed35 = 1'd0;
-reg [2:0] array_muxed0 = 3'd0;
-reg [13:0] array_muxed1 = 14'd0;
-reg array_muxed2 = 1'd0;
-reg array_muxed3 = 1'd0;
-reg array_muxed4 = 1'd0;
-reg array_muxed5 = 1'd0;
-reg array_muxed6 = 1'd0;
-reg [2:0] array_muxed7 = 3'd0;
-reg [13:0] array_muxed8 = 14'd0;
-reg array_muxed9 = 1'd0;
-reg array_muxed10 = 1'd0;
-reg array_muxed11 = 1'd0;
-reg array_muxed12 = 1'd0;
-reg array_muxed13 = 1'd0;
-reg [2:0] array_muxed14 = 3'd0;
-reg [13:0] array_muxed15 = 14'd0;
-reg array_muxed16 = 1'd0;
-reg array_muxed17 = 1'd0;
-reg array_muxed18 = 1'd0;
-reg array_muxed19 = 1'd0;
-reg array_muxed20 = 1'd0;
-reg [2:0] array_muxed21 = 3'd0;
-reg [13:0] array_muxed22 = 14'd0;
-reg array_muxed23 = 1'd0;
-reg array_muxed24 = 1'd0;
-reg array_muxed25 = 1'd0;
-reg array_muxed26 = 1'd0;
-reg array_muxed27 = 1'd0;
-wire xilinxasyncresetsynchronizerimpl0;
-wire xilinxasyncresetsynchronizerimpl0_rst_meta;
-wire xilinxasyncresetsynchronizerimpl1;
-wire xilinxasyncresetsynchronizerimpl1_rst_meta;
-wire xilinxasyncresetsynchronizerimpl2;
-wire xilinxasyncresetsynchronizerimpl2_rst_meta;
-wire xilinxasyncresetsynchronizerimpl2_expr;
-wire xilinxasyncresetsynchronizerimpl3;
-wire xilinxasyncresetsynchronizerimpl3_rst_meta;
-wire xilinxasyncresetsynchronizerimpl3_expr;
+reg rst_1 = 1'd0;
+wire sys_clk;
+wire sys_rst;
+wire sys4x_clk;
+wire sys4x_dqs_clk;
+wire iodelay_clk;
+wire iodelay_rst;
+wire reset;
+reg power_down = 1'd0;
+wire locked;
+wire clkin;
+wire clkout0;
+wire clkout_buf0;
+wire clkout1;
+wire clkout_buf1;
+wire clkout2;
+wire clkout_buf2;
+wire clkout3;
+wire clkout_buf3;
+reg [3:0] reset_counter = 4'd15;
+reg ic_reset = 1'd1;
+reg a7ddrphy_rst_storage = 1'd0;
+reg a7ddrphy_rst_re = 1'd0;
+reg [1:0] a7ddrphy_dly_sel_storage = 2'd0;
+reg a7ddrphy_dly_sel_re = 1'd0;
+reg [4:0] a7ddrphy_half_sys8x_taps_storage = 5'd8;
+reg a7ddrphy_half_sys8x_taps_re = 1'd0;
+reg a7ddrphy_wlevel_en_storage = 1'd0;
+reg a7ddrphy_wlevel_en_re = 1'd0;
+reg a7ddrphy_wlevel_strobe_re = 1'd0;
+wire a7ddrphy_wlevel_strobe_r;
+reg a7ddrphy_wlevel_strobe_we = 1'd0;
+reg a7ddrphy_wlevel_strobe_w = 1'd0;
+reg a7ddrphy_rdly_dq_rst_re = 1'd0;
+wire a7ddrphy_rdly_dq_rst_r;
+reg a7ddrphy_rdly_dq_rst_we = 1'd0;
+reg a7ddrphy_rdly_dq_rst_w = 1'd0;
+reg a7ddrphy_rdly_dq_inc_re = 1'd0;
+wire a7ddrphy_rdly_dq_inc_r;
+reg a7ddrphy_rdly_dq_inc_we = 1'd0;
+reg a7ddrphy_rdly_dq_inc_w = 1'd0;
+reg a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
+wire a7ddrphy_rdly_dq_bitslip_rst_r;
+reg a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
+reg a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
+reg a7ddrphy_rdly_dq_bitslip_re = 1'd0;
+wire a7ddrphy_rdly_dq_bitslip_r;
+reg a7ddrphy_rdly_dq_bitslip_we = 1'd0;
+reg a7ddrphy_rdly_dq_bitslip_w = 1'd0;
+reg a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0;
+wire a7ddrphy_wdly_dq_bitslip_rst_r;
+reg a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0;
+reg a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0;
+reg a7ddrphy_wdly_dq_bitslip_re = 1'd0;
+wire a7ddrphy_wdly_dq_bitslip_r;
+reg a7ddrphy_wdly_dq_bitslip_we = 1'd0;
+reg a7ddrphy_wdly_dq_bitslip_w = 1'd0;
+reg [1:0] a7ddrphy_rdphase_storage = 2'd2;
+reg a7ddrphy_rdphase_re = 1'd0;
+reg [1:0] a7ddrphy_wrphase_storage = 2'd3;
+reg a7ddrphy_wrphase_re = 1'd0;
+wire [13:0] a7ddrphy_dfi_p0_address;
+wire [2:0] a7ddrphy_dfi_p0_bank;
+wire a7ddrphy_dfi_p0_cas_n;
+wire a7ddrphy_dfi_p0_cs_n;
+wire a7ddrphy_dfi_p0_ras_n;
+wire a7ddrphy_dfi_p0_we_n;
+wire a7ddrphy_dfi_p0_cke;
+wire a7ddrphy_dfi_p0_odt;
+wire a7ddrphy_dfi_p0_reset_n;
+wire a7ddrphy_dfi_p0_act_n;
+wire [31:0] a7ddrphy_dfi_p0_wrdata;
+wire a7ddrphy_dfi_p0_wrdata_en;
+wire [3:0] a7ddrphy_dfi_p0_wrdata_mask;
+wire a7ddrphy_dfi_p0_rddata_en;
+reg [31:0] a7ddrphy_dfi_p0_rddata = 32'd0;
+wire a7ddrphy_dfi_p0_rddata_valid;
+wire [13:0] a7ddrphy_dfi_p1_address;
+wire [2:0] a7ddrphy_dfi_p1_bank;
+wire a7ddrphy_dfi_p1_cas_n;
+wire a7ddrphy_dfi_p1_cs_n;
+wire a7ddrphy_dfi_p1_ras_n;
+wire a7ddrphy_dfi_p1_we_n;
+wire a7ddrphy_dfi_p1_cke;
+wire a7ddrphy_dfi_p1_odt;
+wire a7ddrphy_dfi_p1_reset_n;
+wire a7ddrphy_dfi_p1_act_n;
+wire [31:0] a7ddrphy_dfi_p1_wrdata;
+wire a7ddrphy_dfi_p1_wrdata_en;
+wire [3:0] a7ddrphy_dfi_p1_wrdata_mask;
+wire a7ddrphy_dfi_p1_rddata_en;
+reg [31:0] a7ddrphy_dfi_p1_rddata = 32'd0;
+wire a7ddrphy_dfi_p1_rddata_valid;
+wire [13:0] a7ddrphy_dfi_p2_address;
+wire [2:0] a7ddrphy_dfi_p2_bank;
+wire a7ddrphy_dfi_p2_cas_n;
+wire a7ddrphy_dfi_p2_cs_n;
+wire a7ddrphy_dfi_p2_ras_n;
+wire a7ddrphy_dfi_p2_we_n;
+wire a7ddrphy_dfi_p2_cke;
+wire a7ddrphy_dfi_p2_odt;
+wire a7ddrphy_dfi_p2_reset_n;
+wire a7ddrphy_dfi_p2_act_n;
+wire [31:0] a7ddrphy_dfi_p2_wrdata;
+wire a7ddrphy_dfi_p2_wrdata_en;
+wire [3:0] a7ddrphy_dfi_p2_wrdata_mask;
+wire a7ddrphy_dfi_p2_rddata_en;
+reg [31:0] a7ddrphy_dfi_p2_rddata = 32'd0;
+wire a7ddrphy_dfi_p2_rddata_valid;
+wire [13:0] a7ddrphy_dfi_p3_address;
+wire [2:0] a7ddrphy_dfi_p3_bank;
+wire a7ddrphy_dfi_p3_cas_n;
+wire a7ddrphy_dfi_p3_cs_n;
+wire a7ddrphy_dfi_p3_ras_n;
+wire a7ddrphy_dfi_p3_we_n;
+wire a7ddrphy_dfi_p3_cke;
+wire a7ddrphy_dfi_p3_odt;
+wire a7ddrphy_dfi_p3_reset_n;
+wire a7ddrphy_dfi_p3_act_n;
+wire [31:0] a7ddrphy_dfi_p3_wrdata;
+wire a7ddrphy_dfi_p3_wrdata_en;
+wire [3:0] a7ddrphy_dfi_p3_wrdata_mask;
+wire a7ddrphy_dfi_p3_rddata_en;
+reg [31:0] a7ddrphy_dfi_p3_rddata = 32'd0;
+wire a7ddrphy_dfi_p3_rddata_valid;
+wire a7ddrphy_sd_clk_se_nodelay;
+wire [2:0] a7ddrphy_pads_ba;
+reg a7ddrphy_dqs_oe = 1'd0;
+wire a7ddrphy_dqs_preamble;
+wire a7ddrphy_dqs_postamble;
+wire a7ddrphy_dqs_oe_delay_tappeddelayline;
+reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
+reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
+reg a7ddrphy_dqspattern0 = 1'd0;
+reg a7ddrphy_dqspattern1 = 1'd0;
+reg [7:0] a7ddrphy_dqspattern_o0 = 8'd0;
+reg [7:0] a7ddrphy_dqspattern_o1 = 8'd0;
+wire a7ddrphy_dqs_o_no_delay0;
+wire a7ddrphy_dqs_t0;
+reg [7:0] a7ddrphy_bitslip00 = 8'd0;
+reg [2:0] a7ddrphy_bitslip0_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip0_r0 = 16'd0;
+wire a7ddrphy0;
+wire a7ddrphy_dqs_o_no_delay1;
+wire a7ddrphy_dqs_t1;
+reg [7:0] a7ddrphy_bitslip10 = 8'd0;
+reg [2:0] a7ddrphy_bitslip1_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip1_r0 = 16'd0;
+wire a7ddrphy1;
+reg [7:0] a7ddrphy_bitslip01 = 8'd0;
+reg [2:0] a7ddrphy_bitslip0_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip0_r1 = 16'd0;
+reg [7:0] a7ddrphy_bitslip11 = 8'd0;
+reg [2:0] a7ddrphy_bitslip1_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip1_r1 = 16'd0;
+wire a7ddrphy_dq_oe;
+wire a7ddrphy_dq_oe_delay_tappeddelayline;
+reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
+reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
+wire a7ddrphy_dq_o_nodelay0;
+wire a7ddrphy_dq_i_nodelay0;
+wire a7ddrphy_dq_i_delayed0;
+wire a7ddrphy_dq_t0;
+reg [7:0] a7ddrphy_bitslip02 = 8'd0;
+reg [2:0] a7ddrphy_bitslip0_value2 = 3'd7;
+reg [15:0] a7ddrphy_bitslip0_r2 = 16'd0;
+wire [7:0] a7ddrphy_bitslip03;
+reg [7:0] a7ddrphy_bitslip04 = 8'd0;
+reg [2:0] a7ddrphy_bitslip0_value3 = 3'd7;
+reg [15:0] a7ddrphy_bitslip0_r3 = 16'd0;
+wire a7ddrphy_dq_o_nodelay1;
+wire a7ddrphy_dq_i_nodelay1;
+wire a7ddrphy_dq_i_delayed1;
+wire a7ddrphy_dq_t1;
+reg [7:0] a7ddrphy_bitslip12 = 8'd0;
+reg [2:0] a7ddrphy_bitslip1_value2 = 3'd7;
+reg [15:0] a7ddrphy_bitslip1_r2 = 16'd0;
+wire [7:0] a7ddrphy_bitslip13;
+reg [7:0] a7ddrphy_bitslip14 = 8'd0;
+reg [2:0] a7ddrphy_bitslip1_value3 = 3'd7;
+reg [15:0] a7ddrphy_bitslip1_r3 = 16'd0;
+wire a7ddrphy_dq_o_nodelay2;
+wire a7ddrphy_dq_i_nodelay2;
+wire a7ddrphy_dq_i_delayed2;
+wire a7ddrphy_dq_t2;
+reg [7:0] a7ddrphy_bitslip20 = 8'd0;
+reg [2:0] a7ddrphy_bitslip2_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip2_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip21;
+reg [7:0] a7ddrphy_bitslip22 = 8'd0;
+reg [2:0] a7ddrphy_bitslip2_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip2_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay3;
+wire a7ddrphy_dq_i_nodelay3;
+wire a7ddrphy_dq_i_delayed3;
+wire a7ddrphy_dq_t3;
+reg [7:0] a7ddrphy_bitslip30 = 8'd0;
+reg [2:0] a7ddrphy_bitslip3_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip3_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip31;
+reg [7:0] a7ddrphy_bitslip32 = 8'd0;
+reg [2:0] a7ddrphy_bitslip3_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip3_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay4;
+wire a7ddrphy_dq_i_nodelay4;
+wire a7ddrphy_dq_i_delayed4;
+wire a7ddrphy_dq_t4;
+reg [7:0] a7ddrphy_bitslip40 = 8'd0;
+reg [2:0] a7ddrphy_bitslip4_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip4_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip41;
+reg [7:0] a7ddrphy_bitslip42 = 8'd0;
+reg [2:0] a7ddrphy_bitslip4_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip4_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay5;
+wire a7ddrphy_dq_i_nodelay5;
+wire a7ddrphy_dq_i_delayed5;
+wire a7ddrphy_dq_t5;
+reg [7:0] a7ddrphy_bitslip50 = 8'd0;
+reg [2:0] a7ddrphy_bitslip5_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip5_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip51;
+reg [7:0] a7ddrphy_bitslip52 = 8'd0;
+reg [2:0] a7ddrphy_bitslip5_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip5_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay6;
+wire a7ddrphy_dq_i_nodelay6;
+wire a7ddrphy_dq_i_delayed6;
+wire a7ddrphy_dq_t6;
+reg [7:0] a7ddrphy_bitslip60 = 8'd0;
+reg [2:0] a7ddrphy_bitslip6_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip6_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip61;
+reg [7:0] a7ddrphy_bitslip62 = 8'd0;
+reg [2:0] a7ddrphy_bitslip6_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip6_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay7;
+wire a7ddrphy_dq_i_nodelay7;
+wire a7ddrphy_dq_i_delayed7;
+wire a7ddrphy_dq_t7;
+reg [7:0] a7ddrphy_bitslip70 = 8'd0;
+reg [2:0] a7ddrphy_bitslip7_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip7_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip71;
+reg [7:0] a7ddrphy_bitslip72 = 8'd0;
+reg [2:0] a7ddrphy_bitslip7_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip7_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay8;
+wire a7ddrphy_dq_i_nodelay8;
+wire a7ddrphy_dq_i_delayed8;
+wire a7ddrphy_dq_t8;
+reg [7:0] a7ddrphy_bitslip80 = 8'd0;
+reg [2:0] a7ddrphy_bitslip8_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip8_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip81;
+reg [7:0] a7ddrphy_bitslip82 = 8'd0;
+reg [2:0] a7ddrphy_bitslip8_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip8_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay9;
+wire a7ddrphy_dq_i_nodelay9;
+wire a7ddrphy_dq_i_delayed9;
+wire a7ddrphy_dq_t9;
+reg [7:0] a7ddrphy_bitslip90 = 8'd0;
+reg [2:0] a7ddrphy_bitslip9_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip9_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip91;
+reg [7:0] a7ddrphy_bitslip92 = 8'd0;
+reg [2:0] a7ddrphy_bitslip9_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip9_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay10;
+wire a7ddrphy_dq_i_nodelay10;
+wire a7ddrphy_dq_i_delayed10;
+wire a7ddrphy_dq_t10;
+reg [7:0] a7ddrphy_bitslip100 = 8'd0;
+reg [2:0] a7ddrphy_bitslip10_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip10_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip101;
+reg [7:0] a7ddrphy_bitslip102 = 8'd0;
+reg [2:0] a7ddrphy_bitslip10_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip10_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay11;
+wire a7ddrphy_dq_i_nodelay11;
+wire a7ddrphy_dq_i_delayed11;
+wire a7ddrphy_dq_t11;
+reg [7:0] a7ddrphy_bitslip110 = 8'd0;
+reg [2:0] a7ddrphy_bitslip11_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip11_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip111;
+reg [7:0] a7ddrphy_bitslip112 = 8'd0;
+reg [2:0] a7ddrphy_bitslip11_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip11_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay12;
+wire a7ddrphy_dq_i_nodelay12;
+wire a7ddrphy_dq_i_delayed12;
+wire a7ddrphy_dq_t12;
+reg [7:0] a7ddrphy_bitslip120 = 8'd0;
+reg [2:0] a7ddrphy_bitslip12_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip12_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip121;
+reg [7:0] a7ddrphy_bitslip122 = 8'd0;
+reg [2:0] a7ddrphy_bitslip12_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip12_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay13;
+wire a7ddrphy_dq_i_nodelay13;
+wire a7ddrphy_dq_i_delayed13;
+wire a7ddrphy_dq_t13;
+reg [7:0] a7ddrphy_bitslip130 = 8'd0;
+reg [2:0] a7ddrphy_bitslip13_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip13_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip131;
+reg [7:0] a7ddrphy_bitslip132 = 8'd0;
+reg [2:0] a7ddrphy_bitslip13_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip13_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay14;
+wire a7ddrphy_dq_i_nodelay14;
+wire a7ddrphy_dq_i_delayed14;
+wire a7ddrphy_dq_t14;
+reg [7:0] a7ddrphy_bitslip140 = 8'd0;
+reg [2:0] a7ddrphy_bitslip14_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip14_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip141;
+reg [7:0] a7ddrphy_bitslip142 = 8'd0;
+reg [2:0] a7ddrphy_bitslip14_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip14_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay15;
+wire a7ddrphy_dq_i_nodelay15;
+wire a7ddrphy_dq_i_delayed15;
+wire a7ddrphy_dq_t15;
+reg [7:0] a7ddrphy_bitslip150 = 8'd0;
+reg [2:0] a7ddrphy_bitslip15_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip15_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip151;
+reg [7:0] a7ddrphy_bitslip152 = 8'd0;
+reg [2:0] a7ddrphy_bitslip15_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip15_r1 = 16'd0;
+reg a7ddrphy_rddata_en_tappeddelayline0 = 1'd0;
+reg a7ddrphy_rddata_en_tappeddelayline1 = 1'd0;
+reg a7ddrphy_rddata_en_tappeddelayline2 = 1'd0;
+reg a7ddrphy_rddata_en_tappeddelayline3 = 1'd0;
+reg a7ddrphy_rddata_en_tappeddelayline4 = 1'd0;
+reg a7ddrphy_rddata_en_tappeddelayline5 = 1'd0;
+reg a7ddrphy_rddata_en_tappeddelayline6 = 1'd0;
+reg a7ddrphy_rddata_en_tappeddelayline7 = 1'd0;
+reg a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
+reg a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
+reg a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
+wire [13:0] litedramcore_slave_p0_address;
+wire [2:0] litedramcore_slave_p0_bank;
+wire litedramcore_slave_p0_cas_n;
+wire litedramcore_slave_p0_cs_n;
+wire litedramcore_slave_p0_ras_n;
+wire litedramcore_slave_p0_we_n;
+wire litedramcore_slave_p0_cke;
+wire litedramcore_slave_p0_odt;
+wire litedramcore_slave_p0_reset_n;
+wire litedramcore_slave_p0_act_n;
+wire [31:0] litedramcore_slave_p0_wrdata;
+wire litedramcore_slave_p0_wrdata_en;
+wire [3:0] litedramcore_slave_p0_wrdata_mask;
+wire litedramcore_slave_p0_rddata_en;
+reg [31:0] litedramcore_slave_p0_rddata = 32'd0;
+reg litedramcore_slave_p0_rddata_valid = 1'd0;
+wire [13:0] litedramcore_slave_p1_address;
+wire [2:0] litedramcore_slave_p1_bank;
+wire litedramcore_slave_p1_cas_n;
+wire litedramcore_slave_p1_cs_n;
+wire litedramcore_slave_p1_ras_n;
+wire litedramcore_slave_p1_we_n;
+wire litedramcore_slave_p1_cke;
+wire litedramcore_slave_p1_odt;
+wire litedramcore_slave_p1_reset_n;
+wire litedramcore_slave_p1_act_n;
+wire [31:0] litedramcore_slave_p1_wrdata;
+wire litedramcore_slave_p1_wrdata_en;
+wire [3:0] litedramcore_slave_p1_wrdata_mask;
+wire litedramcore_slave_p1_rddata_en;
+reg [31:0] litedramcore_slave_p1_rddata = 32'd0;
+reg litedramcore_slave_p1_rddata_valid = 1'd0;
+wire [13:0] litedramcore_slave_p2_address;
+wire [2:0] litedramcore_slave_p2_bank;
+wire litedramcore_slave_p2_cas_n;
+wire litedramcore_slave_p2_cs_n;
+wire litedramcore_slave_p2_ras_n;
+wire litedramcore_slave_p2_we_n;
+wire litedramcore_slave_p2_cke;
+wire litedramcore_slave_p2_odt;
+wire litedramcore_slave_p2_reset_n;
+wire litedramcore_slave_p2_act_n;
+wire [31:0] litedramcore_slave_p2_wrdata;
+wire litedramcore_slave_p2_wrdata_en;
+wire [3:0] litedramcore_slave_p2_wrdata_mask;
+wire litedramcore_slave_p2_rddata_en;
+reg [31:0] litedramcore_slave_p2_rddata = 32'd0;
+reg litedramcore_slave_p2_rddata_valid = 1'd0;
+wire [13:0] litedramcore_slave_p3_address;
+wire [2:0] litedramcore_slave_p3_bank;
+wire litedramcore_slave_p3_cas_n;
+wire litedramcore_slave_p3_cs_n;
+wire litedramcore_slave_p3_ras_n;
+wire litedramcore_slave_p3_we_n;
+wire litedramcore_slave_p3_cke;
+wire litedramcore_slave_p3_odt;
+wire litedramcore_slave_p3_reset_n;
+wire litedramcore_slave_p3_act_n;
+wire [31:0] litedramcore_slave_p3_wrdata;
+wire litedramcore_slave_p3_wrdata_en;
+wire [3:0] litedramcore_slave_p3_wrdata_mask;
+wire litedramcore_slave_p3_rddata_en;
+reg [31:0] litedramcore_slave_p3_rddata = 32'd0;
+reg litedramcore_slave_p3_rddata_valid = 1'd0;
+reg [13:0] litedramcore_master_p0_address = 14'd0;
+reg [2:0] litedramcore_master_p0_bank = 3'd0;
+reg litedramcore_master_p0_cas_n = 1'd1;
+reg litedramcore_master_p0_cs_n = 1'd1;
+reg litedramcore_master_p0_ras_n = 1'd1;
+reg litedramcore_master_p0_we_n = 1'd1;
+reg litedramcore_master_p0_cke = 1'd0;
+reg litedramcore_master_p0_odt = 1'd0;
+reg litedramcore_master_p0_reset_n = 1'd0;
+reg litedramcore_master_p0_act_n = 1'd1;
+reg [31:0] litedramcore_master_p0_wrdata = 32'd0;
+reg litedramcore_master_p0_wrdata_en = 1'd0;
+reg [3:0] litedramcore_master_p0_wrdata_mask = 4'd0;
+reg litedramcore_master_p0_rddata_en = 1'd0;
+wire [31:0] litedramcore_master_p0_rddata;
+wire litedramcore_master_p0_rddata_valid;
+reg [13:0] litedramcore_master_p1_address = 14'd0;
+reg [2:0] litedramcore_master_p1_bank = 3'd0;
+reg litedramcore_master_p1_cas_n = 1'd1;
+reg litedramcore_master_p1_cs_n = 1'd1;
+reg litedramcore_master_p1_ras_n = 1'd1;
+reg litedramcore_master_p1_we_n = 1'd1;
+reg litedramcore_master_p1_cke = 1'd0;
+reg litedramcore_master_p1_odt = 1'd0;
+reg litedramcore_master_p1_reset_n = 1'd0;
+reg litedramcore_master_p1_act_n = 1'd1;
+reg [31:0] litedramcore_master_p1_wrdata = 32'd0;
+reg litedramcore_master_p1_wrdata_en = 1'd0;
+reg [3:0] litedramcore_master_p1_wrdata_mask = 4'd0;
+reg litedramcore_master_p1_rddata_en = 1'd0;
+wire [31:0] litedramcore_master_p1_rddata;
+wire litedramcore_master_p1_rddata_valid;
+reg [13:0] litedramcore_master_p2_address = 14'd0;
+reg [2:0] litedramcore_master_p2_bank = 3'd0;
+reg litedramcore_master_p2_cas_n = 1'd1;
+reg litedramcore_master_p2_cs_n = 1'd1;
+reg litedramcore_master_p2_ras_n = 1'd1;
+reg litedramcore_master_p2_we_n = 1'd1;
+reg litedramcore_master_p2_cke = 1'd0;
+reg litedramcore_master_p2_odt = 1'd0;
+reg litedramcore_master_p2_reset_n = 1'd0;
+reg litedramcore_master_p2_act_n = 1'd1;
+reg [31:0] litedramcore_master_p2_wrdata = 32'd0;
+reg litedramcore_master_p2_wrdata_en = 1'd0;
+reg [3:0] litedramcore_master_p2_wrdata_mask = 4'd0;
+reg litedramcore_master_p2_rddata_en = 1'd0;
+wire [31:0] litedramcore_master_p2_rddata;
+wire litedramcore_master_p2_rddata_valid;
+reg [13:0] litedramcore_master_p3_address = 14'd0;
+reg [2:0] litedramcore_master_p3_bank = 3'd0;
+reg litedramcore_master_p3_cas_n = 1'd1;
+reg litedramcore_master_p3_cs_n = 1'd1;
+reg litedramcore_master_p3_ras_n = 1'd1;
+reg litedramcore_master_p3_we_n = 1'd1;
+reg litedramcore_master_p3_cke = 1'd0;
+reg litedramcore_master_p3_odt = 1'd0;
+reg litedramcore_master_p3_reset_n = 1'd0;
+reg litedramcore_master_p3_act_n = 1'd1;
+reg [31:0] litedramcore_master_p3_wrdata = 32'd0;
+reg litedramcore_master_p3_wrdata_en = 1'd0;
+reg [3:0] litedramcore_master_p3_wrdata_mask = 4'd0;
+reg litedramcore_master_p3_rddata_en = 1'd0;
+wire [31:0] litedramcore_master_p3_rddata;
+wire litedramcore_master_p3_rddata_valid;
+wire [13:0] litedramcore_csr_dfi_p0_address;
+wire [2:0] litedramcore_csr_dfi_p0_bank;
+reg litedramcore_csr_dfi_p0_cas_n = 1'd1;
+reg litedramcore_csr_dfi_p0_cs_n = 1'd1;
+reg litedramcore_csr_dfi_p0_ras_n = 1'd1;
+reg litedramcore_csr_dfi_p0_we_n = 1'd1;
+wire litedramcore_csr_dfi_p0_cke;
+wire litedramcore_csr_dfi_p0_odt;
+wire litedramcore_csr_dfi_p0_reset_n;
+reg litedramcore_csr_dfi_p0_act_n = 1'd1;
+wire [31:0] litedramcore_csr_dfi_p0_wrdata;
+wire litedramcore_csr_dfi_p0_wrdata_en;
+wire [3:0] litedramcore_csr_dfi_p0_wrdata_mask;
+wire litedramcore_csr_dfi_p0_rddata_en;
+reg [31:0] litedramcore_csr_dfi_p0_rddata = 32'd0;
+reg litedramcore_csr_dfi_p0_rddata_valid = 1'd0;
+wire [13:0] litedramcore_csr_dfi_p1_address;
+wire [2:0] litedramcore_csr_dfi_p1_bank;
+reg litedramcore_csr_dfi_p1_cas_n = 1'd1;
+reg litedramcore_csr_dfi_p1_cs_n = 1'd1;
+reg litedramcore_csr_dfi_p1_ras_n = 1'd1;
+reg litedramcore_csr_dfi_p1_we_n = 1'd1;
+wire litedramcore_csr_dfi_p1_cke;
+wire litedramcore_csr_dfi_p1_odt;
+wire litedramcore_csr_dfi_p1_reset_n;
+reg litedramcore_csr_dfi_p1_act_n = 1'd1;
+wire [31:0] litedramcore_csr_dfi_p1_wrdata;
+wire litedramcore_csr_dfi_p1_wrdata_en;
+wire [3:0] litedramcore_csr_dfi_p1_wrdata_mask;
+wire litedramcore_csr_dfi_p1_rddata_en;
+reg [31:0] litedramcore_csr_dfi_p1_rddata = 32'd0;
+reg litedramcore_csr_dfi_p1_rddata_valid = 1'd0;
+wire [13:0] litedramcore_csr_dfi_p2_address;
+wire [2:0] litedramcore_csr_dfi_p2_bank;
+reg litedramcore_csr_dfi_p2_cas_n = 1'd1;
+reg litedramcore_csr_dfi_p2_cs_n = 1'd1;
+reg litedramcore_csr_dfi_p2_ras_n = 1'd1;
+reg litedramcore_csr_dfi_p2_we_n = 1'd1;
+wire litedramcore_csr_dfi_p2_cke;
+wire litedramcore_csr_dfi_p2_odt;
+wire litedramcore_csr_dfi_p2_reset_n;
+reg litedramcore_csr_dfi_p2_act_n = 1'd1;
+wire [31:0] litedramcore_csr_dfi_p2_wrdata;
+wire litedramcore_csr_dfi_p2_wrdata_en;
+wire [3:0] litedramcore_csr_dfi_p2_wrdata_mask;
+wire litedramcore_csr_dfi_p2_rddata_en;
+reg [31:0] litedramcore_csr_dfi_p2_rddata = 32'd0;
+reg litedramcore_csr_dfi_p2_rddata_valid = 1'd0;
+wire [13:0] litedramcore_csr_dfi_p3_address;
+wire [2:0] litedramcore_csr_dfi_p3_bank;
+reg litedramcore_csr_dfi_p3_cas_n = 1'd1;
+reg litedramcore_csr_dfi_p3_cs_n = 1'd1;
+reg litedramcore_csr_dfi_p3_ras_n = 1'd1;
+reg litedramcore_csr_dfi_p3_we_n = 1'd1;
+wire litedramcore_csr_dfi_p3_cke;
+wire litedramcore_csr_dfi_p3_odt;
+wire litedramcore_csr_dfi_p3_reset_n;
+reg litedramcore_csr_dfi_p3_act_n = 1'd1;
+wire [31:0] litedramcore_csr_dfi_p3_wrdata;
+wire litedramcore_csr_dfi_p3_wrdata_en;
+wire [3:0] litedramcore_csr_dfi_p3_wrdata_mask;
+wire litedramcore_csr_dfi_p3_rddata_en;
+reg [31:0] litedramcore_csr_dfi_p3_rddata = 32'd0;
+reg litedramcore_csr_dfi_p3_rddata_valid = 1'd0;
+reg [13:0] litedramcore_ext_dfi_p0_address = 14'd0;
+reg [2:0] litedramcore_ext_dfi_p0_bank = 3'd0;
+reg litedramcore_ext_dfi_p0_cas_n = 1'd1;
+reg litedramcore_ext_dfi_p0_cs_n = 1'd1;
+reg litedramcore_ext_dfi_p0_ras_n = 1'd1;
+reg litedramcore_ext_dfi_p0_we_n = 1'd1;
+reg litedramcore_ext_dfi_p0_cke = 1'd0;
+reg litedramcore_ext_dfi_p0_odt = 1'd0;
+reg litedramcore_ext_dfi_p0_reset_n = 1'd0;
+reg litedramcore_ext_dfi_p0_act_n = 1'd1;
+reg [31:0] litedramcore_ext_dfi_p0_wrdata = 32'd0;
+reg litedramcore_ext_dfi_p0_wrdata_en = 1'd0;
+reg [3:0] litedramcore_ext_dfi_p0_wrdata_mask = 4'd0;
+reg litedramcore_ext_dfi_p0_rddata_en = 1'd0;
+reg [31:0] litedramcore_ext_dfi_p0_rddata = 32'd0;
+reg litedramcore_ext_dfi_p0_rddata_valid = 1'd0;
+reg [13:0] litedramcore_ext_dfi_p1_address = 14'd0;
+reg [2:0] litedramcore_ext_dfi_p1_bank = 3'd0;
+reg litedramcore_ext_dfi_p1_cas_n = 1'd1;
+reg litedramcore_ext_dfi_p1_cs_n = 1'd1;
+reg litedramcore_ext_dfi_p1_ras_n = 1'd1;
+reg litedramcore_ext_dfi_p1_we_n = 1'd1;
+reg litedramcore_ext_dfi_p1_cke = 1'd0;
+reg litedramcore_ext_dfi_p1_odt = 1'd0;
+reg litedramcore_ext_dfi_p1_reset_n = 1'd0;
+reg litedramcore_ext_dfi_p1_act_n = 1'd1;
+reg [31:0] litedramcore_ext_dfi_p1_wrdata = 32'd0;
+reg litedramcore_ext_dfi_p1_wrdata_en = 1'd0;
+reg [3:0] litedramcore_ext_dfi_p1_wrdata_mask = 4'd0;
+reg litedramcore_ext_dfi_p1_rddata_en = 1'd0;
+reg [31:0] litedramcore_ext_dfi_p1_rddata = 32'd0;
+reg litedramcore_ext_dfi_p1_rddata_valid = 1'd0;
+reg [13:0] litedramcore_ext_dfi_p2_address = 14'd0;
+reg [2:0] litedramcore_ext_dfi_p2_bank = 3'd0;
+reg litedramcore_ext_dfi_p2_cas_n = 1'd1;
+reg litedramcore_ext_dfi_p2_cs_n = 1'd1;
+reg litedramcore_ext_dfi_p2_ras_n = 1'd1;
+reg litedramcore_ext_dfi_p2_we_n = 1'd1;
+reg litedramcore_ext_dfi_p2_cke = 1'd0;
+reg litedramcore_ext_dfi_p2_odt = 1'd0;
+reg litedramcore_ext_dfi_p2_reset_n = 1'd0;
+reg litedramcore_ext_dfi_p2_act_n = 1'd1;
+reg [31:0] litedramcore_ext_dfi_p2_wrdata = 32'd0;
+reg litedramcore_ext_dfi_p2_wrdata_en = 1'd0;
+reg [3:0] litedramcore_ext_dfi_p2_wrdata_mask = 4'd0;
+reg litedramcore_ext_dfi_p2_rddata_en = 1'd0;
+reg [31:0] litedramcore_ext_dfi_p2_rddata = 32'd0;
+reg litedramcore_ext_dfi_p2_rddata_valid = 1'd0;
+reg [13:0] litedramcore_ext_dfi_p3_address = 14'd0;
+reg [2:0] litedramcore_ext_dfi_p3_bank = 3'd0;
+reg litedramcore_ext_dfi_p3_cas_n = 1'd1;
+reg litedramcore_ext_dfi_p3_cs_n = 1'd1;
+reg litedramcore_ext_dfi_p3_ras_n = 1'd1;
+reg litedramcore_ext_dfi_p3_we_n = 1'd1;
+reg litedramcore_ext_dfi_p3_cke = 1'd0;
+reg litedramcore_ext_dfi_p3_odt = 1'd0;
+reg litedramcore_ext_dfi_p3_reset_n = 1'd0;
+reg litedramcore_ext_dfi_p3_act_n = 1'd1;
+reg [31:0] litedramcore_ext_dfi_p3_wrdata = 32'd0;
+reg litedramcore_ext_dfi_p3_wrdata_en = 1'd0;
+reg [3:0] litedramcore_ext_dfi_p3_wrdata_mask = 4'd0;
+reg litedramcore_ext_dfi_p3_rddata_en = 1'd0;
+reg [31:0] litedramcore_ext_dfi_p3_rddata = 32'd0;
+reg litedramcore_ext_dfi_p3_rddata_valid = 1'd0;
+reg litedramcore_ext_dfi_sel = 1'd0;
+wire litedramcore_sel;
+wire litedramcore_cke;
+wire litedramcore_odt;
+wire litedramcore_reset_n;
+reg [3:0] litedramcore_storage = 4'd1;
+reg litedramcore_re = 1'd0;
+wire litedramcore_phaseinjector0_csrfield_cs;
+wire litedramcore_phaseinjector0_csrfield_we;
+wire litedramcore_phaseinjector0_csrfield_cas;
+wire litedramcore_phaseinjector0_csrfield_ras;
+wire litedramcore_phaseinjector0_csrfield_wren;
+wire litedramcore_phaseinjector0_csrfield_rden;
+reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0;
+reg litedramcore_phaseinjector0_command_re = 1'd0;
+reg litedramcore_phaseinjector0_command_issue_re = 1'd0;
+wire litedramcore_phaseinjector0_command_issue_r;
+reg litedramcore_phaseinjector0_command_issue_we = 1'd0;
+reg litedramcore_phaseinjector0_command_issue_w = 1'd0;
+reg [13:0] litedramcore_phaseinjector0_address_storage = 14'd0;
+reg litedramcore_phaseinjector0_address_re = 1'd0;
+reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0;
+reg litedramcore_phaseinjector0_baddress_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector0_wrdata_storage = 32'd0;
+reg litedramcore_phaseinjector0_wrdata_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector0_rddata_status = 32'd0;
+wire litedramcore_phaseinjector0_rddata_we;
+reg litedramcore_phaseinjector0_rddata_re = 1'd0;
+wire litedramcore_phaseinjector1_csrfield_cs;
+wire litedramcore_phaseinjector1_csrfield_we;
+wire litedramcore_phaseinjector1_csrfield_cas;
+wire litedramcore_phaseinjector1_csrfield_ras;
+wire litedramcore_phaseinjector1_csrfield_wren;
+wire litedramcore_phaseinjector1_csrfield_rden;
+reg [5:0] litedramcore_phaseinjector1_command_storage = 6'd0;
+reg litedramcore_phaseinjector1_command_re = 1'd0;
+reg litedramcore_phaseinjector1_command_issue_re = 1'd0;
+wire litedramcore_phaseinjector1_command_issue_r;
+reg litedramcore_phaseinjector1_command_issue_we = 1'd0;
+reg litedramcore_phaseinjector1_command_issue_w = 1'd0;
+reg [13:0] litedramcore_phaseinjector1_address_storage = 14'd0;
+reg litedramcore_phaseinjector1_address_re = 1'd0;
+reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0;
+reg litedramcore_phaseinjector1_baddress_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector1_wrdata_storage = 32'd0;
+reg litedramcore_phaseinjector1_wrdata_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector1_rddata_status = 32'd0;
+wire litedramcore_phaseinjector1_rddata_we;
+reg litedramcore_phaseinjector1_rddata_re = 1'd0;
+wire litedramcore_phaseinjector2_csrfield_cs;
+wire litedramcore_phaseinjector2_csrfield_we;
+wire litedramcore_phaseinjector2_csrfield_cas;
+wire litedramcore_phaseinjector2_csrfield_ras;
+wire litedramcore_phaseinjector2_csrfield_wren;
+wire litedramcore_phaseinjector2_csrfield_rden;
+reg [5:0] litedramcore_phaseinjector2_command_storage = 6'd0;
+reg litedramcore_phaseinjector2_command_re = 1'd0;
+reg litedramcore_phaseinjector2_command_issue_re = 1'd0;
+wire litedramcore_phaseinjector2_command_issue_r;
+reg litedramcore_phaseinjector2_command_issue_we = 1'd0;
+reg litedramcore_phaseinjector2_command_issue_w = 1'd0;
+reg [13:0] litedramcore_phaseinjector2_address_storage = 14'd0;
+reg litedramcore_phaseinjector2_address_re = 1'd0;
+reg [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0;
+reg litedramcore_phaseinjector2_baddress_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector2_wrdata_storage = 32'd0;
+reg litedramcore_phaseinjector2_wrdata_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector2_rddata_status = 32'd0;
+wire litedramcore_phaseinjector2_rddata_we;
+reg litedramcore_phaseinjector2_rddata_re = 1'd0;
+wire litedramcore_phaseinjector3_csrfield_cs;
+wire litedramcore_phaseinjector3_csrfield_we;
+wire litedramcore_phaseinjector3_csrfield_cas;
+wire litedramcore_phaseinjector3_csrfield_ras;
+wire litedramcore_phaseinjector3_csrfield_wren;
+wire litedramcore_phaseinjector3_csrfield_rden;
+reg [5:0] litedramcore_phaseinjector3_command_storage = 6'd0;
+reg litedramcore_phaseinjector3_command_re = 1'd0;
+reg litedramcore_phaseinjector3_command_issue_re = 1'd0;
+wire litedramcore_phaseinjector3_command_issue_r;
+reg litedramcore_phaseinjector3_command_issue_we = 1'd0;
+reg litedramcore_phaseinjector3_command_issue_w = 1'd0;
+reg [13:0] litedramcore_phaseinjector3_address_storage = 14'd0;
+reg litedramcore_phaseinjector3_address_re = 1'd0;
+reg [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0;
+reg litedramcore_phaseinjector3_baddress_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector3_wrdata_storage = 32'd0;
+reg litedramcore_phaseinjector3_wrdata_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector3_rddata_status = 32'd0;
+wire litedramcore_phaseinjector3_rddata_we;
+reg litedramcore_phaseinjector3_rddata_re = 1'd0;
+wire litedramcore_interface_bank0_valid;
+wire litedramcore_interface_bank0_ready;
+wire litedramcore_interface_bank0_we;
+wire [20:0] litedramcore_interface_bank0_addr;
+wire litedramcore_interface_bank0_lock;
+wire litedramcore_interface_bank0_wdata_ready;
+wire litedramcore_interface_bank0_rdata_valid;
+wire litedramcore_interface_bank1_valid;
+wire litedramcore_interface_bank1_ready;
+wire litedramcore_interface_bank1_we;
+wire [20:0] litedramcore_interface_bank1_addr;
+wire litedramcore_interface_bank1_lock;
+wire litedramcore_interface_bank1_wdata_ready;
+wire litedramcore_interface_bank1_rdata_valid;
+wire litedramcore_interface_bank2_valid;
+wire litedramcore_interface_bank2_ready;
+wire litedramcore_interface_bank2_we;
+wire [20:0] litedramcore_interface_bank2_addr;
+wire litedramcore_interface_bank2_lock;
+wire litedramcore_interface_bank2_wdata_ready;
+wire litedramcore_interface_bank2_rdata_valid;
+wire litedramcore_interface_bank3_valid;
+wire litedramcore_interface_bank3_ready;
+wire litedramcore_interface_bank3_we;
+wire [20:0] litedramcore_interface_bank3_addr;
+wire litedramcore_interface_bank3_lock;
+wire litedramcore_interface_bank3_wdata_ready;
+wire litedramcore_interface_bank3_rdata_valid;
+wire litedramcore_interface_bank4_valid;
+wire litedramcore_interface_bank4_ready;
+wire litedramcore_interface_bank4_we;
+wire [20:0] litedramcore_interface_bank4_addr;
+wire litedramcore_interface_bank4_lock;
+wire litedramcore_interface_bank4_wdata_ready;
+wire litedramcore_interface_bank4_rdata_valid;
+wire litedramcore_interface_bank5_valid;
+wire litedramcore_interface_bank5_ready;
+wire litedramcore_interface_bank5_we;
+wire [20:0] litedramcore_interface_bank5_addr;
+wire litedramcore_interface_bank5_lock;
+wire litedramcore_interface_bank5_wdata_ready;
+wire litedramcore_interface_bank5_rdata_valid;
+wire litedramcore_interface_bank6_valid;
+wire litedramcore_interface_bank6_ready;
+wire litedramcore_interface_bank6_we;
+wire [20:0] litedramcore_interface_bank6_addr;
+wire litedramcore_interface_bank6_lock;
+wire litedramcore_interface_bank6_wdata_ready;
+wire litedramcore_interface_bank6_rdata_valid;
+wire litedramcore_interface_bank7_valid;
+wire litedramcore_interface_bank7_ready;
+wire litedramcore_interface_bank7_we;
+wire [20:0] litedramcore_interface_bank7_addr;
+wire litedramcore_interface_bank7_lock;
+wire litedramcore_interface_bank7_wdata_ready;
+wire litedramcore_interface_bank7_rdata_valid;
+reg [127:0] litedramcore_interface_wdata = 128'd0;
+reg [15:0] litedramcore_interface_wdata_we = 16'd0;
+wire [127:0] litedramcore_interface_rdata;
+reg [13:0] litedramcore_dfi_p0_address = 14'd0;
+reg [2:0] litedramcore_dfi_p0_bank = 3'd0;
+reg litedramcore_dfi_p0_cas_n = 1'd1;
+reg litedramcore_dfi_p0_cs_n = 1'd1;
+reg litedramcore_dfi_p0_ras_n = 1'd1;
+reg litedramcore_dfi_p0_we_n = 1'd1;
+wire litedramcore_dfi_p0_cke;
+wire litedramcore_dfi_p0_odt;
+wire litedramcore_dfi_p0_reset_n;
+reg litedramcore_dfi_p0_act_n = 1'd1;
+wire [31:0] litedramcore_dfi_p0_wrdata;
+reg litedramcore_dfi_p0_wrdata_en = 1'd0;
+wire [3:0] litedramcore_dfi_p0_wrdata_mask;
+reg litedramcore_dfi_p0_rddata_en = 1'd0;
+wire [31:0] litedramcore_dfi_p0_rddata;
+wire litedramcore_dfi_p0_rddata_valid;
+reg [13:0] litedramcore_dfi_p1_address = 14'd0;
+reg [2:0] litedramcore_dfi_p1_bank = 3'd0;
+reg litedramcore_dfi_p1_cas_n = 1'd1;
+reg litedramcore_dfi_p1_cs_n = 1'd1;
+reg litedramcore_dfi_p1_ras_n = 1'd1;
+reg litedramcore_dfi_p1_we_n = 1'd1;
+wire litedramcore_dfi_p1_cke;
+wire litedramcore_dfi_p1_odt;
+wire litedramcore_dfi_p1_reset_n;
+reg litedramcore_dfi_p1_act_n = 1'd1;
+wire [31:0] litedramcore_dfi_p1_wrdata;
+reg litedramcore_dfi_p1_wrdata_en = 1'd0;
+wire [3:0] litedramcore_dfi_p1_wrdata_mask;
+reg litedramcore_dfi_p1_rddata_en = 1'd0;
+wire [31:0] litedramcore_dfi_p1_rddata;
+wire litedramcore_dfi_p1_rddata_valid;
+reg [13:0] litedramcore_dfi_p2_address = 14'd0;
+reg [2:0] litedramcore_dfi_p2_bank = 3'd0;
+reg litedramcore_dfi_p2_cas_n = 1'd1;
+reg litedramcore_dfi_p2_cs_n = 1'd1;
+reg litedramcore_dfi_p2_ras_n = 1'd1;
+reg litedramcore_dfi_p2_we_n = 1'd1;
+wire litedramcore_dfi_p2_cke;
+wire litedramcore_dfi_p2_odt;
+wire litedramcore_dfi_p2_reset_n;
+reg litedramcore_dfi_p2_act_n = 1'd1;
+wire [31:0] litedramcore_dfi_p2_wrdata;
+reg litedramcore_dfi_p2_wrdata_en = 1'd0;
+wire [3:0] litedramcore_dfi_p2_wrdata_mask;
+reg litedramcore_dfi_p2_rddata_en = 1'd0;
+wire [31:0] litedramcore_dfi_p2_rddata;
+wire litedramcore_dfi_p2_rddata_valid;
+reg [13:0] litedramcore_dfi_p3_address = 14'd0;
+reg [2:0] litedramcore_dfi_p3_bank = 3'd0;
+reg litedramcore_dfi_p3_cas_n = 1'd1;
+reg litedramcore_dfi_p3_cs_n = 1'd1;
+reg litedramcore_dfi_p3_ras_n = 1'd1;
+reg litedramcore_dfi_p3_we_n = 1'd1;
+wire litedramcore_dfi_p3_cke;
+wire litedramcore_dfi_p3_odt;
+wire litedramcore_dfi_p3_reset_n;
+reg litedramcore_dfi_p3_act_n = 1'd1;
+wire [31:0] litedramcore_dfi_p3_wrdata;
+reg litedramcore_dfi_p3_wrdata_en = 1'd0;
+wire [3:0] litedramcore_dfi_p3_wrdata_mask;
+reg litedramcore_dfi_p3_rddata_en = 1'd0;
+wire [31:0] litedramcore_dfi_p3_rddata;
+wire litedramcore_dfi_p3_rddata_valid;
+reg litedramcore_cmd_valid = 1'd0;
+reg litedramcore_cmd_ready = 1'd0;
+reg litedramcore_cmd_last = 1'd0;
+reg [13:0] litedramcore_cmd_payload_a = 14'd0;
+reg [2:0] litedramcore_cmd_payload_ba = 3'd0;
+reg litedramcore_cmd_payload_cas = 1'd0;
+reg litedramcore_cmd_payload_ras = 1'd0;
+reg litedramcore_cmd_payload_we = 1'd0;
+reg litedramcore_cmd_payload_is_read = 1'd0;
+reg litedramcore_cmd_payload_is_write = 1'd0;
+wire litedramcore_wants_refresh;
+wire litedramcore_wants_zqcs;
+wire litedramcore_timer_wait;
+wire litedramcore_timer_done0;
+wire [9:0] litedramcore_timer_count0;
+wire litedramcore_timer_done1;
+reg [9:0] litedramcore_timer_count1 = 10'd781;
+wire litedramcore_postponer_req_i;
+reg litedramcore_postponer_req_o = 1'd0;
+reg litedramcore_postponer_count = 1'd0;
+reg litedramcore_sequencer_start0 = 1'd0;
+wire litedramcore_sequencer_done0;
+wire litedramcore_sequencer_start1;
+reg litedramcore_sequencer_done1 = 1'd0;
+reg [5:0] litedramcore_sequencer_counter = 6'd0;
+reg litedramcore_sequencer_count = 1'd0;
+wire litedramcore_zqcs_timer_wait;
+wire litedramcore_zqcs_timer_done0;
+wire [26:0] litedramcore_zqcs_timer_count0;
+wire litedramcore_zqcs_timer_done1;
+reg [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999;
+reg litedramcore_zqcs_executer_start = 1'd0;
+reg litedramcore_zqcs_executer_done = 1'd0;
+reg [4:0] litedramcore_zqcs_executer_counter = 5'd0;
+wire litedramcore_bankmachine0_req_valid;
+wire litedramcore_bankmachine0_req_ready;
+wire litedramcore_bankmachine0_req_we;
+wire [20:0] litedramcore_bankmachine0_req_addr;
+wire litedramcore_bankmachine0_req_lock;
+reg litedramcore_bankmachine0_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine0_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine0_refresh_req;
+reg litedramcore_bankmachine0_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine0_cmd_valid = 1'd0;
+reg litedramcore_bankmachine0_cmd_ready = 1'd0;
+reg [13:0] litedramcore_bankmachine0_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine0_cmd_payload_ba;
+reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine0_auto_precharge = 1'd0;
+wire litedramcore_bankmachine0_sink_valid;
+wire litedramcore_bankmachine0_sink_ready;
+reg litedramcore_bankmachine0_sink_first = 1'd0;
+reg litedramcore_bankmachine0_sink_last = 1'd0;
+wire litedramcore_bankmachine0_sink_payload_we;
+wire [20:0] litedramcore_bankmachine0_sink_payload_addr;
+wire litedramcore_bankmachine0_source_valid;
+wire litedramcore_bankmachine0_source_ready;
+wire litedramcore_bankmachine0_source_first;
+wire litedramcore_bankmachine0_source_last;
+wire litedramcore_bankmachine0_source_payload_we;
+wire [20:0] litedramcore_bankmachine0_source_payload_addr;
+wire litedramcore_bankmachine0_syncfifo0_we;
+wire litedramcore_bankmachine0_syncfifo0_writable;
+wire litedramcore_bankmachine0_syncfifo0_re;
+wire litedramcore_bankmachine0_syncfifo0_readable;
+wire [23:0] litedramcore_bankmachine0_syncfifo0_din;
+wire [23:0] litedramcore_bankmachine0_syncfifo0_dout;
+reg [4:0] litedramcore_bankmachine0_level = 5'd0;
+reg litedramcore_bankmachine0_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine0_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine0_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine0_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine0_wrport_dat_r;
+wire litedramcore_bankmachine0_wrport_we;
+wire [23:0] litedramcore_bankmachine0_wrport_dat_w;
+wire litedramcore_bankmachine0_do_read;
+wire [3:0] litedramcore_bankmachine0_rdport_adr;
+wire [23:0] litedramcore_bankmachine0_rdport_dat_r;
+wire litedramcore_bankmachine0_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine0_fifo_in_payload_addr;
+wire litedramcore_bankmachine0_fifo_in_first;
+wire litedramcore_bankmachine0_fifo_in_last;
+wire litedramcore_bankmachine0_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine0_fifo_out_payload_addr;
+wire litedramcore_bankmachine0_fifo_out_first;
+wire litedramcore_bankmachine0_fifo_out_last;
+wire litedramcore_bankmachine0_sink_sink_valid;
+wire litedramcore_bankmachine0_sink_sink_ready;
+wire litedramcore_bankmachine0_sink_sink_first;
+wire litedramcore_bankmachine0_sink_sink_last;
+wire litedramcore_bankmachine0_sink_sink_payload_we;
+wire [20:0] litedramcore_bankmachine0_sink_sink_payload_addr;
+wire litedramcore_bankmachine0_source_source_valid;
+wire litedramcore_bankmachine0_source_source_ready;
+wire litedramcore_bankmachine0_source_source_first;
+wire litedramcore_bankmachine0_source_source_last;
+wire litedramcore_bankmachine0_source_source_payload_we;
+wire [20:0] litedramcore_bankmachine0_source_source_payload_addr;
+wire litedramcore_bankmachine0_pipe_valid_sink_valid;
+wire litedramcore_bankmachine0_pipe_valid_sink_ready;
+wire litedramcore_bankmachine0_pipe_valid_sink_first;
+wire litedramcore_bankmachine0_pipe_valid_sink_last;
+wire litedramcore_bankmachine0_pipe_valid_sink_payload_we;
+wire [20:0] litedramcore_bankmachine0_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine0_pipe_valid_source_ready;
+reg litedramcore_bankmachine0_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine0_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0;
+reg [20:0] litedramcore_bankmachine0_pipe_valid_source_payload_addr = 21'd0;
+reg [13:0] litedramcore_bankmachine0_row = 14'd0;
+reg litedramcore_bankmachine0_row_opened = 1'd0;
+wire litedramcore_bankmachine0_row_hit;
+reg litedramcore_bankmachine0_row_open = 1'd0;
+reg litedramcore_bankmachine0_row_close = 1'd0;
+reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine0_twtpcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine0_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine0_trccon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine0_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine0_trccon_count = 3'd0;
+wire litedramcore_bankmachine0_trascon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine0_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine0_trascon_count = 3'd0;
+wire litedramcore_bankmachine1_req_valid;
+wire litedramcore_bankmachine1_req_ready;
+wire litedramcore_bankmachine1_req_we;
+wire [20:0] litedramcore_bankmachine1_req_addr;
+wire litedramcore_bankmachine1_req_lock;
+reg litedramcore_bankmachine1_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine1_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine1_refresh_req;
+reg litedramcore_bankmachine1_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine1_cmd_valid = 1'd0;
+reg litedramcore_bankmachine1_cmd_ready = 1'd0;
+reg [13:0] litedramcore_bankmachine1_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine1_cmd_payload_ba;
+reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine1_auto_precharge = 1'd0;
+wire litedramcore_bankmachine1_sink_valid;
+wire litedramcore_bankmachine1_sink_ready;
+reg litedramcore_bankmachine1_sink_first = 1'd0;
+reg litedramcore_bankmachine1_sink_last = 1'd0;
+wire litedramcore_bankmachine1_sink_payload_we;
+wire [20:0] litedramcore_bankmachine1_sink_payload_addr;
+wire litedramcore_bankmachine1_source_valid;
+wire litedramcore_bankmachine1_source_ready;
+wire litedramcore_bankmachine1_source_first;
+wire litedramcore_bankmachine1_source_last;
+wire litedramcore_bankmachine1_source_payload_we;
+wire [20:0] litedramcore_bankmachine1_source_payload_addr;
+wire litedramcore_bankmachine1_syncfifo1_we;
+wire litedramcore_bankmachine1_syncfifo1_writable;
+wire litedramcore_bankmachine1_syncfifo1_re;
+wire litedramcore_bankmachine1_syncfifo1_readable;
+wire [23:0] litedramcore_bankmachine1_syncfifo1_din;
+wire [23:0] litedramcore_bankmachine1_syncfifo1_dout;
+reg [4:0] litedramcore_bankmachine1_level = 5'd0;
+reg litedramcore_bankmachine1_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine1_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine1_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine1_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine1_wrport_dat_r;
+wire litedramcore_bankmachine1_wrport_we;
+wire [23:0] litedramcore_bankmachine1_wrport_dat_w;
+wire litedramcore_bankmachine1_do_read;
+wire [3:0] litedramcore_bankmachine1_rdport_adr;
+wire [23:0] litedramcore_bankmachine1_rdport_dat_r;
+wire litedramcore_bankmachine1_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine1_fifo_in_payload_addr;
+wire litedramcore_bankmachine1_fifo_in_first;
+wire litedramcore_bankmachine1_fifo_in_last;
+wire litedramcore_bankmachine1_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine1_fifo_out_payload_addr;
+wire litedramcore_bankmachine1_fifo_out_first;
+wire litedramcore_bankmachine1_fifo_out_last;
+wire litedramcore_bankmachine1_sink_sink_valid;
+wire litedramcore_bankmachine1_sink_sink_ready;
+wire litedramcore_bankmachine1_sink_sink_first;
+wire litedramcore_bankmachine1_sink_sink_last;
+wire litedramcore_bankmachine1_sink_sink_payload_we;
+wire [20:0] litedramcore_bankmachine1_sink_sink_payload_addr;
+wire litedramcore_bankmachine1_source_source_valid;
+wire litedramcore_bankmachine1_source_source_ready;
+wire litedramcore_bankmachine1_source_source_first;
+wire litedramcore_bankmachine1_source_source_last;
+wire litedramcore_bankmachine1_source_source_payload_we;
+wire [20:0] litedramcore_bankmachine1_source_source_payload_addr;
+wire litedramcore_bankmachine1_pipe_valid_sink_valid;
+wire litedramcore_bankmachine1_pipe_valid_sink_ready;
+wire litedramcore_bankmachine1_pipe_valid_sink_first;
+wire litedramcore_bankmachine1_pipe_valid_sink_last;
+wire litedramcore_bankmachine1_pipe_valid_sink_payload_we;
+wire [20:0] litedramcore_bankmachine1_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine1_pipe_valid_source_ready;
+reg litedramcore_bankmachine1_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine1_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0;
+reg [20:0] litedramcore_bankmachine1_pipe_valid_source_payload_addr = 21'd0;
+reg [13:0] litedramcore_bankmachine1_row = 14'd0;
+reg litedramcore_bankmachine1_row_opened = 1'd0;
+wire litedramcore_bankmachine1_row_hit;
+reg litedramcore_bankmachine1_row_open = 1'd0;
+reg litedramcore_bankmachine1_row_close = 1'd0;
+reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine1_twtpcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine1_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine1_trccon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine1_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine1_trccon_count = 3'd0;
+wire litedramcore_bankmachine1_trascon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine1_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine1_trascon_count = 3'd0;
+wire litedramcore_bankmachine2_req_valid;
+wire litedramcore_bankmachine2_req_ready;
+wire litedramcore_bankmachine2_req_we;
+wire [20:0] litedramcore_bankmachine2_req_addr;
+wire litedramcore_bankmachine2_req_lock;
+reg litedramcore_bankmachine2_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine2_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine2_refresh_req;
+reg litedramcore_bankmachine2_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine2_cmd_valid = 1'd0;
+reg litedramcore_bankmachine2_cmd_ready = 1'd0;
+reg [13:0] litedramcore_bankmachine2_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine2_cmd_payload_ba;
+reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine2_auto_precharge = 1'd0;
+wire litedramcore_bankmachine2_sink_valid;
+wire litedramcore_bankmachine2_sink_ready;
+reg litedramcore_bankmachine2_sink_first = 1'd0;
+reg litedramcore_bankmachine2_sink_last = 1'd0;
+wire litedramcore_bankmachine2_sink_payload_we;
+wire [20:0] litedramcore_bankmachine2_sink_payload_addr;
+wire litedramcore_bankmachine2_source_valid;
+wire litedramcore_bankmachine2_source_ready;
+wire litedramcore_bankmachine2_source_first;
+wire litedramcore_bankmachine2_source_last;
+wire litedramcore_bankmachine2_source_payload_we;
+wire [20:0] litedramcore_bankmachine2_source_payload_addr;
+wire litedramcore_bankmachine2_syncfifo2_we;
+wire litedramcore_bankmachine2_syncfifo2_writable;
+wire litedramcore_bankmachine2_syncfifo2_re;
+wire litedramcore_bankmachine2_syncfifo2_readable;
+wire [23:0] litedramcore_bankmachine2_syncfifo2_din;
+wire [23:0] litedramcore_bankmachine2_syncfifo2_dout;
+reg [4:0] litedramcore_bankmachine2_level = 5'd0;
+reg litedramcore_bankmachine2_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine2_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine2_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine2_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine2_wrport_dat_r;
+wire litedramcore_bankmachine2_wrport_we;
+wire [23:0] litedramcore_bankmachine2_wrport_dat_w;
+wire litedramcore_bankmachine2_do_read;
+wire [3:0] litedramcore_bankmachine2_rdport_adr;
+wire [23:0] litedramcore_bankmachine2_rdport_dat_r;
+wire litedramcore_bankmachine2_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine2_fifo_in_payload_addr;
+wire litedramcore_bankmachine2_fifo_in_first;
+wire litedramcore_bankmachine2_fifo_in_last;
+wire litedramcore_bankmachine2_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine2_fifo_out_payload_addr;
+wire litedramcore_bankmachine2_fifo_out_first;
+wire litedramcore_bankmachine2_fifo_out_last;
+wire litedramcore_bankmachine2_sink_sink_valid;
+wire litedramcore_bankmachine2_sink_sink_ready;
+wire litedramcore_bankmachine2_sink_sink_first;
+wire litedramcore_bankmachine2_sink_sink_last;
+wire litedramcore_bankmachine2_sink_sink_payload_we;
+wire [20:0] litedramcore_bankmachine2_sink_sink_payload_addr;
+wire litedramcore_bankmachine2_source_source_valid;
+wire litedramcore_bankmachine2_source_source_ready;
+wire litedramcore_bankmachine2_source_source_first;
+wire litedramcore_bankmachine2_source_source_last;
+wire litedramcore_bankmachine2_source_source_payload_we;
+wire [20:0] litedramcore_bankmachine2_source_source_payload_addr;
+wire litedramcore_bankmachine2_pipe_valid_sink_valid;
+wire litedramcore_bankmachine2_pipe_valid_sink_ready;
+wire litedramcore_bankmachine2_pipe_valid_sink_first;
+wire litedramcore_bankmachine2_pipe_valid_sink_last;
+wire litedramcore_bankmachine2_pipe_valid_sink_payload_we;
+wire [20:0] litedramcore_bankmachine2_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine2_pipe_valid_source_ready;
+reg litedramcore_bankmachine2_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine2_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0;
+reg [20:0] litedramcore_bankmachine2_pipe_valid_source_payload_addr = 21'd0;
+reg [13:0] litedramcore_bankmachine2_row = 14'd0;
+reg litedramcore_bankmachine2_row_opened = 1'd0;
+wire litedramcore_bankmachine2_row_hit;
+reg litedramcore_bankmachine2_row_open = 1'd0;
+reg litedramcore_bankmachine2_row_close = 1'd0;
+reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine2_twtpcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine2_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine2_trccon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine2_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine2_trccon_count = 3'd0;
+wire litedramcore_bankmachine2_trascon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine2_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine2_trascon_count = 3'd0;
+wire litedramcore_bankmachine3_req_valid;
+wire litedramcore_bankmachine3_req_ready;
+wire litedramcore_bankmachine3_req_we;
+wire [20:0] litedramcore_bankmachine3_req_addr;
+wire litedramcore_bankmachine3_req_lock;
+reg litedramcore_bankmachine3_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine3_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine3_refresh_req;
+reg litedramcore_bankmachine3_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine3_cmd_valid = 1'd0;
+reg litedramcore_bankmachine3_cmd_ready = 1'd0;
+reg [13:0] litedramcore_bankmachine3_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine3_cmd_payload_ba;
+reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine3_auto_precharge = 1'd0;
+wire litedramcore_bankmachine3_sink_valid;
+wire litedramcore_bankmachine3_sink_ready;
+reg litedramcore_bankmachine3_sink_first = 1'd0;
+reg litedramcore_bankmachine3_sink_last = 1'd0;
+wire litedramcore_bankmachine3_sink_payload_we;
+wire [20:0] litedramcore_bankmachine3_sink_payload_addr;
+wire litedramcore_bankmachine3_source_valid;
+wire litedramcore_bankmachine3_source_ready;
+wire litedramcore_bankmachine3_source_first;
+wire litedramcore_bankmachine3_source_last;
+wire litedramcore_bankmachine3_source_payload_we;
+wire [20:0] litedramcore_bankmachine3_source_payload_addr;
+wire litedramcore_bankmachine3_syncfifo3_we;
+wire litedramcore_bankmachine3_syncfifo3_writable;
+wire litedramcore_bankmachine3_syncfifo3_re;
+wire litedramcore_bankmachine3_syncfifo3_readable;
+wire [23:0] litedramcore_bankmachine3_syncfifo3_din;
+wire [23:0] litedramcore_bankmachine3_syncfifo3_dout;
+reg [4:0] litedramcore_bankmachine3_level = 5'd0;
+reg litedramcore_bankmachine3_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine3_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine3_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine3_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine3_wrport_dat_r;
+wire litedramcore_bankmachine3_wrport_we;
+wire [23:0] litedramcore_bankmachine3_wrport_dat_w;
+wire litedramcore_bankmachine3_do_read;
+wire [3:0] litedramcore_bankmachine3_rdport_adr;
+wire [23:0] litedramcore_bankmachine3_rdport_dat_r;
+wire litedramcore_bankmachine3_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine3_fifo_in_payload_addr;
+wire litedramcore_bankmachine3_fifo_in_first;
+wire litedramcore_bankmachine3_fifo_in_last;
+wire litedramcore_bankmachine3_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine3_fifo_out_payload_addr;
+wire litedramcore_bankmachine3_fifo_out_first;
+wire litedramcore_bankmachine3_fifo_out_last;
+wire litedramcore_bankmachine3_sink_sink_valid;
+wire litedramcore_bankmachine3_sink_sink_ready;
+wire litedramcore_bankmachine3_sink_sink_first;
+wire litedramcore_bankmachine3_sink_sink_last;
+wire litedramcore_bankmachine3_sink_sink_payload_we;
+wire [20:0] litedramcore_bankmachine3_sink_sink_payload_addr;
+wire litedramcore_bankmachine3_source_source_valid;
+wire litedramcore_bankmachine3_source_source_ready;
+wire litedramcore_bankmachine3_source_source_first;
+wire litedramcore_bankmachine3_source_source_last;
+wire litedramcore_bankmachine3_source_source_payload_we;
+wire [20:0] litedramcore_bankmachine3_source_source_payload_addr;
+wire litedramcore_bankmachine3_pipe_valid_sink_valid;
+wire litedramcore_bankmachine3_pipe_valid_sink_ready;
+wire litedramcore_bankmachine3_pipe_valid_sink_first;
+wire litedramcore_bankmachine3_pipe_valid_sink_last;
+wire litedramcore_bankmachine3_pipe_valid_sink_payload_we;
+wire [20:0] litedramcore_bankmachine3_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine3_pipe_valid_source_ready;
+reg litedramcore_bankmachine3_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine3_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0;
+reg [20:0] litedramcore_bankmachine3_pipe_valid_source_payload_addr = 21'd0;
+reg [13:0] litedramcore_bankmachine3_row = 14'd0;
+reg litedramcore_bankmachine3_row_opened = 1'd0;
+wire litedramcore_bankmachine3_row_hit;
+reg litedramcore_bankmachine3_row_open = 1'd0;
+reg litedramcore_bankmachine3_row_close = 1'd0;
+reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine3_twtpcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine3_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine3_trccon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine3_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine3_trccon_count = 3'd0;
+wire litedramcore_bankmachine3_trascon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine3_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine3_trascon_count = 3'd0;
+wire litedramcore_bankmachine4_req_valid;
+wire litedramcore_bankmachine4_req_ready;
+wire litedramcore_bankmachine4_req_we;
+wire [20:0] litedramcore_bankmachine4_req_addr;
+wire litedramcore_bankmachine4_req_lock;
+reg litedramcore_bankmachine4_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine4_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine4_refresh_req;
+reg litedramcore_bankmachine4_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine4_cmd_valid = 1'd0;
+reg litedramcore_bankmachine4_cmd_ready = 1'd0;
+reg [13:0] litedramcore_bankmachine4_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine4_cmd_payload_ba;
+reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine4_auto_precharge = 1'd0;
+wire litedramcore_bankmachine4_sink_valid;
+wire litedramcore_bankmachine4_sink_ready;
+reg litedramcore_bankmachine4_sink_first = 1'd0;
+reg litedramcore_bankmachine4_sink_last = 1'd0;
+wire litedramcore_bankmachine4_sink_payload_we;
+wire [20:0] litedramcore_bankmachine4_sink_payload_addr;
+wire litedramcore_bankmachine4_source_valid;
+wire litedramcore_bankmachine4_source_ready;
+wire litedramcore_bankmachine4_source_first;
+wire litedramcore_bankmachine4_source_last;
+wire litedramcore_bankmachine4_source_payload_we;
+wire [20:0] litedramcore_bankmachine4_source_payload_addr;
+wire litedramcore_bankmachine4_syncfifo4_we;
+wire litedramcore_bankmachine4_syncfifo4_writable;
+wire litedramcore_bankmachine4_syncfifo4_re;
+wire litedramcore_bankmachine4_syncfifo4_readable;
+wire [23:0] litedramcore_bankmachine4_syncfifo4_din;
+wire [23:0] litedramcore_bankmachine4_syncfifo4_dout;
+reg [4:0] litedramcore_bankmachine4_level = 5'd0;
+reg litedramcore_bankmachine4_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine4_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine4_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine4_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine4_wrport_dat_r;
+wire litedramcore_bankmachine4_wrport_we;
+wire [23:0] litedramcore_bankmachine4_wrport_dat_w;
+wire litedramcore_bankmachine4_do_read;
+wire [3:0] litedramcore_bankmachine4_rdport_adr;
+wire [23:0] litedramcore_bankmachine4_rdport_dat_r;
+wire litedramcore_bankmachine4_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine4_fifo_in_payload_addr;
+wire litedramcore_bankmachine4_fifo_in_first;
+wire litedramcore_bankmachine4_fifo_in_last;
+wire litedramcore_bankmachine4_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine4_fifo_out_payload_addr;
+wire litedramcore_bankmachine4_fifo_out_first;
+wire litedramcore_bankmachine4_fifo_out_last;
+wire litedramcore_bankmachine4_sink_sink_valid;
+wire litedramcore_bankmachine4_sink_sink_ready;
+wire litedramcore_bankmachine4_sink_sink_first;
+wire litedramcore_bankmachine4_sink_sink_last;
+wire litedramcore_bankmachine4_sink_sink_payload_we;
+wire [20:0] litedramcore_bankmachine4_sink_sink_payload_addr;
+wire litedramcore_bankmachine4_source_source_valid;
+wire litedramcore_bankmachine4_source_source_ready;
+wire litedramcore_bankmachine4_source_source_first;
+wire litedramcore_bankmachine4_source_source_last;
+wire litedramcore_bankmachine4_source_source_payload_we;
+wire [20:0] litedramcore_bankmachine4_source_source_payload_addr;
+wire litedramcore_bankmachine4_pipe_valid_sink_valid;
+wire litedramcore_bankmachine4_pipe_valid_sink_ready;
+wire litedramcore_bankmachine4_pipe_valid_sink_first;
+wire litedramcore_bankmachine4_pipe_valid_sink_last;
+wire litedramcore_bankmachine4_pipe_valid_sink_payload_we;
+wire [20:0] litedramcore_bankmachine4_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine4_pipe_valid_source_ready;
+reg litedramcore_bankmachine4_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine4_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0;
+reg [20:0] litedramcore_bankmachine4_pipe_valid_source_payload_addr = 21'd0;
+reg [13:0] litedramcore_bankmachine4_row = 14'd0;
+reg litedramcore_bankmachine4_row_opened = 1'd0;
+wire litedramcore_bankmachine4_row_hit;
+reg litedramcore_bankmachine4_row_open = 1'd0;
+reg litedramcore_bankmachine4_row_close = 1'd0;
+reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine4_twtpcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine4_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine4_trccon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine4_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine4_trccon_count = 3'd0;
+wire litedramcore_bankmachine4_trascon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine4_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine4_trascon_count = 3'd0;
+wire litedramcore_bankmachine5_req_valid;
+wire litedramcore_bankmachine5_req_ready;
+wire litedramcore_bankmachine5_req_we;
+wire [20:0] litedramcore_bankmachine5_req_addr;
+wire litedramcore_bankmachine5_req_lock;
+reg litedramcore_bankmachine5_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine5_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine5_refresh_req;
+reg litedramcore_bankmachine5_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine5_cmd_valid = 1'd0;
+reg litedramcore_bankmachine5_cmd_ready = 1'd0;
+reg [13:0] litedramcore_bankmachine5_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine5_cmd_payload_ba;
+reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine5_auto_precharge = 1'd0;
+wire litedramcore_bankmachine5_sink_valid;
+wire litedramcore_bankmachine5_sink_ready;
+reg litedramcore_bankmachine5_sink_first = 1'd0;
+reg litedramcore_bankmachine5_sink_last = 1'd0;
+wire litedramcore_bankmachine5_sink_payload_we;
+wire [20:0] litedramcore_bankmachine5_sink_payload_addr;
+wire litedramcore_bankmachine5_source_valid;
+wire litedramcore_bankmachine5_source_ready;
+wire litedramcore_bankmachine5_source_first;
+wire litedramcore_bankmachine5_source_last;
+wire litedramcore_bankmachine5_source_payload_we;
+wire [20:0] litedramcore_bankmachine5_source_payload_addr;
+wire litedramcore_bankmachine5_syncfifo5_we;
+wire litedramcore_bankmachine5_syncfifo5_writable;
+wire litedramcore_bankmachine5_syncfifo5_re;
+wire litedramcore_bankmachine5_syncfifo5_readable;
+wire [23:0] litedramcore_bankmachine5_syncfifo5_din;
+wire [23:0] litedramcore_bankmachine5_syncfifo5_dout;
+reg [4:0] litedramcore_bankmachine5_level = 5'd0;
+reg litedramcore_bankmachine5_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine5_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine5_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine5_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine5_wrport_dat_r;
+wire litedramcore_bankmachine5_wrport_we;
+wire [23:0] litedramcore_bankmachine5_wrport_dat_w;
+wire litedramcore_bankmachine5_do_read;
+wire [3:0] litedramcore_bankmachine5_rdport_adr;
+wire [23:0] litedramcore_bankmachine5_rdport_dat_r;
+wire litedramcore_bankmachine5_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine5_fifo_in_payload_addr;
+wire litedramcore_bankmachine5_fifo_in_first;
+wire litedramcore_bankmachine5_fifo_in_last;
+wire litedramcore_bankmachine5_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine5_fifo_out_payload_addr;
+wire litedramcore_bankmachine5_fifo_out_first;
+wire litedramcore_bankmachine5_fifo_out_last;
+wire litedramcore_bankmachine5_sink_sink_valid;
+wire litedramcore_bankmachine5_sink_sink_ready;
+wire litedramcore_bankmachine5_sink_sink_first;
+wire litedramcore_bankmachine5_sink_sink_last;
+wire litedramcore_bankmachine5_sink_sink_payload_we;
+wire [20:0] litedramcore_bankmachine5_sink_sink_payload_addr;
+wire litedramcore_bankmachine5_source_source_valid;
+wire litedramcore_bankmachine5_source_source_ready;
+wire litedramcore_bankmachine5_source_source_first;
+wire litedramcore_bankmachine5_source_source_last;
+wire litedramcore_bankmachine5_source_source_payload_we;
+wire [20:0] litedramcore_bankmachine5_source_source_payload_addr;
+wire litedramcore_bankmachine5_pipe_valid_sink_valid;
+wire litedramcore_bankmachine5_pipe_valid_sink_ready;
+wire litedramcore_bankmachine5_pipe_valid_sink_first;
+wire litedramcore_bankmachine5_pipe_valid_sink_last;
+wire litedramcore_bankmachine5_pipe_valid_sink_payload_we;
+wire [20:0] litedramcore_bankmachine5_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine5_pipe_valid_source_ready;
+reg litedramcore_bankmachine5_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine5_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0;
+reg [20:0] litedramcore_bankmachine5_pipe_valid_source_payload_addr = 21'd0;
+reg [13:0] litedramcore_bankmachine5_row = 14'd0;
+reg litedramcore_bankmachine5_row_opened = 1'd0;
+wire litedramcore_bankmachine5_row_hit;
+reg litedramcore_bankmachine5_row_open = 1'd0;
+reg litedramcore_bankmachine5_row_close = 1'd0;
+reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine5_twtpcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine5_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine5_trccon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine5_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine5_trccon_count = 3'd0;
+wire litedramcore_bankmachine5_trascon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine5_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine5_trascon_count = 3'd0;
+wire litedramcore_bankmachine6_req_valid;
+wire litedramcore_bankmachine6_req_ready;
+wire litedramcore_bankmachine6_req_we;
+wire [20:0] litedramcore_bankmachine6_req_addr;
+wire litedramcore_bankmachine6_req_lock;
+reg litedramcore_bankmachine6_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine6_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine6_refresh_req;
+reg litedramcore_bankmachine6_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine6_cmd_valid = 1'd0;
+reg litedramcore_bankmachine6_cmd_ready = 1'd0;
+reg [13:0] litedramcore_bankmachine6_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine6_cmd_payload_ba;
+reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine6_auto_precharge = 1'd0;
+wire litedramcore_bankmachine6_sink_valid;
+wire litedramcore_bankmachine6_sink_ready;
+reg litedramcore_bankmachine6_sink_first = 1'd0;
+reg litedramcore_bankmachine6_sink_last = 1'd0;
+wire litedramcore_bankmachine6_sink_payload_we;
+wire [20:0] litedramcore_bankmachine6_sink_payload_addr;
+wire litedramcore_bankmachine6_source_valid;
+wire litedramcore_bankmachine6_source_ready;
+wire litedramcore_bankmachine6_source_first;
+wire litedramcore_bankmachine6_source_last;
+wire litedramcore_bankmachine6_source_payload_we;
+wire [20:0] litedramcore_bankmachine6_source_payload_addr;
+wire litedramcore_bankmachine6_syncfifo6_we;
+wire litedramcore_bankmachine6_syncfifo6_writable;
+wire litedramcore_bankmachine6_syncfifo6_re;
+wire litedramcore_bankmachine6_syncfifo6_readable;
+wire [23:0] litedramcore_bankmachine6_syncfifo6_din;
+wire [23:0] litedramcore_bankmachine6_syncfifo6_dout;
+reg [4:0] litedramcore_bankmachine6_level = 5'd0;
+reg litedramcore_bankmachine6_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine6_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine6_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine6_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine6_wrport_dat_r;
+wire litedramcore_bankmachine6_wrport_we;
+wire [23:0] litedramcore_bankmachine6_wrport_dat_w;
+wire litedramcore_bankmachine6_do_read;
+wire [3:0] litedramcore_bankmachine6_rdport_adr;
+wire [23:0] litedramcore_bankmachine6_rdport_dat_r;
+wire litedramcore_bankmachine6_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine6_fifo_in_payload_addr;
+wire litedramcore_bankmachine6_fifo_in_first;
+wire litedramcore_bankmachine6_fifo_in_last;
+wire litedramcore_bankmachine6_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine6_fifo_out_payload_addr;
+wire litedramcore_bankmachine6_fifo_out_first;
+wire litedramcore_bankmachine6_fifo_out_last;
+wire litedramcore_bankmachine6_sink_sink_valid;
+wire litedramcore_bankmachine6_sink_sink_ready;
+wire litedramcore_bankmachine6_sink_sink_first;
+wire litedramcore_bankmachine6_sink_sink_last;
+wire litedramcore_bankmachine6_sink_sink_payload_we;
+wire [20:0] litedramcore_bankmachine6_sink_sink_payload_addr;
+wire litedramcore_bankmachine6_source_source_valid;
+wire litedramcore_bankmachine6_source_source_ready;
+wire litedramcore_bankmachine6_source_source_first;
+wire litedramcore_bankmachine6_source_source_last;
+wire litedramcore_bankmachine6_source_source_payload_we;
+wire [20:0] litedramcore_bankmachine6_source_source_payload_addr;
+wire litedramcore_bankmachine6_pipe_valid_sink_valid;
+wire litedramcore_bankmachine6_pipe_valid_sink_ready;
+wire litedramcore_bankmachine6_pipe_valid_sink_first;
+wire litedramcore_bankmachine6_pipe_valid_sink_last;
+wire litedramcore_bankmachine6_pipe_valid_sink_payload_we;
+wire [20:0] litedramcore_bankmachine6_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine6_pipe_valid_source_ready;
+reg litedramcore_bankmachine6_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine6_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0;
+reg [20:0] litedramcore_bankmachine6_pipe_valid_source_payload_addr = 21'd0;
+reg [13:0] litedramcore_bankmachine6_row = 14'd0;
+reg litedramcore_bankmachine6_row_opened = 1'd0;
+wire litedramcore_bankmachine6_row_hit;
+reg litedramcore_bankmachine6_row_open = 1'd0;
+reg litedramcore_bankmachine6_row_close = 1'd0;
+reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine6_twtpcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine6_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine6_trccon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine6_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine6_trccon_count = 3'd0;
+wire litedramcore_bankmachine6_trascon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine6_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine6_trascon_count = 3'd0;
+wire litedramcore_bankmachine7_req_valid;
+wire litedramcore_bankmachine7_req_ready;
+wire litedramcore_bankmachine7_req_we;
+wire [20:0] litedramcore_bankmachine7_req_addr;
+wire litedramcore_bankmachine7_req_lock;
+reg litedramcore_bankmachine7_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine7_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine7_refresh_req;
+reg litedramcore_bankmachine7_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine7_cmd_valid = 1'd0;
+reg litedramcore_bankmachine7_cmd_ready = 1'd0;
+reg [13:0] litedramcore_bankmachine7_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine7_cmd_payload_ba;
+reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine7_auto_precharge = 1'd0;
+wire litedramcore_bankmachine7_sink_valid;
+wire litedramcore_bankmachine7_sink_ready;
+reg litedramcore_bankmachine7_sink_first = 1'd0;
+reg litedramcore_bankmachine7_sink_last = 1'd0;
+wire litedramcore_bankmachine7_sink_payload_we;
+wire [20:0] litedramcore_bankmachine7_sink_payload_addr;
+wire litedramcore_bankmachine7_source_valid;
+wire litedramcore_bankmachine7_source_ready;
+wire litedramcore_bankmachine7_source_first;
+wire litedramcore_bankmachine7_source_last;
+wire litedramcore_bankmachine7_source_payload_we;
+wire [20:0] litedramcore_bankmachine7_source_payload_addr;
+wire litedramcore_bankmachine7_syncfifo7_we;
+wire litedramcore_bankmachine7_syncfifo7_writable;
+wire litedramcore_bankmachine7_syncfifo7_re;
+wire litedramcore_bankmachine7_syncfifo7_readable;
+wire [23:0] litedramcore_bankmachine7_syncfifo7_din;
+wire [23:0] litedramcore_bankmachine7_syncfifo7_dout;
+reg [4:0] litedramcore_bankmachine7_level = 5'd0;
+reg litedramcore_bankmachine7_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine7_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine7_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine7_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine7_wrport_dat_r;
+wire litedramcore_bankmachine7_wrport_we;
+wire [23:0] litedramcore_bankmachine7_wrport_dat_w;
+wire litedramcore_bankmachine7_do_read;
+wire [3:0] litedramcore_bankmachine7_rdport_adr;
+wire [23:0] litedramcore_bankmachine7_rdport_dat_r;
+wire litedramcore_bankmachine7_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine7_fifo_in_payload_addr;
+wire litedramcore_bankmachine7_fifo_in_first;
+wire litedramcore_bankmachine7_fifo_in_last;
+wire litedramcore_bankmachine7_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine7_fifo_out_payload_addr;
+wire litedramcore_bankmachine7_fifo_out_first;
+wire litedramcore_bankmachine7_fifo_out_last;
+wire litedramcore_bankmachine7_sink_sink_valid;
+wire litedramcore_bankmachine7_sink_sink_ready;
+wire litedramcore_bankmachine7_sink_sink_first;
+wire litedramcore_bankmachine7_sink_sink_last;
+wire litedramcore_bankmachine7_sink_sink_payload_we;
+wire [20:0] litedramcore_bankmachine7_sink_sink_payload_addr;
+wire litedramcore_bankmachine7_source_source_valid;
+wire litedramcore_bankmachine7_source_source_ready;
+wire litedramcore_bankmachine7_source_source_first;
+wire litedramcore_bankmachine7_source_source_last;
+wire litedramcore_bankmachine7_source_source_payload_we;
+wire [20:0] litedramcore_bankmachine7_source_source_payload_addr;
+wire litedramcore_bankmachine7_pipe_valid_sink_valid;
+wire litedramcore_bankmachine7_pipe_valid_sink_ready;
+wire litedramcore_bankmachine7_pipe_valid_sink_first;
+wire litedramcore_bankmachine7_pipe_valid_sink_last;
+wire litedramcore_bankmachine7_pipe_valid_sink_payload_we;
+wire [20:0] litedramcore_bankmachine7_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine7_pipe_valid_source_ready;
+reg litedramcore_bankmachine7_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine7_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0;
+reg [20:0] litedramcore_bankmachine7_pipe_valid_source_payload_addr = 21'd0;
+reg [13:0] litedramcore_bankmachine7_row = 14'd0;
+reg litedramcore_bankmachine7_row_opened = 1'd0;
+wire litedramcore_bankmachine7_row_hit;
+reg litedramcore_bankmachine7_row_open = 1'd0;
+reg litedramcore_bankmachine7_row_close = 1'd0;
+reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine7_twtpcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine7_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine7_trccon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine7_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine7_trccon_count = 3'd0;
+wire litedramcore_bankmachine7_trascon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine7_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine7_trascon_count = 3'd0;
+wire litedramcore_ras_allowed;
+wire litedramcore_cas_allowed;
+wire [1:0] litedramcore_rdcmdphase;
+wire [1:0] litedramcore_wrcmdphase;
+reg litedramcore_choose_cmd_want_reads = 1'd0;
+reg litedramcore_choose_cmd_want_writes = 1'd0;
+reg litedramcore_choose_cmd_want_cmds = 1'd0;
+reg litedramcore_choose_cmd_want_activates = 1'd0;
+wire litedramcore_choose_cmd_cmd_valid;
+reg litedramcore_choose_cmd_cmd_ready = 1'd0;
+wire [13:0] litedramcore_choose_cmd_cmd_payload_a;
+wire [2:0] litedramcore_choose_cmd_cmd_payload_ba;
+reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
+reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
+reg litedramcore_choose_cmd_cmd_payload_we = 1'd0;
+wire litedramcore_choose_cmd_cmd_payload_is_cmd;
+wire litedramcore_choose_cmd_cmd_payload_is_read;
+wire litedramcore_choose_cmd_cmd_payload_is_write;
+reg [7:0] litedramcore_choose_cmd_valids = 8'd0;
+wire [7:0] litedramcore_choose_cmd_request;
+reg [2:0] litedramcore_choose_cmd_grant = 3'd0;
+wire litedramcore_choose_cmd_ce;
+reg litedramcore_choose_req_want_reads = 1'd0;
+reg litedramcore_choose_req_want_writes = 1'd0;
+reg litedramcore_choose_req_want_cmds = 1'd0;
+reg litedramcore_choose_req_want_activates = 1'd0;
+wire litedramcore_choose_req_cmd_valid;
+reg litedramcore_choose_req_cmd_ready = 1'd0;
+wire [13:0] litedramcore_choose_req_cmd_payload_a;
+wire [2:0] litedramcore_choose_req_cmd_payload_ba;
+reg litedramcore_choose_req_cmd_payload_cas = 1'd0;
+reg litedramcore_choose_req_cmd_payload_ras = 1'd0;
+reg litedramcore_choose_req_cmd_payload_we = 1'd0;
+wire litedramcore_choose_req_cmd_payload_is_cmd;
+wire litedramcore_choose_req_cmd_payload_is_read;
+wire litedramcore_choose_req_cmd_payload_is_write;
+reg [7:0] litedramcore_choose_req_valids = 8'd0;
+wire [7:0] litedramcore_choose_req_request;
+reg [2:0] litedramcore_choose_req_grant = 3'd0;
+wire litedramcore_choose_req_ce;
+reg [13:0] litedramcore_nop_a = 14'd0;
+reg [2:0] litedramcore_nop_ba = 3'd0;
+reg [1:0] litedramcore_steerer_sel0 = 2'd0;
+reg [1:0] litedramcore_steerer_sel1 = 2'd0;
+reg [1:0] litedramcore_steerer_sel2 = 2'd0;
+reg [1:0] litedramcore_steerer_sel3 = 2'd0;
+reg litedramcore_steerer0 = 1'd1;
+reg litedramcore_steerer1 = 1'd1;
+reg litedramcore_steerer2 = 1'd1;
+reg litedramcore_steerer3 = 1'd1;
+reg litedramcore_steerer4 = 1'd1;
+reg litedramcore_steerer5 = 1'd1;
+reg litedramcore_steerer6 = 1'd1;
+reg litedramcore_steerer7 = 1'd1;
+wire litedramcore_trrdcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_trrdcon_ready = 1'd0;
+reg litedramcore_trrdcon_count = 1'd0;
+wire litedramcore_tfawcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_tfawcon_ready = 1'd1;
+wire [2:0] litedramcore_tfawcon_count;
+reg [4:0] litedramcore_tfawcon_window = 5'd0;
+wire litedramcore_tccdcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_tccdcon_ready = 1'd0;
+reg litedramcore_tccdcon_count = 1'd0;
+wire litedramcore_twtrcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_twtrcon_ready = 1'd0;
+reg [2:0] litedramcore_twtrcon_count = 3'd0;
+wire litedramcore_read_available;
+wire litedramcore_write_available;
+reg litedramcore_en0 = 1'd0;
+wire litedramcore_max_time0;
+reg [4:0] litedramcore_time0 = 5'd0;
+reg litedramcore_en1 = 1'd0;
+wire litedramcore_max_time1;
+reg [3:0] litedramcore_time1 = 4'd0;
+wire litedramcore_go_to_refresh;
+reg init_done_storage = 1'd0;
+reg init_done_re = 1'd0;
+reg init_error_storage = 1'd0;
+reg init_error_re = 1'd0;
+wire [29:0] wb_bus_adr;
+wire [31:0] wb_bus_dat_w;
+wire [31:0] wb_bus_dat_r;
+wire [3:0] wb_bus_sel;
+wire wb_bus_cyc;
+wire wb_bus_stb;
+wire wb_bus_ack;
+wire wb_bus_we;
+wire [2:0] wb_bus_cti;
+wire [1:0] wb_bus_bte;
+wire wb_bus_err;
+wire user_enable;
+wire user_port_cmd_valid;
+wire user_port_cmd_ready;
+wire user_port_cmd_payload_we;
+wire [23:0] user_port_cmd_payload_addr;
+wire user_port_wdata_valid;
+wire user_port_wdata_ready;
+wire [127:0] user_port_wdata_payload_data;
+wire [15:0] user_port_wdata_payload_we;
+wire user_port_rdata_valid;
+wire user_port_rdata_ready;
+wire [127:0] user_port_rdata_payload_data;
+reg [13:0] litedramcore_adr = 14'd0;
+reg litedramcore_we = 1'd0;
+reg [31:0] litedramcore_dat_w = 32'd0;
+wire [31:0] litedramcore_dat_r;
+wire [29:0] litedramcore_wishbone_adr;
+wire [31:0] litedramcore_wishbone_dat_w;
+reg [31:0] litedramcore_wishbone_dat_r = 32'd0;
+wire [3:0] litedramcore_wishbone_sel;
+wire litedramcore_wishbone_cyc;
+wire litedramcore_wishbone_stb;
+reg litedramcore_wishbone_ack = 1'd0;
+wire litedramcore_wishbone_we;
+wire [2:0] litedramcore_wishbone_cti;
+wire [1:0] litedramcore_wishbone_bte;
+reg litedramcore_wishbone_err = 1'd0;
+wire [13:0] interface0_bank_bus_adr;
+wire interface0_bank_bus_we;
+wire [31:0] interface0_bank_bus_dat_w;
+reg [31:0] interface0_bank_bus_dat_r = 32'd0;
+reg csrbank0_init_done0_re = 1'd0;
+wire csrbank0_init_done0_r;
+reg csrbank0_init_done0_we = 1'd0;
+wire csrbank0_init_done0_w;
+reg csrbank0_init_error0_re = 1'd0;
+wire csrbank0_init_error0_r;
+reg csrbank0_init_error0_we = 1'd0;
+wire csrbank0_init_error0_w;
+wire csrbank0_sel;
+wire [13:0] interface1_bank_bus_adr;
+wire interface1_bank_bus_we;
+wire [31:0] interface1_bank_bus_dat_w;
+reg [31:0] interface1_bank_bus_dat_r = 32'd0;
+reg csrbank1_rst0_re = 1'd0;
+wire csrbank1_rst0_r;
+reg csrbank1_rst0_we = 1'd0;
+wire csrbank1_rst0_w;
+reg csrbank1_dly_sel0_re = 1'd0;
+wire [1:0] csrbank1_dly_sel0_r;
+reg csrbank1_dly_sel0_we = 1'd0;
+wire [1:0] csrbank1_dly_sel0_w;
+reg csrbank1_half_sys8x_taps0_re = 1'd0;
+wire [4:0] csrbank1_half_sys8x_taps0_r;
+reg csrbank1_half_sys8x_taps0_we = 1'd0;
+wire [4:0] csrbank1_half_sys8x_taps0_w;
+reg csrbank1_wlevel_en0_re = 1'd0;
+wire csrbank1_wlevel_en0_r;
+reg csrbank1_wlevel_en0_we = 1'd0;
+wire csrbank1_wlevel_en0_w;
+reg csrbank1_rdphase0_re = 1'd0;
+wire [1:0] csrbank1_rdphase0_r;
+reg csrbank1_rdphase0_we = 1'd0;
+wire [1:0] csrbank1_rdphase0_w;
+reg csrbank1_wrphase0_re = 1'd0;
+wire [1:0] csrbank1_wrphase0_r;
+reg csrbank1_wrphase0_we = 1'd0;
+wire [1:0] csrbank1_wrphase0_w;
+wire csrbank1_sel;
+wire [13:0] interface2_bank_bus_adr;
+wire interface2_bank_bus_we;
+wire [31:0] interface2_bank_bus_dat_w;
+reg [31:0] interface2_bank_bus_dat_r = 32'd0;
+reg csrbank2_dfii_control0_re = 1'd0;
+wire [3:0] csrbank2_dfii_control0_r;
+reg csrbank2_dfii_control0_we = 1'd0;
+wire [3:0] csrbank2_dfii_control0_w;
+reg csrbank2_dfii_pi0_command0_re = 1'd0;
+wire [5:0] csrbank2_dfii_pi0_command0_r;
+reg csrbank2_dfii_pi0_command0_we = 1'd0;
+wire [5:0] csrbank2_dfii_pi0_command0_w;
+reg csrbank2_dfii_pi0_address0_re = 1'd0;
+wire [13:0] csrbank2_dfii_pi0_address0_r;
+reg csrbank2_dfii_pi0_address0_we = 1'd0;
+wire [13:0] csrbank2_dfii_pi0_address0_w;
+reg csrbank2_dfii_pi0_baddress0_re = 1'd0;
+wire [2:0] csrbank2_dfii_pi0_baddress0_r;
+reg csrbank2_dfii_pi0_baddress0_we = 1'd0;
+wire [2:0] csrbank2_dfii_pi0_baddress0_w;
+reg csrbank2_dfii_pi0_wrdata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_wrdata0_r;
+reg csrbank2_dfii_pi0_wrdata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_wrdata0_w;
+reg csrbank2_dfii_pi0_rddata_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_rddata_r;
+reg csrbank2_dfii_pi0_rddata_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_rddata_w;
+reg csrbank2_dfii_pi1_command0_re = 1'd0;
+wire [5:0] csrbank2_dfii_pi1_command0_r;
+reg csrbank2_dfii_pi1_command0_we = 1'd0;
+wire [5:0] csrbank2_dfii_pi1_command0_w;
+reg csrbank2_dfii_pi1_address0_re = 1'd0;
+wire [13:0] csrbank2_dfii_pi1_address0_r;
+reg csrbank2_dfii_pi1_address0_we = 1'd0;
+wire [13:0] csrbank2_dfii_pi1_address0_w;
+reg csrbank2_dfii_pi1_baddress0_re = 1'd0;
+wire [2:0] csrbank2_dfii_pi1_baddress0_r;
+reg csrbank2_dfii_pi1_baddress0_we = 1'd0;
+wire [2:0] csrbank2_dfii_pi1_baddress0_w;
+reg csrbank2_dfii_pi1_wrdata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_wrdata0_r;
+reg csrbank2_dfii_pi1_wrdata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_wrdata0_w;
+reg csrbank2_dfii_pi1_rddata_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_rddata_r;
+reg csrbank2_dfii_pi1_rddata_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_rddata_w;
+reg csrbank2_dfii_pi2_command0_re = 1'd0;
+wire [5:0] csrbank2_dfii_pi2_command0_r;
+reg csrbank2_dfii_pi2_command0_we = 1'd0;
+wire [5:0] csrbank2_dfii_pi2_command0_w;
+reg csrbank2_dfii_pi2_address0_re = 1'd0;
+wire [13:0] csrbank2_dfii_pi2_address0_r;
+reg csrbank2_dfii_pi2_address0_we = 1'd0;
+wire [13:0] csrbank2_dfii_pi2_address0_w;
+reg csrbank2_dfii_pi2_baddress0_re = 1'd0;
+wire [2:0] csrbank2_dfii_pi2_baddress0_r;
+reg csrbank2_dfii_pi2_baddress0_we = 1'd0;
+wire [2:0] csrbank2_dfii_pi2_baddress0_w;
+reg csrbank2_dfii_pi2_wrdata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_wrdata0_r;
+reg csrbank2_dfii_pi2_wrdata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_wrdata0_w;
+reg csrbank2_dfii_pi2_rddata_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_rddata_r;
+reg csrbank2_dfii_pi2_rddata_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_rddata_w;
+reg csrbank2_dfii_pi3_command0_re = 1'd0;
+wire [5:0] csrbank2_dfii_pi3_command0_r;
+reg csrbank2_dfii_pi3_command0_we = 1'd0;
+wire [5:0] csrbank2_dfii_pi3_command0_w;
+reg csrbank2_dfii_pi3_address0_re = 1'd0;
+wire [13:0] csrbank2_dfii_pi3_address0_r;
+reg csrbank2_dfii_pi3_address0_we = 1'd0;
+wire [13:0] csrbank2_dfii_pi3_address0_w;
+reg csrbank2_dfii_pi3_baddress0_re = 1'd0;
+wire [2:0] csrbank2_dfii_pi3_baddress0_r;
+reg csrbank2_dfii_pi3_baddress0_we = 1'd0;
+wire [2:0] csrbank2_dfii_pi3_baddress0_w;
+reg csrbank2_dfii_pi3_wrdata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_wrdata0_r;
+reg csrbank2_dfii_pi3_wrdata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_wrdata0_w;
+reg csrbank2_dfii_pi3_rddata_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_rddata_r;
+reg csrbank2_dfii_pi3_rddata_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_rddata_w;
+wire csrbank2_sel;
+wire [13:0] csr_interconnect_adr;
+wire csr_interconnect_we;
+wire [31:0] csr_interconnect_dat_w;
+wire [31:0] csr_interconnect_dat_r;
+wire litedramcore_reset0;
+wire litedramcore_reset1;
+wire litedramcore_reset2;
+wire litedramcore_reset3;
+wire litedramcore_reset4;
+wire litedramcore_reset5;
+wire litedramcore_reset6;
+wire litedramcore_reset7;
+wire litedramcore_pll_fb;
+reg [1:0] litedramcore_refresher_state = 2'd0;
+reg [1:0] litedramcore_refresher_next_state = 2'd0;
+reg [3:0] litedramcore_bankmachine0_state = 4'd0;
+reg [3:0] litedramcore_bankmachine0_next_state = 4'd0;
+reg [3:0] litedramcore_bankmachine1_state = 4'd0;
+reg [3:0] litedramcore_bankmachine1_next_state = 4'd0;
+reg [3:0] litedramcore_bankmachine2_state = 4'd0;
+reg [3:0] litedramcore_bankmachine2_next_state = 4'd0;
+reg [3:0] litedramcore_bankmachine3_state = 4'd0;
+reg [3:0] litedramcore_bankmachine3_next_state = 4'd0;
+reg [3:0] litedramcore_bankmachine4_state = 4'd0;
+reg [3:0] litedramcore_bankmachine4_next_state = 4'd0;
+reg [3:0] litedramcore_bankmachine5_state = 4'd0;
+reg [3:0] litedramcore_bankmachine5_next_state = 4'd0;
+reg [3:0] litedramcore_bankmachine6_state = 4'd0;
+reg [3:0] litedramcore_bankmachine6_next_state = 4'd0;
+reg [3:0] litedramcore_bankmachine7_state = 4'd0;
+reg [3:0] litedramcore_bankmachine7_next_state = 4'd0;
+reg [3:0] litedramcore_multiplexer_state = 4'd0;
+reg [3:0] litedramcore_multiplexer_next_state = 4'd0;
+wire litedramcore_roundrobin0_request;
+wire litedramcore_roundrobin0_grant;
+wire litedramcore_roundrobin0_ce;
+wire litedramcore_roundrobin1_request;
+wire litedramcore_roundrobin1_grant;
+wire litedramcore_roundrobin1_ce;
+wire litedramcore_roundrobin2_request;
+wire litedramcore_roundrobin2_grant;
+wire litedramcore_roundrobin2_ce;
+wire litedramcore_roundrobin3_request;
+wire litedramcore_roundrobin3_grant;
+wire litedramcore_roundrobin3_ce;
+wire litedramcore_roundrobin4_request;
+wire litedramcore_roundrobin4_grant;
+wire litedramcore_roundrobin4_ce;
+wire litedramcore_roundrobin5_request;
+wire litedramcore_roundrobin5_grant;
+wire litedramcore_roundrobin5_ce;
+wire litedramcore_roundrobin6_request;
+wire litedramcore_roundrobin6_grant;
+wire litedramcore_roundrobin6_ce;
+wire litedramcore_roundrobin7_request;
+wire litedramcore_roundrobin7_grant;
+wire litedramcore_roundrobin7_ce;
+reg litedramcore_locked0 = 1'd0;
+reg litedramcore_locked1 = 1'd0;
+reg litedramcore_locked2 = 1'd0;
+reg litedramcore_locked3 = 1'd0;
+reg litedramcore_locked4 = 1'd0;
+reg litedramcore_locked5 = 1'd0;
+reg litedramcore_locked6 = 1'd0;
+reg litedramcore_locked7 = 1'd0;
+reg litedramcore_new_master_wdata_ready0 = 1'd0;
+reg litedramcore_new_master_wdata_ready1 = 1'd0;
+reg litedramcore_new_master_rdata_valid0 = 1'd0;
+reg litedramcore_new_master_rdata_valid1 = 1'd0;
+reg litedramcore_new_master_rdata_valid2 = 1'd0;
+reg litedramcore_new_master_rdata_valid3 = 1'd0;
+reg litedramcore_new_master_rdata_valid4 = 1'd0;
+reg litedramcore_new_master_rdata_valid5 = 1'd0;
+reg litedramcore_new_master_rdata_valid6 = 1'd0;
+reg litedramcore_new_master_rdata_valid7 = 1'd0;
+reg litedramcore_new_master_rdata_valid8 = 1'd0;
+reg [1:0] litedramcore_state = 2'd0;
+reg [1:0] litedramcore_next_state = 2'd0;
+reg [31:0] litedramcore_dat_w_next_value0 = 32'd0;
+reg litedramcore_dat_w_next_value_ce0 = 1'd0;
+reg [13:0] litedramcore_adr_next_value1 = 14'd0;
+reg litedramcore_adr_next_value_ce1 = 1'd0;
+reg litedramcore_we_next_value2 = 1'd0;
+reg litedramcore_we_next_value_ce2 = 1'd0;
+reg rhs_array_muxed0 = 1'd0;
+reg [13:0] rhs_array_muxed1 = 14'd0;
+reg [2:0] rhs_array_muxed2 = 3'd0;
+reg rhs_array_muxed3 = 1'd0;
+reg rhs_array_muxed4 = 1'd0;
+reg rhs_array_muxed5 = 1'd0;
+reg t_array_muxed0 = 1'd0;
+reg t_array_muxed1 = 1'd0;
+reg t_array_muxed2 = 1'd0;
+reg rhs_array_muxed6 = 1'd0;
+reg [13:0] rhs_array_muxed7 = 14'd0;
+reg [2:0] rhs_array_muxed8 = 3'd0;
+reg rhs_array_muxed9 = 1'd0;
+reg rhs_array_muxed10 = 1'd0;
+reg rhs_array_muxed11 = 1'd0;
+reg t_array_muxed3 = 1'd0;
+reg t_array_muxed4 = 1'd0;
+reg t_array_muxed5 = 1'd0;
+reg [20:0] rhs_array_muxed12 = 21'd0;
+reg rhs_array_muxed13 = 1'd0;
+reg rhs_array_muxed14 = 1'd0;
+reg [20:0] rhs_array_muxed15 = 21'd0;
+reg rhs_array_muxed16 = 1'd0;
+reg rhs_array_muxed17 = 1'd0;
+reg [20:0] rhs_array_muxed18 = 21'd0;
+reg rhs_array_muxed19 = 1'd0;
+reg rhs_array_muxed20 = 1'd0;
+reg [20:0] rhs_array_muxed21 = 21'd0;
+reg rhs_array_muxed22 = 1'd0;
+reg rhs_array_muxed23 = 1'd0;
+reg [20:0] rhs_array_muxed24 = 21'd0;
+reg rhs_array_muxed25 = 1'd0;
+reg rhs_array_muxed26 = 1'd0;
+reg [20:0] rhs_array_muxed27 = 21'd0;
+reg rhs_array_muxed28 = 1'd0;
+reg rhs_array_muxed29 = 1'd0;
+reg [20:0] rhs_array_muxed30 = 21'd0;
+reg rhs_array_muxed31 = 1'd0;
+reg rhs_array_muxed32 = 1'd0;
+reg [20:0] rhs_array_muxed33 = 21'd0;
+reg rhs_array_muxed34 = 1'd0;
+reg rhs_array_muxed35 = 1'd0;
+reg [2:0] array_muxed0 = 3'd0;
+reg [13:0] array_muxed1 = 14'd0;
+reg array_muxed2 = 1'd0;
+reg array_muxed3 = 1'd0;
+reg array_muxed4 = 1'd0;
+reg array_muxed5 = 1'd0;
+reg array_muxed6 = 1'd0;
+reg [2:0] array_muxed7 = 3'd0;
+reg [13:0] array_muxed8 = 14'd0;
+reg array_muxed9 = 1'd0;
+reg array_muxed10 = 1'd0;
+reg array_muxed11 = 1'd0;
+reg array_muxed12 = 1'd0;
+reg array_muxed13 = 1'd0;
+reg [2:0] array_muxed14 = 3'd0;
+reg [13:0] array_muxed15 = 14'd0;
+reg array_muxed16 = 1'd0;
+reg array_muxed17 = 1'd0;
+reg array_muxed18 = 1'd0;
+reg array_muxed19 = 1'd0;
+reg array_muxed20 = 1'd0;
+reg [2:0] array_muxed21 = 3'd0;
+reg [13:0] array_muxed22 = 14'd0;
+reg array_muxed23 = 1'd0;
+reg array_muxed24 = 1'd0;
+reg array_muxed25 = 1'd0;
+reg array_muxed26 = 1'd0;
+reg array_muxed27 = 1'd0;
+wire xilinxasyncresetsynchronizerimpl0;
+wire xilinxasyncresetsynchronizerimpl0_rst_meta;
+wire xilinxasyncresetsynchronizerimpl1;
+wire xilinxasyncresetsynchronizerimpl1_rst_meta;
+wire xilinxasyncresetsynchronizerimpl2;
+wire xilinxasyncresetsynchronizerimpl2_rst_meta;
+wire xilinxasyncresetsynchronizerimpl2_expr;
+wire xilinxasyncresetsynchronizerimpl3;
+wire xilinxasyncresetsynchronizerimpl3_rst_meta;
+wire xilinxasyncresetsynchronizerimpl3_expr;
//------------------------------------------------------------------------------
// Combinatorial Logic
assign a7ddrphy_dqs_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dqs_oe) | a7ddrphy_dqs_postamble);
assign a7ddrphy_dq_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dq_oe) | a7ddrphy_dqs_postamble);
always @(*) begin
- a7ddrphy_dfi_p0_rddata <= 32'd0;
- a7ddrphy_dfi_p0_rddata[0] <= a7ddrphy_bitslip04[0];
- a7ddrphy_dfi_p0_rddata[16] <= a7ddrphy_bitslip04[1];
- a7ddrphy_dfi_p0_rddata[1] <= a7ddrphy_bitslip14[0];
- a7ddrphy_dfi_p0_rddata[17] <= a7ddrphy_bitslip14[1];
- a7ddrphy_dfi_p0_rddata[2] <= a7ddrphy_bitslip22[0];
- a7ddrphy_dfi_p0_rddata[18] <= a7ddrphy_bitslip22[1];
- a7ddrphy_dfi_p0_rddata[3] <= a7ddrphy_bitslip32[0];
- a7ddrphy_dfi_p0_rddata[19] <= a7ddrphy_bitslip32[1];
- a7ddrphy_dfi_p0_rddata[4] <= a7ddrphy_bitslip42[0];
- a7ddrphy_dfi_p0_rddata[20] <= a7ddrphy_bitslip42[1];
- a7ddrphy_dfi_p0_rddata[5] <= a7ddrphy_bitslip52[0];
- a7ddrphy_dfi_p0_rddata[21] <= a7ddrphy_bitslip52[1];
- a7ddrphy_dfi_p0_rddata[6] <= a7ddrphy_bitslip62[0];
- a7ddrphy_dfi_p0_rddata[22] <= a7ddrphy_bitslip62[1];
- a7ddrphy_dfi_p0_rddata[7] <= a7ddrphy_bitslip72[0];
- a7ddrphy_dfi_p0_rddata[23] <= a7ddrphy_bitslip72[1];
- a7ddrphy_dfi_p0_rddata[8] <= a7ddrphy_bitslip82[0];
- a7ddrphy_dfi_p0_rddata[24] <= a7ddrphy_bitslip82[1];
- a7ddrphy_dfi_p0_rddata[9] <= a7ddrphy_bitslip92[0];
- a7ddrphy_dfi_p0_rddata[25] <= a7ddrphy_bitslip92[1];
- a7ddrphy_dfi_p0_rddata[10] <= a7ddrphy_bitslip102[0];
- a7ddrphy_dfi_p0_rddata[26] <= a7ddrphy_bitslip102[1];
- a7ddrphy_dfi_p0_rddata[11] <= a7ddrphy_bitslip112[0];
- a7ddrphy_dfi_p0_rddata[27] <= a7ddrphy_bitslip112[1];
- a7ddrphy_dfi_p0_rddata[12] <= a7ddrphy_bitslip122[0];
- a7ddrphy_dfi_p0_rddata[28] <= a7ddrphy_bitslip122[1];
- a7ddrphy_dfi_p0_rddata[13] <= a7ddrphy_bitslip132[0];
- a7ddrphy_dfi_p0_rddata[29] <= a7ddrphy_bitslip132[1];
- a7ddrphy_dfi_p0_rddata[14] <= a7ddrphy_bitslip142[0];
- a7ddrphy_dfi_p0_rddata[30] <= a7ddrphy_bitslip142[1];
- a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip152[0];
- a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip152[1];
-end
-always @(*) begin
- a7ddrphy_dfi_p1_rddata <= 32'd0;
- a7ddrphy_dfi_p1_rddata[0] <= a7ddrphy_bitslip04[2];
- a7ddrphy_dfi_p1_rddata[16] <= a7ddrphy_bitslip04[3];
- a7ddrphy_dfi_p1_rddata[1] <= a7ddrphy_bitslip14[2];
- a7ddrphy_dfi_p1_rddata[17] <= a7ddrphy_bitslip14[3];
- a7ddrphy_dfi_p1_rddata[2] <= a7ddrphy_bitslip22[2];
- a7ddrphy_dfi_p1_rddata[18] <= a7ddrphy_bitslip22[3];
- a7ddrphy_dfi_p1_rddata[3] <= a7ddrphy_bitslip32[2];
- a7ddrphy_dfi_p1_rddata[19] <= a7ddrphy_bitslip32[3];
- a7ddrphy_dfi_p1_rddata[4] <= a7ddrphy_bitslip42[2];
- a7ddrphy_dfi_p1_rddata[20] <= a7ddrphy_bitslip42[3];
- a7ddrphy_dfi_p1_rddata[5] <= a7ddrphy_bitslip52[2];
- a7ddrphy_dfi_p1_rddata[21] <= a7ddrphy_bitslip52[3];
- a7ddrphy_dfi_p1_rddata[6] <= a7ddrphy_bitslip62[2];
- a7ddrphy_dfi_p1_rddata[22] <= a7ddrphy_bitslip62[3];
- a7ddrphy_dfi_p1_rddata[7] <= a7ddrphy_bitslip72[2];
- a7ddrphy_dfi_p1_rddata[23] <= a7ddrphy_bitslip72[3];
- a7ddrphy_dfi_p1_rddata[8] <= a7ddrphy_bitslip82[2];
- a7ddrphy_dfi_p1_rddata[24] <= a7ddrphy_bitslip82[3];
- a7ddrphy_dfi_p1_rddata[9] <= a7ddrphy_bitslip92[2];
- a7ddrphy_dfi_p1_rddata[25] <= a7ddrphy_bitslip92[3];
- a7ddrphy_dfi_p1_rddata[10] <= a7ddrphy_bitslip102[2];
- a7ddrphy_dfi_p1_rddata[26] <= a7ddrphy_bitslip102[3];
- a7ddrphy_dfi_p1_rddata[11] <= a7ddrphy_bitslip112[2];
- a7ddrphy_dfi_p1_rddata[27] <= a7ddrphy_bitslip112[3];
- a7ddrphy_dfi_p1_rddata[12] <= a7ddrphy_bitslip122[2];
- a7ddrphy_dfi_p1_rddata[28] <= a7ddrphy_bitslip122[3];
- a7ddrphy_dfi_p1_rddata[13] <= a7ddrphy_bitslip132[2];
- a7ddrphy_dfi_p1_rddata[29] <= a7ddrphy_bitslip132[3];
- a7ddrphy_dfi_p1_rddata[14] <= a7ddrphy_bitslip142[2];
- a7ddrphy_dfi_p1_rddata[30] <= a7ddrphy_bitslip142[3];
- a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip152[2];
- a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip152[3];
-end
-always @(*) begin
- a7ddrphy_dfi_p2_rddata <= 32'd0;
- a7ddrphy_dfi_p2_rddata[0] <= a7ddrphy_bitslip04[4];
- a7ddrphy_dfi_p2_rddata[16] <= a7ddrphy_bitslip04[5];
- a7ddrphy_dfi_p2_rddata[1] <= a7ddrphy_bitslip14[4];
- a7ddrphy_dfi_p2_rddata[17] <= a7ddrphy_bitslip14[5];
- a7ddrphy_dfi_p2_rddata[2] <= a7ddrphy_bitslip22[4];
- a7ddrphy_dfi_p2_rddata[18] <= a7ddrphy_bitslip22[5];
- a7ddrphy_dfi_p2_rddata[3] <= a7ddrphy_bitslip32[4];
- a7ddrphy_dfi_p2_rddata[19] <= a7ddrphy_bitslip32[5];
- a7ddrphy_dfi_p2_rddata[4] <= a7ddrphy_bitslip42[4];
- a7ddrphy_dfi_p2_rddata[20] <= a7ddrphy_bitslip42[5];
- a7ddrphy_dfi_p2_rddata[5] <= a7ddrphy_bitslip52[4];
- a7ddrphy_dfi_p2_rddata[21] <= a7ddrphy_bitslip52[5];
- a7ddrphy_dfi_p2_rddata[6] <= a7ddrphy_bitslip62[4];
- a7ddrphy_dfi_p2_rddata[22] <= a7ddrphy_bitslip62[5];
- a7ddrphy_dfi_p2_rddata[7] <= a7ddrphy_bitslip72[4];
- a7ddrphy_dfi_p2_rddata[23] <= a7ddrphy_bitslip72[5];
- a7ddrphy_dfi_p2_rddata[8] <= a7ddrphy_bitslip82[4];
- a7ddrphy_dfi_p2_rddata[24] <= a7ddrphy_bitslip82[5];
- a7ddrphy_dfi_p2_rddata[9] <= a7ddrphy_bitslip92[4];
- a7ddrphy_dfi_p2_rddata[25] <= a7ddrphy_bitslip92[5];
- a7ddrphy_dfi_p2_rddata[10] <= a7ddrphy_bitslip102[4];
- a7ddrphy_dfi_p2_rddata[26] <= a7ddrphy_bitslip102[5];
- a7ddrphy_dfi_p2_rddata[11] <= a7ddrphy_bitslip112[4];
- a7ddrphy_dfi_p2_rddata[27] <= a7ddrphy_bitslip112[5];
- a7ddrphy_dfi_p2_rddata[12] <= a7ddrphy_bitslip122[4];
- a7ddrphy_dfi_p2_rddata[28] <= a7ddrphy_bitslip122[5];
- a7ddrphy_dfi_p2_rddata[13] <= a7ddrphy_bitslip132[4];
- a7ddrphy_dfi_p2_rddata[29] <= a7ddrphy_bitslip132[5];
- a7ddrphy_dfi_p2_rddata[14] <= a7ddrphy_bitslip142[4];
- a7ddrphy_dfi_p2_rddata[30] <= a7ddrphy_bitslip142[5];
- a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip152[4];
- a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip152[5];
-end
-always @(*) begin
- a7ddrphy_dfi_p3_rddata <= 32'd0;
- a7ddrphy_dfi_p3_rddata[0] <= a7ddrphy_bitslip04[6];
- a7ddrphy_dfi_p3_rddata[16] <= a7ddrphy_bitslip04[7];
- a7ddrphy_dfi_p3_rddata[1] <= a7ddrphy_bitslip14[6];
- a7ddrphy_dfi_p3_rddata[17] <= a7ddrphy_bitslip14[7];
- a7ddrphy_dfi_p3_rddata[2] <= a7ddrphy_bitslip22[6];
- a7ddrphy_dfi_p3_rddata[18] <= a7ddrphy_bitslip22[7];
- a7ddrphy_dfi_p3_rddata[3] <= a7ddrphy_bitslip32[6];
- a7ddrphy_dfi_p3_rddata[19] <= a7ddrphy_bitslip32[7];
- a7ddrphy_dfi_p3_rddata[4] <= a7ddrphy_bitslip42[6];
- a7ddrphy_dfi_p3_rddata[20] <= a7ddrphy_bitslip42[7];
- a7ddrphy_dfi_p3_rddata[5] <= a7ddrphy_bitslip52[6];
- a7ddrphy_dfi_p3_rddata[21] <= a7ddrphy_bitslip52[7];
- a7ddrphy_dfi_p3_rddata[6] <= a7ddrphy_bitslip62[6];
- a7ddrphy_dfi_p3_rddata[22] <= a7ddrphy_bitslip62[7];
- a7ddrphy_dfi_p3_rddata[7] <= a7ddrphy_bitslip72[6];
- a7ddrphy_dfi_p3_rddata[23] <= a7ddrphy_bitslip72[7];
- a7ddrphy_dfi_p3_rddata[8] <= a7ddrphy_bitslip82[6];
- a7ddrphy_dfi_p3_rddata[24] <= a7ddrphy_bitslip82[7];
- a7ddrphy_dfi_p3_rddata[9] <= a7ddrphy_bitslip92[6];
- a7ddrphy_dfi_p3_rddata[25] <= a7ddrphy_bitslip92[7];
- a7ddrphy_dfi_p3_rddata[10] <= a7ddrphy_bitslip102[6];
- a7ddrphy_dfi_p3_rddata[26] <= a7ddrphy_bitslip102[7];
- a7ddrphy_dfi_p3_rddata[11] <= a7ddrphy_bitslip112[6];
- a7ddrphy_dfi_p3_rddata[27] <= a7ddrphy_bitslip112[7];
- a7ddrphy_dfi_p3_rddata[12] <= a7ddrphy_bitslip122[6];
- a7ddrphy_dfi_p3_rddata[28] <= a7ddrphy_bitslip122[7];
- a7ddrphy_dfi_p3_rddata[13] <= a7ddrphy_bitslip132[6];
- a7ddrphy_dfi_p3_rddata[29] <= a7ddrphy_bitslip132[7];
- a7ddrphy_dfi_p3_rddata[14] <= a7ddrphy_bitslip142[6];
- a7ddrphy_dfi_p3_rddata[30] <= a7ddrphy_bitslip142[7];
- a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip152[6];
- a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip152[7];
+ a7ddrphy_dfi_p0_rddata <= 32'd0;
+ a7ddrphy_dfi_p0_rddata[0] <= a7ddrphy_bitslip04[0];
+ a7ddrphy_dfi_p0_rddata[16] <= a7ddrphy_bitslip04[1];
+ a7ddrphy_dfi_p0_rddata[1] <= a7ddrphy_bitslip14[0];
+ a7ddrphy_dfi_p0_rddata[17] <= a7ddrphy_bitslip14[1];
+ a7ddrphy_dfi_p0_rddata[2] <= a7ddrphy_bitslip22[0];
+ a7ddrphy_dfi_p0_rddata[18] <= a7ddrphy_bitslip22[1];
+ a7ddrphy_dfi_p0_rddata[3] <= a7ddrphy_bitslip32[0];
+ a7ddrphy_dfi_p0_rddata[19] <= a7ddrphy_bitslip32[1];
+ a7ddrphy_dfi_p0_rddata[4] <= a7ddrphy_bitslip42[0];
+ a7ddrphy_dfi_p0_rddata[20] <= a7ddrphy_bitslip42[1];
+ a7ddrphy_dfi_p0_rddata[5] <= a7ddrphy_bitslip52[0];
+ a7ddrphy_dfi_p0_rddata[21] <= a7ddrphy_bitslip52[1];
+ a7ddrphy_dfi_p0_rddata[6] <= a7ddrphy_bitslip62[0];
+ a7ddrphy_dfi_p0_rddata[22] <= a7ddrphy_bitslip62[1];
+ a7ddrphy_dfi_p0_rddata[7] <= a7ddrphy_bitslip72[0];
+ a7ddrphy_dfi_p0_rddata[23] <= a7ddrphy_bitslip72[1];
+ a7ddrphy_dfi_p0_rddata[8] <= a7ddrphy_bitslip82[0];
+ a7ddrphy_dfi_p0_rddata[24] <= a7ddrphy_bitslip82[1];
+ a7ddrphy_dfi_p0_rddata[9] <= a7ddrphy_bitslip92[0];
+ a7ddrphy_dfi_p0_rddata[25] <= a7ddrphy_bitslip92[1];
+ a7ddrphy_dfi_p0_rddata[10] <= a7ddrphy_bitslip102[0];
+ a7ddrphy_dfi_p0_rddata[26] <= a7ddrphy_bitslip102[1];
+ a7ddrphy_dfi_p0_rddata[11] <= a7ddrphy_bitslip112[0];
+ a7ddrphy_dfi_p0_rddata[27] <= a7ddrphy_bitslip112[1];
+ a7ddrphy_dfi_p0_rddata[12] <= a7ddrphy_bitslip122[0];
+ a7ddrphy_dfi_p0_rddata[28] <= a7ddrphy_bitslip122[1];
+ a7ddrphy_dfi_p0_rddata[13] <= a7ddrphy_bitslip132[0];
+ a7ddrphy_dfi_p0_rddata[29] <= a7ddrphy_bitslip132[1];
+ a7ddrphy_dfi_p0_rddata[14] <= a7ddrphy_bitslip142[0];
+ a7ddrphy_dfi_p0_rddata[30] <= a7ddrphy_bitslip142[1];
+ a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip152[0];
+ a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip152[1];
+end
+always @(*) begin
+ a7ddrphy_dfi_p1_rddata <= 32'd0;
+ a7ddrphy_dfi_p1_rddata[0] <= a7ddrphy_bitslip04[2];
+ a7ddrphy_dfi_p1_rddata[16] <= a7ddrphy_bitslip04[3];
+ a7ddrphy_dfi_p1_rddata[1] <= a7ddrphy_bitslip14[2];
+ a7ddrphy_dfi_p1_rddata[17] <= a7ddrphy_bitslip14[3];
+ a7ddrphy_dfi_p1_rddata[2] <= a7ddrphy_bitslip22[2];
+ a7ddrphy_dfi_p1_rddata[18] <= a7ddrphy_bitslip22[3];
+ a7ddrphy_dfi_p1_rddata[3] <= a7ddrphy_bitslip32[2];
+ a7ddrphy_dfi_p1_rddata[19] <= a7ddrphy_bitslip32[3];
+ a7ddrphy_dfi_p1_rddata[4] <= a7ddrphy_bitslip42[2];
+ a7ddrphy_dfi_p1_rddata[20] <= a7ddrphy_bitslip42[3];
+ a7ddrphy_dfi_p1_rddata[5] <= a7ddrphy_bitslip52[2];
+ a7ddrphy_dfi_p1_rddata[21] <= a7ddrphy_bitslip52[3];
+ a7ddrphy_dfi_p1_rddata[6] <= a7ddrphy_bitslip62[2];
+ a7ddrphy_dfi_p1_rddata[22] <= a7ddrphy_bitslip62[3];
+ a7ddrphy_dfi_p1_rddata[7] <= a7ddrphy_bitslip72[2];
+ a7ddrphy_dfi_p1_rddata[23] <= a7ddrphy_bitslip72[3];
+ a7ddrphy_dfi_p1_rddata[8] <= a7ddrphy_bitslip82[2];
+ a7ddrphy_dfi_p1_rddata[24] <= a7ddrphy_bitslip82[3];
+ a7ddrphy_dfi_p1_rddata[9] <= a7ddrphy_bitslip92[2];
+ a7ddrphy_dfi_p1_rddata[25] <= a7ddrphy_bitslip92[3];
+ a7ddrphy_dfi_p1_rddata[10] <= a7ddrphy_bitslip102[2];
+ a7ddrphy_dfi_p1_rddata[26] <= a7ddrphy_bitslip102[3];
+ a7ddrphy_dfi_p1_rddata[11] <= a7ddrphy_bitslip112[2];
+ a7ddrphy_dfi_p1_rddata[27] <= a7ddrphy_bitslip112[3];
+ a7ddrphy_dfi_p1_rddata[12] <= a7ddrphy_bitslip122[2];
+ a7ddrphy_dfi_p1_rddata[28] <= a7ddrphy_bitslip122[3];
+ a7ddrphy_dfi_p1_rddata[13] <= a7ddrphy_bitslip132[2];
+ a7ddrphy_dfi_p1_rddata[29] <= a7ddrphy_bitslip132[3];
+ a7ddrphy_dfi_p1_rddata[14] <= a7ddrphy_bitslip142[2];
+ a7ddrphy_dfi_p1_rddata[30] <= a7ddrphy_bitslip142[3];
+ a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip152[2];
+ a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip152[3];
+end
+always @(*) begin
+ a7ddrphy_dfi_p2_rddata <= 32'd0;
+ a7ddrphy_dfi_p2_rddata[0] <= a7ddrphy_bitslip04[4];
+ a7ddrphy_dfi_p2_rddata[16] <= a7ddrphy_bitslip04[5];
+ a7ddrphy_dfi_p2_rddata[1] <= a7ddrphy_bitslip14[4];
+ a7ddrphy_dfi_p2_rddata[17] <= a7ddrphy_bitslip14[5];
+ a7ddrphy_dfi_p2_rddata[2] <= a7ddrphy_bitslip22[4];
+ a7ddrphy_dfi_p2_rddata[18] <= a7ddrphy_bitslip22[5];
+ a7ddrphy_dfi_p2_rddata[3] <= a7ddrphy_bitslip32[4];
+ a7ddrphy_dfi_p2_rddata[19] <= a7ddrphy_bitslip32[5];
+ a7ddrphy_dfi_p2_rddata[4] <= a7ddrphy_bitslip42[4];
+ a7ddrphy_dfi_p2_rddata[20] <= a7ddrphy_bitslip42[5];
+ a7ddrphy_dfi_p2_rddata[5] <= a7ddrphy_bitslip52[4];
+ a7ddrphy_dfi_p2_rddata[21] <= a7ddrphy_bitslip52[5];
+ a7ddrphy_dfi_p2_rddata[6] <= a7ddrphy_bitslip62[4];
+ a7ddrphy_dfi_p2_rddata[22] <= a7ddrphy_bitslip62[5];
+ a7ddrphy_dfi_p2_rddata[7] <= a7ddrphy_bitslip72[4];
+ a7ddrphy_dfi_p2_rddata[23] <= a7ddrphy_bitslip72[5];
+ a7ddrphy_dfi_p2_rddata[8] <= a7ddrphy_bitslip82[4];
+ a7ddrphy_dfi_p2_rddata[24] <= a7ddrphy_bitslip82[5];
+ a7ddrphy_dfi_p2_rddata[9] <= a7ddrphy_bitslip92[4];
+ a7ddrphy_dfi_p2_rddata[25] <= a7ddrphy_bitslip92[5];
+ a7ddrphy_dfi_p2_rddata[10] <= a7ddrphy_bitslip102[4];
+ a7ddrphy_dfi_p2_rddata[26] <= a7ddrphy_bitslip102[5];
+ a7ddrphy_dfi_p2_rddata[11] <= a7ddrphy_bitslip112[4];
+ a7ddrphy_dfi_p2_rddata[27] <= a7ddrphy_bitslip112[5];
+ a7ddrphy_dfi_p2_rddata[12] <= a7ddrphy_bitslip122[4];
+ a7ddrphy_dfi_p2_rddata[28] <= a7ddrphy_bitslip122[5];
+ a7ddrphy_dfi_p2_rddata[13] <= a7ddrphy_bitslip132[4];
+ a7ddrphy_dfi_p2_rddata[29] <= a7ddrphy_bitslip132[5];
+ a7ddrphy_dfi_p2_rddata[14] <= a7ddrphy_bitslip142[4];
+ a7ddrphy_dfi_p2_rddata[30] <= a7ddrphy_bitslip142[5];
+ a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip152[4];
+ a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip152[5];
+end
+always @(*) begin
+ a7ddrphy_dfi_p3_rddata <= 32'd0;
+ a7ddrphy_dfi_p3_rddata[0] <= a7ddrphy_bitslip04[6];
+ a7ddrphy_dfi_p3_rddata[16] <= a7ddrphy_bitslip04[7];
+ a7ddrphy_dfi_p3_rddata[1] <= a7ddrphy_bitslip14[6];
+ a7ddrphy_dfi_p3_rddata[17] <= a7ddrphy_bitslip14[7];
+ a7ddrphy_dfi_p3_rddata[2] <= a7ddrphy_bitslip22[6];
+ a7ddrphy_dfi_p3_rddata[18] <= a7ddrphy_bitslip22[7];
+ a7ddrphy_dfi_p3_rddata[3] <= a7ddrphy_bitslip32[6];
+ a7ddrphy_dfi_p3_rddata[19] <= a7ddrphy_bitslip32[7];
+ a7ddrphy_dfi_p3_rddata[4] <= a7ddrphy_bitslip42[6];
+ a7ddrphy_dfi_p3_rddata[20] <= a7ddrphy_bitslip42[7];
+ a7ddrphy_dfi_p3_rddata[5] <= a7ddrphy_bitslip52[6];
+ a7ddrphy_dfi_p3_rddata[21] <= a7ddrphy_bitslip52[7];
+ a7ddrphy_dfi_p3_rddata[6] <= a7ddrphy_bitslip62[6];
+ a7ddrphy_dfi_p3_rddata[22] <= a7ddrphy_bitslip62[7];
+ a7ddrphy_dfi_p3_rddata[7] <= a7ddrphy_bitslip72[6];
+ a7ddrphy_dfi_p3_rddata[23] <= a7ddrphy_bitslip72[7];
+ a7ddrphy_dfi_p3_rddata[8] <= a7ddrphy_bitslip82[6];
+ a7ddrphy_dfi_p3_rddata[24] <= a7ddrphy_bitslip82[7];
+ a7ddrphy_dfi_p3_rddata[9] <= a7ddrphy_bitslip92[6];
+ a7ddrphy_dfi_p3_rddata[25] <= a7ddrphy_bitslip92[7];
+ a7ddrphy_dfi_p3_rddata[10] <= a7ddrphy_bitslip102[6];
+ a7ddrphy_dfi_p3_rddata[26] <= a7ddrphy_bitslip102[7];
+ a7ddrphy_dfi_p3_rddata[11] <= a7ddrphy_bitslip112[6];
+ a7ddrphy_dfi_p3_rddata[27] <= a7ddrphy_bitslip112[7];
+ a7ddrphy_dfi_p3_rddata[12] <= a7ddrphy_bitslip122[6];
+ a7ddrphy_dfi_p3_rddata[28] <= a7ddrphy_bitslip122[7];
+ a7ddrphy_dfi_p3_rddata[13] <= a7ddrphy_bitslip132[6];
+ a7ddrphy_dfi_p3_rddata[29] <= a7ddrphy_bitslip132[7];
+ a7ddrphy_dfi_p3_rddata[14] <= a7ddrphy_bitslip142[6];
+ a7ddrphy_dfi_p3_rddata[30] <= a7ddrphy_bitslip142[7];
+ a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip152[6];
+ a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip152[7];
end
assign a7ddrphy_dfi_p0_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage);
assign a7ddrphy_dfi_p1_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage);
assign a7ddrphy_dfi_p3_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage);
assign a7ddrphy_dq_oe = a7ddrphy_wrdata_en_tappeddelayline1;
always @(*) begin
- a7ddrphy_dqs_oe <= 1'd0;
- if (a7ddrphy_wlevel_en_storage) begin
- a7ddrphy_dqs_oe <= 1'd1;
- end else begin
- a7ddrphy_dqs_oe <= a7ddrphy_dq_oe;
- end
+ a7ddrphy_dqs_oe <= 1'd0;
+ if (a7ddrphy_wlevel_en_storage) begin
+ a7ddrphy_dqs_oe <= 1'd1;
+ end else begin
+ a7ddrphy_dqs_oe <= a7ddrphy_dq_oe;
+ end
end
assign a7ddrphy_dqs_preamble = (a7ddrphy_wrdata_en_tappeddelayline0 & (~a7ddrphy_wrdata_en_tappeddelayline1));
assign a7ddrphy_dqs_postamble = (a7ddrphy_wrdata_en_tappeddelayline2 & (~a7ddrphy_wrdata_en_tappeddelayline1));
always @(*) begin
- a7ddrphy_dqspattern_o0 <= 8'd0;
- a7ddrphy_dqspattern_o0 <= 7'd85;
- if (a7ddrphy_dqspattern0) begin
- a7ddrphy_dqspattern_o0 <= 5'd21;
- end
- if (a7ddrphy_dqspattern1) begin
- a7ddrphy_dqspattern_o0 <= 7'd84;
- end
- if (a7ddrphy_wlevel_en_storage) begin
- a7ddrphy_dqspattern_o0 <= 1'd0;
- if (a7ddrphy_wlevel_strobe_re) begin
- a7ddrphy_dqspattern_o0 <= 1'd1;
- end
- end
-end
-always @(*) begin
- a7ddrphy_bitslip00 <= 8'd0;
- case (a7ddrphy_bitslip0_value0)
- 1'd0: begin
- a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip10 <= 8'd0;
- case (a7ddrphy_bitslip1_value0)
- 1'd0: begin
- a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip01 <= 8'd0;
- case (a7ddrphy_bitslip0_value1)
- 1'd0: begin
- a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip11 <= 8'd0;
- case (a7ddrphy_bitslip1_value1)
- 1'd0: begin
- a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip02 <= 8'd0;
- case (a7ddrphy_bitslip0_value2)
- 1'd0: begin
- a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip04 <= 8'd0;
- case (a7ddrphy_bitslip0_value3)
- 1'd0: begin
- a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip12 <= 8'd0;
- case (a7ddrphy_bitslip1_value2)
- 1'd0: begin
- a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip14 <= 8'd0;
- case (a7ddrphy_bitslip1_value3)
- 1'd0: begin
- a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip20 <= 8'd0;
- case (a7ddrphy_bitslip2_value0)
- 1'd0: begin
- a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip22 <= 8'd0;
- case (a7ddrphy_bitslip2_value1)
- 1'd0: begin
- a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip30 <= 8'd0;
- case (a7ddrphy_bitslip3_value0)
- 1'd0: begin
- a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip32 <= 8'd0;
- case (a7ddrphy_bitslip3_value1)
- 1'd0: begin
- a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip40 <= 8'd0;
- case (a7ddrphy_bitslip4_value0)
- 1'd0: begin
- a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip42 <= 8'd0;
- case (a7ddrphy_bitslip4_value1)
- 1'd0: begin
- a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip50 <= 8'd0;
- case (a7ddrphy_bitslip5_value0)
- 1'd0: begin
- a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip52 <= 8'd0;
- case (a7ddrphy_bitslip5_value1)
- 1'd0: begin
- a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip60 <= 8'd0;
- case (a7ddrphy_bitslip6_value0)
- 1'd0: begin
- a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip62 <= 8'd0;
- case (a7ddrphy_bitslip6_value1)
- 1'd0: begin
- a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip70 <= 8'd0;
- case (a7ddrphy_bitslip7_value0)
- 1'd0: begin
- a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip72 <= 8'd0;
- case (a7ddrphy_bitslip7_value1)
- 1'd0: begin
- a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip80 <= 8'd0;
- case (a7ddrphy_bitslip8_value0)
- 1'd0: begin
- a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip82 <= 8'd0;
- case (a7ddrphy_bitslip8_value1)
- 1'd0: begin
- a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip90 <= 8'd0;
- case (a7ddrphy_bitslip9_value0)
- 1'd0: begin
- a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip92 <= 8'd0;
- case (a7ddrphy_bitslip9_value1)
- 1'd0: begin
- a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip100 <= 8'd0;
- case (a7ddrphy_bitslip10_value0)
- 1'd0: begin
- a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip102 <= 8'd0;
- case (a7ddrphy_bitslip10_value1)
- 1'd0: begin
- a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip110 <= 8'd0;
- case (a7ddrphy_bitslip11_value0)
- 1'd0: begin
- a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip112 <= 8'd0;
- case (a7ddrphy_bitslip11_value1)
- 1'd0: begin
- a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip120 <= 8'd0;
- case (a7ddrphy_bitslip12_value0)
- 1'd0: begin
- a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip122 <= 8'd0;
- case (a7ddrphy_bitslip12_value1)
- 1'd0: begin
- a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip130 <= 8'd0;
- case (a7ddrphy_bitslip13_value0)
- 1'd0: begin
- a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip132 <= 8'd0;
- case (a7ddrphy_bitslip13_value1)
- 1'd0: begin
- a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip140 <= 8'd0;
- case (a7ddrphy_bitslip14_value0)
- 1'd0: begin
- a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip142 <= 8'd0;
- case (a7ddrphy_bitslip14_value1)
- 1'd0: begin
- a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip150 <= 8'd0;
- case (a7ddrphy_bitslip15_value0)
- 1'd0: begin
- a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip152 <= 8'd0;
- case (a7ddrphy_bitslip15_value1)
- 1'd0: begin
- a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[15:8];
- end
- endcase
+ a7ddrphy_dqspattern_o0 <= 8'd0;
+ a7ddrphy_dqspattern_o0 <= 7'd85;
+ if (a7ddrphy_dqspattern0) begin
+ a7ddrphy_dqspattern_o0 <= 5'd21;
+ end
+ if (a7ddrphy_dqspattern1) begin
+ a7ddrphy_dqspattern_o0 <= 7'd84;
+ end
+ if (a7ddrphy_wlevel_en_storage) begin
+ a7ddrphy_dqspattern_o0 <= 1'd0;
+ if (a7ddrphy_wlevel_strobe_re) begin
+ a7ddrphy_dqspattern_o0 <= 1'd1;
+ end
+ end
+end
+always @(*) begin
+ a7ddrphy_bitslip00 <= 8'd0;
+ case (a7ddrphy_bitslip0_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip10 <= 8'd0;
+ case (a7ddrphy_bitslip1_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip01 <= 8'd0;
+ case (a7ddrphy_bitslip0_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip11 <= 8'd0;
+ case (a7ddrphy_bitslip1_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip02 <= 8'd0;
+ case (a7ddrphy_bitslip0_value2)
+ 1'd0: begin
+ a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip04 <= 8'd0;
+ case (a7ddrphy_bitslip0_value3)
+ 1'd0: begin
+ a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip12 <= 8'd0;
+ case (a7ddrphy_bitslip1_value2)
+ 1'd0: begin
+ a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip14 <= 8'd0;
+ case (a7ddrphy_bitslip1_value3)
+ 1'd0: begin
+ a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip20 <= 8'd0;
+ case (a7ddrphy_bitslip2_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip22 <= 8'd0;
+ case (a7ddrphy_bitslip2_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip30 <= 8'd0;
+ case (a7ddrphy_bitslip3_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip32 <= 8'd0;
+ case (a7ddrphy_bitslip3_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip40 <= 8'd0;
+ case (a7ddrphy_bitslip4_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip42 <= 8'd0;
+ case (a7ddrphy_bitslip4_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip50 <= 8'd0;
+ case (a7ddrphy_bitslip5_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip52 <= 8'd0;
+ case (a7ddrphy_bitslip5_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip60 <= 8'd0;
+ case (a7ddrphy_bitslip6_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip62 <= 8'd0;
+ case (a7ddrphy_bitslip6_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip70 <= 8'd0;
+ case (a7ddrphy_bitslip7_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip72 <= 8'd0;
+ case (a7ddrphy_bitslip7_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip80 <= 8'd0;
+ case (a7ddrphy_bitslip8_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip82 <= 8'd0;
+ case (a7ddrphy_bitslip8_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip90 <= 8'd0;
+ case (a7ddrphy_bitslip9_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip92 <= 8'd0;
+ case (a7ddrphy_bitslip9_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip100 <= 8'd0;
+ case (a7ddrphy_bitslip10_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip102 <= 8'd0;
+ case (a7ddrphy_bitslip10_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip110 <= 8'd0;
+ case (a7ddrphy_bitslip11_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip112 <= 8'd0;
+ case (a7ddrphy_bitslip11_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip120 <= 8'd0;
+ case (a7ddrphy_bitslip12_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip122 <= 8'd0;
+ case (a7ddrphy_bitslip12_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip130 <= 8'd0;
+ case (a7ddrphy_bitslip13_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip132 <= 8'd0;
+ case (a7ddrphy_bitslip13_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip140 <= 8'd0;
+ case (a7ddrphy_bitslip14_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip142 <= 8'd0;
+ case (a7ddrphy_bitslip14_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip150 <= 8'd0;
+ case (a7ddrphy_bitslip15_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip152 <= 8'd0;
+ case (a7ddrphy_bitslip15_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[15:8];
+ end
+ endcase
end
assign a7ddrphy_dfi_p0_address = litedramcore_master_p0_address;
assign a7ddrphy_dfi_p0_bank = litedramcore_master_p0_bank;
assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata;
assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid;
always @(*) begin
- litedramcore_csr_dfi_p0_rddata <= 32'd0;
- if (litedramcore_sel) begin
- end else begin
- litedramcore_csr_dfi_p0_rddata <= litedramcore_master_p0_rddata;
- end
+ litedramcore_csr_dfi_p0_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_csr_dfi_p0_rddata <= litedramcore_master_p0_rddata;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p0_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- end else begin
- litedramcore_csr_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
- end
-end
-always @(*) begin
- litedramcore_csr_dfi_p1_rddata <= 32'd0;
- if (litedramcore_sel) begin
- end else begin
- litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata;
- end
-end
-always @(*) begin
- litedramcore_csr_dfi_p1_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- end else begin
- litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
- end
-end
-always @(*) begin
- litedramcore_csr_dfi_p2_rddata <= 32'd0;
- if (litedramcore_sel) begin
- end else begin
- litedramcore_csr_dfi_p2_rddata <= litedramcore_master_p2_rddata;
- end
-end
-always @(*) begin
- litedramcore_csr_dfi_p2_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- end else begin
- litedramcore_csr_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
- end
-end
-always @(*) begin
- litedramcore_csr_dfi_p3_rddata <= 32'd0;
- if (litedramcore_sel) begin
- end else begin
- litedramcore_csr_dfi_p3_rddata <= litedramcore_master_p3_rddata;
- end
-end
-always @(*) begin
- litedramcore_csr_dfi_p3_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- end else begin
- litedramcore_csr_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
- end
-end
-always @(*) begin
- litedramcore_ext_dfi_p0_rddata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_ext_dfi_p0_rddata <= litedramcore_master_p0_rddata;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_ext_dfi_p0_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_ext_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_ext_dfi_p1_rddata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_ext_dfi_p1_rddata <= litedramcore_master_p1_rddata;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_ext_dfi_p1_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_ext_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_ext_dfi_p2_rddata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_ext_dfi_p2_rddata <= litedramcore_master_p2_rddata;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_ext_dfi_p2_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_ext_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_slave_p0_rddata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- end else begin
- litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata;
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_slave_p0_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- end else begin
- litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_ext_dfi_p3_rddata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_ext_dfi_p3_rddata <= litedramcore_master_p3_rddata;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_ext_dfi_p3_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_ext_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_slave_p1_rddata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- end else begin
- litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata;
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_slave_p1_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- end else begin
- litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_slave_p2_rddata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- end else begin
- litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata;
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_slave_p2_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- end else begin
- litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_slave_p3_rddata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- end else begin
- litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata;
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_slave_p3_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- end else begin
- litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_master_p0_address <= 14'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_address <= litedramcore_ext_dfi_p0_address;
- end else begin
- litedramcore_master_p0_address <= litedramcore_slave_p0_address;
- end
- end else begin
- litedramcore_master_p0_address <= litedramcore_csr_dfi_p0_address;
- end
-end
-always @(*) begin
- litedramcore_master_p0_bank <= 3'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_bank <= litedramcore_ext_dfi_p0_bank;
- end else begin
- litedramcore_master_p0_bank <= litedramcore_slave_p0_bank;
- end
- end else begin
- litedramcore_master_p0_bank <= litedramcore_csr_dfi_p0_bank;
- end
-end
-always @(*) begin
- litedramcore_master_p0_cas_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_cas_n <= litedramcore_ext_dfi_p0_cas_n;
- end else begin
- litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n;
- end
- end else begin
- litedramcore_master_p0_cas_n <= litedramcore_csr_dfi_p0_cas_n;
- end
-end
-always @(*) begin
- litedramcore_master_p0_cs_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n;
- end else begin
- litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n;
- end
- end else begin
- litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n;
- end
-end
-always @(*) begin
- litedramcore_master_p0_ras_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n;
- end else begin
- litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n;
- end
- end else begin
- litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n;
- end
-end
-always @(*) begin
- litedramcore_master_p0_we_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n;
- end else begin
- litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n;
- end
- end else begin
- litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n;
- end
-end
-always @(*) begin
- litedramcore_master_p0_cke <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_cke <= litedramcore_ext_dfi_p0_cke;
- end else begin
- litedramcore_master_p0_cke <= litedramcore_slave_p0_cke;
- end
- end else begin
- litedramcore_master_p0_cke <= litedramcore_csr_dfi_p0_cke;
- end
-end
-always @(*) begin
- litedramcore_master_p0_odt <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_odt <= litedramcore_ext_dfi_p0_odt;
- end else begin
- litedramcore_master_p0_odt <= litedramcore_slave_p0_odt;
- end
- end else begin
- litedramcore_master_p0_odt <= litedramcore_csr_dfi_p0_odt;
- end
-end
-always @(*) begin
- litedramcore_master_p0_reset_n <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_reset_n <= litedramcore_ext_dfi_p0_reset_n;
- end else begin
- litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n;
- end
- end else begin
- litedramcore_master_p0_reset_n <= litedramcore_csr_dfi_p0_reset_n;
- end
-end
-always @(*) begin
- litedramcore_master_p0_act_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_act_n <= litedramcore_ext_dfi_p0_act_n;
- end else begin
- litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n;
- end
- end else begin
- litedramcore_master_p0_act_n <= litedramcore_csr_dfi_p0_act_n;
- end
-end
-always @(*) begin
- litedramcore_master_p0_wrdata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_wrdata <= litedramcore_ext_dfi_p0_wrdata;
- end else begin
- litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata;
- end
- end else begin
- litedramcore_master_p0_wrdata <= litedramcore_csr_dfi_p0_wrdata;
- end
-end
-always @(*) begin
- litedramcore_master_p0_wrdata_en <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_wrdata_en <= litedramcore_ext_dfi_p0_wrdata_en;
- end else begin
- litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en;
- end
- end else begin
- litedramcore_master_p0_wrdata_en <= litedramcore_csr_dfi_p0_wrdata_en;
- end
-end
-always @(*) begin
- litedramcore_master_p0_wrdata_mask <= 4'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_wrdata_mask <= litedramcore_ext_dfi_p0_wrdata_mask;
- end else begin
- litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask;
- end
- end else begin
- litedramcore_master_p0_wrdata_mask <= litedramcore_csr_dfi_p0_wrdata_mask;
- end
-end
-always @(*) begin
- litedramcore_master_p0_rddata_en <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_rddata_en <= litedramcore_ext_dfi_p0_rddata_en;
- end else begin
- litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en;
- end
- end else begin
- litedramcore_master_p0_rddata_en <= litedramcore_csr_dfi_p0_rddata_en;
- end
-end
-always @(*) begin
- litedramcore_master_p1_address <= 14'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_address <= litedramcore_ext_dfi_p1_address;
- end else begin
- litedramcore_master_p1_address <= litedramcore_slave_p1_address;
- end
- end else begin
- litedramcore_master_p1_address <= litedramcore_csr_dfi_p1_address;
- end
-end
-always @(*) begin
- litedramcore_master_p1_bank <= 3'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_bank <= litedramcore_ext_dfi_p1_bank;
- end else begin
- litedramcore_master_p1_bank <= litedramcore_slave_p1_bank;
- end
- end else begin
- litedramcore_master_p1_bank <= litedramcore_csr_dfi_p1_bank;
- end
-end
-always @(*) begin
- litedramcore_master_p1_cas_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_cas_n <= litedramcore_ext_dfi_p1_cas_n;
- end else begin
- litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n;
- end
- end else begin
- litedramcore_master_p1_cas_n <= litedramcore_csr_dfi_p1_cas_n;
- end
-end
-always @(*) begin
- litedramcore_master_p1_cs_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_cs_n <= litedramcore_ext_dfi_p1_cs_n;
- end else begin
- litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n;
- end
- end else begin
- litedramcore_master_p1_cs_n <= litedramcore_csr_dfi_p1_cs_n;
- end
-end
-always @(*) begin
- litedramcore_master_p1_ras_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_ras_n <= litedramcore_ext_dfi_p1_ras_n;
- end else begin
- litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n;
- end
- end else begin
- litedramcore_master_p1_ras_n <= litedramcore_csr_dfi_p1_ras_n;
- end
-end
-always @(*) begin
- litedramcore_master_p1_we_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_we_n <= litedramcore_ext_dfi_p1_we_n;
- end else begin
- litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n;
- end
- end else begin
- litedramcore_master_p1_we_n <= litedramcore_csr_dfi_p1_we_n;
- end
-end
-always @(*) begin
- litedramcore_master_p1_cke <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_cke <= litedramcore_ext_dfi_p1_cke;
- end else begin
- litedramcore_master_p1_cke <= litedramcore_slave_p1_cke;
- end
- end else begin
- litedramcore_master_p1_cke <= litedramcore_csr_dfi_p1_cke;
- end
-end
-always @(*) begin
- litedramcore_master_p1_odt <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_odt <= litedramcore_ext_dfi_p1_odt;
- end else begin
- litedramcore_master_p1_odt <= litedramcore_slave_p1_odt;
- end
- end else begin
- litedramcore_master_p1_odt <= litedramcore_csr_dfi_p1_odt;
- end
-end
-always @(*) begin
- litedramcore_master_p1_reset_n <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_reset_n <= litedramcore_ext_dfi_p1_reset_n;
- end else begin
- litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n;
- end
- end else begin
- litedramcore_master_p1_reset_n <= litedramcore_csr_dfi_p1_reset_n;
- end
-end
-always @(*) begin
- litedramcore_master_p1_act_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_act_n <= litedramcore_ext_dfi_p1_act_n;
- end else begin
- litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n;
- end
- end else begin
- litedramcore_master_p1_act_n <= litedramcore_csr_dfi_p1_act_n;
- end
-end
-always @(*) begin
- litedramcore_master_p1_wrdata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_wrdata <= litedramcore_ext_dfi_p1_wrdata;
- end else begin
- litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata;
- end
- end else begin
- litedramcore_master_p1_wrdata <= litedramcore_csr_dfi_p1_wrdata;
- end
-end
-always @(*) begin
- litedramcore_master_p1_wrdata_en <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_wrdata_en <= litedramcore_ext_dfi_p1_wrdata_en;
- end else begin
- litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en;
- end
- end else begin
- litedramcore_master_p1_wrdata_en <= litedramcore_csr_dfi_p1_wrdata_en;
- end
-end
-always @(*) begin
- litedramcore_master_p1_wrdata_mask <= 4'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_wrdata_mask <= litedramcore_ext_dfi_p1_wrdata_mask;
- end else begin
- litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask;
- end
- end else begin
- litedramcore_master_p1_wrdata_mask <= litedramcore_csr_dfi_p1_wrdata_mask;
- end
-end
-always @(*) begin
- litedramcore_master_p1_rddata_en <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_rddata_en <= litedramcore_ext_dfi_p1_rddata_en;
- end else begin
- litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en;
- end
- end else begin
- litedramcore_master_p1_rddata_en <= litedramcore_csr_dfi_p1_rddata_en;
- end
-end
-always @(*) begin
- litedramcore_master_p2_address <= 14'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_address <= litedramcore_ext_dfi_p2_address;
- end else begin
- litedramcore_master_p2_address <= litedramcore_slave_p2_address;
- end
- end else begin
- litedramcore_master_p2_address <= litedramcore_csr_dfi_p2_address;
- end
-end
-always @(*) begin
- litedramcore_master_p2_bank <= 3'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_bank <= litedramcore_ext_dfi_p2_bank;
- end else begin
- litedramcore_master_p2_bank <= litedramcore_slave_p2_bank;
- end
- end else begin
- litedramcore_master_p2_bank <= litedramcore_csr_dfi_p2_bank;
- end
-end
-always @(*) begin
- litedramcore_master_p2_cas_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_cas_n <= litedramcore_ext_dfi_p2_cas_n;
- end else begin
- litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n;
- end
- end else begin
- litedramcore_master_p2_cas_n <= litedramcore_csr_dfi_p2_cas_n;
- end
-end
-always @(*) begin
- litedramcore_master_p2_cs_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_cs_n <= litedramcore_ext_dfi_p2_cs_n;
- end else begin
- litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n;
- end
- end else begin
- litedramcore_master_p2_cs_n <= litedramcore_csr_dfi_p2_cs_n;
- end
-end
-always @(*) begin
- litedramcore_master_p2_ras_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_ras_n <= litedramcore_ext_dfi_p2_ras_n;
- end else begin
- litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n;
- end
- end else begin
- litedramcore_master_p2_ras_n <= litedramcore_csr_dfi_p2_ras_n;
- end
-end
-always @(*) begin
- litedramcore_master_p2_we_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_we_n <= litedramcore_ext_dfi_p2_we_n;
- end else begin
- litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n;
- end
- end else begin
- litedramcore_master_p2_we_n <= litedramcore_csr_dfi_p2_we_n;
- end
-end
-always @(*) begin
- litedramcore_master_p2_cke <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_cke <= litedramcore_ext_dfi_p2_cke;
- end else begin
- litedramcore_master_p2_cke <= litedramcore_slave_p2_cke;
- end
- end else begin
- litedramcore_master_p2_cke <= litedramcore_csr_dfi_p2_cke;
- end
-end
-always @(*) begin
- litedramcore_master_p2_odt <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_odt <= litedramcore_ext_dfi_p2_odt;
- end else begin
- litedramcore_master_p2_odt <= litedramcore_slave_p2_odt;
- end
- end else begin
- litedramcore_master_p2_odt <= litedramcore_csr_dfi_p2_odt;
- end
-end
-always @(*) begin
- litedramcore_master_p2_reset_n <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_reset_n <= litedramcore_ext_dfi_p2_reset_n;
- end else begin
- litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n;
- end
- end else begin
- litedramcore_master_p2_reset_n <= litedramcore_csr_dfi_p2_reset_n;
- end
-end
-always @(*) begin
- litedramcore_master_p2_act_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_act_n <= litedramcore_ext_dfi_p2_act_n;
- end else begin
- litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n;
- end
- end else begin
- litedramcore_master_p2_act_n <= litedramcore_csr_dfi_p2_act_n;
- end
-end
-always @(*) begin
- litedramcore_master_p2_wrdata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_wrdata <= litedramcore_ext_dfi_p2_wrdata;
- end else begin
- litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata;
- end
- end else begin
- litedramcore_master_p2_wrdata <= litedramcore_csr_dfi_p2_wrdata;
- end
-end
-always @(*) begin
- litedramcore_master_p2_wrdata_en <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_wrdata_en <= litedramcore_ext_dfi_p2_wrdata_en;
- end else begin
- litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en;
- end
- end else begin
- litedramcore_master_p2_wrdata_en <= litedramcore_csr_dfi_p2_wrdata_en;
- end
-end
-always @(*) begin
- litedramcore_master_p2_wrdata_mask <= 4'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_wrdata_mask <= litedramcore_ext_dfi_p2_wrdata_mask;
- end else begin
- litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask;
- end
- end else begin
- litedramcore_master_p2_wrdata_mask <= litedramcore_csr_dfi_p2_wrdata_mask;
- end
-end
-always @(*) begin
- litedramcore_master_p2_rddata_en <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_rddata_en <= litedramcore_ext_dfi_p2_rddata_en;
- end else begin
- litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en;
- end
- end else begin
- litedramcore_master_p2_rddata_en <= litedramcore_csr_dfi_p2_rddata_en;
- end
-end
-always @(*) begin
- litedramcore_master_p3_address <= 14'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_address <= litedramcore_ext_dfi_p3_address;
- end else begin
- litedramcore_master_p3_address <= litedramcore_slave_p3_address;
- end
- end else begin
- litedramcore_master_p3_address <= litedramcore_csr_dfi_p3_address;
- end
-end
-always @(*) begin
- litedramcore_master_p3_bank <= 3'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_bank <= litedramcore_ext_dfi_p3_bank;
- end else begin
- litedramcore_master_p3_bank <= litedramcore_slave_p3_bank;
- end
- end else begin
- litedramcore_master_p3_bank <= litedramcore_csr_dfi_p3_bank;
- end
-end
-always @(*) begin
- litedramcore_master_p3_cas_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_cas_n <= litedramcore_ext_dfi_p3_cas_n;
- end else begin
- litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n;
- end
- end else begin
- litedramcore_master_p3_cas_n <= litedramcore_csr_dfi_p3_cas_n;
- end
-end
-always @(*) begin
- litedramcore_master_p3_cs_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_cs_n <= litedramcore_ext_dfi_p3_cs_n;
- end else begin
- litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n;
- end
- end else begin
- litedramcore_master_p3_cs_n <= litedramcore_csr_dfi_p3_cs_n;
- end
-end
-always @(*) begin
- litedramcore_master_p3_ras_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_ras_n <= litedramcore_ext_dfi_p3_ras_n;
- end else begin
- litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n;
- end
- end else begin
- litedramcore_master_p3_ras_n <= litedramcore_csr_dfi_p3_ras_n;
- end
-end
-always @(*) begin
- litedramcore_master_p3_we_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_we_n <= litedramcore_ext_dfi_p3_we_n;
- end else begin
- litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n;
- end
- end else begin
- litedramcore_master_p3_we_n <= litedramcore_csr_dfi_p3_we_n;
- end
-end
-always @(*) begin
- litedramcore_master_p3_cke <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_cke <= litedramcore_ext_dfi_p3_cke;
- end else begin
- litedramcore_master_p3_cke <= litedramcore_slave_p3_cke;
- end
- end else begin
- litedramcore_master_p3_cke <= litedramcore_csr_dfi_p3_cke;
- end
-end
-always @(*) begin
- litedramcore_master_p3_odt <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_odt <= litedramcore_ext_dfi_p3_odt;
- end else begin
- litedramcore_master_p3_odt <= litedramcore_slave_p3_odt;
- end
- end else begin
- litedramcore_master_p3_odt <= litedramcore_csr_dfi_p3_odt;
- end
-end
-always @(*) begin
- litedramcore_master_p3_reset_n <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_reset_n <= litedramcore_ext_dfi_p3_reset_n;
- end else begin
- litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n;
- end
- end else begin
- litedramcore_master_p3_reset_n <= litedramcore_csr_dfi_p3_reset_n;
- end
-end
-always @(*) begin
- litedramcore_master_p3_act_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_act_n <= litedramcore_ext_dfi_p3_act_n;
- end else begin
- litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n;
- end
- end else begin
- litedramcore_master_p3_act_n <= litedramcore_csr_dfi_p3_act_n;
- end
-end
-always @(*) begin
- litedramcore_master_p3_wrdata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_wrdata <= litedramcore_ext_dfi_p3_wrdata;
- end else begin
- litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata;
- end
- end else begin
- litedramcore_master_p3_wrdata <= litedramcore_csr_dfi_p3_wrdata;
- end
-end
-always @(*) begin
- litedramcore_master_p3_wrdata_en <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_wrdata_en <= litedramcore_ext_dfi_p3_wrdata_en;
- end else begin
- litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en;
- end
- end else begin
- litedramcore_master_p3_wrdata_en <= litedramcore_csr_dfi_p3_wrdata_en;
- end
-end
-always @(*) begin
- litedramcore_master_p3_wrdata_mask <= 4'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_wrdata_mask <= litedramcore_ext_dfi_p3_wrdata_mask;
- end else begin
- litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask;
- end
- end else begin
- litedramcore_master_p3_wrdata_mask <= litedramcore_csr_dfi_p3_wrdata_mask;
- end
-end
-always @(*) begin
- litedramcore_master_p3_rddata_en <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_rddata_en <= litedramcore_ext_dfi_p3_rddata_en;
- end else begin
- litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en;
- end
- end else begin
- litedramcore_master_p3_rddata_en <= litedramcore_csr_dfi_p3_rddata_en;
- end
+ litedramcore_csr_dfi_p0_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_csr_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+ end
+end
+always @(*) begin
+ litedramcore_csr_dfi_p1_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata;
+ end
+end
+always @(*) begin
+ litedramcore_csr_dfi_p1_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+ end
+end
+always @(*) begin
+ litedramcore_csr_dfi_p2_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_csr_dfi_p2_rddata <= litedramcore_master_p2_rddata;
+ end
+end
+always @(*) begin
+ litedramcore_csr_dfi_p2_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_csr_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+ end
+end
+always @(*) begin
+ litedramcore_csr_dfi_p3_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_csr_dfi_p3_rddata <= litedramcore_master_p3_rddata;
+ end
+end
+always @(*) begin
+ litedramcore_csr_dfi_p3_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_csr_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+ end
+end
+always @(*) begin
+ litedramcore_ext_dfi_p0_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_ext_dfi_p0_rddata <= litedramcore_master_p0_rddata;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_ext_dfi_p0_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_ext_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_ext_dfi_p1_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_ext_dfi_p1_rddata <= litedramcore_master_p1_rddata;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_ext_dfi_p1_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_ext_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_ext_dfi_p2_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_ext_dfi_p2_rddata <= litedramcore_master_p2_rddata;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_ext_dfi_p2_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_ext_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p0_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ end else begin
+ litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p0_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ end else begin
+ litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_ext_dfi_p3_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_ext_dfi_p3_rddata <= litedramcore_master_p3_rddata;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_ext_dfi_p3_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_ext_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p1_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ end else begin
+ litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p1_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ end else begin
+ litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p2_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ end else begin
+ litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p2_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ end else begin
+ litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p3_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ end else begin
+ litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p3_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ end else begin
+ litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_address <= 14'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_address <= litedramcore_ext_dfi_p0_address;
+ end else begin
+ litedramcore_master_p0_address <= litedramcore_slave_p0_address;
+ end
+ end else begin
+ litedramcore_master_p0_address <= litedramcore_csr_dfi_p0_address;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_bank <= 3'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_bank <= litedramcore_ext_dfi_p0_bank;
+ end else begin
+ litedramcore_master_p0_bank <= litedramcore_slave_p0_bank;
+ end
+ end else begin
+ litedramcore_master_p0_bank <= litedramcore_csr_dfi_p0_bank;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_cas_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_cas_n <= litedramcore_ext_dfi_p0_cas_n;
+ end else begin
+ litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n;
+ end
+ end else begin
+ litedramcore_master_p0_cas_n <= litedramcore_csr_dfi_p0_cas_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_cs_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n;
+ end else begin
+ litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n;
+ end
+ end else begin
+ litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_ras_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n;
+ end else begin
+ litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n;
+ end
+ end else begin
+ litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_we_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n;
+ end else begin
+ litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n;
+ end
+ end else begin
+ litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_cke <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_cke <= litedramcore_ext_dfi_p0_cke;
+ end else begin
+ litedramcore_master_p0_cke <= litedramcore_slave_p0_cke;
+ end
+ end else begin
+ litedramcore_master_p0_cke <= litedramcore_csr_dfi_p0_cke;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_odt <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_odt <= litedramcore_ext_dfi_p0_odt;
+ end else begin
+ litedramcore_master_p0_odt <= litedramcore_slave_p0_odt;
+ end
+ end else begin
+ litedramcore_master_p0_odt <= litedramcore_csr_dfi_p0_odt;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_reset_n <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_reset_n <= litedramcore_ext_dfi_p0_reset_n;
+ end else begin
+ litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n;
+ end
+ end else begin
+ litedramcore_master_p0_reset_n <= litedramcore_csr_dfi_p0_reset_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_act_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_act_n <= litedramcore_ext_dfi_p0_act_n;
+ end else begin
+ litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n;
+ end
+ end else begin
+ litedramcore_master_p0_act_n <= litedramcore_csr_dfi_p0_act_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_wrdata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_wrdata <= litedramcore_ext_dfi_p0_wrdata;
+ end else begin
+ litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata;
+ end
+ end else begin
+ litedramcore_master_p0_wrdata <= litedramcore_csr_dfi_p0_wrdata;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_wrdata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_wrdata_en <= litedramcore_ext_dfi_p0_wrdata_en;
+ end else begin
+ litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en;
+ end
+ end else begin
+ litedramcore_master_p0_wrdata_en <= litedramcore_csr_dfi_p0_wrdata_en;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_wrdata_mask <= 4'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_wrdata_mask <= litedramcore_ext_dfi_p0_wrdata_mask;
+ end else begin
+ litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask;
+ end
+ end else begin
+ litedramcore_master_p0_wrdata_mask <= litedramcore_csr_dfi_p0_wrdata_mask;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_rddata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_rddata_en <= litedramcore_ext_dfi_p0_rddata_en;
+ end else begin
+ litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en;
+ end
+ end else begin
+ litedramcore_master_p0_rddata_en <= litedramcore_csr_dfi_p0_rddata_en;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_address <= 14'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_address <= litedramcore_ext_dfi_p1_address;
+ end else begin
+ litedramcore_master_p1_address <= litedramcore_slave_p1_address;
+ end
+ end else begin
+ litedramcore_master_p1_address <= litedramcore_csr_dfi_p1_address;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_bank <= 3'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_bank <= litedramcore_ext_dfi_p1_bank;
+ end else begin
+ litedramcore_master_p1_bank <= litedramcore_slave_p1_bank;
+ end
+ end else begin
+ litedramcore_master_p1_bank <= litedramcore_csr_dfi_p1_bank;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_cas_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_cas_n <= litedramcore_ext_dfi_p1_cas_n;
+ end else begin
+ litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n;
+ end
+ end else begin
+ litedramcore_master_p1_cas_n <= litedramcore_csr_dfi_p1_cas_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_cs_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_cs_n <= litedramcore_ext_dfi_p1_cs_n;
+ end else begin
+ litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n;
+ end
+ end else begin
+ litedramcore_master_p1_cs_n <= litedramcore_csr_dfi_p1_cs_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_ras_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_ras_n <= litedramcore_ext_dfi_p1_ras_n;
+ end else begin
+ litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n;
+ end
+ end else begin
+ litedramcore_master_p1_ras_n <= litedramcore_csr_dfi_p1_ras_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_we_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_we_n <= litedramcore_ext_dfi_p1_we_n;
+ end else begin
+ litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n;
+ end
+ end else begin
+ litedramcore_master_p1_we_n <= litedramcore_csr_dfi_p1_we_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_cke <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_cke <= litedramcore_ext_dfi_p1_cke;
+ end else begin
+ litedramcore_master_p1_cke <= litedramcore_slave_p1_cke;
+ end
+ end else begin
+ litedramcore_master_p1_cke <= litedramcore_csr_dfi_p1_cke;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_odt <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_odt <= litedramcore_ext_dfi_p1_odt;
+ end else begin
+ litedramcore_master_p1_odt <= litedramcore_slave_p1_odt;
+ end
+ end else begin
+ litedramcore_master_p1_odt <= litedramcore_csr_dfi_p1_odt;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_reset_n <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_reset_n <= litedramcore_ext_dfi_p1_reset_n;
+ end else begin
+ litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n;
+ end
+ end else begin
+ litedramcore_master_p1_reset_n <= litedramcore_csr_dfi_p1_reset_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_act_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_act_n <= litedramcore_ext_dfi_p1_act_n;
+ end else begin
+ litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n;
+ end
+ end else begin
+ litedramcore_master_p1_act_n <= litedramcore_csr_dfi_p1_act_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_wrdata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_wrdata <= litedramcore_ext_dfi_p1_wrdata;
+ end else begin
+ litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata;
+ end
+ end else begin
+ litedramcore_master_p1_wrdata <= litedramcore_csr_dfi_p1_wrdata;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_wrdata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_wrdata_en <= litedramcore_ext_dfi_p1_wrdata_en;
+ end else begin
+ litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en;
+ end
+ end else begin
+ litedramcore_master_p1_wrdata_en <= litedramcore_csr_dfi_p1_wrdata_en;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_wrdata_mask <= 4'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_wrdata_mask <= litedramcore_ext_dfi_p1_wrdata_mask;
+ end else begin
+ litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask;
+ end
+ end else begin
+ litedramcore_master_p1_wrdata_mask <= litedramcore_csr_dfi_p1_wrdata_mask;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_rddata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_rddata_en <= litedramcore_ext_dfi_p1_rddata_en;
+ end else begin
+ litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en;
+ end
+ end else begin
+ litedramcore_master_p1_rddata_en <= litedramcore_csr_dfi_p1_rddata_en;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_address <= 14'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_address <= litedramcore_ext_dfi_p2_address;
+ end else begin
+ litedramcore_master_p2_address <= litedramcore_slave_p2_address;
+ end
+ end else begin
+ litedramcore_master_p2_address <= litedramcore_csr_dfi_p2_address;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_bank <= 3'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_bank <= litedramcore_ext_dfi_p2_bank;
+ end else begin
+ litedramcore_master_p2_bank <= litedramcore_slave_p2_bank;
+ end
+ end else begin
+ litedramcore_master_p2_bank <= litedramcore_csr_dfi_p2_bank;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_cas_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_cas_n <= litedramcore_ext_dfi_p2_cas_n;
+ end else begin
+ litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n;
+ end
+ end else begin
+ litedramcore_master_p2_cas_n <= litedramcore_csr_dfi_p2_cas_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_cs_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_cs_n <= litedramcore_ext_dfi_p2_cs_n;
+ end else begin
+ litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n;
+ end
+ end else begin
+ litedramcore_master_p2_cs_n <= litedramcore_csr_dfi_p2_cs_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_ras_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_ras_n <= litedramcore_ext_dfi_p2_ras_n;
+ end else begin
+ litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n;
+ end
+ end else begin
+ litedramcore_master_p2_ras_n <= litedramcore_csr_dfi_p2_ras_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_we_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_we_n <= litedramcore_ext_dfi_p2_we_n;
+ end else begin
+ litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n;
+ end
+ end else begin
+ litedramcore_master_p2_we_n <= litedramcore_csr_dfi_p2_we_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_cke <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_cke <= litedramcore_ext_dfi_p2_cke;
+ end else begin
+ litedramcore_master_p2_cke <= litedramcore_slave_p2_cke;
+ end
+ end else begin
+ litedramcore_master_p2_cke <= litedramcore_csr_dfi_p2_cke;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_odt <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_odt <= litedramcore_ext_dfi_p2_odt;
+ end else begin
+ litedramcore_master_p2_odt <= litedramcore_slave_p2_odt;
+ end
+ end else begin
+ litedramcore_master_p2_odt <= litedramcore_csr_dfi_p2_odt;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_reset_n <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_reset_n <= litedramcore_ext_dfi_p2_reset_n;
+ end else begin
+ litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n;
+ end
+ end else begin
+ litedramcore_master_p2_reset_n <= litedramcore_csr_dfi_p2_reset_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_act_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_act_n <= litedramcore_ext_dfi_p2_act_n;
+ end else begin
+ litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n;
+ end
+ end else begin
+ litedramcore_master_p2_act_n <= litedramcore_csr_dfi_p2_act_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_wrdata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_wrdata <= litedramcore_ext_dfi_p2_wrdata;
+ end else begin
+ litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata;
+ end
+ end else begin
+ litedramcore_master_p2_wrdata <= litedramcore_csr_dfi_p2_wrdata;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_wrdata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_wrdata_en <= litedramcore_ext_dfi_p2_wrdata_en;
+ end else begin
+ litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en;
+ end
+ end else begin
+ litedramcore_master_p2_wrdata_en <= litedramcore_csr_dfi_p2_wrdata_en;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_wrdata_mask <= 4'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_wrdata_mask <= litedramcore_ext_dfi_p2_wrdata_mask;
+ end else begin
+ litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask;
+ end
+ end else begin
+ litedramcore_master_p2_wrdata_mask <= litedramcore_csr_dfi_p2_wrdata_mask;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_rddata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_rddata_en <= litedramcore_ext_dfi_p2_rddata_en;
+ end else begin
+ litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en;
+ end
+ end else begin
+ litedramcore_master_p2_rddata_en <= litedramcore_csr_dfi_p2_rddata_en;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_address <= 14'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_address <= litedramcore_ext_dfi_p3_address;
+ end else begin
+ litedramcore_master_p3_address <= litedramcore_slave_p3_address;
+ end
+ end else begin
+ litedramcore_master_p3_address <= litedramcore_csr_dfi_p3_address;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_bank <= 3'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_bank <= litedramcore_ext_dfi_p3_bank;
+ end else begin
+ litedramcore_master_p3_bank <= litedramcore_slave_p3_bank;
+ end
+ end else begin
+ litedramcore_master_p3_bank <= litedramcore_csr_dfi_p3_bank;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_cas_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_cas_n <= litedramcore_ext_dfi_p3_cas_n;
+ end else begin
+ litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n;
+ end
+ end else begin
+ litedramcore_master_p3_cas_n <= litedramcore_csr_dfi_p3_cas_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_cs_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_cs_n <= litedramcore_ext_dfi_p3_cs_n;
+ end else begin
+ litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n;
+ end
+ end else begin
+ litedramcore_master_p3_cs_n <= litedramcore_csr_dfi_p3_cs_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_ras_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_ras_n <= litedramcore_ext_dfi_p3_ras_n;
+ end else begin
+ litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n;
+ end
+ end else begin
+ litedramcore_master_p3_ras_n <= litedramcore_csr_dfi_p3_ras_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_we_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_we_n <= litedramcore_ext_dfi_p3_we_n;
+ end else begin
+ litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n;
+ end
+ end else begin
+ litedramcore_master_p3_we_n <= litedramcore_csr_dfi_p3_we_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_cke <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_cke <= litedramcore_ext_dfi_p3_cke;
+ end else begin
+ litedramcore_master_p3_cke <= litedramcore_slave_p3_cke;
+ end
+ end else begin
+ litedramcore_master_p3_cke <= litedramcore_csr_dfi_p3_cke;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_odt <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_odt <= litedramcore_ext_dfi_p3_odt;
+ end else begin
+ litedramcore_master_p3_odt <= litedramcore_slave_p3_odt;
+ end
+ end else begin
+ litedramcore_master_p3_odt <= litedramcore_csr_dfi_p3_odt;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_reset_n <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_reset_n <= litedramcore_ext_dfi_p3_reset_n;
+ end else begin
+ litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n;
+ end
+ end else begin
+ litedramcore_master_p3_reset_n <= litedramcore_csr_dfi_p3_reset_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_act_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_act_n <= litedramcore_ext_dfi_p3_act_n;
+ end else begin
+ litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n;
+ end
+ end else begin
+ litedramcore_master_p3_act_n <= litedramcore_csr_dfi_p3_act_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_wrdata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_wrdata <= litedramcore_ext_dfi_p3_wrdata;
+ end else begin
+ litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata;
+ end
+ end else begin
+ litedramcore_master_p3_wrdata <= litedramcore_csr_dfi_p3_wrdata;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_wrdata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_wrdata_en <= litedramcore_ext_dfi_p3_wrdata_en;
+ end else begin
+ litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en;
+ end
+ end else begin
+ litedramcore_master_p3_wrdata_en <= litedramcore_csr_dfi_p3_wrdata_en;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_wrdata_mask <= 4'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_wrdata_mask <= litedramcore_ext_dfi_p3_wrdata_mask;
+ end else begin
+ litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask;
+ end
+ end else begin
+ litedramcore_master_p3_wrdata_mask <= litedramcore_csr_dfi_p3_wrdata_mask;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_rddata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_rddata_en <= litedramcore_ext_dfi_p3_rddata_en;
+ end else begin
+ litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en;
+ end
+ end else begin
+ litedramcore_master_p3_rddata_en <= litedramcore_csr_dfi_p3_rddata_en;
+ end
end
assign litedramcore_csr_dfi_p0_cke = litedramcore_cke;
assign litedramcore_csr_dfi_p1_cke = litedramcore_cke;
assign litedramcore_csr_dfi_p2_reset_n = litedramcore_reset_n;
assign litedramcore_csr_dfi_p3_reset_n = litedramcore_reset_n;
always @(*) begin
- litedramcore_csr_dfi_p0_we_n <= 1'd1;
- if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we);
- end else begin
- litedramcore_csr_dfi_p0_we_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p0_we_n <= 1'd1;
+ if (litedramcore_phaseinjector0_command_issue_re) begin
+ litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we);
+ end else begin
+ litedramcore_csr_dfi_p0_we_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p0_cas_n <= 1'd1;
- if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_csr_dfi_p0_cas_n <= (~litedramcore_phaseinjector0_csrfield_cas);
- end else begin
- litedramcore_csr_dfi_p0_cas_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p0_cas_n <= 1'd1;
+ if (litedramcore_phaseinjector0_command_issue_re) begin
+ litedramcore_csr_dfi_p0_cas_n <= (~litedramcore_phaseinjector0_csrfield_cas);
+ end else begin
+ litedramcore_csr_dfi_p0_cas_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p0_cs_n <= 1'd1;
- if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}};
- end else begin
- litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}};
- end
+ litedramcore_csr_dfi_p0_cs_n <= 1'd1;
+ if (litedramcore_phaseinjector0_command_issue_re) begin
+ litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}};
+ end else begin
+ litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}};
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p0_ras_n <= 1'd1;
- if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_csr_dfi_p0_ras_n <= (~litedramcore_phaseinjector0_csrfield_ras);
- end else begin
- litedramcore_csr_dfi_p0_ras_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p0_ras_n <= 1'd1;
+ if (litedramcore_phaseinjector0_command_issue_re) begin
+ litedramcore_csr_dfi_p0_ras_n <= (~litedramcore_phaseinjector0_csrfield_ras);
+ end else begin
+ litedramcore_csr_dfi_p0_ras_n <= 1'd1;
+ end
end
assign litedramcore_csr_dfi_p0_address = litedramcore_phaseinjector0_address_storage;
assign litedramcore_csr_dfi_p0_bank = litedramcore_phaseinjector0_baddress_storage;
assign litedramcore_csr_dfi_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage;
assign litedramcore_csr_dfi_p0_wrdata_mask = 1'd0;
always @(*) begin
- litedramcore_csr_dfi_p1_we_n <= 1'd1;
- if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we);
- end else begin
- litedramcore_csr_dfi_p1_we_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p1_we_n <= 1'd1;
+ if (litedramcore_phaseinjector1_command_issue_re) begin
+ litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we);
+ end else begin
+ litedramcore_csr_dfi_p1_we_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p1_cas_n <= 1'd1;
- if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_csr_dfi_p1_cas_n <= (~litedramcore_phaseinjector1_csrfield_cas);
- end else begin
- litedramcore_csr_dfi_p1_cas_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p1_cas_n <= 1'd1;
+ if (litedramcore_phaseinjector1_command_issue_re) begin
+ litedramcore_csr_dfi_p1_cas_n <= (~litedramcore_phaseinjector1_csrfield_cas);
+ end else begin
+ litedramcore_csr_dfi_p1_cas_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p1_cs_n <= 1'd1;
- if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}};
- end else begin
- litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}};
- end
+ litedramcore_csr_dfi_p1_cs_n <= 1'd1;
+ if (litedramcore_phaseinjector1_command_issue_re) begin
+ litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}};
+ end else begin
+ litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}};
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p1_ras_n <= 1'd1;
- if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_csr_dfi_p1_ras_n <= (~litedramcore_phaseinjector1_csrfield_ras);
- end else begin
- litedramcore_csr_dfi_p1_ras_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p1_ras_n <= 1'd1;
+ if (litedramcore_phaseinjector1_command_issue_re) begin
+ litedramcore_csr_dfi_p1_ras_n <= (~litedramcore_phaseinjector1_csrfield_ras);
+ end else begin
+ litedramcore_csr_dfi_p1_ras_n <= 1'd1;
+ end
end
assign litedramcore_csr_dfi_p1_address = litedramcore_phaseinjector1_address_storage;
assign litedramcore_csr_dfi_p1_bank = litedramcore_phaseinjector1_baddress_storage;
assign litedramcore_csr_dfi_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage;
assign litedramcore_csr_dfi_p1_wrdata_mask = 1'd0;
always @(*) begin
- litedramcore_csr_dfi_p2_we_n <= 1'd1;
- if (litedramcore_phaseinjector2_command_issue_re) begin
- litedramcore_csr_dfi_p2_we_n <= (~litedramcore_phaseinjector2_csrfield_we);
- end else begin
- litedramcore_csr_dfi_p2_we_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p2_we_n <= 1'd1;
+ if (litedramcore_phaseinjector2_command_issue_re) begin
+ litedramcore_csr_dfi_p2_we_n <= (~litedramcore_phaseinjector2_csrfield_we);
+ end else begin
+ litedramcore_csr_dfi_p2_we_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p2_cas_n <= 1'd1;
- if (litedramcore_phaseinjector2_command_issue_re) begin
- litedramcore_csr_dfi_p2_cas_n <= (~litedramcore_phaseinjector2_csrfield_cas);
- end else begin
- litedramcore_csr_dfi_p2_cas_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p2_cas_n <= 1'd1;
+ if (litedramcore_phaseinjector2_command_issue_re) begin
+ litedramcore_csr_dfi_p2_cas_n <= (~litedramcore_phaseinjector2_csrfield_cas);
+ end else begin
+ litedramcore_csr_dfi_p2_cas_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p2_cs_n <= 1'd1;
- if (litedramcore_phaseinjector2_command_issue_re) begin
- litedramcore_csr_dfi_p2_cs_n <= {1{(~litedramcore_phaseinjector2_csrfield_cs)}};
- end else begin
- litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}};
- end
+ litedramcore_csr_dfi_p2_cs_n <= 1'd1;
+ if (litedramcore_phaseinjector2_command_issue_re) begin
+ litedramcore_csr_dfi_p2_cs_n <= {1{(~litedramcore_phaseinjector2_csrfield_cs)}};
+ end else begin
+ litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}};
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p2_ras_n <= 1'd1;
- if (litedramcore_phaseinjector2_command_issue_re) begin
- litedramcore_csr_dfi_p2_ras_n <= (~litedramcore_phaseinjector2_csrfield_ras);
- end else begin
- litedramcore_csr_dfi_p2_ras_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p2_ras_n <= 1'd1;
+ if (litedramcore_phaseinjector2_command_issue_re) begin
+ litedramcore_csr_dfi_p2_ras_n <= (~litedramcore_phaseinjector2_csrfield_ras);
+ end else begin
+ litedramcore_csr_dfi_p2_ras_n <= 1'd1;
+ end
end
assign litedramcore_csr_dfi_p2_address = litedramcore_phaseinjector2_address_storage;
assign litedramcore_csr_dfi_p2_bank = litedramcore_phaseinjector2_baddress_storage;
assign litedramcore_csr_dfi_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage;
assign litedramcore_csr_dfi_p2_wrdata_mask = 1'd0;
always @(*) begin
- litedramcore_csr_dfi_p3_we_n <= 1'd1;
- if (litedramcore_phaseinjector3_command_issue_re) begin
- litedramcore_csr_dfi_p3_we_n <= (~litedramcore_phaseinjector3_csrfield_we);
- end else begin
- litedramcore_csr_dfi_p3_we_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p3_we_n <= 1'd1;
+ if (litedramcore_phaseinjector3_command_issue_re) begin
+ litedramcore_csr_dfi_p3_we_n <= (~litedramcore_phaseinjector3_csrfield_we);
+ end else begin
+ litedramcore_csr_dfi_p3_we_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p3_cas_n <= 1'd1;
- if (litedramcore_phaseinjector3_command_issue_re) begin
- litedramcore_csr_dfi_p3_cas_n <= (~litedramcore_phaseinjector3_csrfield_cas);
- end else begin
- litedramcore_csr_dfi_p3_cas_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p3_cas_n <= 1'd1;
+ if (litedramcore_phaseinjector3_command_issue_re) begin
+ litedramcore_csr_dfi_p3_cas_n <= (~litedramcore_phaseinjector3_csrfield_cas);
+ end else begin
+ litedramcore_csr_dfi_p3_cas_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p3_cs_n <= 1'd1;
- if (litedramcore_phaseinjector3_command_issue_re) begin
- litedramcore_csr_dfi_p3_cs_n <= {1{(~litedramcore_phaseinjector3_csrfield_cs)}};
- end else begin
- litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}};
- end
+ litedramcore_csr_dfi_p3_cs_n <= 1'd1;
+ if (litedramcore_phaseinjector3_command_issue_re) begin
+ litedramcore_csr_dfi_p3_cs_n <= {1{(~litedramcore_phaseinjector3_csrfield_cs)}};
+ end else begin
+ litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}};
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p3_ras_n <= 1'd1;
- if (litedramcore_phaseinjector3_command_issue_re) begin
- litedramcore_csr_dfi_p3_ras_n <= (~litedramcore_phaseinjector3_csrfield_ras);
- end else begin
- litedramcore_csr_dfi_p3_ras_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p3_ras_n <= 1'd1;
+ if (litedramcore_phaseinjector3_command_issue_re) begin
+ litedramcore_csr_dfi_p3_ras_n <= (~litedramcore_phaseinjector3_csrfield_ras);
+ end else begin
+ litedramcore_csr_dfi_p3_ras_n <= 1'd1;
+ end
end
assign litedramcore_csr_dfi_p3_address = litedramcore_phaseinjector3_address_storage;
assign litedramcore_csr_dfi_p3_bank = litedramcore_phaseinjector3_baddress_storage;
assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1;
assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1;
always @(*) begin
- litedramcore_refresher_next_state <= 2'd0;
- litedramcore_refresher_next_state <= litedramcore_refresher_state;
- case (litedramcore_refresher_state)
- 1'd1: begin
- if (litedramcore_cmd_ready) begin
- litedramcore_refresher_next_state <= 2'd2;
- end
- end
- 2'd2: begin
- if (litedramcore_sequencer_done0) begin
- if (litedramcore_wants_zqcs) begin
- litedramcore_refresher_next_state <= 2'd3;
- end else begin
- litedramcore_refresher_next_state <= 1'd0;
- end
- end
- end
- 2'd3: begin
- if (litedramcore_zqcs_executer_done) begin
- litedramcore_refresher_next_state <= 1'd0;
- end
- end
- default: begin
- if (1'd1) begin
- if (litedramcore_wants_refresh) begin
- litedramcore_refresher_next_state <= 1'd1;
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_zqcs_executer_start <= 1'd0;
- case (litedramcore_refresher_state)
- 1'd1: begin
- end
- 2'd2: begin
- if (litedramcore_sequencer_done0) begin
- if (litedramcore_wants_zqcs) begin
- litedramcore_zqcs_executer_start <= 1'd1;
- end else begin
- end
- end
- end
- 2'd3: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_cmd_last <= 1'd0;
- case (litedramcore_refresher_state)
- 1'd1: begin
- end
- 2'd2: begin
- if (litedramcore_sequencer_done0) begin
- if (litedramcore_wants_zqcs) begin
- end else begin
- litedramcore_cmd_last <= 1'd1;
- end
- end
- end
- 2'd3: begin
- if (litedramcore_zqcs_executer_done) begin
- litedramcore_cmd_last <= 1'd1;
- end
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_sequencer_start0 <= 1'd0;
- case (litedramcore_refresher_state)
- 1'd1: begin
- if (litedramcore_cmd_ready) begin
- litedramcore_sequencer_start0 <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_cmd_valid <= 1'd0;
- case (litedramcore_refresher_state)
- 1'd1: begin
- litedramcore_cmd_valid <= 1'd1;
- end
- 2'd2: begin
- litedramcore_cmd_valid <= 1'd1;
- if (litedramcore_sequencer_done0) begin
- if (litedramcore_wants_zqcs) begin
- end else begin
- litedramcore_cmd_valid <= 1'd0;
- end
- end
- end
- 2'd3: begin
- litedramcore_cmd_valid <= 1'd1;
- if (litedramcore_zqcs_executer_done) begin
- litedramcore_cmd_valid <= 1'd0;
- end
- end
- default: begin
- end
- endcase
-end
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine0_req_valid;
-assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine0_req_we;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine0_req_addr;
-assign litedramcore_bankmachine0_cmd_buffer_sink_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine0_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine0_cmd_buffer_sink_first = litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine0_cmd_buffer_sink_last = litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine0_cmd_buffer_sink_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine0_cmd_buffer_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid);
-assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine0_cmd_buffer_source_valid);
-assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]);
+ litedramcore_refresher_next_state <= 2'd0;
+ litedramcore_refresher_next_state <= litedramcore_refresher_state;
+ case (litedramcore_refresher_state)
+ 1'd1: begin
+ if (litedramcore_cmd_ready) begin
+ litedramcore_refresher_next_state <= 2'd2;
+ end
+ end
+ 2'd2: begin
+ if (litedramcore_sequencer_done0) begin
+ if (litedramcore_wants_zqcs) begin
+ litedramcore_refresher_next_state <= 2'd3;
+ end else begin
+ litedramcore_refresher_next_state <= 1'd0;
+ end
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_zqcs_executer_done) begin
+ litedramcore_refresher_next_state <= 1'd0;
+ end
+ end
+ default: begin
+ if (1'd1) begin
+ if (litedramcore_wants_refresh) begin
+ litedramcore_refresher_next_state <= 1'd1;
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_zqcs_executer_start <= 1'd0;
+ case (litedramcore_refresher_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ if (litedramcore_sequencer_done0) begin
+ if (litedramcore_wants_zqcs) begin
+ litedramcore_zqcs_executer_start <= 1'd1;
+ end else begin
+ end
+ end
+ end
+ 2'd3: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_cmd_last <= 1'd0;
+ case (litedramcore_refresher_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ if (litedramcore_sequencer_done0) begin
+ if (litedramcore_wants_zqcs) begin
+ end else begin
+ litedramcore_cmd_last <= 1'd1;
+ end
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_zqcs_executer_done) begin
+ litedramcore_cmd_last <= 1'd1;
+ end
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_sequencer_start0 <= 1'd0;
+ case (litedramcore_refresher_state)
+ 1'd1: begin
+ if (litedramcore_cmd_ready) begin
+ litedramcore_sequencer_start0 <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_cmd_valid <= 1'd0;
+ case (litedramcore_refresher_state)
+ 1'd1: begin
+ litedramcore_cmd_valid <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_cmd_valid <= 1'd1;
+ if (litedramcore_sequencer_done0) begin
+ if (litedramcore_wants_zqcs) begin
+ end else begin
+ litedramcore_cmd_valid <= 1'd0;
+ end
+ end
+ end
+ 2'd3: begin
+ litedramcore_cmd_valid <= 1'd1;
+ if (litedramcore_zqcs_executer_done) begin
+ litedramcore_cmd_valid <= 1'd0;
+ end
+ end
+ default: begin
+ end
+ endcase
+end
+assign litedramcore_bankmachine0_sink_valid = litedramcore_bankmachine0_req_valid;
+assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_sink_ready;
+assign litedramcore_bankmachine0_sink_payload_we = litedramcore_bankmachine0_req_we;
+assign litedramcore_bankmachine0_sink_payload_addr = litedramcore_bankmachine0_req_addr;
+assign litedramcore_bankmachine0_sink_sink_valid = litedramcore_bankmachine0_source_valid;
+assign litedramcore_bankmachine0_source_ready = litedramcore_bankmachine0_sink_sink_ready;
+assign litedramcore_bankmachine0_sink_sink_first = litedramcore_bankmachine0_source_first;
+assign litedramcore_bankmachine0_sink_sink_last = litedramcore_bankmachine0_source_last;
+assign litedramcore_bankmachine0_sink_sink_payload_we = litedramcore_bankmachine0_source_payload_we;
+assign litedramcore_bankmachine0_sink_sink_payload_addr = litedramcore_bankmachine0_source_payload_addr;
+assign litedramcore_bankmachine0_source_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid);
+assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_source_valid | litedramcore_bankmachine0_source_source_valid);
+assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_source_source_payload_addr[20:7]);
assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
always @(*) begin
- litedramcore_bankmachine0_cmd_payload_a <= 14'd0;
- if (litedramcore_bankmachine0_row_col_n_addr_sel) begin
- litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7];
- end else begin
- litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine0_cmd_payload_a <= 14'd0;
+ if (litedramcore_bankmachine0_row_col_n_addr_sel) begin
+ litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_source_source_payload_addr[20:7];
+ end else begin
+ litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write);
assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
always @(*) begin
- litedramcore_bankmachine0_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine0_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7])) begin
- litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine0_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | litedramcore_bankmachine0_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re);
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine0_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine0_next_state <= 4'd0;
- litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- if (litedramcore_bankmachine0_cmd_ready) begin
- litedramcore_bankmachine0_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- if (litedramcore_bankmachine0_cmd_ready) begin
- litedramcore_bankmachine0_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine0_refresh_req)) begin
- litedramcore_bankmachine0_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine0_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine0_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine0_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine0_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- litedramcore_bankmachine0_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin
- litedramcore_bankmachine0_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine0_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine0_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine0_twtpcon_ready) begin
- litedramcore_bankmachine0_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- litedramcore_bankmachine0_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_row_open <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_row_close <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- litedramcore_bankmachine0_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine0_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine0_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine1_req_valid;
-assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine1_req_we;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine1_req_addr;
-assign litedramcore_bankmachine1_cmd_buffer_sink_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine1_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine1_cmd_buffer_sink_first = litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine1_cmd_buffer_sink_last = litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine1_cmd_buffer_sink_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine1_cmd_buffer_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid);
-assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine1_cmd_buffer_source_valid);
-assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]);
+ litedramcore_bankmachine0_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine0_source_valid & litedramcore_bankmachine0_source_source_valid)) begin
+ if ((litedramcore_bankmachine0_source_payload_addr[20:7] != litedramcore_bankmachine0_source_source_payload_addr[20:7])) begin
+ litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine0_syncfifo0_din = {litedramcore_bankmachine0_fifo_in_last, litedramcore_bankmachine0_fifo_in_first, litedramcore_bankmachine0_fifo_in_payload_addr, litedramcore_bankmachine0_fifo_in_payload_we};
+assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout;
+assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout;
+assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout;
+assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout;
+assign litedramcore_bankmachine0_sink_ready = litedramcore_bankmachine0_syncfifo0_writable;
+assign litedramcore_bankmachine0_syncfifo0_we = litedramcore_bankmachine0_sink_valid;
+assign litedramcore_bankmachine0_fifo_in_first = litedramcore_bankmachine0_sink_first;
+assign litedramcore_bankmachine0_fifo_in_last = litedramcore_bankmachine0_sink_last;
+assign litedramcore_bankmachine0_fifo_in_payload_we = litedramcore_bankmachine0_sink_payload_we;
+assign litedramcore_bankmachine0_fifo_in_payload_addr = litedramcore_bankmachine0_sink_payload_addr;
+assign litedramcore_bankmachine0_source_valid = litedramcore_bankmachine0_syncfifo0_readable;
+assign litedramcore_bankmachine0_source_first = litedramcore_bankmachine0_fifo_out_first;
+assign litedramcore_bankmachine0_source_last = litedramcore_bankmachine0_fifo_out_last;
+assign litedramcore_bankmachine0_source_payload_we = litedramcore_bankmachine0_fifo_out_payload_we;
+assign litedramcore_bankmachine0_source_payload_addr = litedramcore_bankmachine0_fifo_out_payload_addr;
+assign litedramcore_bankmachine0_syncfifo0_re = litedramcore_bankmachine0_source_ready;
+always @(*) begin
+ litedramcore_bankmachine0_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine0_replace) begin
+ litedramcore_bankmachine0_wrport_adr <= (litedramcore_bankmachine0_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine0_wrport_adr <= litedramcore_bankmachine0_produce;
+ end
+end
+assign litedramcore_bankmachine0_wrport_dat_w = litedramcore_bankmachine0_syncfifo0_din;
+assign litedramcore_bankmachine0_wrport_we = (litedramcore_bankmachine0_syncfifo0_we & (litedramcore_bankmachine0_syncfifo0_writable | litedramcore_bankmachine0_replace));
+assign litedramcore_bankmachine0_do_read = (litedramcore_bankmachine0_syncfifo0_readable & litedramcore_bankmachine0_syncfifo0_re);
+assign litedramcore_bankmachine0_rdport_adr = litedramcore_bankmachine0_consume;
+assign litedramcore_bankmachine0_syncfifo0_dout = litedramcore_bankmachine0_rdport_dat_r;
+assign litedramcore_bankmachine0_syncfifo0_writable = (litedramcore_bankmachine0_level != 5'd16);
+assign litedramcore_bankmachine0_syncfifo0_readable = (litedramcore_bankmachine0_level != 1'd0);
+assign litedramcore_bankmachine0_pipe_valid_sink_ready = ((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready);
+assign litedramcore_bankmachine0_pipe_valid_sink_valid = litedramcore_bankmachine0_sink_sink_valid;
+assign litedramcore_bankmachine0_sink_sink_ready = litedramcore_bankmachine0_pipe_valid_sink_ready;
+assign litedramcore_bankmachine0_pipe_valid_sink_first = litedramcore_bankmachine0_sink_sink_first;
+assign litedramcore_bankmachine0_pipe_valid_sink_last = litedramcore_bankmachine0_sink_sink_last;
+assign litedramcore_bankmachine0_pipe_valid_sink_payload_we = litedramcore_bankmachine0_sink_sink_payload_we;
+assign litedramcore_bankmachine0_pipe_valid_sink_payload_addr = litedramcore_bankmachine0_sink_sink_payload_addr;
+assign litedramcore_bankmachine0_source_source_valid = litedramcore_bankmachine0_pipe_valid_source_valid;
+assign litedramcore_bankmachine0_pipe_valid_source_ready = litedramcore_bankmachine0_source_source_ready;
+assign litedramcore_bankmachine0_source_source_first = litedramcore_bankmachine0_pipe_valid_source_first;
+assign litedramcore_bankmachine0_source_source_last = litedramcore_bankmachine0_pipe_valid_source_last;
+assign litedramcore_bankmachine0_source_source_payload_we = litedramcore_bankmachine0_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine0_source_source_payload_addr = litedramcore_bankmachine0_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine0_next_state <= 4'd0;
+ litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ if (litedramcore_bankmachine0_cmd_ready) begin
+ litedramcore_bankmachine0_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ if (litedramcore_bankmachine0_cmd_ready) begin
+ litedramcore_bankmachine0_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine0_refresh_req)) begin
+ litedramcore_bankmachine0_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine0_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine0_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine0_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine0_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ litedramcore_bankmachine0_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin
+ litedramcore_bankmachine0_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine0_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine0_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if (litedramcore_bankmachine0_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine0_twtpcon_ready) begin
+ litedramcore_bankmachine0_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_row_open <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ litedramcore_bankmachine0_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_row_close <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ litedramcore_bankmachine0_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine0_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine0_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if (litedramcore_bankmachine0_source_source_payload_we) begin
+ litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if (litedramcore_bankmachine0_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if (litedramcore_bankmachine0_source_source_payload_we) begin
+ litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if (litedramcore_bankmachine0_source_source_payload_we) begin
+ litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+assign litedramcore_bankmachine1_sink_valid = litedramcore_bankmachine1_req_valid;
+assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_sink_ready;
+assign litedramcore_bankmachine1_sink_payload_we = litedramcore_bankmachine1_req_we;
+assign litedramcore_bankmachine1_sink_payload_addr = litedramcore_bankmachine1_req_addr;
+assign litedramcore_bankmachine1_sink_sink_valid = litedramcore_bankmachine1_source_valid;
+assign litedramcore_bankmachine1_source_ready = litedramcore_bankmachine1_sink_sink_ready;
+assign litedramcore_bankmachine1_sink_sink_first = litedramcore_bankmachine1_source_first;
+assign litedramcore_bankmachine1_sink_sink_last = litedramcore_bankmachine1_source_last;
+assign litedramcore_bankmachine1_sink_sink_payload_we = litedramcore_bankmachine1_source_payload_we;
+assign litedramcore_bankmachine1_sink_sink_payload_addr = litedramcore_bankmachine1_source_payload_addr;
+assign litedramcore_bankmachine1_source_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid);
+assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_source_valid | litedramcore_bankmachine1_source_source_valid);
+assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_source_source_payload_addr[20:7]);
assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
always @(*) begin
- litedramcore_bankmachine1_cmd_payload_a <= 14'd0;
- if (litedramcore_bankmachine1_row_col_n_addr_sel) begin
- litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7];
- end else begin
- litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine1_cmd_payload_a <= 14'd0;
+ if (litedramcore_bankmachine1_row_col_n_addr_sel) begin
+ litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_source_source_payload_addr[20:7];
+ end else begin
+ litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write);
assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
always @(*) begin
- litedramcore_bankmachine1_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine1_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7])) begin
- litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine1_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | litedramcore_bankmachine1_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re);
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine1_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine1_next_state <= 4'd0;
- litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- if (litedramcore_bankmachine1_cmd_ready) begin
- litedramcore_bankmachine1_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- if (litedramcore_bankmachine1_cmd_ready) begin
- litedramcore_bankmachine1_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine1_refresh_req)) begin
- litedramcore_bankmachine1_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine1_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine1_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine1_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine1_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- litedramcore_bankmachine1_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin
- litedramcore_bankmachine1_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine1_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine1_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine1_twtpcon_ready) begin
- litedramcore_bankmachine1_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_row_open <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_row_close <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- litedramcore_bankmachine1_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine1_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine1_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine2_req_valid;
-assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine2_req_we;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine2_req_addr;
-assign litedramcore_bankmachine2_cmd_buffer_sink_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine2_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine2_cmd_buffer_sink_first = litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine2_cmd_buffer_sink_last = litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine2_cmd_buffer_sink_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine2_cmd_buffer_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid);
-assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine2_cmd_buffer_source_valid);
-assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]);
+ litedramcore_bankmachine1_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine1_source_valid & litedramcore_bankmachine1_source_source_valid)) begin
+ if ((litedramcore_bankmachine1_source_payload_addr[20:7] != litedramcore_bankmachine1_source_source_payload_addr[20:7])) begin
+ litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine1_syncfifo1_din = {litedramcore_bankmachine1_fifo_in_last, litedramcore_bankmachine1_fifo_in_first, litedramcore_bankmachine1_fifo_in_payload_addr, litedramcore_bankmachine1_fifo_in_payload_we};
+assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout;
+assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout;
+assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout;
+assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout;
+assign litedramcore_bankmachine1_sink_ready = litedramcore_bankmachine1_syncfifo1_writable;
+assign litedramcore_bankmachine1_syncfifo1_we = litedramcore_bankmachine1_sink_valid;
+assign litedramcore_bankmachine1_fifo_in_first = litedramcore_bankmachine1_sink_first;
+assign litedramcore_bankmachine1_fifo_in_last = litedramcore_bankmachine1_sink_last;
+assign litedramcore_bankmachine1_fifo_in_payload_we = litedramcore_bankmachine1_sink_payload_we;
+assign litedramcore_bankmachine1_fifo_in_payload_addr = litedramcore_bankmachine1_sink_payload_addr;
+assign litedramcore_bankmachine1_source_valid = litedramcore_bankmachine1_syncfifo1_readable;
+assign litedramcore_bankmachine1_source_first = litedramcore_bankmachine1_fifo_out_first;
+assign litedramcore_bankmachine1_source_last = litedramcore_bankmachine1_fifo_out_last;
+assign litedramcore_bankmachine1_source_payload_we = litedramcore_bankmachine1_fifo_out_payload_we;
+assign litedramcore_bankmachine1_source_payload_addr = litedramcore_bankmachine1_fifo_out_payload_addr;
+assign litedramcore_bankmachine1_syncfifo1_re = litedramcore_bankmachine1_source_ready;
+always @(*) begin
+ litedramcore_bankmachine1_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine1_replace) begin
+ litedramcore_bankmachine1_wrport_adr <= (litedramcore_bankmachine1_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine1_wrport_adr <= litedramcore_bankmachine1_produce;
+ end
+end
+assign litedramcore_bankmachine1_wrport_dat_w = litedramcore_bankmachine1_syncfifo1_din;
+assign litedramcore_bankmachine1_wrport_we = (litedramcore_bankmachine1_syncfifo1_we & (litedramcore_bankmachine1_syncfifo1_writable | litedramcore_bankmachine1_replace));
+assign litedramcore_bankmachine1_do_read = (litedramcore_bankmachine1_syncfifo1_readable & litedramcore_bankmachine1_syncfifo1_re);
+assign litedramcore_bankmachine1_rdport_adr = litedramcore_bankmachine1_consume;
+assign litedramcore_bankmachine1_syncfifo1_dout = litedramcore_bankmachine1_rdport_dat_r;
+assign litedramcore_bankmachine1_syncfifo1_writable = (litedramcore_bankmachine1_level != 5'd16);
+assign litedramcore_bankmachine1_syncfifo1_readable = (litedramcore_bankmachine1_level != 1'd0);
+assign litedramcore_bankmachine1_pipe_valid_sink_ready = ((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready);
+assign litedramcore_bankmachine1_pipe_valid_sink_valid = litedramcore_bankmachine1_sink_sink_valid;
+assign litedramcore_bankmachine1_sink_sink_ready = litedramcore_bankmachine1_pipe_valid_sink_ready;
+assign litedramcore_bankmachine1_pipe_valid_sink_first = litedramcore_bankmachine1_sink_sink_first;
+assign litedramcore_bankmachine1_pipe_valid_sink_last = litedramcore_bankmachine1_sink_sink_last;
+assign litedramcore_bankmachine1_pipe_valid_sink_payload_we = litedramcore_bankmachine1_sink_sink_payload_we;
+assign litedramcore_bankmachine1_pipe_valid_sink_payload_addr = litedramcore_bankmachine1_sink_sink_payload_addr;
+assign litedramcore_bankmachine1_source_source_valid = litedramcore_bankmachine1_pipe_valid_source_valid;
+assign litedramcore_bankmachine1_pipe_valid_source_ready = litedramcore_bankmachine1_source_source_ready;
+assign litedramcore_bankmachine1_source_source_first = litedramcore_bankmachine1_pipe_valid_source_first;
+assign litedramcore_bankmachine1_source_source_last = litedramcore_bankmachine1_pipe_valid_source_last;
+assign litedramcore_bankmachine1_source_source_payload_we = litedramcore_bankmachine1_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine1_source_source_payload_addr = litedramcore_bankmachine1_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine1_next_state <= 4'd0;
+ litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ if (litedramcore_bankmachine1_cmd_ready) begin
+ litedramcore_bankmachine1_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ if (litedramcore_bankmachine1_cmd_ready) begin
+ litedramcore_bankmachine1_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine1_refresh_req)) begin
+ litedramcore_bankmachine1_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine1_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine1_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine1_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine1_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ litedramcore_bankmachine1_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin
+ litedramcore_bankmachine1_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine1_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine1_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if (litedramcore_bankmachine1_source_source_payload_we) begin
+ litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if (litedramcore_bankmachine1_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if (litedramcore_bankmachine1_source_source_payload_we) begin
+ litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if (litedramcore_bankmachine1_source_source_payload_we) begin
+ litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if (litedramcore_bankmachine1_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine1_twtpcon_ready) begin
+ litedramcore_bankmachine1_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_row_open <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ litedramcore_bankmachine1_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_row_close <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ litedramcore_bankmachine1_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine1_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine1_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+assign litedramcore_bankmachine2_sink_valid = litedramcore_bankmachine2_req_valid;
+assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_sink_ready;
+assign litedramcore_bankmachine2_sink_payload_we = litedramcore_bankmachine2_req_we;
+assign litedramcore_bankmachine2_sink_payload_addr = litedramcore_bankmachine2_req_addr;
+assign litedramcore_bankmachine2_sink_sink_valid = litedramcore_bankmachine2_source_valid;
+assign litedramcore_bankmachine2_source_ready = litedramcore_bankmachine2_sink_sink_ready;
+assign litedramcore_bankmachine2_sink_sink_first = litedramcore_bankmachine2_source_first;
+assign litedramcore_bankmachine2_sink_sink_last = litedramcore_bankmachine2_source_last;
+assign litedramcore_bankmachine2_sink_sink_payload_we = litedramcore_bankmachine2_source_payload_we;
+assign litedramcore_bankmachine2_sink_sink_payload_addr = litedramcore_bankmachine2_source_payload_addr;
+assign litedramcore_bankmachine2_source_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid);
+assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_source_valid | litedramcore_bankmachine2_source_source_valid);
+assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_source_source_payload_addr[20:7]);
assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
always @(*) begin
- litedramcore_bankmachine2_cmd_payload_a <= 14'd0;
- if (litedramcore_bankmachine2_row_col_n_addr_sel) begin
- litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7];
- end else begin
- litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine2_cmd_payload_a <= 14'd0;
+ if (litedramcore_bankmachine2_row_col_n_addr_sel) begin
+ litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_source_source_payload_addr[20:7];
+ end else begin
+ litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write);
assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
always @(*) begin
- litedramcore_bankmachine2_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine2_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7])) begin
- litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine2_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | litedramcore_bankmachine2_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re);
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine2_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine2_next_state <= 4'd0;
- litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- if (litedramcore_bankmachine2_cmd_ready) begin
- litedramcore_bankmachine2_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- if (litedramcore_bankmachine2_cmd_ready) begin
- litedramcore_bankmachine2_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine2_refresh_req)) begin
- litedramcore_bankmachine2_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine2_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine2_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine2_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine2_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- litedramcore_bankmachine2_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin
- litedramcore_bankmachine2_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine2_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine2_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine2_twtpcon_ready) begin
- litedramcore_bankmachine2_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- litedramcore_bankmachine2_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_row_open <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_row_close <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- litedramcore_bankmachine2_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine2_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine2_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine3_req_valid;
-assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine3_req_we;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine3_req_addr;
-assign litedramcore_bankmachine3_cmd_buffer_sink_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine3_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine3_cmd_buffer_sink_first = litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine3_cmd_buffer_sink_last = litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine3_cmd_buffer_sink_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine3_cmd_buffer_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid);
-assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine3_cmd_buffer_source_valid);
-assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]);
+ litedramcore_bankmachine2_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine2_source_valid & litedramcore_bankmachine2_source_source_valid)) begin
+ if ((litedramcore_bankmachine2_source_payload_addr[20:7] != litedramcore_bankmachine2_source_source_payload_addr[20:7])) begin
+ litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine2_syncfifo2_din = {litedramcore_bankmachine2_fifo_in_last, litedramcore_bankmachine2_fifo_in_first, litedramcore_bankmachine2_fifo_in_payload_addr, litedramcore_bankmachine2_fifo_in_payload_we};
+assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout;
+assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout;
+assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout;
+assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout;
+assign litedramcore_bankmachine2_sink_ready = litedramcore_bankmachine2_syncfifo2_writable;
+assign litedramcore_bankmachine2_syncfifo2_we = litedramcore_bankmachine2_sink_valid;
+assign litedramcore_bankmachine2_fifo_in_first = litedramcore_bankmachine2_sink_first;
+assign litedramcore_bankmachine2_fifo_in_last = litedramcore_bankmachine2_sink_last;
+assign litedramcore_bankmachine2_fifo_in_payload_we = litedramcore_bankmachine2_sink_payload_we;
+assign litedramcore_bankmachine2_fifo_in_payload_addr = litedramcore_bankmachine2_sink_payload_addr;
+assign litedramcore_bankmachine2_source_valid = litedramcore_bankmachine2_syncfifo2_readable;
+assign litedramcore_bankmachine2_source_first = litedramcore_bankmachine2_fifo_out_first;
+assign litedramcore_bankmachine2_source_last = litedramcore_bankmachine2_fifo_out_last;
+assign litedramcore_bankmachine2_source_payload_we = litedramcore_bankmachine2_fifo_out_payload_we;
+assign litedramcore_bankmachine2_source_payload_addr = litedramcore_bankmachine2_fifo_out_payload_addr;
+assign litedramcore_bankmachine2_syncfifo2_re = litedramcore_bankmachine2_source_ready;
+always @(*) begin
+ litedramcore_bankmachine2_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine2_replace) begin
+ litedramcore_bankmachine2_wrport_adr <= (litedramcore_bankmachine2_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine2_wrport_adr <= litedramcore_bankmachine2_produce;
+ end
+end
+assign litedramcore_bankmachine2_wrport_dat_w = litedramcore_bankmachine2_syncfifo2_din;
+assign litedramcore_bankmachine2_wrport_we = (litedramcore_bankmachine2_syncfifo2_we & (litedramcore_bankmachine2_syncfifo2_writable | litedramcore_bankmachine2_replace));
+assign litedramcore_bankmachine2_do_read = (litedramcore_bankmachine2_syncfifo2_readable & litedramcore_bankmachine2_syncfifo2_re);
+assign litedramcore_bankmachine2_rdport_adr = litedramcore_bankmachine2_consume;
+assign litedramcore_bankmachine2_syncfifo2_dout = litedramcore_bankmachine2_rdport_dat_r;
+assign litedramcore_bankmachine2_syncfifo2_writable = (litedramcore_bankmachine2_level != 5'd16);
+assign litedramcore_bankmachine2_syncfifo2_readable = (litedramcore_bankmachine2_level != 1'd0);
+assign litedramcore_bankmachine2_pipe_valid_sink_ready = ((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready);
+assign litedramcore_bankmachine2_pipe_valid_sink_valid = litedramcore_bankmachine2_sink_sink_valid;
+assign litedramcore_bankmachine2_sink_sink_ready = litedramcore_bankmachine2_pipe_valid_sink_ready;
+assign litedramcore_bankmachine2_pipe_valid_sink_first = litedramcore_bankmachine2_sink_sink_first;
+assign litedramcore_bankmachine2_pipe_valid_sink_last = litedramcore_bankmachine2_sink_sink_last;
+assign litedramcore_bankmachine2_pipe_valid_sink_payload_we = litedramcore_bankmachine2_sink_sink_payload_we;
+assign litedramcore_bankmachine2_pipe_valid_sink_payload_addr = litedramcore_bankmachine2_sink_sink_payload_addr;
+assign litedramcore_bankmachine2_source_source_valid = litedramcore_bankmachine2_pipe_valid_source_valid;
+assign litedramcore_bankmachine2_pipe_valid_source_ready = litedramcore_bankmachine2_source_source_ready;
+assign litedramcore_bankmachine2_source_source_first = litedramcore_bankmachine2_pipe_valid_source_first;
+assign litedramcore_bankmachine2_source_source_last = litedramcore_bankmachine2_pipe_valid_source_last;
+assign litedramcore_bankmachine2_source_source_payload_we = litedramcore_bankmachine2_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine2_source_source_payload_addr = litedramcore_bankmachine2_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine2_next_state <= 4'd0;
+ litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ if (litedramcore_bankmachine2_cmd_ready) begin
+ litedramcore_bankmachine2_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ if (litedramcore_bankmachine2_cmd_ready) begin
+ litedramcore_bankmachine2_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine2_refresh_req)) begin
+ litedramcore_bankmachine2_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine2_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine2_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine2_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine2_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ litedramcore_bankmachine2_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin
+ litedramcore_bankmachine2_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine2_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine2_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if (litedramcore_bankmachine2_source_source_payload_we) begin
+ litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if (litedramcore_bankmachine2_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if (litedramcore_bankmachine2_source_source_payload_we) begin
+ litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if (litedramcore_bankmachine2_source_source_payload_we) begin
+ litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if (litedramcore_bankmachine2_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine2_twtpcon_ready) begin
+ litedramcore_bankmachine2_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_row_open <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ litedramcore_bankmachine2_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_row_close <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ litedramcore_bankmachine2_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine2_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine2_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+assign litedramcore_bankmachine3_sink_valid = litedramcore_bankmachine3_req_valid;
+assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_sink_ready;
+assign litedramcore_bankmachine3_sink_payload_we = litedramcore_bankmachine3_req_we;
+assign litedramcore_bankmachine3_sink_payload_addr = litedramcore_bankmachine3_req_addr;
+assign litedramcore_bankmachine3_sink_sink_valid = litedramcore_bankmachine3_source_valid;
+assign litedramcore_bankmachine3_source_ready = litedramcore_bankmachine3_sink_sink_ready;
+assign litedramcore_bankmachine3_sink_sink_first = litedramcore_bankmachine3_source_first;
+assign litedramcore_bankmachine3_sink_sink_last = litedramcore_bankmachine3_source_last;
+assign litedramcore_bankmachine3_sink_sink_payload_we = litedramcore_bankmachine3_source_payload_we;
+assign litedramcore_bankmachine3_sink_sink_payload_addr = litedramcore_bankmachine3_source_payload_addr;
+assign litedramcore_bankmachine3_source_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid);
+assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_source_valid | litedramcore_bankmachine3_source_source_valid);
+assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_source_source_payload_addr[20:7]);
assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
always @(*) begin
- litedramcore_bankmachine3_cmd_payload_a <= 14'd0;
- if (litedramcore_bankmachine3_row_col_n_addr_sel) begin
- litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7];
- end else begin
- litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine3_cmd_payload_a <= 14'd0;
+ if (litedramcore_bankmachine3_row_col_n_addr_sel) begin
+ litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_source_source_payload_addr[20:7];
+ end else begin
+ litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write);
assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
always @(*) begin
- litedramcore_bankmachine3_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine3_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7])) begin
- litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine3_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | litedramcore_bankmachine3_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re);
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine3_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine3_next_state <= 4'd0;
- litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- if (litedramcore_bankmachine3_cmd_ready) begin
- litedramcore_bankmachine3_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- if (litedramcore_bankmachine3_cmd_ready) begin
- litedramcore_bankmachine3_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine3_refresh_req)) begin
- litedramcore_bankmachine3_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine3_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine3_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine3_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine3_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- litedramcore_bankmachine3_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin
- litedramcore_bankmachine3_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine3_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine3_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine3_twtpcon_ready) begin
- litedramcore_bankmachine3_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- litedramcore_bankmachine3_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_row_open <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_row_close <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- litedramcore_bankmachine3_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine3_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine3_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine4_req_valid;
-assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine4_req_we;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine4_req_addr;
-assign litedramcore_bankmachine4_cmd_buffer_sink_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine4_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine4_cmd_buffer_sink_first = litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine4_cmd_buffer_sink_last = litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine4_cmd_buffer_sink_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine4_cmd_buffer_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid);
-assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine4_cmd_buffer_source_valid);
-assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]);
+ litedramcore_bankmachine3_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine3_source_valid & litedramcore_bankmachine3_source_source_valid)) begin
+ if ((litedramcore_bankmachine3_source_payload_addr[20:7] != litedramcore_bankmachine3_source_source_payload_addr[20:7])) begin
+ litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine3_syncfifo3_din = {litedramcore_bankmachine3_fifo_in_last, litedramcore_bankmachine3_fifo_in_first, litedramcore_bankmachine3_fifo_in_payload_addr, litedramcore_bankmachine3_fifo_in_payload_we};
+assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout;
+assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout;
+assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout;
+assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout;
+assign litedramcore_bankmachine3_sink_ready = litedramcore_bankmachine3_syncfifo3_writable;
+assign litedramcore_bankmachine3_syncfifo3_we = litedramcore_bankmachine3_sink_valid;
+assign litedramcore_bankmachine3_fifo_in_first = litedramcore_bankmachine3_sink_first;
+assign litedramcore_bankmachine3_fifo_in_last = litedramcore_bankmachine3_sink_last;
+assign litedramcore_bankmachine3_fifo_in_payload_we = litedramcore_bankmachine3_sink_payload_we;
+assign litedramcore_bankmachine3_fifo_in_payload_addr = litedramcore_bankmachine3_sink_payload_addr;
+assign litedramcore_bankmachine3_source_valid = litedramcore_bankmachine3_syncfifo3_readable;
+assign litedramcore_bankmachine3_source_first = litedramcore_bankmachine3_fifo_out_first;
+assign litedramcore_bankmachine3_source_last = litedramcore_bankmachine3_fifo_out_last;
+assign litedramcore_bankmachine3_source_payload_we = litedramcore_bankmachine3_fifo_out_payload_we;
+assign litedramcore_bankmachine3_source_payload_addr = litedramcore_bankmachine3_fifo_out_payload_addr;
+assign litedramcore_bankmachine3_syncfifo3_re = litedramcore_bankmachine3_source_ready;
+always @(*) begin
+ litedramcore_bankmachine3_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine3_replace) begin
+ litedramcore_bankmachine3_wrport_adr <= (litedramcore_bankmachine3_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine3_wrport_adr <= litedramcore_bankmachine3_produce;
+ end
+end
+assign litedramcore_bankmachine3_wrport_dat_w = litedramcore_bankmachine3_syncfifo3_din;
+assign litedramcore_bankmachine3_wrport_we = (litedramcore_bankmachine3_syncfifo3_we & (litedramcore_bankmachine3_syncfifo3_writable | litedramcore_bankmachine3_replace));
+assign litedramcore_bankmachine3_do_read = (litedramcore_bankmachine3_syncfifo3_readable & litedramcore_bankmachine3_syncfifo3_re);
+assign litedramcore_bankmachine3_rdport_adr = litedramcore_bankmachine3_consume;
+assign litedramcore_bankmachine3_syncfifo3_dout = litedramcore_bankmachine3_rdport_dat_r;
+assign litedramcore_bankmachine3_syncfifo3_writable = (litedramcore_bankmachine3_level != 5'd16);
+assign litedramcore_bankmachine3_syncfifo3_readable = (litedramcore_bankmachine3_level != 1'd0);
+assign litedramcore_bankmachine3_pipe_valid_sink_ready = ((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready);
+assign litedramcore_bankmachine3_pipe_valid_sink_valid = litedramcore_bankmachine3_sink_sink_valid;
+assign litedramcore_bankmachine3_sink_sink_ready = litedramcore_bankmachine3_pipe_valid_sink_ready;
+assign litedramcore_bankmachine3_pipe_valid_sink_first = litedramcore_bankmachine3_sink_sink_first;
+assign litedramcore_bankmachine3_pipe_valid_sink_last = litedramcore_bankmachine3_sink_sink_last;
+assign litedramcore_bankmachine3_pipe_valid_sink_payload_we = litedramcore_bankmachine3_sink_sink_payload_we;
+assign litedramcore_bankmachine3_pipe_valid_sink_payload_addr = litedramcore_bankmachine3_sink_sink_payload_addr;
+assign litedramcore_bankmachine3_source_source_valid = litedramcore_bankmachine3_pipe_valid_source_valid;
+assign litedramcore_bankmachine3_pipe_valid_source_ready = litedramcore_bankmachine3_source_source_ready;
+assign litedramcore_bankmachine3_source_source_first = litedramcore_bankmachine3_pipe_valid_source_first;
+assign litedramcore_bankmachine3_source_source_last = litedramcore_bankmachine3_pipe_valid_source_last;
+assign litedramcore_bankmachine3_source_source_payload_we = litedramcore_bankmachine3_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine3_source_source_payload_addr = litedramcore_bankmachine3_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine3_next_state <= 4'd0;
+ litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ if (litedramcore_bankmachine3_cmd_ready) begin
+ litedramcore_bankmachine3_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ if (litedramcore_bankmachine3_cmd_ready) begin
+ litedramcore_bankmachine3_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine3_refresh_req)) begin
+ litedramcore_bankmachine3_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine3_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine3_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine3_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine3_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ litedramcore_bankmachine3_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin
+ litedramcore_bankmachine3_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine3_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine3_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if (litedramcore_bankmachine3_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if (litedramcore_bankmachine3_source_source_payload_we) begin
+ litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if (litedramcore_bankmachine3_source_source_payload_we) begin
+ litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if (litedramcore_bankmachine3_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine3_twtpcon_ready) begin
+ litedramcore_bankmachine3_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_row_open <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ litedramcore_bankmachine3_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_row_close <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ litedramcore_bankmachine3_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine3_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine3_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if (litedramcore_bankmachine3_source_source_payload_we) begin
+ litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+assign litedramcore_bankmachine4_sink_valid = litedramcore_bankmachine4_req_valid;
+assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_sink_ready;
+assign litedramcore_bankmachine4_sink_payload_we = litedramcore_bankmachine4_req_we;
+assign litedramcore_bankmachine4_sink_payload_addr = litedramcore_bankmachine4_req_addr;
+assign litedramcore_bankmachine4_sink_sink_valid = litedramcore_bankmachine4_source_valid;
+assign litedramcore_bankmachine4_source_ready = litedramcore_bankmachine4_sink_sink_ready;
+assign litedramcore_bankmachine4_sink_sink_first = litedramcore_bankmachine4_source_first;
+assign litedramcore_bankmachine4_sink_sink_last = litedramcore_bankmachine4_source_last;
+assign litedramcore_bankmachine4_sink_sink_payload_we = litedramcore_bankmachine4_source_payload_we;
+assign litedramcore_bankmachine4_sink_sink_payload_addr = litedramcore_bankmachine4_source_payload_addr;
+assign litedramcore_bankmachine4_source_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid);
+assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_source_valid | litedramcore_bankmachine4_source_source_valid);
+assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_source_source_payload_addr[20:7]);
assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
always @(*) begin
- litedramcore_bankmachine4_cmd_payload_a <= 14'd0;
- if (litedramcore_bankmachine4_row_col_n_addr_sel) begin
- litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7];
- end else begin
- litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine4_cmd_payload_a <= 14'd0;
+ if (litedramcore_bankmachine4_row_col_n_addr_sel) begin
+ litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_source_source_payload_addr[20:7];
+ end else begin
+ litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write);
assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
always @(*) begin
- litedramcore_bankmachine4_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine4_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7])) begin
- litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine4_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | litedramcore_bankmachine4_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re);
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine4_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine4_next_state <= 4'd0;
- litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- if (litedramcore_bankmachine4_cmd_ready) begin
- litedramcore_bankmachine4_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- if (litedramcore_bankmachine4_cmd_ready) begin
- litedramcore_bankmachine4_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine4_refresh_req)) begin
- litedramcore_bankmachine4_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine4_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine4_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine4_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine4_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- litedramcore_bankmachine4_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin
- litedramcore_bankmachine4_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine4_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine4_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine4_twtpcon_ready) begin
- litedramcore_bankmachine4_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- litedramcore_bankmachine4_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_row_open <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_row_close <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- litedramcore_bankmachine4_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine4_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine4_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine5_req_valid;
-assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine5_req_we;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine5_req_addr;
-assign litedramcore_bankmachine5_cmd_buffer_sink_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine5_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine5_cmd_buffer_sink_first = litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine5_cmd_buffer_sink_last = litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine5_cmd_buffer_sink_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine5_cmd_buffer_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid);
-assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine5_cmd_buffer_source_valid);
-assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]);
+ litedramcore_bankmachine4_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine4_source_valid & litedramcore_bankmachine4_source_source_valid)) begin
+ if ((litedramcore_bankmachine4_source_payload_addr[20:7] != litedramcore_bankmachine4_source_source_payload_addr[20:7])) begin
+ litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine4_syncfifo4_din = {litedramcore_bankmachine4_fifo_in_last, litedramcore_bankmachine4_fifo_in_first, litedramcore_bankmachine4_fifo_in_payload_addr, litedramcore_bankmachine4_fifo_in_payload_we};
+assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout;
+assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout;
+assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout;
+assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout;
+assign litedramcore_bankmachine4_sink_ready = litedramcore_bankmachine4_syncfifo4_writable;
+assign litedramcore_bankmachine4_syncfifo4_we = litedramcore_bankmachine4_sink_valid;
+assign litedramcore_bankmachine4_fifo_in_first = litedramcore_bankmachine4_sink_first;
+assign litedramcore_bankmachine4_fifo_in_last = litedramcore_bankmachine4_sink_last;
+assign litedramcore_bankmachine4_fifo_in_payload_we = litedramcore_bankmachine4_sink_payload_we;
+assign litedramcore_bankmachine4_fifo_in_payload_addr = litedramcore_bankmachine4_sink_payload_addr;
+assign litedramcore_bankmachine4_source_valid = litedramcore_bankmachine4_syncfifo4_readable;
+assign litedramcore_bankmachine4_source_first = litedramcore_bankmachine4_fifo_out_first;
+assign litedramcore_bankmachine4_source_last = litedramcore_bankmachine4_fifo_out_last;
+assign litedramcore_bankmachine4_source_payload_we = litedramcore_bankmachine4_fifo_out_payload_we;
+assign litedramcore_bankmachine4_source_payload_addr = litedramcore_bankmachine4_fifo_out_payload_addr;
+assign litedramcore_bankmachine4_syncfifo4_re = litedramcore_bankmachine4_source_ready;
+always @(*) begin
+ litedramcore_bankmachine4_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine4_replace) begin
+ litedramcore_bankmachine4_wrport_adr <= (litedramcore_bankmachine4_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine4_wrport_adr <= litedramcore_bankmachine4_produce;
+ end
+end
+assign litedramcore_bankmachine4_wrport_dat_w = litedramcore_bankmachine4_syncfifo4_din;
+assign litedramcore_bankmachine4_wrport_we = (litedramcore_bankmachine4_syncfifo4_we & (litedramcore_bankmachine4_syncfifo4_writable | litedramcore_bankmachine4_replace));
+assign litedramcore_bankmachine4_do_read = (litedramcore_bankmachine4_syncfifo4_readable & litedramcore_bankmachine4_syncfifo4_re);
+assign litedramcore_bankmachine4_rdport_adr = litedramcore_bankmachine4_consume;
+assign litedramcore_bankmachine4_syncfifo4_dout = litedramcore_bankmachine4_rdport_dat_r;
+assign litedramcore_bankmachine4_syncfifo4_writable = (litedramcore_bankmachine4_level != 5'd16);
+assign litedramcore_bankmachine4_syncfifo4_readable = (litedramcore_bankmachine4_level != 1'd0);
+assign litedramcore_bankmachine4_pipe_valid_sink_ready = ((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready);
+assign litedramcore_bankmachine4_pipe_valid_sink_valid = litedramcore_bankmachine4_sink_sink_valid;
+assign litedramcore_bankmachine4_sink_sink_ready = litedramcore_bankmachine4_pipe_valid_sink_ready;
+assign litedramcore_bankmachine4_pipe_valid_sink_first = litedramcore_bankmachine4_sink_sink_first;
+assign litedramcore_bankmachine4_pipe_valid_sink_last = litedramcore_bankmachine4_sink_sink_last;
+assign litedramcore_bankmachine4_pipe_valid_sink_payload_we = litedramcore_bankmachine4_sink_sink_payload_we;
+assign litedramcore_bankmachine4_pipe_valid_sink_payload_addr = litedramcore_bankmachine4_sink_sink_payload_addr;
+assign litedramcore_bankmachine4_source_source_valid = litedramcore_bankmachine4_pipe_valid_source_valid;
+assign litedramcore_bankmachine4_pipe_valid_source_ready = litedramcore_bankmachine4_source_source_ready;
+assign litedramcore_bankmachine4_source_source_first = litedramcore_bankmachine4_pipe_valid_source_first;
+assign litedramcore_bankmachine4_source_source_last = litedramcore_bankmachine4_pipe_valid_source_last;
+assign litedramcore_bankmachine4_source_source_payload_we = litedramcore_bankmachine4_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine4_source_source_payload_addr = litedramcore_bankmachine4_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine4_next_state <= 4'd0;
+ litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ if (litedramcore_bankmachine4_cmd_ready) begin
+ litedramcore_bankmachine4_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ if (litedramcore_bankmachine4_cmd_ready) begin
+ litedramcore_bankmachine4_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine4_refresh_req)) begin
+ litedramcore_bankmachine4_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine4_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine4_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine4_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine4_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ litedramcore_bankmachine4_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin
+ litedramcore_bankmachine4_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine4_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine4_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if (litedramcore_bankmachine4_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine4_twtpcon_ready) begin
+ litedramcore_bankmachine4_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_row_open <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ litedramcore_bankmachine4_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ litedramcore_bankmachine4_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ litedramcore_bankmachine4_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_row_close <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ litedramcore_bankmachine4_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine4_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine4_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if (litedramcore_bankmachine4_source_source_payload_we) begin
+ litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if (litedramcore_bankmachine4_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if (litedramcore_bankmachine4_source_source_payload_we) begin
+ litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if (litedramcore_bankmachine4_source_source_payload_we) begin
+ litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+assign litedramcore_bankmachine5_sink_valid = litedramcore_bankmachine5_req_valid;
+assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_sink_ready;
+assign litedramcore_bankmachine5_sink_payload_we = litedramcore_bankmachine5_req_we;
+assign litedramcore_bankmachine5_sink_payload_addr = litedramcore_bankmachine5_req_addr;
+assign litedramcore_bankmachine5_sink_sink_valid = litedramcore_bankmachine5_source_valid;
+assign litedramcore_bankmachine5_source_ready = litedramcore_bankmachine5_sink_sink_ready;
+assign litedramcore_bankmachine5_sink_sink_first = litedramcore_bankmachine5_source_first;
+assign litedramcore_bankmachine5_sink_sink_last = litedramcore_bankmachine5_source_last;
+assign litedramcore_bankmachine5_sink_sink_payload_we = litedramcore_bankmachine5_source_payload_we;
+assign litedramcore_bankmachine5_sink_sink_payload_addr = litedramcore_bankmachine5_source_payload_addr;
+assign litedramcore_bankmachine5_source_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid);
+assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_source_valid | litedramcore_bankmachine5_source_source_valid);
+assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_source_source_payload_addr[20:7]);
assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
always @(*) begin
- litedramcore_bankmachine5_cmd_payload_a <= 14'd0;
- if (litedramcore_bankmachine5_row_col_n_addr_sel) begin
- litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7];
- end else begin
- litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine5_cmd_payload_a <= 14'd0;
+ if (litedramcore_bankmachine5_row_col_n_addr_sel) begin
+ litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_source_source_payload_addr[20:7];
+ end else begin
+ litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write);
assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
always @(*) begin
- litedramcore_bankmachine5_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine5_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7])) begin
- litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine5_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | litedramcore_bankmachine5_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re);
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine5_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine5_next_state <= 4'd0;
- litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- if (litedramcore_bankmachine5_cmd_ready) begin
- litedramcore_bankmachine5_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- if (litedramcore_bankmachine5_cmd_ready) begin
- litedramcore_bankmachine5_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine5_refresh_req)) begin
- litedramcore_bankmachine5_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine5_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine5_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine5_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine5_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- litedramcore_bankmachine5_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin
- litedramcore_bankmachine5_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine5_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine5_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine5_twtpcon_ready) begin
- litedramcore_bankmachine5_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_row_open <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_row_close <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- litedramcore_bankmachine5_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine5_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine5_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine6_req_valid;
-assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine6_req_we;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine6_req_addr;
-assign litedramcore_bankmachine6_cmd_buffer_sink_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine6_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine6_cmd_buffer_sink_first = litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine6_cmd_buffer_sink_last = litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine6_cmd_buffer_sink_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine6_cmd_buffer_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid);
-assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine6_cmd_buffer_source_valid);
-assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]);
+ litedramcore_bankmachine5_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine5_source_valid & litedramcore_bankmachine5_source_source_valid)) begin
+ if ((litedramcore_bankmachine5_source_payload_addr[20:7] != litedramcore_bankmachine5_source_source_payload_addr[20:7])) begin
+ litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine5_syncfifo5_din = {litedramcore_bankmachine5_fifo_in_last, litedramcore_bankmachine5_fifo_in_first, litedramcore_bankmachine5_fifo_in_payload_addr, litedramcore_bankmachine5_fifo_in_payload_we};
+assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout;
+assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout;
+assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout;
+assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout;
+assign litedramcore_bankmachine5_sink_ready = litedramcore_bankmachine5_syncfifo5_writable;
+assign litedramcore_bankmachine5_syncfifo5_we = litedramcore_bankmachine5_sink_valid;
+assign litedramcore_bankmachine5_fifo_in_first = litedramcore_bankmachine5_sink_first;
+assign litedramcore_bankmachine5_fifo_in_last = litedramcore_bankmachine5_sink_last;
+assign litedramcore_bankmachine5_fifo_in_payload_we = litedramcore_bankmachine5_sink_payload_we;
+assign litedramcore_bankmachine5_fifo_in_payload_addr = litedramcore_bankmachine5_sink_payload_addr;
+assign litedramcore_bankmachine5_source_valid = litedramcore_bankmachine5_syncfifo5_readable;
+assign litedramcore_bankmachine5_source_first = litedramcore_bankmachine5_fifo_out_first;
+assign litedramcore_bankmachine5_source_last = litedramcore_bankmachine5_fifo_out_last;
+assign litedramcore_bankmachine5_source_payload_we = litedramcore_bankmachine5_fifo_out_payload_we;
+assign litedramcore_bankmachine5_source_payload_addr = litedramcore_bankmachine5_fifo_out_payload_addr;
+assign litedramcore_bankmachine5_syncfifo5_re = litedramcore_bankmachine5_source_ready;
+always @(*) begin
+ litedramcore_bankmachine5_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine5_replace) begin
+ litedramcore_bankmachine5_wrport_adr <= (litedramcore_bankmachine5_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine5_wrport_adr <= litedramcore_bankmachine5_produce;
+ end
+end
+assign litedramcore_bankmachine5_wrport_dat_w = litedramcore_bankmachine5_syncfifo5_din;
+assign litedramcore_bankmachine5_wrport_we = (litedramcore_bankmachine5_syncfifo5_we & (litedramcore_bankmachine5_syncfifo5_writable | litedramcore_bankmachine5_replace));
+assign litedramcore_bankmachine5_do_read = (litedramcore_bankmachine5_syncfifo5_readable & litedramcore_bankmachine5_syncfifo5_re);
+assign litedramcore_bankmachine5_rdport_adr = litedramcore_bankmachine5_consume;
+assign litedramcore_bankmachine5_syncfifo5_dout = litedramcore_bankmachine5_rdport_dat_r;
+assign litedramcore_bankmachine5_syncfifo5_writable = (litedramcore_bankmachine5_level != 5'd16);
+assign litedramcore_bankmachine5_syncfifo5_readable = (litedramcore_bankmachine5_level != 1'd0);
+assign litedramcore_bankmachine5_pipe_valid_sink_ready = ((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready);
+assign litedramcore_bankmachine5_pipe_valid_sink_valid = litedramcore_bankmachine5_sink_sink_valid;
+assign litedramcore_bankmachine5_sink_sink_ready = litedramcore_bankmachine5_pipe_valid_sink_ready;
+assign litedramcore_bankmachine5_pipe_valid_sink_first = litedramcore_bankmachine5_sink_sink_first;
+assign litedramcore_bankmachine5_pipe_valid_sink_last = litedramcore_bankmachine5_sink_sink_last;
+assign litedramcore_bankmachine5_pipe_valid_sink_payload_we = litedramcore_bankmachine5_sink_sink_payload_we;
+assign litedramcore_bankmachine5_pipe_valid_sink_payload_addr = litedramcore_bankmachine5_sink_sink_payload_addr;
+assign litedramcore_bankmachine5_source_source_valid = litedramcore_bankmachine5_pipe_valid_source_valid;
+assign litedramcore_bankmachine5_pipe_valid_source_ready = litedramcore_bankmachine5_source_source_ready;
+assign litedramcore_bankmachine5_source_source_first = litedramcore_bankmachine5_pipe_valid_source_first;
+assign litedramcore_bankmachine5_source_source_last = litedramcore_bankmachine5_pipe_valid_source_last;
+assign litedramcore_bankmachine5_source_source_payload_we = litedramcore_bankmachine5_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine5_source_source_payload_addr = litedramcore_bankmachine5_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine5_next_state <= 4'd0;
+ litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ if (litedramcore_bankmachine5_cmd_ready) begin
+ litedramcore_bankmachine5_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ if (litedramcore_bankmachine5_cmd_ready) begin
+ litedramcore_bankmachine5_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine5_refresh_req)) begin
+ litedramcore_bankmachine5_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine5_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine5_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine5_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine5_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ litedramcore_bankmachine5_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin
+ litedramcore_bankmachine5_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine5_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine5_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if (litedramcore_bankmachine5_source_source_payload_we) begin
+ litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if (litedramcore_bankmachine5_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if (litedramcore_bankmachine5_source_source_payload_we) begin
+ litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if (litedramcore_bankmachine5_source_source_payload_we) begin
+ litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if (litedramcore_bankmachine5_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine5_twtpcon_ready) begin
+ litedramcore_bankmachine5_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_row_open <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_row_close <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ litedramcore_bankmachine5_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine5_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine5_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+assign litedramcore_bankmachine6_sink_valid = litedramcore_bankmachine6_req_valid;
+assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_sink_ready;
+assign litedramcore_bankmachine6_sink_payload_we = litedramcore_bankmachine6_req_we;
+assign litedramcore_bankmachine6_sink_payload_addr = litedramcore_bankmachine6_req_addr;
+assign litedramcore_bankmachine6_sink_sink_valid = litedramcore_bankmachine6_source_valid;
+assign litedramcore_bankmachine6_source_ready = litedramcore_bankmachine6_sink_sink_ready;
+assign litedramcore_bankmachine6_sink_sink_first = litedramcore_bankmachine6_source_first;
+assign litedramcore_bankmachine6_sink_sink_last = litedramcore_bankmachine6_source_last;
+assign litedramcore_bankmachine6_sink_sink_payload_we = litedramcore_bankmachine6_source_payload_we;
+assign litedramcore_bankmachine6_sink_sink_payload_addr = litedramcore_bankmachine6_source_payload_addr;
+assign litedramcore_bankmachine6_source_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid);
+assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_source_valid | litedramcore_bankmachine6_source_source_valid);
+assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_source_source_payload_addr[20:7]);
assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
always @(*) begin
- litedramcore_bankmachine6_cmd_payload_a <= 14'd0;
- if (litedramcore_bankmachine6_row_col_n_addr_sel) begin
- litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7];
- end else begin
- litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine6_cmd_payload_a <= 14'd0;
+ if (litedramcore_bankmachine6_row_col_n_addr_sel) begin
+ litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_source_source_payload_addr[20:7];
+ end else begin
+ litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write);
assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
always @(*) begin
- litedramcore_bankmachine6_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine6_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7])) begin
- litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine6_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | litedramcore_bankmachine6_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re);
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine6_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine6_next_state <= 4'd0;
- litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- if (litedramcore_bankmachine6_cmd_ready) begin
- litedramcore_bankmachine6_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- if (litedramcore_bankmachine6_cmd_ready) begin
- litedramcore_bankmachine6_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine6_refresh_req)) begin
- litedramcore_bankmachine6_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine6_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine6_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine6_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine6_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- litedramcore_bankmachine6_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin
- litedramcore_bankmachine6_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine6_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine6_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine6_twtpcon_ready) begin
- litedramcore_bankmachine6_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- litedramcore_bankmachine6_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_row_open <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_row_close <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- litedramcore_bankmachine6_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine6_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine6_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine7_req_valid;
-assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine7_req_we;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine7_req_addr;
-assign litedramcore_bankmachine7_cmd_buffer_sink_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine7_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine7_cmd_buffer_sink_first = litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine7_cmd_buffer_sink_last = litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine7_cmd_buffer_sink_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine7_cmd_buffer_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid);
-assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine7_cmd_buffer_source_valid);
-assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]);
+ litedramcore_bankmachine6_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine6_source_valid & litedramcore_bankmachine6_source_source_valid)) begin
+ if ((litedramcore_bankmachine6_source_payload_addr[20:7] != litedramcore_bankmachine6_source_source_payload_addr[20:7])) begin
+ litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine6_syncfifo6_din = {litedramcore_bankmachine6_fifo_in_last, litedramcore_bankmachine6_fifo_in_first, litedramcore_bankmachine6_fifo_in_payload_addr, litedramcore_bankmachine6_fifo_in_payload_we};
+assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout;
+assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout;
+assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout;
+assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout;
+assign litedramcore_bankmachine6_sink_ready = litedramcore_bankmachine6_syncfifo6_writable;
+assign litedramcore_bankmachine6_syncfifo6_we = litedramcore_bankmachine6_sink_valid;
+assign litedramcore_bankmachine6_fifo_in_first = litedramcore_bankmachine6_sink_first;
+assign litedramcore_bankmachine6_fifo_in_last = litedramcore_bankmachine6_sink_last;
+assign litedramcore_bankmachine6_fifo_in_payload_we = litedramcore_bankmachine6_sink_payload_we;
+assign litedramcore_bankmachine6_fifo_in_payload_addr = litedramcore_bankmachine6_sink_payload_addr;
+assign litedramcore_bankmachine6_source_valid = litedramcore_bankmachine6_syncfifo6_readable;
+assign litedramcore_bankmachine6_source_first = litedramcore_bankmachine6_fifo_out_first;
+assign litedramcore_bankmachine6_source_last = litedramcore_bankmachine6_fifo_out_last;
+assign litedramcore_bankmachine6_source_payload_we = litedramcore_bankmachine6_fifo_out_payload_we;
+assign litedramcore_bankmachine6_source_payload_addr = litedramcore_bankmachine6_fifo_out_payload_addr;
+assign litedramcore_bankmachine6_syncfifo6_re = litedramcore_bankmachine6_source_ready;
+always @(*) begin
+ litedramcore_bankmachine6_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine6_replace) begin
+ litedramcore_bankmachine6_wrport_adr <= (litedramcore_bankmachine6_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine6_wrport_adr <= litedramcore_bankmachine6_produce;
+ end
+end
+assign litedramcore_bankmachine6_wrport_dat_w = litedramcore_bankmachine6_syncfifo6_din;
+assign litedramcore_bankmachine6_wrport_we = (litedramcore_bankmachine6_syncfifo6_we & (litedramcore_bankmachine6_syncfifo6_writable | litedramcore_bankmachine6_replace));
+assign litedramcore_bankmachine6_do_read = (litedramcore_bankmachine6_syncfifo6_readable & litedramcore_bankmachine6_syncfifo6_re);
+assign litedramcore_bankmachine6_rdport_adr = litedramcore_bankmachine6_consume;
+assign litedramcore_bankmachine6_syncfifo6_dout = litedramcore_bankmachine6_rdport_dat_r;
+assign litedramcore_bankmachine6_syncfifo6_writable = (litedramcore_bankmachine6_level != 5'd16);
+assign litedramcore_bankmachine6_syncfifo6_readable = (litedramcore_bankmachine6_level != 1'd0);
+assign litedramcore_bankmachine6_pipe_valid_sink_ready = ((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready);
+assign litedramcore_bankmachine6_pipe_valid_sink_valid = litedramcore_bankmachine6_sink_sink_valid;
+assign litedramcore_bankmachine6_sink_sink_ready = litedramcore_bankmachine6_pipe_valid_sink_ready;
+assign litedramcore_bankmachine6_pipe_valid_sink_first = litedramcore_bankmachine6_sink_sink_first;
+assign litedramcore_bankmachine6_pipe_valid_sink_last = litedramcore_bankmachine6_sink_sink_last;
+assign litedramcore_bankmachine6_pipe_valid_sink_payload_we = litedramcore_bankmachine6_sink_sink_payload_we;
+assign litedramcore_bankmachine6_pipe_valid_sink_payload_addr = litedramcore_bankmachine6_sink_sink_payload_addr;
+assign litedramcore_bankmachine6_source_source_valid = litedramcore_bankmachine6_pipe_valid_source_valid;
+assign litedramcore_bankmachine6_pipe_valid_source_ready = litedramcore_bankmachine6_source_source_ready;
+assign litedramcore_bankmachine6_source_source_first = litedramcore_bankmachine6_pipe_valid_source_first;
+assign litedramcore_bankmachine6_source_source_last = litedramcore_bankmachine6_pipe_valid_source_last;
+assign litedramcore_bankmachine6_source_source_payload_we = litedramcore_bankmachine6_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine6_source_source_payload_addr = litedramcore_bankmachine6_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine6_next_state <= 4'd0;
+ litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ if (litedramcore_bankmachine6_cmd_ready) begin
+ litedramcore_bankmachine6_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ if (litedramcore_bankmachine6_cmd_ready) begin
+ litedramcore_bankmachine6_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine6_refresh_req)) begin
+ litedramcore_bankmachine6_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine6_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine6_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine6_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine6_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ litedramcore_bankmachine6_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin
+ litedramcore_bankmachine6_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine6_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine6_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if (litedramcore_bankmachine6_source_source_payload_we) begin
+ litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if (litedramcore_bankmachine6_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if (litedramcore_bankmachine6_source_source_payload_we) begin
+ litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if (litedramcore_bankmachine6_source_source_payload_we) begin
+ litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if (litedramcore_bankmachine6_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine6_twtpcon_ready) begin
+ litedramcore_bankmachine6_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_row_open <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ litedramcore_bankmachine6_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_row_close <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ litedramcore_bankmachine6_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine6_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine6_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+assign litedramcore_bankmachine7_sink_valid = litedramcore_bankmachine7_req_valid;
+assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_sink_ready;
+assign litedramcore_bankmachine7_sink_payload_we = litedramcore_bankmachine7_req_we;
+assign litedramcore_bankmachine7_sink_payload_addr = litedramcore_bankmachine7_req_addr;
+assign litedramcore_bankmachine7_sink_sink_valid = litedramcore_bankmachine7_source_valid;
+assign litedramcore_bankmachine7_source_ready = litedramcore_bankmachine7_sink_sink_ready;
+assign litedramcore_bankmachine7_sink_sink_first = litedramcore_bankmachine7_source_first;
+assign litedramcore_bankmachine7_sink_sink_last = litedramcore_bankmachine7_source_last;
+assign litedramcore_bankmachine7_sink_sink_payload_we = litedramcore_bankmachine7_source_payload_we;
+assign litedramcore_bankmachine7_sink_sink_payload_addr = litedramcore_bankmachine7_source_payload_addr;
+assign litedramcore_bankmachine7_source_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid);
+assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_source_valid | litedramcore_bankmachine7_source_source_valid);
+assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_source_source_payload_addr[20:7]);
assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
always @(*) begin
- litedramcore_bankmachine7_cmd_payload_a <= 14'd0;
- if (litedramcore_bankmachine7_row_col_n_addr_sel) begin
- litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7];
- end else begin
- litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine7_cmd_payload_a <= 14'd0;
+ if (litedramcore_bankmachine7_row_col_n_addr_sel) begin
+ litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_source_source_payload_addr[20:7];
+ end else begin
+ litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write);
assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
always @(*) begin
- litedramcore_bankmachine7_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine7_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7])) begin
- litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine7_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | litedramcore_bankmachine7_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re);
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine7_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine7_next_state <= 4'd0;
- litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- if (litedramcore_bankmachine7_cmd_ready) begin
- litedramcore_bankmachine7_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- if (litedramcore_bankmachine7_cmd_ready) begin
- litedramcore_bankmachine7_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine7_refresh_req)) begin
- litedramcore_bankmachine7_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine7_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine7_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine7_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine7_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- litedramcore_bankmachine7_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin
- litedramcore_bankmachine7_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine7_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine7_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine7_twtpcon_ready) begin
- litedramcore_bankmachine7_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- litedramcore_bankmachine7_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_row_open <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_row_close <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- litedramcore_bankmachine7_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine7_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine7_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
+ litedramcore_bankmachine7_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine7_source_valid & litedramcore_bankmachine7_source_source_valid)) begin
+ if ((litedramcore_bankmachine7_source_payload_addr[20:7] != litedramcore_bankmachine7_source_source_payload_addr[20:7])) begin
+ litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine7_syncfifo7_din = {litedramcore_bankmachine7_fifo_in_last, litedramcore_bankmachine7_fifo_in_first, litedramcore_bankmachine7_fifo_in_payload_addr, litedramcore_bankmachine7_fifo_in_payload_we};
+assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout;
+assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout;
+assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout;
+assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout;
+assign litedramcore_bankmachine7_sink_ready = litedramcore_bankmachine7_syncfifo7_writable;
+assign litedramcore_bankmachine7_syncfifo7_we = litedramcore_bankmachine7_sink_valid;
+assign litedramcore_bankmachine7_fifo_in_first = litedramcore_bankmachine7_sink_first;
+assign litedramcore_bankmachine7_fifo_in_last = litedramcore_bankmachine7_sink_last;
+assign litedramcore_bankmachine7_fifo_in_payload_we = litedramcore_bankmachine7_sink_payload_we;
+assign litedramcore_bankmachine7_fifo_in_payload_addr = litedramcore_bankmachine7_sink_payload_addr;
+assign litedramcore_bankmachine7_source_valid = litedramcore_bankmachine7_syncfifo7_readable;
+assign litedramcore_bankmachine7_source_first = litedramcore_bankmachine7_fifo_out_first;
+assign litedramcore_bankmachine7_source_last = litedramcore_bankmachine7_fifo_out_last;
+assign litedramcore_bankmachine7_source_payload_we = litedramcore_bankmachine7_fifo_out_payload_we;
+assign litedramcore_bankmachine7_source_payload_addr = litedramcore_bankmachine7_fifo_out_payload_addr;
+assign litedramcore_bankmachine7_syncfifo7_re = litedramcore_bankmachine7_source_ready;
+always @(*) begin
+ litedramcore_bankmachine7_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine7_replace) begin
+ litedramcore_bankmachine7_wrport_adr <= (litedramcore_bankmachine7_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine7_wrport_adr <= litedramcore_bankmachine7_produce;
+ end
+end
+assign litedramcore_bankmachine7_wrport_dat_w = litedramcore_bankmachine7_syncfifo7_din;
+assign litedramcore_bankmachine7_wrport_we = (litedramcore_bankmachine7_syncfifo7_we & (litedramcore_bankmachine7_syncfifo7_writable | litedramcore_bankmachine7_replace));
+assign litedramcore_bankmachine7_do_read = (litedramcore_bankmachine7_syncfifo7_readable & litedramcore_bankmachine7_syncfifo7_re);
+assign litedramcore_bankmachine7_rdport_adr = litedramcore_bankmachine7_consume;
+assign litedramcore_bankmachine7_syncfifo7_dout = litedramcore_bankmachine7_rdport_dat_r;
+assign litedramcore_bankmachine7_syncfifo7_writable = (litedramcore_bankmachine7_level != 5'd16);
+assign litedramcore_bankmachine7_syncfifo7_readable = (litedramcore_bankmachine7_level != 1'd0);
+assign litedramcore_bankmachine7_pipe_valid_sink_ready = ((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready);
+assign litedramcore_bankmachine7_pipe_valid_sink_valid = litedramcore_bankmachine7_sink_sink_valid;
+assign litedramcore_bankmachine7_sink_sink_ready = litedramcore_bankmachine7_pipe_valid_sink_ready;
+assign litedramcore_bankmachine7_pipe_valid_sink_first = litedramcore_bankmachine7_sink_sink_first;
+assign litedramcore_bankmachine7_pipe_valid_sink_last = litedramcore_bankmachine7_sink_sink_last;
+assign litedramcore_bankmachine7_pipe_valid_sink_payload_we = litedramcore_bankmachine7_sink_sink_payload_we;
+assign litedramcore_bankmachine7_pipe_valid_sink_payload_addr = litedramcore_bankmachine7_sink_sink_payload_addr;
+assign litedramcore_bankmachine7_source_source_valid = litedramcore_bankmachine7_pipe_valid_source_valid;
+assign litedramcore_bankmachine7_pipe_valid_source_ready = litedramcore_bankmachine7_source_source_ready;
+assign litedramcore_bankmachine7_source_source_first = litedramcore_bankmachine7_pipe_valid_source_first;
+assign litedramcore_bankmachine7_source_source_last = litedramcore_bankmachine7_pipe_valid_source_last;
+assign litedramcore_bankmachine7_source_source_payload_we = litedramcore_bankmachine7_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine7_source_source_payload_addr = litedramcore_bankmachine7_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine7_next_state <= 4'd0;
+ litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ if (litedramcore_bankmachine7_cmd_ready) begin
+ litedramcore_bankmachine7_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ if (litedramcore_bankmachine7_cmd_ready) begin
+ litedramcore_bankmachine7_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine7_refresh_req)) begin
+ litedramcore_bankmachine7_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine7_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine7_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine7_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine7_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ litedramcore_bankmachine7_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin
+ litedramcore_bankmachine7_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine7_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine7_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if (litedramcore_bankmachine7_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if (litedramcore_bankmachine7_source_source_payload_we) begin
+ litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if (litedramcore_bankmachine7_source_source_payload_we) begin
+ litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if (litedramcore_bankmachine7_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine7_twtpcon_ready) begin
+ litedramcore_bankmachine7_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_row_open <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ litedramcore_bankmachine7_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_row_close <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ litedramcore_bankmachine7_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine7_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine7_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if (litedramcore_bankmachine7_source_source_payload_we) begin
+ litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
end
assign litedramcore_rdcmdphase = (a7ddrphy_rdphase_storage - 1'd1);
assign litedramcore_wrcmdphase = (a7ddrphy_wrphase_storage - 1'd1);
assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
always @(*) begin
- litedramcore_choose_cmd_valids <= 8'd0;
- litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids <= 8'd0;
+ litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
end
assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids;
assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0;
assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4;
assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5;
always @(*) begin
- litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
- if (litedramcore_choose_cmd_cmd_valid) begin
- litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0;
- end
+ litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
+ if (litedramcore_choose_cmd_cmd_valid) begin
+ litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0;
+ end
end
always @(*) begin
- litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
- if (litedramcore_choose_cmd_cmd_valid) begin
- litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1;
- end
+ litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
+ if (litedramcore_choose_cmd_cmd_valid) begin
+ litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1;
+ end
end
always @(*) begin
- litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
- if (litedramcore_choose_cmd_cmd_valid) begin
- litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2;
- end
+ litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
+ if (litedramcore_choose_cmd_cmd_valid) begin
+ litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2;
+ end
end
always @(*) begin
- litedramcore_bankmachine0_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin
- litedramcore_bankmachine0_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin
- litedramcore_bankmachine0_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine0_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin
+ litedramcore_bankmachine0_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin
+ litedramcore_bankmachine0_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_bankmachine1_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin
- litedramcore_bankmachine1_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin
- litedramcore_bankmachine1_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine1_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin
+ litedramcore_bankmachine1_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin
+ litedramcore_bankmachine1_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_bankmachine2_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin
- litedramcore_bankmachine2_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin
- litedramcore_bankmachine2_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine2_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin
+ litedramcore_bankmachine2_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin
+ litedramcore_bankmachine2_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_bankmachine3_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin
- litedramcore_bankmachine3_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin
- litedramcore_bankmachine3_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine3_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin
+ litedramcore_bankmachine3_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin
+ litedramcore_bankmachine3_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_bankmachine4_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin
- litedramcore_bankmachine4_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin
- litedramcore_bankmachine4_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine4_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin
+ litedramcore_bankmachine4_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin
+ litedramcore_bankmachine4_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_bankmachine5_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin
- litedramcore_bankmachine5_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin
- litedramcore_bankmachine5_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine5_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin
+ litedramcore_bankmachine5_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin
+ litedramcore_bankmachine5_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_bankmachine6_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin
- litedramcore_bankmachine6_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin
- litedramcore_bankmachine6_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine6_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin
+ litedramcore_bankmachine6_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin
+ litedramcore_bankmachine6_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_bankmachine7_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin
- litedramcore_bankmachine7_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin
- litedramcore_bankmachine7_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine7_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin
+ litedramcore_bankmachine7_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin
+ litedramcore_bankmachine7_cmd_ready <= 1'd1;
+ end
end
assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid));
always @(*) begin
- litedramcore_choose_req_valids <= 8'd0;
- litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids <= 8'd0;
+ litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
end
assign litedramcore_choose_req_request = litedramcore_choose_req_valids;
assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6;
assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10;
assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11;
always @(*) begin
- litedramcore_choose_req_cmd_payload_cas <= 1'd0;
- if (litedramcore_choose_req_cmd_valid) begin
- litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3;
- end
+ litedramcore_choose_req_cmd_payload_cas <= 1'd0;
+ if (litedramcore_choose_req_cmd_valid) begin
+ litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3;
+ end
end
always @(*) begin
- litedramcore_choose_req_cmd_payload_ras <= 1'd0;
- if (litedramcore_choose_req_cmd_valid) begin
- litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4;
- end
+ litedramcore_choose_req_cmd_payload_ras <= 1'd0;
+ if (litedramcore_choose_req_cmd_valid) begin
+ litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4;
+ end
end
always @(*) begin
- litedramcore_choose_req_cmd_payload_we <= 1'd0;
- if (litedramcore_choose_req_cmd_valid) begin
- litedramcore_choose_req_cmd_payload_we <= t_array_muxed5;
- end
+ litedramcore_choose_req_cmd_payload_we <= 1'd0;
+ if (litedramcore_choose_req_cmd_valid) begin
+ litedramcore_choose_req_cmd_payload_we <= t_array_muxed5;
+ end
end
assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid));
assign litedramcore_dfi_p0_reset_n = 1'd1;
assign litedramcore_dfi_p3_odt = {1{litedramcore_steerer7}};
assign litedramcore_tfawcon_count = ((((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]) + litedramcore_tfawcon_window[3]) + litedramcore_tfawcon_window[4]);
always @(*) begin
- litedramcore_multiplexer_next_state <= 4'd0;
- litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- if (litedramcore_read_available) begin
- if (((~litedramcore_write_available) | litedramcore_max_time1)) begin
- litedramcore_multiplexer_next_state <= 2'd3;
- end
- end
- if (litedramcore_go_to_refresh) begin
- litedramcore_multiplexer_next_state <= 2'd2;
- end
- end
- 2'd2: begin
- if (litedramcore_cmd_last) begin
- litedramcore_multiplexer_next_state <= 1'd0;
- end
- end
- 2'd3: begin
- if (litedramcore_twtrcon_ready) begin
- litedramcore_multiplexer_next_state <= 1'd0;
- end
- end
- 3'd4: begin
- litedramcore_multiplexer_next_state <= 3'd5;
- end
- 3'd5: begin
- litedramcore_multiplexer_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_multiplexer_next_state <= 3'd7;
- end
- 3'd7: begin
- litedramcore_multiplexer_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_multiplexer_next_state <= 4'd9;
- end
- 4'd9: begin
- litedramcore_multiplexer_next_state <= 4'd10;
- end
- 4'd10: begin
- litedramcore_multiplexer_next_state <= 1'd1;
- end
- default: begin
- if (litedramcore_write_available) begin
- if (((~litedramcore_read_available) | litedramcore_max_time0)) begin
- litedramcore_multiplexer_next_state <= 3'd4;
- end
- end
- if (litedramcore_go_to_refresh) begin
- litedramcore_multiplexer_next_state <= 2'd2;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_steerer_sel0 <= 2'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- litedramcore_steerer_sel0 <= 1'd0;
- if ((a7ddrphy_wrphase_storage == 1'd0)) begin
- litedramcore_steerer_sel0 <= 2'd2;
- end
- if ((litedramcore_wrcmdphase == 1'd0)) begin
- litedramcore_steerer_sel0 <= 1'd1;
- end
- end
- 2'd2: begin
- litedramcore_steerer_sel0 <= 2'd3;
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- litedramcore_steerer_sel0 <= 1'd0;
- if ((a7ddrphy_rdphase_storage == 1'd0)) begin
- litedramcore_steerer_sel0 <= 2'd2;
- end
- if ((litedramcore_rdcmdphase == 1'd0)) begin
- litedramcore_steerer_sel0 <= 1'd1;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_cmd_ready <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- end
- 2'd2: begin
- litedramcore_cmd_ready <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_steerer_sel1 <= 2'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- litedramcore_steerer_sel1 <= 1'd0;
- if ((a7ddrphy_wrphase_storage == 1'd1)) begin
- litedramcore_steerer_sel1 <= 2'd2;
- end
- if ((litedramcore_wrcmdphase == 1'd1)) begin
- litedramcore_steerer_sel1 <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- litedramcore_steerer_sel1 <= 1'd0;
- if ((a7ddrphy_rdphase_storage == 1'd1)) begin
- litedramcore_steerer_sel1 <= 2'd2;
- end
- if ((litedramcore_rdcmdphase == 1'd1)) begin
- litedramcore_steerer_sel1 <= 1'd1;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_steerer_sel2 <= 2'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- litedramcore_steerer_sel2 <= 1'd0;
- if ((a7ddrphy_wrphase_storage == 2'd2)) begin
- litedramcore_steerer_sel2 <= 2'd2;
- end
- if ((litedramcore_wrcmdphase == 2'd2)) begin
- litedramcore_steerer_sel2 <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- litedramcore_steerer_sel2 <= 1'd0;
- if ((a7ddrphy_rdphase_storage == 2'd2)) begin
- litedramcore_steerer_sel2 <= 2'd2;
- end
- if ((litedramcore_rdcmdphase == 2'd2)) begin
- litedramcore_steerer_sel2 <= 1'd1;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_choose_cmd_want_activates <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_steerer_sel3 <= 2'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- litedramcore_steerer_sel3 <= 1'd0;
- if ((a7ddrphy_wrphase_storage == 2'd3)) begin
- litedramcore_steerer_sel3 <= 2'd2;
- end
- if ((litedramcore_wrcmdphase == 2'd3)) begin
- litedramcore_steerer_sel3 <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- litedramcore_steerer_sel3 <= 1'd0;
- if ((a7ddrphy_rdphase_storage == 2'd3)) begin
- litedramcore_steerer_sel3 <= 2'd2;
- end
- if ((litedramcore_rdcmdphase == 2'd3)) begin
- litedramcore_steerer_sel3 <= 1'd1;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_en0 <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- litedramcore_en0 <= 1'd1;
- end
- endcase
-end
-always @(*) begin
- litedramcore_choose_cmd_cmd_ready <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_choose_req_want_reads <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- litedramcore_choose_req_want_reads <= 1'd1;
- end
- endcase
-end
-always @(*) begin
- litedramcore_choose_req_want_writes <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- litedramcore_choose_req_want_writes <= 1'd1;
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_choose_req_cmd_ready <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- if (1'd0) begin
- litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
- end else begin
- litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- if (1'd0) begin
- litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
- end else begin
- litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_en1 <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- litedramcore_en1 <= 1'd1;
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- end
- endcase
+ litedramcore_multiplexer_next_state <= 4'd0;
+ litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ if (litedramcore_read_available) begin
+ if (((~litedramcore_write_available) | litedramcore_max_time1)) begin
+ litedramcore_multiplexer_next_state <= 2'd3;
+ end
+ end
+ if (litedramcore_go_to_refresh) begin
+ litedramcore_multiplexer_next_state <= 2'd2;
+ end
+ end
+ 2'd2: begin
+ if (litedramcore_cmd_last) begin
+ litedramcore_multiplexer_next_state <= 1'd0;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_twtrcon_ready) begin
+ litedramcore_multiplexer_next_state <= 1'd0;
+ end
+ end
+ 3'd4: begin
+ litedramcore_multiplexer_next_state <= 3'd5;
+ end
+ 3'd5: begin
+ litedramcore_multiplexer_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_multiplexer_next_state <= 3'd7;
+ end
+ 3'd7: begin
+ litedramcore_multiplexer_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_multiplexer_next_state <= 4'd9;
+ end
+ 4'd9: begin
+ litedramcore_multiplexer_next_state <= 4'd10;
+ end
+ 4'd10: begin
+ litedramcore_multiplexer_next_state <= 1'd1;
+ end
+ default: begin
+ if (litedramcore_write_available) begin
+ if (((~litedramcore_read_available) | litedramcore_max_time0)) begin
+ litedramcore_multiplexer_next_state <= 3'd4;
+ end
+ end
+ if (litedramcore_go_to_refresh) begin
+ litedramcore_multiplexer_next_state <= 2'd2;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_steerer_sel0 <= 2'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ litedramcore_steerer_sel0 <= 1'd0;
+ if ((a7ddrphy_wrphase_storage == 1'd0)) begin
+ litedramcore_steerer_sel0 <= 2'd2;
+ end
+ if ((litedramcore_wrcmdphase == 1'd0)) begin
+ litedramcore_steerer_sel0 <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ litedramcore_steerer_sel0 <= 2'd3;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ litedramcore_steerer_sel0 <= 1'd0;
+ if ((a7ddrphy_rdphase_storage == 1'd0)) begin
+ litedramcore_steerer_sel0 <= 2'd2;
+ end
+ if ((litedramcore_rdcmdphase == 1'd0)) begin
+ litedramcore_steerer_sel0 <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_cmd_ready <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ litedramcore_cmd_ready <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_steerer_sel1 <= 2'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ litedramcore_steerer_sel1 <= 1'd0;
+ if ((a7ddrphy_wrphase_storage == 1'd1)) begin
+ litedramcore_steerer_sel1 <= 2'd2;
+ end
+ if ((litedramcore_wrcmdphase == 1'd1)) begin
+ litedramcore_steerer_sel1 <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ litedramcore_steerer_sel1 <= 1'd0;
+ if ((a7ddrphy_rdphase_storage == 1'd1)) begin
+ litedramcore_steerer_sel1 <= 2'd2;
+ end
+ if ((litedramcore_rdcmdphase == 1'd1)) begin
+ litedramcore_steerer_sel1 <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_steerer_sel2 <= 2'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ litedramcore_steerer_sel2 <= 1'd0;
+ if ((a7ddrphy_wrphase_storage == 2'd2)) begin
+ litedramcore_steerer_sel2 <= 2'd2;
+ end
+ if ((litedramcore_wrcmdphase == 2'd2)) begin
+ litedramcore_steerer_sel2 <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ litedramcore_steerer_sel2 <= 1'd0;
+ if ((a7ddrphy_rdphase_storage == 2'd2)) begin
+ litedramcore_steerer_sel2 <= 2'd2;
+ end
+ if ((litedramcore_rdcmdphase == 2'd2)) begin
+ litedramcore_steerer_sel2 <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_choose_cmd_want_activates <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ if (1'd0) begin
+ end else begin
+ litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ if (1'd0) begin
+ end else begin
+ litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_steerer_sel3 <= 2'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ litedramcore_steerer_sel3 <= 1'd0;
+ if ((a7ddrphy_wrphase_storage == 2'd3)) begin
+ litedramcore_steerer_sel3 <= 2'd2;
+ end
+ if ((litedramcore_wrcmdphase == 2'd3)) begin
+ litedramcore_steerer_sel3 <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ litedramcore_steerer_sel3 <= 1'd0;
+ if ((a7ddrphy_rdphase_storage == 2'd3)) begin
+ litedramcore_steerer_sel3 <= 2'd2;
+ end
+ if ((litedramcore_rdcmdphase == 2'd3)) begin
+ litedramcore_steerer_sel3 <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_en0 <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ litedramcore_en0 <= 1'd1;
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_choose_cmd_cmd_ready <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ if (1'd0) begin
+ end else begin
+ litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ if (1'd0) begin
+ end else begin
+ litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_choose_req_want_reads <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ litedramcore_choose_req_want_reads <= 1'd1;
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_choose_req_want_writes <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ litedramcore_choose_req_want_writes <= 1'd1;
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_choose_req_cmd_ready <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ if (1'd0) begin
+ litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+ end else begin
+ litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ if (1'd0) begin
+ litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+ end else begin
+ litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_en1 <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ litedramcore_en1 <= 1'd1;
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ end
+ endcase
end
assign litedramcore_roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
assign litedramcore_roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock));
assign user_port_wdata_ready = litedramcore_new_master_wdata_ready1;
assign user_port_rdata_valid = litedramcore_new_master_rdata_valid8;
always @(*) begin
- litedramcore_interface_wdata <= 128'd0;
- case ({litedramcore_new_master_wdata_ready1})
- 1'd1: begin
- litedramcore_interface_wdata <= user_port_wdata_payload_data;
- end
- default: begin
- litedramcore_interface_wdata <= 1'd0;
- end
- endcase
-end
-always @(*) begin
- litedramcore_interface_wdata_we <= 16'd0;
- case ({litedramcore_new_master_wdata_ready1})
- 1'd1: begin
- litedramcore_interface_wdata_we <= user_port_wdata_payload_we;
- end
- default: begin
- litedramcore_interface_wdata_we <= 1'd0;
- end
- endcase
+ litedramcore_interface_wdata <= 128'd0;
+ case ({litedramcore_new_master_wdata_ready1})
+ 1'd1: begin
+ litedramcore_interface_wdata <= user_port_wdata_payload_data;
+ end
+ default: begin
+ litedramcore_interface_wdata <= 1'd0;
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_interface_wdata_we <= 16'd0;
+ case ({litedramcore_new_master_wdata_ready1})
+ 1'd1: begin
+ litedramcore_interface_wdata_we <= user_port_wdata_payload_we;
+ end
+ default: begin
+ litedramcore_interface_wdata_we <= 1'd0;
+ end
+ endcase
end
assign user_port_rdata_payload_data = litedramcore_interface_rdata;
assign litedramcore_roundrobin0_grant = 1'd0;
assign litedramcore_roundrobin6_grant = 1'd0;
assign litedramcore_roundrobin7_grant = 1'd0;
always @(*) begin
- litedramcore_next_state <= 2'd0;
- litedramcore_next_state <= litedramcore_state;
- case (litedramcore_state)
- 1'd1: begin
- litedramcore_next_state <= 2'd2;
- end
- 2'd2: begin
- litedramcore_next_state <= 1'd0;
- end
- default: begin
- if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_next_state <= 1'd1;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_we_next_value2 <= 1'd0;
- case (litedramcore_state)
- 1'd1: begin
- litedramcore_we_next_value2 <= 1'd0;
- end
- 2'd2: begin
- end
- default: begin
- if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_we_next_value_ce2 <= 1'd0;
- case (litedramcore_state)
- 1'd1: begin
- litedramcore_we_next_value_ce2 <= 1'd1;
- end
- 2'd2: begin
- end
- default: begin
- if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_we_next_value_ce2 <= 1'd1;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_wishbone_ack <= 1'd0;
- case (litedramcore_state)
- 1'd1: begin
- end
- 2'd2: begin
- litedramcore_wishbone_ack <= 1'd1;
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_wishbone_dat_r <= 32'd0;
- case (litedramcore_state)
- 1'd1: begin
- end
- 2'd2: begin
- litedramcore_wishbone_dat_r <= litedramcore_dat_r;
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_dat_w_next_value0 <= 32'd0;
- case (litedramcore_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- default: begin
- litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w;
- end
- endcase
-end
-always @(*) begin
- litedramcore_dat_w_next_value_ce0 <= 1'd0;
- case (litedramcore_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- default: begin
- litedramcore_dat_w_next_value_ce0 <= 1'd1;
- end
- endcase
-end
-always @(*) begin
- litedramcore_adr_next_value1 <= 14'd0;
- case (litedramcore_state)
- 1'd1: begin
- litedramcore_adr_next_value1 <= 1'd0;
- end
- 2'd2: begin
- end
- default: begin
- if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_adr_next_value1 <= litedramcore_wishbone_adr;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_adr_next_value_ce1 <= 1'd0;
- case (litedramcore_state)
- 1'd1: begin
- litedramcore_adr_next_value_ce1 <= 1'd1;
- end
- 2'd2: begin
- end
- default: begin
- if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_adr_next_value_ce1 <= 1'd1;
- end
- end
- endcase
+ litedramcore_next_state <= 2'd0;
+ litedramcore_next_state <= litedramcore_state;
+ case (litedramcore_state)
+ 1'd1: begin
+ litedramcore_next_state <= 2'd2;
+ end
+ 2'd2: begin
+ litedramcore_next_state <= 1'd0;
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_next_state <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_we_next_value2 <= 1'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ litedramcore_we_next_value2 <= 1'd0;
+ end
+ 2'd2: begin
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_we_next_value_ce2 <= 1'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ litedramcore_we_next_value_ce2 <= 1'd1;
+ end
+ 2'd2: begin
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_we_next_value_ce2 <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_wishbone_ack <= 1'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ litedramcore_wishbone_ack <= 1'd1;
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_wishbone_dat_r <= 32'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ litedramcore_wishbone_dat_r <= litedramcore_dat_r;
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_dat_w_next_value0 <= 32'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ default: begin
+ litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w;
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_dat_w_next_value_ce0 <= 1'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ default: begin
+ litedramcore_dat_w_next_value_ce0 <= 1'd1;
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_adr_next_value1 <= 14'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ litedramcore_adr_next_value1 <= 1'd0;
+ end
+ 2'd2: begin
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_adr_next_value1 <= litedramcore_wishbone_adr;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_adr_next_value_ce1 <= 1'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ litedramcore_adr_next_value_ce1 <= 1'd1;
+ end
+ 2'd2: begin
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_adr_next_value_ce1 <= 1'd1;
+ end
+ end
+ endcase
end
assign litedramcore_wishbone_adr = wb_bus_adr;
assign litedramcore_wishbone_dat_w = wb_bus_dat_w;
assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0);
assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
always @(*) begin
- csrbank0_init_done0_we <= 1'd0;
- if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
- csrbank0_init_done0_we <= (~interface0_bank_bus_we);
- end
+ csrbank0_init_done0_we <= 1'd0;
+ if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank0_init_done0_we <= (~interface0_bank_bus_we);
+ end
end
always @(*) begin
- csrbank0_init_done0_re <= 1'd0;
- if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
- csrbank0_init_done0_re <= interface0_bank_bus_we;
- end
+ csrbank0_init_done0_re <= 1'd0;
+ if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank0_init_done0_re <= interface0_bank_bus_we;
+ end
end
assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0];
always @(*) begin
- csrbank0_init_error0_re <= 1'd0;
- if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
- csrbank0_init_error0_re <= interface0_bank_bus_we;
- end
+ csrbank0_init_error0_re <= 1'd0;
+ if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
+ csrbank0_init_error0_re <= interface0_bank_bus_we;
+ end
end
always @(*) begin
- csrbank0_init_error0_we <= 1'd0;
- if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
- csrbank0_init_error0_we <= (~interface0_bank_bus_we);
- end
+ csrbank0_init_error0_we <= 1'd0;
+ if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
+ csrbank0_init_error0_we <= (~interface0_bank_bus_we);
+ end
end
assign csrbank0_init_done0_w = init_done_storage;
assign csrbank0_init_error0_w = init_error_storage;
assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1);
assign csrbank1_rst0_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- csrbank1_rst0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
- csrbank1_rst0_re <= interface1_bank_bus_we;
- end
+ csrbank1_rst0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank1_rst0_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- csrbank1_rst0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
- csrbank1_rst0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_rst0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank1_rst0_we <= (~interface1_bank_bus_we);
+ end
end
assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0];
always @(*) begin
- csrbank1_dly_sel0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
- csrbank1_dly_sel0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_dly_sel0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
+ csrbank1_dly_sel0_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- csrbank1_dly_sel0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
- csrbank1_dly_sel0_re <= interface1_bank_bus_we;
- end
+ csrbank1_dly_sel0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
+ csrbank1_dly_sel0_re <= interface1_bank_bus_we;
+ end
end
assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0];
always @(*) begin
- csrbank1_half_sys8x_taps0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
- csrbank1_half_sys8x_taps0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_half_sys8x_taps0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
+ csrbank1_half_sys8x_taps0_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- csrbank1_half_sys8x_taps0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
- csrbank1_half_sys8x_taps0_re <= interface1_bank_bus_we;
- end
+ csrbank1_half_sys8x_taps0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
+ csrbank1_half_sys8x_taps0_re <= interface1_bank_bus_we;
+ end
end
assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- csrbank1_wlevel_en0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
- csrbank1_wlevel_en0_re <= interface1_bank_bus_we;
- end
+ csrbank1_wlevel_en0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
+ csrbank1_wlevel_en0_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- csrbank1_wlevel_en0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
- csrbank1_wlevel_en0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_wlevel_en0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
+ csrbank1_wlevel_en0_we <= (~interface1_bank_bus_we);
+ end
end
assign a7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- a7ddrphy_wlevel_strobe_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
- a7ddrphy_wlevel_strobe_re <= interface1_bank_bus_we;
- end
+ a7ddrphy_wlevel_strobe_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
+ a7ddrphy_wlevel_strobe_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- a7ddrphy_wlevel_strobe_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
- a7ddrphy_wlevel_strobe_we <= (~interface1_bank_bus_we);
- end
+ a7ddrphy_wlevel_strobe_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
+ a7ddrphy_wlevel_strobe_we <= (~interface1_bank_bus_we);
+ end
end
assign a7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- a7ddrphy_rdly_dq_rst_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
- a7ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we;
- end
+ a7ddrphy_rdly_dq_rst_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
+ a7ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- a7ddrphy_rdly_dq_rst_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
- a7ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we);
- end
+ a7ddrphy_rdly_dq_rst_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
+ a7ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we);
+ end
end
assign a7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- a7ddrphy_rdly_dq_inc_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
- a7ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we;
- end
+ a7ddrphy_rdly_dq_inc_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
+ a7ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- a7ddrphy_rdly_dq_inc_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
- a7ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we);
- end
+ a7ddrphy_rdly_dq_inc_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
+ a7ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we);
+ end
end
assign a7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
- a7ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
- end
+ a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
+ a7ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
- a7ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
- end
+ a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
+ a7ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
+ end
end
assign a7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- a7ddrphy_rdly_dq_bitslip_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
- a7ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we);
- end
+ a7ddrphy_rdly_dq_bitslip_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
+ a7ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- a7ddrphy_rdly_dq_bitslip_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
- a7ddrphy_rdly_dq_bitslip_re <= interface1_bank_bus_we;
- end
+ a7ddrphy_rdly_dq_bitslip_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
+ a7ddrphy_rdly_dq_bitslip_re <= interface1_bank_bus_we;
+ end
end
assign a7ddrphy_wdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
- a7ddrphy_wdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
- end
+ a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
+ a7ddrphy_wdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
- a7ddrphy_wdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
- end
+ a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
+ a7ddrphy_wdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
+ end
end
assign a7ddrphy_wdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- a7ddrphy_wdly_dq_bitslip_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
- a7ddrphy_wdly_dq_bitslip_we <= (~interface1_bank_bus_we);
- end
+ a7ddrphy_wdly_dq_bitslip_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
+ a7ddrphy_wdly_dq_bitslip_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- a7ddrphy_wdly_dq_bitslip_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
- a7ddrphy_wdly_dq_bitslip_re <= interface1_bank_bus_we;
- end
+ a7ddrphy_wdly_dq_bitslip_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
+ a7ddrphy_wdly_dq_bitslip_re <= interface1_bank_bus_we;
+ end
end
assign csrbank1_rdphase0_r = interface1_bank_bus_dat_w[1:0];
always @(*) begin
- csrbank1_rdphase0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
- csrbank1_rdphase0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_rdphase0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
+ csrbank1_rdphase0_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- csrbank1_rdphase0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
- csrbank1_rdphase0_re <= interface1_bank_bus_we;
- end
+ csrbank1_rdphase0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
+ csrbank1_rdphase0_re <= interface1_bank_bus_we;
+ end
end
assign csrbank1_wrphase0_r = interface1_bank_bus_dat_w[1:0];
always @(*) begin
- csrbank1_wrphase0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
- csrbank1_wrphase0_re <= interface1_bank_bus_we;
- end
+ csrbank1_wrphase0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
+ csrbank1_wrphase0_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- csrbank1_wrphase0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
- csrbank1_wrphase0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_wrphase0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
+ csrbank1_wrphase0_we <= (~interface1_bank_bus_we);
+ end
end
assign csrbank1_rst0_w = a7ddrphy_rst_storage;
assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0];
assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2);
assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0];
always @(*) begin
- csrbank2_dfii_control0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
- csrbank2_dfii_control0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_control0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank2_dfii_control0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_control0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
- csrbank2_dfii_control0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_control0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank2_dfii_control0_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0];
always @(*) begin
- csrbank2_dfii_pi0_command0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
- csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi0_command0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
+ csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi0_command0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
- csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi0_command0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
+ csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we);
+ end
end
assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0];
always @(*) begin
- litedramcore_phaseinjector0_command_issue_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
- litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we;
- end
+ litedramcore_phaseinjector0_command_issue_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
+ litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- litedramcore_phaseinjector0_command_issue_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
- litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we);
- end
+ litedramcore_phaseinjector0_command_issue_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
+ litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[13:0];
always @(*) begin
- csrbank2_dfii_pi0_address0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
- csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi0_address0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
+ csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi0_address0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
- csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi0_address0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
+ csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0];
always @(*) begin
- csrbank2_dfii_pi0_baddress0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
- csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi0_baddress0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
+ csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi0_baddress0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
- csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi0_baddress0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
+ csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
- csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
+ csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
- csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
+ csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi0_rddata_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi0_rddata_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
- csrbank2_dfii_pi0_rddata_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi0_rddata_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
+ csrbank2_dfii_pi0_rddata_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi0_rddata_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
- csrbank2_dfii_pi0_rddata_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi0_rddata_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
+ csrbank2_dfii_pi0_rddata_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0];
always @(*) begin
- csrbank2_dfii_pi1_command0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
- csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi1_command0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
+ csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi1_command0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
- csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi1_command0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
+ csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we;
+ end
end
assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0];
always @(*) begin
- litedramcore_phaseinjector1_command_issue_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
- litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we);
- end
+ litedramcore_phaseinjector1_command_issue_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
+ litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- litedramcore_phaseinjector1_command_issue_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
- litedramcore_phaseinjector1_command_issue_re <= interface2_bank_bus_we;
- end
+ litedramcore_phaseinjector1_command_issue_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
+ litedramcore_phaseinjector1_command_issue_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[13:0];
always @(*) begin
- csrbank2_dfii_pi1_address0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
- csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi1_address0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
+ csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi1_address0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
- csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi1_address0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
+ csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0];
always @(*) begin
- csrbank2_dfii_pi1_baddress0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
- csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi1_baddress0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
+ csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi1_baddress0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
- csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi1_baddress0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
+ csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
- csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
+ csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
- csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
+ csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi1_rddata_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi1_rddata_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
- csrbank2_dfii_pi1_rddata_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi1_rddata_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
+ csrbank2_dfii_pi1_rddata_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi1_rddata_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
- csrbank2_dfii_pi1_rddata_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi1_rddata_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
+ csrbank2_dfii_pi1_rddata_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0];
always @(*) begin
- csrbank2_dfii_pi2_command0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
- csrbank2_dfii_pi2_command0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi2_command0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
+ csrbank2_dfii_pi2_command0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi2_command0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
- csrbank2_dfii_pi2_command0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi2_command0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
+ csrbank2_dfii_pi2_command0_re <= interface2_bank_bus_we;
+ end
end
assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0];
always @(*) begin
- litedramcore_phaseinjector2_command_issue_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
- litedramcore_phaseinjector2_command_issue_we <= (~interface2_bank_bus_we);
- end
+ litedramcore_phaseinjector2_command_issue_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
+ litedramcore_phaseinjector2_command_issue_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- litedramcore_phaseinjector2_command_issue_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
- litedramcore_phaseinjector2_command_issue_re <= interface2_bank_bus_we;
- end
+ litedramcore_phaseinjector2_command_issue_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
+ litedramcore_phaseinjector2_command_issue_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[13:0];
always @(*) begin
- csrbank2_dfii_pi2_address0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
- csrbank2_dfii_pi2_address0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi2_address0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
+ csrbank2_dfii_pi2_address0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi2_address0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
- csrbank2_dfii_pi2_address0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi2_address0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
+ csrbank2_dfii_pi2_address0_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0];
always @(*) begin
- csrbank2_dfii_pi2_baddress0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
- csrbank2_dfii_pi2_baddress0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi2_baddress0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
+ csrbank2_dfii_pi2_baddress0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi2_baddress0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
- csrbank2_dfii_pi2_baddress0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi2_baddress0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
+ csrbank2_dfii_pi2_baddress0_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
- csrbank2_dfii_pi2_wrdata0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
+ csrbank2_dfii_pi2_wrdata0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
- csrbank2_dfii_pi2_wrdata0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
+ csrbank2_dfii_pi2_wrdata0_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi2_rddata_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi2_rddata_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
- csrbank2_dfii_pi2_rddata_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi2_rddata_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
+ csrbank2_dfii_pi2_rddata_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi2_rddata_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
- csrbank2_dfii_pi2_rddata_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi2_rddata_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
+ csrbank2_dfii_pi2_rddata_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0];
always @(*) begin
- csrbank2_dfii_pi3_command0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin
- csrbank2_dfii_pi3_command0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi3_command0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin
+ csrbank2_dfii_pi3_command0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi3_command0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin
- csrbank2_dfii_pi3_command0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi3_command0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin
+ csrbank2_dfii_pi3_command0_we <= (~interface2_bank_bus_we);
+ end
end
assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0];
always @(*) begin
- litedramcore_phaseinjector3_command_issue_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin
- litedramcore_phaseinjector3_command_issue_re <= interface2_bank_bus_we;
- end
+ litedramcore_phaseinjector3_command_issue_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin
+ litedramcore_phaseinjector3_command_issue_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- litedramcore_phaseinjector3_command_issue_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin
- litedramcore_phaseinjector3_command_issue_we <= (~interface2_bank_bus_we);
- end
+ litedramcore_phaseinjector3_command_issue_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin
+ litedramcore_phaseinjector3_command_issue_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[13:0];
always @(*) begin
- csrbank2_dfii_pi3_address0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin
- csrbank2_dfii_pi3_address0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi3_address0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin
+ csrbank2_dfii_pi3_address0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi3_address0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin
- csrbank2_dfii_pi3_address0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi3_address0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin
+ csrbank2_dfii_pi3_address0_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0];
always @(*) begin
- csrbank2_dfii_pi3_baddress0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin
- csrbank2_dfii_pi3_baddress0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi3_baddress0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin
+ csrbank2_dfii_pi3_baddress0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi3_baddress0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin
- csrbank2_dfii_pi3_baddress0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi3_baddress0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin
+ csrbank2_dfii_pi3_baddress0_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi3_wrdata0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin
- csrbank2_dfii_pi3_wrdata0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi3_wrdata0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin
+ csrbank2_dfii_pi3_wrdata0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin
- csrbank2_dfii_pi3_wrdata0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin
+ csrbank2_dfii_pi3_wrdata0_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi3_rddata_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi3_rddata_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin
- csrbank2_dfii_pi3_rddata_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi3_rddata_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin
+ csrbank2_dfii_pi3_rddata_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi3_rddata_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin
- csrbank2_dfii_pi3_rddata_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi3_rddata_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin
+ csrbank2_dfii_pi3_rddata_re <= interface2_bank_bus_we;
+ end
end
assign litedramcore_sel = litedramcore_storage[0];
assign litedramcore_cke = litedramcore_storage[1];
assign interface2_bank_bus_dat_w = csr_interconnect_dat_w;
assign csr_interconnect_dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r);
always @(*) begin
- rhs_array_muxed0 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0];
- end
- 1'd1: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1];
- end
- 2'd2: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2];
- end
- 2'd3: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3];
- end
- 3'd4: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4];
- end
- 3'd5: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5];
- end
- 3'd6: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6];
- end
- default: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7];
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed1 <= 14'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a;
- end
- 1'd1: begin
- rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a;
- end
- 2'd2: begin
- rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a;
- end
- 2'd3: begin
- rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a;
- end
- 3'd4: begin
- rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a;
- end
- 3'd5: begin
- rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a;
- end
- 3'd6: begin
- rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a;
- end
- default: begin
- rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed2 <= 3'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba;
- end
- 1'd1: begin
- rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba;
- end
- 2'd2: begin
- rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba;
- end
- 2'd3: begin
- rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba;
- end
- 3'd4: begin
- rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba;
- end
- 3'd5: begin
- rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba;
- end
- 3'd6: begin
- rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba;
- end
- default: begin
- rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed3 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read;
- end
- 1'd1: begin
- rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read;
- end
- 2'd2: begin
- rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read;
- end
- 2'd3: begin
- rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read;
- end
- 3'd4: begin
- rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read;
- end
- 3'd5: begin
- rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read;
- end
- 3'd6: begin
- rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read;
- end
- default: begin
- rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed4 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write;
- end
- 1'd1: begin
- rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write;
- end
- 2'd2: begin
- rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write;
- end
- 2'd3: begin
- rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write;
- end
- 3'd4: begin
- rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write;
- end
- 3'd5: begin
- rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write;
- end
- 3'd6: begin
- rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write;
- end
- default: begin
- rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed5 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
- end
- 1'd1: begin
- rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
- end
- 2'd2: begin
- rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
- end
- 2'd3: begin
- rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
- end
- 3'd4: begin
- rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
- end
- 3'd5: begin
- rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
- end
- 3'd6: begin
- rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
- end
- default: begin
- rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
- end
- endcase
-end
-always @(*) begin
- t_array_muxed0 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas;
- end
- 1'd1: begin
- t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas;
- end
- 2'd2: begin
- t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas;
- end
- 2'd3: begin
- t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas;
- end
- 3'd4: begin
- t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas;
- end
- 3'd5: begin
- t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas;
- end
- 3'd6: begin
- t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas;
- end
- default: begin
- t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas;
- end
- endcase
-end
-always @(*) begin
- t_array_muxed1 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras;
- end
- 1'd1: begin
- t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras;
- end
- 2'd2: begin
- t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras;
- end
- 2'd3: begin
- t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras;
- end
- 3'd4: begin
- t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras;
- end
- 3'd5: begin
- t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras;
- end
- 3'd6: begin
- t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras;
- end
- default: begin
- t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras;
- end
- endcase
-end
-always @(*) begin
- t_array_muxed2 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we;
- end
- 1'd1: begin
- t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we;
- end
- 2'd2: begin
- t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we;
- end
- 2'd3: begin
- t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we;
- end
- 3'd4: begin
- t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we;
- end
- 3'd5: begin
- t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we;
- end
- 3'd6: begin
- t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we;
- end
- default: begin
- t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed6 <= 1'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[0];
- end
- 1'd1: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[1];
- end
- 2'd2: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[2];
- end
- 2'd3: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[3];
- end
- 3'd4: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[4];
- end
- 3'd5: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[5];
- end
- 3'd6: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[6];
- end
- default: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[7];
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed7 <= 14'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a;
- end
- 1'd1: begin
- rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a;
- end
- 2'd2: begin
- rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a;
- end
- 2'd3: begin
- rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a;
- end
- 3'd4: begin
- rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a;
- end
- 3'd5: begin
- rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a;
- end
- 3'd6: begin
- rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a;
- end
- default: begin
- rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed8 <= 3'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba;
- end
- 1'd1: begin
- rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba;
- end
- 2'd2: begin
- rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba;
- end
- 2'd3: begin
- rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba;
- end
- 3'd4: begin
- rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba;
- end
- 3'd5: begin
- rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba;
- end
- 3'd6: begin
- rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba;
- end
- default: begin
- rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed9 <= 1'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read;
- end
- 1'd1: begin
- rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read;
- end
- 2'd2: begin
- rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read;
- end
- 2'd3: begin
- rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read;
- end
- 3'd4: begin
- rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read;
- end
- 3'd5: begin
- rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read;
- end
- 3'd6: begin
- rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read;
- end
- default: begin
- rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed10 <= 1'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write;
- end
- 1'd1: begin
- rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write;
- end
- 2'd2: begin
- rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write;
- end
- 2'd3: begin
- rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write;
- end
- 3'd4: begin
- rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write;
- end
- 3'd5: begin
- rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write;
- end
- 3'd6: begin
- rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write;
- end
- default: begin
- rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed11 <= 1'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
- end
- 1'd1: begin
- rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
- end
- 2'd2: begin
- rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
- end
- 2'd3: begin
- rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
- end
- 3'd4: begin
- rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
- end
- 3'd5: begin
- rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
- end
- 3'd6: begin
- rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
- end
- default: begin
- rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
- end
- endcase
-end
-always @(*) begin
- t_array_muxed3 <= 1'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas;
- end
- 1'd1: begin
- t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas;
- end
- 2'd2: begin
- t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas;
- end
- 2'd3: begin
- t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas;
- end
- 3'd4: begin
- t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas;
- end
- 3'd5: begin
- t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas;
- end
- 3'd6: begin
- t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas;
- end
- default: begin
- t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas;
- end
- endcase
-end
-always @(*) begin
- t_array_muxed4 <= 1'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras;
- end
- 1'd1: begin
- t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras;
- end
- 2'd2: begin
- t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras;
- end
- 2'd3: begin
- t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras;
- end
- 3'd4: begin
- t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras;
- end
- 3'd5: begin
- t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras;
- end
- 3'd6: begin
- t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras;
- end
- default: begin
- t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras;
- end
- endcase
-end
-always @(*) begin
- t_array_muxed5 <= 1'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we;
- end
- 1'd1: begin
- t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we;
- end
- 2'd2: begin
- t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we;
- end
- 2'd3: begin
- t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we;
- end
- 3'd4: begin
- t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we;
- end
- 3'd5: begin
- t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we;
- end
- 3'd6: begin
- t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we;
- end
- default: begin
- t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed12 <= 21'd0;
- case (litedramcore_roundrobin0_grant)
- default: begin
- rhs_array_muxed12 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed13 <= 1'd0;
- case (litedramcore_roundrobin0_grant)
- default: begin
- rhs_array_muxed13 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed14 <= 1'd0;
- case (litedramcore_roundrobin0_grant)
- default: begin
- rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed15 <= 21'd0;
- case (litedramcore_roundrobin1_grant)
- default: begin
- rhs_array_muxed15 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed16 <= 1'd0;
- case (litedramcore_roundrobin1_grant)
- default: begin
- rhs_array_muxed16 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed17 <= 1'd0;
- case (litedramcore_roundrobin1_grant)
- default: begin
- rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed18 <= 21'd0;
- case (litedramcore_roundrobin2_grant)
- default: begin
- rhs_array_muxed18 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed19 <= 1'd0;
- case (litedramcore_roundrobin2_grant)
- default: begin
- rhs_array_muxed19 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed20 <= 1'd0;
- case (litedramcore_roundrobin2_grant)
- default: begin
- rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed21 <= 21'd0;
- case (litedramcore_roundrobin3_grant)
- default: begin
- rhs_array_muxed21 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed22 <= 1'd0;
- case (litedramcore_roundrobin3_grant)
- default: begin
- rhs_array_muxed22 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed23 <= 1'd0;
- case (litedramcore_roundrobin3_grant)
- default: begin
- rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
+ rhs_array_muxed0 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0];
+ end
+ 1'd1: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1];
+ end
+ 2'd2: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2];
+ end
+ 2'd3: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3];
+ end
+ 3'd4: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4];
+ end
+ 3'd5: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5];
+ end
+ 3'd6: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6];
+ end
+ default: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7];
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed1 <= 14'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a;
+ end
+ 1'd1: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a;
+ end
+ 2'd2: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a;
+ end
+ 2'd3: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a;
+ end
+ 3'd4: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a;
+ end
+ 3'd5: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a;
+ end
+ 3'd6: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a;
+ end
+ default: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed2 <= 3'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba;
+ end
+ 1'd1: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba;
+ end
+ 2'd2: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba;
+ end
+ 2'd3: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba;
+ end
+ 3'd4: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba;
+ end
+ 3'd5: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba;
+ end
+ 3'd6: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba;
+ end
+ default: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed3 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read;
+ end
+ 1'd1: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read;
+ end
+ 2'd2: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read;
+ end
+ 2'd3: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read;
+ end
+ 3'd4: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read;
+ end
+ 3'd5: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read;
+ end
+ 3'd6: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read;
+ end
+ default: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed4 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write;
+ end
+ 1'd1: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write;
+ end
+ 2'd2: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write;
+ end
+ 2'd3: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write;
+ end
+ 3'd4: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write;
+ end
+ 3'd5: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write;
+ end
+ 3'd6: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write;
+ end
+ default: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed5 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
+ end
+ 1'd1: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
+ end
+ 2'd2: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
+ end
+ 2'd3: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
+ end
+ 3'd4: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
+ end
+ 3'd5: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
+ end
+ 3'd6: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
+ end
+ default: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed0 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas;
+ end
+ 1'd1: begin
+ t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas;
+ end
+ 2'd2: begin
+ t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas;
+ end
+ 2'd3: begin
+ t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas;
+ end
+ 3'd4: begin
+ t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas;
+ end
+ 3'd5: begin
+ t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas;
+ end
+ 3'd6: begin
+ t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas;
+ end
+ default: begin
+ t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed1 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras;
+ end
+ 1'd1: begin
+ t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras;
+ end
+ 2'd2: begin
+ t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras;
+ end
+ 2'd3: begin
+ t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras;
+ end
+ 3'd4: begin
+ t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras;
+ end
+ 3'd5: begin
+ t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras;
+ end
+ 3'd6: begin
+ t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras;
+ end
+ default: begin
+ t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed2 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we;
+ end
+ 1'd1: begin
+ t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we;
+ end
+ 2'd2: begin
+ t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we;
+ end
+ 2'd3: begin
+ t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we;
+ end
+ 3'd4: begin
+ t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we;
+ end
+ 3'd5: begin
+ t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we;
+ end
+ 3'd6: begin
+ t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we;
+ end
+ default: begin
+ t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed6 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[0];
+ end
+ 1'd1: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[1];
+ end
+ 2'd2: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[2];
+ end
+ 2'd3: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[3];
+ end
+ 3'd4: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[4];
+ end
+ 3'd5: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[5];
+ end
+ 3'd6: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[6];
+ end
+ default: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[7];
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed7 <= 14'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a;
+ end
+ 1'd1: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a;
+ end
+ 2'd2: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a;
+ end
+ 2'd3: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a;
+ end
+ 3'd4: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a;
+ end
+ 3'd5: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a;
+ end
+ 3'd6: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a;
+ end
+ default: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed8 <= 3'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba;
+ end
+ 1'd1: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba;
+ end
+ 2'd2: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba;
+ end
+ 2'd3: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba;
+ end
+ 3'd4: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba;
+ end
+ 3'd5: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba;
+ end
+ 3'd6: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba;
+ end
+ default: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed9 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read;
+ end
+ 1'd1: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read;
+ end
+ 2'd2: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read;
+ end
+ 2'd3: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read;
+ end
+ 3'd4: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read;
+ end
+ 3'd5: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read;
+ end
+ 3'd6: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read;
+ end
+ default: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed10 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write;
+ end
+ 1'd1: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write;
+ end
+ 2'd2: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write;
+ end
+ 2'd3: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write;
+ end
+ 3'd4: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write;
+ end
+ 3'd5: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write;
+ end
+ 3'd6: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write;
+ end
+ default: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed11 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
+ end
+ 1'd1: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
+ end
+ 2'd2: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
+ end
+ 2'd3: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
+ end
+ 3'd4: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
+ end
+ 3'd5: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
+ end
+ 3'd6: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
+ end
+ default: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed3 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas;
+ end
+ 1'd1: begin
+ t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas;
+ end
+ 2'd2: begin
+ t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas;
+ end
+ 2'd3: begin
+ t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas;
+ end
+ 3'd4: begin
+ t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas;
+ end
+ 3'd5: begin
+ t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas;
+ end
+ 3'd6: begin
+ t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas;
+ end
+ default: begin
+ t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed4 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras;
+ end
+ 1'd1: begin
+ t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras;
+ end
+ 2'd2: begin
+ t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras;
+ end
+ 2'd3: begin
+ t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras;
+ end
+ 3'd4: begin
+ t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras;
+ end
+ 3'd5: begin
+ t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras;
+ end
+ 3'd6: begin
+ t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras;
+ end
+ default: begin
+ t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed5 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we;
+ end
+ 1'd1: begin
+ t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we;
+ end
+ 2'd2: begin
+ t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we;
+ end
+ 2'd3: begin
+ t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we;
+ end
+ 3'd4: begin
+ t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we;
+ end
+ 3'd5: begin
+ t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we;
+ end
+ 3'd6: begin
+ t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we;
+ end
+ default: begin
+ t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed12 <= 21'd0;
+ case (litedramcore_roundrobin0_grant)
+ default: begin
+ rhs_array_muxed12 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed13 <= 1'd0;
+ case (litedramcore_roundrobin0_grant)
+ default: begin
+ rhs_array_muxed13 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed14 <= 1'd0;
+ case (litedramcore_roundrobin0_grant)
+ default: begin
+ rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed15 <= 21'd0;
+ case (litedramcore_roundrobin1_grant)
+ default: begin
+ rhs_array_muxed15 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed16 <= 1'd0;
+ case (litedramcore_roundrobin1_grant)
+ default: begin
+ rhs_array_muxed16 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed17 <= 1'd0;
+ case (litedramcore_roundrobin1_grant)
+ default: begin
+ rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed18 <= 21'd0;
+ case (litedramcore_roundrobin2_grant)
+ default: begin
+ rhs_array_muxed18 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed19 <= 1'd0;
+ case (litedramcore_roundrobin2_grant)
+ default: begin
+ rhs_array_muxed19 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed20 <= 1'd0;
+ case (litedramcore_roundrobin2_grant)
+ default: begin
+ rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed21 <= 21'd0;
+ case (litedramcore_roundrobin3_grant)
+ default: begin
+ rhs_array_muxed21 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed22 <= 1'd0;
+ case (litedramcore_roundrobin3_grant)
+ default: begin
+ rhs_array_muxed22 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed23 <= 1'd0;
+ case (litedramcore_roundrobin3_grant)
+ default: begin
+ rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
end
always @(*) begin
- rhs_array_muxed24 <= 21'd0;
- case (litedramcore_roundrobin4_grant)
- default: begin
- rhs_array_muxed24 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed25 <= 1'd0;
- case (litedramcore_roundrobin4_grant)
- default: begin
- rhs_array_muxed25 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed26 <= 1'd0;
- case (litedramcore_roundrobin4_grant)
- default: begin
- rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed27 <= 21'd0;
- case (litedramcore_roundrobin5_grant)
- default: begin
- rhs_array_muxed27 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed28 <= 1'd0;
- case (litedramcore_roundrobin5_grant)
- default: begin
- rhs_array_muxed28 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed29 <= 1'd0;
- case (litedramcore_roundrobin5_grant)
- default: begin
- rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed30 <= 21'd0;
- case (litedramcore_roundrobin6_grant)
- default: begin
- rhs_array_muxed30 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed31 <= 1'd0;
- case (litedramcore_roundrobin6_grant)
- default: begin
- rhs_array_muxed31 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed32 <= 1'd0;
- case (litedramcore_roundrobin6_grant)
- default: begin
- rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed33 <= 21'd0;
- case (litedramcore_roundrobin7_grant)
- default: begin
- rhs_array_muxed33 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed34 <= 1'd0;
- case (litedramcore_roundrobin7_grant)
- default: begin
- rhs_array_muxed34 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed35 <= 1'd0;
- case (litedramcore_roundrobin7_grant)
- default: begin
- rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- array_muxed0 <= 3'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed0 <= litedramcore_nop_ba[2:0];
- end
- 1'd1: begin
- array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
- end
- 2'd2: begin
- array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0];
- end
- default: begin
- array_muxed0 <= litedramcore_cmd_payload_ba[2:0];
- end
- endcase
-end
-always @(*) begin
- array_muxed1 <= 14'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed1 <= litedramcore_nop_a;
- end
- 1'd1: begin
- array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a;
- end
- 2'd2: begin
- array_muxed1 <= litedramcore_choose_req_cmd_payload_a;
- end
- default: begin
- array_muxed1 <= litedramcore_cmd_payload_a;
- end
- endcase
-end
-always @(*) begin
- array_muxed2 <= 1'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed2 <= 1'd0;
- end
- 1'd1: begin
- array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
- end
- 2'd2: begin
- array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
- end
- default: begin
- array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
- end
- endcase
-end
-always @(*) begin
- array_muxed3 <= 1'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed3 <= 1'd0;
- end
- 1'd1: begin
- array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
- end
- 2'd2: begin
- array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
- end
- default: begin
- array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
- end
- endcase
-end
-always @(*) begin
- array_muxed4 <= 1'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed4 <= 1'd0;
- end
- 1'd1: begin
- array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
- end
- 2'd2: begin
- array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
- end
- default: begin
- array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
- end
- endcase
-end
-always @(*) begin
- array_muxed5 <= 1'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed5 <= 1'd0;
- end
- 1'd1: begin
- array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
- end
- 2'd2: begin
- array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
- end
- default: begin
- array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
- end
- endcase
-end
-always @(*) begin
- array_muxed6 <= 1'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed6 <= 1'd0;
- end
- 1'd1: begin
- array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
- end
- 2'd2: begin
- array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
- end
- default: begin
- array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
- end
- endcase
-end
-always @(*) begin
- array_muxed7 <= 3'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed7 <= litedramcore_nop_ba[2:0];
- end
- 1'd1: begin
- array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
- end
- 2'd2: begin
- array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0];
- end
- default: begin
- array_muxed7 <= litedramcore_cmd_payload_ba[2:0];
- end
- endcase
-end
-always @(*) begin
- array_muxed8 <= 14'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed8 <= litedramcore_nop_a;
- end
- 1'd1: begin
- array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a;
- end
- 2'd2: begin
- array_muxed8 <= litedramcore_choose_req_cmd_payload_a;
- end
- default: begin
- array_muxed8 <= litedramcore_cmd_payload_a;
- end
- endcase
-end
-always @(*) begin
- array_muxed9 <= 1'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed9 <= 1'd0;
- end
- 1'd1: begin
- array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
- end
- 2'd2: begin
- array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
- end
- default: begin
- array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
- end
- endcase
-end
-always @(*) begin
- array_muxed10 <= 1'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed10 <= 1'd0;
- end
- 1'd1: begin
- array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
- end
- 2'd2: begin
- array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
- end
- default: begin
- array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
- end
- endcase
-end
-always @(*) begin
- array_muxed11 <= 1'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed11 <= 1'd0;
- end
- 1'd1: begin
- array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
- end
- 2'd2: begin
- array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
- end
- default: begin
- array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
- end
- endcase
-end
-always @(*) begin
- array_muxed12 <= 1'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed12 <= 1'd0;
- end
- 1'd1: begin
- array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
- end
- 2'd2: begin
- array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
- end
- default: begin
- array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
- end
- endcase
-end
-always @(*) begin
- array_muxed13 <= 1'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed13 <= 1'd0;
- end
- 1'd1: begin
- array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
- end
- 2'd2: begin
- array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
- end
- default: begin
- array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
- end
- endcase
-end
-always @(*) begin
- array_muxed14 <= 3'd0;
- case (litedramcore_steerer_sel2)
- 1'd0: begin
- array_muxed14 <= litedramcore_nop_ba[2:0];
- end
- 1'd1: begin
- array_muxed14 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
- end
- 2'd2: begin
- array_muxed14 <= litedramcore_choose_req_cmd_payload_ba[2:0];
- end
- default: begin
- array_muxed14 <= litedramcore_cmd_payload_ba[2:0];
- end
- endcase
-end
-always @(*) begin
- array_muxed15 <= 14'd0;
- case (litedramcore_steerer_sel2)
- 1'd0: begin
- array_muxed15 <= litedramcore_nop_a;
- end
- 1'd1: begin
- array_muxed15 <= litedramcore_choose_cmd_cmd_payload_a;
- end
- 2'd2: begin
- array_muxed15 <= litedramcore_choose_req_cmd_payload_a;
- end
- default: begin
- array_muxed15 <= litedramcore_cmd_payload_a;
- end
- endcase
-end
-always @(*) begin
- array_muxed16 <= 1'd0;
- case (litedramcore_steerer_sel2)
- 1'd0: begin
- array_muxed16 <= 1'd0;
- end
- 1'd1: begin
- array_muxed16 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
- end
- 2'd2: begin
- array_muxed16 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
- end
- default: begin
- array_muxed16 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
- end
- endcase
-end
-always @(*) begin
- array_muxed17 <= 1'd0;
- case (litedramcore_steerer_sel2)
- 1'd0: begin
- array_muxed17 <= 1'd0;
- end
- 1'd1: begin
- array_muxed17 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
- end
- 2'd2: begin
- array_muxed17 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
- end
- default: begin
- array_muxed17 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
- end
- endcase
-end
-always @(*) begin
- array_muxed18 <= 1'd0;
- case (litedramcore_steerer_sel2)
- 1'd0: begin
- array_muxed18 <= 1'd0;
- end
- 1'd1: begin
- array_muxed18 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
- end
- 2'd2: begin
- array_muxed18 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
- end
- default: begin
- array_muxed18 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
- end
- endcase
-end
-always @(*) begin
- array_muxed19 <= 1'd0;
- case (litedramcore_steerer_sel2)
- 1'd0: begin
- array_muxed19 <= 1'd0;
- end
- 1'd1: begin
- array_muxed19 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
- end
- 2'd2: begin
- array_muxed19 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
- end
- default: begin
- array_muxed19 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
- end
- endcase
-end
-always @(*) begin
- array_muxed20 <= 1'd0;
- case (litedramcore_steerer_sel2)
- 1'd0: begin
- array_muxed20 <= 1'd0;
- end
- 1'd1: begin
- array_muxed20 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
- end
- 2'd2: begin
- array_muxed20 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
- end
- default: begin
- array_muxed20 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
- end
- endcase
-end
-always @(*) begin
- array_muxed21 <= 3'd0;
- case (litedramcore_steerer_sel3)
- 1'd0: begin
- array_muxed21 <= litedramcore_nop_ba[2:0];
- end
- 1'd1: begin
- array_muxed21 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
- end
- 2'd2: begin
- array_muxed21 <= litedramcore_choose_req_cmd_payload_ba[2:0];
- end
- default: begin
- array_muxed21 <= litedramcore_cmd_payload_ba[2:0];
- end
- endcase
-end
-always @(*) begin
- array_muxed22 <= 14'd0;
- case (litedramcore_steerer_sel3)
- 1'd0: begin
- array_muxed22 <= litedramcore_nop_a;
- end
- 1'd1: begin
- array_muxed22 <= litedramcore_choose_cmd_cmd_payload_a;
- end
- 2'd2: begin
- array_muxed22 <= litedramcore_choose_req_cmd_payload_a;
- end
- default: begin
- array_muxed22 <= litedramcore_cmd_payload_a;
- end
- endcase
-end
-always @(*) begin
- array_muxed23 <= 1'd0;
- case (litedramcore_steerer_sel3)
- 1'd0: begin
- array_muxed23 <= 1'd0;
- end
- 1'd1: begin
- array_muxed23 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
- end
- 2'd2: begin
- array_muxed23 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
- end
- default: begin
- array_muxed23 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
- end
- endcase
-end
-always @(*) begin
- array_muxed24 <= 1'd0;
- case (litedramcore_steerer_sel3)
- 1'd0: begin
- array_muxed24 <= 1'd0;
- end
- 1'd1: begin
- array_muxed24 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
- end
- 2'd2: begin
- array_muxed24 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
- end
- default: begin
- array_muxed24 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
- end
- endcase
-end
-always @(*) begin
- array_muxed25 <= 1'd0;
- case (litedramcore_steerer_sel3)
- 1'd0: begin
- array_muxed25 <= 1'd0;
- end
- 1'd1: begin
- array_muxed25 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
- end
- 2'd2: begin
- array_muxed25 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
- end
- default: begin
- array_muxed25 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
- end
- endcase
-end
-always @(*) begin
- array_muxed26 <= 1'd0;
- case (litedramcore_steerer_sel3)
- 1'd0: begin
- array_muxed26 <= 1'd0;
- end
- 1'd1: begin
- array_muxed26 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
- end
- 2'd2: begin
- array_muxed26 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
- end
- default: begin
- array_muxed26 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
- end
- endcase
-end
-always @(*) begin
- array_muxed27 <= 1'd0;
- case (litedramcore_steerer_sel3)
- 1'd0: begin
- array_muxed27 <= 1'd0;
- end
- 1'd1: begin
- array_muxed27 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
- end
- 2'd2: begin
- array_muxed27 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
- end
- default: begin
- array_muxed27 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
- end
- endcase
+ rhs_array_muxed24 <= 21'd0;
+ case (litedramcore_roundrobin4_grant)
+ default: begin
+ rhs_array_muxed24 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed25 <= 1'd0;
+ case (litedramcore_roundrobin4_grant)
+ default: begin
+ rhs_array_muxed25 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed26 <= 1'd0;
+ case (litedramcore_roundrobin4_grant)
+ default: begin
+ rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed27 <= 21'd0;
+ case (litedramcore_roundrobin5_grant)
+ default: begin
+ rhs_array_muxed27 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed28 <= 1'd0;
+ case (litedramcore_roundrobin5_grant)
+ default: begin
+ rhs_array_muxed28 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed29 <= 1'd0;
+ case (litedramcore_roundrobin5_grant)
+ default: begin
+ rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed30 <= 21'd0;
+ case (litedramcore_roundrobin6_grant)
+ default: begin
+ rhs_array_muxed30 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed31 <= 1'd0;
+ case (litedramcore_roundrobin6_grant)
+ default: begin
+ rhs_array_muxed31 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed32 <= 1'd0;
+ case (litedramcore_roundrobin6_grant)
+ default: begin
+ rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed33 <= 21'd0;
+ case (litedramcore_roundrobin7_grant)
+ default: begin
+ rhs_array_muxed33 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed34 <= 1'd0;
+ case (litedramcore_roundrobin7_grant)
+ default: begin
+ rhs_array_muxed34 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed35 <= 1'd0;
+ case (litedramcore_roundrobin7_grant)
+ default: begin
+ rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed0 <= 3'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed0 <= litedramcore_nop_ba[2:0];
+ end
+ 1'd1: begin
+ array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+ end
+ 2'd2: begin
+ array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+ end
+ default: begin
+ array_muxed0 <= litedramcore_cmd_payload_ba[2:0];
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed1 <= 14'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed1 <= litedramcore_nop_a;
+ end
+ 1'd1: begin
+ array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a;
+ end
+ 2'd2: begin
+ array_muxed1 <= litedramcore_choose_req_cmd_payload_a;
+ end
+ default: begin
+ array_muxed1 <= litedramcore_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed2 <= 1'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed2 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+ end
+ 2'd2: begin
+ array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+ end
+ default: begin
+ array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed3 <= 1'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed3 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+ end
+ 2'd2: begin
+ array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+ end
+ default: begin
+ array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed4 <= 1'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed4 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+ end
+ 2'd2: begin
+ array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+ end
+ default: begin
+ array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed5 <= 1'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed5 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+ end
+ 2'd2: begin
+ array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+ end
+ default: begin
+ array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed6 <= 1'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed6 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+ end
+ 2'd2: begin
+ array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+ end
+ default: begin
+ array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed7 <= 3'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed7 <= litedramcore_nop_ba[2:0];
+ end
+ 1'd1: begin
+ array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+ end
+ 2'd2: begin
+ array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+ end
+ default: begin
+ array_muxed7 <= litedramcore_cmd_payload_ba[2:0];
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed8 <= 14'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed8 <= litedramcore_nop_a;
+ end
+ 1'd1: begin
+ array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a;
+ end
+ 2'd2: begin
+ array_muxed8 <= litedramcore_choose_req_cmd_payload_a;
+ end
+ default: begin
+ array_muxed8 <= litedramcore_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed9 <= 1'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed9 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+ end
+ 2'd2: begin
+ array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+ end
+ default: begin
+ array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed10 <= 1'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed10 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+ end
+ 2'd2: begin
+ array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+ end
+ default: begin
+ array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed11 <= 1'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed11 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+ end
+ 2'd2: begin
+ array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+ end
+ default: begin
+ array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed12 <= 1'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed12 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+ end
+ 2'd2: begin
+ array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+ end
+ default: begin
+ array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed13 <= 1'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed13 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+ end
+ 2'd2: begin
+ array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+ end
+ default: begin
+ array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed14 <= 3'd0;
+ case (litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed14 <= litedramcore_nop_ba[2:0];
+ end
+ 1'd1: begin
+ array_muxed14 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+ end
+ 2'd2: begin
+ array_muxed14 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+ end
+ default: begin
+ array_muxed14 <= litedramcore_cmd_payload_ba[2:0];
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed15 <= 14'd0;
+ case (litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed15 <= litedramcore_nop_a;
+ end
+ 1'd1: begin
+ array_muxed15 <= litedramcore_choose_cmd_cmd_payload_a;
+ end
+ 2'd2: begin
+ array_muxed15 <= litedramcore_choose_req_cmd_payload_a;
+ end
+ default: begin
+ array_muxed15 <= litedramcore_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed16 <= 1'd0;
+ case (litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed16 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed16 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+ end
+ 2'd2: begin
+ array_muxed16 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+ end
+ default: begin
+ array_muxed16 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed17 <= 1'd0;
+ case (litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed17 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed17 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+ end
+ 2'd2: begin
+ array_muxed17 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+ end
+ default: begin
+ array_muxed17 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed18 <= 1'd0;
+ case (litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed18 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed18 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+ end
+ 2'd2: begin
+ array_muxed18 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+ end
+ default: begin
+ array_muxed18 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed19 <= 1'd0;
+ case (litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed19 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed19 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+ end
+ 2'd2: begin
+ array_muxed19 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+ end
+ default: begin
+ array_muxed19 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed20 <= 1'd0;
+ case (litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed20 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed20 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+ end
+ 2'd2: begin
+ array_muxed20 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+ end
+ default: begin
+ array_muxed20 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed21 <= 3'd0;
+ case (litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed21 <= litedramcore_nop_ba[2:0];
+ end
+ 1'd1: begin
+ array_muxed21 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+ end
+ 2'd2: begin
+ array_muxed21 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+ end
+ default: begin
+ array_muxed21 <= litedramcore_cmd_payload_ba[2:0];
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed22 <= 14'd0;
+ case (litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed22 <= litedramcore_nop_a;
+ end
+ 1'd1: begin
+ array_muxed22 <= litedramcore_choose_cmd_cmd_payload_a;
+ end
+ 2'd2: begin
+ array_muxed22 <= litedramcore_choose_req_cmd_payload_a;
+ end
+ default: begin
+ array_muxed22 <= litedramcore_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed23 <= 1'd0;
+ case (litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed23 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed23 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+ end
+ 2'd2: begin
+ array_muxed23 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+ end
+ default: begin
+ array_muxed23 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed24 <= 1'd0;
+ case (litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed24 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed24 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+ end
+ 2'd2: begin
+ array_muxed24 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+ end
+ default: begin
+ array_muxed24 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed25 <= 1'd0;
+ case (litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed25 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed25 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+ end
+ 2'd2: begin
+ array_muxed25 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+ end
+ default: begin
+ array_muxed25 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed26 <= 1'd0;
+ case (litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed26 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed26 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+ end
+ 2'd2: begin
+ array_muxed26 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+ end
+ default: begin
+ array_muxed26 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed27 <= 1'd0;
+ case (litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed27 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed27 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+ end
+ 2'd2: begin
+ array_muxed27 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+ end
+ default: begin
+ array_muxed27 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+ end
+ endcase
end
assign xilinxasyncresetsynchronizerimpl0 = (~locked);
assign xilinxasyncresetsynchronizerimpl1 = (~locked);
//------------------------------------------------------------------------------
always @(posedge iodelay_clk) begin
- if ((reset_counter != 1'd0)) begin
- reset_counter <= (reset_counter - 1'd1);
- end else begin
- ic_reset <= 1'd0;
- end
- if (iodelay_rst) begin
- reset_counter <= 4'd15;
- ic_reset <= 1'd1;
- end
+ if ((reset_counter != 1'd0)) begin
+ reset_counter <= (reset_counter - 1'd1);
+ end else begin
+ ic_reset <= 1'd0;
+ end
+ if (iodelay_rst) begin
+ reset_counter <= 4'd15;
+ ic_reset <= 1'd1;
+ end
end
always @(posedge sys_clk) begin
- a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dqs_oe_delay_tappeddelayline;
- a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0;
- a7ddrphy_dqspattern_o1 <= a7ddrphy_dqspattern_o0;
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip0_value0 <= (a7ddrphy_bitslip0_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip0_value0 <= 3'd7;
- end
- a7ddrphy_bitslip0_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip0_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip1_value0 <= (a7ddrphy_bitslip1_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip1_value0 <= 3'd7;
- end
- a7ddrphy_bitslip1_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip1_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip0_value1 <= (a7ddrphy_bitslip0_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip0_value1 <= 3'd7;
- end
- a7ddrphy_bitslip0_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[2], a7ddrphy_dfi_p3_wrdata_mask[0], a7ddrphy_dfi_p2_wrdata_mask[2], a7ddrphy_dfi_p2_wrdata_mask[0], a7ddrphy_dfi_p1_wrdata_mask[2], a7ddrphy_dfi_p1_wrdata_mask[0], a7ddrphy_dfi_p0_wrdata_mask[2], a7ddrphy_dfi_p0_wrdata_mask[0]}, a7ddrphy_bitslip0_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip1_value1 <= (a7ddrphy_bitslip1_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip1_value1 <= 3'd7;
- end
- a7ddrphy_bitslip1_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[3], a7ddrphy_dfi_p3_wrdata_mask[1], a7ddrphy_dfi_p2_wrdata_mask[3], a7ddrphy_dfi_p2_wrdata_mask[1], a7ddrphy_dfi_p1_wrdata_mask[3], a7ddrphy_dfi_p1_wrdata_mask[1], a7ddrphy_dfi_p0_wrdata_mask[3], a7ddrphy_dfi_p0_wrdata_mask[1]}, a7ddrphy_bitslip1_r1[15:8]};
- a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dq_oe_delay_tappeddelayline;
- a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0;
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip0_value2 <= (a7ddrphy_bitslip0_value2 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip0_value2 <= 3'd7;
- end
- a7ddrphy_bitslip0_r2 <= {{a7ddrphy_dfi_p3_wrdata[16], a7ddrphy_dfi_p3_wrdata[0], a7ddrphy_dfi_p2_wrdata[16], a7ddrphy_dfi_p2_wrdata[0], a7ddrphy_dfi_p1_wrdata[16], a7ddrphy_dfi_p1_wrdata[0], a7ddrphy_dfi_p0_wrdata[16], a7ddrphy_dfi_p0_wrdata[0]}, a7ddrphy_bitslip0_r2[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip0_value3 <= (a7ddrphy_bitslip0_value3 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip0_value3 <= 3'd7;
- end
- a7ddrphy_bitslip0_r3 <= {a7ddrphy_bitslip03, a7ddrphy_bitslip0_r3[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip1_value2 <= (a7ddrphy_bitslip1_value2 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip1_value2 <= 3'd7;
- end
- a7ddrphy_bitslip1_r2 <= {{a7ddrphy_dfi_p3_wrdata[17], a7ddrphy_dfi_p3_wrdata[1], a7ddrphy_dfi_p2_wrdata[17], a7ddrphy_dfi_p2_wrdata[1], a7ddrphy_dfi_p1_wrdata[17], a7ddrphy_dfi_p1_wrdata[1], a7ddrphy_dfi_p0_wrdata[17], a7ddrphy_dfi_p0_wrdata[1]}, a7ddrphy_bitslip1_r2[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip1_value3 <= (a7ddrphy_bitslip1_value3 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip1_value3 <= 3'd7;
- end
- a7ddrphy_bitslip1_r3 <= {a7ddrphy_bitslip13, a7ddrphy_bitslip1_r3[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip2_value0 <= (a7ddrphy_bitslip2_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip2_value0 <= 3'd7;
- end
- a7ddrphy_bitslip2_r0 <= {{a7ddrphy_dfi_p3_wrdata[18], a7ddrphy_dfi_p3_wrdata[2], a7ddrphy_dfi_p2_wrdata[18], a7ddrphy_dfi_p2_wrdata[2], a7ddrphy_dfi_p1_wrdata[18], a7ddrphy_dfi_p1_wrdata[2], a7ddrphy_dfi_p0_wrdata[18], a7ddrphy_dfi_p0_wrdata[2]}, a7ddrphy_bitslip2_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip2_value1 <= (a7ddrphy_bitslip2_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip2_value1 <= 3'd7;
- end
- a7ddrphy_bitslip2_r1 <= {a7ddrphy_bitslip21, a7ddrphy_bitslip2_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip3_value0 <= (a7ddrphy_bitslip3_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip3_value0 <= 3'd7;
- end
- a7ddrphy_bitslip3_r0 <= {{a7ddrphy_dfi_p3_wrdata[19], a7ddrphy_dfi_p3_wrdata[3], a7ddrphy_dfi_p2_wrdata[19], a7ddrphy_dfi_p2_wrdata[3], a7ddrphy_dfi_p1_wrdata[19], a7ddrphy_dfi_p1_wrdata[3], a7ddrphy_dfi_p0_wrdata[19], a7ddrphy_dfi_p0_wrdata[3]}, a7ddrphy_bitslip3_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip3_value1 <= (a7ddrphy_bitslip3_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip3_value1 <= 3'd7;
- end
- a7ddrphy_bitslip3_r1 <= {a7ddrphy_bitslip31, a7ddrphy_bitslip3_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip4_value0 <= (a7ddrphy_bitslip4_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip4_value0 <= 3'd7;
- end
- a7ddrphy_bitslip4_r0 <= {{a7ddrphy_dfi_p3_wrdata[20], a7ddrphy_dfi_p3_wrdata[4], a7ddrphy_dfi_p2_wrdata[20], a7ddrphy_dfi_p2_wrdata[4], a7ddrphy_dfi_p1_wrdata[20], a7ddrphy_dfi_p1_wrdata[4], a7ddrphy_dfi_p0_wrdata[20], a7ddrphy_dfi_p0_wrdata[4]}, a7ddrphy_bitslip4_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip4_value1 <= (a7ddrphy_bitslip4_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip4_value1 <= 3'd7;
- end
- a7ddrphy_bitslip4_r1 <= {a7ddrphy_bitslip41, a7ddrphy_bitslip4_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip5_value0 <= (a7ddrphy_bitslip5_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip5_value0 <= 3'd7;
- end
- a7ddrphy_bitslip5_r0 <= {{a7ddrphy_dfi_p3_wrdata[21], a7ddrphy_dfi_p3_wrdata[5], a7ddrphy_dfi_p2_wrdata[21], a7ddrphy_dfi_p2_wrdata[5], a7ddrphy_dfi_p1_wrdata[21], a7ddrphy_dfi_p1_wrdata[5], a7ddrphy_dfi_p0_wrdata[21], a7ddrphy_dfi_p0_wrdata[5]}, a7ddrphy_bitslip5_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip5_value1 <= (a7ddrphy_bitslip5_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip5_value1 <= 3'd7;
- end
- a7ddrphy_bitslip5_r1 <= {a7ddrphy_bitslip51, a7ddrphy_bitslip5_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip6_value0 <= (a7ddrphy_bitslip6_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip6_value0 <= 3'd7;
- end
- a7ddrphy_bitslip6_r0 <= {{a7ddrphy_dfi_p3_wrdata[22], a7ddrphy_dfi_p3_wrdata[6], a7ddrphy_dfi_p2_wrdata[22], a7ddrphy_dfi_p2_wrdata[6], a7ddrphy_dfi_p1_wrdata[22], a7ddrphy_dfi_p1_wrdata[6], a7ddrphy_dfi_p0_wrdata[22], a7ddrphy_dfi_p0_wrdata[6]}, a7ddrphy_bitslip6_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip6_value1 <= (a7ddrphy_bitslip6_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip6_value1 <= 3'd7;
- end
- a7ddrphy_bitslip6_r1 <= {a7ddrphy_bitslip61, a7ddrphy_bitslip6_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip7_value0 <= (a7ddrphy_bitslip7_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip7_value0 <= 3'd7;
- end
- a7ddrphy_bitslip7_r0 <= {{a7ddrphy_dfi_p3_wrdata[23], a7ddrphy_dfi_p3_wrdata[7], a7ddrphy_dfi_p2_wrdata[23], a7ddrphy_dfi_p2_wrdata[7], a7ddrphy_dfi_p1_wrdata[23], a7ddrphy_dfi_p1_wrdata[7], a7ddrphy_dfi_p0_wrdata[23], a7ddrphy_dfi_p0_wrdata[7]}, a7ddrphy_bitslip7_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip7_value1 <= (a7ddrphy_bitslip7_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip7_value1 <= 3'd7;
- end
- a7ddrphy_bitslip7_r1 <= {a7ddrphy_bitslip71, a7ddrphy_bitslip7_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip8_value0 <= (a7ddrphy_bitslip8_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip8_value0 <= 3'd7;
- end
- a7ddrphy_bitslip8_r0 <= {{a7ddrphy_dfi_p3_wrdata[24], a7ddrphy_dfi_p3_wrdata[8], a7ddrphy_dfi_p2_wrdata[24], a7ddrphy_dfi_p2_wrdata[8], a7ddrphy_dfi_p1_wrdata[24], a7ddrphy_dfi_p1_wrdata[8], a7ddrphy_dfi_p0_wrdata[24], a7ddrphy_dfi_p0_wrdata[8]}, a7ddrphy_bitslip8_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip8_value1 <= (a7ddrphy_bitslip8_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip8_value1 <= 3'd7;
- end
- a7ddrphy_bitslip8_r1 <= {a7ddrphy_bitslip81, a7ddrphy_bitslip8_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip9_value0 <= (a7ddrphy_bitslip9_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip9_value0 <= 3'd7;
- end
- a7ddrphy_bitslip9_r0 <= {{a7ddrphy_dfi_p3_wrdata[25], a7ddrphy_dfi_p3_wrdata[9], a7ddrphy_dfi_p2_wrdata[25], a7ddrphy_dfi_p2_wrdata[9], a7ddrphy_dfi_p1_wrdata[25], a7ddrphy_dfi_p1_wrdata[9], a7ddrphy_dfi_p0_wrdata[25], a7ddrphy_dfi_p0_wrdata[9]}, a7ddrphy_bitslip9_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip9_value1 <= (a7ddrphy_bitslip9_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip9_value1 <= 3'd7;
- end
- a7ddrphy_bitslip9_r1 <= {a7ddrphy_bitslip91, a7ddrphy_bitslip9_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip10_value0 <= (a7ddrphy_bitslip10_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip10_value0 <= 3'd7;
- end
- a7ddrphy_bitslip10_r0 <= {{a7ddrphy_dfi_p3_wrdata[26], a7ddrphy_dfi_p3_wrdata[10], a7ddrphy_dfi_p2_wrdata[26], a7ddrphy_dfi_p2_wrdata[10], a7ddrphy_dfi_p1_wrdata[26], a7ddrphy_dfi_p1_wrdata[10], a7ddrphy_dfi_p0_wrdata[26], a7ddrphy_dfi_p0_wrdata[10]}, a7ddrphy_bitslip10_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip10_value1 <= (a7ddrphy_bitslip10_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip10_value1 <= 3'd7;
- end
- a7ddrphy_bitslip10_r1 <= {a7ddrphy_bitslip101, a7ddrphy_bitslip10_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip11_value0 <= (a7ddrphy_bitslip11_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip11_value0 <= 3'd7;
- end
- a7ddrphy_bitslip11_r0 <= {{a7ddrphy_dfi_p3_wrdata[27], a7ddrphy_dfi_p3_wrdata[11], a7ddrphy_dfi_p2_wrdata[27], a7ddrphy_dfi_p2_wrdata[11], a7ddrphy_dfi_p1_wrdata[27], a7ddrphy_dfi_p1_wrdata[11], a7ddrphy_dfi_p0_wrdata[27], a7ddrphy_dfi_p0_wrdata[11]}, a7ddrphy_bitslip11_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip11_value1 <= (a7ddrphy_bitslip11_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip11_value1 <= 3'd7;
- end
- a7ddrphy_bitslip11_r1 <= {a7ddrphy_bitslip111, a7ddrphy_bitslip11_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip12_value0 <= (a7ddrphy_bitslip12_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip12_value0 <= 3'd7;
- end
- a7ddrphy_bitslip12_r0 <= {{a7ddrphy_dfi_p3_wrdata[28], a7ddrphy_dfi_p3_wrdata[12], a7ddrphy_dfi_p2_wrdata[28], a7ddrphy_dfi_p2_wrdata[12], a7ddrphy_dfi_p1_wrdata[28], a7ddrphy_dfi_p1_wrdata[12], a7ddrphy_dfi_p0_wrdata[28], a7ddrphy_dfi_p0_wrdata[12]}, a7ddrphy_bitslip12_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip12_value1 <= (a7ddrphy_bitslip12_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip12_value1 <= 3'd7;
- end
- a7ddrphy_bitslip12_r1 <= {a7ddrphy_bitslip121, a7ddrphy_bitslip12_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip13_value0 <= (a7ddrphy_bitslip13_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip13_value0 <= 3'd7;
- end
- a7ddrphy_bitslip13_r0 <= {{a7ddrphy_dfi_p3_wrdata[29], a7ddrphy_dfi_p3_wrdata[13], a7ddrphy_dfi_p2_wrdata[29], a7ddrphy_dfi_p2_wrdata[13], a7ddrphy_dfi_p1_wrdata[29], a7ddrphy_dfi_p1_wrdata[13], a7ddrphy_dfi_p0_wrdata[29], a7ddrphy_dfi_p0_wrdata[13]}, a7ddrphy_bitslip13_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip13_value1 <= (a7ddrphy_bitslip13_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip13_value1 <= 3'd7;
- end
- a7ddrphy_bitslip13_r1 <= {a7ddrphy_bitslip131, a7ddrphy_bitslip13_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip14_value0 <= (a7ddrphy_bitslip14_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip14_value0 <= 3'd7;
- end
- a7ddrphy_bitslip14_r0 <= {{a7ddrphy_dfi_p3_wrdata[30], a7ddrphy_dfi_p3_wrdata[14], a7ddrphy_dfi_p2_wrdata[30], a7ddrphy_dfi_p2_wrdata[14], a7ddrphy_dfi_p1_wrdata[30], a7ddrphy_dfi_p1_wrdata[14], a7ddrphy_dfi_p0_wrdata[30], a7ddrphy_dfi_p0_wrdata[14]}, a7ddrphy_bitslip14_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip14_value1 <= (a7ddrphy_bitslip14_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip14_value1 <= 3'd7;
- end
- a7ddrphy_bitslip14_r1 <= {a7ddrphy_bitslip141, a7ddrphy_bitslip14_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip15_value0 <= (a7ddrphy_bitslip15_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip15_value0 <= 3'd7;
- end
- a7ddrphy_bitslip15_r0 <= {{a7ddrphy_dfi_p3_wrdata[31], a7ddrphy_dfi_p3_wrdata[15], a7ddrphy_dfi_p2_wrdata[31], a7ddrphy_dfi_p2_wrdata[15], a7ddrphy_dfi_p1_wrdata[31], a7ddrphy_dfi_p1_wrdata[15], a7ddrphy_dfi_p0_wrdata[31], a7ddrphy_dfi_p0_wrdata[15]}, a7ddrphy_bitslip15_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip15_value1 <= (a7ddrphy_bitslip15_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip15_value1 <= 3'd7;
- end
- a7ddrphy_bitslip15_r1 <= {a7ddrphy_bitslip151, a7ddrphy_bitslip15_r1[15:8]};
- a7ddrphy_rddata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_rddata_en | a7ddrphy_dfi_p1_rddata_en) | a7ddrphy_dfi_p2_rddata_en) | a7ddrphy_dfi_p3_rddata_en);
- a7ddrphy_rddata_en_tappeddelayline1 <= a7ddrphy_rddata_en_tappeddelayline0;
- a7ddrphy_rddata_en_tappeddelayline2 <= a7ddrphy_rddata_en_tappeddelayline1;
- a7ddrphy_rddata_en_tappeddelayline3 <= a7ddrphy_rddata_en_tappeddelayline2;
- a7ddrphy_rddata_en_tappeddelayline4 <= a7ddrphy_rddata_en_tappeddelayline3;
- a7ddrphy_rddata_en_tappeddelayline5 <= a7ddrphy_rddata_en_tappeddelayline4;
- a7ddrphy_rddata_en_tappeddelayline6 <= a7ddrphy_rddata_en_tappeddelayline5;
- a7ddrphy_rddata_en_tappeddelayline7 <= a7ddrphy_rddata_en_tappeddelayline6;
- a7ddrphy_wrdata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_wrdata_en | a7ddrphy_dfi_p1_wrdata_en) | a7ddrphy_dfi_p2_wrdata_en) | a7ddrphy_dfi_p3_wrdata_en);
- a7ddrphy_wrdata_en_tappeddelayline1 <= a7ddrphy_wrdata_en_tappeddelayline0;
- a7ddrphy_wrdata_en_tappeddelayline2 <= a7ddrphy_wrdata_en_tappeddelayline1;
- if (litedramcore_csr_dfi_p0_rddata_valid) begin
- litedramcore_phaseinjector0_rddata_status <= litedramcore_csr_dfi_p0_rddata;
- end
- if (litedramcore_csr_dfi_p1_rddata_valid) begin
- litedramcore_phaseinjector1_rddata_status <= litedramcore_csr_dfi_p1_rddata;
- end
- if (litedramcore_csr_dfi_p2_rddata_valid) begin
- litedramcore_phaseinjector2_rddata_status <= litedramcore_csr_dfi_p2_rddata;
- end
- if (litedramcore_csr_dfi_p3_rddata_valid) begin
- litedramcore_phaseinjector3_rddata_status <= litedramcore_csr_dfi_p3_rddata;
- end
- if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin
- litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1);
- end else begin
- litedramcore_timer_count1 <= 10'd781;
- end
- litedramcore_postponer_req_o <= 1'd0;
- if (litedramcore_postponer_req_i) begin
- litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1);
- if ((litedramcore_postponer_count == 1'd0)) begin
- litedramcore_postponer_count <= 1'd0;
- litedramcore_postponer_req_o <= 1'd1;
- end
- end
- if (litedramcore_sequencer_start0) begin
- litedramcore_sequencer_count <= 1'd0;
- end else begin
- if (litedramcore_sequencer_done1) begin
- if ((litedramcore_sequencer_count != 1'd0)) begin
- litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1);
- end
- end
- end
- litedramcore_cmd_payload_a <= 1'd0;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd0;
- litedramcore_cmd_payload_we <= 1'd0;
- litedramcore_sequencer_done1 <= 1'd0;
- if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin
- litedramcore_cmd_payload_a <= 11'd1024;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd1;
- litedramcore_cmd_payload_we <= 1'd1;
- end
- if ((litedramcore_sequencer_counter == 2'd3)) begin
- litedramcore_cmd_payload_a <= 11'd1024;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd1;
- litedramcore_cmd_payload_ras <= 1'd1;
- litedramcore_cmd_payload_we <= 1'd0;
- end
- if ((litedramcore_sequencer_counter == 6'd35)) begin
- litedramcore_cmd_payload_a <= 1'd0;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd0;
- litedramcore_cmd_payload_we <= 1'd0;
- litedramcore_sequencer_done1 <= 1'd1;
- end
- if ((litedramcore_sequencer_counter == 6'd35)) begin
- litedramcore_sequencer_counter <= 1'd0;
- end else begin
- if ((litedramcore_sequencer_counter != 1'd0)) begin
- litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1);
- end else begin
- if (litedramcore_sequencer_start1) begin
- litedramcore_sequencer_counter <= 1'd1;
- end
- end
- end
- if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin
- litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1);
- end else begin
- litedramcore_zqcs_timer_count1 <= 27'd99999999;
- end
- litedramcore_zqcs_executer_done <= 1'd0;
- if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin
- litedramcore_cmd_payload_a <= 11'd1024;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd1;
- litedramcore_cmd_payload_we <= 1'd1;
- end
- if ((litedramcore_zqcs_executer_counter == 2'd3)) begin
- litedramcore_cmd_payload_a <= 1'd0;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd0;
- litedramcore_cmd_payload_we <= 1'd1;
- end
- if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
- litedramcore_cmd_payload_a <= 1'd0;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd0;
- litedramcore_cmd_payload_we <= 1'd0;
- litedramcore_zqcs_executer_done <= 1'd1;
- end
- if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
- litedramcore_zqcs_executer_counter <= 1'd0;
- end else begin
- if ((litedramcore_zqcs_executer_counter != 1'd0)) begin
- litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1);
- end else begin
- if (litedramcore_zqcs_executer_start) begin
- litedramcore_zqcs_executer_counter <= 1'd1;
- end
- end
- end
- litedramcore_refresher_state <= litedramcore_refresher_next_state;
- if (litedramcore_bankmachine0_row_close) begin
- litedramcore_bankmachine0_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine0_row_open) begin
- litedramcore_bankmachine0_row_opened <= 1'd1;
- litedramcore_bankmachine0_row <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7];
- end
- end
- if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine0_cmd_buffer_source_valid <= litedramcore_bankmachine0_cmd_buffer_sink_valid;
- litedramcore_bankmachine0_cmd_buffer_source_first <= litedramcore_bankmachine0_cmd_buffer_sink_first;
- litedramcore_bankmachine0_cmd_buffer_source_last <= litedramcore_bankmachine0_cmd_buffer_sink_last;
- litedramcore_bankmachine0_cmd_buffer_source_payload_we <= litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine0_twtpcon_valid) begin
- litedramcore_bankmachine0_twtpcon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine0_twtpcon_ready)) begin
- litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine0_trccon_valid) begin
- litedramcore_bankmachine0_trccon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine0_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine0_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine0_trccon_ready)) begin
- litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1);
- if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin
- litedramcore_bankmachine0_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine0_trascon_valid) begin
- litedramcore_bankmachine0_trascon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_bankmachine0_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine0_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1);
- if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin
- litedramcore_bankmachine0_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state;
- if (litedramcore_bankmachine1_row_close) begin
- litedramcore_bankmachine1_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine1_row_open) begin
- litedramcore_bankmachine1_row_opened <= 1'd1;
- litedramcore_bankmachine1_row <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7];
- end
- end
- if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine1_cmd_buffer_source_valid <= litedramcore_bankmachine1_cmd_buffer_sink_valid;
- litedramcore_bankmachine1_cmd_buffer_source_first <= litedramcore_bankmachine1_cmd_buffer_sink_first;
- litedramcore_bankmachine1_cmd_buffer_source_last <= litedramcore_bankmachine1_cmd_buffer_sink_last;
- litedramcore_bankmachine1_cmd_buffer_source_payload_we <= litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine1_twtpcon_valid) begin
- litedramcore_bankmachine1_twtpcon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine1_twtpcon_ready)) begin
- litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine1_trccon_valid) begin
- litedramcore_bankmachine1_trccon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine1_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine1_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine1_trccon_ready)) begin
- litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1);
- if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin
- litedramcore_bankmachine1_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine1_trascon_valid) begin
- litedramcore_bankmachine1_trascon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_bankmachine1_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine1_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1);
- if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin
- litedramcore_bankmachine1_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state;
- if (litedramcore_bankmachine2_row_close) begin
- litedramcore_bankmachine2_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine2_row_open) begin
- litedramcore_bankmachine2_row_opened <= 1'd1;
- litedramcore_bankmachine2_row <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7];
- end
- end
- if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine2_cmd_buffer_source_valid <= litedramcore_bankmachine2_cmd_buffer_sink_valid;
- litedramcore_bankmachine2_cmd_buffer_source_first <= litedramcore_bankmachine2_cmd_buffer_sink_first;
- litedramcore_bankmachine2_cmd_buffer_source_last <= litedramcore_bankmachine2_cmd_buffer_sink_last;
- litedramcore_bankmachine2_cmd_buffer_source_payload_we <= litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine2_twtpcon_valid) begin
- litedramcore_bankmachine2_twtpcon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine2_twtpcon_ready)) begin
- litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine2_trccon_valid) begin
- litedramcore_bankmachine2_trccon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine2_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine2_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine2_trccon_ready)) begin
- litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1);
- if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin
- litedramcore_bankmachine2_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine2_trascon_valid) begin
- litedramcore_bankmachine2_trascon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_bankmachine2_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine2_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1);
- if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin
- litedramcore_bankmachine2_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state;
- if (litedramcore_bankmachine3_row_close) begin
- litedramcore_bankmachine3_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine3_row_open) begin
- litedramcore_bankmachine3_row_opened <= 1'd1;
- litedramcore_bankmachine3_row <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7];
- end
- end
- if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine3_cmd_buffer_source_valid <= litedramcore_bankmachine3_cmd_buffer_sink_valid;
- litedramcore_bankmachine3_cmd_buffer_source_first <= litedramcore_bankmachine3_cmd_buffer_sink_first;
- litedramcore_bankmachine3_cmd_buffer_source_last <= litedramcore_bankmachine3_cmd_buffer_sink_last;
- litedramcore_bankmachine3_cmd_buffer_source_payload_we <= litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine3_twtpcon_valid) begin
- litedramcore_bankmachine3_twtpcon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine3_twtpcon_ready)) begin
- litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine3_trccon_valid) begin
- litedramcore_bankmachine3_trccon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine3_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine3_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine3_trccon_ready)) begin
- litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1);
- if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin
- litedramcore_bankmachine3_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine3_trascon_valid) begin
- litedramcore_bankmachine3_trascon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_bankmachine3_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine3_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1);
- if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin
- litedramcore_bankmachine3_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state;
- if (litedramcore_bankmachine4_row_close) begin
- litedramcore_bankmachine4_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine4_row_open) begin
- litedramcore_bankmachine4_row_opened <= 1'd1;
- litedramcore_bankmachine4_row <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7];
- end
- end
- if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine4_cmd_buffer_source_valid <= litedramcore_bankmachine4_cmd_buffer_sink_valid;
- litedramcore_bankmachine4_cmd_buffer_source_first <= litedramcore_bankmachine4_cmd_buffer_sink_first;
- litedramcore_bankmachine4_cmd_buffer_source_last <= litedramcore_bankmachine4_cmd_buffer_sink_last;
- litedramcore_bankmachine4_cmd_buffer_source_payload_we <= litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine4_twtpcon_valid) begin
- litedramcore_bankmachine4_twtpcon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine4_twtpcon_ready)) begin
- litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine4_trccon_valid) begin
- litedramcore_bankmachine4_trccon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine4_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine4_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine4_trccon_ready)) begin
- litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1);
- if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin
- litedramcore_bankmachine4_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine4_trascon_valid) begin
- litedramcore_bankmachine4_trascon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_bankmachine4_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine4_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1);
- if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin
- litedramcore_bankmachine4_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state;
- if (litedramcore_bankmachine5_row_close) begin
- litedramcore_bankmachine5_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine5_row_open) begin
- litedramcore_bankmachine5_row_opened <= 1'd1;
- litedramcore_bankmachine5_row <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7];
- end
- end
- if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine5_cmd_buffer_source_valid <= litedramcore_bankmachine5_cmd_buffer_sink_valid;
- litedramcore_bankmachine5_cmd_buffer_source_first <= litedramcore_bankmachine5_cmd_buffer_sink_first;
- litedramcore_bankmachine5_cmd_buffer_source_last <= litedramcore_bankmachine5_cmd_buffer_sink_last;
- litedramcore_bankmachine5_cmd_buffer_source_payload_we <= litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine5_twtpcon_valid) begin
- litedramcore_bankmachine5_twtpcon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine5_twtpcon_ready)) begin
- litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine5_trccon_valid) begin
- litedramcore_bankmachine5_trccon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine5_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine5_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine5_trccon_ready)) begin
- litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1);
- if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin
- litedramcore_bankmachine5_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine5_trascon_valid) begin
- litedramcore_bankmachine5_trascon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_bankmachine5_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine5_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1);
- if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin
- litedramcore_bankmachine5_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state;
- if (litedramcore_bankmachine6_row_close) begin
- litedramcore_bankmachine6_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine6_row_open) begin
- litedramcore_bankmachine6_row_opened <= 1'd1;
- litedramcore_bankmachine6_row <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7];
- end
- end
- if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine6_cmd_buffer_source_valid <= litedramcore_bankmachine6_cmd_buffer_sink_valid;
- litedramcore_bankmachine6_cmd_buffer_source_first <= litedramcore_bankmachine6_cmd_buffer_sink_first;
- litedramcore_bankmachine6_cmd_buffer_source_last <= litedramcore_bankmachine6_cmd_buffer_sink_last;
- litedramcore_bankmachine6_cmd_buffer_source_payload_we <= litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine6_twtpcon_valid) begin
- litedramcore_bankmachine6_twtpcon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine6_twtpcon_ready)) begin
- litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine6_trccon_valid) begin
- litedramcore_bankmachine6_trccon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine6_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine6_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine6_trccon_ready)) begin
- litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1);
- if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin
- litedramcore_bankmachine6_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine6_trascon_valid) begin
- litedramcore_bankmachine6_trascon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_bankmachine6_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine6_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1);
- if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin
- litedramcore_bankmachine6_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state;
- if (litedramcore_bankmachine7_row_close) begin
- litedramcore_bankmachine7_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine7_row_open) begin
- litedramcore_bankmachine7_row_opened <= 1'd1;
- litedramcore_bankmachine7_row <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7];
- end
- end
- if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine7_cmd_buffer_source_valid <= litedramcore_bankmachine7_cmd_buffer_sink_valid;
- litedramcore_bankmachine7_cmd_buffer_source_first <= litedramcore_bankmachine7_cmd_buffer_sink_first;
- litedramcore_bankmachine7_cmd_buffer_source_last <= litedramcore_bankmachine7_cmd_buffer_sink_last;
- litedramcore_bankmachine7_cmd_buffer_source_payload_we <= litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine7_twtpcon_valid) begin
- litedramcore_bankmachine7_twtpcon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine7_twtpcon_ready)) begin
- litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine7_trccon_valid) begin
- litedramcore_bankmachine7_trccon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine7_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine7_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine7_trccon_ready)) begin
- litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1);
- if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin
- litedramcore_bankmachine7_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine7_trascon_valid) begin
- litedramcore_bankmachine7_trascon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_bankmachine7_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine7_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1);
- if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin
- litedramcore_bankmachine7_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state;
- if ((~litedramcore_en0)) begin
- litedramcore_time0 <= 5'd31;
- end else begin
- if ((~litedramcore_max_time0)) begin
- litedramcore_time0 <= (litedramcore_time0 - 1'd1);
- end
- end
- if ((~litedramcore_en1)) begin
- litedramcore_time1 <= 4'd15;
- end else begin
- if ((~litedramcore_max_time1)) begin
- litedramcore_time1 <= (litedramcore_time1 - 1'd1);
- end
- end
- if (litedramcore_choose_cmd_ce) begin
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
- end
- end
- end
- end
- end
- end
- end
- end
- 1'd1: begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
- end
- end
- end
- end
- end
- end
- end
- end
- 2'd2: begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
- end
- end
- end
- end
- end
- end
- end
- end
- 2'd3: begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd4: begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd5: begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd6: begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd7: begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
- end
- end
- end
- end
- end
- end
- end
- end
- endcase
- end
- if (litedramcore_choose_req_ce) begin
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
- end
- end
- end
- end
- end
- end
- end
- end
- 1'd1: begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
- end
- end
- end
- end
- end
- end
- end
- end
- 2'd2: begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
- end
- end
- end
- end
- end
- end
- end
- end
- 2'd3: begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd4: begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd5: begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd6: begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd7: begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
- end
- end
- end
- end
- end
- end
- end
- end
- endcase
- end
- litedramcore_dfi_p0_cs_n <= 1'd0;
- litedramcore_dfi_p0_bank <= array_muxed0;
- litedramcore_dfi_p0_address <= array_muxed1;
- litedramcore_dfi_p0_cas_n <= (~array_muxed2);
- litedramcore_dfi_p0_ras_n <= (~array_muxed3);
- litedramcore_dfi_p0_we_n <= (~array_muxed4);
- litedramcore_dfi_p0_rddata_en <= array_muxed5;
- litedramcore_dfi_p0_wrdata_en <= array_muxed6;
- litedramcore_dfi_p1_cs_n <= 1'd0;
- litedramcore_dfi_p1_bank <= array_muxed7;
- litedramcore_dfi_p1_address <= array_muxed8;
- litedramcore_dfi_p1_cas_n <= (~array_muxed9);
- litedramcore_dfi_p1_ras_n <= (~array_muxed10);
- litedramcore_dfi_p1_we_n <= (~array_muxed11);
- litedramcore_dfi_p1_rddata_en <= array_muxed12;
- litedramcore_dfi_p1_wrdata_en <= array_muxed13;
- litedramcore_dfi_p2_cs_n <= 1'd0;
- litedramcore_dfi_p2_bank <= array_muxed14;
- litedramcore_dfi_p2_address <= array_muxed15;
- litedramcore_dfi_p2_cas_n <= (~array_muxed16);
- litedramcore_dfi_p2_ras_n <= (~array_muxed17);
- litedramcore_dfi_p2_we_n <= (~array_muxed18);
- litedramcore_dfi_p2_rddata_en <= array_muxed19;
- litedramcore_dfi_p2_wrdata_en <= array_muxed20;
- litedramcore_dfi_p3_cs_n <= 1'd0;
- litedramcore_dfi_p3_bank <= array_muxed21;
- litedramcore_dfi_p3_address <= array_muxed22;
- litedramcore_dfi_p3_cas_n <= (~array_muxed23);
- litedramcore_dfi_p3_ras_n <= (~array_muxed24);
- litedramcore_dfi_p3_we_n <= (~array_muxed25);
- litedramcore_dfi_p3_rddata_en <= array_muxed26;
- litedramcore_dfi_p3_wrdata_en <= array_muxed27;
- if (litedramcore_trrdcon_valid) begin
- litedramcore_trrdcon_count <= 1'd1;
- if (1'd0) begin
- litedramcore_trrdcon_ready <= 1'd1;
- end else begin
- litedramcore_trrdcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_trrdcon_ready)) begin
- litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1);
- if ((litedramcore_trrdcon_count == 1'd1)) begin
- litedramcore_trrdcon_ready <= 1'd1;
- end
- end
- end
- litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid};
- if ((litedramcore_tfawcon_count < 3'd4)) begin
- if ((litedramcore_tfawcon_count == 2'd3)) begin
- litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid);
- end else begin
- litedramcore_tfawcon_ready <= 1'd1;
- end
- end
- if (litedramcore_tccdcon_valid) begin
- litedramcore_tccdcon_count <= 1'd0;
- if (1'd1) begin
- litedramcore_tccdcon_ready <= 1'd1;
- end else begin
- litedramcore_tccdcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_tccdcon_ready)) begin
- litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1);
- if ((litedramcore_tccdcon_count == 1'd1)) begin
- litedramcore_tccdcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_twtrcon_valid) begin
- litedramcore_twtrcon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_twtrcon_ready <= 1'd1;
- end else begin
- litedramcore_twtrcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_twtrcon_ready)) begin
- litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1);
- if ((litedramcore_twtrcon_count == 1'd1)) begin
- litedramcore_twtrcon_ready <= 1'd1;
- end
- end
- end
- litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state;
- litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready));
- litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0;
- litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid));
- litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0;
- litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1;
- litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2;
- litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3;
- litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4;
- litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5;
- litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6;
- litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7;
- litedramcore_state <= litedramcore_next_state;
- if (litedramcore_dat_w_next_value_ce0) begin
- litedramcore_dat_w <= litedramcore_dat_w_next_value0;
- end
- if (litedramcore_adr_next_value_ce1) begin
- litedramcore_adr <= litedramcore_adr_next_value1;
- end
- if (litedramcore_we_next_value_ce2) begin
- litedramcore_we <= litedramcore_we_next_value2;
- end
- interface0_bank_bus_dat_r <= 1'd0;
- if (csrbank0_sel) begin
- case (interface0_bank_bus_adr[8:0])
- 1'd0: begin
- interface0_bank_bus_dat_r <= csrbank0_init_done0_w;
- end
- 1'd1: begin
- interface0_bank_bus_dat_r <= csrbank0_init_error0_w;
- end
- endcase
- end
- if (csrbank0_init_done0_re) begin
- init_done_storage <= csrbank0_init_done0_r;
- end
- init_done_re <= csrbank0_init_done0_re;
- if (csrbank0_init_error0_re) begin
- init_error_storage <= csrbank0_init_error0_r;
- end
- init_error_re <= csrbank0_init_error0_re;
- interface1_bank_bus_dat_r <= 1'd0;
- if (csrbank1_sel) begin
- case (interface1_bank_bus_adr[8:0])
- 1'd0: begin
- interface1_bank_bus_dat_r <= csrbank1_rst0_w;
- end
- 1'd1: begin
- interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w;
- end
- 2'd2: begin
- interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w;
- end
- 2'd3: begin
- interface1_bank_bus_dat_r <= csrbank1_wlevel_en0_w;
- end
- 3'd4: begin
- interface1_bank_bus_dat_r <= a7ddrphy_wlevel_strobe_w;
- end
- 3'd5: begin
- interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_rst_w;
- end
- 3'd6: begin
- interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_inc_w;
- end
- 3'd7: begin
- interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_rst_w;
- end
- 4'd8: begin
- interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_w;
- end
- 4'd9: begin
- interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_rst_w;
- end
- 4'd10: begin
- interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_w;
- end
- 4'd11: begin
- interface1_bank_bus_dat_r <= csrbank1_rdphase0_w;
- end
- 4'd12: begin
- interface1_bank_bus_dat_r <= csrbank1_wrphase0_w;
- end
- endcase
- end
- if (csrbank1_rst0_re) begin
- a7ddrphy_rst_storage <= csrbank1_rst0_r;
- end
- a7ddrphy_rst_re <= csrbank1_rst0_re;
- if (csrbank1_dly_sel0_re) begin
- a7ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r;
- end
- a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re;
- if (csrbank1_half_sys8x_taps0_re) begin
- a7ddrphy_half_sys8x_taps_storage[4:0] <= csrbank1_half_sys8x_taps0_r;
- end
- a7ddrphy_half_sys8x_taps_re <= csrbank1_half_sys8x_taps0_re;
- if (csrbank1_wlevel_en0_re) begin
- a7ddrphy_wlevel_en_storage <= csrbank1_wlevel_en0_r;
- end
- a7ddrphy_wlevel_en_re <= csrbank1_wlevel_en0_re;
- if (csrbank1_rdphase0_re) begin
- a7ddrphy_rdphase_storage[1:0] <= csrbank1_rdphase0_r;
- end
- a7ddrphy_rdphase_re <= csrbank1_rdphase0_re;
- if (csrbank1_wrphase0_re) begin
- a7ddrphy_wrphase_storage[1:0] <= csrbank1_wrphase0_r;
- end
- a7ddrphy_wrphase_re <= csrbank1_wrphase0_re;
- interface2_bank_bus_dat_r <= 1'd0;
- if (csrbank2_sel) begin
- case (interface2_bank_bus_adr[8:0])
- 1'd0: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w;
- end
- 1'd1: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w;
- end
- 2'd2: begin
- interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w;
- end
- 2'd3: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w;
- end
- 3'd4: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w;
- end
- 3'd5: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w;
- end
- 3'd6: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata_w;
- end
- 3'd7: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w;
- end
- 4'd8: begin
- interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w;
- end
- 4'd9: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w;
- end
- 4'd10: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w;
- end
- 4'd11: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w;
- end
- 4'd12: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata_w;
- end
- 4'd13: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w;
- end
- 4'd14: begin
- interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w;
- end
- 4'd15: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w;
- end
- 5'd16: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w;
- end
- 5'd17: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w;
- end
- 5'd18: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata_w;
- end
- 5'd19: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w;
- end
- 5'd20: begin
- interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w;
- end
- 5'd21: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w;
- end
- 5'd22: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w;
- end
- 5'd23: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w;
- end
- 5'd24: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata_w;
- end
- endcase
- end
- if (csrbank2_dfii_control0_re) begin
- litedramcore_storage[3:0] <= csrbank2_dfii_control0_r;
- end
- litedramcore_re <= csrbank2_dfii_control0_re;
- if (csrbank2_dfii_pi0_command0_re) begin
- litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r;
- end
- litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re;
- if (csrbank2_dfii_pi0_address0_re) begin
- litedramcore_phaseinjector0_address_storage[13:0] <= csrbank2_dfii_pi0_address0_r;
- end
- litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re;
- if (csrbank2_dfii_pi0_baddress0_re) begin
- litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r;
- end
- litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re;
- if (csrbank2_dfii_pi0_wrdata0_re) begin
- litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r;
- end
- litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re;
- litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata_re;
- if (csrbank2_dfii_pi1_command0_re) begin
- litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r;
- end
- litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re;
- if (csrbank2_dfii_pi1_address0_re) begin
- litedramcore_phaseinjector1_address_storage[13:0] <= csrbank2_dfii_pi1_address0_r;
- end
- litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re;
- if (csrbank2_dfii_pi1_baddress0_re) begin
- litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r;
- end
- litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re;
- if (csrbank2_dfii_pi1_wrdata0_re) begin
- litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r;
- end
- litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re;
- litedramcore_phaseinjector1_rddata_re <= csrbank2_dfii_pi1_rddata_re;
- if (csrbank2_dfii_pi2_command0_re) begin
- litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r;
- end
- litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re;
- if (csrbank2_dfii_pi2_address0_re) begin
- litedramcore_phaseinjector2_address_storage[13:0] <= csrbank2_dfii_pi2_address0_r;
- end
- litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re;
- if (csrbank2_dfii_pi2_baddress0_re) begin
- litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r;
- end
- litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re;
- if (csrbank2_dfii_pi2_wrdata0_re) begin
- litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r;
- end
- litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re;
- litedramcore_phaseinjector2_rddata_re <= csrbank2_dfii_pi2_rddata_re;
- if (csrbank2_dfii_pi3_command0_re) begin
- litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r;
- end
- litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re;
- if (csrbank2_dfii_pi3_address0_re) begin
- litedramcore_phaseinjector3_address_storage[13:0] <= csrbank2_dfii_pi3_address0_r;
- end
- litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re;
- if (csrbank2_dfii_pi3_baddress0_re) begin
- litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r;
- end
- litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re;
- if (csrbank2_dfii_pi3_wrdata0_re) begin
- litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r;
- end
- litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re;
- litedramcore_phaseinjector3_rddata_re <= csrbank2_dfii_pi3_rddata_re;
- if (sys_rst) begin
- a7ddrphy_rst_storage <= 1'd0;
- a7ddrphy_rst_re <= 1'd0;
- a7ddrphy_dly_sel_storage <= 2'd0;
- a7ddrphy_dly_sel_re <= 1'd0;
- a7ddrphy_half_sys8x_taps_storage <= 5'd8;
- a7ddrphy_half_sys8x_taps_re <= 1'd0;
- a7ddrphy_wlevel_en_storage <= 1'd0;
- a7ddrphy_wlevel_en_re <= 1'd0;
- a7ddrphy_rdphase_storage <= 2'd2;
- a7ddrphy_rdphase_re <= 1'd0;
- a7ddrphy_wrphase_storage <= 2'd3;
- a7ddrphy_wrphase_re <= 1'd0;
- a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
- a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
- a7ddrphy_dqspattern_o1 <= 8'd0;
- a7ddrphy_bitslip0_value0 <= 3'd7;
- a7ddrphy_bitslip1_value0 <= 3'd7;
- a7ddrphy_bitslip0_value1 <= 3'd7;
- a7ddrphy_bitslip1_value1 <= 3'd7;
- a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
- a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
- a7ddrphy_bitslip0_value2 <= 3'd7;
- a7ddrphy_bitslip0_value3 <= 3'd7;
- a7ddrphy_bitslip1_value2 <= 3'd7;
- a7ddrphy_bitslip1_value3 <= 3'd7;
- a7ddrphy_bitslip2_value0 <= 3'd7;
- a7ddrphy_bitslip2_value1 <= 3'd7;
- a7ddrphy_bitslip3_value0 <= 3'd7;
- a7ddrphy_bitslip3_value1 <= 3'd7;
- a7ddrphy_bitslip4_value0 <= 3'd7;
- a7ddrphy_bitslip4_value1 <= 3'd7;
- a7ddrphy_bitslip5_value0 <= 3'd7;
- a7ddrphy_bitslip5_value1 <= 3'd7;
- a7ddrphy_bitslip6_value0 <= 3'd7;
- a7ddrphy_bitslip6_value1 <= 3'd7;
- a7ddrphy_bitslip7_value0 <= 3'd7;
- a7ddrphy_bitslip7_value1 <= 3'd7;
- a7ddrphy_bitslip8_value0 <= 3'd7;
- a7ddrphy_bitslip8_value1 <= 3'd7;
- a7ddrphy_bitslip9_value0 <= 3'd7;
- a7ddrphy_bitslip9_value1 <= 3'd7;
- a7ddrphy_bitslip10_value0 <= 3'd7;
- a7ddrphy_bitslip10_value1 <= 3'd7;
- a7ddrphy_bitslip11_value0 <= 3'd7;
- a7ddrphy_bitslip11_value1 <= 3'd7;
- a7ddrphy_bitslip12_value0 <= 3'd7;
- a7ddrphy_bitslip12_value1 <= 3'd7;
- a7ddrphy_bitslip13_value0 <= 3'd7;
- a7ddrphy_bitslip13_value1 <= 3'd7;
- a7ddrphy_bitslip14_value0 <= 3'd7;
- a7ddrphy_bitslip14_value1 <= 3'd7;
- a7ddrphy_bitslip15_value0 <= 3'd7;
- a7ddrphy_bitslip15_value1 <= 3'd7;
- a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0;
- a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0;
- a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0;
- a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0;
- a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0;
- a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0;
- a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0;
- a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0;
- a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0;
- a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0;
- a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0;
- litedramcore_storage <= 4'd1;
- litedramcore_re <= 1'd0;
- litedramcore_phaseinjector0_command_storage <= 6'd0;
- litedramcore_phaseinjector0_command_re <= 1'd0;
- litedramcore_phaseinjector0_address_re <= 1'd0;
- litedramcore_phaseinjector0_baddress_re <= 1'd0;
- litedramcore_phaseinjector0_wrdata_re <= 1'd0;
- litedramcore_phaseinjector0_rddata_status <= 32'd0;
- litedramcore_phaseinjector0_rddata_re <= 1'd0;
- litedramcore_phaseinjector1_command_storage <= 6'd0;
- litedramcore_phaseinjector1_command_re <= 1'd0;
- litedramcore_phaseinjector1_address_re <= 1'd0;
- litedramcore_phaseinjector1_baddress_re <= 1'd0;
- litedramcore_phaseinjector1_wrdata_re <= 1'd0;
- litedramcore_phaseinjector1_rddata_status <= 32'd0;
- litedramcore_phaseinjector1_rddata_re <= 1'd0;
- litedramcore_phaseinjector2_command_storage <= 6'd0;
- litedramcore_phaseinjector2_command_re <= 1'd0;
- litedramcore_phaseinjector2_address_re <= 1'd0;
- litedramcore_phaseinjector2_baddress_re <= 1'd0;
- litedramcore_phaseinjector2_wrdata_re <= 1'd0;
- litedramcore_phaseinjector2_rddata_status <= 32'd0;
- litedramcore_phaseinjector2_rddata_re <= 1'd0;
- litedramcore_phaseinjector3_command_storage <= 6'd0;
- litedramcore_phaseinjector3_command_re <= 1'd0;
- litedramcore_phaseinjector3_address_re <= 1'd0;
- litedramcore_phaseinjector3_baddress_re <= 1'd0;
- litedramcore_phaseinjector3_wrdata_re <= 1'd0;
- litedramcore_phaseinjector3_rddata_status <= 32'd0;
- litedramcore_phaseinjector3_rddata_re <= 1'd0;
- litedramcore_dfi_p0_address <= 14'd0;
- litedramcore_dfi_p0_bank <= 3'd0;
- litedramcore_dfi_p0_cas_n <= 1'd1;
- litedramcore_dfi_p0_cs_n <= 1'd1;
- litedramcore_dfi_p0_ras_n <= 1'd1;
- litedramcore_dfi_p0_we_n <= 1'd1;
- litedramcore_dfi_p0_wrdata_en <= 1'd0;
- litedramcore_dfi_p0_rddata_en <= 1'd0;
- litedramcore_dfi_p1_address <= 14'd0;
- litedramcore_dfi_p1_bank <= 3'd0;
- litedramcore_dfi_p1_cas_n <= 1'd1;
- litedramcore_dfi_p1_cs_n <= 1'd1;
- litedramcore_dfi_p1_ras_n <= 1'd1;
- litedramcore_dfi_p1_we_n <= 1'd1;
- litedramcore_dfi_p1_wrdata_en <= 1'd0;
- litedramcore_dfi_p1_rddata_en <= 1'd0;
- litedramcore_dfi_p2_address <= 14'd0;
- litedramcore_dfi_p2_bank <= 3'd0;
- litedramcore_dfi_p2_cas_n <= 1'd1;
- litedramcore_dfi_p2_cs_n <= 1'd1;
- litedramcore_dfi_p2_ras_n <= 1'd1;
- litedramcore_dfi_p2_we_n <= 1'd1;
- litedramcore_dfi_p2_wrdata_en <= 1'd0;
- litedramcore_dfi_p2_rddata_en <= 1'd0;
- litedramcore_dfi_p3_address <= 14'd0;
- litedramcore_dfi_p3_bank <= 3'd0;
- litedramcore_dfi_p3_cas_n <= 1'd1;
- litedramcore_dfi_p3_cs_n <= 1'd1;
- litedramcore_dfi_p3_ras_n <= 1'd1;
- litedramcore_dfi_p3_we_n <= 1'd1;
- litedramcore_dfi_p3_wrdata_en <= 1'd0;
- litedramcore_dfi_p3_rddata_en <= 1'd0;
- litedramcore_cmd_payload_a <= 14'd0;
- litedramcore_cmd_payload_ba <= 3'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd0;
- litedramcore_cmd_payload_we <= 1'd0;
- litedramcore_timer_count1 <= 10'd781;
- litedramcore_postponer_req_o <= 1'd0;
- litedramcore_postponer_count <= 1'd0;
- litedramcore_sequencer_done1 <= 1'd0;
- litedramcore_sequencer_counter <= 6'd0;
- litedramcore_sequencer_count <= 1'd0;
- litedramcore_zqcs_timer_count1 <= 27'd99999999;
- litedramcore_zqcs_executer_done <= 1'd0;
- litedramcore_zqcs_executer_counter <= 5'd0;
- litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine0_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= 21'd0;
- litedramcore_bankmachine0_row <= 14'd0;
- litedramcore_bankmachine0_row_opened <= 1'd0;
- litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine0_twtpcon_count <= 3'd0;
- litedramcore_bankmachine0_trccon_ready <= 1'd0;
- litedramcore_bankmachine0_trccon_count <= 3'd0;
- litedramcore_bankmachine0_trascon_ready <= 1'd0;
- litedramcore_bankmachine0_trascon_count <= 3'd0;
- litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine1_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= 21'd0;
- litedramcore_bankmachine1_row <= 14'd0;
- litedramcore_bankmachine1_row_opened <= 1'd0;
- litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine1_twtpcon_count <= 3'd0;
- litedramcore_bankmachine1_trccon_ready <= 1'd0;
- litedramcore_bankmachine1_trccon_count <= 3'd0;
- litedramcore_bankmachine1_trascon_ready <= 1'd0;
- litedramcore_bankmachine1_trascon_count <= 3'd0;
- litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine2_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= 21'd0;
- litedramcore_bankmachine2_row <= 14'd0;
- litedramcore_bankmachine2_row_opened <= 1'd0;
- litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine2_twtpcon_count <= 3'd0;
- litedramcore_bankmachine2_trccon_ready <= 1'd0;
- litedramcore_bankmachine2_trccon_count <= 3'd0;
- litedramcore_bankmachine2_trascon_ready <= 1'd0;
- litedramcore_bankmachine2_trascon_count <= 3'd0;
- litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine3_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= 21'd0;
- litedramcore_bankmachine3_row <= 14'd0;
- litedramcore_bankmachine3_row_opened <= 1'd0;
- litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine3_twtpcon_count <= 3'd0;
- litedramcore_bankmachine3_trccon_ready <= 1'd0;
- litedramcore_bankmachine3_trccon_count <= 3'd0;
- litedramcore_bankmachine3_trascon_ready <= 1'd0;
- litedramcore_bankmachine3_trascon_count <= 3'd0;
- litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine4_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= 21'd0;
- litedramcore_bankmachine4_row <= 14'd0;
- litedramcore_bankmachine4_row_opened <= 1'd0;
- litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine4_twtpcon_count <= 3'd0;
- litedramcore_bankmachine4_trccon_ready <= 1'd0;
- litedramcore_bankmachine4_trccon_count <= 3'd0;
- litedramcore_bankmachine4_trascon_ready <= 1'd0;
- litedramcore_bankmachine4_trascon_count <= 3'd0;
- litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine5_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= 21'd0;
- litedramcore_bankmachine5_row <= 14'd0;
- litedramcore_bankmachine5_row_opened <= 1'd0;
- litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine5_twtpcon_count <= 3'd0;
- litedramcore_bankmachine5_trccon_ready <= 1'd0;
- litedramcore_bankmachine5_trccon_count <= 3'd0;
- litedramcore_bankmachine5_trascon_ready <= 1'd0;
- litedramcore_bankmachine5_trascon_count <= 3'd0;
- litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine6_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= 21'd0;
- litedramcore_bankmachine6_row <= 14'd0;
- litedramcore_bankmachine6_row_opened <= 1'd0;
- litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine6_twtpcon_count <= 3'd0;
- litedramcore_bankmachine6_trccon_ready <= 1'd0;
- litedramcore_bankmachine6_trccon_count <= 3'd0;
- litedramcore_bankmachine6_trascon_ready <= 1'd0;
- litedramcore_bankmachine6_trascon_count <= 3'd0;
- litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine7_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= 21'd0;
- litedramcore_bankmachine7_row <= 14'd0;
- litedramcore_bankmachine7_row_opened <= 1'd0;
- litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine7_twtpcon_count <= 3'd0;
- litedramcore_bankmachine7_trccon_ready <= 1'd0;
- litedramcore_bankmachine7_trccon_count <= 3'd0;
- litedramcore_bankmachine7_trascon_ready <= 1'd0;
- litedramcore_bankmachine7_trascon_count <= 3'd0;
- litedramcore_choose_cmd_grant <= 3'd0;
- litedramcore_choose_req_grant <= 3'd0;
- litedramcore_trrdcon_ready <= 1'd0;
- litedramcore_trrdcon_count <= 1'd0;
- litedramcore_tfawcon_ready <= 1'd1;
- litedramcore_tfawcon_window <= 5'd0;
- litedramcore_tccdcon_ready <= 1'd0;
- litedramcore_tccdcon_count <= 1'd0;
- litedramcore_twtrcon_ready <= 1'd0;
- litedramcore_twtrcon_count <= 3'd0;
- litedramcore_time0 <= 5'd0;
- litedramcore_time1 <= 4'd0;
- init_done_storage <= 1'd0;
- init_done_re <= 1'd0;
- init_error_storage <= 1'd0;
- init_error_re <= 1'd0;
- litedramcore_we <= 1'd0;
- litedramcore_refresher_state <= 2'd0;
- litedramcore_bankmachine0_state <= 4'd0;
- litedramcore_bankmachine1_state <= 4'd0;
- litedramcore_bankmachine2_state <= 4'd0;
- litedramcore_bankmachine3_state <= 4'd0;
- litedramcore_bankmachine4_state <= 4'd0;
- litedramcore_bankmachine5_state <= 4'd0;
- litedramcore_bankmachine6_state <= 4'd0;
- litedramcore_bankmachine7_state <= 4'd0;
- litedramcore_multiplexer_state <= 4'd0;
- litedramcore_new_master_wdata_ready0 <= 1'd0;
- litedramcore_new_master_wdata_ready1 <= 1'd0;
- litedramcore_new_master_rdata_valid0 <= 1'd0;
- litedramcore_new_master_rdata_valid1 <= 1'd0;
- litedramcore_new_master_rdata_valid2 <= 1'd0;
- litedramcore_new_master_rdata_valid3 <= 1'd0;
- litedramcore_new_master_rdata_valid4 <= 1'd0;
- litedramcore_new_master_rdata_valid5 <= 1'd0;
- litedramcore_new_master_rdata_valid6 <= 1'd0;
- litedramcore_new_master_rdata_valid7 <= 1'd0;
- litedramcore_new_master_rdata_valid8 <= 1'd0;
- litedramcore_state <= 2'd0;
- end
+ a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dqs_oe_delay_tappeddelayline;
+ a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0;
+ a7ddrphy_dqspattern_o1 <= a7ddrphy_dqspattern_o0;
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip0_value0 <= (a7ddrphy_bitslip0_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip0_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip0_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip0_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip1_value0 <= (a7ddrphy_bitslip1_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip1_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip1_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip1_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip0_value1 <= (a7ddrphy_bitslip0_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip0_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip0_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[2], a7ddrphy_dfi_p3_wrdata_mask[0], a7ddrphy_dfi_p2_wrdata_mask[2], a7ddrphy_dfi_p2_wrdata_mask[0], a7ddrphy_dfi_p1_wrdata_mask[2], a7ddrphy_dfi_p1_wrdata_mask[0], a7ddrphy_dfi_p0_wrdata_mask[2], a7ddrphy_dfi_p0_wrdata_mask[0]}, a7ddrphy_bitslip0_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip1_value1 <= (a7ddrphy_bitslip1_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip1_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip1_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[3], a7ddrphy_dfi_p3_wrdata_mask[1], a7ddrphy_dfi_p2_wrdata_mask[3], a7ddrphy_dfi_p2_wrdata_mask[1], a7ddrphy_dfi_p1_wrdata_mask[3], a7ddrphy_dfi_p1_wrdata_mask[1], a7ddrphy_dfi_p0_wrdata_mask[3], a7ddrphy_dfi_p0_wrdata_mask[1]}, a7ddrphy_bitslip1_r1[15:8]};
+ a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dq_oe_delay_tappeddelayline;
+ a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0;
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip0_value2 <= (a7ddrphy_bitslip0_value2 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip0_value2 <= 3'd7;
+ end
+ a7ddrphy_bitslip0_r2 <= {{a7ddrphy_dfi_p3_wrdata[16], a7ddrphy_dfi_p3_wrdata[0], a7ddrphy_dfi_p2_wrdata[16], a7ddrphy_dfi_p2_wrdata[0], a7ddrphy_dfi_p1_wrdata[16], a7ddrphy_dfi_p1_wrdata[0], a7ddrphy_dfi_p0_wrdata[16], a7ddrphy_dfi_p0_wrdata[0]}, a7ddrphy_bitslip0_r2[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip0_value3 <= (a7ddrphy_bitslip0_value3 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip0_value3 <= 3'd7;
+ end
+ a7ddrphy_bitslip0_r3 <= {a7ddrphy_bitslip03, a7ddrphy_bitslip0_r3[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip1_value2 <= (a7ddrphy_bitslip1_value2 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip1_value2 <= 3'd7;
+ end
+ a7ddrphy_bitslip1_r2 <= {{a7ddrphy_dfi_p3_wrdata[17], a7ddrphy_dfi_p3_wrdata[1], a7ddrphy_dfi_p2_wrdata[17], a7ddrphy_dfi_p2_wrdata[1], a7ddrphy_dfi_p1_wrdata[17], a7ddrphy_dfi_p1_wrdata[1], a7ddrphy_dfi_p0_wrdata[17], a7ddrphy_dfi_p0_wrdata[1]}, a7ddrphy_bitslip1_r2[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip1_value3 <= (a7ddrphy_bitslip1_value3 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip1_value3 <= 3'd7;
+ end
+ a7ddrphy_bitslip1_r3 <= {a7ddrphy_bitslip13, a7ddrphy_bitslip1_r3[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip2_value0 <= (a7ddrphy_bitslip2_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip2_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip2_r0 <= {{a7ddrphy_dfi_p3_wrdata[18], a7ddrphy_dfi_p3_wrdata[2], a7ddrphy_dfi_p2_wrdata[18], a7ddrphy_dfi_p2_wrdata[2], a7ddrphy_dfi_p1_wrdata[18], a7ddrphy_dfi_p1_wrdata[2], a7ddrphy_dfi_p0_wrdata[18], a7ddrphy_dfi_p0_wrdata[2]}, a7ddrphy_bitslip2_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip2_value1 <= (a7ddrphy_bitslip2_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip2_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip2_r1 <= {a7ddrphy_bitslip21, a7ddrphy_bitslip2_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip3_value0 <= (a7ddrphy_bitslip3_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip3_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip3_r0 <= {{a7ddrphy_dfi_p3_wrdata[19], a7ddrphy_dfi_p3_wrdata[3], a7ddrphy_dfi_p2_wrdata[19], a7ddrphy_dfi_p2_wrdata[3], a7ddrphy_dfi_p1_wrdata[19], a7ddrphy_dfi_p1_wrdata[3], a7ddrphy_dfi_p0_wrdata[19], a7ddrphy_dfi_p0_wrdata[3]}, a7ddrphy_bitslip3_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip3_value1 <= (a7ddrphy_bitslip3_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip3_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip3_r1 <= {a7ddrphy_bitslip31, a7ddrphy_bitslip3_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip4_value0 <= (a7ddrphy_bitslip4_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip4_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip4_r0 <= {{a7ddrphy_dfi_p3_wrdata[20], a7ddrphy_dfi_p3_wrdata[4], a7ddrphy_dfi_p2_wrdata[20], a7ddrphy_dfi_p2_wrdata[4], a7ddrphy_dfi_p1_wrdata[20], a7ddrphy_dfi_p1_wrdata[4], a7ddrphy_dfi_p0_wrdata[20], a7ddrphy_dfi_p0_wrdata[4]}, a7ddrphy_bitslip4_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip4_value1 <= (a7ddrphy_bitslip4_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip4_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip4_r1 <= {a7ddrphy_bitslip41, a7ddrphy_bitslip4_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip5_value0 <= (a7ddrphy_bitslip5_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip5_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip5_r0 <= {{a7ddrphy_dfi_p3_wrdata[21], a7ddrphy_dfi_p3_wrdata[5], a7ddrphy_dfi_p2_wrdata[21], a7ddrphy_dfi_p2_wrdata[5], a7ddrphy_dfi_p1_wrdata[21], a7ddrphy_dfi_p1_wrdata[5], a7ddrphy_dfi_p0_wrdata[21], a7ddrphy_dfi_p0_wrdata[5]}, a7ddrphy_bitslip5_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip5_value1 <= (a7ddrphy_bitslip5_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip5_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip5_r1 <= {a7ddrphy_bitslip51, a7ddrphy_bitslip5_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip6_value0 <= (a7ddrphy_bitslip6_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip6_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip6_r0 <= {{a7ddrphy_dfi_p3_wrdata[22], a7ddrphy_dfi_p3_wrdata[6], a7ddrphy_dfi_p2_wrdata[22], a7ddrphy_dfi_p2_wrdata[6], a7ddrphy_dfi_p1_wrdata[22], a7ddrphy_dfi_p1_wrdata[6], a7ddrphy_dfi_p0_wrdata[22], a7ddrphy_dfi_p0_wrdata[6]}, a7ddrphy_bitslip6_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip6_value1 <= (a7ddrphy_bitslip6_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip6_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip6_r1 <= {a7ddrphy_bitslip61, a7ddrphy_bitslip6_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip7_value0 <= (a7ddrphy_bitslip7_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip7_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip7_r0 <= {{a7ddrphy_dfi_p3_wrdata[23], a7ddrphy_dfi_p3_wrdata[7], a7ddrphy_dfi_p2_wrdata[23], a7ddrphy_dfi_p2_wrdata[7], a7ddrphy_dfi_p1_wrdata[23], a7ddrphy_dfi_p1_wrdata[7], a7ddrphy_dfi_p0_wrdata[23], a7ddrphy_dfi_p0_wrdata[7]}, a7ddrphy_bitslip7_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip7_value1 <= (a7ddrphy_bitslip7_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip7_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip7_r1 <= {a7ddrphy_bitslip71, a7ddrphy_bitslip7_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip8_value0 <= (a7ddrphy_bitslip8_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip8_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip8_r0 <= {{a7ddrphy_dfi_p3_wrdata[24], a7ddrphy_dfi_p3_wrdata[8], a7ddrphy_dfi_p2_wrdata[24], a7ddrphy_dfi_p2_wrdata[8], a7ddrphy_dfi_p1_wrdata[24], a7ddrphy_dfi_p1_wrdata[8], a7ddrphy_dfi_p0_wrdata[24], a7ddrphy_dfi_p0_wrdata[8]}, a7ddrphy_bitslip8_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip8_value1 <= (a7ddrphy_bitslip8_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip8_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip8_r1 <= {a7ddrphy_bitslip81, a7ddrphy_bitslip8_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip9_value0 <= (a7ddrphy_bitslip9_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip9_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip9_r0 <= {{a7ddrphy_dfi_p3_wrdata[25], a7ddrphy_dfi_p3_wrdata[9], a7ddrphy_dfi_p2_wrdata[25], a7ddrphy_dfi_p2_wrdata[9], a7ddrphy_dfi_p1_wrdata[25], a7ddrphy_dfi_p1_wrdata[9], a7ddrphy_dfi_p0_wrdata[25], a7ddrphy_dfi_p0_wrdata[9]}, a7ddrphy_bitslip9_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip9_value1 <= (a7ddrphy_bitslip9_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip9_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip9_r1 <= {a7ddrphy_bitslip91, a7ddrphy_bitslip9_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip10_value0 <= (a7ddrphy_bitslip10_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip10_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip10_r0 <= {{a7ddrphy_dfi_p3_wrdata[26], a7ddrphy_dfi_p3_wrdata[10], a7ddrphy_dfi_p2_wrdata[26], a7ddrphy_dfi_p2_wrdata[10], a7ddrphy_dfi_p1_wrdata[26], a7ddrphy_dfi_p1_wrdata[10], a7ddrphy_dfi_p0_wrdata[26], a7ddrphy_dfi_p0_wrdata[10]}, a7ddrphy_bitslip10_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip10_value1 <= (a7ddrphy_bitslip10_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip10_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip10_r1 <= {a7ddrphy_bitslip101, a7ddrphy_bitslip10_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip11_value0 <= (a7ddrphy_bitslip11_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip11_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip11_r0 <= {{a7ddrphy_dfi_p3_wrdata[27], a7ddrphy_dfi_p3_wrdata[11], a7ddrphy_dfi_p2_wrdata[27], a7ddrphy_dfi_p2_wrdata[11], a7ddrphy_dfi_p1_wrdata[27], a7ddrphy_dfi_p1_wrdata[11], a7ddrphy_dfi_p0_wrdata[27], a7ddrphy_dfi_p0_wrdata[11]}, a7ddrphy_bitslip11_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip11_value1 <= (a7ddrphy_bitslip11_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip11_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip11_r1 <= {a7ddrphy_bitslip111, a7ddrphy_bitslip11_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip12_value0 <= (a7ddrphy_bitslip12_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip12_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip12_r0 <= {{a7ddrphy_dfi_p3_wrdata[28], a7ddrphy_dfi_p3_wrdata[12], a7ddrphy_dfi_p2_wrdata[28], a7ddrphy_dfi_p2_wrdata[12], a7ddrphy_dfi_p1_wrdata[28], a7ddrphy_dfi_p1_wrdata[12], a7ddrphy_dfi_p0_wrdata[28], a7ddrphy_dfi_p0_wrdata[12]}, a7ddrphy_bitslip12_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip12_value1 <= (a7ddrphy_bitslip12_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip12_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip12_r1 <= {a7ddrphy_bitslip121, a7ddrphy_bitslip12_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip13_value0 <= (a7ddrphy_bitslip13_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip13_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip13_r0 <= {{a7ddrphy_dfi_p3_wrdata[29], a7ddrphy_dfi_p3_wrdata[13], a7ddrphy_dfi_p2_wrdata[29], a7ddrphy_dfi_p2_wrdata[13], a7ddrphy_dfi_p1_wrdata[29], a7ddrphy_dfi_p1_wrdata[13], a7ddrphy_dfi_p0_wrdata[29], a7ddrphy_dfi_p0_wrdata[13]}, a7ddrphy_bitslip13_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip13_value1 <= (a7ddrphy_bitslip13_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip13_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip13_r1 <= {a7ddrphy_bitslip131, a7ddrphy_bitslip13_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip14_value0 <= (a7ddrphy_bitslip14_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip14_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip14_r0 <= {{a7ddrphy_dfi_p3_wrdata[30], a7ddrphy_dfi_p3_wrdata[14], a7ddrphy_dfi_p2_wrdata[30], a7ddrphy_dfi_p2_wrdata[14], a7ddrphy_dfi_p1_wrdata[30], a7ddrphy_dfi_p1_wrdata[14], a7ddrphy_dfi_p0_wrdata[30], a7ddrphy_dfi_p0_wrdata[14]}, a7ddrphy_bitslip14_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip14_value1 <= (a7ddrphy_bitslip14_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip14_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip14_r1 <= {a7ddrphy_bitslip141, a7ddrphy_bitslip14_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip15_value0 <= (a7ddrphy_bitslip15_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip15_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip15_r0 <= {{a7ddrphy_dfi_p3_wrdata[31], a7ddrphy_dfi_p3_wrdata[15], a7ddrphy_dfi_p2_wrdata[31], a7ddrphy_dfi_p2_wrdata[15], a7ddrphy_dfi_p1_wrdata[31], a7ddrphy_dfi_p1_wrdata[15], a7ddrphy_dfi_p0_wrdata[31], a7ddrphy_dfi_p0_wrdata[15]}, a7ddrphy_bitslip15_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip15_value1 <= (a7ddrphy_bitslip15_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip15_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip15_r1 <= {a7ddrphy_bitslip151, a7ddrphy_bitslip15_r1[15:8]};
+ a7ddrphy_rddata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_rddata_en | a7ddrphy_dfi_p1_rddata_en) | a7ddrphy_dfi_p2_rddata_en) | a7ddrphy_dfi_p3_rddata_en);
+ a7ddrphy_rddata_en_tappeddelayline1 <= a7ddrphy_rddata_en_tappeddelayline0;
+ a7ddrphy_rddata_en_tappeddelayline2 <= a7ddrphy_rddata_en_tappeddelayline1;
+ a7ddrphy_rddata_en_tappeddelayline3 <= a7ddrphy_rddata_en_tappeddelayline2;
+ a7ddrphy_rddata_en_tappeddelayline4 <= a7ddrphy_rddata_en_tappeddelayline3;
+ a7ddrphy_rddata_en_tappeddelayline5 <= a7ddrphy_rddata_en_tappeddelayline4;
+ a7ddrphy_rddata_en_tappeddelayline6 <= a7ddrphy_rddata_en_tappeddelayline5;
+ a7ddrphy_rddata_en_tappeddelayline7 <= a7ddrphy_rddata_en_tappeddelayline6;
+ a7ddrphy_wrdata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_wrdata_en | a7ddrphy_dfi_p1_wrdata_en) | a7ddrphy_dfi_p2_wrdata_en) | a7ddrphy_dfi_p3_wrdata_en);
+ a7ddrphy_wrdata_en_tappeddelayline1 <= a7ddrphy_wrdata_en_tappeddelayline0;
+ a7ddrphy_wrdata_en_tappeddelayline2 <= a7ddrphy_wrdata_en_tappeddelayline1;
+ if (litedramcore_csr_dfi_p0_rddata_valid) begin
+ litedramcore_phaseinjector0_rddata_status <= litedramcore_csr_dfi_p0_rddata;
+ end
+ if (litedramcore_csr_dfi_p1_rddata_valid) begin
+ litedramcore_phaseinjector1_rddata_status <= litedramcore_csr_dfi_p1_rddata;
+ end
+ if (litedramcore_csr_dfi_p2_rddata_valid) begin
+ litedramcore_phaseinjector2_rddata_status <= litedramcore_csr_dfi_p2_rddata;
+ end
+ if (litedramcore_csr_dfi_p3_rddata_valid) begin
+ litedramcore_phaseinjector3_rddata_status <= litedramcore_csr_dfi_p3_rddata;
+ end
+ if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin
+ litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1);
+ end else begin
+ litedramcore_timer_count1 <= 10'd781;
+ end
+ litedramcore_postponer_req_o <= 1'd0;
+ if (litedramcore_postponer_req_i) begin
+ litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1);
+ if ((litedramcore_postponer_count == 1'd0)) begin
+ litedramcore_postponer_count <= 1'd0;
+ litedramcore_postponer_req_o <= 1'd1;
+ end
+ end
+ if (litedramcore_sequencer_start0) begin
+ litedramcore_sequencer_count <= 1'd0;
+ end else begin
+ if (litedramcore_sequencer_done1) begin
+ if ((litedramcore_sequencer_count != 1'd0)) begin
+ litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1);
+ end
+ end
+ end
+ litedramcore_cmd_payload_a <= 1'd0;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd0;
+ litedramcore_cmd_payload_we <= 1'd0;
+ litedramcore_sequencer_done1 <= 1'd0;
+ if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin
+ litedramcore_cmd_payload_a <= 11'd1024;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd1;
+ litedramcore_cmd_payload_we <= 1'd1;
+ end
+ if ((litedramcore_sequencer_counter == 2'd3)) begin
+ litedramcore_cmd_payload_a <= 11'd1024;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd1;
+ litedramcore_cmd_payload_ras <= 1'd1;
+ litedramcore_cmd_payload_we <= 1'd0;
+ end
+ if ((litedramcore_sequencer_counter == 6'd35)) begin
+ litedramcore_cmd_payload_a <= 1'd0;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd0;
+ litedramcore_cmd_payload_we <= 1'd0;
+ litedramcore_sequencer_done1 <= 1'd1;
+ end
+ if ((litedramcore_sequencer_counter == 6'd35)) begin
+ litedramcore_sequencer_counter <= 1'd0;
+ end else begin
+ if ((litedramcore_sequencer_counter != 1'd0)) begin
+ litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1);
+ end else begin
+ if (litedramcore_sequencer_start1) begin
+ litedramcore_sequencer_counter <= 1'd1;
+ end
+ end
+ end
+ if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin
+ litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1);
+ end else begin
+ litedramcore_zqcs_timer_count1 <= 27'd99999999;
+ end
+ litedramcore_zqcs_executer_done <= 1'd0;
+ if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin
+ litedramcore_cmd_payload_a <= 11'd1024;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd1;
+ litedramcore_cmd_payload_we <= 1'd1;
+ end
+ if ((litedramcore_zqcs_executer_counter == 2'd3)) begin
+ litedramcore_cmd_payload_a <= 1'd0;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd0;
+ litedramcore_cmd_payload_we <= 1'd1;
+ end
+ if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
+ litedramcore_cmd_payload_a <= 1'd0;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd0;
+ litedramcore_cmd_payload_we <= 1'd0;
+ litedramcore_zqcs_executer_done <= 1'd1;
+ end
+ if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
+ litedramcore_zqcs_executer_counter <= 1'd0;
+ end else begin
+ if ((litedramcore_zqcs_executer_counter != 1'd0)) begin
+ litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1);
+ end else begin
+ if (litedramcore_zqcs_executer_start) begin
+ litedramcore_zqcs_executer_counter <= 1'd1;
+ end
+ end
+ end
+ litedramcore_refresher_state <= litedramcore_refresher_next_state;
+ if (litedramcore_bankmachine0_row_close) begin
+ litedramcore_bankmachine0_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine0_row_open) begin
+ litedramcore_bankmachine0_row_opened <= 1'd1;
+ litedramcore_bankmachine0_row <= litedramcore_bankmachine0_source_source_payload_addr[20:7];
+ end
+ end
+ if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin
+ litedramcore_bankmachine0_produce <= (litedramcore_bankmachine0_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine0_do_read) begin
+ litedramcore_bankmachine0_consume <= (litedramcore_bankmachine0_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin
+ if ((~litedramcore_bankmachine0_do_read)) begin
+ litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine0_do_read) begin
+ litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine0_pipe_valid_source_valid <= litedramcore_bankmachine0_pipe_valid_sink_valid;
+ litedramcore_bankmachine0_pipe_valid_source_first <= litedramcore_bankmachine0_pipe_valid_sink_first;
+ litedramcore_bankmachine0_pipe_valid_source_last <= litedramcore_bankmachine0_pipe_valid_sink_last;
+ litedramcore_bankmachine0_pipe_valid_source_payload_we <= litedramcore_bankmachine0_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine0_pipe_valid_source_payload_addr <= litedramcore_bankmachine0_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine0_twtpcon_valid) begin
+ litedramcore_bankmachine0_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine0_twtpcon_ready)) begin
+ litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine0_trccon_valid) begin
+ litedramcore_bankmachine0_trccon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine0_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine0_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine0_trccon_ready)) begin
+ litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine0_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine0_trascon_valid) begin
+ litedramcore_bankmachine0_trascon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_bankmachine0_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine0_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine0_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state;
+ if (litedramcore_bankmachine1_row_close) begin
+ litedramcore_bankmachine1_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine1_row_open) begin
+ litedramcore_bankmachine1_row_opened <= 1'd1;
+ litedramcore_bankmachine1_row <= litedramcore_bankmachine1_source_source_payload_addr[20:7];
+ end
+ end
+ if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin
+ litedramcore_bankmachine1_produce <= (litedramcore_bankmachine1_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine1_do_read) begin
+ litedramcore_bankmachine1_consume <= (litedramcore_bankmachine1_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin
+ if ((~litedramcore_bankmachine1_do_read)) begin
+ litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine1_do_read) begin
+ litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine1_pipe_valid_source_valid <= litedramcore_bankmachine1_pipe_valid_sink_valid;
+ litedramcore_bankmachine1_pipe_valid_source_first <= litedramcore_bankmachine1_pipe_valid_sink_first;
+ litedramcore_bankmachine1_pipe_valid_source_last <= litedramcore_bankmachine1_pipe_valid_sink_last;
+ litedramcore_bankmachine1_pipe_valid_source_payload_we <= litedramcore_bankmachine1_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine1_pipe_valid_source_payload_addr <= litedramcore_bankmachine1_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine1_twtpcon_valid) begin
+ litedramcore_bankmachine1_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine1_twtpcon_ready)) begin
+ litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine1_trccon_valid) begin
+ litedramcore_bankmachine1_trccon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine1_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine1_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine1_trccon_ready)) begin
+ litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine1_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine1_trascon_valid) begin
+ litedramcore_bankmachine1_trascon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_bankmachine1_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine1_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine1_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state;
+ if (litedramcore_bankmachine2_row_close) begin
+ litedramcore_bankmachine2_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine2_row_open) begin
+ litedramcore_bankmachine2_row_opened <= 1'd1;
+ litedramcore_bankmachine2_row <= litedramcore_bankmachine2_source_source_payload_addr[20:7];
+ end
+ end
+ if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin
+ litedramcore_bankmachine2_produce <= (litedramcore_bankmachine2_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine2_do_read) begin
+ litedramcore_bankmachine2_consume <= (litedramcore_bankmachine2_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin
+ if ((~litedramcore_bankmachine2_do_read)) begin
+ litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine2_do_read) begin
+ litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine2_pipe_valid_source_valid <= litedramcore_bankmachine2_pipe_valid_sink_valid;
+ litedramcore_bankmachine2_pipe_valid_source_first <= litedramcore_bankmachine2_pipe_valid_sink_first;
+ litedramcore_bankmachine2_pipe_valid_source_last <= litedramcore_bankmachine2_pipe_valid_sink_last;
+ litedramcore_bankmachine2_pipe_valid_source_payload_we <= litedramcore_bankmachine2_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine2_pipe_valid_source_payload_addr <= litedramcore_bankmachine2_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine2_twtpcon_valid) begin
+ litedramcore_bankmachine2_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine2_twtpcon_ready)) begin
+ litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine2_trccon_valid) begin
+ litedramcore_bankmachine2_trccon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine2_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine2_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine2_trccon_ready)) begin
+ litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine2_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine2_trascon_valid) begin
+ litedramcore_bankmachine2_trascon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_bankmachine2_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine2_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine2_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state;
+ if (litedramcore_bankmachine3_row_close) begin
+ litedramcore_bankmachine3_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine3_row_open) begin
+ litedramcore_bankmachine3_row_opened <= 1'd1;
+ litedramcore_bankmachine3_row <= litedramcore_bankmachine3_source_source_payload_addr[20:7];
+ end
+ end
+ if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin
+ litedramcore_bankmachine3_produce <= (litedramcore_bankmachine3_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine3_do_read) begin
+ litedramcore_bankmachine3_consume <= (litedramcore_bankmachine3_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin
+ if ((~litedramcore_bankmachine3_do_read)) begin
+ litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine3_do_read) begin
+ litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine3_pipe_valid_source_valid <= litedramcore_bankmachine3_pipe_valid_sink_valid;
+ litedramcore_bankmachine3_pipe_valid_source_first <= litedramcore_bankmachine3_pipe_valid_sink_first;
+ litedramcore_bankmachine3_pipe_valid_source_last <= litedramcore_bankmachine3_pipe_valid_sink_last;
+ litedramcore_bankmachine3_pipe_valid_source_payload_we <= litedramcore_bankmachine3_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine3_pipe_valid_source_payload_addr <= litedramcore_bankmachine3_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine3_twtpcon_valid) begin
+ litedramcore_bankmachine3_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine3_twtpcon_ready)) begin
+ litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine3_trccon_valid) begin
+ litedramcore_bankmachine3_trccon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine3_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine3_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine3_trccon_ready)) begin
+ litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine3_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine3_trascon_valid) begin
+ litedramcore_bankmachine3_trascon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_bankmachine3_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine3_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine3_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state;
+ if (litedramcore_bankmachine4_row_close) begin
+ litedramcore_bankmachine4_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine4_row_open) begin
+ litedramcore_bankmachine4_row_opened <= 1'd1;
+ litedramcore_bankmachine4_row <= litedramcore_bankmachine4_source_source_payload_addr[20:7];
+ end
+ end
+ if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin
+ litedramcore_bankmachine4_produce <= (litedramcore_bankmachine4_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine4_do_read) begin
+ litedramcore_bankmachine4_consume <= (litedramcore_bankmachine4_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin
+ if ((~litedramcore_bankmachine4_do_read)) begin
+ litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine4_do_read) begin
+ litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine4_pipe_valid_source_valid <= litedramcore_bankmachine4_pipe_valid_sink_valid;
+ litedramcore_bankmachine4_pipe_valid_source_first <= litedramcore_bankmachine4_pipe_valid_sink_first;
+ litedramcore_bankmachine4_pipe_valid_source_last <= litedramcore_bankmachine4_pipe_valid_sink_last;
+ litedramcore_bankmachine4_pipe_valid_source_payload_we <= litedramcore_bankmachine4_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine4_pipe_valid_source_payload_addr <= litedramcore_bankmachine4_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine4_twtpcon_valid) begin
+ litedramcore_bankmachine4_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine4_twtpcon_ready)) begin
+ litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine4_trccon_valid) begin
+ litedramcore_bankmachine4_trccon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine4_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine4_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine4_trccon_ready)) begin
+ litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine4_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine4_trascon_valid) begin
+ litedramcore_bankmachine4_trascon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_bankmachine4_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine4_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine4_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state;
+ if (litedramcore_bankmachine5_row_close) begin
+ litedramcore_bankmachine5_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine5_row_open) begin
+ litedramcore_bankmachine5_row_opened <= 1'd1;
+ litedramcore_bankmachine5_row <= litedramcore_bankmachine5_source_source_payload_addr[20:7];
+ end
+ end
+ if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin
+ litedramcore_bankmachine5_produce <= (litedramcore_bankmachine5_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine5_do_read) begin
+ litedramcore_bankmachine5_consume <= (litedramcore_bankmachine5_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin
+ if ((~litedramcore_bankmachine5_do_read)) begin
+ litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine5_do_read) begin
+ litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine5_pipe_valid_source_valid <= litedramcore_bankmachine5_pipe_valid_sink_valid;
+ litedramcore_bankmachine5_pipe_valid_source_first <= litedramcore_bankmachine5_pipe_valid_sink_first;
+ litedramcore_bankmachine5_pipe_valid_source_last <= litedramcore_bankmachine5_pipe_valid_sink_last;
+ litedramcore_bankmachine5_pipe_valid_source_payload_we <= litedramcore_bankmachine5_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine5_pipe_valid_source_payload_addr <= litedramcore_bankmachine5_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine5_twtpcon_valid) begin
+ litedramcore_bankmachine5_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine5_twtpcon_ready)) begin
+ litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine5_trccon_valid) begin
+ litedramcore_bankmachine5_trccon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine5_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine5_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine5_trccon_ready)) begin
+ litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine5_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine5_trascon_valid) begin
+ litedramcore_bankmachine5_trascon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_bankmachine5_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine5_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine5_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state;
+ if (litedramcore_bankmachine6_row_close) begin
+ litedramcore_bankmachine6_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine6_row_open) begin
+ litedramcore_bankmachine6_row_opened <= 1'd1;
+ litedramcore_bankmachine6_row <= litedramcore_bankmachine6_source_source_payload_addr[20:7];
+ end
+ end
+ if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin
+ litedramcore_bankmachine6_produce <= (litedramcore_bankmachine6_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine6_do_read) begin
+ litedramcore_bankmachine6_consume <= (litedramcore_bankmachine6_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin
+ if ((~litedramcore_bankmachine6_do_read)) begin
+ litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine6_do_read) begin
+ litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine6_pipe_valid_source_valid <= litedramcore_bankmachine6_pipe_valid_sink_valid;
+ litedramcore_bankmachine6_pipe_valid_source_first <= litedramcore_bankmachine6_pipe_valid_sink_first;
+ litedramcore_bankmachine6_pipe_valid_source_last <= litedramcore_bankmachine6_pipe_valid_sink_last;
+ litedramcore_bankmachine6_pipe_valid_source_payload_we <= litedramcore_bankmachine6_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine6_pipe_valid_source_payload_addr <= litedramcore_bankmachine6_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine6_twtpcon_valid) begin
+ litedramcore_bankmachine6_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine6_twtpcon_ready)) begin
+ litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine6_trccon_valid) begin
+ litedramcore_bankmachine6_trccon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine6_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine6_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine6_trccon_ready)) begin
+ litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine6_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine6_trascon_valid) begin
+ litedramcore_bankmachine6_trascon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_bankmachine6_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine6_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine6_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state;
+ if (litedramcore_bankmachine7_row_close) begin
+ litedramcore_bankmachine7_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine7_row_open) begin
+ litedramcore_bankmachine7_row_opened <= 1'd1;
+ litedramcore_bankmachine7_row <= litedramcore_bankmachine7_source_source_payload_addr[20:7];
+ end
+ end
+ if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin
+ litedramcore_bankmachine7_produce <= (litedramcore_bankmachine7_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine7_do_read) begin
+ litedramcore_bankmachine7_consume <= (litedramcore_bankmachine7_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin
+ if ((~litedramcore_bankmachine7_do_read)) begin
+ litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine7_do_read) begin
+ litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine7_pipe_valid_source_valid <= litedramcore_bankmachine7_pipe_valid_sink_valid;
+ litedramcore_bankmachine7_pipe_valid_source_first <= litedramcore_bankmachine7_pipe_valid_sink_first;
+ litedramcore_bankmachine7_pipe_valid_source_last <= litedramcore_bankmachine7_pipe_valid_sink_last;
+ litedramcore_bankmachine7_pipe_valid_source_payload_we <= litedramcore_bankmachine7_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine7_pipe_valid_source_payload_addr <= litedramcore_bankmachine7_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine7_twtpcon_valid) begin
+ litedramcore_bankmachine7_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine7_twtpcon_ready)) begin
+ litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine7_trccon_valid) begin
+ litedramcore_bankmachine7_trccon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine7_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine7_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine7_trccon_ready)) begin
+ litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine7_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine7_trascon_valid) begin
+ litedramcore_bankmachine7_trascon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_bankmachine7_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine7_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine7_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state;
+ if ((~litedramcore_en0)) begin
+ litedramcore_time0 <= 5'd31;
+ end else begin
+ if ((~litedramcore_max_time0)) begin
+ litedramcore_time0 <= (litedramcore_time0 - 1'd1);
+ end
+ end
+ if ((~litedramcore_en1)) begin
+ litedramcore_time1 <= 4'd15;
+ end else begin
+ if ((~litedramcore_max_time1)) begin
+ litedramcore_time1 <= (litedramcore_time1 - 1'd1);
+ end
+ end
+ if (litedramcore_choose_cmd_ce) begin
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 1'd1: begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 2'd2: begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd4: begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd5: begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd6: begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd7: begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ endcase
+ end
+ if (litedramcore_choose_req_ce) begin
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 1'd1: begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 2'd2: begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd4: begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd5: begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd6: begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd7: begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ endcase
+ end
+ litedramcore_dfi_p0_cs_n <= 1'd0;
+ litedramcore_dfi_p0_bank <= array_muxed0;
+ litedramcore_dfi_p0_address <= array_muxed1;
+ litedramcore_dfi_p0_cas_n <= (~array_muxed2);
+ litedramcore_dfi_p0_ras_n <= (~array_muxed3);
+ litedramcore_dfi_p0_we_n <= (~array_muxed4);
+ litedramcore_dfi_p0_rddata_en <= array_muxed5;
+ litedramcore_dfi_p0_wrdata_en <= array_muxed6;
+ litedramcore_dfi_p1_cs_n <= 1'd0;
+ litedramcore_dfi_p1_bank <= array_muxed7;
+ litedramcore_dfi_p1_address <= array_muxed8;
+ litedramcore_dfi_p1_cas_n <= (~array_muxed9);
+ litedramcore_dfi_p1_ras_n <= (~array_muxed10);
+ litedramcore_dfi_p1_we_n <= (~array_muxed11);
+ litedramcore_dfi_p1_rddata_en <= array_muxed12;
+ litedramcore_dfi_p1_wrdata_en <= array_muxed13;
+ litedramcore_dfi_p2_cs_n <= 1'd0;
+ litedramcore_dfi_p2_bank <= array_muxed14;
+ litedramcore_dfi_p2_address <= array_muxed15;
+ litedramcore_dfi_p2_cas_n <= (~array_muxed16);
+ litedramcore_dfi_p2_ras_n <= (~array_muxed17);
+ litedramcore_dfi_p2_we_n <= (~array_muxed18);
+ litedramcore_dfi_p2_rddata_en <= array_muxed19;
+ litedramcore_dfi_p2_wrdata_en <= array_muxed20;
+ litedramcore_dfi_p3_cs_n <= 1'd0;
+ litedramcore_dfi_p3_bank <= array_muxed21;
+ litedramcore_dfi_p3_address <= array_muxed22;
+ litedramcore_dfi_p3_cas_n <= (~array_muxed23);
+ litedramcore_dfi_p3_ras_n <= (~array_muxed24);
+ litedramcore_dfi_p3_we_n <= (~array_muxed25);
+ litedramcore_dfi_p3_rddata_en <= array_muxed26;
+ litedramcore_dfi_p3_wrdata_en <= array_muxed27;
+ if (litedramcore_trrdcon_valid) begin
+ litedramcore_trrdcon_count <= 1'd1;
+ if (1'd0) begin
+ litedramcore_trrdcon_ready <= 1'd1;
+ end else begin
+ litedramcore_trrdcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_trrdcon_ready)) begin
+ litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1);
+ if ((litedramcore_trrdcon_count == 1'd1)) begin
+ litedramcore_trrdcon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid};
+ if ((litedramcore_tfawcon_count < 3'd4)) begin
+ if ((litedramcore_tfawcon_count == 2'd3)) begin
+ litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid);
+ end else begin
+ litedramcore_tfawcon_ready <= 1'd1;
+ end
+ end
+ if (litedramcore_tccdcon_valid) begin
+ litedramcore_tccdcon_count <= 1'd0;
+ if (1'd1) begin
+ litedramcore_tccdcon_ready <= 1'd1;
+ end else begin
+ litedramcore_tccdcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_tccdcon_ready)) begin
+ litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1);
+ if ((litedramcore_tccdcon_count == 1'd1)) begin
+ litedramcore_tccdcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_twtrcon_valid) begin
+ litedramcore_twtrcon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_twtrcon_ready <= 1'd1;
+ end else begin
+ litedramcore_twtrcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_twtrcon_ready)) begin
+ litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1);
+ if ((litedramcore_twtrcon_count == 1'd1)) begin
+ litedramcore_twtrcon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state;
+ litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready));
+ litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0;
+ litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid));
+ litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0;
+ litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1;
+ litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2;
+ litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3;
+ litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4;
+ litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5;
+ litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6;
+ litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7;
+ litedramcore_state <= litedramcore_next_state;
+ if (litedramcore_dat_w_next_value_ce0) begin
+ litedramcore_dat_w <= litedramcore_dat_w_next_value0;
+ end
+ if (litedramcore_adr_next_value_ce1) begin
+ litedramcore_adr <= litedramcore_adr_next_value1;
+ end
+ if (litedramcore_we_next_value_ce2) begin
+ litedramcore_we <= litedramcore_we_next_value2;
+ end
+ interface0_bank_bus_dat_r <= 1'd0;
+ if (csrbank0_sel) begin
+ case (interface0_bank_bus_adr[8:0])
+ 1'd0: begin
+ interface0_bank_bus_dat_r <= csrbank0_init_done0_w;
+ end
+ 1'd1: begin
+ interface0_bank_bus_dat_r <= csrbank0_init_error0_w;
+ end
+ endcase
+ end
+ if (csrbank0_init_done0_re) begin
+ init_done_storage <= csrbank0_init_done0_r;
+ end
+ init_done_re <= csrbank0_init_done0_re;
+ if (csrbank0_init_error0_re) begin
+ init_error_storage <= csrbank0_init_error0_r;
+ end
+ init_error_re <= csrbank0_init_error0_re;
+ interface1_bank_bus_dat_r <= 1'd0;
+ if (csrbank1_sel) begin
+ case (interface1_bank_bus_adr[8:0])
+ 1'd0: begin
+ interface1_bank_bus_dat_r <= csrbank1_rst0_w;
+ end
+ 1'd1: begin
+ interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w;
+ end
+ 2'd2: begin
+ interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w;
+ end
+ 2'd3: begin
+ interface1_bank_bus_dat_r <= csrbank1_wlevel_en0_w;
+ end
+ 3'd4: begin
+ interface1_bank_bus_dat_r <= a7ddrphy_wlevel_strobe_w;
+ end
+ 3'd5: begin
+ interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_rst_w;
+ end
+ 3'd6: begin
+ interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_inc_w;
+ end
+ 3'd7: begin
+ interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_rst_w;
+ end
+ 4'd8: begin
+ interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_w;
+ end
+ 4'd9: begin
+ interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_rst_w;
+ end
+ 4'd10: begin
+ interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_w;
+ end
+ 4'd11: begin
+ interface1_bank_bus_dat_r <= csrbank1_rdphase0_w;
+ end
+ 4'd12: begin
+ interface1_bank_bus_dat_r <= csrbank1_wrphase0_w;
+ end
+ endcase
+ end
+ if (csrbank1_rst0_re) begin
+ a7ddrphy_rst_storage <= csrbank1_rst0_r;
+ end
+ a7ddrphy_rst_re <= csrbank1_rst0_re;
+ if (csrbank1_dly_sel0_re) begin
+ a7ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r;
+ end
+ a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re;
+ if (csrbank1_half_sys8x_taps0_re) begin
+ a7ddrphy_half_sys8x_taps_storage[4:0] <= csrbank1_half_sys8x_taps0_r;
+ end
+ a7ddrphy_half_sys8x_taps_re <= csrbank1_half_sys8x_taps0_re;
+ if (csrbank1_wlevel_en0_re) begin
+ a7ddrphy_wlevel_en_storage <= csrbank1_wlevel_en0_r;
+ end
+ a7ddrphy_wlevel_en_re <= csrbank1_wlevel_en0_re;
+ if (csrbank1_rdphase0_re) begin
+ a7ddrphy_rdphase_storage[1:0] <= csrbank1_rdphase0_r;
+ end
+ a7ddrphy_rdphase_re <= csrbank1_rdphase0_re;
+ if (csrbank1_wrphase0_re) begin
+ a7ddrphy_wrphase_storage[1:0] <= csrbank1_wrphase0_r;
+ end
+ a7ddrphy_wrphase_re <= csrbank1_wrphase0_re;
+ interface2_bank_bus_dat_r <= 1'd0;
+ if (csrbank2_sel) begin
+ case (interface2_bank_bus_adr[8:0])
+ 1'd0: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w;
+ end
+ 1'd1: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w;
+ end
+ 2'd2: begin
+ interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w;
+ end
+ 2'd3: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w;
+ end
+ 3'd4: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w;
+ end
+ 3'd5: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w;
+ end
+ 3'd6: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata_w;
+ end
+ 3'd7: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w;
+ end
+ 4'd8: begin
+ interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w;
+ end
+ 4'd9: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w;
+ end
+ 4'd10: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w;
+ end
+ 4'd11: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w;
+ end
+ 4'd12: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata_w;
+ end
+ 4'd13: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w;
+ end
+ 4'd14: begin
+ interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w;
+ end
+ 4'd15: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w;
+ end
+ 5'd16: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w;
+ end
+ 5'd17: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w;
+ end
+ 5'd18: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata_w;
+ end
+ 5'd19: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w;
+ end
+ 5'd20: begin
+ interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w;
+ end
+ 5'd21: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w;
+ end
+ 5'd22: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w;
+ end
+ 5'd23: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w;
+ end
+ 5'd24: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata_w;
+ end
+ endcase
+ end
+ if (csrbank2_dfii_control0_re) begin
+ litedramcore_storage[3:0] <= csrbank2_dfii_control0_r;
+ end
+ litedramcore_re <= csrbank2_dfii_control0_re;
+ if (csrbank2_dfii_pi0_command0_re) begin
+ litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r;
+ end
+ litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re;
+ if (csrbank2_dfii_pi0_address0_re) begin
+ litedramcore_phaseinjector0_address_storage[13:0] <= csrbank2_dfii_pi0_address0_r;
+ end
+ litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re;
+ if (csrbank2_dfii_pi0_baddress0_re) begin
+ litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r;
+ end
+ litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re;
+ if (csrbank2_dfii_pi0_wrdata0_re) begin
+ litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r;
+ end
+ litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re;
+ litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata_re;
+ if (csrbank2_dfii_pi1_command0_re) begin
+ litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r;
+ end
+ litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re;
+ if (csrbank2_dfii_pi1_address0_re) begin
+ litedramcore_phaseinjector1_address_storage[13:0] <= csrbank2_dfii_pi1_address0_r;
+ end
+ litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re;
+ if (csrbank2_dfii_pi1_baddress0_re) begin
+ litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r;
+ end
+ litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re;
+ if (csrbank2_dfii_pi1_wrdata0_re) begin
+ litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r;
+ end
+ litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re;
+ litedramcore_phaseinjector1_rddata_re <= csrbank2_dfii_pi1_rddata_re;
+ if (csrbank2_dfii_pi2_command0_re) begin
+ litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r;
+ end
+ litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re;
+ if (csrbank2_dfii_pi2_address0_re) begin
+ litedramcore_phaseinjector2_address_storage[13:0] <= csrbank2_dfii_pi2_address0_r;
+ end
+ litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re;
+ if (csrbank2_dfii_pi2_baddress0_re) begin
+ litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r;
+ end
+ litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re;
+ if (csrbank2_dfii_pi2_wrdata0_re) begin
+ litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r;
+ end
+ litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re;
+ litedramcore_phaseinjector2_rddata_re <= csrbank2_dfii_pi2_rddata_re;
+ if (csrbank2_dfii_pi3_command0_re) begin
+ litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r;
+ end
+ litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re;
+ if (csrbank2_dfii_pi3_address0_re) begin
+ litedramcore_phaseinjector3_address_storage[13:0] <= csrbank2_dfii_pi3_address0_r;
+ end
+ litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re;
+ if (csrbank2_dfii_pi3_baddress0_re) begin
+ litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r;
+ end
+ litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re;
+ if (csrbank2_dfii_pi3_wrdata0_re) begin
+ litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r;
+ end
+ litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re;
+ litedramcore_phaseinjector3_rddata_re <= csrbank2_dfii_pi3_rddata_re;
+ if (sys_rst) begin
+ a7ddrphy_rst_storage <= 1'd0;
+ a7ddrphy_rst_re <= 1'd0;
+ a7ddrphy_dly_sel_storage <= 2'd0;
+ a7ddrphy_dly_sel_re <= 1'd0;
+ a7ddrphy_half_sys8x_taps_storage <= 5'd8;
+ a7ddrphy_half_sys8x_taps_re <= 1'd0;
+ a7ddrphy_wlevel_en_storage <= 1'd0;
+ a7ddrphy_wlevel_en_re <= 1'd0;
+ a7ddrphy_rdphase_storage <= 2'd2;
+ a7ddrphy_rdphase_re <= 1'd0;
+ a7ddrphy_wrphase_storage <= 2'd3;
+ a7ddrphy_wrphase_re <= 1'd0;
+ a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
+ a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
+ a7ddrphy_dqspattern_o1 <= 8'd0;
+ a7ddrphy_bitslip0_value0 <= 3'd7;
+ a7ddrphy_bitslip1_value0 <= 3'd7;
+ a7ddrphy_bitslip0_value1 <= 3'd7;
+ a7ddrphy_bitslip1_value1 <= 3'd7;
+ a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
+ a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
+ a7ddrphy_bitslip0_value2 <= 3'd7;
+ a7ddrphy_bitslip0_value3 <= 3'd7;
+ a7ddrphy_bitslip1_value2 <= 3'd7;
+ a7ddrphy_bitslip1_value3 <= 3'd7;
+ a7ddrphy_bitslip2_value0 <= 3'd7;
+ a7ddrphy_bitslip2_value1 <= 3'd7;
+ a7ddrphy_bitslip3_value0 <= 3'd7;
+ a7ddrphy_bitslip3_value1 <= 3'd7;
+ a7ddrphy_bitslip4_value0 <= 3'd7;
+ a7ddrphy_bitslip4_value1 <= 3'd7;
+ a7ddrphy_bitslip5_value0 <= 3'd7;
+ a7ddrphy_bitslip5_value1 <= 3'd7;
+ a7ddrphy_bitslip6_value0 <= 3'd7;
+ a7ddrphy_bitslip6_value1 <= 3'd7;
+ a7ddrphy_bitslip7_value0 <= 3'd7;
+ a7ddrphy_bitslip7_value1 <= 3'd7;
+ a7ddrphy_bitslip8_value0 <= 3'd7;
+ a7ddrphy_bitslip8_value1 <= 3'd7;
+ a7ddrphy_bitslip9_value0 <= 3'd7;
+ a7ddrphy_bitslip9_value1 <= 3'd7;
+ a7ddrphy_bitslip10_value0 <= 3'd7;
+ a7ddrphy_bitslip10_value1 <= 3'd7;
+ a7ddrphy_bitslip11_value0 <= 3'd7;
+ a7ddrphy_bitslip11_value1 <= 3'd7;
+ a7ddrphy_bitslip12_value0 <= 3'd7;
+ a7ddrphy_bitslip12_value1 <= 3'd7;
+ a7ddrphy_bitslip13_value0 <= 3'd7;
+ a7ddrphy_bitslip13_value1 <= 3'd7;
+ a7ddrphy_bitslip14_value0 <= 3'd7;
+ a7ddrphy_bitslip14_value1 <= 3'd7;
+ a7ddrphy_bitslip15_value0 <= 3'd7;
+ a7ddrphy_bitslip15_value1 <= 3'd7;
+ a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0;
+ a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0;
+ a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0;
+ a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0;
+ a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0;
+ a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0;
+ a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0;
+ a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0;
+ a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0;
+ a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0;
+ a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0;
+ litedramcore_storage <= 4'd1;
+ litedramcore_re <= 1'd0;
+ litedramcore_phaseinjector0_command_storage <= 6'd0;
+ litedramcore_phaseinjector0_command_re <= 1'd0;
+ litedramcore_phaseinjector0_address_re <= 1'd0;
+ litedramcore_phaseinjector0_baddress_re <= 1'd0;
+ litedramcore_phaseinjector0_wrdata_re <= 1'd0;
+ litedramcore_phaseinjector0_rddata_status <= 32'd0;
+ litedramcore_phaseinjector0_rddata_re <= 1'd0;
+ litedramcore_phaseinjector1_command_storage <= 6'd0;
+ litedramcore_phaseinjector1_command_re <= 1'd0;
+ litedramcore_phaseinjector1_address_re <= 1'd0;
+ litedramcore_phaseinjector1_baddress_re <= 1'd0;
+ litedramcore_phaseinjector1_wrdata_re <= 1'd0;
+ litedramcore_phaseinjector1_rddata_status <= 32'd0;
+ litedramcore_phaseinjector1_rddata_re <= 1'd0;
+ litedramcore_phaseinjector2_command_storage <= 6'd0;
+ litedramcore_phaseinjector2_command_re <= 1'd0;
+ litedramcore_phaseinjector2_address_re <= 1'd0;
+ litedramcore_phaseinjector2_baddress_re <= 1'd0;
+ litedramcore_phaseinjector2_wrdata_re <= 1'd0;
+ litedramcore_phaseinjector2_rddata_status <= 32'd0;
+ litedramcore_phaseinjector2_rddata_re <= 1'd0;
+ litedramcore_phaseinjector3_command_storage <= 6'd0;
+ litedramcore_phaseinjector3_command_re <= 1'd0;
+ litedramcore_phaseinjector3_address_re <= 1'd0;
+ litedramcore_phaseinjector3_baddress_re <= 1'd0;
+ litedramcore_phaseinjector3_wrdata_re <= 1'd0;
+ litedramcore_phaseinjector3_rddata_status <= 32'd0;
+ litedramcore_phaseinjector3_rddata_re <= 1'd0;
+ litedramcore_dfi_p0_address <= 14'd0;
+ litedramcore_dfi_p0_bank <= 3'd0;
+ litedramcore_dfi_p0_cas_n <= 1'd1;
+ litedramcore_dfi_p0_cs_n <= 1'd1;
+ litedramcore_dfi_p0_ras_n <= 1'd1;
+ litedramcore_dfi_p0_we_n <= 1'd1;
+ litedramcore_dfi_p0_wrdata_en <= 1'd0;
+ litedramcore_dfi_p0_rddata_en <= 1'd0;
+ litedramcore_dfi_p1_address <= 14'd0;
+ litedramcore_dfi_p1_bank <= 3'd0;
+ litedramcore_dfi_p1_cas_n <= 1'd1;
+ litedramcore_dfi_p1_cs_n <= 1'd1;
+ litedramcore_dfi_p1_ras_n <= 1'd1;
+ litedramcore_dfi_p1_we_n <= 1'd1;
+ litedramcore_dfi_p1_wrdata_en <= 1'd0;
+ litedramcore_dfi_p1_rddata_en <= 1'd0;
+ litedramcore_dfi_p2_address <= 14'd0;
+ litedramcore_dfi_p2_bank <= 3'd0;
+ litedramcore_dfi_p2_cas_n <= 1'd1;
+ litedramcore_dfi_p2_cs_n <= 1'd1;
+ litedramcore_dfi_p2_ras_n <= 1'd1;
+ litedramcore_dfi_p2_we_n <= 1'd1;
+ litedramcore_dfi_p2_wrdata_en <= 1'd0;
+ litedramcore_dfi_p2_rddata_en <= 1'd0;
+ litedramcore_dfi_p3_address <= 14'd0;
+ litedramcore_dfi_p3_bank <= 3'd0;
+ litedramcore_dfi_p3_cas_n <= 1'd1;
+ litedramcore_dfi_p3_cs_n <= 1'd1;
+ litedramcore_dfi_p3_ras_n <= 1'd1;
+ litedramcore_dfi_p3_we_n <= 1'd1;
+ litedramcore_dfi_p3_wrdata_en <= 1'd0;
+ litedramcore_dfi_p3_rddata_en <= 1'd0;
+ litedramcore_cmd_payload_a <= 14'd0;
+ litedramcore_cmd_payload_ba <= 3'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd0;
+ litedramcore_cmd_payload_we <= 1'd0;
+ litedramcore_timer_count1 <= 10'd781;
+ litedramcore_postponer_req_o <= 1'd0;
+ litedramcore_postponer_count <= 1'd0;
+ litedramcore_sequencer_done1 <= 1'd0;
+ litedramcore_sequencer_counter <= 6'd0;
+ litedramcore_sequencer_count <= 1'd0;
+ litedramcore_zqcs_timer_count1 <= 27'd99999999;
+ litedramcore_zqcs_executer_done <= 1'd0;
+ litedramcore_zqcs_executer_counter <= 5'd0;
+ litedramcore_bankmachine0_level <= 5'd0;
+ litedramcore_bankmachine0_produce <= 4'd0;
+ litedramcore_bankmachine0_consume <= 4'd0;
+ litedramcore_bankmachine0_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine0_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine0_pipe_valid_source_payload_addr <= 21'd0;
+ litedramcore_bankmachine0_row <= 14'd0;
+ litedramcore_bankmachine0_row_opened <= 1'd0;
+ litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine0_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine0_trccon_ready <= 1'd0;
+ litedramcore_bankmachine0_trccon_count <= 3'd0;
+ litedramcore_bankmachine0_trascon_ready <= 1'd0;
+ litedramcore_bankmachine0_trascon_count <= 3'd0;
+ litedramcore_bankmachine1_level <= 5'd0;
+ litedramcore_bankmachine1_produce <= 4'd0;
+ litedramcore_bankmachine1_consume <= 4'd0;
+ litedramcore_bankmachine1_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine1_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine1_pipe_valid_source_payload_addr <= 21'd0;
+ litedramcore_bankmachine1_row <= 14'd0;
+ litedramcore_bankmachine1_row_opened <= 1'd0;
+ litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine1_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine1_trccon_ready <= 1'd0;
+ litedramcore_bankmachine1_trccon_count <= 3'd0;
+ litedramcore_bankmachine1_trascon_ready <= 1'd0;
+ litedramcore_bankmachine1_trascon_count <= 3'd0;
+ litedramcore_bankmachine2_level <= 5'd0;
+ litedramcore_bankmachine2_produce <= 4'd0;
+ litedramcore_bankmachine2_consume <= 4'd0;
+ litedramcore_bankmachine2_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine2_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine2_pipe_valid_source_payload_addr <= 21'd0;
+ litedramcore_bankmachine2_row <= 14'd0;
+ litedramcore_bankmachine2_row_opened <= 1'd0;
+ litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine2_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine2_trccon_ready <= 1'd0;
+ litedramcore_bankmachine2_trccon_count <= 3'd0;
+ litedramcore_bankmachine2_trascon_ready <= 1'd0;
+ litedramcore_bankmachine2_trascon_count <= 3'd0;
+ litedramcore_bankmachine3_level <= 5'd0;
+ litedramcore_bankmachine3_produce <= 4'd0;
+ litedramcore_bankmachine3_consume <= 4'd0;
+ litedramcore_bankmachine3_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine3_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine3_pipe_valid_source_payload_addr <= 21'd0;
+ litedramcore_bankmachine3_row <= 14'd0;
+ litedramcore_bankmachine3_row_opened <= 1'd0;
+ litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine3_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine3_trccon_ready <= 1'd0;
+ litedramcore_bankmachine3_trccon_count <= 3'd0;
+ litedramcore_bankmachine3_trascon_ready <= 1'd0;
+ litedramcore_bankmachine3_trascon_count <= 3'd0;
+ litedramcore_bankmachine4_level <= 5'd0;
+ litedramcore_bankmachine4_produce <= 4'd0;
+ litedramcore_bankmachine4_consume <= 4'd0;
+ litedramcore_bankmachine4_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine4_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine4_pipe_valid_source_payload_addr <= 21'd0;
+ litedramcore_bankmachine4_row <= 14'd0;
+ litedramcore_bankmachine4_row_opened <= 1'd0;
+ litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine4_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine4_trccon_ready <= 1'd0;
+ litedramcore_bankmachine4_trccon_count <= 3'd0;
+ litedramcore_bankmachine4_trascon_ready <= 1'd0;
+ litedramcore_bankmachine4_trascon_count <= 3'd0;
+ litedramcore_bankmachine5_level <= 5'd0;
+ litedramcore_bankmachine5_produce <= 4'd0;
+ litedramcore_bankmachine5_consume <= 4'd0;
+ litedramcore_bankmachine5_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine5_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine5_pipe_valid_source_payload_addr <= 21'd0;
+ litedramcore_bankmachine5_row <= 14'd0;
+ litedramcore_bankmachine5_row_opened <= 1'd0;
+ litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine5_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine5_trccon_ready <= 1'd0;
+ litedramcore_bankmachine5_trccon_count <= 3'd0;
+ litedramcore_bankmachine5_trascon_ready <= 1'd0;
+ litedramcore_bankmachine5_trascon_count <= 3'd0;
+ litedramcore_bankmachine6_level <= 5'd0;
+ litedramcore_bankmachine6_produce <= 4'd0;
+ litedramcore_bankmachine6_consume <= 4'd0;
+ litedramcore_bankmachine6_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine6_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine6_pipe_valid_source_payload_addr <= 21'd0;
+ litedramcore_bankmachine6_row <= 14'd0;
+ litedramcore_bankmachine6_row_opened <= 1'd0;
+ litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine6_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine6_trccon_ready <= 1'd0;
+ litedramcore_bankmachine6_trccon_count <= 3'd0;
+ litedramcore_bankmachine6_trascon_ready <= 1'd0;
+ litedramcore_bankmachine6_trascon_count <= 3'd0;
+ litedramcore_bankmachine7_level <= 5'd0;
+ litedramcore_bankmachine7_produce <= 4'd0;
+ litedramcore_bankmachine7_consume <= 4'd0;
+ litedramcore_bankmachine7_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine7_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine7_pipe_valid_source_payload_addr <= 21'd0;
+ litedramcore_bankmachine7_row <= 14'd0;
+ litedramcore_bankmachine7_row_opened <= 1'd0;
+ litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine7_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine7_trccon_ready <= 1'd0;
+ litedramcore_bankmachine7_trccon_count <= 3'd0;
+ litedramcore_bankmachine7_trascon_ready <= 1'd0;
+ litedramcore_bankmachine7_trascon_count <= 3'd0;
+ litedramcore_choose_cmd_grant <= 3'd0;
+ litedramcore_choose_req_grant <= 3'd0;
+ litedramcore_trrdcon_ready <= 1'd0;
+ litedramcore_trrdcon_count <= 1'd0;
+ litedramcore_tfawcon_ready <= 1'd1;
+ litedramcore_tfawcon_window <= 5'd0;
+ litedramcore_tccdcon_ready <= 1'd0;
+ litedramcore_tccdcon_count <= 1'd0;
+ litedramcore_twtrcon_ready <= 1'd0;
+ litedramcore_twtrcon_count <= 3'd0;
+ litedramcore_time0 <= 5'd0;
+ litedramcore_time1 <= 4'd0;
+ init_done_storage <= 1'd0;
+ init_done_re <= 1'd0;
+ init_error_storage <= 1'd0;
+ init_error_re <= 1'd0;
+ litedramcore_we <= 1'd0;
+ litedramcore_refresher_state <= 2'd0;
+ litedramcore_bankmachine0_state <= 4'd0;
+ litedramcore_bankmachine1_state <= 4'd0;
+ litedramcore_bankmachine2_state <= 4'd0;
+ litedramcore_bankmachine3_state <= 4'd0;
+ litedramcore_bankmachine4_state <= 4'd0;
+ litedramcore_bankmachine5_state <= 4'd0;
+ litedramcore_bankmachine6_state <= 4'd0;
+ litedramcore_bankmachine7_state <= 4'd0;
+ litedramcore_multiplexer_state <= 4'd0;
+ litedramcore_new_master_wdata_ready0 <= 1'd0;
+ litedramcore_new_master_wdata_ready1 <= 1'd0;
+ litedramcore_new_master_rdata_valid0 <= 1'd0;
+ litedramcore_new_master_rdata_valid1 <= 1'd0;
+ litedramcore_new_master_rdata_valid2 <= 1'd0;
+ litedramcore_new_master_rdata_valid3 <= 1'd0;
+ litedramcore_new_master_rdata_valid4 <= 1'd0;
+ litedramcore_new_master_rdata_valid5 <= 1'd0;
+ litedramcore_new_master_rdata_valid6 <= 1'd0;
+ litedramcore_new_master_rdata_valid7 <= 1'd0;
+ litedramcore_new_master_rdata_valid8 <= 1'd0;
+ litedramcore_state <= 2'd0;
+ end
end
reg [23:0] storage[0:15];
reg [23:0] storage_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we)
- storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
- storage_dat0 <= storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine0_wrport_we)
+ storage[litedramcore_bankmachine0_wrport_adr] <= litedramcore_bankmachine0_wrport_dat_w;
+ storage_dat0 <= storage[litedramcore_bankmachine0_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = storage_dat0;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine0_wrport_dat_r = storage_dat0;
+assign litedramcore_bankmachine0_rdport_dat_r = storage[litedramcore_bankmachine0_rdport_adr];
//------------------------------------------------------------------------------
reg [23:0] storage_1[0:15];
reg [23:0] storage_1_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we)
- storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
- storage_1_dat0 <= storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine1_wrport_we)
+ storage_1[litedramcore_bankmachine1_wrport_adr] <= litedramcore_bankmachine1_wrport_dat_w;
+ storage_1_dat0 <= storage_1[litedramcore_bankmachine1_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = storage_1_dat0;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine1_wrport_dat_r = storage_1_dat0;
+assign litedramcore_bankmachine1_rdport_dat_r = storage_1[litedramcore_bankmachine1_rdport_adr];
//------------------------------------------------------------------------------
reg [23:0] storage_2[0:15];
reg [23:0] storage_2_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we)
- storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
- storage_2_dat0 <= storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine2_wrport_we)
+ storage_2[litedramcore_bankmachine2_wrport_adr] <= litedramcore_bankmachine2_wrport_dat_w;
+ storage_2_dat0 <= storage_2[litedramcore_bankmachine2_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = storage_2_dat0;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine2_wrport_dat_r = storage_2_dat0;
+assign litedramcore_bankmachine2_rdport_dat_r = storage_2[litedramcore_bankmachine2_rdport_adr];
//------------------------------------------------------------------------------
reg [23:0] storage_3[0:15];
reg [23:0] storage_3_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we)
- storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
- storage_3_dat0 <= storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine3_wrport_we)
+ storage_3[litedramcore_bankmachine3_wrport_adr] <= litedramcore_bankmachine3_wrport_dat_w;
+ storage_3_dat0 <= storage_3[litedramcore_bankmachine3_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = storage_3_dat0;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine3_wrport_dat_r = storage_3_dat0;
+assign litedramcore_bankmachine3_rdport_dat_r = storage_3[litedramcore_bankmachine3_rdport_adr];
//------------------------------------------------------------------------------
reg [23:0] storage_4[0:15];
reg [23:0] storage_4_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we)
- storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
- storage_4_dat0 <= storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine4_wrport_we)
+ storage_4[litedramcore_bankmachine4_wrport_adr] <= litedramcore_bankmachine4_wrport_dat_w;
+ storage_4_dat0 <= storage_4[litedramcore_bankmachine4_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = storage_4_dat0;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine4_wrport_dat_r = storage_4_dat0;
+assign litedramcore_bankmachine4_rdport_dat_r = storage_4[litedramcore_bankmachine4_rdport_adr];
//------------------------------------------------------------------------------
reg [23:0] storage_5[0:15];
reg [23:0] storage_5_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we)
- storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
- storage_5_dat0 <= storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine5_wrport_we)
+ storage_5[litedramcore_bankmachine5_wrport_adr] <= litedramcore_bankmachine5_wrport_dat_w;
+ storage_5_dat0 <= storage_5[litedramcore_bankmachine5_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = storage_5_dat0;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine5_wrport_dat_r = storage_5_dat0;
+assign litedramcore_bankmachine5_rdport_dat_r = storage_5[litedramcore_bankmachine5_rdport_adr];
//------------------------------------------------------------------------------
reg [23:0] storage_6[0:15];
reg [23:0] storage_6_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we)
- storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
- storage_6_dat0 <= storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine6_wrport_we)
+ storage_6[litedramcore_bankmachine6_wrport_adr] <= litedramcore_bankmachine6_wrport_dat_w;
+ storage_6_dat0 <= storage_6[litedramcore_bankmachine6_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = storage_6_dat0;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine6_wrport_dat_r = storage_6_dat0;
+assign litedramcore_bankmachine6_rdport_dat_r = storage_6[litedramcore_bankmachine6_rdport_adr];
//------------------------------------------------------------------------------
reg [23:0] storage_7[0:15];
reg [23:0] storage_7_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we)
- storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
- storage_7_dat0 <= storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine7_wrport_we)
+ storage_7[litedramcore_bankmachine7_wrport_adr] <= litedramcore_bankmachine7_wrport_dat_w;
+ storage_7_dat0 <= storage_7[litedramcore_bankmachine7_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = storage_7_dat0;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine7_wrport_dat_r = storage_7_dat0;
+assign litedramcore_bankmachine7_rdport_dat_r = storage_7[litedramcore_bankmachine7_rdport_adr];
FDCE FDCE(
.LOCKED(locked)
);
-(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
+(* ars_ff1 = "true", async_reg = "true" *)
+FDPE #(
.INIT(1'd1)
) FDPE (
.C(iodelay_clk),
.Q(xilinxasyncresetsynchronizerimpl0_rst_meta)
);
-(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
+(* ars_ff2 = "true", async_reg = "true" *)
+FDPE #(
.INIT(1'd1)
) FDPE_1 (
.C(iodelay_clk),
.Q(iodelay_rst)
);
-(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
+(* ars_ff1 = "true", async_reg = "true" *)
+FDPE #(
.INIT(1'd1)
) FDPE_2 (
.C(sys_clk),
.Q(xilinxasyncresetsynchronizerimpl1_rst_meta)
);
-(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
+(* ars_ff2 = "true", async_reg = "true" *)
+FDPE #(
.INIT(1'd1)
) FDPE_3 (
.C(sys_clk),
.Q(sys_rst)
);
-(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
+(* ars_ff1 = "true", async_reg = "true" *)
+FDPE #(
.INIT(1'd1)
) FDPE_4 (
.C(sys4x_clk),
.Q(xilinxasyncresetsynchronizerimpl2_rst_meta)
);
-(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
+(* ars_ff2 = "true", async_reg = "true" *)
+FDPE #(
.INIT(1'd1)
) FDPE_5 (
.C(sys4x_clk),
.Q(xilinxasyncresetsynchronizerimpl2_expr)
);
-(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
+(* ars_ff1 = "true", async_reg = "true" *)
+FDPE #(
.INIT(1'd1)
) FDPE_6 (
.C(sys4x_dqs_clk),
.Q(xilinxasyncresetsynchronizerimpl3_rst_meta)
);
-(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
+(* ars_ff2 = "true", async_reg = "true" *)
+FDPE #(
.INIT(1'd1)
) FDPE_7 (
.C(sys4x_dqs_clk),
endmodule
// -----------------------------------------------------------------------------
-// Auto-Generated by LiteX on 2022-08-04 21:06:55.
+// Auto-Generated by LiteX on 2022-10-28 19:01:19.
//------------------------------------------------------------------------------
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//
// Filename : litedram_core.v
// Device :
-// LiteX sha1 : 6932fc51
-// Date : 2022-08-04 21:06:58
+// LiteX sha1 : --------
+// Date : 2022-10-28 19:01:21
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
module litedram_core (
- input wire clk,
- input wire rst,
- output wire pll_locked,
- output wire [14:0] ddram_a,
- output wire [2:0] ddram_ba,
- output wire ddram_ras_n,
- output wire ddram_cas_n,
- output wire ddram_we_n,
- output wire ddram_cs_n,
- output wire [3:0] ddram_dm,
- inout wire [31:0] ddram_dq,
- inout wire [3:0] ddram_dqs_p,
- inout wire [3:0] ddram_dqs_n,
- output wire ddram_clk_p,
- output wire ddram_clk_n,
- output wire ddram_cke,
- output wire ddram_odt,
- output wire ddram_reset_n,
- output wire init_done,
- output wire init_error,
- input wire [29:0] wb_ctrl_adr,
- input wire [31:0] wb_ctrl_dat_w,
- output wire [31:0] wb_ctrl_dat_r,
- input wire [3:0] wb_ctrl_sel,
- input wire wb_ctrl_cyc,
- input wire wb_ctrl_stb,
- output wire wb_ctrl_ack,
- input wire wb_ctrl_we,
- input wire [2:0] wb_ctrl_cti,
- input wire [1:0] wb_ctrl_bte,
- output wire wb_ctrl_err,
- output wire user_clk,
- output wire user_rst,
- input wire user_port_native_0_cmd_valid,
- output wire user_port_native_0_cmd_ready,
- input wire user_port_native_0_cmd_we,
- input wire [24:0] user_port_native_0_cmd_addr,
- input wire user_port_native_0_wdata_valid,
- output wire user_port_native_0_wdata_ready,
- input wire [31:0] user_port_native_0_wdata_we,
- input wire [255:0] user_port_native_0_wdata_data,
- output wire user_port_native_0_rdata_valid,
- input wire user_port_native_0_rdata_ready,
- output wire [255:0] user_port_native_0_rdata_data
+ input wire clk,
+ input wire rst,
+ output wire pll_locked,
+ output wire [14:0] ddram_a,
+ output wire [2:0] ddram_ba,
+ output wire ddram_ras_n,
+ output wire ddram_cas_n,
+ output wire ddram_we_n,
+ output wire ddram_cs_n,
+ output wire [3:0] ddram_dm,
+ inout wire [31:0] ddram_dq,
+ inout wire [3:0] ddram_dqs_p,
+ inout wire [3:0] ddram_dqs_n,
+ output wire ddram_clk_p,
+ output wire ddram_clk_n,
+ output wire ddram_cke,
+ output wire ddram_odt,
+ output wire ddram_reset_n,
+ output wire init_done,
+ output wire init_error,
+ input wire [29:0] wb_ctrl_adr,
+ input wire [31:0] wb_ctrl_dat_w,
+ output wire [31:0] wb_ctrl_dat_r,
+ input wire [3:0] wb_ctrl_sel,
+ input wire wb_ctrl_cyc,
+ input wire wb_ctrl_stb,
+ output wire wb_ctrl_ack,
+ input wire wb_ctrl_we,
+ input wire [2:0] wb_ctrl_cti,
+ input wire [1:0] wb_ctrl_bte,
+ output wire wb_ctrl_err,
+ output wire user_clk,
+ output wire user_rst,
+ input wire user_port_native_0_cmd_valid,
+ output wire user_port_native_0_cmd_ready,
+ input wire user_port_native_0_cmd_we,
+ input wire [24:0] user_port_native_0_cmd_addr,
+ input wire user_port_native_0_wdata_valid,
+ output wire user_port_native_0_wdata_ready,
+ input wire [31:0] user_port_native_0_wdata_we,
+ input wire [255:0] user_port_native_0_wdata_data,
+ output wire user_port_native_0_rdata_valid,
+ input wire user_port_native_0_rdata_ready,
+ output wire [255:0] user_port_native_0_rdata_data
);
// Signals
//------------------------------------------------------------------------------
-reg rst_1 = 1'd0;
-wire sys_clk;
-wire sys_rst;
-wire sys4x_clk;
-wire sys4x_dqs_clk;
-wire iodelay_clk;
-wire iodelay_rst;
-wire reset;
-reg power_down = 1'd0;
-wire locked;
-wire clkin;
-wire clkout0;
-wire clkout_buf0;
-wire clkout1;
-wire clkout_buf1;
-wire clkout2;
-wire clkout_buf2;
-wire clkout3;
-wire clkout_buf3;
-reg [3:0] reset_counter = 4'd15;
-reg ic_reset = 1'd1;
-reg k7ddrphy_rst_storage = 1'd0;
-reg k7ddrphy_rst_re = 1'd0;
-reg [3:0] k7ddrphy_dly_sel_storage = 4'd0;
-reg k7ddrphy_dly_sel_re = 1'd0;
-reg [4:0] k7ddrphy_half_sys8x_taps_storage = 5'd8;
-reg k7ddrphy_half_sys8x_taps_re = 1'd0;
-reg k7ddrphy_wlevel_en_storage = 1'd0;
-reg k7ddrphy_wlevel_en_re = 1'd0;
-reg k7ddrphy_wlevel_strobe_re = 1'd0;
-wire k7ddrphy_wlevel_strobe_r;
-reg k7ddrphy_wlevel_strobe_we = 1'd0;
-reg k7ddrphy_wlevel_strobe_w = 1'd0;
-reg k7ddrphy_cdly_rst_re = 1'd0;
-wire k7ddrphy_cdly_rst_r;
-reg k7ddrphy_cdly_rst_we = 1'd0;
-reg k7ddrphy_cdly_rst_w = 1'd0;
-reg k7ddrphy_cdly_inc_re = 1'd0;
-wire k7ddrphy_cdly_inc_r;
-reg k7ddrphy_cdly_inc_we = 1'd0;
-reg k7ddrphy_cdly_inc_w = 1'd0;
-reg k7ddrphy_rdly_dq_rst_re = 1'd0;
-wire k7ddrphy_rdly_dq_rst_r;
-reg k7ddrphy_rdly_dq_rst_we = 1'd0;
-reg k7ddrphy_rdly_dq_rst_w = 1'd0;
-reg k7ddrphy_rdly_dq_inc_re = 1'd0;
-wire k7ddrphy_rdly_dq_inc_r;
-reg k7ddrphy_rdly_dq_inc_we = 1'd0;
-reg k7ddrphy_rdly_dq_inc_w = 1'd0;
-reg k7ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
-wire k7ddrphy_rdly_dq_bitslip_rst_r;
-reg k7ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
-reg k7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
-reg k7ddrphy_rdly_dq_bitslip_re = 1'd0;
-wire k7ddrphy_rdly_dq_bitslip_r;
-reg k7ddrphy_rdly_dq_bitslip_we = 1'd0;
-reg k7ddrphy_rdly_dq_bitslip_w = 1'd0;
-reg k7ddrphy_wdly_dq_rst_re = 1'd0;
-wire k7ddrphy_wdly_dq_rst_r;
-reg k7ddrphy_wdly_dq_rst_we = 1'd0;
-reg k7ddrphy_wdly_dq_rst_w = 1'd0;
-reg k7ddrphy_wdly_dq_inc_re = 1'd0;
-wire k7ddrphy_wdly_dq_inc_r;
-reg k7ddrphy_wdly_dq_inc_we = 1'd0;
-reg k7ddrphy_wdly_dq_inc_w = 1'd0;
-reg k7ddrphy_wdly_dqs_rst_re = 1'd0;
-wire k7ddrphy_wdly_dqs_rst_r;
-reg k7ddrphy_wdly_dqs_rst_we = 1'd0;
-reg k7ddrphy_wdly_dqs_rst_w = 1'd0;
-reg k7ddrphy_wdly_dqs_inc_re = 1'd0;
-wire k7ddrphy_wdly_dqs_inc_r;
-reg k7ddrphy_wdly_dqs_inc_we = 1'd0;
-reg k7ddrphy_wdly_dqs_inc_w = 1'd0;
-reg k7ddrphy_wdly_dq_bitslip_rst_re = 1'd0;
-wire k7ddrphy_wdly_dq_bitslip_rst_r;
-reg k7ddrphy_wdly_dq_bitslip_rst_we = 1'd0;
-reg k7ddrphy_wdly_dq_bitslip_rst_w = 1'd0;
-reg k7ddrphy_wdly_dq_bitslip_re = 1'd0;
-wire k7ddrphy_wdly_dq_bitslip_r;
-reg k7ddrphy_wdly_dq_bitslip_we = 1'd0;
-reg k7ddrphy_wdly_dq_bitslip_w = 1'd0;
-reg [1:0] k7ddrphy_rdphase_storage = 2'd1;
-reg k7ddrphy_rdphase_re = 1'd0;
-reg [1:0] k7ddrphy_wrphase_storage = 2'd2;
-reg k7ddrphy_wrphase_re = 1'd0;
-wire [14:0] k7ddrphy_dfi_p0_address;
-wire [2:0] k7ddrphy_dfi_p0_bank;
-wire k7ddrphy_dfi_p0_cas_n;
-wire k7ddrphy_dfi_p0_cs_n;
-wire k7ddrphy_dfi_p0_ras_n;
-wire k7ddrphy_dfi_p0_we_n;
-wire k7ddrphy_dfi_p0_cke;
-wire k7ddrphy_dfi_p0_odt;
-wire k7ddrphy_dfi_p0_reset_n;
-wire k7ddrphy_dfi_p0_act_n;
-wire [63:0] k7ddrphy_dfi_p0_wrdata;
-wire k7ddrphy_dfi_p0_wrdata_en;
-wire [7:0] k7ddrphy_dfi_p0_wrdata_mask;
-wire k7ddrphy_dfi_p0_rddata_en;
-reg [63:0] k7ddrphy_dfi_p0_rddata = 64'd0;
-wire k7ddrphy_dfi_p0_rddata_valid;
-wire [14:0] k7ddrphy_dfi_p1_address;
-wire [2:0] k7ddrphy_dfi_p1_bank;
-wire k7ddrphy_dfi_p1_cas_n;
-wire k7ddrphy_dfi_p1_cs_n;
-wire k7ddrphy_dfi_p1_ras_n;
-wire k7ddrphy_dfi_p1_we_n;
-wire k7ddrphy_dfi_p1_cke;
-wire k7ddrphy_dfi_p1_odt;
-wire k7ddrphy_dfi_p1_reset_n;
-wire k7ddrphy_dfi_p1_act_n;
-wire [63:0] k7ddrphy_dfi_p1_wrdata;
-wire k7ddrphy_dfi_p1_wrdata_en;
-wire [7:0] k7ddrphy_dfi_p1_wrdata_mask;
-wire k7ddrphy_dfi_p1_rddata_en;
-reg [63:0] k7ddrphy_dfi_p1_rddata = 64'd0;
-wire k7ddrphy_dfi_p1_rddata_valid;
-wire [14:0] k7ddrphy_dfi_p2_address;
-wire [2:0] k7ddrphy_dfi_p2_bank;
-wire k7ddrphy_dfi_p2_cas_n;
-wire k7ddrphy_dfi_p2_cs_n;
-wire k7ddrphy_dfi_p2_ras_n;
-wire k7ddrphy_dfi_p2_we_n;
-wire k7ddrphy_dfi_p2_cke;
-wire k7ddrphy_dfi_p2_odt;
-wire k7ddrphy_dfi_p2_reset_n;
-wire k7ddrphy_dfi_p2_act_n;
-wire [63:0] k7ddrphy_dfi_p2_wrdata;
-wire k7ddrphy_dfi_p2_wrdata_en;
-wire [7:0] k7ddrphy_dfi_p2_wrdata_mask;
-wire k7ddrphy_dfi_p2_rddata_en;
-reg [63:0] k7ddrphy_dfi_p2_rddata = 64'd0;
-wire k7ddrphy_dfi_p2_rddata_valid;
-wire [14:0] k7ddrphy_dfi_p3_address;
-wire [2:0] k7ddrphy_dfi_p3_bank;
-wire k7ddrphy_dfi_p3_cas_n;
-wire k7ddrphy_dfi_p3_cs_n;
-wire k7ddrphy_dfi_p3_ras_n;
-wire k7ddrphy_dfi_p3_we_n;
-wire k7ddrphy_dfi_p3_cke;
-wire k7ddrphy_dfi_p3_odt;
-wire k7ddrphy_dfi_p3_reset_n;
-wire k7ddrphy_dfi_p3_act_n;
-wire [63:0] k7ddrphy_dfi_p3_wrdata;
-wire k7ddrphy_dfi_p3_wrdata_en;
-wire [7:0] k7ddrphy_dfi_p3_wrdata_mask;
-wire k7ddrphy_dfi_p3_rddata_en;
-reg [63:0] k7ddrphy_dfi_p3_rddata = 64'd0;
-wire k7ddrphy_dfi_p3_rddata_valid;
-wire k7ddrphy_sd_clk_se_nodelay;
-wire k7ddrphy_sd_clk_se_delayed;
-wire [2:0] k7ddrphy_pads_ba;
-wire k7ddrphy_oq0;
-wire k7ddrphy_oq1;
-wire k7ddrphy_oq2;
-wire k7ddrphy_oq3;
-wire k7ddrphy_oq4;
-wire k7ddrphy_oq5;
-wire k7ddrphy_oq6;
-wire k7ddrphy_oq7;
-wire k7ddrphy_oq8;
-wire k7ddrphy_oq9;
-wire k7ddrphy_oq10;
-wire k7ddrphy_oq11;
-wire k7ddrphy_oq12;
-wire k7ddrphy_oq13;
-wire k7ddrphy_oq14;
-wire k7ddrphy_oq15;
-wire k7ddrphy_oq16;
-wire k7ddrphy_oq17;
-wire k7ddrphy_oq18;
-wire k7ddrphy_oq19;
-wire k7ddrphy_oq20;
-wire k7ddrphy_oq21;
-wire k7ddrphy_oq22;
-wire k7ddrphy_oq23;
-wire k7ddrphy_oq24;
-reg k7ddrphy_dqs_oe = 1'd0;
-wire k7ddrphy_dqs_preamble;
-wire k7ddrphy_dqs_postamble;
-wire k7ddrphy_dqs_oe_delay_tappeddelayline;
-reg k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
-reg k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
-reg k7ddrphy_dqspattern0 = 1'd0;
-reg k7ddrphy_dqspattern1 = 1'd0;
-reg [7:0] k7ddrphy_dqspattern_o = 8'd0;
-wire k7ddrphy_dqs_o_no_delay0;
-wire k7ddrphy_dqs_o_delayed0;
-wire k7ddrphy_dqs_t0;
-reg [7:0] k7ddrphy_bitslip00 = 8'd0;
-reg [2:0] k7ddrphy_bitslip0_value0 = 3'd7;
-reg [15:0] k7ddrphy_bitslip0_r0 = 16'd0;
-wire k7ddrphy0;
-wire k7ddrphy_dqs_o_no_delay1;
-wire k7ddrphy_dqs_o_delayed1;
-wire k7ddrphy_dqs_t1;
-reg [7:0] k7ddrphy_bitslip10 = 8'd0;
-reg [2:0] k7ddrphy_bitslip1_value0 = 3'd7;
-reg [15:0] k7ddrphy_bitslip1_r0 = 16'd0;
-wire k7ddrphy1;
-wire k7ddrphy_dqs_o_no_delay2;
-wire k7ddrphy_dqs_o_delayed2;
-wire k7ddrphy_dqs_t2;
-reg [7:0] k7ddrphy_bitslip20 = 8'd0;
-reg [2:0] k7ddrphy_bitslip2_value0 = 3'd7;
-reg [15:0] k7ddrphy_bitslip2_r0 = 16'd0;
-wire k7ddrphy2;
-wire k7ddrphy_dqs_o_no_delay3;
-wire k7ddrphy_dqs_o_delayed3;
-wire k7ddrphy_dqs_t3;
-reg [7:0] k7ddrphy_bitslip30 = 8'd0;
-reg [2:0] k7ddrphy_bitslip3_value0 = 3'd7;
-reg [15:0] k7ddrphy_bitslip3_r0 = 16'd0;
-wire k7ddrphy3;
-wire k7ddrphy_dm_o_nodelay0;
-reg [7:0] k7ddrphy_bitslip01 = 8'd0;
-reg [2:0] k7ddrphy_bitslip0_value1 = 3'd7;
-reg [15:0] k7ddrphy_bitslip0_r1 = 16'd0;
-wire k7ddrphy_dm_o_nodelay1;
-reg [7:0] k7ddrphy_bitslip11 = 8'd0;
-reg [2:0] k7ddrphy_bitslip1_value1 = 3'd7;
-reg [15:0] k7ddrphy_bitslip1_r1 = 16'd0;
-wire k7ddrphy_dm_o_nodelay2;
-reg [7:0] k7ddrphy_bitslip21 = 8'd0;
-reg [2:0] k7ddrphy_bitslip2_value1 = 3'd7;
-reg [15:0] k7ddrphy_bitslip2_r1 = 16'd0;
-wire k7ddrphy_dm_o_nodelay3;
-reg [7:0] k7ddrphy_bitslip31 = 8'd0;
-reg [2:0] k7ddrphy_bitslip3_value1 = 3'd7;
-reg [15:0] k7ddrphy_bitslip3_r1 = 16'd0;
-wire k7ddrphy_dq_oe;
-wire k7ddrphy_dq_oe_delay_tappeddelayline;
-reg k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
-reg k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
-wire k7ddrphy_dq_o_nodelay0;
-wire k7ddrphy_dq_o_delayed0;
-wire k7ddrphy_dq_i_nodelay0;
-wire k7ddrphy_dq_i_delayed0;
-wire k7ddrphy_dq_t0;
-reg [7:0] k7ddrphy_bitslip02 = 8'd0;
-reg [2:0] k7ddrphy_bitslip0_value2 = 3'd7;
-reg [15:0] k7ddrphy_bitslip0_r2 = 16'd0;
-wire [7:0] k7ddrphy_bitslip03;
-reg [7:0] k7ddrphy_bitslip04 = 8'd0;
-reg [2:0] k7ddrphy_bitslip0_value3 = 3'd7;
-reg [15:0] k7ddrphy_bitslip0_r3 = 16'd0;
-wire k7ddrphy_dq_o_nodelay1;
-wire k7ddrphy_dq_o_delayed1;
-wire k7ddrphy_dq_i_nodelay1;
-wire k7ddrphy_dq_i_delayed1;
-wire k7ddrphy_dq_t1;
-reg [7:0] k7ddrphy_bitslip12 = 8'd0;
-reg [2:0] k7ddrphy_bitslip1_value2 = 3'd7;
-reg [15:0] k7ddrphy_bitslip1_r2 = 16'd0;
-wire [7:0] k7ddrphy_bitslip13;
-reg [7:0] k7ddrphy_bitslip14 = 8'd0;
-reg [2:0] k7ddrphy_bitslip1_value3 = 3'd7;
-reg [15:0] k7ddrphy_bitslip1_r3 = 16'd0;
-wire k7ddrphy_dq_o_nodelay2;
-wire k7ddrphy_dq_o_delayed2;
-wire k7ddrphy_dq_i_nodelay2;
-wire k7ddrphy_dq_i_delayed2;
-wire k7ddrphy_dq_t2;
-reg [7:0] k7ddrphy_bitslip22 = 8'd0;
-reg [2:0] k7ddrphy_bitslip2_value2 = 3'd7;
-reg [15:0] k7ddrphy_bitslip2_r2 = 16'd0;
-wire [7:0] k7ddrphy_bitslip23;
-reg [7:0] k7ddrphy_bitslip24 = 8'd0;
-reg [2:0] k7ddrphy_bitslip2_value3 = 3'd7;
-reg [15:0] k7ddrphy_bitslip2_r3 = 16'd0;
-wire k7ddrphy_dq_o_nodelay3;
-wire k7ddrphy_dq_o_delayed3;
-wire k7ddrphy_dq_i_nodelay3;
-wire k7ddrphy_dq_i_delayed3;
-wire k7ddrphy_dq_t3;
-reg [7:0] k7ddrphy_bitslip32 = 8'd0;
-reg [2:0] k7ddrphy_bitslip3_value2 = 3'd7;
-reg [15:0] k7ddrphy_bitslip3_r2 = 16'd0;
-wire [7:0] k7ddrphy_bitslip33;
-reg [7:0] k7ddrphy_bitslip34 = 8'd0;
-reg [2:0] k7ddrphy_bitslip3_value3 = 3'd7;
-reg [15:0] k7ddrphy_bitslip3_r3 = 16'd0;
-wire k7ddrphy_dq_o_nodelay4;
-wire k7ddrphy_dq_o_delayed4;
-wire k7ddrphy_dq_i_nodelay4;
-wire k7ddrphy_dq_i_delayed4;
-wire k7ddrphy_dq_t4;
-reg [7:0] k7ddrphy_bitslip40 = 8'd0;
-reg [2:0] k7ddrphy_bitslip4_value0 = 3'd7;
-reg [15:0] k7ddrphy_bitslip4_r0 = 16'd0;
-wire [7:0] k7ddrphy_bitslip41;
-reg [7:0] k7ddrphy_bitslip42 = 8'd0;
-reg [2:0] k7ddrphy_bitslip4_value1 = 3'd7;
-reg [15:0] k7ddrphy_bitslip4_r1 = 16'd0;
-wire k7ddrphy_dq_o_nodelay5;
-wire k7ddrphy_dq_o_delayed5;
-wire k7ddrphy_dq_i_nodelay5;
-wire k7ddrphy_dq_i_delayed5;
-wire k7ddrphy_dq_t5;
-reg [7:0] k7ddrphy_bitslip50 = 8'd0;
-reg [2:0] k7ddrphy_bitslip5_value0 = 3'd7;
-reg [15:0] k7ddrphy_bitslip5_r0 = 16'd0;
-wire [7:0] k7ddrphy_bitslip51;
-reg [7:0] k7ddrphy_bitslip52 = 8'd0;
-reg [2:0] k7ddrphy_bitslip5_value1 = 3'd7;
-reg [15:0] k7ddrphy_bitslip5_r1 = 16'd0;
-wire k7ddrphy_dq_o_nodelay6;
-wire k7ddrphy_dq_o_delayed6;
-wire k7ddrphy_dq_i_nodelay6;
-wire k7ddrphy_dq_i_delayed6;
-wire k7ddrphy_dq_t6;
-reg [7:0] k7ddrphy_bitslip60 = 8'd0;
-reg [2:0] k7ddrphy_bitslip6_value0 = 3'd7;
-reg [15:0] k7ddrphy_bitslip6_r0 = 16'd0;
-wire [7:0] k7ddrphy_bitslip61;
-reg [7:0] k7ddrphy_bitslip62 = 8'd0;
-reg [2:0] k7ddrphy_bitslip6_value1 = 3'd7;
-reg [15:0] k7ddrphy_bitslip6_r1 = 16'd0;
-wire k7ddrphy_dq_o_nodelay7;
-wire k7ddrphy_dq_o_delayed7;
-wire k7ddrphy_dq_i_nodelay7;
-wire k7ddrphy_dq_i_delayed7;
-wire k7ddrphy_dq_t7;
-reg [7:0] k7ddrphy_bitslip70 = 8'd0;
-reg [2:0] k7ddrphy_bitslip7_value0 = 3'd7;
-reg [15:0] k7ddrphy_bitslip7_r0 = 16'd0;
-wire [7:0] k7ddrphy_bitslip71;
-reg [7:0] k7ddrphy_bitslip72 = 8'd0;
-reg [2:0] k7ddrphy_bitslip7_value1 = 3'd7;
-reg [15:0] k7ddrphy_bitslip7_r1 = 16'd0;
-wire k7ddrphy_dq_o_nodelay8;
-wire k7ddrphy_dq_o_delayed8;
-wire k7ddrphy_dq_i_nodelay8;
-wire k7ddrphy_dq_i_delayed8;
-wire k7ddrphy_dq_t8;
-reg [7:0] k7ddrphy_bitslip80 = 8'd0;
-reg [2:0] k7ddrphy_bitslip8_value0 = 3'd7;
-reg [15:0] k7ddrphy_bitslip8_r0 = 16'd0;
-wire [7:0] k7ddrphy_bitslip81;
-reg [7:0] k7ddrphy_bitslip82 = 8'd0;
-reg [2:0] k7ddrphy_bitslip8_value1 = 3'd7;
-reg [15:0] k7ddrphy_bitslip8_r1 = 16'd0;
-wire k7ddrphy_dq_o_nodelay9;
-wire k7ddrphy_dq_o_delayed9;
-wire k7ddrphy_dq_i_nodelay9;
-wire k7ddrphy_dq_i_delayed9;
-wire k7ddrphy_dq_t9;
-reg [7:0] k7ddrphy_bitslip90 = 8'd0;
-reg [2:0] k7ddrphy_bitslip9_value0 = 3'd7;
-reg [15:0] k7ddrphy_bitslip9_r0 = 16'd0;
-wire [7:0] k7ddrphy_bitslip91;
-reg [7:0] k7ddrphy_bitslip92 = 8'd0;
-reg [2:0] k7ddrphy_bitslip9_value1 = 3'd7;
-reg [15:0] k7ddrphy_bitslip9_r1 = 16'd0;
-wire k7ddrphy_dq_o_nodelay10;
-wire k7ddrphy_dq_o_delayed10;
-wire k7ddrphy_dq_i_nodelay10;
-wire k7ddrphy_dq_i_delayed10;
-wire k7ddrphy_dq_t10;
-reg [7:0] k7ddrphy_bitslip100 = 8'd0;
-reg [2:0] k7ddrphy_bitslip10_value0 = 3'd7;
-reg [15:0] k7ddrphy_bitslip10_r0 = 16'd0;
-wire [7:0] k7ddrphy_bitslip101;
-reg [7:0] k7ddrphy_bitslip102 = 8'd0;
-reg [2:0] k7ddrphy_bitslip10_value1 = 3'd7;
-reg [15:0] k7ddrphy_bitslip10_r1 = 16'd0;
-wire k7ddrphy_dq_o_nodelay11;
-wire k7ddrphy_dq_o_delayed11;
-wire k7ddrphy_dq_i_nodelay11;
-wire k7ddrphy_dq_i_delayed11;
-wire k7ddrphy_dq_t11;
-reg [7:0] k7ddrphy_bitslip110 = 8'd0;
-reg [2:0] k7ddrphy_bitslip11_value0 = 3'd7;
-reg [15:0] k7ddrphy_bitslip11_r0 = 16'd0;
-wire [7:0] k7ddrphy_bitslip111;
-reg [7:0] k7ddrphy_bitslip112 = 8'd0;
-reg [2:0] k7ddrphy_bitslip11_value1 = 3'd7;
-reg [15:0] k7ddrphy_bitslip11_r1 = 16'd0;
-wire k7ddrphy_dq_o_nodelay12;
-wire k7ddrphy_dq_o_delayed12;
-wire k7ddrphy_dq_i_nodelay12;
-wire k7ddrphy_dq_i_delayed12;
-wire k7ddrphy_dq_t12;
-reg [7:0] k7ddrphy_bitslip120 = 8'd0;
-reg [2:0] k7ddrphy_bitslip12_value0 = 3'd7;
-reg [15:0] k7ddrphy_bitslip12_r0 = 16'd0;
-wire [7:0] k7ddrphy_bitslip121;
-reg [7:0] k7ddrphy_bitslip122 = 8'd0;
-reg [2:0] k7ddrphy_bitslip12_value1 = 3'd7;
-reg [15:0] k7ddrphy_bitslip12_r1 = 16'd0;
-wire k7ddrphy_dq_o_nodelay13;
-wire k7ddrphy_dq_o_delayed13;
-wire k7ddrphy_dq_i_nodelay13;
-wire k7ddrphy_dq_i_delayed13;
-wire k7ddrphy_dq_t13;
-reg [7:0] k7ddrphy_bitslip130 = 8'd0;
-reg [2:0] k7ddrphy_bitslip13_value0 = 3'd7;
-reg [15:0] k7ddrphy_bitslip13_r0 = 16'd0;
-wire [7:0] k7ddrphy_bitslip131;
-reg [7:0] k7ddrphy_bitslip132 = 8'd0;
-reg [2:0] k7ddrphy_bitslip13_value1 = 3'd7;
-reg [15:0] k7ddrphy_bitslip13_r1 = 16'd0;
-wire k7ddrphy_dq_o_nodelay14;
-wire k7ddrphy_dq_o_delayed14;
-wire k7ddrphy_dq_i_nodelay14;
-wire k7ddrphy_dq_i_delayed14;
-wire k7ddrphy_dq_t14;
-reg [7:0] k7ddrphy_bitslip140 = 8'd0;
-reg [2:0] k7ddrphy_bitslip14_value0 = 3'd7;
-reg [15:0] k7ddrphy_bitslip14_r0 = 16'd0;
-wire [7:0] k7ddrphy_bitslip141;
-reg [7:0] k7ddrphy_bitslip142 = 8'd0;
-reg [2:0] k7ddrphy_bitslip14_value1 = 3'd7;
-reg [15:0] k7ddrphy_bitslip14_r1 = 16'd0;
-wire k7ddrphy_dq_o_nodelay15;
-wire k7ddrphy_dq_o_delayed15;
-wire k7ddrphy_dq_i_nodelay15;
-wire k7ddrphy_dq_i_delayed15;
-wire k7ddrphy_dq_t15;
-reg [7:0] k7ddrphy_bitslip150 = 8'd0;
-reg [2:0] k7ddrphy_bitslip15_value0 = 3'd7;
-reg [15:0] k7ddrphy_bitslip15_r0 = 16'd0;
-wire [7:0] k7ddrphy_bitslip151;
-reg [7:0] k7ddrphy_bitslip152 = 8'd0;
-reg [2:0] k7ddrphy_bitslip15_value1 = 3'd7;
-reg [15:0] k7ddrphy_bitslip15_r1 = 16'd0;
-wire k7ddrphy_dq_o_nodelay16;
-wire k7ddrphy_dq_o_delayed16;
-wire k7ddrphy_dq_i_nodelay16;
-wire k7ddrphy_dq_i_delayed16;
-wire k7ddrphy_dq_t16;
-reg [7:0] k7ddrphy_bitslip160 = 8'd0;
-reg [2:0] k7ddrphy_bitslip16_value0 = 3'd7;
-reg [15:0] k7ddrphy_bitslip16_r0 = 16'd0;
-wire [7:0] k7ddrphy_bitslip161;
-reg [7:0] k7ddrphy_bitslip162 = 8'd0;
-reg [2:0] k7ddrphy_bitslip16_value1 = 3'd7;
-reg [15:0] k7ddrphy_bitslip16_r1 = 16'd0;
-wire k7ddrphy_dq_o_nodelay17;
-wire k7ddrphy_dq_o_delayed17;
-wire k7ddrphy_dq_i_nodelay17;
-wire k7ddrphy_dq_i_delayed17;
-wire k7ddrphy_dq_t17;
-reg [7:0] k7ddrphy_bitslip170 = 8'd0;
-reg [2:0] k7ddrphy_bitslip17_value0 = 3'd7;
-reg [15:0] k7ddrphy_bitslip17_r0 = 16'd0;
-wire [7:0] k7ddrphy_bitslip171;
-reg [7:0] k7ddrphy_bitslip172 = 8'd0;
-reg [2:0] k7ddrphy_bitslip17_value1 = 3'd7;
-reg [15:0] k7ddrphy_bitslip17_r1 = 16'd0;
-wire k7ddrphy_dq_o_nodelay18;
-wire k7ddrphy_dq_o_delayed18;
-wire k7ddrphy_dq_i_nodelay18;
-wire k7ddrphy_dq_i_delayed18;
-wire k7ddrphy_dq_t18;
-reg [7:0] k7ddrphy_bitslip180 = 8'd0;
-reg [2:0] k7ddrphy_bitslip18_value0 = 3'd7;
-reg [15:0] k7ddrphy_bitslip18_r0 = 16'd0;
-wire [7:0] k7ddrphy_bitslip181;
-reg [7:0] k7ddrphy_bitslip182 = 8'd0;
-reg [2:0] k7ddrphy_bitslip18_value1 = 3'd7;
-reg [15:0] k7ddrphy_bitslip18_r1 = 16'd0;
-wire k7ddrphy_dq_o_nodelay19;
-wire k7ddrphy_dq_o_delayed19;
-wire k7ddrphy_dq_i_nodelay19;
-wire k7ddrphy_dq_i_delayed19;
-wire k7ddrphy_dq_t19;
-reg [7:0] k7ddrphy_bitslip190 = 8'd0;
-reg [2:0] k7ddrphy_bitslip19_value0 = 3'd7;
-reg [15:0] k7ddrphy_bitslip19_r0 = 16'd0;
-wire [7:0] k7ddrphy_bitslip191;
-reg [7:0] k7ddrphy_bitslip192 = 8'd0;
-reg [2:0] k7ddrphy_bitslip19_value1 = 3'd7;
-reg [15:0] k7ddrphy_bitslip19_r1 = 16'd0;
-wire k7ddrphy_dq_o_nodelay20;
-wire k7ddrphy_dq_o_delayed20;
-wire k7ddrphy_dq_i_nodelay20;
-wire k7ddrphy_dq_i_delayed20;
-wire k7ddrphy_dq_t20;
-reg [7:0] k7ddrphy_bitslip200 = 8'd0;
-reg [2:0] k7ddrphy_bitslip20_value0 = 3'd7;
-reg [15:0] k7ddrphy_bitslip20_r0 = 16'd0;
-wire [7:0] k7ddrphy_bitslip201;
-reg [7:0] k7ddrphy_bitslip202 = 8'd0;
-reg [2:0] k7ddrphy_bitslip20_value1 = 3'd7;
-reg [15:0] k7ddrphy_bitslip20_r1 = 16'd0;
-wire k7ddrphy_dq_o_nodelay21;
-wire k7ddrphy_dq_o_delayed21;
-wire k7ddrphy_dq_i_nodelay21;
-wire k7ddrphy_dq_i_delayed21;
-wire k7ddrphy_dq_t21;
-reg [7:0] k7ddrphy_bitslip210 = 8'd0;
-reg [2:0] k7ddrphy_bitslip21_value0 = 3'd7;
-reg [15:0] k7ddrphy_bitslip21_r0 = 16'd0;
-wire [7:0] k7ddrphy_bitslip211;
-reg [7:0] k7ddrphy_bitslip212 = 8'd0;
-reg [2:0] k7ddrphy_bitslip21_value1 = 3'd7;
-reg [15:0] k7ddrphy_bitslip21_r1 = 16'd0;
-wire k7ddrphy_dq_o_nodelay22;
-wire k7ddrphy_dq_o_delayed22;
-wire k7ddrphy_dq_i_nodelay22;
-wire k7ddrphy_dq_i_delayed22;
-wire k7ddrphy_dq_t22;
-reg [7:0] k7ddrphy_bitslip220 = 8'd0;
-reg [2:0] k7ddrphy_bitslip22_value0 = 3'd7;
-reg [15:0] k7ddrphy_bitslip22_r0 = 16'd0;
-wire [7:0] k7ddrphy_bitslip221;
-reg [7:0] k7ddrphy_bitslip222 = 8'd0;
-reg [2:0] k7ddrphy_bitslip22_value1 = 3'd7;
-reg [15:0] k7ddrphy_bitslip22_r1 = 16'd0;
-wire k7ddrphy_dq_o_nodelay23;
-wire k7ddrphy_dq_o_delayed23;
-wire k7ddrphy_dq_i_nodelay23;
-wire k7ddrphy_dq_i_delayed23;
-wire k7ddrphy_dq_t23;
-reg [7:0] k7ddrphy_bitslip230 = 8'd0;
-reg [2:0] k7ddrphy_bitslip23_value0 = 3'd7;
-reg [15:0] k7ddrphy_bitslip23_r0 = 16'd0;
-wire [7:0] k7ddrphy_bitslip231;
-reg [7:0] k7ddrphy_bitslip232 = 8'd0;
-reg [2:0] k7ddrphy_bitslip23_value1 = 3'd7;
-reg [15:0] k7ddrphy_bitslip23_r1 = 16'd0;
-wire k7ddrphy_dq_o_nodelay24;
-wire k7ddrphy_dq_o_delayed24;
-wire k7ddrphy_dq_i_nodelay24;
-wire k7ddrphy_dq_i_delayed24;
-wire k7ddrphy_dq_t24;
-reg [7:0] k7ddrphy_bitslip240 = 8'd0;
-reg [2:0] k7ddrphy_bitslip24_value0 = 3'd7;
-reg [15:0] k7ddrphy_bitslip24_r0 = 16'd0;
-wire [7:0] k7ddrphy_bitslip241;
-reg [7:0] k7ddrphy_bitslip242 = 8'd0;
-reg [2:0] k7ddrphy_bitslip24_value1 = 3'd7;
-reg [15:0] k7ddrphy_bitslip24_r1 = 16'd0;
-wire k7ddrphy_dq_o_nodelay25;
-wire k7ddrphy_dq_o_delayed25;
-wire k7ddrphy_dq_i_nodelay25;
-wire k7ddrphy_dq_i_delayed25;
-wire k7ddrphy_dq_t25;
-reg [7:0] k7ddrphy_bitslip250 = 8'd0;
-reg [2:0] k7ddrphy_bitslip25_value0 = 3'd7;
-reg [15:0] k7ddrphy_bitslip25_r0 = 16'd0;
-wire [7:0] k7ddrphy_bitslip251;
-reg [7:0] k7ddrphy_bitslip252 = 8'd0;
-reg [2:0] k7ddrphy_bitslip25_value1 = 3'd7;
-reg [15:0] k7ddrphy_bitslip25_r1 = 16'd0;
-wire k7ddrphy_dq_o_nodelay26;
-wire k7ddrphy_dq_o_delayed26;
-wire k7ddrphy_dq_i_nodelay26;
-wire k7ddrphy_dq_i_delayed26;
-wire k7ddrphy_dq_t26;
-reg [7:0] k7ddrphy_bitslip260 = 8'd0;
-reg [2:0] k7ddrphy_bitslip26_value0 = 3'd7;
-reg [15:0] k7ddrphy_bitslip26_r0 = 16'd0;
-wire [7:0] k7ddrphy_bitslip261;
-reg [7:0] k7ddrphy_bitslip262 = 8'd0;
-reg [2:0] k7ddrphy_bitslip26_value1 = 3'd7;
-reg [15:0] k7ddrphy_bitslip26_r1 = 16'd0;
-wire k7ddrphy_dq_o_nodelay27;
-wire k7ddrphy_dq_o_delayed27;
-wire k7ddrphy_dq_i_nodelay27;
-wire k7ddrphy_dq_i_delayed27;
-wire k7ddrphy_dq_t27;
-reg [7:0] k7ddrphy_bitslip270 = 8'd0;
-reg [2:0] k7ddrphy_bitslip27_value0 = 3'd7;
-reg [15:0] k7ddrphy_bitslip27_r0 = 16'd0;
-wire [7:0] k7ddrphy_bitslip271;
-reg [7:0] k7ddrphy_bitslip272 = 8'd0;
-reg [2:0] k7ddrphy_bitslip27_value1 = 3'd7;
-reg [15:0] k7ddrphy_bitslip27_r1 = 16'd0;
-wire k7ddrphy_dq_o_nodelay28;
-wire k7ddrphy_dq_o_delayed28;
-wire k7ddrphy_dq_i_nodelay28;
-wire k7ddrphy_dq_i_delayed28;
-wire k7ddrphy_dq_t28;
-reg [7:0] k7ddrphy_bitslip280 = 8'd0;
-reg [2:0] k7ddrphy_bitslip28_value0 = 3'd7;
-reg [15:0] k7ddrphy_bitslip28_r0 = 16'd0;
-wire [7:0] k7ddrphy_bitslip281;
-reg [7:0] k7ddrphy_bitslip282 = 8'd0;
-reg [2:0] k7ddrphy_bitslip28_value1 = 3'd7;
-reg [15:0] k7ddrphy_bitslip28_r1 = 16'd0;
-wire k7ddrphy_dq_o_nodelay29;
-wire k7ddrphy_dq_o_delayed29;
-wire k7ddrphy_dq_i_nodelay29;
-wire k7ddrphy_dq_i_delayed29;
-wire k7ddrphy_dq_t29;
-reg [7:0] k7ddrphy_bitslip290 = 8'd0;
-reg [2:0] k7ddrphy_bitslip29_value0 = 3'd7;
-reg [15:0] k7ddrphy_bitslip29_r0 = 16'd0;
-wire [7:0] k7ddrphy_bitslip291;
-reg [7:0] k7ddrphy_bitslip292 = 8'd0;
-reg [2:0] k7ddrphy_bitslip29_value1 = 3'd7;
-reg [15:0] k7ddrphy_bitslip29_r1 = 16'd0;
-wire k7ddrphy_dq_o_nodelay30;
-wire k7ddrphy_dq_o_delayed30;
-wire k7ddrphy_dq_i_nodelay30;
-wire k7ddrphy_dq_i_delayed30;
-wire k7ddrphy_dq_t30;
-reg [7:0] k7ddrphy_bitslip300 = 8'd0;
-reg [2:0] k7ddrphy_bitslip30_value0 = 3'd7;
-reg [15:0] k7ddrphy_bitslip30_r0 = 16'd0;
-wire [7:0] k7ddrphy_bitslip301;
-reg [7:0] k7ddrphy_bitslip302 = 8'd0;
-reg [2:0] k7ddrphy_bitslip30_value1 = 3'd7;
-reg [15:0] k7ddrphy_bitslip30_r1 = 16'd0;
-wire k7ddrphy_dq_o_nodelay31;
-wire k7ddrphy_dq_o_delayed31;
-wire k7ddrphy_dq_i_nodelay31;
-wire k7ddrphy_dq_i_delayed31;
-wire k7ddrphy_dq_t31;
-reg [7:0] k7ddrphy_bitslip310 = 8'd0;
-reg [2:0] k7ddrphy_bitslip31_value0 = 3'd7;
-reg [15:0] k7ddrphy_bitslip31_r0 = 16'd0;
-wire [7:0] k7ddrphy_bitslip311;
-reg [7:0] k7ddrphy_bitslip312 = 8'd0;
-reg [2:0] k7ddrphy_bitslip31_value1 = 3'd7;
-reg [15:0] k7ddrphy_bitslip31_r1 = 16'd0;
-reg k7ddrphy_rddata_en_tappeddelayline0 = 1'd0;
-reg k7ddrphy_rddata_en_tappeddelayline1 = 1'd0;
-reg k7ddrphy_rddata_en_tappeddelayline2 = 1'd0;
-reg k7ddrphy_rddata_en_tappeddelayline3 = 1'd0;
-reg k7ddrphy_rddata_en_tappeddelayline4 = 1'd0;
-reg k7ddrphy_rddata_en_tappeddelayline5 = 1'd0;
-reg k7ddrphy_rddata_en_tappeddelayline6 = 1'd0;
-reg k7ddrphy_rddata_en_tappeddelayline7 = 1'd0;
-reg k7ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
-reg k7ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
-reg k7ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
-wire [14:0] litedramcore_slave_p0_address;
-wire [2:0] litedramcore_slave_p0_bank;
-wire litedramcore_slave_p0_cas_n;
-wire litedramcore_slave_p0_cs_n;
-wire litedramcore_slave_p0_ras_n;
-wire litedramcore_slave_p0_we_n;
-wire litedramcore_slave_p0_cke;
-wire litedramcore_slave_p0_odt;
-wire litedramcore_slave_p0_reset_n;
-wire litedramcore_slave_p0_act_n;
-wire [63:0] litedramcore_slave_p0_wrdata;
-wire litedramcore_slave_p0_wrdata_en;
-wire [7:0] litedramcore_slave_p0_wrdata_mask;
-wire litedramcore_slave_p0_rddata_en;
-reg [63:0] litedramcore_slave_p0_rddata = 64'd0;
-reg litedramcore_slave_p0_rddata_valid = 1'd0;
-wire [14:0] litedramcore_slave_p1_address;
-wire [2:0] litedramcore_slave_p1_bank;
-wire litedramcore_slave_p1_cas_n;
-wire litedramcore_slave_p1_cs_n;
-wire litedramcore_slave_p1_ras_n;
-wire litedramcore_slave_p1_we_n;
-wire litedramcore_slave_p1_cke;
-wire litedramcore_slave_p1_odt;
-wire litedramcore_slave_p1_reset_n;
-wire litedramcore_slave_p1_act_n;
-wire [63:0] litedramcore_slave_p1_wrdata;
-wire litedramcore_slave_p1_wrdata_en;
-wire [7:0] litedramcore_slave_p1_wrdata_mask;
-wire litedramcore_slave_p1_rddata_en;
-reg [63:0] litedramcore_slave_p1_rddata = 64'd0;
-reg litedramcore_slave_p1_rddata_valid = 1'd0;
-wire [14:0] litedramcore_slave_p2_address;
-wire [2:0] litedramcore_slave_p2_bank;
-wire litedramcore_slave_p2_cas_n;
-wire litedramcore_slave_p2_cs_n;
-wire litedramcore_slave_p2_ras_n;
-wire litedramcore_slave_p2_we_n;
-wire litedramcore_slave_p2_cke;
-wire litedramcore_slave_p2_odt;
-wire litedramcore_slave_p2_reset_n;
-wire litedramcore_slave_p2_act_n;
-wire [63:0] litedramcore_slave_p2_wrdata;
-wire litedramcore_slave_p2_wrdata_en;
-wire [7:0] litedramcore_slave_p2_wrdata_mask;
-wire litedramcore_slave_p2_rddata_en;
-reg [63:0] litedramcore_slave_p2_rddata = 64'd0;
-reg litedramcore_slave_p2_rddata_valid = 1'd0;
-wire [14:0] litedramcore_slave_p3_address;
-wire [2:0] litedramcore_slave_p3_bank;
-wire litedramcore_slave_p3_cas_n;
-wire litedramcore_slave_p3_cs_n;
-wire litedramcore_slave_p3_ras_n;
-wire litedramcore_slave_p3_we_n;
-wire litedramcore_slave_p3_cke;
-wire litedramcore_slave_p3_odt;
-wire litedramcore_slave_p3_reset_n;
-wire litedramcore_slave_p3_act_n;
-wire [63:0] litedramcore_slave_p3_wrdata;
-wire litedramcore_slave_p3_wrdata_en;
-wire [7:0] litedramcore_slave_p3_wrdata_mask;
-wire litedramcore_slave_p3_rddata_en;
-reg [63:0] litedramcore_slave_p3_rddata = 64'd0;
-reg litedramcore_slave_p3_rddata_valid = 1'd0;
-reg [14:0] litedramcore_master_p0_address = 15'd0;
-reg [2:0] litedramcore_master_p0_bank = 3'd0;
-reg litedramcore_master_p0_cas_n = 1'd1;
-reg litedramcore_master_p0_cs_n = 1'd1;
-reg litedramcore_master_p0_ras_n = 1'd1;
-reg litedramcore_master_p0_we_n = 1'd1;
-reg litedramcore_master_p0_cke = 1'd0;
-reg litedramcore_master_p0_odt = 1'd0;
-reg litedramcore_master_p0_reset_n = 1'd0;
-reg litedramcore_master_p0_act_n = 1'd1;
-reg [63:0] litedramcore_master_p0_wrdata = 64'd0;
-reg litedramcore_master_p0_wrdata_en = 1'd0;
-reg [7:0] litedramcore_master_p0_wrdata_mask = 8'd0;
-reg litedramcore_master_p0_rddata_en = 1'd0;
-wire [63:0] litedramcore_master_p0_rddata;
-wire litedramcore_master_p0_rddata_valid;
-reg [14:0] litedramcore_master_p1_address = 15'd0;
-reg [2:0] litedramcore_master_p1_bank = 3'd0;
-reg litedramcore_master_p1_cas_n = 1'd1;
-reg litedramcore_master_p1_cs_n = 1'd1;
-reg litedramcore_master_p1_ras_n = 1'd1;
-reg litedramcore_master_p1_we_n = 1'd1;
-reg litedramcore_master_p1_cke = 1'd0;
-reg litedramcore_master_p1_odt = 1'd0;
-reg litedramcore_master_p1_reset_n = 1'd0;
-reg litedramcore_master_p1_act_n = 1'd1;
-reg [63:0] litedramcore_master_p1_wrdata = 64'd0;
-reg litedramcore_master_p1_wrdata_en = 1'd0;
-reg [7:0] litedramcore_master_p1_wrdata_mask = 8'd0;
-reg litedramcore_master_p1_rddata_en = 1'd0;
-wire [63:0] litedramcore_master_p1_rddata;
-wire litedramcore_master_p1_rddata_valid;
-reg [14:0] litedramcore_master_p2_address = 15'd0;
-reg [2:0] litedramcore_master_p2_bank = 3'd0;
-reg litedramcore_master_p2_cas_n = 1'd1;
-reg litedramcore_master_p2_cs_n = 1'd1;
-reg litedramcore_master_p2_ras_n = 1'd1;
-reg litedramcore_master_p2_we_n = 1'd1;
-reg litedramcore_master_p2_cke = 1'd0;
-reg litedramcore_master_p2_odt = 1'd0;
-reg litedramcore_master_p2_reset_n = 1'd0;
-reg litedramcore_master_p2_act_n = 1'd1;
-reg [63:0] litedramcore_master_p2_wrdata = 64'd0;
-reg litedramcore_master_p2_wrdata_en = 1'd0;
-reg [7:0] litedramcore_master_p2_wrdata_mask = 8'd0;
-reg litedramcore_master_p2_rddata_en = 1'd0;
-wire [63:0] litedramcore_master_p2_rddata;
-wire litedramcore_master_p2_rddata_valid;
-reg [14:0] litedramcore_master_p3_address = 15'd0;
-reg [2:0] litedramcore_master_p3_bank = 3'd0;
-reg litedramcore_master_p3_cas_n = 1'd1;
-reg litedramcore_master_p3_cs_n = 1'd1;
-reg litedramcore_master_p3_ras_n = 1'd1;
-reg litedramcore_master_p3_we_n = 1'd1;
-reg litedramcore_master_p3_cke = 1'd0;
-reg litedramcore_master_p3_odt = 1'd0;
-reg litedramcore_master_p3_reset_n = 1'd0;
-reg litedramcore_master_p3_act_n = 1'd1;
-reg [63:0] litedramcore_master_p3_wrdata = 64'd0;
-reg litedramcore_master_p3_wrdata_en = 1'd0;
-reg [7:0] litedramcore_master_p3_wrdata_mask = 8'd0;
-reg litedramcore_master_p3_rddata_en = 1'd0;
-wire [63:0] litedramcore_master_p3_rddata;
-wire litedramcore_master_p3_rddata_valid;
-wire [14:0] litedramcore_csr_dfi_p0_address;
-wire [2:0] litedramcore_csr_dfi_p0_bank;
-reg litedramcore_csr_dfi_p0_cas_n = 1'd1;
-reg litedramcore_csr_dfi_p0_cs_n = 1'd1;
-reg litedramcore_csr_dfi_p0_ras_n = 1'd1;
-reg litedramcore_csr_dfi_p0_we_n = 1'd1;
-wire litedramcore_csr_dfi_p0_cke;
-wire litedramcore_csr_dfi_p0_odt;
-wire litedramcore_csr_dfi_p0_reset_n;
-reg litedramcore_csr_dfi_p0_act_n = 1'd1;
-wire [63:0] litedramcore_csr_dfi_p0_wrdata;
-wire litedramcore_csr_dfi_p0_wrdata_en;
-wire [7:0] litedramcore_csr_dfi_p0_wrdata_mask;
-wire litedramcore_csr_dfi_p0_rddata_en;
-reg [63:0] litedramcore_csr_dfi_p0_rddata = 64'd0;
-reg litedramcore_csr_dfi_p0_rddata_valid = 1'd0;
-wire [14:0] litedramcore_csr_dfi_p1_address;
-wire [2:0] litedramcore_csr_dfi_p1_bank;
-reg litedramcore_csr_dfi_p1_cas_n = 1'd1;
-reg litedramcore_csr_dfi_p1_cs_n = 1'd1;
-reg litedramcore_csr_dfi_p1_ras_n = 1'd1;
-reg litedramcore_csr_dfi_p1_we_n = 1'd1;
-wire litedramcore_csr_dfi_p1_cke;
-wire litedramcore_csr_dfi_p1_odt;
-wire litedramcore_csr_dfi_p1_reset_n;
-reg litedramcore_csr_dfi_p1_act_n = 1'd1;
-wire [63:0] litedramcore_csr_dfi_p1_wrdata;
-wire litedramcore_csr_dfi_p1_wrdata_en;
-wire [7:0] litedramcore_csr_dfi_p1_wrdata_mask;
-wire litedramcore_csr_dfi_p1_rddata_en;
-reg [63:0] litedramcore_csr_dfi_p1_rddata = 64'd0;
-reg litedramcore_csr_dfi_p1_rddata_valid = 1'd0;
-wire [14:0] litedramcore_csr_dfi_p2_address;
-wire [2:0] litedramcore_csr_dfi_p2_bank;
-reg litedramcore_csr_dfi_p2_cas_n = 1'd1;
-reg litedramcore_csr_dfi_p2_cs_n = 1'd1;
-reg litedramcore_csr_dfi_p2_ras_n = 1'd1;
-reg litedramcore_csr_dfi_p2_we_n = 1'd1;
-wire litedramcore_csr_dfi_p2_cke;
-wire litedramcore_csr_dfi_p2_odt;
-wire litedramcore_csr_dfi_p2_reset_n;
-reg litedramcore_csr_dfi_p2_act_n = 1'd1;
-wire [63:0] litedramcore_csr_dfi_p2_wrdata;
-wire litedramcore_csr_dfi_p2_wrdata_en;
-wire [7:0] litedramcore_csr_dfi_p2_wrdata_mask;
-wire litedramcore_csr_dfi_p2_rddata_en;
-reg [63:0] litedramcore_csr_dfi_p2_rddata = 64'd0;
-reg litedramcore_csr_dfi_p2_rddata_valid = 1'd0;
-wire [14:0] litedramcore_csr_dfi_p3_address;
-wire [2:0] litedramcore_csr_dfi_p3_bank;
-reg litedramcore_csr_dfi_p3_cas_n = 1'd1;
-reg litedramcore_csr_dfi_p3_cs_n = 1'd1;
-reg litedramcore_csr_dfi_p3_ras_n = 1'd1;
-reg litedramcore_csr_dfi_p3_we_n = 1'd1;
-wire litedramcore_csr_dfi_p3_cke;
-wire litedramcore_csr_dfi_p3_odt;
-wire litedramcore_csr_dfi_p3_reset_n;
-reg litedramcore_csr_dfi_p3_act_n = 1'd1;
-wire [63:0] litedramcore_csr_dfi_p3_wrdata;
-wire litedramcore_csr_dfi_p3_wrdata_en;
-wire [7:0] litedramcore_csr_dfi_p3_wrdata_mask;
-wire litedramcore_csr_dfi_p3_rddata_en;
-reg [63:0] litedramcore_csr_dfi_p3_rddata = 64'd0;
-reg litedramcore_csr_dfi_p3_rddata_valid = 1'd0;
-reg [14:0] litedramcore_ext_dfi_p0_address = 15'd0;
-reg [2:0] litedramcore_ext_dfi_p0_bank = 3'd0;
-reg litedramcore_ext_dfi_p0_cas_n = 1'd1;
-reg litedramcore_ext_dfi_p0_cs_n = 1'd1;
-reg litedramcore_ext_dfi_p0_ras_n = 1'd1;
-reg litedramcore_ext_dfi_p0_we_n = 1'd1;
-reg litedramcore_ext_dfi_p0_cke = 1'd0;
-reg litedramcore_ext_dfi_p0_odt = 1'd0;
-reg litedramcore_ext_dfi_p0_reset_n = 1'd0;
-reg litedramcore_ext_dfi_p0_act_n = 1'd1;
-reg [63:0] litedramcore_ext_dfi_p0_wrdata = 64'd0;
-reg litedramcore_ext_dfi_p0_wrdata_en = 1'd0;
-reg [7:0] litedramcore_ext_dfi_p0_wrdata_mask = 8'd0;
-reg litedramcore_ext_dfi_p0_rddata_en = 1'd0;
-reg [63:0] litedramcore_ext_dfi_p0_rddata = 64'd0;
-reg litedramcore_ext_dfi_p0_rddata_valid = 1'd0;
-reg [14:0] litedramcore_ext_dfi_p1_address = 15'd0;
-reg [2:0] litedramcore_ext_dfi_p1_bank = 3'd0;
-reg litedramcore_ext_dfi_p1_cas_n = 1'd1;
-reg litedramcore_ext_dfi_p1_cs_n = 1'd1;
-reg litedramcore_ext_dfi_p1_ras_n = 1'd1;
-reg litedramcore_ext_dfi_p1_we_n = 1'd1;
-reg litedramcore_ext_dfi_p1_cke = 1'd0;
-reg litedramcore_ext_dfi_p1_odt = 1'd0;
-reg litedramcore_ext_dfi_p1_reset_n = 1'd0;
-reg litedramcore_ext_dfi_p1_act_n = 1'd1;
-reg [63:0] litedramcore_ext_dfi_p1_wrdata = 64'd0;
-reg litedramcore_ext_dfi_p1_wrdata_en = 1'd0;
-reg [7:0] litedramcore_ext_dfi_p1_wrdata_mask = 8'd0;
-reg litedramcore_ext_dfi_p1_rddata_en = 1'd0;
-reg [63:0] litedramcore_ext_dfi_p1_rddata = 64'd0;
-reg litedramcore_ext_dfi_p1_rddata_valid = 1'd0;
-reg [14:0] litedramcore_ext_dfi_p2_address = 15'd0;
-reg [2:0] litedramcore_ext_dfi_p2_bank = 3'd0;
-reg litedramcore_ext_dfi_p2_cas_n = 1'd1;
-reg litedramcore_ext_dfi_p2_cs_n = 1'd1;
-reg litedramcore_ext_dfi_p2_ras_n = 1'd1;
-reg litedramcore_ext_dfi_p2_we_n = 1'd1;
-reg litedramcore_ext_dfi_p2_cke = 1'd0;
-reg litedramcore_ext_dfi_p2_odt = 1'd0;
-reg litedramcore_ext_dfi_p2_reset_n = 1'd0;
-reg litedramcore_ext_dfi_p2_act_n = 1'd1;
-reg [63:0] litedramcore_ext_dfi_p2_wrdata = 64'd0;
-reg litedramcore_ext_dfi_p2_wrdata_en = 1'd0;
-reg [7:0] litedramcore_ext_dfi_p2_wrdata_mask = 8'd0;
-reg litedramcore_ext_dfi_p2_rddata_en = 1'd0;
-reg [63:0] litedramcore_ext_dfi_p2_rddata = 64'd0;
-reg litedramcore_ext_dfi_p2_rddata_valid = 1'd0;
-reg [14:0] litedramcore_ext_dfi_p3_address = 15'd0;
-reg [2:0] litedramcore_ext_dfi_p3_bank = 3'd0;
-reg litedramcore_ext_dfi_p3_cas_n = 1'd1;
-reg litedramcore_ext_dfi_p3_cs_n = 1'd1;
-reg litedramcore_ext_dfi_p3_ras_n = 1'd1;
-reg litedramcore_ext_dfi_p3_we_n = 1'd1;
-reg litedramcore_ext_dfi_p3_cke = 1'd0;
-reg litedramcore_ext_dfi_p3_odt = 1'd0;
-reg litedramcore_ext_dfi_p3_reset_n = 1'd0;
-reg litedramcore_ext_dfi_p3_act_n = 1'd1;
-reg [63:0] litedramcore_ext_dfi_p3_wrdata = 64'd0;
-reg litedramcore_ext_dfi_p3_wrdata_en = 1'd0;
-reg [7:0] litedramcore_ext_dfi_p3_wrdata_mask = 8'd0;
-reg litedramcore_ext_dfi_p3_rddata_en = 1'd0;
-reg [63:0] litedramcore_ext_dfi_p3_rddata = 64'd0;
-reg litedramcore_ext_dfi_p3_rddata_valid = 1'd0;
-reg litedramcore_ext_dfi_sel = 1'd0;
-wire litedramcore_sel;
-wire litedramcore_cke;
-wire litedramcore_odt;
-wire litedramcore_reset_n;
-reg [3:0] litedramcore_storage = 4'd1;
-reg litedramcore_re = 1'd0;
-wire litedramcore_phaseinjector0_csrfield_cs;
-wire litedramcore_phaseinjector0_csrfield_we;
-wire litedramcore_phaseinjector0_csrfield_cas;
-wire litedramcore_phaseinjector0_csrfield_ras;
-wire litedramcore_phaseinjector0_csrfield_wren;
-wire litedramcore_phaseinjector0_csrfield_rden;
-reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0;
-reg litedramcore_phaseinjector0_command_re = 1'd0;
-reg litedramcore_phaseinjector0_command_issue_re = 1'd0;
-wire litedramcore_phaseinjector0_command_issue_r;
-reg litedramcore_phaseinjector0_command_issue_we = 1'd0;
-reg litedramcore_phaseinjector0_command_issue_w = 1'd0;
-reg [14:0] litedramcore_phaseinjector0_address_storage = 15'd0;
-reg litedramcore_phaseinjector0_address_re = 1'd0;
-reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0;
-reg litedramcore_phaseinjector0_baddress_re = 1'd0;
-reg [63:0] litedramcore_phaseinjector0_wrdata_storage = 64'd0;
-reg litedramcore_phaseinjector0_wrdata_re = 1'd0;
-reg [63:0] litedramcore_phaseinjector0_rddata_status = 64'd0;
-wire litedramcore_phaseinjector0_rddata_we;
-reg litedramcore_phaseinjector0_rddata_re = 1'd0;
-wire litedramcore_phaseinjector1_csrfield_cs;
-wire litedramcore_phaseinjector1_csrfield_we;
-wire litedramcore_phaseinjector1_csrfield_cas;
-wire litedramcore_phaseinjector1_csrfield_ras;
-wire litedramcore_phaseinjector1_csrfield_wren;
-wire litedramcore_phaseinjector1_csrfield_rden;
-reg [5:0] litedramcore_phaseinjector1_command_storage = 6'd0;
-reg litedramcore_phaseinjector1_command_re = 1'd0;
-reg litedramcore_phaseinjector1_command_issue_re = 1'd0;
-wire litedramcore_phaseinjector1_command_issue_r;
-reg litedramcore_phaseinjector1_command_issue_we = 1'd0;
-reg litedramcore_phaseinjector1_command_issue_w = 1'd0;
-reg [14:0] litedramcore_phaseinjector1_address_storage = 15'd0;
-reg litedramcore_phaseinjector1_address_re = 1'd0;
-reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0;
-reg litedramcore_phaseinjector1_baddress_re = 1'd0;
-reg [63:0] litedramcore_phaseinjector1_wrdata_storage = 64'd0;
-reg litedramcore_phaseinjector1_wrdata_re = 1'd0;
-reg [63:0] litedramcore_phaseinjector1_rddata_status = 64'd0;
-wire litedramcore_phaseinjector1_rddata_we;
-reg litedramcore_phaseinjector1_rddata_re = 1'd0;
-wire litedramcore_phaseinjector2_csrfield_cs;
-wire litedramcore_phaseinjector2_csrfield_we;
-wire litedramcore_phaseinjector2_csrfield_cas;
-wire litedramcore_phaseinjector2_csrfield_ras;
-wire litedramcore_phaseinjector2_csrfield_wren;
-wire litedramcore_phaseinjector2_csrfield_rden;
-reg [5:0] litedramcore_phaseinjector2_command_storage = 6'd0;
-reg litedramcore_phaseinjector2_command_re = 1'd0;
-reg litedramcore_phaseinjector2_command_issue_re = 1'd0;
-wire litedramcore_phaseinjector2_command_issue_r;
-reg litedramcore_phaseinjector2_command_issue_we = 1'd0;
-reg litedramcore_phaseinjector2_command_issue_w = 1'd0;
-reg [14:0] litedramcore_phaseinjector2_address_storage = 15'd0;
-reg litedramcore_phaseinjector2_address_re = 1'd0;
-reg [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0;
-reg litedramcore_phaseinjector2_baddress_re = 1'd0;
-reg [63:0] litedramcore_phaseinjector2_wrdata_storage = 64'd0;
-reg litedramcore_phaseinjector2_wrdata_re = 1'd0;
-reg [63:0] litedramcore_phaseinjector2_rddata_status = 64'd0;
-wire litedramcore_phaseinjector2_rddata_we;
-reg litedramcore_phaseinjector2_rddata_re = 1'd0;
-wire litedramcore_phaseinjector3_csrfield_cs;
-wire litedramcore_phaseinjector3_csrfield_we;
-wire litedramcore_phaseinjector3_csrfield_cas;
-wire litedramcore_phaseinjector3_csrfield_ras;
-wire litedramcore_phaseinjector3_csrfield_wren;
-wire litedramcore_phaseinjector3_csrfield_rden;
-reg [5:0] litedramcore_phaseinjector3_command_storage = 6'd0;
-reg litedramcore_phaseinjector3_command_re = 1'd0;
-reg litedramcore_phaseinjector3_command_issue_re = 1'd0;
-wire litedramcore_phaseinjector3_command_issue_r;
-reg litedramcore_phaseinjector3_command_issue_we = 1'd0;
-reg litedramcore_phaseinjector3_command_issue_w = 1'd0;
-reg [14:0] litedramcore_phaseinjector3_address_storage = 15'd0;
-reg litedramcore_phaseinjector3_address_re = 1'd0;
-reg [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0;
-reg litedramcore_phaseinjector3_baddress_re = 1'd0;
-reg [63:0] litedramcore_phaseinjector3_wrdata_storage = 64'd0;
-reg litedramcore_phaseinjector3_wrdata_re = 1'd0;
-reg [63:0] litedramcore_phaseinjector3_rddata_status = 64'd0;
-wire litedramcore_phaseinjector3_rddata_we;
-reg litedramcore_phaseinjector3_rddata_re = 1'd0;
-wire litedramcore_interface_bank0_valid;
-wire litedramcore_interface_bank0_ready;
-wire litedramcore_interface_bank0_we;
-wire [21:0] litedramcore_interface_bank0_addr;
-wire litedramcore_interface_bank0_lock;
-wire litedramcore_interface_bank0_wdata_ready;
-wire litedramcore_interface_bank0_rdata_valid;
-wire litedramcore_interface_bank1_valid;
-wire litedramcore_interface_bank1_ready;
-wire litedramcore_interface_bank1_we;
-wire [21:0] litedramcore_interface_bank1_addr;
-wire litedramcore_interface_bank1_lock;
-wire litedramcore_interface_bank1_wdata_ready;
-wire litedramcore_interface_bank1_rdata_valid;
-wire litedramcore_interface_bank2_valid;
-wire litedramcore_interface_bank2_ready;
-wire litedramcore_interface_bank2_we;
-wire [21:0] litedramcore_interface_bank2_addr;
-wire litedramcore_interface_bank2_lock;
-wire litedramcore_interface_bank2_wdata_ready;
-wire litedramcore_interface_bank2_rdata_valid;
-wire litedramcore_interface_bank3_valid;
-wire litedramcore_interface_bank3_ready;
-wire litedramcore_interface_bank3_we;
-wire [21:0] litedramcore_interface_bank3_addr;
-wire litedramcore_interface_bank3_lock;
-wire litedramcore_interface_bank3_wdata_ready;
-wire litedramcore_interface_bank3_rdata_valid;
-wire litedramcore_interface_bank4_valid;
-wire litedramcore_interface_bank4_ready;
-wire litedramcore_interface_bank4_we;
-wire [21:0] litedramcore_interface_bank4_addr;
-wire litedramcore_interface_bank4_lock;
-wire litedramcore_interface_bank4_wdata_ready;
-wire litedramcore_interface_bank4_rdata_valid;
-wire litedramcore_interface_bank5_valid;
-wire litedramcore_interface_bank5_ready;
-wire litedramcore_interface_bank5_we;
-wire [21:0] litedramcore_interface_bank5_addr;
-wire litedramcore_interface_bank5_lock;
-wire litedramcore_interface_bank5_wdata_ready;
-wire litedramcore_interface_bank5_rdata_valid;
-wire litedramcore_interface_bank6_valid;
-wire litedramcore_interface_bank6_ready;
-wire litedramcore_interface_bank6_we;
-wire [21:0] litedramcore_interface_bank6_addr;
-wire litedramcore_interface_bank6_lock;
-wire litedramcore_interface_bank6_wdata_ready;
-wire litedramcore_interface_bank6_rdata_valid;
-wire litedramcore_interface_bank7_valid;
-wire litedramcore_interface_bank7_ready;
-wire litedramcore_interface_bank7_we;
-wire [21:0] litedramcore_interface_bank7_addr;
-wire litedramcore_interface_bank7_lock;
-wire litedramcore_interface_bank7_wdata_ready;
-wire litedramcore_interface_bank7_rdata_valid;
-reg [255:0] litedramcore_interface_wdata = 256'd0;
-reg [31:0] litedramcore_interface_wdata_we = 32'd0;
-wire [255:0] litedramcore_interface_rdata;
-reg [14:0] litedramcore_dfi_p0_address = 15'd0;
-reg [2:0] litedramcore_dfi_p0_bank = 3'd0;
-reg litedramcore_dfi_p0_cas_n = 1'd1;
-reg litedramcore_dfi_p0_cs_n = 1'd1;
-reg litedramcore_dfi_p0_ras_n = 1'd1;
-reg litedramcore_dfi_p0_we_n = 1'd1;
-wire litedramcore_dfi_p0_cke;
-wire litedramcore_dfi_p0_odt;
-wire litedramcore_dfi_p0_reset_n;
-reg litedramcore_dfi_p0_act_n = 1'd1;
-wire [63:0] litedramcore_dfi_p0_wrdata;
-reg litedramcore_dfi_p0_wrdata_en = 1'd0;
-wire [7:0] litedramcore_dfi_p0_wrdata_mask;
-reg litedramcore_dfi_p0_rddata_en = 1'd0;
-wire [63:0] litedramcore_dfi_p0_rddata;
-wire litedramcore_dfi_p0_rddata_valid;
-reg [14:0] litedramcore_dfi_p1_address = 15'd0;
-reg [2:0] litedramcore_dfi_p1_bank = 3'd0;
-reg litedramcore_dfi_p1_cas_n = 1'd1;
-reg litedramcore_dfi_p1_cs_n = 1'd1;
-reg litedramcore_dfi_p1_ras_n = 1'd1;
-reg litedramcore_dfi_p1_we_n = 1'd1;
-wire litedramcore_dfi_p1_cke;
-wire litedramcore_dfi_p1_odt;
-wire litedramcore_dfi_p1_reset_n;
-reg litedramcore_dfi_p1_act_n = 1'd1;
-wire [63:0] litedramcore_dfi_p1_wrdata;
-reg litedramcore_dfi_p1_wrdata_en = 1'd0;
-wire [7:0] litedramcore_dfi_p1_wrdata_mask;
-reg litedramcore_dfi_p1_rddata_en = 1'd0;
-wire [63:0] litedramcore_dfi_p1_rddata;
-wire litedramcore_dfi_p1_rddata_valid;
-reg [14:0] litedramcore_dfi_p2_address = 15'd0;
-reg [2:0] litedramcore_dfi_p2_bank = 3'd0;
-reg litedramcore_dfi_p2_cas_n = 1'd1;
-reg litedramcore_dfi_p2_cs_n = 1'd1;
-reg litedramcore_dfi_p2_ras_n = 1'd1;
-reg litedramcore_dfi_p2_we_n = 1'd1;
-wire litedramcore_dfi_p2_cke;
-wire litedramcore_dfi_p2_odt;
-wire litedramcore_dfi_p2_reset_n;
-reg litedramcore_dfi_p2_act_n = 1'd1;
-wire [63:0] litedramcore_dfi_p2_wrdata;
-reg litedramcore_dfi_p2_wrdata_en = 1'd0;
-wire [7:0] litedramcore_dfi_p2_wrdata_mask;
-reg litedramcore_dfi_p2_rddata_en = 1'd0;
-wire [63:0] litedramcore_dfi_p2_rddata;
-wire litedramcore_dfi_p2_rddata_valid;
-reg [14:0] litedramcore_dfi_p3_address = 15'd0;
-reg [2:0] litedramcore_dfi_p3_bank = 3'd0;
-reg litedramcore_dfi_p3_cas_n = 1'd1;
-reg litedramcore_dfi_p3_cs_n = 1'd1;
-reg litedramcore_dfi_p3_ras_n = 1'd1;
-reg litedramcore_dfi_p3_we_n = 1'd1;
-wire litedramcore_dfi_p3_cke;
-wire litedramcore_dfi_p3_odt;
-wire litedramcore_dfi_p3_reset_n;
-reg litedramcore_dfi_p3_act_n = 1'd1;
-wire [63:0] litedramcore_dfi_p3_wrdata;
-reg litedramcore_dfi_p3_wrdata_en = 1'd0;
-wire [7:0] litedramcore_dfi_p3_wrdata_mask;
-reg litedramcore_dfi_p3_rddata_en = 1'd0;
-wire [63:0] litedramcore_dfi_p3_rddata;
-wire litedramcore_dfi_p3_rddata_valid;
-reg litedramcore_cmd_valid = 1'd0;
-reg litedramcore_cmd_ready = 1'd0;
-reg litedramcore_cmd_last = 1'd0;
-reg [14:0] litedramcore_cmd_payload_a = 15'd0;
-reg [2:0] litedramcore_cmd_payload_ba = 3'd0;
-reg litedramcore_cmd_payload_cas = 1'd0;
-reg litedramcore_cmd_payload_ras = 1'd0;
-reg litedramcore_cmd_payload_we = 1'd0;
-reg litedramcore_cmd_payload_is_read = 1'd0;
-reg litedramcore_cmd_payload_is_write = 1'd0;
-wire litedramcore_wants_refresh;
-wire litedramcore_wants_zqcs;
-wire litedramcore_timer_wait;
-wire litedramcore_timer_done0;
-wire [9:0] litedramcore_timer_count0;
-wire litedramcore_timer_done1;
-reg [9:0] litedramcore_timer_count1 = 10'd781;
-wire litedramcore_postponer_req_i;
-reg litedramcore_postponer_req_o = 1'd0;
-reg litedramcore_postponer_count = 1'd0;
-reg litedramcore_sequencer_start0 = 1'd0;
-wire litedramcore_sequencer_done0;
-wire litedramcore_sequencer_start1;
-reg litedramcore_sequencer_done1 = 1'd0;
-reg [5:0] litedramcore_sequencer_counter = 6'd0;
-reg litedramcore_sequencer_count = 1'd0;
-wire litedramcore_zqcs_timer_wait;
-wire litedramcore_zqcs_timer_done0;
-wire [26:0] litedramcore_zqcs_timer_count0;
-wire litedramcore_zqcs_timer_done1;
-reg [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999;
-reg litedramcore_zqcs_executer_start = 1'd0;
-reg litedramcore_zqcs_executer_done = 1'd0;
-reg [4:0] litedramcore_zqcs_executer_counter = 5'd0;
-wire litedramcore_bankmachine0_req_valid;
-wire litedramcore_bankmachine0_req_ready;
-wire litedramcore_bankmachine0_req_we;
-wire [21:0] litedramcore_bankmachine0_req_addr;
-wire litedramcore_bankmachine0_req_lock;
-reg litedramcore_bankmachine0_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine0_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine0_refresh_req;
-reg litedramcore_bankmachine0_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine0_cmd_valid = 1'd0;
-reg litedramcore_bankmachine0_cmd_ready = 1'd0;
-reg [14:0] litedramcore_bankmachine0_cmd_payload_a = 15'd0;
-wire [2:0] litedramcore_bankmachine0_cmd_payload_ba;
-reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine0_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine0_auto_precharge = 1'd0;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
-wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
-wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-reg [4:0] litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we;
-wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine0_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine0_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine0_cmd_buffer_sink_first;
-wire litedramcore_bankmachine0_cmd_buffer_sink_last;
-wire litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
-wire [21:0] litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine0_cmd_buffer_source_ready;
-reg litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] litedramcore_bankmachine0_row = 15'd0;
-reg litedramcore_bankmachine0_row_opened = 1'd0;
-wire litedramcore_bankmachine0_row_hit;
-reg litedramcore_bankmachine0_row_open = 1'd0;
-reg litedramcore_bankmachine0_row_close = 1'd0;
-reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine0_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine0_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine0_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine0_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine0_trccon_count = 3'd0;
-wire litedramcore_bankmachine0_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine0_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine0_trascon_count = 3'd0;
-wire litedramcore_bankmachine1_req_valid;
-wire litedramcore_bankmachine1_req_ready;
-wire litedramcore_bankmachine1_req_we;
-wire [21:0] litedramcore_bankmachine1_req_addr;
-wire litedramcore_bankmachine1_req_lock;
-reg litedramcore_bankmachine1_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine1_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine1_refresh_req;
-reg litedramcore_bankmachine1_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine1_cmd_valid = 1'd0;
-reg litedramcore_bankmachine1_cmd_ready = 1'd0;
-reg [14:0] litedramcore_bankmachine1_cmd_payload_a = 15'd0;
-wire [2:0] litedramcore_bankmachine1_cmd_payload_ba;
-reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine1_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine1_auto_precharge = 1'd0;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
-wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
-wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-reg [4:0] litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we;
-wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine1_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine1_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine1_cmd_buffer_sink_first;
-wire litedramcore_bankmachine1_cmd_buffer_sink_last;
-wire litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
-wire [21:0] litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine1_cmd_buffer_source_ready;
-reg litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] litedramcore_bankmachine1_row = 15'd0;
-reg litedramcore_bankmachine1_row_opened = 1'd0;
-wire litedramcore_bankmachine1_row_hit;
-reg litedramcore_bankmachine1_row_open = 1'd0;
-reg litedramcore_bankmachine1_row_close = 1'd0;
-reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine1_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine1_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine1_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine1_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine1_trccon_count = 3'd0;
-wire litedramcore_bankmachine1_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine1_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine1_trascon_count = 3'd0;
-wire litedramcore_bankmachine2_req_valid;
-wire litedramcore_bankmachine2_req_ready;
-wire litedramcore_bankmachine2_req_we;
-wire [21:0] litedramcore_bankmachine2_req_addr;
-wire litedramcore_bankmachine2_req_lock;
-reg litedramcore_bankmachine2_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine2_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine2_refresh_req;
-reg litedramcore_bankmachine2_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine2_cmd_valid = 1'd0;
-reg litedramcore_bankmachine2_cmd_ready = 1'd0;
-reg [14:0] litedramcore_bankmachine2_cmd_payload_a = 15'd0;
-wire [2:0] litedramcore_bankmachine2_cmd_payload_ba;
-reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine2_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine2_auto_precharge = 1'd0;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
-wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
-wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-reg [4:0] litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we;
-wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine2_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine2_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine2_cmd_buffer_sink_first;
-wire litedramcore_bankmachine2_cmd_buffer_sink_last;
-wire litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
-wire [21:0] litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine2_cmd_buffer_source_ready;
-reg litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] litedramcore_bankmachine2_row = 15'd0;
-reg litedramcore_bankmachine2_row_opened = 1'd0;
-wire litedramcore_bankmachine2_row_hit;
-reg litedramcore_bankmachine2_row_open = 1'd0;
-reg litedramcore_bankmachine2_row_close = 1'd0;
-reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine2_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine2_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine2_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine2_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine2_trccon_count = 3'd0;
-wire litedramcore_bankmachine2_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine2_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine2_trascon_count = 3'd0;
-wire litedramcore_bankmachine3_req_valid;
-wire litedramcore_bankmachine3_req_ready;
-wire litedramcore_bankmachine3_req_we;
-wire [21:0] litedramcore_bankmachine3_req_addr;
-wire litedramcore_bankmachine3_req_lock;
-reg litedramcore_bankmachine3_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine3_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine3_refresh_req;
-reg litedramcore_bankmachine3_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine3_cmd_valid = 1'd0;
-reg litedramcore_bankmachine3_cmd_ready = 1'd0;
-reg [14:0] litedramcore_bankmachine3_cmd_payload_a = 15'd0;
-wire [2:0] litedramcore_bankmachine3_cmd_payload_ba;
-reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine3_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine3_auto_precharge = 1'd0;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
-wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
-wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-reg [4:0] litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we;
-wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine3_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine3_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine3_cmd_buffer_sink_first;
-wire litedramcore_bankmachine3_cmd_buffer_sink_last;
-wire litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
-wire [21:0] litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine3_cmd_buffer_source_ready;
-reg litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] litedramcore_bankmachine3_row = 15'd0;
-reg litedramcore_bankmachine3_row_opened = 1'd0;
-wire litedramcore_bankmachine3_row_hit;
-reg litedramcore_bankmachine3_row_open = 1'd0;
-reg litedramcore_bankmachine3_row_close = 1'd0;
-reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine3_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine3_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine3_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine3_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine3_trccon_count = 3'd0;
-wire litedramcore_bankmachine3_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine3_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine3_trascon_count = 3'd0;
-wire litedramcore_bankmachine4_req_valid;
-wire litedramcore_bankmachine4_req_ready;
-wire litedramcore_bankmachine4_req_we;
-wire [21:0] litedramcore_bankmachine4_req_addr;
-wire litedramcore_bankmachine4_req_lock;
-reg litedramcore_bankmachine4_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine4_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine4_refresh_req;
-reg litedramcore_bankmachine4_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine4_cmd_valid = 1'd0;
-reg litedramcore_bankmachine4_cmd_ready = 1'd0;
-reg [14:0] litedramcore_bankmachine4_cmd_payload_a = 15'd0;
-wire [2:0] litedramcore_bankmachine4_cmd_payload_ba;
-reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine4_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine4_auto_precharge = 1'd0;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
-wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
-wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-reg [4:0] litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we;
-wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine4_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine4_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine4_cmd_buffer_sink_first;
-wire litedramcore_bankmachine4_cmd_buffer_sink_last;
-wire litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
-wire [21:0] litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine4_cmd_buffer_source_ready;
-reg litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] litedramcore_bankmachine4_row = 15'd0;
-reg litedramcore_bankmachine4_row_opened = 1'd0;
-wire litedramcore_bankmachine4_row_hit;
-reg litedramcore_bankmachine4_row_open = 1'd0;
-reg litedramcore_bankmachine4_row_close = 1'd0;
-reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine4_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine4_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine4_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine4_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine4_trccon_count = 3'd0;
-wire litedramcore_bankmachine4_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine4_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine4_trascon_count = 3'd0;
-wire litedramcore_bankmachine5_req_valid;
-wire litedramcore_bankmachine5_req_ready;
-wire litedramcore_bankmachine5_req_we;
-wire [21:0] litedramcore_bankmachine5_req_addr;
-wire litedramcore_bankmachine5_req_lock;
-reg litedramcore_bankmachine5_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine5_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine5_refresh_req;
-reg litedramcore_bankmachine5_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine5_cmd_valid = 1'd0;
-reg litedramcore_bankmachine5_cmd_ready = 1'd0;
-reg [14:0] litedramcore_bankmachine5_cmd_payload_a = 15'd0;
-wire [2:0] litedramcore_bankmachine5_cmd_payload_ba;
-reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine5_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine5_auto_precharge = 1'd0;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
-wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
-wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-reg [4:0] litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we;
-wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine5_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine5_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine5_cmd_buffer_sink_first;
-wire litedramcore_bankmachine5_cmd_buffer_sink_last;
-wire litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
-wire [21:0] litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine5_cmd_buffer_source_ready;
-reg litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] litedramcore_bankmachine5_row = 15'd0;
-reg litedramcore_bankmachine5_row_opened = 1'd0;
-wire litedramcore_bankmachine5_row_hit;
-reg litedramcore_bankmachine5_row_open = 1'd0;
-reg litedramcore_bankmachine5_row_close = 1'd0;
-reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine5_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine5_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine5_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine5_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine5_trccon_count = 3'd0;
-wire litedramcore_bankmachine5_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine5_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine5_trascon_count = 3'd0;
-wire litedramcore_bankmachine6_req_valid;
-wire litedramcore_bankmachine6_req_ready;
-wire litedramcore_bankmachine6_req_we;
-wire [21:0] litedramcore_bankmachine6_req_addr;
-wire litedramcore_bankmachine6_req_lock;
-reg litedramcore_bankmachine6_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine6_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine6_refresh_req;
-reg litedramcore_bankmachine6_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine6_cmd_valid = 1'd0;
-reg litedramcore_bankmachine6_cmd_ready = 1'd0;
-reg [14:0] litedramcore_bankmachine6_cmd_payload_a = 15'd0;
-wire [2:0] litedramcore_bankmachine6_cmd_payload_ba;
-reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine6_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine6_auto_precharge = 1'd0;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
-wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
-wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-reg [4:0] litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we;
-wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine6_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine6_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine6_cmd_buffer_sink_first;
-wire litedramcore_bankmachine6_cmd_buffer_sink_last;
-wire litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
-wire [21:0] litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine6_cmd_buffer_source_ready;
-reg litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] litedramcore_bankmachine6_row = 15'd0;
-reg litedramcore_bankmachine6_row_opened = 1'd0;
-wire litedramcore_bankmachine6_row_hit;
-reg litedramcore_bankmachine6_row_open = 1'd0;
-reg litedramcore_bankmachine6_row_close = 1'd0;
-reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine6_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine6_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine6_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine6_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine6_trccon_count = 3'd0;
-wire litedramcore_bankmachine6_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine6_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine6_trascon_count = 3'd0;
-wire litedramcore_bankmachine7_req_valid;
-wire litedramcore_bankmachine7_req_ready;
-wire litedramcore_bankmachine7_req_we;
-wire [21:0] litedramcore_bankmachine7_req_addr;
-wire litedramcore_bankmachine7_req_lock;
-reg litedramcore_bankmachine7_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine7_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine7_refresh_req;
-reg litedramcore_bankmachine7_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine7_cmd_valid = 1'd0;
-reg litedramcore_bankmachine7_cmd_ready = 1'd0;
-reg [14:0] litedramcore_bankmachine7_cmd_payload_a = 15'd0;
-wire [2:0] litedramcore_bankmachine7_cmd_payload_ba;
-reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine7_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine7_auto_precharge = 1'd0;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
-wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
-wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-reg [4:0] litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we;
-wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine7_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine7_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine7_cmd_buffer_sink_first;
-wire litedramcore_bankmachine7_cmd_buffer_sink_last;
-wire litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
-wire [21:0] litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine7_cmd_buffer_source_ready;
-reg litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] litedramcore_bankmachine7_row = 15'd0;
-reg litedramcore_bankmachine7_row_opened = 1'd0;
-wire litedramcore_bankmachine7_row_hit;
-reg litedramcore_bankmachine7_row_open = 1'd0;
-reg litedramcore_bankmachine7_row_close = 1'd0;
-reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine7_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine7_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine7_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine7_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine7_trccon_count = 3'd0;
-wire litedramcore_bankmachine7_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine7_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine7_trascon_count = 3'd0;
-wire litedramcore_ras_allowed;
-wire litedramcore_cas_allowed;
-wire [1:0] litedramcore_rdcmdphase;
-wire [1:0] litedramcore_wrcmdphase;
-reg litedramcore_choose_cmd_want_reads = 1'd0;
-reg litedramcore_choose_cmd_want_writes = 1'd0;
-reg litedramcore_choose_cmd_want_cmds = 1'd0;
-reg litedramcore_choose_cmd_want_activates = 1'd0;
-wire litedramcore_choose_cmd_cmd_valid;
-reg litedramcore_choose_cmd_cmd_ready = 1'd0;
-wire [14:0] litedramcore_choose_cmd_cmd_payload_a;
-wire [2:0] litedramcore_choose_cmd_cmd_payload_ba;
-reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
-reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
-reg litedramcore_choose_cmd_cmd_payload_we = 1'd0;
-wire litedramcore_choose_cmd_cmd_payload_is_cmd;
-wire litedramcore_choose_cmd_cmd_payload_is_read;
-wire litedramcore_choose_cmd_cmd_payload_is_write;
-reg [7:0] litedramcore_choose_cmd_valids = 8'd0;
-wire [7:0] litedramcore_choose_cmd_request;
-reg [2:0] litedramcore_choose_cmd_grant = 3'd0;
-wire litedramcore_choose_cmd_ce;
-reg litedramcore_choose_req_want_reads = 1'd0;
-reg litedramcore_choose_req_want_writes = 1'd0;
-reg litedramcore_choose_req_want_cmds = 1'd0;
-reg litedramcore_choose_req_want_activates = 1'd0;
-wire litedramcore_choose_req_cmd_valid;
-reg litedramcore_choose_req_cmd_ready = 1'd0;
-wire [14:0] litedramcore_choose_req_cmd_payload_a;
-wire [2:0] litedramcore_choose_req_cmd_payload_ba;
-reg litedramcore_choose_req_cmd_payload_cas = 1'd0;
-reg litedramcore_choose_req_cmd_payload_ras = 1'd0;
-reg litedramcore_choose_req_cmd_payload_we = 1'd0;
-wire litedramcore_choose_req_cmd_payload_is_cmd;
-wire litedramcore_choose_req_cmd_payload_is_read;
-wire litedramcore_choose_req_cmd_payload_is_write;
-reg [7:0] litedramcore_choose_req_valids = 8'd0;
-wire [7:0] litedramcore_choose_req_request;
-reg [2:0] litedramcore_choose_req_grant = 3'd0;
-wire litedramcore_choose_req_ce;
-reg [14:0] litedramcore_nop_a = 15'd0;
-reg [2:0] litedramcore_nop_ba = 3'd0;
-reg [1:0] litedramcore_steerer_sel0 = 2'd0;
-reg [1:0] litedramcore_steerer_sel1 = 2'd0;
-reg [1:0] litedramcore_steerer_sel2 = 2'd0;
-reg [1:0] litedramcore_steerer_sel3 = 2'd0;
-reg litedramcore_steerer0 = 1'd1;
-reg litedramcore_steerer1 = 1'd1;
-reg litedramcore_steerer2 = 1'd1;
-reg litedramcore_steerer3 = 1'd1;
-reg litedramcore_steerer4 = 1'd1;
-reg litedramcore_steerer5 = 1'd1;
-reg litedramcore_steerer6 = 1'd1;
-reg litedramcore_steerer7 = 1'd1;
-wire litedramcore_trrdcon_valid;
-(* dont_touch = "true" *) reg litedramcore_trrdcon_ready = 1'd0;
-reg litedramcore_trrdcon_count = 1'd0;
-wire litedramcore_tfawcon_valid;
-(* dont_touch = "true" *) reg litedramcore_tfawcon_ready = 1'd1;
-wire [2:0] litedramcore_tfawcon_count;
-reg [4:0] litedramcore_tfawcon_window = 5'd0;
-wire litedramcore_tccdcon_valid;
-(* dont_touch = "true" *) reg litedramcore_tccdcon_ready = 1'd0;
-reg litedramcore_tccdcon_count = 1'd0;
-wire litedramcore_twtrcon_valid;
-(* dont_touch = "true" *) reg litedramcore_twtrcon_ready = 1'd0;
-reg [2:0] litedramcore_twtrcon_count = 3'd0;
-wire litedramcore_read_available;
-wire litedramcore_write_available;
-reg litedramcore_en0 = 1'd0;
-wire litedramcore_max_time0;
-reg [4:0] litedramcore_time0 = 5'd0;
-reg litedramcore_en1 = 1'd0;
-wire litedramcore_max_time1;
-reg [3:0] litedramcore_time1 = 4'd0;
-wire litedramcore_go_to_refresh;
-reg init_done_storage = 1'd0;
-reg init_done_re = 1'd0;
-reg init_error_storage = 1'd0;
-reg init_error_re = 1'd0;
-wire [29:0] wb_bus_adr;
-wire [31:0] wb_bus_dat_w;
-wire [31:0] wb_bus_dat_r;
-wire [3:0] wb_bus_sel;
-wire wb_bus_cyc;
-wire wb_bus_stb;
-wire wb_bus_ack;
-wire wb_bus_we;
-wire [2:0] wb_bus_cti;
-wire [1:0] wb_bus_bte;
-wire wb_bus_err;
-wire user_enable;
-wire user_port_cmd_valid;
-wire user_port_cmd_ready;
-wire user_port_cmd_payload_we;
-wire [24:0] user_port_cmd_payload_addr;
-wire user_port_wdata_valid;
-wire user_port_wdata_ready;
-wire [255:0] user_port_wdata_payload_data;
-wire [31:0] user_port_wdata_payload_we;
-wire user_port_rdata_valid;
-wire user_port_rdata_ready;
-wire [255:0] user_port_rdata_payload_data;
-reg [13:0] litedramcore_adr = 14'd0;
-reg litedramcore_we = 1'd0;
-reg [31:0] litedramcore_dat_w = 32'd0;
-wire [31:0] litedramcore_dat_r;
-wire [29:0] litedramcore_wishbone_adr;
-wire [31:0] litedramcore_wishbone_dat_w;
-reg [31:0] litedramcore_wishbone_dat_r = 32'd0;
-wire [3:0] litedramcore_wishbone_sel;
-wire litedramcore_wishbone_cyc;
-wire litedramcore_wishbone_stb;
-reg litedramcore_wishbone_ack = 1'd0;
-wire litedramcore_wishbone_we;
-wire [2:0] litedramcore_wishbone_cti;
-wire [1:0] litedramcore_wishbone_bte;
-reg litedramcore_wishbone_err = 1'd0;
-wire [13:0] interface0_bank_bus_adr;
-wire interface0_bank_bus_we;
-wire [31:0] interface0_bank_bus_dat_w;
-reg [31:0] interface0_bank_bus_dat_r = 32'd0;
-reg csrbank0_init_done0_re = 1'd0;
-wire csrbank0_init_done0_r;
-reg csrbank0_init_done0_we = 1'd0;
-wire csrbank0_init_done0_w;
-reg csrbank0_init_error0_re = 1'd0;
-wire csrbank0_init_error0_r;
-reg csrbank0_init_error0_we = 1'd0;
-wire csrbank0_init_error0_w;
-wire csrbank0_sel;
-wire [13:0] interface1_bank_bus_adr;
-wire interface1_bank_bus_we;
-wire [31:0] interface1_bank_bus_dat_w;
-reg [31:0] interface1_bank_bus_dat_r = 32'd0;
-reg csrbank1_rst0_re = 1'd0;
-wire csrbank1_rst0_r;
-reg csrbank1_rst0_we = 1'd0;
-wire csrbank1_rst0_w;
-reg csrbank1_dly_sel0_re = 1'd0;
-wire [3:0] csrbank1_dly_sel0_r;
-reg csrbank1_dly_sel0_we = 1'd0;
-wire [3:0] csrbank1_dly_sel0_w;
-reg csrbank1_half_sys8x_taps0_re = 1'd0;
-wire [4:0] csrbank1_half_sys8x_taps0_r;
-reg csrbank1_half_sys8x_taps0_we = 1'd0;
-wire [4:0] csrbank1_half_sys8x_taps0_w;
-reg csrbank1_wlevel_en0_re = 1'd0;
-wire csrbank1_wlevel_en0_r;
-reg csrbank1_wlevel_en0_we = 1'd0;
-wire csrbank1_wlevel_en0_w;
-reg csrbank1_rdphase0_re = 1'd0;
-wire [1:0] csrbank1_rdphase0_r;
-reg csrbank1_rdphase0_we = 1'd0;
-wire [1:0] csrbank1_rdphase0_w;
-reg csrbank1_wrphase0_re = 1'd0;
-wire [1:0] csrbank1_wrphase0_r;
-reg csrbank1_wrphase0_we = 1'd0;
-wire [1:0] csrbank1_wrphase0_w;
-wire csrbank1_sel;
-wire [13:0] interface2_bank_bus_adr;
-wire interface2_bank_bus_we;
-wire [31:0] interface2_bank_bus_dat_w;
-reg [31:0] interface2_bank_bus_dat_r = 32'd0;
-reg csrbank2_dfii_control0_re = 1'd0;
-wire [3:0] csrbank2_dfii_control0_r;
-reg csrbank2_dfii_control0_we = 1'd0;
-wire [3:0] csrbank2_dfii_control0_w;
-reg csrbank2_dfii_pi0_command0_re = 1'd0;
-wire [5:0] csrbank2_dfii_pi0_command0_r;
-reg csrbank2_dfii_pi0_command0_we = 1'd0;
-wire [5:0] csrbank2_dfii_pi0_command0_w;
-reg csrbank2_dfii_pi0_address0_re = 1'd0;
-wire [14:0] csrbank2_dfii_pi0_address0_r;
-reg csrbank2_dfii_pi0_address0_we = 1'd0;
-wire [14:0] csrbank2_dfii_pi0_address0_w;
-reg csrbank2_dfii_pi0_baddress0_re = 1'd0;
-wire [2:0] csrbank2_dfii_pi0_baddress0_r;
-reg csrbank2_dfii_pi0_baddress0_we = 1'd0;
-wire [2:0] csrbank2_dfii_pi0_baddress0_w;
-reg csrbank2_dfii_pi0_wrdata1_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi0_wrdata1_r;
-reg csrbank2_dfii_pi0_wrdata1_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi0_wrdata1_w;
-reg csrbank2_dfii_pi0_wrdata0_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi0_wrdata0_r;
-reg csrbank2_dfii_pi0_wrdata0_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi0_wrdata0_w;
-reg csrbank2_dfii_pi0_rddata1_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi0_rddata1_r;
-reg csrbank2_dfii_pi0_rddata1_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi0_rddata1_w;
-reg csrbank2_dfii_pi0_rddata0_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi0_rddata0_r;
-reg csrbank2_dfii_pi0_rddata0_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi0_rddata0_w;
-reg csrbank2_dfii_pi1_command0_re = 1'd0;
-wire [5:0] csrbank2_dfii_pi1_command0_r;
-reg csrbank2_dfii_pi1_command0_we = 1'd0;
-wire [5:0] csrbank2_dfii_pi1_command0_w;
-reg csrbank2_dfii_pi1_address0_re = 1'd0;
-wire [14:0] csrbank2_dfii_pi1_address0_r;
-reg csrbank2_dfii_pi1_address0_we = 1'd0;
-wire [14:0] csrbank2_dfii_pi1_address0_w;
-reg csrbank2_dfii_pi1_baddress0_re = 1'd0;
-wire [2:0] csrbank2_dfii_pi1_baddress0_r;
-reg csrbank2_dfii_pi1_baddress0_we = 1'd0;
-wire [2:0] csrbank2_dfii_pi1_baddress0_w;
-reg csrbank2_dfii_pi1_wrdata1_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi1_wrdata1_r;
-reg csrbank2_dfii_pi1_wrdata1_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi1_wrdata1_w;
-reg csrbank2_dfii_pi1_wrdata0_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi1_wrdata0_r;
-reg csrbank2_dfii_pi1_wrdata0_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi1_wrdata0_w;
-reg csrbank2_dfii_pi1_rddata1_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi1_rddata1_r;
-reg csrbank2_dfii_pi1_rddata1_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi1_rddata1_w;
-reg csrbank2_dfii_pi1_rddata0_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi1_rddata0_r;
-reg csrbank2_dfii_pi1_rddata0_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi1_rddata0_w;
-reg csrbank2_dfii_pi2_command0_re = 1'd0;
-wire [5:0] csrbank2_dfii_pi2_command0_r;
-reg csrbank2_dfii_pi2_command0_we = 1'd0;
-wire [5:0] csrbank2_dfii_pi2_command0_w;
-reg csrbank2_dfii_pi2_address0_re = 1'd0;
-wire [14:0] csrbank2_dfii_pi2_address0_r;
-reg csrbank2_dfii_pi2_address0_we = 1'd0;
-wire [14:0] csrbank2_dfii_pi2_address0_w;
-reg csrbank2_dfii_pi2_baddress0_re = 1'd0;
-wire [2:0] csrbank2_dfii_pi2_baddress0_r;
-reg csrbank2_dfii_pi2_baddress0_we = 1'd0;
-wire [2:0] csrbank2_dfii_pi2_baddress0_w;
-reg csrbank2_dfii_pi2_wrdata1_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi2_wrdata1_r;
-reg csrbank2_dfii_pi2_wrdata1_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi2_wrdata1_w;
-reg csrbank2_dfii_pi2_wrdata0_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi2_wrdata0_r;
-reg csrbank2_dfii_pi2_wrdata0_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi2_wrdata0_w;
-reg csrbank2_dfii_pi2_rddata1_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi2_rddata1_r;
-reg csrbank2_dfii_pi2_rddata1_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi2_rddata1_w;
-reg csrbank2_dfii_pi2_rddata0_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi2_rddata0_r;
-reg csrbank2_dfii_pi2_rddata0_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi2_rddata0_w;
-reg csrbank2_dfii_pi3_command0_re = 1'd0;
-wire [5:0] csrbank2_dfii_pi3_command0_r;
-reg csrbank2_dfii_pi3_command0_we = 1'd0;
-wire [5:0] csrbank2_dfii_pi3_command0_w;
-reg csrbank2_dfii_pi3_address0_re = 1'd0;
-wire [14:0] csrbank2_dfii_pi3_address0_r;
-reg csrbank2_dfii_pi3_address0_we = 1'd0;
-wire [14:0] csrbank2_dfii_pi3_address0_w;
-reg csrbank2_dfii_pi3_baddress0_re = 1'd0;
-wire [2:0] csrbank2_dfii_pi3_baddress0_r;
-reg csrbank2_dfii_pi3_baddress0_we = 1'd0;
-wire [2:0] csrbank2_dfii_pi3_baddress0_w;
-reg csrbank2_dfii_pi3_wrdata1_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi3_wrdata1_r;
-reg csrbank2_dfii_pi3_wrdata1_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi3_wrdata1_w;
-reg csrbank2_dfii_pi3_wrdata0_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi3_wrdata0_r;
-reg csrbank2_dfii_pi3_wrdata0_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi3_wrdata0_w;
-reg csrbank2_dfii_pi3_rddata1_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi3_rddata1_r;
-reg csrbank2_dfii_pi3_rddata1_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi3_rddata1_w;
-reg csrbank2_dfii_pi3_rddata0_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi3_rddata0_r;
-reg csrbank2_dfii_pi3_rddata0_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi3_rddata0_w;
-wire csrbank2_sel;
-wire [13:0] csr_interconnect_adr;
-wire csr_interconnect_we;
-wire [31:0] csr_interconnect_dat_w;
-wire [31:0] csr_interconnect_dat_r;
-wire litedramcore_reset0;
-wire litedramcore_reset1;
-wire litedramcore_reset2;
-wire litedramcore_reset3;
-wire litedramcore_reset4;
-wire litedramcore_reset5;
-wire litedramcore_reset6;
-wire litedramcore_reset7;
-wire litedramcore_pll_fb;
-reg [1:0] litedramcore_refresher_state = 2'd0;
-reg [1:0] litedramcore_refresher_next_state = 2'd0;
-reg [3:0] litedramcore_bankmachine0_state = 4'd0;
-reg [3:0] litedramcore_bankmachine0_next_state = 4'd0;
-reg [3:0] litedramcore_bankmachine1_state = 4'd0;
-reg [3:0] litedramcore_bankmachine1_next_state = 4'd0;
-reg [3:0] litedramcore_bankmachine2_state = 4'd0;
-reg [3:0] litedramcore_bankmachine2_next_state = 4'd0;
-reg [3:0] litedramcore_bankmachine3_state = 4'd0;
-reg [3:0] litedramcore_bankmachine3_next_state = 4'd0;
-reg [3:0] litedramcore_bankmachine4_state = 4'd0;
-reg [3:0] litedramcore_bankmachine4_next_state = 4'd0;
-reg [3:0] litedramcore_bankmachine5_state = 4'd0;
-reg [3:0] litedramcore_bankmachine5_next_state = 4'd0;
-reg [3:0] litedramcore_bankmachine6_state = 4'd0;
-reg [3:0] litedramcore_bankmachine6_next_state = 4'd0;
-reg [3:0] litedramcore_bankmachine7_state = 4'd0;
-reg [3:0] litedramcore_bankmachine7_next_state = 4'd0;
-reg [3:0] litedramcore_multiplexer_state = 4'd0;
-reg [3:0] litedramcore_multiplexer_next_state = 4'd0;
-wire litedramcore_roundrobin0_request;
-wire litedramcore_roundrobin0_grant;
-wire litedramcore_roundrobin0_ce;
-wire litedramcore_roundrobin1_request;
-wire litedramcore_roundrobin1_grant;
-wire litedramcore_roundrobin1_ce;
-wire litedramcore_roundrobin2_request;
-wire litedramcore_roundrobin2_grant;
-wire litedramcore_roundrobin2_ce;
-wire litedramcore_roundrobin3_request;
-wire litedramcore_roundrobin3_grant;
-wire litedramcore_roundrobin3_ce;
-wire litedramcore_roundrobin4_request;
-wire litedramcore_roundrobin4_grant;
-wire litedramcore_roundrobin4_ce;
-wire litedramcore_roundrobin5_request;
-wire litedramcore_roundrobin5_grant;
-wire litedramcore_roundrobin5_ce;
-wire litedramcore_roundrobin6_request;
-wire litedramcore_roundrobin6_grant;
-wire litedramcore_roundrobin6_ce;
-wire litedramcore_roundrobin7_request;
-wire litedramcore_roundrobin7_grant;
-wire litedramcore_roundrobin7_ce;
-reg litedramcore_locked0 = 1'd0;
-reg litedramcore_locked1 = 1'd0;
-reg litedramcore_locked2 = 1'd0;
-reg litedramcore_locked3 = 1'd0;
-reg litedramcore_locked4 = 1'd0;
-reg litedramcore_locked5 = 1'd0;
-reg litedramcore_locked6 = 1'd0;
-reg litedramcore_locked7 = 1'd0;
-reg litedramcore_new_master_wdata_ready0 = 1'd0;
-reg litedramcore_new_master_wdata_ready1 = 1'd0;
-reg litedramcore_new_master_rdata_valid0 = 1'd0;
-reg litedramcore_new_master_rdata_valid1 = 1'd0;
-reg litedramcore_new_master_rdata_valid2 = 1'd0;
-reg litedramcore_new_master_rdata_valid3 = 1'd0;
-reg litedramcore_new_master_rdata_valid4 = 1'd0;
-reg litedramcore_new_master_rdata_valid5 = 1'd0;
-reg litedramcore_new_master_rdata_valid6 = 1'd0;
-reg litedramcore_new_master_rdata_valid7 = 1'd0;
-reg litedramcore_new_master_rdata_valid8 = 1'd0;
-reg [1:0] litedramcore_state = 2'd0;
-reg [1:0] litedramcore_next_state = 2'd0;
-reg [31:0] litedramcore_dat_w_next_value0 = 32'd0;
-reg litedramcore_dat_w_next_value_ce0 = 1'd0;
-reg [13:0] litedramcore_adr_next_value1 = 14'd0;
-reg litedramcore_adr_next_value_ce1 = 1'd0;
-reg litedramcore_we_next_value2 = 1'd0;
-reg litedramcore_we_next_value_ce2 = 1'd0;
-reg rhs_array_muxed0 = 1'd0;
-reg [14:0] rhs_array_muxed1 = 15'd0;
-reg [2:0] rhs_array_muxed2 = 3'd0;
-reg rhs_array_muxed3 = 1'd0;
-reg rhs_array_muxed4 = 1'd0;
-reg rhs_array_muxed5 = 1'd0;
-reg t_array_muxed0 = 1'd0;
-reg t_array_muxed1 = 1'd0;
-reg t_array_muxed2 = 1'd0;
-reg rhs_array_muxed6 = 1'd0;
-reg [14:0] rhs_array_muxed7 = 15'd0;
-reg [2:0] rhs_array_muxed8 = 3'd0;
-reg rhs_array_muxed9 = 1'd0;
-reg rhs_array_muxed10 = 1'd0;
-reg rhs_array_muxed11 = 1'd0;
-reg t_array_muxed3 = 1'd0;
-reg t_array_muxed4 = 1'd0;
-reg t_array_muxed5 = 1'd0;
-reg [21:0] rhs_array_muxed12 = 22'd0;
-reg rhs_array_muxed13 = 1'd0;
-reg rhs_array_muxed14 = 1'd0;
-reg [21:0] rhs_array_muxed15 = 22'd0;
-reg rhs_array_muxed16 = 1'd0;
-reg rhs_array_muxed17 = 1'd0;
-reg [21:0] rhs_array_muxed18 = 22'd0;
-reg rhs_array_muxed19 = 1'd0;
-reg rhs_array_muxed20 = 1'd0;
-reg [21:0] rhs_array_muxed21 = 22'd0;
-reg rhs_array_muxed22 = 1'd0;
-reg rhs_array_muxed23 = 1'd0;
-reg [21:0] rhs_array_muxed24 = 22'd0;
-reg rhs_array_muxed25 = 1'd0;
-reg rhs_array_muxed26 = 1'd0;
-reg [21:0] rhs_array_muxed27 = 22'd0;
-reg rhs_array_muxed28 = 1'd0;
-reg rhs_array_muxed29 = 1'd0;
-reg [21:0] rhs_array_muxed30 = 22'd0;
-reg rhs_array_muxed31 = 1'd0;
-reg rhs_array_muxed32 = 1'd0;
-reg [21:0] rhs_array_muxed33 = 22'd0;
-reg rhs_array_muxed34 = 1'd0;
-reg rhs_array_muxed35 = 1'd0;
-reg [2:0] array_muxed0 = 3'd0;
-reg [14:0] array_muxed1 = 15'd0;
-reg array_muxed2 = 1'd0;
-reg array_muxed3 = 1'd0;
-reg array_muxed4 = 1'd0;
-reg array_muxed5 = 1'd0;
-reg array_muxed6 = 1'd0;
-reg [2:0] array_muxed7 = 3'd0;
-reg [14:0] array_muxed8 = 15'd0;
-reg array_muxed9 = 1'd0;
-reg array_muxed10 = 1'd0;
-reg array_muxed11 = 1'd0;
-reg array_muxed12 = 1'd0;
-reg array_muxed13 = 1'd0;
-reg [2:0] array_muxed14 = 3'd0;
-reg [14:0] array_muxed15 = 15'd0;
-reg array_muxed16 = 1'd0;
-reg array_muxed17 = 1'd0;
-reg array_muxed18 = 1'd0;
-reg array_muxed19 = 1'd0;
-reg array_muxed20 = 1'd0;
-reg [2:0] array_muxed21 = 3'd0;
-reg [14:0] array_muxed22 = 15'd0;
-reg array_muxed23 = 1'd0;
-reg array_muxed24 = 1'd0;
-reg array_muxed25 = 1'd0;
-reg array_muxed26 = 1'd0;
-reg array_muxed27 = 1'd0;
-wire xilinxasyncresetsynchronizerimpl0;
-wire xilinxasyncresetsynchronizerimpl0_rst_meta;
-wire xilinxasyncresetsynchronizerimpl1;
-wire xilinxasyncresetsynchronizerimpl1_rst_meta;
-wire xilinxasyncresetsynchronizerimpl2;
-wire xilinxasyncresetsynchronizerimpl2_rst_meta;
-wire xilinxasyncresetsynchronizerimpl2_expr;
-wire xilinxasyncresetsynchronizerimpl3;
-wire xilinxasyncresetsynchronizerimpl3_rst_meta;
-wire xilinxasyncresetsynchronizerimpl3_expr;
+reg rst_1 = 1'd0;
+wire sys_clk;
+wire sys_rst;
+wire sys4x_clk;
+wire sys4x_dqs_clk;
+wire iodelay_clk;
+wire iodelay_rst;
+wire reset;
+reg power_down = 1'd0;
+wire locked;
+wire clkin;
+wire clkout0;
+wire clkout_buf0;
+wire clkout1;
+wire clkout_buf1;
+wire clkout2;
+wire clkout_buf2;
+wire clkout3;
+wire clkout_buf3;
+reg [3:0] reset_counter = 4'd15;
+reg ic_reset = 1'd1;
+reg k7ddrphy_rst_storage = 1'd0;
+reg k7ddrphy_rst_re = 1'd0;
+reg [3:0] k7ddrphy_dly_sel_storage = 4'd0;
+reg k7ddrphy_dly_sel_re = 1'd0;
+reg [4:0] k7ddrphy_half_sys8x_taps_storage = 5'd8;
+reg k7ddrphy_half_sys8x_taps_re = 1'd0;
+reg k7ddrphy_wlevel_en_storage = 1'd0;
+reg k7ddrphy_wlevel_en_re = 1'd0;
+reg k7ddrphy_wlevel_strobe_re = 1'd0;
+wire k7ddrphy_wlevel_strobe_r;
+reg k7ddrphy_wlevel_strobe_we = 1'd0;
+reg k7ddrphy_wlevel_strobe_w = 1'd0;
+reg k7ddrphy_cdly_rst_re = 1'd0;
+wire k7ddrphy_cdly_rst_r;
+reg k7ddrphy_cdly_rst_we = 1'd0;
+reg k7ddrphy_cdly_rst_w = 1'd0;
+reg k7ddrphy_cdly_inc_re = 1'd0;
+wire k7ddrphy_cdly_inc_r;
+reg k7ddrphy_cdly_inc_we = 1'd0;
+reg k7ddrphy_cdly_inc_w = 1'd0;
+reg k7ddrphy_rdly_dq_rst_re = 1'd0;
+wire k7ddrphy_rdly_dq_rst_r;
+reg k7ddrphy_rdly_dq_rst_we = 1'd0;
+reg k7ddrphy_rdly_dq_rst_w = 1'd0;
+reg k7ddrphy_rdly_dq_inc_re = 1'd0;
+wire k7ddrphy_rdly_dq_inc_r;
+reg k7ddrphy_rdly_dq_inc_we = 1'd0;
+reg k7ddrphy_rdly_dq_inc_w = 1'd0;
+reg k7ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
+wire k7ddrphy_rdly_dq_bitslip_rst_r;
+reg k7ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
+reg k7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
+reg k7ddrphy_rdly_dq_bitslip_re = 1'd0;
+wire k7ddrphy_rdly_dq_bitslip_r;
+reg k7ddrphy_rdly_dq_bitslip_we = 1'd0;
+reg k7ddrphy_rdly_dq_bitslip_w = 1'd0;
+reg k7ddrphy_wdly_dq_rst_re = 1'd0;
+wire k7ddrphy_wdly_dq_rst_r;
+reg k7ddrphy_wdly_dq_rst_we = 1'd0;
+reg k7ddrphy_wdly_dq_rst_w = 1'd0;
+reg k7ddrphy_wdly_dq_inc_re = 1'd0;
+wire k7ddrphy_wdly_dq_inc_r;
+reg k7ddrphy_wdly_dq_inc_we = 1'd0;
+reg k7ddrphy_wdly_dq_inc_w = 1'd0;
+reg k7ddrphy_wdly_dqs_rst_re = 1'd0;
+wire k7ddrphy_wdly_dqs_rst_r;
+reg k7ddrphy_wdly_dqs_rst_we = 1'd0;
+reg k7ddrphy_wdly_dqs_rst_w = 1'd0;
+reg k7ddrphy_wdly_dqs_inc_re = 1'd0;
+wire k7ddrphy_wdly_dqs_inc_r;
+reg k7ddrphy_wdly_dqs_inc_we = 1'd0;
+reg k7ddrphy_wdly_dqs_inc_w = 1'd0;
+reg k7ddrphy_wdly_dq_bitslip_rst_re = 1'd0;
+wire k7ddrphy_wdly_dq_bitslip_rst_r;
+reg k7ddrphy_wdly_dq_bitslip_rst_we = 1'd0;
+reg k7ddrphy_wdly_dq_bitslip_rst_w = 1'd0;
+reg k7ddrphy_wdly_dq_bitslip_re = 1'd0;
+wire k7ddrphy_wdly_dq_bitslip_r;
+reg k7ddrphy_wdly_dq_bitslip_we = 1'd0;
+reg k7ddrphy_wdly_dq_bitslip_w = 1'd0;
+reg [1:0] k7ddrphy_rdphase_storage = 2'd1;
+reg k7ddrphy_rdphase_re = 1'd0;
+reg [1:0] k7ddrphy_wrphase_storage = 2'd2;
+reg k7ddrphy_wrphase_re = 1'd0;
+wire [14:0] k7ddrphy_dfi_p0_address;
+wire [2:0] k7ddrphy_dfi_p0_bank;
+wire k7ddrphy_dfi_p0_cas_n;
+wire k7ddrphy_dfi_p0_cs_n;
+wire k7ddrphy_dfi_p0_ras_n;
+wire k7ddrphy_dfi_p0_we_n;
+wire k7ddrphy_dfi_p0_cke;
+wire k7ddrphy_dfi_p0_odt;
+wire k7ddrphy_dfi_p0_reset_n;
+wire k7ddrphy_dfi_p0_act_n;
+wire [63:0] k7ddrphy_dfi_p0_wrdata;
+wire k7ddrphy_dfi_p0_wrdata_en;
+wire [7:0] k7ddrphy_dfi_p0_wrdata_mask;
+wire k7ddrphy_dfi_p0_rddata_en;
+reg [63:0] k7ddrphy_dfi_p0_rddata = 64'd0;
+wire k7ddrphy_dfi_p0_rddata_valid;
+wire [14:0] k7ddrphy_dfi_p1_address;
+wire [2:0] k7ddrphy_dfi_p1_bank;
+wire k7ddrphy_dfi_p1_cas_n;
+wire k7ddrphy_dfi_p1_cs_n;
+wire k7ddrphy_dfi_p1_ras_n;
+wire k7ddrphy_dfi_p1_we_n;
+wire k7ddrphy_dfi_p1_cke;
+wire k7ddrphy_dfi_p1_odt;
+wire k7ddrphy_dfi_p1_reset_n;
+wire k7ddrphy_dfi_p1_act_n;
+wire [63:0] k7ddrphy_dfi_p1_wrdata;
+wire k7ddrphy_dfi_p1_wrdata_en;
+wire [7:0] k7ddrphy_dfi_p1_wrdata_mask;
+wire k7ddrphy_dfi_p1_rddata_en;
+reg [63:0] k7ddrphy_dfi_p1_rddata = 64'd0;
+wire k7ddrphy_dfi_p1_rddata_valid;
+wire [14:0] k7ddrphy_dfi_p2_address;
+wire [2:0] k7ddrphy_dfi_p2_bank;
+wire k7ddrphy_dfi_p2_cas_n;
+wire k7ddrphy_dfi_p2_cs_n;
+wire k7ddrphy_dfi_p2_ras_n;
+wire k7ddrphy_dfi_p2_we_n;
+wire k7ddrphy_dfi_p2_cke;
+wire k7ddrphy_dfi_p2_odt;
+wire k7ddrphy_dfi_p2_reset_n;
+wire k7ddrphy_dfi_p2_act_n;
+wire [63:0] k7ddrphy_dfi_p2_wrdata;
+wire k7ddrphy_dfi_p2_wrdata_en;
+wire [7:0] k7ddrphy_dfi_p2_wrdata_mask;
+wire k7ddrphy_dfi_p2_rddata_en;
+reg [63:0] k7ddrphy_dfi_p2_rddata = 64'd0;
+wire k7ddrphy_dfi_p2_rddata_valid;
+wire [14:0] k7ddrphy_dfi_p3_address;
+wire [2:0] k7ddrphy_dfi_p3_bank;
+wire k7ddrphy_dfi_p3_cas_n;
+wire k7ddrphy_dfi_p3_cs_n;
+wire k7ddrphy_dfi_p3_ras_n;
+wire k7ddrphy_dfi_p3_we_n;
+wire k7ddrphy_dfi_p3_cke;
+wire k7ddrphy_dfi_p3_odt;
+wire k7ddrphy_dfi_p3_reset_n;
+wire k7ddrphy_dfi_p3_act_n;
+wire [63:0] k7ddrphy_dfi_p3_wrdata;
+wire k7ddrphy_dfi_p3_wrdata_en;
+wire [7:0] k7ddrphy_dfi_p3_wrdata_mask;
+wire k7ddrphy_dfi_p3_rddata_en;
+reg [63:0] k7ddrphy_dfi_p3_rddata = 64'd0;
+wire k7ddrphy_dfi_p3_rddata_valid;
+wire k7ddrphy_sd_clk_se_nodelay;
+wire k7ddrphy_sd_clk_se_delayed;
+wire [2:0] k7ddrphy_pads_ba;
+wire k7ddrphy_oq0;
+wire k7ddrphy_oq1;
+wire k7ddrphy_oq2;
+wire k7ddrphy_oq3;
+wire k7ddrphy_oq4;
+wire k7ddrphy_oq5;
+wire k7ddrphy_oq6;
+wire k7ddrphy_oq7;
+wire k7ddrphy_oq8;
+wire k7ddrphy_oq9;
+wire k7ddrphy_oq10;
+wire k7ddrphy_oq11;
+wire k7ddrphy_oq12;
+wire k7ddrphy_oq13;
+wire k7ddrphy_oq14;
+wire k7ddrphy_oq15;
+wire k7ddrphy_oq16;
+wire k7ddrphy_oq17;
+wire k7ddrphy_oq18;
+wire k7ddrphy_oq19;
+wire k7ddrphy_oq20;
+wire k7ddrphy_oq21;
+wire k7ddrphy_oq22;
+wire k7ddrphy_oq23;
+wire k7ddrphy_oq24;
+reg k7ddrphy_dqs_oe = 1'd0;
+wire k7ddrphy_dqs_preamble;
+wire k7ddrphy_dqs_postamble;
+wire k7ddrphy_dqs_oe_delay_tappeddelayline;
+reg k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
+reg k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
+reg k7ddrphy_dqspattern0 = 1'd0;
+reg k7ddrphy_dqspattern1 = 1'd0;
+reg [7:0] k7ddrphy_dqspattern_o = 8'd0;
+wire k7ddrphy_dqs_o_no_delay0;
+wire k7ddrphy_dqs_o_delayed0;
+wire k7ddrphy_dqs_t0;
+reg [7:0] k7ddrphy_bitslip00 = 8'd0;
+reg [2:0] k7ddrphy_bitslip0_value0 = 3'd7;
+reg [15:0] k7ddrphy_bitslip0_r0 = 16'd0;
+wire k7ddrphy0;
+wire k7ddrphy_dqs_o_no_delay1;
+wire k7ddrphy_dqs_o_delayed1;
+wire k7ddrphy_dqs_t1;
+reg [7:0] k7ddrphy_bitslip10 = 8'd0;
+reg [2:0] k7ddrphy_bitslip1_value0 = 3'd7;
+reg [15:0] k7ddrphy_bitslip1_r0 = 16'd0;
+wire k7ddrphy1;
+wire k7ddrphy_dqs_o_no_delay2;
+wire k7ddrphy_dqs_o_delayed2;
+wire k7ddrphy_dqs_t2;
+reg [7:0] k7ddrphy_bitslip20 = 8'd0;
+reg [2:0] k7ddrphy_bitslip2_value0 = 3'd7;
+reg [15:0] k7ddrphy_bitslip2_r0 = 16'd0;
+wire k7ddrphy2;
+wire k7ddrphy_dqs_o_no_delay3;
+wire k7ddrphy_dqs_o_delayed3;
+wire k7ddrphy_dqs_t3;
+reg [7:0] k7ddrphy_bitslip30 = 8'd0;
+reg [2:0] k7ddrphy_bitslip3_value0 = 3'd7;
+reg [15:0] k7ddrphy_bitslip3_r0 = 16'd0;
+wire k7ddrphy3;
+wire k7ddrphy_dm_o_nodelay0;
+reg [7:0] k7ddrphy_bitslip01 = 8'd0;
+reg [2:0] k7ddrphy_bitslip0_value1 = 3'd7;
+reg [15:0] k7ddrphy_bitslip0_r1 = 16'd0;
+wire k7ddrphy_dm_o_nodelay1;
+reg [7:0] k7ddrphy_bitslip11 = 8'd0;
+reg [2:0] k7ddrphy_bitslip1_value1 = 3'd7;
+reg [15:0] k7ddrphy_bitslip1_r1 = 16'd0;
+wire k7ddrphy_dm_o_nodelay2;
+reg [7:0] k7ddrphy_bitslip21 = 8'd0;
+reg [2:0] k7ddrphy_bitslip2_value1 = 3'd7;
+reg [15:0] k7ddrphy_bitslip2_r1 = 16'd0;
+wire k7ddrphy_dm_o_nodelay3;
+reg [7:0] k7ddrphy_bitslip31 = 8'd0;
+reg [2:0] k7ddrphy_bitslip3_value1 = 3'd7;
+reg [15:0] k7ddrphy_bitslip3_r1 = 16'd0;
+wire k7ddrphy_dq_oe;
+wire k7ddrphy_dq_oe_delay_tappeddelayline;
+reg k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
+reg k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
+wire k7ddrphy_dq_o_nodelay0;
+wire k7ddrphy_dq_o_delayed0;
+wire k7ddrphy_dq_i_nodelay0;
+wire k7ddrphy_dq_i_delayed0;
+wire k7ddrphy_dq_t0;
+reg [7:0] k7ddrphy_bitslip02 = 8'd0;
+reg [2:0] k7ddrphy_bitslip0_value2 = 3'd7;
+reg [15:0] k7ddrphy_bitslip0_r2 = 16'd0;
+wire [7:0] k7ddrphy_bitslip03;
+reg [7:0] k7ddrphy_bitslip04 = 8'd0;
+reg [2:0] k7ddrphy_bitslip0_value3 = 3'd7;
+reg [15:0] k7ddrphy_bitslip0_r3 = 16'd0;
+wire k7ddrphy_dq_o_nodelay1;
+wire k7ddrphy_dq_o_delayed1;
+wire k7ddrphy_dq_i_nodelay1;
+wire k7ddrphy_dq_i_delayed1;
+wire k7ddrphy_dq_t1;
+reg [7:0] k7ddrphy_bitslip12 = 8'd0;
+reg [2:0] k7ddrphy_bitslip1_value2 = 3'd7;
+reg [15:0] k7ddrphy_bitslip1_r2 = 16'd0;
+wire [7:0] k7ddrphy_bitslip13;
+reg [7:0] k7ddrphy_bitslip14 = 8'd0;
+reg [2:0] k7ddrphy_bitslip1_value3 = 3'd7;
+reg [15:0] k7ddrphy_bitslip1_r3 = 16'd0;
+wire k7ddrphy_dq_o_nodelay2;
+wire k7ddrphy_dq_o_delayed2;
+wire k7ddrphy_dq_i_nodelay2;
+wire k7ddrphy_dq_i_delayed2;
+wire k7ddrphy_dq_t2;
+reg [7:0] k7ddrphy_bitslip22 = 8'd0;
+reg [2:0] k7ddrphy_bitslip2_value2 = 3'd7;
+reg [15:0] k7ddrphy_bitslip2_r2 = 16'd0;
+wire [7:0] k7ddrphy_bitslip23;
+reg [7:0] k7ddrphy_bitslip24 = 8'd0;
+reg [2:0] k7ddrphy_bitslip2_value3 = 3'd7;
+reg [15:0] k7ddrphy_bitslip2_r3 = 16'd0;
+wire k7ddrphy_dq_o_nodelay3;
+wire k7ddrphy_dq_o_delayed3;
+wire k7ddrphy_dq_i_nodelay3;
+wire k7ddrphy_dq_i_delayed3;
+wire k7ddrphy_dq_t3;
+reg [7:0] k7ddrphy_bitslip32 = 8'd0;
+reg [2:0] k7ddrphy_bitslip3_value2 = 3'd7;
+reg [15:0] k7ddrphy_bitslip3_r2 = 16'd0;
+wire [7:0] k7ddrphy_bitslip33;
+reg [7:0] k7ddrphy_bitslip34 = 8'd0;
+reg [2:0] k7ddrphy_bitslip3_value3 = 3'd7;
+reg [15:0] k7ddrphy_bitslip3_r3 = 16'd0;
+wire k7ddrphy_dq_o_nodelay4;
+wire k7ddrphy_dq_o_delayed4;
+wire k7ddrphy_dq_i_nodelay4;
+wire k7ddrphy_dq_i_delayed4;
+wire k7ddrphy_dq_t4;
+reg [7:0] k7ddrphy_bitslip40 = 8'd0;
+reg [2:0] k7ddrphy_bitslip4_value0 = 3'd7;
+reg [15:0] k7ddrphy_bitslip4_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip41;
+reg [7:0] k7ddrphy_bitslip42 = 8'd0;
+reg [2:0] k7ddrphy_bitslip4_value1 = 3'd7;
+reg [15:0] k7ddrphy_bitslip4_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay5;
+wire k7ddrphy_dq_o_delayed5;
+wire k7ddrphy_dq_i_nodelay5;
+wire k7ddrphy_dq_i_delayed5;
+wire k7ddrphy_dq_t5;
+reg [7:0] k7ddrphy_bitslip50 = 8'd0;
+reg [2:0] k7ddrphy_bitslip5_value0 = 3'd7;
+reg [15:0] k7ddrphy_bitslip5_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip51;
+reg [7:0] k7ddrphy_bitslip52 = 8'd0;
+reg [2:0] k7ddrphy_bitslip5_value1 = 3'd7;
+reg [15:0] k7ddrphy_bitslip5_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay6;
+wire k7ddrphy_dq_o_delayed6;
+wire k7ddrphy_dq_i_nodelay6;
+wire k7ddrphy_dq_i_delayed6;
+wire k7ddrphy_dq_t6;
+reg [7:0] k7ddrphy_bitslip60 = 8'd0;
+reg [2:0] k7ddrphy_bitslip6_value0 = 3'd7;
+reg [15:0] k7ddrphy_bitslip6_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip61;
+reg [7:0] k7ddrphy_bitslip62 = 8'd0;
+reg [2:0] k7ddrphy_bitslip6_value1 = 3'd7;
+reg [15:0] k7ddrphy_bitslip6_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay7;
+wire k7ddrphy_dq_o_delayed7;
+wire k7ddrphy_dq_i_nodelay7;
+wire k7ddrphy_dq_i_delayed7;
+wire k7ddrphy_dq_t7;
+reg [7:0] k7ddrphy_bitslip70 = 8'd0;
+reg [2:0] k7ddrphy_bitslip7_value0 = 3'd7;
+reg [15:0] k7ddrphy_bitslip7_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip71;
+reg [7:0] k7ddrphy_bitslip72 = 8'd0;
+reg [2:0] k7ddrphy_bitslip7_value1 = 3'd7;
+reg [15:0] k7ddrphy_bitslip7_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay8;
+wire k7ddrphy_dq_o_delayed8;
+wire k7ddrphy_dq_i_nodelay8;
+wire k7ddrphy_dq_i_delayed8;
+wire k7ddrphy_dq_t8;
+reg [7:0] k7ddrphy_bitslip80 = 8'd0;
+reg [2:0] k7ddrphy_bitslip8_value0 = 3'd7;
+reg [15:0] k7ddrphy_bitslip8_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip81;
+reg [7:0] k7ddrphy_bitslip82 = 8'd0;
+reg [2:0] k7ddrphy_bitslip8_value1 = 3'd7;
+reg [15:0] k7ddrphy_bitslip8_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay9;
+wire k7ddrphy_dq_o_delayed9;
+wire k7ddrphy_dq_i_nodelay9;
+wire k7ddrphy_dq_i_delayed9;
+wire k7ddrphy_dq_t9;
+reg [7:0] k7ddrphy_bitslip90 = 8'd0;
+reg [2:0] k7ddrphy_bitslip9_value0 = 3'd7;
+reg [15:0] k7ddrphy_bitslip9_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip91;
+reg [7:0] k7ddrphy_bitslip92 = 8'd0;
+reg [2:0] k7ddrphy_bitslip9_value1 = 3'd7;
+reg [15:0] k7ddrphy_bitslip9_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay10;
+wire k7ddrphy_dq_o_delayed10;
+wire k7ddrphy_dq_i_nodelay10;
+wire k7ddrphy_dq_i_delayed10;
+wire k7ddrphy_dq_t10;
+reg [7:0] k7ddrphy_bitslip100 = 8'd0;
+reg [2:0] k7ddrphy_bitslip10_value0 = 3'd7;
+reg [15:0] k7ddrphy_bitslip10_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip101;
+reg [7:0] k7ddrphy_bitslip102 = 8'd0;
+reg [2:0] k7ddrphy_bitslip10_value1 = 3'd7;
+reg [15:0] k7ddrphy_bitslip10_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay11;
+wire k7ddrphy_dq_o_delayed11;
+wire k7ddrphy_dq_i_nodelay11;
+wire k7ddrphy_dq_i_delayed11;
+wire k7ddrphy_dq_t11;
+reg [7:0] k7ddrphy_bitslip110 = 8'd0;
+reg [2:0] k7ddrphy_bitslip11_value0 = 3'd7;
+reg [15:0] k7ddrphy_bitslip11_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip111;
+reg [7:0] k7ddrphy_bitslip112 = 8'd0;
+reg [2:0] k7ddrphy_bitslip11_value1 = 3'd7;
+reg [15:0] k7ddrphy_bitslip11_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay12;
+wire k7ddrphy_dq_o_delayed12;
+wire k7ddrphy_dq_i_nodelay12;
+wire k7ddrphy_dq_i_delayed12;
+wire k7ddrphy_dq_t12;
+reg [7:0] k7ddrphy_bitslip120 = 8'd0;
+reg [2:0] k7ddrphy_bitslip12_value0 = 3'd7;
+reg [15:0] k7ddrphy_bitslip12_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip121;
+reg [7:0] k7ddrphy_bitslip122 = 8'd0;
+reg [2:0] k7ddrphy_bitslip12_value1 = 3'd7;
+reg [15:0] k7ddrphy_bitslip12_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay13;
+wire k7ddrphy_dq_o_delayed13;
+wire k7ddrphy_dq_i_nodelay13;
+wire k7ddrphy_dq_i_delayed13;
+wire k7ddrphy_dq_t13;
+reg [7:0] k7ddrphy_bitslip130 = 8'd0;
+reg [2:0] k7ddrphy_bitslip13_value0 = 3'd7;
+reg [15:0] k7ddrphy_bitslip13_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip131;
+reg [7:0] k7ddrphy_bitslip132 = 8'd0;
+reg [2:0] k7ddrphy_bitslip13_value1 = 3'd7;
+reg [15:0] k7ddrphy_bitslip13_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay14;
+wire k7ddrphy_dq_o_delayed14;
+wire k7ddrphy_dq_i_nodelay14;
+wire k7ddrphy_dq_i_delayed14;
+wire k7ddrphy_dq_t14;
+reg [7:0] k7ddrphy_bitslip140 = 8'd0;
+reg [2:0] k7ddrphy_bitslip14_value0 = 3'd7;
+reg [15:0] k7ddrphy_bitslip14_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip141;
+reg [7:0] k7ddrphy_bitslip142 = 8'd0;
+reg [2:0] k7ddrphy_bitslip14_value1 = 3'd7;
+reg [15:0] k7ddrphy_bitslip14_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay15;
+wire k7ddrphy_dq_o_delayed15;
+wire k7ddrphy_dq_i_nodelay15;
+wire k7ddrphy_dq_i_delayed15;
+wire k7ddrphy_dq_t15;
+reg [7:0] k7ddrphy_bitslip150 = 8'd0;
+reg [2:0] k7ddrphy_bitslip15_value0 = 3'd7;
+reg [15:0] k7ddrphy_bitslip15_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip151;
+reg [7:0] k7ddrphy_bitslip152 = 8'd0;
+reg [2:0] k7ddrphy_bitslip15_value1 = 3'd7;
+reg [15:0] k7ddrphy_bitslip15_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay16;
+wire k7ddrphy_dq_o_delayed16;
+wire k7ddrphy_dq_i_nodelay16;
+wire k7ddrphy_dq_i_delayed16;
+wire k7ddrphy_dq_t16;
+reg [7:0] k7ddrphy_bitslip160 = 8'd0;
+reg [2:0] k7ddrphy_bitslip16_value0 = 3'd7;
+reg [15:0] k7ddrphy_bitslip16_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip161;
+reg [7:0] k7ddrphy_bitslip162 = 8'd0;
+reg [2:0] k7ddrphy_bitslip16_value1 = 3'd7;
+reg [15:0] k7ddrphy_bitslip16_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay17;
+wire k7ddrphy_dq_o_delayed17;
+wire k7ddrphy_dq_i_nodelay17;
+wire k7ddrphy_dq_i_delayed17;
+wire k7ddrphy_dq_t17;
+reg [7:0] k7ddrphy_bitslip170 = 8'd0;
+reg [2:0] k7ddrphy_bitslip17_value0 = 3'd7;
+reg [15:0] k7ddrphy_bitslip17_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip171;
+reg [7:0] k7ddrphy_bitslip172 = 8'd0;
+reg [2:0] k7ddrphy_bitslip17_value1 = 3'd7;
+reg [15:0] k7ddrphy_bitslip17_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay18;
+wire k7ddrphy_dq_o_delayed18;
+wire k7ddrphy_dq_i_nodelay18;
+wire k7ddrphy_dq_i_delayed18;
+wire k7ddrphy_dq_t18;
+reg [7:0] k7ddrphy_bitslip180 = 8'd0;
+reg [2:0] k7ddrphy_bitslip18_value0 = 3'd7;
+reg [15:0] k7ddrphy_bitslip18_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip181;
+reg [7:0] k7ddrphy_bitslip182 = 8'd0;
+reg [2:0] k7ddrphy_bitslip18_value1 = 3'd7;
+reg [15:0] k7ddrphy_bitslip18_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay19;
+wire k7ddrphy_dq_o_delayed19;
+wire k7ddrphy_dq_i_nodelay19;
+wire k7ddrphy_dq_i_delayed19;
+wire k7ddrphy_dq_t19;
+reg [7:0] k7ddrphy_bitslip190 = 8'd0;
+reg [2:0] k7ddrphy_bitslip19_value0 = 3'd7;
+reg [15:0] k7ddrphy_bitslip19_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip191;
+reg [7:0] k7ddrphy_bitslip192 = 8'd0;
+reg [2:0] k7ddrphy_bitslip19_value1 = 3'd7;
+reg [15:0] k7ddrphy_bitslip19_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay20;
+wire k7ddrphy_dq_o_delayed20;
+wire k7ddrphy_dq_i_nodelay20;
+wire k7ddrphy_dq_i_delayed20;
+wire k7ddrphy_dq_t20;
+reg [7:0] k7ddrphy_bitslip200 = 8'd0;
+reg [2:0] k7ddrphy_bitslip20_value0 = 3'd7;
+reg [15:0] k7ddrphy_bitslip20_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip201;
+reg [7:0] k7ddrphy_bitslip202 = 8'd0;
+reg [2:0] k7ddrphy_bitslip20_value1 = 3'd7;
+reg [15:0] k7ddrphy_bitslip20_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay21;
+wire k7ddrphy_dq_o_delayed21;
+wire k7ddrphy_dq_i_nodelay21;
+wire k7ddrphy_dq_i_delayed21;
+wire k7ddrphy_dq_t21;
+reg [7:0] k7ddrphy_bitslip210 = 8'd0;
+reg [2:0] k7ddrphy_bitslip21_value0 = 3'd7;
+reg [15:0] k7ddrphy_bitslip21_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip211;
+reg [7:0] k7ddrphy_bitslip212 = 8'd0;
+reg [2:0] k7ddrphy_bitslip21_value1 = 3'd7;
+reg [15:0] k7ddrphy_bitslip21_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay22;
+wire k7ddrphy_dq_o_delayed22;
+wire k7ddrphy_dq_i_nodelay22;
+wire k7ddrphy_dq_i_delayed22;
+wire k7ddrphy_dq_t22;
+reg [7:0] k7ddrphy_bitslip220 = 8'd0;
+reg [2:0] k7ddrphy_bitslip22_value0 = 3'd7;
+reg [15:0] k7ddrphy_bitslip22_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip221;
+reg [7:0] k7ddrphy_bitslip222 = 8'd0;
+reg [2:0] k7ddrphy_bitslip22_value1 = 3'd7;
+reg [15:0] k7ddrphy_bitslip22_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay23;
+wire k7ddrphy_dq_o_delayed23;
+wire k7ddrphy_dq_i_nodelay23;
+wire k7ddrphy_dq_i_delayed23;
+wire k7ddrphy_dq_t23;
+reg [7:0] k7ddrphy_bitslip230 = 8'd0;
+reg [2:0] k7ddrphy_bitslip23_value0 = 3'd7;
+reg [15:0] k7ddrphy_bitslip23_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip231;
+reg [7:0] k7ddrphy_bitslip232 = 8'd0;
+reg [2:0] k7ddrphy_bitslip23_value1 = 3'd7;
+reg [15:0] k7ddrphy_bitslip23_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay24;
+wire k7ddrphy_dq_o_delayed24;
+wire k7ddrphy_dq_i_nodelay24;
+wire k7ddrphy_dq_i_delayed24;
+wire k7ddrphy_dq_t24;
+reg [7:0] k7ddrphy_bitslip240 = 8'd0;
+reg [2:0] k7ddrphy_bitslip24_value0 = 3'd7;
+reg [15:0] k7ddrphy_bitslip24_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip241;
+reg [7:0] k7ddrphy_bitslip242 = 8'd0;
+reg [2:0] k7ddrphy_bitslip24_value1 = 3'd7;
+reg [15:0] k7ddrphy_bitslip24_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay25;
+wire k7ddrphy_dq_o_delayed25;
+wire k7ddrphy_dq_i_nodelay25;
+wire k7ddrphy_dq_i_delayed25;
+wire k7ddrphy_dq_t25;
+reg [7:0] k7ddrphy_bitslip250 = 8'd0;
+reg [2:0] k7ddrphy_bitslip25_value0 = 3'd7;
+reg [15:0] k7ddrphy_bitslip25_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip251;
+reg [7:0] k7ddrphy_bitslip252 = 8'd0;
+reg [2:0] k7ddrphy_bitslip25_value1 = 3'd7;
+reg [15:0] k7ddrphy_bitslip25_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay26;
+wire k7ddrphy_dq_o_delayed26;
+wire k7ddrphy_dq_i_nodelay26;
+wire k7ddrphy_dq_i_delayed26;
+wire k7ddrphy_dq_t26;
+reg [7:0] k7ddrphy_bitslip260 = 8'd0;
+reg [2:0] k7ddrphy_bitslip26_value0 = 3'd7;
+reg [15:0] k7ddrphy_bitslip26_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip261;
+reg [7:0] k7ddrphy_bitslip262 = 8'd0;
+reg [2:0] k7ddrphy_bitslip26_value1 = 3'd7;
+reg [15:0] k7ddrphy_bitslip26_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay27;
+wire k7ddrphy_dq_o_delayed27;
+wire k7ddrphy_dq_i_nodelay27;
+wire k7ddrphy_dq_i_delayed27;
+wire k7ddrphy_dq_t27;
+reg [7:0] k7ddrphy_bitslip270 = 8'd0;
+reg [2:0] k7ddrphy_bitslip27_value0 = 3'd7;
+reg [15:0] k7ddrphy_bitslip27_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip271;
+reg [7:0] k7ddrphy_bitslip272 = 8'd0;
+reg [2:0] k7ddrphy_bitslip27_value1 = 3'd7;
+reg [15:0] k7ddrphy_bitslip27_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay28;
+wire k7ddrphy_dq_o_delayed28;
+wire k7ddrphy_dq_i_nodelay28;
+wire k7ddrphy_dq_i_delayed28;
+wire k7ddrphy_dq_t28;
+reg [7:0] k7ddrphy_bitslip280 = 8'd0;
+reg [2:0] k7ddrphy_bitslip28_value0 = 3'd7;
+reg [15:0] k7ddrphy_bitslip28_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip281;
+reg [7:0] k7ddrphy_bitslip282 = 8'd0;
+reg [2:0] k7ddrphy_bitslip28_value1 = 3'd7;
+reg [15:0] k7ddrphy_bitslip28_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay29;
+wire k7ddrphy_dq_o_delayed29;
+wire k7ddrphy_dq_i_nodelay29;
+wire k7ddrphy_dq_i_delayed29;
+wire k7ddrphy_dq_t29;
+reg [7:0] k7ddrphy_bitslip290 = 8'd0;
+reg [2:0] k7ddrphy_bitslip29_value0 = 3'd7;
+reg [15:0] k7ddrphy_bitslip29_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip291;
+reg [7:0] k7ddrphy_bitslip292 = 8'd0;
+reg [2:0] k7ddrphy_bitslip29_value1 = 3'd7;
+reg [15:0] k7ddrphy_bitslip29_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay30;
+wire k7ddrphy_dq_o_delayed30;
+wire k7ddrphy_dq_i_nodelay30;
+wire k7ddrphy_dq_i_delayed30;
+wire k7ddrphy_dq_t30;
+reg [7:0] k7ddrphy_bitslip300 = 8'd0;
+reg [2:0] k7ddrphy_bitslip30_value0 = 3'd7;
+reg [15:0] k7ddrphy_bitslip30_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip301;
+reg [7:0] k7ddrphy_bitslip302 = 8'd0;
+reg [2:0] k7ddrphy_bitslip30_value1 = 3'd7;
+reg [15:0] k7ddrphy_bitslip30_r1 = 16'd0;
+wire k7ddrphy_dq_o_nodelay31;
+wire k7ddrphy_dq_o_delayed31;
+wire k7ddrphy_dq_i_nodelay31;
+wire k7ddrphy_dq_i_delayed31;
+wire k7ddrphy_dq_t31;
+reg [7:0] k7ddrphy_bitslip310 = 8'd0;
+reg [2:0] k7ddrphy_bitslip31_value0 = 3'd7;
+reg [15:0] k7ddrphy_bitslip31_r0 = 16'd0;
+wire [7:0] k7ddrphy_bitslip311;
+reg [7:0] k7ddrphy_bitslip312 = 8'd0;
+reg [2:0] k7ddrphy_bitslip31_value1 = 3'd7;
+reg [15:0] k7ddrphy_bitslip31_r1 = 16'd0;
+reg k7ddrphy_rddata_en_tappeddelayline0 = 1'd0;
+reg k7ddrphy_rddata_en_tappeddelayline1 = 1'd0;
+reg k7ddrphy_rddata_en_tappeddelayline2 = 1'd0;
+reg k7ddrphy_rddata_en_tappeddelayline3 = 1'd0;
+reg k7ddrphy_rddata_en_tappeddelayline4 = 1'd0;
+reg k7ddrphy_rddata_en_tappeddelayline5 = 1'd0;
+reg k7ddrphy_rddata_en_tappeddelayline6 = 1'd0;
+reg k7ddrphy_rddata_en_tappeddelayline7 = 1'd0;
+reg k7ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
+reg k7ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
+reg k7ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
+wire [14:0] litedramcore_slave_p0_address;
+wire [2:0] litedramcore_slave_p0_bank;
+wire litedramcore_slave_p0_cas_n;
+wire litedramcore_slave_p0_cs_n;
+wire litedramcore_slave_p0_ras_n;
+wire litedramcore_slave_p0_we_n;
+wire litedramcore_slave_p0_cke;
+wire litedramcore_slave_p0_odt;
+wire litedramcore_slave_p0_reset_n;
+wire litedramcore_slave_p0_act_n;
+wire [63:0] litedramcore_slave_p0_wrdata;
+wire litedramcore_slave_p0_wrdata_en;
+wire [7:0] litedramcore_slave_p0_wrdata_mask;
+wire litedramcore_slave_p0_rddata_en;
+reg [63:0] litedramcore_slave_p0_rddata = 64'd0;
+reg litedramcore_slave_p0_rddata_valid = 1'd0;
+wire [14:0] litedramcore_slave_p1_address;
+wire [2:0] litedramcore_slave_p1_bank;
+wire litedramcore_slave_p1_cas_n;
+wire litedramcore_slave_p1_cs_n;
+wire litedramcore_slave_p1_ras_n;
+wire litedramcore_slave_p1_we_n;
+wire litedramcore_slave_p1_cke;
+wire litedramcore_slave_p1_odt;
+wire litedramcore_slave_p1_reset_n;
+wire litedramcore_slave_p1_act_n;
+wire [63:0] litedramcore_slave_p1_wrdata;
+wire litedramcore_slave_p1_wrdata_en;
+wire [7:0] litedramcore_slave_p1_wrdata_mask;
+wire litedramcore_slave_p1_rddata_en;
+reg [63:0] litedramcore_slave_p1_rddata = 64'd0;
+reg litedramcore_slave_p1_rddata_valid = 1'd0;
+wire [14:0] litedramcore_slave_p2_address;
+wire [2:0] litedramcore_slave_p2_bank;
+wire litedramcore_slave_p2_cas_n;
+wire litedramcore_slave_p2_cs_n;
+wire litedramcore_slave_p2_ras_n;
+wire litedramcore_slave_p2_we_n;
+wire litedramcore_slave_p2_cke;
+wire litedramcore_slave_p2_odt;
+wire litedramcore_slave_p2_reset_n;
+wire litedramcore_slave_p2_act_n;
+wire [63:0] litedramcore_slave_p2_wrdata;
+wire litedramcore_slave_p2_wrdata_en;
+wire [7:0] litedramcore_slave_p2_wrdata_mask;
+wire litedramcore_slave_p2_rddata_en;
+reg [63:0] litedramcore_slave_p2_rddata = 64'd0;
+reg litedramcore_slave_p2_rddata_valid = 1'd0;
+wire [14:0] litedramcore_slave_p3_address;
+wire [2:0] litedramcore_slave_p3_bank;
+wire litedramcore_slave_p3_cas_n;
+wire litedramcore_slave_p3_cs_n;
+wire litedramcore_slave_p3_ras_n;
+wire litedramcore_slave_p3_we_n;
+wire litedramcore_slave_p3_cke;
+wire litedramcore_slave_p3_odt;
+wire litedramcore_slave_p3_reset_n;
+wire litedramcore_slave_p3_act_n;
+wire [63:0] litedramcore_slave_p3_wrdata;
+wire litedramcore_slave_p3_wrdata_en;
+wire [7:0] litedramcore_slave_p3_wrdata_mask;
+wire litedramcore_slave_p3_rddata_en;
+reg [63:0] litedramcore_slave_p3_rddata = 64'd0;
+reg litedramcore_slave_p3_rddata_valid = 1'd0;
+reg [14:0] litedramcore_master_p0_address = 15'd0;
+reg [2:0] litedramcore_master_p0_bank = 3'd0;
+reg litedramcore_master_p0_cas_n = 1'd1;
+reg litedramcore_master_p0_cs_n = 1'd1;
+reg litedramcore_master_p0_ras_n = 1'd1;
+reg litedramcore_master_p0_we_n = 1'd1;
+reg litedramcore_master_p0_cke = 1'd0;
+reg litedramcore_master_p0_odt = 1'd0;
+reg litedramcore_master_p0_reset_n = 1'd0;
+reg litedramcore_master_p0_act_n = 1'd1;
+reg [63:0] litedramcore_master_p0_wrdata = 64'd0;
+reg litedramcore_master_p0_wrdata_en = 1'd0;
+reg [7:0] litedramcore_master_p0_wrdata_mask = 8'd0;
+reg litedramcore_master_p0_rddata_en = 1'd0;
+wire [63:0] litedramcore_master_p0_rddata;
+wire litedramcore_master_p0_rddata_valid;
+reg [14:0] litedramcore_master_p1_address = 15'd0;
+reg [2:0] litedramcore_master_p1_bank = 3'd0;
+reg litedramcore_master_p1_cas_n = 1'd1;
+reg litedramcore_master_p1_cs_n = 1'd1;
+reg litedramcore_master_p1_ras_n = 1'd1;
+reg litedramcore_master_p1_we_n = 1'd1;
+reg litedramcore_master_p1_cke = 1'd0;
+reg litedramcore_master_p1_odt = 1'd0;
+reg litedramcore_master_p1_reset_n = 1'd0;
+reg litedramcore_master_p1_act_n = 1'd1;
+reg [63:0] litedramcore_master_p1_wrdata = 64'd0;
+reg litedramcore_master_p1_wrdata_en = 1'd0;
+reg [7:0] litedramcore_master_p1_wrdata_mask = 8'd0;
+reg litedramcore_master_p1_rddata_en = 1'd0;
+wire [63:0] litedramcore_master_p1_rddata;
+wire litedramcore_master_p1_rddata_valid;
+reg [14:0] litedramcore_master_p2_address = 15'd0;
+reg [2:0] litedramcore_master_p2_bank = 3'd0;
+reg litedramcore_master_p2_cas_n = 1'd1;
+reg litedramcore_master_p2_cs_n = 1'd1;
+reg litedramcore_master_p2_ras_n = 1'd1;
+reg litedramcore_master_p2_we_n = 1'd1;
+reg litedramcore_master_p2_cke = 1'd0;
+reg litedramcore_master_p2_odt = 1'd0;
+reg litedramcore_master_p2_reset_n = 1'd0;
+reg litedramcore_master_p2_act_n = 1'd1;
+reg [63:0] litedramcore_master_p2_wrdata = 64'd0;
+reg litedramcore_master_p2_wrdata_en = 1'd0;
+reg [7:0] litedramcore_master_p2_wrdata_mask = 8'd0;
+reg litedramcore_master_p2_rddata_en = 1'd0;
+wire [63:0] litedramcore_master_p2_rddata;
+wire litedramcore_master_p2_rddata_valid;
+reg [14:0] litedramcore_master_p3_address = 15'd0;
+reg [2:0] litedramcore_master_p3_bank = 3'd0;
+reg litedramcore_master_p3_cas_n = 1'd1;
+reg litedramcore_master_p3_cs_n = 1'd1;
+reg litedramcore_master_p3_ras_n = 1'd1;
+reg litedramcore_master_p3_we_n = 1'd1;
+reg litedramcore_master_p3_cke = 1'd0;
+reg litedramcore_master_p3_odt = 1'd0;
+reg litedramcore_master_p3_reset_n = 1'd0;
+reg litedramcore_master_p3_act_n = 1'd1;
+reg [63:0] litedramcore_master_p3_wrdata = 64'd0;
+reg litedramcore_master_p3_wrdata_en = 1'd0;
+reg [7:0] litedramcore_master_p3_wrdata_mask = 8'd0;
+reg litedramcore_master_p3_rddata_en = 1'd0;
+wire [63:0] litedramcore_master_p3_rddata;
+wire litedramcore_master_p3_rddata_valid;
+wire [14:0] litedramcore_csr_dfi_p0_address;
+wire [2:0] litedramcore_csr_dfi_p0_bank;
+reg litedramcore_csr_dfi_p0_cas_n = 1'd1;
+reg litedramcore_csr_dfi_p0_cs_n = 1'd1;
+reg litedramcore_csr_dfi_p0_ras_n = 1'd1;
+reg litedramcore_csr_dfi_p0_we_n = 1'd1;
+wire litedramcore_csr_dfi_p0_cke;
+wire litedramcore_csr_dfi_p0_odt;
+wire litedramcore_csr_dfi_p0_reset_n;
+reg litedramcore_csr_dfi_p0_act_n = 1'd1;
+wire [63:0] litedramcore_csr_dfi_p0_wrdata;
+wire litedramcore_csr_dfi_p0_wrdata_en;
+wire [7:0] litedramcore_csr_dfi_p0_wrdata_mask;
+wire litedramcore_csr_dfi_p0_rddata_en;
+reg [63:0] litedramcore_csr_dfi_p0_rddata = 64'd0;
+reg litedramcore_csr_dfi_p0_rddata_valid = 1'd0;
+wire [14:0] litedramcore_csr_dfi_p1_address;
+wire [2:0] litedramcore_csr_dfi_p1_bank;
+reg litedramcore_csr_dfi_p1_cas_n = 1'd1;
+reg litedramcore_csr_dfi_p1_cs_n = 1'd1;
+reg litedramcore_csr_dfi_p1_ras_n = 1'd1;
+reg litedramcore_csr_dfi_p1_we_n = 1'd1;
+wire litedramcore_csr_dfi_p1_cke;
+wire litedramcore_csr_dfi_p1_odt;
+wire litedramcore_csr_dfi_p1_reset_n;
+reg litedramcore_csr_dfi_p1_act_n = 1'd1;
+wire [63:0] litedramcore_csr_dfi_p1_wrdata;
+wire litedramcore_csr_dfi_p1_wrdata_en;
+wire [7:0] litedramcore_csr_dfi_p1_wrdata_mask;
+wire litedramcore_csr_dfi_p1_rddata_en;
+reg [63:0] litedramcore_csr_dfi_p1_rddata = 64'd0;
+reg litedramcore_csr_dfi_p1_rddata_valid = 1'd0;
+wire [14:0] litedramcore_csr_dfi_p2_address;
+wire [2:0] litedramcore_csr_dfi_p2_bank;
+reg litedramcore_csr_dfi_p2_cas_n = 1'd1;
+reg litedramcore_csr_dfi_p2_cs_n = 1'd1;
+reg litedramcore_csr_dfi_p2_ras_n = 1'd1;
+reg litedramcore_csr_dfi_p2_we_n = 1'd1;
+wire litedramcore_csr_dfi_p2_cke;
+wire litedramcore_csr_dfi_p2_odt;
+wire litedramcore_csr_dfi_p2_reset_n;
+reg litedramcore_csr_dfi_p2_act_n = 1'd1;
+wire [63:0] litedramcore_csr_dfi_p2_wrdata;
+wire litedramcore_csr_dfi_p2_wrdata_en;
+wire [7:0] litedramcore_csr_dfi_p2_wrdata_mask;
+wire litedramcore_csr_dfi_p2_rddata_en;
+reg [63:0] litedramcore_csr_dfi_p2_rddata = 64'd0;
+reg litedramcore_csr_dfi_p2_rddata_valid = 1'd0;
+wire [14:0] litedramcore_csr_dfi_p3_address;
+wire [2:0] litedramcore_csr_dfi_p3_bank;
+reg litedramcore_csr_dfi_p3_cas_n = 1'd1;
+reg litedramcore_csr_dfi_p3_cs_n = 1'd1;
+reg litedramcore_csr_dfi_p3_ras_n = 1'd1;
+reg litedramcore_csr_dfi_p3_we_n = 1'd1;
+wire litedramcore_csr_dfi_p3_cke;
+wire litedramcore_csr_dfi_p3_odt;
+wire litedramcore_csr_dfi_p3_reset_n;
+reg litedramcore_csr_dfi_p3_act_n = 1'd1;
+wire [63:0] litedramcore_csr_dfi_p3_wrdata;
+wire litedramcore_csr_dfi_p3_wrdata_en;
+wire [7:0] litedramcore_csr_dfi_p3_wrdata_mask;
+wire litedramcore_csr_dfi_p3_rddata_en;
+reg [63:0] litedramcore_csr_dfi_p3_rddata = 64'd0;
+reg litedramcore_csr_dfi_p3_rddata_valid = 1'd0;
+reg [14:0] litedramcore_ext_dfi_p0_address = 15'd0;
+reg [2:0] litedramcore_ext_dfi_p0_bank = 3'd0;
+reg litedramcore_ext_dfi_p0_cas_n = 1'd1;
+reg litedramcore_ext_dfi_p0_cs_n = 1'd1;
+reg litedramcore_ext_dfi_p0_ras_n = 1'd1;
+reg litedramcore_ext_dfi_p0_we_n = 1'd1;
+reg litedramcore_ext_dfi_p0_cke = 1'd0;
+reg litedramcore_ext_dfi_p0_odt = 1'd0;
+reg litedramcore_ext_dfi_p0_reset_n = 1'd0;
+reg litedramcore_ext_dfi_p0_act_n = 1'd1;
+reg [63:0] litedramcore_ext_dfi_p0_wrdata = 64'd0;
+reg litedramcore_ext_dfi_p0_wrdata_en = 1'd0;
+reg [7:0] litedramcore_ext_dfi_p0_wrdata_mask = 8'd0;
+reg litedramcore_ext_dfi_p0_rddata_en = 1'd0;
+reg [63:0] litedramcore_ext_dfi_p0_rddata = 64'd0;
+reg litedramcore_ext_dfi_p0_rddata_valid = 1'd0;
+reg [14:0] litedramcore_ext_dfi_p1_address = 15'd0;
+reg [2:0] litedramcore_ext_dfi_p1_bank = 3'd0;
+reg litedramcore_ext_dfi_p1_cas_n = 1'd1;
+reg litedramcore_ext_dfi_p1_cs_n = 1'd1;
+reg litedramcore_ext_dfi_p1_ras_n = 1'd1;
+reg litedramcore_ext_dfi_p1_we_n = 1'd1;
+reg litedramcore_ext_dfi_p1_cke = 1'd0;
+reg litedramcore_ext_dfi_p1_odt = 1'd0;
+reg litedramcore_ext_dfi_p1_reset_n = 1'd0;
+reg litedramcore_ext_dfi_p1_act_n = 1'd1;
+reg [63:0] litedramcore_ext_dfi_p1_wrdata = 64'd0;
+reg litedramcore_ext_dfi_p1_wrdata_en = 1'd0;
+reg [7:0] litedramcore_ext_dfi_p1_wrdata_mask = 8'd0;
+reg litedramcore_ext_dfi_p1_rddata_en = 1'd0;
+reg [63:0] litedramcore_ext_dfi_p1_rddata = 64'd0;
+reg litedramcore_ext_dfi_p1_rddata_valid = 1'd0;
+reg [14:0] litedramcore_ext_dfi_p2_address = 15'd0;
+reg [2:0] litedramcore_ext_dfi_p2_bank = 3'd0;
+reg litedramcore_ext_dfi_p2_cas_n = 1'd1;
+reg litedramcore_ext_dfi_p2_cs_n = 1'd1;
+reg litedramcore_ext_dfi_p2_ras_n = 1'd1;
+reg litedramcore_ext_dfi_p2_we_n = 1'd1;
+reg litedramcore_ext_dfi_p2_cke = 1'd0;
+reg litedramcore_ext_dfi_p2_odt = 1'd0;
+reg litedramcore_ext_dfi_p2_reset_n = 1'd0;
+reg litedramcore_ext_dfi_p2_act_n = 1'd1;
+reg [63:0] litedramcore_ext_dfi_p2_wrdata = 64'd0;
+reg litedramcore_ext_dfi_p2_wrdata_en = 1'd0;
+reg [7:0] litedramcore_ext_dfi_p2_wrdata_mask = 8'd0;
+reg litedramcore_ext_dfi_p2_rddata_en = 1'd0;
+reg [63:0] litedramcore_ext_dfi_p2_rddata = 64'd0;
+reg litedramcore_ext_dfi_p2_rddata_valid = 1'd0;
+reg [14:0] litedramcore_ext_dfi_p3_address = 15'd0;
+reg [2:0] litedramcore_ext_dfi_p3_bank = 3'd0;
+reg litedramcore_ext_dfi_p3_cas_n = 1'd1;
+reg litedramcore_ext_dfi_p3_cs_n = 1'd1;
+reg litedramcore_ext_dfi_p3_ras_n = 1'd1;
+reg litedramcore_ext_dfi_p3_we_n = 1'd1;
+reg litedramcore_ext_dfi_p3_cke = 1'd0;
+reg litedramcore_ext_dfi_p3_odt = 1'd0;
+reg litedramcore_ext_dfi_p3_reset_n = 1'd0;
+reg litedramcore_ext_dfi_p3_act_n = 1'd1;
+reg [63:0] litedramcore_ext_dfi_p3_wrdata = 64'd0;
+reg litedramcore_ext_dfi_p3_wrdata_en = 1'd0;
+reg [7:0] litedramcore_ext_dfi_p3_wrdata_mask = 8'd0;
+reg litedramcore_ext_dfi_p3_rddata_en = 1'd0;
+reg [63:0] litedramcore_ext_dfi_p3_rddata = 64'd0;
+reg litedramcore_ext_dfi_p3_rddata_valid = 1'd0;
+reg litedramcore_ext_dfi_sel = 1'd0;
+wire litedramcore_sel;
+wire litedramcore_cke;
+wire litedramcore_odt;
+wire litedramcore_reset_n;
+reg [3:0] litedramcore_storage = 4'd1;
+reg litedramcore_re = 1'd0;
+wire litedramcore_phaseinjector0_csrfield_cs;
+wire litedramcore_phaseinjector0_csrfield_we;
+wire litedramcore_phaseinjector0_csrfield_cas;
+wire litedramcore_phaseinjector0_csrfield_ras;
+wire litedramcore_phaseinjector0_csrfield_wren;
+wire litedramcore_phaseinjector0_csrfield_rden;
+reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0;
+reg litedramcore_phaseinjector0_command_re = 1'd0;
+reg litedramcore_phaseinjector0_command_issue_re = 1'd0;
+wire litedramcore_phaseinjector0_command_issue_r;
+reg litedramcore_phaseinjector0_command_issue_we = 1'd0;
+reg litedramcore_phaseinjector0_command_issue_w = 1'd0;
+reg [14:0] litedramcore_phaseinjector0_address_storage = 15'd0;
+reg litedramcore_phaseinjector0_address_re = 1'd0;
+reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0;
+reg litedramcore_phaseinjector0_baddress_re = 1'd0;
+reg [63:0] litedramcore_phaseinjector0_wrdata_storage = 64'd0;
+reg litedramcore_phaseinjector0_wrdata_re = 1'd0;
+reg [63:0] litedramcore_phaseinjector0_rddata_status = 64'd0;
+wire litedramcore_phaseinjector0_rddata_we;
+reg litedramcore_phaseinjector0_rddata_re = 1'd0;
+wire litedramcore_phaseinjector1_csrfield_cs;
+wire litedramcore_phaseinjector1_csrfield_we;
+wire litedramcore_phaseinjector1_csrfield_cas;
+wire litedramcore_phaseinjector1_csrfield_ras;
+wire litedramcore_phaseinjector1_csrfield_wren;
+wire litedramcore_phaseinjector1_csrfield_rden;
+reg [5:0] litedramcore_phaseinjector1_command_storage = 6'd0;
+reg litedramcore_phaseinjector1_command_re = 1'd0;
+reg litedramcore_phaseinjector1_command_issue_re = 1'd0;
+wire litedramcore_phaseinjector1_command_issue_r;
+reg litedramcore_phaseinjector1_command_issue_we = 1'd0;
+reg litedramcore_phaseinjector1_command_issue_w = 1'd0;
+reg [14:0] litedramcore_phaseinjector1_address_storage = 15'd0;
+reg litedramcore_phaseinjector1_address_re = 1'd0;
+reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0;
+reg litedramcore_phaseinjector1_baddress_re = 1'd0;
+reg [63:0] litedramcore_phaseinjector1_wrdata_storage = 64'd0;
+reg litedramcore_phaseinjector1_wrdata_re = 1'd0;
+reg [63:0] litedramcore_phaseinjector1_rddata_status = 64'd0;
+wire litedramcore_phaseinjector1_rddata_we;
+reg litedramcore_phaseinjector1_rddata_re = 1'd0;
+wire litedramcore_phaseinjector2_csrfield_cs;
+wire litedramcore_phaseinjector2_csrfield_we;
+wire litedramcore_phaseinjector2_csrfield_cas;
+wire litedramcore_phaseinjector2_csrfield_ras;
+wire litedramcore_phaseinjector2_csrfield_wren;
+wire litedramcore_phaseinjector2_csrfield_rden;
+reg [5:0] litedramcore_phaseinjector2_command_storage = 6'd0;
+reg litedramcore_phaseinjector2_command_re = 1'd0;
+reg litedramcore_phaseinjector2_command_issue_re = 1'd0;
+wire litedramcore_phaseinjector2_command_issue_r;
+reg litedramcore_phaseinjector2_command_issue_we = 1'd0;
+reg litedramcore_phaseinjector2_command_issue_w = 1'd0;
+reg [14:0] litedramcore_phaseinjector2_address_storage = 15'd0;
+reg litedramcore_phaseinjector2_address_re = 1'd0;
+reg [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0;
+reg litedramcore_phaseinjector2_baddress_re = 1'd0;
+reg [63:0] litedramcore_phaseinjector2_wrdata_storage = 64'd0;
+reg litedramcore_phaseinjector2_wrdata_re = 1'd0;
+reg [63:0] litedramcore_phaseinjector2_rddata_status = 64'd0;
+wire litedramcore_phaseinjector2_rddata_we;
+reg litedramcore_phaseinjector2_rddata_re = 1'd0;
+wire litedramcore_phaseinjector3_csrfield_cs;
+wire litedramcore_phaseinjector3_csrfield_we;
+wire litedramcore_phaseinjector3_csrfield_cas;
+wire litedramcore_phaseinjector3_csrfield_ras;
+wire litedramcore_phaseinjector3_csrfield_wren;
+wire litedramcore_phaseinjector3_csrfield_rden;
+reg [5:0] litedramcore_phaseinjector3_command_storage = 6'd0;
+reg litedramcore_phaseinjector3_command_re = 1'd0;
+reg litedramcore_phaseinjector3_command_issue_re = 1'd0;
+wire litedramcore_phaseinjector3_command_issue_r;
+reg litedramcore_phaseinjector3_command_issue_we = 1'd0;
+reg litedramcore_phaseinjector3_command_issue_w = 1'd0;
+reg [14:0] litedramcore_phaseinjector3_address_storage = 15'd0;
+reg litedramcore_phaseinjector3_address_re = 1'd0;
+reg [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0;
+reg litedramcore_phaseinjector3_baddress_re = 1'd0;
+reg [63:0] litedramcore_phaseinjector3_wrdata_storage = 64'd0;
+reg litedramcore_phaseinjector3_wrdata_re = 1'd0;
+reg [63:0] litedramcore_phaseinjector3_rddata_status = 64'd0;
+wire litedramcore_phaseinjector3_rddata_we;
+reg litedramcore_phaseinjector3_rddata_re = 1'd0;
+wire litedramcore_interface_bank0_valid;
+wire litedramcore_interface_bank0_ready;
+wire litedramcore_interface_bank0_we;
+wire [21:0] litedramcore_interface_bank0_addr;
+wire litedramcore_interface_bank0_lock;
+wire litedramcore_interface_bank0_wdata_ready;
+wire litedramcore_interface_bank0_rdata_valid;
+wire litedramcore_interface_bank1_valid;
+wire litedramcore_interface_bank1_ready;
+wire litedramcore_interface_bank1_we;
+wire [21:0] litedramcore_interface_bank1_addr;
+wire litedramcore_interface_bank1_lock;
+wire litedramcore_interface_bank1_wdata_ready;
+wire litedramcore_interface_bank1_rdata_valid;
+wire litedramcore_interface_bank2_valid;
+wire litedramcore_interface_bank2_ready;
+wire litedramcore_interface_bank2_we;
+wire [21:0] litedramcore_interface_bank2_addr;
+wire litedramcore_interface_bank2_lock;
+wire litedramcore_interface_bank2_wdata_ready;
+wire litedramcore_interface_bank2_rdata_valid;
+wire litedramcore_interface_bank3_valid;
+wire litedramcore_interface_bank3_ready;
+wire litedramcore_interface_bank3_we;
+wire [21:0] litedramcore_interface_bank3_addr;
+wire litedramcore_interface_bank3_lock;
+wire litedramcore_interface_bank3_wdata_ready;
+wire litedramcore_interface_bank3_rdata_valid;
+wire litedramcore_interface_bank4_valid;
+wire litedramcore_interface_bank4_ready;
+wire litedramcore_interface_bank4_we;
+wire [21:0] litedramcore_interface_bank4_addr;
+wire litedramcore_interface_bank4_lock;
+wire litedramcore_interface_bank4_wdata_ready;
+wire litedramcore_interface_bank4_rdata_valid;
+wire litedramcore_interface_bank5_valid;
+wire litedramcore_interface_bank5_ready;
+wire litedramcore_interface_bank5_we;
+wire [21:0] litedramcore_interface_bank5_addr;
+wire litedramcore_interface_bank5_lock;
+wire litedramcore_interface_bank5_wdata_ready;
+wire litedramcore_interface_bank5_rdata_valid;
+wire litedramcore_interface_bank6_valid;
+wire litedramcore_interface_bank6_ready;
+wire litedramcore_interface_bank6_we;
+wire [21:0] litedramcore_interface_bank6_addr;
+wire litedramcore_interface_bank6_lock;
+wire litedramcore_interface_bank6_wdata_ready;
+wire litedramcore_interface_bank6_rdata_valid;
+wire litedramcore_interface_bank7_valid;
+wire litedramcore_interface_bank7_ready;
+wire litedramcore_interface_bank7_we;
+wire [21:0] litedramcore_interface_bank7_addr;
+wire litedramcore_interface_bank7_lock;
+wire litedramcore_interface_bank7_wdata_ready;
+wire litedramcore_interface_bank7_rdata_valid;
+reg [255:0] litedramcore_interface_wdata = 256'd0;
+reg [31:0] litedramcore_interface_wdata_we = 32'd0;
+wire [255:0] litedramcore_interface_rdata;
+reg [14:0] litedramcore_dfi_p0_address = 15'd0;
+reg [2:0] litedramcore_dfi_p0_bank = 3'd0;
+reg litedramcore_dfi_p0_cas_n = 1'd1;
+reg litedramcore_dfi_p0_cs_n = 1'd1;
+reg litedramcore_dfi_p0_ras_n = 1'd1;
+reg litedramcore_dfi_p0_we_n = 1'd1;
+wire litedramcore_dfi_p0_cke;
+wire litedramcore_dfi_p0_odt;
+wire litedramcore_dfi_p0_reset_n;
+reg litedramcore_dfi_p0_act_n = 1'd1;
+wire [63:0] litedramcore_dfi_p0_wrdata;
+reg litedramcore_dfi_p0_wrdata_en = 1'd0;
+wire [7:0] litedramcore_dfi_p0_wrdata_mask;
+reg litedramcore_dfi_p0_rddata_en = 1'd0;
+wire [63:0] litedramcore_dfi_p0_rddata;
+wire litedramcore_dfi_p0_rddata_valid;
+reg [14:0] litedramcore_dfi_p1_address = 15'd0;
+reg [2:0] litedramcore_dfi_p1_bank = 3'd0;
+reg litedramcore_dfi_p1_cas_n = 1'd1;
+reg litedramcore_dfi_p1_cs_n = 1'd1;
+reg litedramcore_dfi_p1_ras_n = 1'd1;
+reg litedramcore_dfi_p1_we_n = 1'd1;
+wire litedramcore_dfi_p1_cke;
+wire litedramcore_dfi_p1_odt;
+wire litedramcore_dfi_p1_reset_n;
+reg litedramcore_dfi_p1_act_n = 1'd1;
+wire [63:0] litedramcore_dfi_p1_wrdata;
+reg litedramcore_dfi_p1_wrdata_en = 1'd0;
+wire [7:0] litedramcore_dfi_p1_wrdata_mask;
+reg litedramcore_dfi_p1_rddata_en = 1'd0;
+wire [63:0] litedramcore_dfi_p1_rddata;
+wire litedramcore_dfi_p1_rddata_valid;
+reg [14:0] litedramcore_dfi_p2_address = 15'd0;
+reg [2:0] litedramcore_dfi_p2_bank = 3'd0;
+reg litedramcore_dfi_p2_cas_n = 1'd1;
+reg litedramcore_dfi_p2_cs_n = 1'd1;
+reg litedramcore_dfi_p2_ras_n = 1'd1;
+reg litedramcore_dfi_p2_we_n = 1'd1;
+wire litedramcore_dfi_p2_cke;
+wire litedramcore_dfi_p2_odt;
+wire litedramcore_dfi_p2_reset_n;
+reg litedramcore_dfi_p2_act_n = 1'd1;
+wire [63:0] litedramcore_dfi_p2_wrdata;
+reg litedramcore_dfi_p2_wrdata_en = 1'd0;
+wire [7:0] litedramcore_dfi_p2_wrdata_mask;
+reg litedramcore_dfi_p2_rddata_en = 1'd0;
+wire [63:0] litedramcore_dfi_p2_rddata;
+wire litedramcore_dfi_p2_rddata_valid;
+reg [14:0] litedramcore_dfi_p3_address = 15'd0;
+reg [2:0] litedramcore_dfi_p3_bank = 3'd0;
+reg litedramcore_dfi_p3_cas_n = 1'd1;
+reg litedramcore_dfi_p3_cs_n = 1'd1;
+reg litedramcore_dfi_p3_ras_n = 1'd1;
+reg litedramcore_dfi_p3_we_n = 1'd1;
+wire litedramcore_dfi_p3_cke;
+wire litedramcore_dfi_p3_odt;
+wire litedramcore_dfi_p3_reset_n;
+reg litedramcore_dfi_p3_act_n = 1'd1;
+wire [63:0] litedramcore_dfi_p3_wrdata;
+reg litedramcore_dfi_p3_wrdata_en = 1'd0;
+wire [7:0] litedramcore_dfi_p3_wrdata_mask;
+reg litedramcore_dfi_p3_rddata_en = 1'd0;
+wire [63:0] litedramcore_dfi_p3_rddata;
+wire litedramcore_dfi_p3_rddata_valid;
+reg litedramcore_cmd_valid = 1'd0;
+reg litedramcore_cmd_ready = 1'd0;
+reg litedramcore_cmd_last = 1'd0;
+reg [14:0] litedramcore_cmd_payload_a = 15'd0;
+reg [2:0] litedramcore_cmd_payload_ba = 3'd0;
+reg litedramcore_cmd_payload_cas = 1'd0;
+reg litedramcore_cmd_payload_ras = 1'd0;
+reg litedramcore_cmd_payload_we = 1'd0;
+reg litedramcore_cmd_payload_is_read = 1'd0;
+reg litedramcore_cmd_payload_is_write = 1'd0;
+wire litedramcore_wants_refresh;
+wire litedramcore_wants_zqcs;
+wire litedramcore_timer_wait;
+wire litedramcore_timer_done0;
+wire [9:0] litedramcore_timer_count0;
+wire litedramcore_timer_done1;
+reg [9:0] litedramcore_timer_count1 = 10'd781;
+wire litedramcore_postponer_req_i;
+reg litedramcore_postponer_req_o = 1'd0;
+reg litedramcore_postponer_count = 1'd0;
+reg litedramcore_sequencer_start0 = 1'd0;
+wire litedramcore_sequencer_done0;
+wire litedramcore_sequencer_start1;
+reg litedramcore_sequencer_done1 = 1'd0;
+reg [5:0] litedramcore_sequencer_counter = 6'd0;
+reg litedramcore_sequencer_count = 1'd0;
+wire litedramcore_zqcs_timer_wait;
+wire litedramcore_zqcs_timer_done0;
+wire [26:0] litedramcore_zqcs_timer_count0;
+wire litedramcore_zqcs_timer_done1;
+reg [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999;
+reg litedramcore_zqcs_executer_start = 1'd0;
+reg litedramcore_zqcs_executer_done = 1'd0;
+reg [4:0] litedramcore_zqcs_executer_counter = 5'd0;
+wire litedramcore_bankmachine0_req_valid;
+wire litedramcore_bankmachine0_req_ready;
+wire litedramcore_bankmachine0_req_we;
+wire [21:0] litedramcore_bankmachine0_req_addr;
+wire litedramcore_bankmachine0_req_lock;
+reg litedramcore_bankmachine0_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine0_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine0_refresh_req;
+reg litedramcore_bankmachine0_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine0_cmd_valid = 1'd0;
+reg litedramcore_bankmachine0_cmd_ready = 1'd0;
+reg [14:0] litedramcore_bankmachine0_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine0_cmd_payload_ba;
+reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine0_auto_precharge = 1'd0;
+wire litedramcore_bankmachine0_sink_valid;
+wire litedramcore_bankmachine0_sink_ready;
+reg litedramcore_bankmachine0_sink_first = 1'd0;
+reg litedramcore_bankmachine0_sink_last = 1'd0;
+wire litedramcore_bankmachine0_sink_payload_we;
+wire [21:0] litedramcore_bankmachine0_sink_payload_addr;
+wire litedramcore_bankmachine0_source_valid;
+wire litedramcore_bankmachine0_source_ready;
+wire litedramcore_bankmachine0_source_first;
+wire litedramcore_bankmachine0_source_last;
+wire litedramcore_bankmachine0_source_payload_we;
+wire [21:0] litedramcore_bankmachine0_source_payload_addr;
+wire litedramcore_bankmachine0_syncfifo0_we;
+wire litedramcore_bankmachine0_syncfifo0_writable;
+wire litedramcore_bankmachine0_syncfifo0_re;
+wire litedramcore_bankmachine0_syncfifo0_readable;
+wire [24:0] litedramcore_bankmachine0_syncfifo0_din;
+wire [24:0] litedramcore_bankmachine0_syncfifo0_dout;
+reg [4:0] litedramcore_bankmachine0_level = 5'd0;
+reg litedramcore_bankmachine0_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine0_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine0_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine0_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine0_wrport_dat_r;
+wire litedramcore_bankmachine0_wrport_we;
+wire [24:0] litedramcore_bankmachine0_wrport_dat_w;
+wire litedramcore_bankmachine0_do_read;
+wire [3:0] litedramcore_bankmachine0_rdport_adr;
+wire [24:0] litedramcore_bankmachine0_rdport_dat_r;
+wire litedramcore_bankmachine0_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine0_fifo_in_payload_addr;
+wire litedramcore_bankmachine0_fifo_in_first;
+wire litedramcore_bankmachine0_fifo_in_last;
+wire litedramcore_bankmachine0_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine0_fifo_out_payload_addr;
+wire litedramcore_bankmachine0_fifo_out_first;
+wire litedramcore_bankmachine0_fifo_out_last;
+wire litedramcore_bankmachine0_sink_sink_valid;
+wire litedramcore_bankmachine0_sink_sink_ready;
+wire litedramcore_bankmachine0_sink_sink_first;
+wire litedramcore_bankmachine0_sink_sink_last;
+wire litedramcore_bankmachine0_sink_sink_payload_we;
+wire [21:0] litedramcore_bankmachine0_sink_sink_payload_addr;
+wire litedramcore_bankmachine0_source_source_valid;
+wire litedramcore_bankmachine0_source_source_ready;
+wire litedramcore_bankmachine0_source_source_first;
+wire litedramcore_bankmachine0_source_source_last;
+wire litedramcore_bankmachine0_source_source_payload_we;
+wire [21:0] litedramcore_bankmachine0_source_source_payload_addr;
+wire litedramcore_bankmachine0_pipe_valid_sink_valid;
+wire litedramcore_bankmachine0_pipe_valid_sink_ready;
+wire litedramcore_bankmachine0_pipe_valid_sink_first;
+wire litedramcore_bankmachine0_pipe_valid_sink_last;
+wire litedramcore_bankmachine0_pipe_valid_sink_payload_we;
+wire [21:0] litedramcore_bankmachine0_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine0_pipe_valid_source_ready;
+reg litedramcore_bankmachine0_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine0_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0;
+reg [21:0] litedramcore_bankmachine0_pipe_valid_source_payload_addr = 22'd0;
+reg [14:0] litedramcore_bankmachine0_row = 15'd0;
+reg litedramcore_bankmachine0_row_opened = 1'd0;
+wire litedramcore_bankmachine0_row_hit;
+reg litedramcore_bankmachine0_row_open = 1'd0;
+reg litedramcore_bankmachine0_row_close = 1'd0;
+reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine0_twtpcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine0_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine0_trccon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine0_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine0_trccon_count = 3'd0;
+wire litedramcore_bankmachine0_trascon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine0_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine0_trascon_count = 3'd0;
+wire litedramcore_bankmachine1_req_valid;
+wire litedramcore_bankmachine1_req_ready;
+wire litedramcore_bankmachine1_req_we;
+wire [21:0] litedramcore_bankmachine1_req_addr;
+wire litedramcore_bankmachine1_req_lock;
+reg litedramcore_bankmachine1_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine1_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine1_refresh_req;
+reg litedramcore_bankmachine1_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine1_cmd_valid = 1'd0;
+reg litedramcore_bankmachine1_cmd_ready = 1'd0;
+reg [14:0] litedramcore_bankmachine1_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine1_cmd_payload_ba;
+reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine1_auto_precharge = 1'd0;
+wire litedramcore_bankmachine1_sink_valid;
+wire litedramcore_bankmachine1_sink_ready;
+reg litedramcore_bankmachine1_sink_first = 1'd0;
+reg litedramcore_bankmachine1_sink_last = 1'd0;
+wire litedramcore_bankmachine1_sink_payload_we;
+wire [21:0] litedramcore_bankmachine1_sink_payload_addr;
+wire litedramcore_bankmachine1_source_valid;
+wire litedramcore_bankmachine1_source_ready;
+wire litedramcore_bankmachine1_source_first;
+wire litedramcore_bankmachine1_source_last;
+wire litedramcore_bankmachine1_source_payload_we;
+wire [21:0] litedramcore_bankmachine1_source_payload_addr;
+wire litedramcore_bankmachine1_syncfifo1_we;
+wire litedramcore_bankmachine1_syncfifo1_writable;
+wire litedramcore_bankmachine1_syncfifo1_re;
+wire litedramcore_bankmachine1_syncfifo1_readable;
+wire [24:0] litedramcore_bankmachine1_syncfifo1_din;
+wire [24:0] litedramcore_bankmachine1_syncfifo1_dout;
+reg [4:0] litedramcore_bankmachine1_level = 5'd0;
+reg litedramcore_bankmachine1_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine1_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine1_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine1_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine1_wrport_dat_r;
+wire litedramcore_bankmachine1_wrport_we;
+wire [24:0] litedramcore_bankmachine1_wrport_dat_w;
+wire litedramcore_bankmachine1_do_read;
+wire [3:0] litedramcore_bankmachine1_rdport_adr;
+wire [24:0] litedramcore_bankmachine1_rdport_dat_r;
+wire litedramcore_bankmachine1_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine1_fifo_in_payload_addr;
+wire litedramcore_bankmachine1_fifo_in_first;
+wire litedramcore_bankmachine1_fifo_in_last;
+wire litedramcore_bankmachine1_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine1_fifo_out_payload_addr;
+wire litedramcore_bankmachine1_fifo_out_first;
+wire litedramcore_bankmachine1_fifo_out_last;
+wire litedramcore_bankmachine1_sink_sink_valid;
+wire litedramcore_bankmachine1_sink_sink_ready;
+wire litedramcore_bankmachine1_sink_sink_first;
+wire litedramcore_bankmachine1_sink_sink_last;
+wire litedramcore_bankmachine1_sink_sink_payload_we;
+wire [21:0] litedramcore_bankmachine1_sink_sink_payload_addr;
+wire litedramcore_bankmachine1_source_source_valid;
+wire litedramcore_bankmachine1_source_source_ready;
+wire litedramcore_bankmachine1_source_source_first;
+wire litedramcore_bankmachine1_source_source_last;
+wire litedramcore_bankmachine1_source_source_payload_we;
+wire [21:0] litedramcore_bankmachine1_source_source_payload_addr;
+wire litedramcore_bankmachine1_pipe_valid_sink_valid;
+wire litedramcore_bankmachine1_pipe_valid_sink_ready;
+wire litedramcore_bankmachine1_pipe_valid_sink_first;
+wire litedramcore_bankmachine1_pipe_valid_sink_last;
+wire litedramcore_bankmachine1_pipe_valid_sink_payload_we;
+wire [21:0] litedramcore_bankmachine1_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine1_pipe_valid_source_ready;
+reg litedramcore_bankmachine1_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine1_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0;
+reg [21:0] litedramcore_bankmachine1_pipe_valid_source_payload_addr = 22'd0;
+reg [14:0] litedramcore_bankmachine1_row = 15'd0;
+reg litedramcore_bankmachine1_row_opened = 1'd0;
+wire litedramcore_bankmachine1_row_hit;
+reg litedramcore_bankmachine1_row_open = 1'd0;
+reg litedramcore_bankmachine1_row_close = 1'd0;
+reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine1_twtpcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine1_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine1_trccon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine1_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine1_trccon_count = 3'd0;
+wire litedramcore_bankmachine1_trascon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine1_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine1_trascon_count = 3'd0;
+wire litedramcore_bankmachine2_req_valid;
+wire litedramcore_bankmachine2_req_ready;
+wire litedramcore_bankmachine2_req_we;
+wire [21:0] litedramcore_bankmachine2_req_addr;
+wire litedramcore_bankmachine2_req_lock;
+reg litedramcore_bankmachine2_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine2_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine2_refresh_req;
+reg litedramcore_bankmachine2_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine2_cmd_valid = 1'd0;
+reg litedramcore_bankmachine2_cmd_ready = 1'd0;
+reg [14:0] litedramcore_bankmachine2_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine2_cmd_payload_ba;
+reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine2_auto_precharge = 1'd0;
+wire litedramcore_bankmachine2_sink_valid;
+wire litedramcore_bankmachine2_sink_ready;
+reg litedramcore_bankmachine2_sink_first = 1'd0;
+reg litedramcore_bankmachine2_sink_last = 1'd0;
+wire litedramcore_bankmachine2_sink_payload_we;
+wire [21:0] litedramcore_bankmachine2_sink_payload_addr;
+wire litedramcore_bankmachine2_source_valid;
+wire litedramcore_bankmachine2_source_ready;
+wire litedramcore_bankmachine2_source_first;
+wire litedramcore_bankmachine2_source_last;
+wire litedramcore_bankmachine2_source_payload_we;
+wire [21:0] litedramcore_bankmachine2_source_payload_addr;
+wire litedramcore_bankmachine2_syncfifo2_we;
+wire litedramcore_bankmachine2_syncfifo2_writable;
+wire litedramcore_bankmachine2_syncfifo2_re;
+wire litedramcore_bankmachine2_syncfifo2_readable;
+wire [24:0] litedramcore_bankmachine2_syncfifo2_din;
+wire [24:0] litedramcore_bankmachine2_syncfifo2_dout;
+reg [4:0] litedramcore_bankmachine2_level = 5'd0;
+reg litedramcore_bankmachine2_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine2_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine2_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine2_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine2_wrport_dat_r;
+wire litedramcore_bankmachine2_wrport_we;
+wire [24:0] litedramcore_bankmachine2_wrport_dat_w;
+wire litedramcore_bankmachine2_do_read;
+wire [3:0] litedramcore_bankmachine2_rdport_adr;
+wire [24:0] litedramcore_bankmachine2_rdport_dat_r;
+wire litedramcore_bankmachine2_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine2_fifo_in_payload_addr;
+wire litedramcore_bankmachine2_fifo_in_first;
+wire litedramcore_bankmachine2_fifo_in_last;
+wire litedramcore_bankmachine2_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine2_fifo_out_payload_addr;
+wire litedramcore_bankmachine2_fifo_out_first;
+wire litedramcore_bankmachine2_fifo_out_last;
+wire litedramcore_bankmachine2_sink_sink_valid;
+wire litedramcore_bankmachine2_sink_sink_ready;
+wire litedramcore_bankmachine2_sink_sink_first;
+wire litedramcore_bankmachine2_sink_sink_last;
+wire litedramcore_bankmachine2_sink_sink_payload_we;
+wire [21:0] litedramcore_bankmachine2_sink_sink_payload_addr;
+wire litedramcore_bankmachine2_source_source_valid;
+wire litedramcore_bankmachine2_source_source_ready;
+wire litedramcore_bankmachine2_source_source_first;
+wire litedramcore_bankmachine2_source_source_last;
+wire litedramcore_bankmachine2_source_source_payload_we;
+wire [21:0] litedramcore_bankmachine2_source_source_payload_addr;
+wire litedramcore_bankmachine2_pipe_valid_sink_valid;
+wire litedramcore_bankmachine2_pipe_valid_sink_ready;
+wire litedramcore_bankmachine2_pipe_valid_sink_first;
+wire litedramcore_bankmachine2_pipe_valid_sink_last;
+wire litedramcore_bankmachine2_pipe_valid_sink_payload_we;
+wire [21:0] litedramcore_bankmachine2_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine2_pipe_valid_source_ready;
+reg litedramcore_bankmachine2_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine2_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0;
+reg [21:0] litedramcore_bankmachine2_pipe_valid_source_payload_addr = 22'd0;
+reg [14:0] litedramcore_bankmachine2_row = 15'd0;
+reg litedramcore_bankmachine2_row_opened = 1'd0;
+wire litedramcore_bankmachine2_row_hit;
+reg litedramcore_bankmachine2_row_open = 1'd0;
+reg litedramcore_bankmachine2_row_close = 1'd0;
+reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine2_twtpcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine2_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine2_trccon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine2_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine2_trccon_count = 3'd0;
+wire litedramcore_bankmachine2_trascon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine2_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine2_trascon_count = 3'd0;
+wire litedramcore_bankmachine3_req_valid;
+wire litedramcore_bankmachine3_req_ready;
+wire litedramcore_bankmachine3_req_we;
+wire [21:0] litedramcore_bankmachine3_req_addr;
+wire litedramcore_bankmachine3_req_lock;
+reg litedramcore_bankmachine3_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine3_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine3_refresh_req;
+reg litedramcore_bankmachine3_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine3_cmd_valid = 1'd0;
+reg litedramcore_bankmachine3_cmd_ready = 1'd0;
+reg [14:0] litedramcore_bankmachine3_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine3_cmd_payload_ba;
+reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine3_auto_precharge = 1'd0;
+wire litedramcore_bankmachine3_sink_valid;
+wire litedramcore_bankmachine3_sink_ready;
+reg litedramcore_bankmachine3_sink_first = 1'd0;
+reg litedramcore_bankmachine3_sink_last = 1'd0;
+wire litedramcore_bankmachine3_sink_payload_we;
+wire [21:0] litedramcore_bankmachine3_sink_payload_addr;
+wire litedramcore_bankmachine3_source_valid;
+wire litedramcore_bankmachine3_source_ready;
+wire litedramcore_bankmachine3_source_first;
+wire litedramcore_bankmachine3_source_last;
+wire litedramcore_bankmachine3_source_payload_we;
+wire [21:0] litedramcore_bankmachine3_source_payload_addr;
+wire litedramcore_bankmachine3_syncfifo3_we;
+wire litedramcore_bankmachine3_syncfifo3_writable;
+wire litedramcore_bankmachine3_syncfifo3_re;
+wire litedramcore_bankmachine3_syncfifo3_readable;
+wire [24:0] litedramcore_bankmachine3_syncfifo3_din;
+wire [24:0] litedramcore_bankmachine3_syncfifo3_dout;
+reg [4:0] litedramcore_bankmachine3_level = 5'd0;
+reg litedramcore_bankmachine3_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine3_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine3_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine3_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine3_wrport_dat_r;
+wire litedramcore_bankmachine3_wrport_we;
+wire [24:0] litedramcore_bankmachine3_wrport_dat_w;
+wire litedramcore_bankmachine3_do_read;
+wire [3:0] litedramcore_bankmachine3_rdport_adr;
+wire [24:0] litedramcore_bankmachine3_rdport_dat_r;
+wire litedramcore_bankmachine3_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine3_fifo_in_payload_addr;
+wire litedramcore_bankmachine3_fifo_in_first;
+wire litedramcore_bankmachine3_fifo_in_last;
+wire litedramcore_bankmachine3_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine3_fifo_out_payload_addr;
+wire litedramcore_bankmachine3_fifo_out_first;
+wire litedramcore_bankmachine3_fifo_out_last;
+wire litedramcore_bankmachine3_sink_sink_valid;
+wire litedramcore_bankmachine3_sink_sink_ready;
+wire litedramcore_bankmachine3_sink_sink_first;
+wire litedramcore_bankmachine3_sink_sink_last;
+wire litedramcore_bankmachine3_sink_sink_payload_we;
+wire [21:0] litedramcore_bankmachine3_sink_sink_payload_addr;
+wire litedramcore_bankmachine3_source_source_valid;
+wire litedramcore_bankmachine3_source_source_ready;
+wire litedramcore_bankmachine3_source_source_first;
+wire litedramcore_bankmachine3_source_source_last;
+wire litedramcore_bankmachine3_source_source_payload_we;
+wire [21:0] litedramcore_bankmachine3_source_source_payload_addr;
+wire litedramcore_bankmachine3_pipe_valid_sink_valid;
+wire litedramcore_bankmachine3_pipe_valid_sink_ready;
+wire litedramcore_bankmachine3_pipe_valid_sink_first;
+wire litedramcore_bankmachine3_pipe_valid_sink_last;
+wire litedramcore_bankmachine3_pipe_valid_sink_payload_we;
+wire [21:0] litedramcore_bankmachine3_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine3_pipe_valid_source_ready;
+reg litedramcore_bankmachine3_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine3_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0;
+reg [21:0] litedramcore_bankmachine3_pipe_valid_source_payload_addr = 22'd0;
+reg [14:0] litedramcore_bankmachine3_row = 15'd0;
+reg litedramcore_bankmachine3_row_opened = 1'd0;
+wire litedramcore_bankmachine3_row_hit;
+reg litedramcore_bankmachine3_row_open = 1'd0;
+reg litedramcore_bankmachine3_row_close = 1'd0;
+reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine3_twtpcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine3_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine3_trccon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine3_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine3_trccon_count = 3'd0;
+wire litedramcore_bankmachine3_trascon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine3_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine3_trascon_count = 3'd0;
+wire litedramcore_bankmachine4_req_valid;
+wire litedramcore_bankmachine4_req_ready;
+wire litedramcore_bankmachine4_req_we;
+wire [21:0] litedramcore_bankmachine4_req_addr;
+wire litedramcore_bankmachine4_req_lock;
+reg litedramcore_bankmachine4_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine4_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine4_refresh_req;
+reg litedramcore_bankmachine4_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine4_cmd_valid = 1'd0;
+reg litedramcore_bankmachine4_cmd_ready = 1'd0;
+reg [14:0] litedramcore_bankmachine4_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine4_cmd_payload_ba;
+reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine4_auto_precharge = 1'd0;
+wire litedramcore_bankmachine4_sink_valid;
+wire litedramcore_bankmachine4_sink_ready;
+reg litedramcore_bankmachine4_sink_first = 1'd0;
+reg litedramcore_bankmachine4_sink_last = 1'd0;
+wire litedramcore_bankmachine4_sink_payload_we;
+wire [21:0] litedramcore_bankmachine4_sink_payload_addr;
+wire litedramcore_bankmachine4_source_valid;
+wire litedramcore_bankmachine4_source_ready;
+wire litedramcore_bankmachine4_source_first;
+wire litedramcore_bankmachine4_source_last;
+wire litedramcore_bankmachine4_source_payload_we;
+wire [21:0] litedramcore_bankmachine4_source_payload_addr;
+wire litedramcore_bankmachine4_syncfifo4_we;
+wire litedramcore_bankmachine4_syncfifo4_writable;
+wire litedramcore_bankmachine4_syncfifo4_re;
+wire litedramcore_bankmachine4_syncfifo4_readable;
+wire [24:0] litedramcore_bankmachine4_syncfifo4_din;
+wire [24:0] litedramcore_bankmachine4_syncfifo4_dout;
+reg [4:0] litedramcore_bankmachine4_level = 5'd0;
+reg litedramcore_bankmachine4_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine4_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine4_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine4_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine4_wrport_dat_r;
+wire litedramcore_bankmachine4_wrport_we;
+wire [24:0] litedramcore_bankmachine4_wrport_dat_w;
+wire litedramcore_bankmachine4_do_read;
+wire [3:0] litedramcore_bankmachine4_rdport_adr;
+wire [24:0] litedramcore_bankmachine4_rdport_dat_r;
+wire litedramcore_bankmachine4_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine4_fifo_in_payload_addr;
+wire litedramcore_bankmachine4_fifo_in_first;
+wire litedramcore_bankmachine4_fifo_in_last;
+wire litedramcore_bankmachine4_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine4_fifo_out_payload_addr;
+wire litedramcore_bankmachine4_fifo_out_first;
+wire litedramcore_bankmachine4_fifo_out_last;
+wire litedramcore_bankmachine4_sink_sink_valid;
+wire litedramcore_bankmachine4_sink_sink_ready;
+wire litedramcore_bankmachine4_sink_sink_first;
+wire litedramcore_bankmachine4_sink_sink_last;
+wire litedramcore_bankmachine4_sink_sink_payload_we;
+wire [21:0] litedramcore_bankmachine4_sink_sink_payload_addr;
+wire litedramcore_bankmachine4_source_source_valid;
+wire litedramcore_bankmachine4_source_source_ready;
+wire litedramcore_bankmachine4_source_source_first;
+wire litedramcore_bankmachine4_source_source_last;
+wire litedramcore_bankmachine4_source_source_payload_we;
+wire [21:0] litedramcore_bankmachine4_source_source_payload_addr;
+wire litedramcore_bankmachine4_pipe_valid_sink_valid;
+wire litedramcore_bankmachine4_pipe_valid_sink_ready;
+wire litedramcore_bankmachine4_pipe_valid_sink_first;
+wire litedramcore_bankmachine4_pipe_valid_sink_last;
+wire litedramcore_bankmachine4_pipe_valid_sink_payload_we;
+wire [21:0] litedramcore_bankmachine4_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine4_pipe_valid_source_ready;
+reg litedramcore_bankmachine4_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine4_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0;
+reg [21:0] litedramcore_bankmachine4_pipe_valid_source_payload_addr = 22'd0;
+reg [14:0] litedramcore_bankmachine4_row = 15'd0;
+reg litedramcore_bankmachine4_row_opened = 1'd0;
+wire litedramcore_bankmachine4_row_hit;
+reg litedramcore_bankmachine4_row_open = 1'd0;
+reg litedramcore_bankmachine4_row_close = 1'd0;
+reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine4_twtpcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine4_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine4_trccon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine4_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine4_trccon_count = 3'd0;
+wire litedramcore_bankmachine4_trascon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine4_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine4_trascon_count = 3'd0;
+wire litedramcore_bankmachine5_req_valid;
+wire litedramcore_bankmachine5_req_ready;
+wire litedramcore_bankmachine5_req_we;
+wire [21:0] litedramcore_bankmachine5_req_addr;
+wire litedramcore_bankmachine5_req_lock;
+reg litedramcore_bankmachine5_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine5_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine5_refresh_req;
+reg litedramcore_bankmachine5_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine5_cmd_valid = 1'd0;
+reg litedramcore_bankmachine5_cmd_ready = 1'd0;
+reg [14:0] litedramcore_bankmachine5_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine5_cmd_payload_ba;
+reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine5_auto_precharge = 1'd0;
+wire litedramcore_bankmachine5_sink_valid;
+wire litedramcore_bankmachine5_sink_ready;
+reg litedramcore_bankmachine5_sink_first = 1'd0;
+reg litedramcore_bankmachine5_sink_last = 1'd0;
+wire litedramcore_bankmachine5_sink_payload_we;
+wire [21:0] litedramcore_bankmachine5_sink_payload_addr;
+wire litedramcore_bankmachine5_source_valid;
+wire litedramcore_bankmachine5_source_ready;
+wire litedramcore_bankmachine5_source_first;
+wire litedramcore_bankmachine5_source_last;
+wire litedramcore_bankmachine5_source_payload_we;
+wire [21:0] litedramcore_bankmachine5_source_payload_addr;
+wire litedramcore_bankmachine5_syncfifo5_we;
+wire litedramcore_bankmachine5_syncfifo5_writable;
+wire litedramcore_bankmachine5_syncfifo5_re;
+wire litedramcore_bankmachine5_syncfifo5_readable;
+wire [24:0] litedramcore_bankmachine5_syncfifo5_din;
+wire [24:0] litedramcore_bankmachine5_syncfifo5_dout;
+reg [4:0] litedramcore_bankmachine5_level = 5'd0;
+reg litedramcore_bankmachine5_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine5_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine5_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine5_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine5_wrport_dat_r;
+wire litedramcore_bankmachine5_wrport_we;
+wire [24:0] litedramcore_bankmachine5_wrport_dat_w;
+wire litedramcore_bankmachine5_do_read;
+wire [3:0] litedramcore_bankmachine5_rdport_adr;
+wire [24:0] litedramcore_bankmachine5_rdport_dat_r;
+wire litedramcore_bankmachine5_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine5_fifo_in_payload_addr;
+wire litedramcore_bankmachine5_fifo_in_first;
+wire litedramcore_bankmachine5_fifo_in_last;
+wire litedramcore_bankmachine5_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine5_fifo_out_payload_addr;
+wire litedramcore_bankmachine5_fifo_out_first;
+wire litedramcore_bankmachine5_fifo_out_last;
+wire litedramcore_bankmachine5_sink_sink_valid;
+wire litedramcore_bankmachine5_sink_sink_ready;
+wire litedramcore_bankmachine5_sink_sink_first;
+wire litedramcore_bankmachine5_sink_sink_last;
+wire litedramcore_bankmachine5_sink_sink_payload_we;
+wire [21:0] litedramcore_bankmachine5_sink_sink_payload_addr;
+wire litedramcore_bankmachine5_source_source_valid;
+wire litedramcore_bankmachine5_source_source_ready;
+wire litedramcore_bankmachine5_source_source_first;
+wire litedramcore_bankmachine5_source_source_last;
+wire litedramcore_bankmachine5_source_source_payload_we;
+wire [21:0] litedramcore_bankmachine5_source_source_payload_addr;
+wire litedramcore_bankmachine5_pipe_valid_sink_valid;
+wire litedramcore_bankmachine5_pipe_valid_sink_ready;
+wire litedramcore_bankmachine5_pipe_valid_sink_first;
+wire litedramcore_bankmachine5_pipe_valid_sink_last;
+wire litedramcore_bankmachine5_pipe_valid_sink_payload_we;
+wire [21:0] litedramcore_bankmachine5_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine5_pipe_valid_source_ready;
+reg litedramcore_bankmachine5_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine5_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0;
+reg [21:0] litedramcore_bankmachine5_pipe_valid_source_payload_addr = 22'd0;
+reg [14:0] litedramcore_bankmachine5_row = 15'd0;
+reg litedramcore_bankmachine5_row_opened = 1'd0;
+wire litedramcore_bankmachine5_row_hit;
+reg litedramcore_bankmachine5_row_open = 1'd0;
+reg litedramcore_bankmachine5_row_close = 1'd0;
+reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine5_twtpcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine5_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine5_trccon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine5_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine5_trccon_count = 3'd0;
+wire litedramcore_bankmachine5_trascon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine5_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine5_trascon_count = 3'd0;
+wire litedramcore_bankmachine6_req_valid;
+wire litedramcore_bankmachine6_req_ready;
+wire litedramcore_bankmachine6_req_we;
+wire [21:0] litedramcore_bankmachine6_req_addr;
+wire litedramcore_bankmachine6_req_lock;
+reg litedramcore_bankmachine6_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine6_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine6_refresh_req;
+reg litedramcore_bankmachine6_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine6_cmd_valid = 1'd0;
+reg litedramcore_bankmachine6_cmd_ready = 1'd0;
+reg [14:0] litedramcore_bankmachine6_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine6_cmd_payload_ba;
+reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine6_auto_precharge = 1'd0;
+wire litedramcore_bankmachine6_sink_valid;
+wire litedramcore_bankmachine6_sink_ready;
+reg litedramcore_bankmachine6_sink_first = 1'd0;
+reg litedramcore_bankmachine6_sink_last = 1'd0;
+wire litedramcore_bankmachine6_sink_payload_we;
+wire [21:0] litedramcore_bankmachine6_sink_payload_addr;
+wire litedramcore_bankmachine6_source_valid;
+wire litedramcore_bankmachine6_source_ready;
+wire litedramcore_bankmachine6_source_first;
+wire litedramcore_bankmachine6_source_last;
+wire litedramcore_bankmachine6_source_payload_we;
+wire [21:0] litedramcore_bankmachine6_source_payload_addr;
+wire litedramcore_bankmachine6_syncfifo6_we;
+wire litedramcore_bankmachine6_syncfifo6_writable;
+wire litedramcore_bankmachine6_syncfifo6_re;
+wire litedramcore_bankmachine6_syncfifo6_readable;
+wire [24:0] litedramcore_bankmachine6_syncfifo6_din;
+wire [24:0] litedramcore_bankmachine6_syncfifo6_dout;
+reg [4:0] litedramcore_bankmachine6_level = 5'd0;
+reg litedramcore_bankmachine6_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine6_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine6_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine6_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine6_wrport_dat_r;
+wire litedramcore_bankmachine6_wrport_we;
+wire [24:0] litedramcore_bankmachine6_wrport_dat_w;
+wire litedramcore_bankmachine6_do_read;
+wire [3:0] litedramcore_bankmachine6_rdport_adr;
+wire [24:0] litedramcore_bankmachine6_rdport_dat_r;
+wire litedramcore_bankmachine6_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine6_fifo_in_payload_addr;
+wire litedramcore_bankmachine6_fifo_in_first;
+wire litedramcore_bankmachine6_fifo_in_last;
+wire litedramcore_bankmachine6_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine6_fifo_out_payload_addr;
+wire litedramcore_bankmachine6_fifo_out_first;
+wire litedramcore_bankmachine6_fifo_out_last;
+wire litedramcore_bankmachine6_sink_sink_valid;
+wire litedramcore_bankmachine6_sink_sink_ready;
+wire litedramcore_bankmachine6_sink_sink_first;
+wire litedramcore_bankmachine6_sink_sink_last;
+wire litedramcore_bankmachine6_sink_sink_payload_we;
+wire [21:0] litedramcore_bankmachine6_sink_sink_payload_addr;
+wire litedramcore_bankmachine6_source_source_valid;
+wire litedramcore_bankmachine6_source_source_ready;
+wire litedramcore_bankmachine6_source_source_first;
+wire litedramcore_bankmachine6_source_source_last;
+wire litedramcore_bankmachine6_source_source_payload_we;
+wire [21:0] litedramcore_bankmachine6_source_source_payload_addr;
+wire litedramcore_bankmachine6_pipe_valid_sink_valid;
+wire litedramcore_bankmachine6_pipe_valid_sink_ready;
+wire litedramcore_bankmachine6_pipe_valid_sink_first;
+wire litedramcore_bankmachine6_pipe_valid_sink_last;
+wire litedramcore_bankmachine6_pipe_valid_sink_payload_we;
+wire [21:0] litedramcore_bankmachine6_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine6_pipe_valid_source_ready;
+reg litedramcore_bankmachine6_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine6_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0;
+reg [21:0] litedramcore_bankmachine6_pipe_valid_source_payload_addr = 22'd0;
+reg [14:0] litedramcore_bankmachine6_row = 15'd0;
+reg litedramcore_bankmachine6_row_opened = 1'd0;
+wire litedramcore_bankmachine6_row_hit;
+reg litedramcore_bankmachine6_row_open = 1'd0;
+reg litedramcore_bankmachine6_row_close = 1'd0;
+reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine6_twtpcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine6_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine6_trccon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine6_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine6_trccon_count = 3'd0;
+wire litedramcore_bankmachine6_trascon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine6_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine6_trascon_count = 3'd0;
+wire litedramcore_bankmachine7_req_valid;
+wire litedramcore_bankmachine7_req_ready;
+wire litedramcore_bankmachine7_req_we;
+wire [21:0] litedramcore_bankmachine7_req_addr;
+wire litedramcore_bankmachine7_req_lock;
+reg litedramcore_bankmachine7_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine7_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine7_refresh_req;
+reg litedramcore_bankmachine7_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine7_cmd_valid = 1'd0;
+reg litedramcore_bankmachine7_cmd_ready = 1'd0;
+reg [14:0] litedramcore_bankmachine7_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine7_cmd_payload_ba;
+reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine7_auto_precharge = 1'd0;
+wire litedramcore_bankmachine7_sink_valid;
+wire litedramcore_bankmachine7_sink_ready;
+reg litedramcore_bankmachine7_sink_first = 1'd0;
+reg litedramcore_bankmachine7_sink_last = 1'd0;
+wire litedramcore_bankmachine7_sink_payload_we;
+wire [21:0] litedramcore_bankmachine7_sink_payload_addr;
+wire litedramcore_bankmachine7_source_valid;
+wire litedramcore_bankmachine7_source_ready;
+wire litedramcore_bankmachine7_source_first;
+wire litedramcore_bankmachine7_source_last;
+wire litedramcore_bankmachine7_source_payload_we;
+wire [21:0] litedramcore_bankmachine7_source_payload_addr;
+wire litedramcore_bankmachine7_syncfifo7_we;
+wire litedramcore_bankmachine7_syncfifo7_writable;
+wire litedramcore_bankmachine7_syncfifo7_re;
+wire litedramcore_bankmachine7_syncfifo7_readable;
+wire [24:0] litedramcore_bankmachine7_syncfifo7_din;
+wire [24:0] litedramcore_bankmachine7_syncfifo7_dout;
+reg [4:0] litedramcore_bankmachine7_level = 5'd0;
+reg litedramcore_bankmachine7_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine7_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine7_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine7_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine7_wrport_dat_r;
+wire litedramcore_bankmachine7_wrport_we;
+wire [24:0] litedramcore_bankmachine7_wrport_dat_w;
+wire litedramcore_bankmachine7_do_read;
+wire [3:0] litedramcore_bankmachine7_rdport_adr;
+wire [24:0] litedramcore_bankmachine7_rdport_dat_r;
+wire litedramcore_bankmachine7_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine7_fifo_in_payload_addr;
+wire litedramcore_bankmachine7_fifo_in_first;
+wire litedramcore_bankmachine7_fifo_in_last;
+wire litedramcore_bankmachine7_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine7_fifo_out_payload_addr;
+wire litedramcore_bankmachine7_fifo_out_first;
+wire litedramcore_bankmachine7_fifo_out_last;
+wire litedramcore_bankmachine7_sink_sink_valid;
+wire litedramcore_bankmachine7_sink_sink_ready;
+wire litedramcore_bankmachine7_sink_sink_first;
+wire litedramcore_bankmachine7_sink_sink_last;
+wire litedramcore_bankmachine7_sink_sink_payload_we;
+wire [21:0] litedramcore_bankmachine7_sink_sink_payload_addr;
+wire litedramcore_bankmachine7_source_source_valid;
+wire litedramcore_bankmachine7_source_source_ready;
+wire litedramcore_bankmachine7_source_source_first;
+wire litedramcore_bankmachine7_source_source_last;
+wire litedramcore_bankmachine7_source_source_payload_we;
+wire [21:0] litedramcore_bankmachine7_source_source_payload_addr;
+wire litedramcore_bankmachine7_pipe_valid_sink_valid;
+wire litedramcore_bankmachine7_pipe_valid_sink_ready;
+wire litedramcore_bankmachine7_pipe_valid_sink_first;
+wire litedramcore_bankmachine7_pipe_valid_sink_last;
+wire litedramcore_bankmachine7_pipe_valid_sink_payload_we;
+wire [21:0] litedramcore_bankmachine7_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine7_pipe_valid_source_ready;
+reg litedramcore_bankmachine7_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine7_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0;
+reg [21:0] litedramcore_bankmachine7_pipe_valid_source_payload_addr = 22'd0;
+reg [14:0] litedramcore_bankmachine7_row = 15'd0;
+reg litedramcore_bankmachine7_row_opened = 1'd0;
+wire litedramcore_bankmachine7_row_hit;
+reg litedramcore_bankmachine7_row_open = 1'd0;
+reg litedramcore_bankmachine7_row_close = 1'd0;
+reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine7_twtpcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine7_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine7_trccon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine7_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine7_trccon_count = 3'd0;
+wire litedramcore_bankmachine7_trascon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine7_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine7_trascon_count = 3'd0;
+wire litedramcore_ras_allowed;
+wire litedramcore_cas_allowed;
+wire [1:0] litedramcore_rdcmdphase;
+wire [1:0] litedramcore_wrcmdphase;
+reg litedramcore_choose_cmd_want_reads = 1'd0;
+reg litedramcore_choose_cmd_want_writes = 1'd0;
+reg litedramcore_choose_cmd_want_cmds = 1'd0;
+reg litedramcore_choose_cmd_want_activates = 1'd0;
+wire litedramcore_choose_cmd_cmd_valid;
+reg litedramcore_choose_cmd_cmd_ready = 1'd0;
+wire [14:0] litedramcore_choose_cmd_cmd_payload_a;
+wire [2:0] litedramcore_choose_cmd_cmd_payload_ba;
+reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
+reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
+reg litedramcore_choose_cmd_cmd_payload_we = 1'd0;
+wire litedramcore_choose_cmd_cmd_payload_is_cmd;
+wire litedramcore_choose_cmd_cmd_payload_is_read;
+wire litedramcore_choose_cmd_cmd_payload_is_write;
+reg [7:0] litedramcore_choose_cmd_valids = 8'd0;
+wire [7:0] litedramcore_choose_cmd_request;
+reg [2:0] litedramcore_choose_cmd_grant = 3'd0;
+wire litedramcore_choose_cmd_ce;
+reg litedramcore_choose_req_want_reads = 1'd0;
+reg litedramcore_choose_req_want_writes = 1'd0;
+reg litedramcore_choose_req_want_cmds = 1'd0;
+reg litedramcore_choose_req_want_activates = 1'd0;
+wire litedramcore_choose_req_cmd_valid;
+reg litedramcore_choose_req_cmd_ready = 1'd0;
+wire [14:0] litedramcore_choose_req_cmd_payload_a;
+wire [2:0] litedramcore_choose_req_cmd_payload_ba;
+reg litedramcore_choose_req_cmd_payload_cas = 1'd0;
+reg litedramcore_choose_req_cmd_payload_ras = 1'd0;
+reg litedramcore_choose_req_cmd_payload_we = 1'd0;
+wire litedramcore_choose_req_cmd_payload_is_cmd;
+wire litedramcore_choose_req_cmd_payload_is_read;
+wire litedramcore_choose_req_cmd_payload_is_write;
+reg [7:0] litedramcore_choose_req_valids = 8'd0;
+wire [7:0] litedramcore_choose_req_request;
+reg [2:0] litedramcore_choose_req_grant = 3'd0;
+wire litedramcore_choose_req_ce;
+reg [14:0] litedramcore_nop_a = 15'd0;
+reg [2:0] litedramcore_nop_ba = 3'd0;
+reg [1:0] litedramcore_steerer_sel0 = 2'd0;
+reg [1:0] litedramcore_steerer_sel1 = 2'd0;
+reg [1:0] litedramcore_steerer_sel2 = 2'd0;
+reg [1:0] litedramcore_steerer_sel3 = 2'd0;
+reg litedramcore_steerer0 = 1'd1;
+reg litedramcore_steerer1 = 1'd1;
+reg litedramcore_steerer2 = 1'd1;
+reg litedramcore_steerer3 = 1'd1;
+reg litedramcore_steerer4 = 1'd1;
+reg litedramcore_steerer5 = 1'd1;
+reg litedramcore_steerer6 = 1'd1;
+reg litedramcore_steerer7 = 1'd1;
+wire litedramcore_trrdcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_trrdcon_ready = 1'd0;
+reg litedramcore_trrdcon_count = 1'd0;
+wire litedramcore_tfawcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_tfawcon_ready = 1'd1;
+wire [2:0] litedramcore_tfawcon_count;
+reg [4:0] litedramcore_tfawcon_window = 5'd0;
+wire litedramcore_tccdcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_tccdcon_ready = 1'd0;
+reg litedramcore_tccdcon_count = 1'd0;
+wire litedramcore_twtrcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_twtrcon_ready = 1'd0;
+reg [2:0] litedramcore_twtrcon_count = 3'd0;
+wire litedramcore_read_available;
+wire litedramcore_write_available;
+reg litedramcore_en0 = 1'd0;
+wire litedramcore_max_time0;
+reg [4:0] litedramcore_time0 = 5'd0;
+reg litedramcore_en1 = 1'd0;
+wire litedramcore_max_time1;
+reg [3:0] litedramcore_time1 = 4'd0;
+wire litedramcore_go_to_refresh;
+reg init_done_storage = 1'd0;
+reg init_done_re = 1'd0;
+reg init_error_storage = 1'd0;
+reg init_error_re = 1'd0;
+wire [29:0] wb_bus_adr;
+wire [31:0] wb_bus_dat_w;
+wire [31:0] wb_bus_dat_r;
+wire [3:0] wb_bus_sel;
+wire wb_bus_cyc;
+wire wb_bus_stb;
+wire wb_bus_ack;
+wire wb_bus_we;
+wire [2:0] wb_bus_cti;
+wire [1:0] wb_bus_bte;
+wire wb_bus_err;
+wire user_enable;
+wire user_port_cmd_valid;
+wire user_port_cmd_ready;
+wire user_port_cmd_payload_we;
+wire [24:0] user_port_cmd_payload_addr;
+wire user_port_wdata_valid;
+wire user_port_wdata_ready;
+wire [255:0] user_port_wdata_payload_data;
+wire [31:0] user_port_wdata_payload_we;
+wire user_port_rdata_valid;
+wire user_port_rdata_ready;
+wire [255:0] user_port_rdata_payload_data;
+reg [13:0] litedramcore_adr = 14'd0;
+reg litedramcore_we = 1'd0;
+reg [31:0] litedramcore_dat_w = 32'd0;
+wire [31:0] litedramcore_dat_r;
+wire [29:0] litedramcore_wishbone_adr;
+wire [31:0] litedramcore_wishbone_dat_w;
+reg [31:0] litedramcore_wishbone_dat_r = 32'd0;
+wire [3:0] litedramcore_wishbone_sel;
+wire litedramcore_wishbone_cyc;
+wire litedramcore_wishbone_stb;
+reg litedramcore_wishbone_ack = 1'd0;
+wire litedramcore_wishbone_we;
+wire [2:0] litedramcore_wishbone_cti;
+wire [1:0] litedramcore_wishbone_bte;
+reg litedramcore_wishbone_err = 1'd0;
+wire [13:0] interface0_bank_bus_adr;
+wire interface0_bank_bus_we;
+wire [31:0] interface0_bank_bus_dat_w;
+reg [31:0] interface0_bank_bus_dat_r = 32'd0;
+reg csrbank0_init_done0_re = 1'd0;
+wire csrbank0_init_done0_r;
+reg csrbank0_init_done0_we = 1'd0;
+wire csrbank0_init_done0_w;
+reg csrbank0_init_error0_re = 1'd0;
+wire csrbank0_init_error0_r;
+reg csrbank0_init_error0_we = 1'd0;
+wire csrbank0_init_error0_w;
+wire csrbank0_sel;
+wire [13:0] interface1_bank_bus_adr;
+wire interface1_bank_bus_we;
+wire [31:0] interface1_bank_bus_dat_w;
+reg [31:0] interface1_bank_bus_dat_r = 32'd0;
+reg csrbank1_rst0_re = 1'd0;
+wire csrbank1_rst0_r;
+reg csrbank1_rst0_we = 1'd0;
+wire csrbank1_rst0_w;
+reg csrbank1_dly_sel0_re = 1'd0;
+wire [3:0] csrbank1_dly_sel0_r;
+reg csrbank1_dly_sel0_we = 1'd0;
+wire [3:0] csrbank1_dly_sel0_w;
+reg csrbank1_half_sys8x_taps0_re = 1'd0;
+wire [4:0] csrbank1_half_sys8x_taps0_r;
+reg csrbank1_half_sys8x_taps0_we = 1'd0;
+wire [4:0] csrbank1_half_sys8x_taps0_w;
+reg csrbank1_wlevel_en0_re = 1'd0;
+wire csrbank1_wlevel_en0_r;
+reg csrbank1_wlevel_en0_we = 1'd0;
+wire csrbank1_wlevel_en0_w;
+reg csrbank1_rdphase0_re = 1'd0;
+wire [1:0] csrbank1_rdphase0_r;
+reg csrbank1_rdphase0_we = 1'd0;
+wire [1:0] csrbank1_rdphase0_w;
+reg csrbank1_wrphase0_re = 1'd0;
+wire [1:0] csrbank1_wrphase0_r;
+reg csrbank1_wrphase0_we = 1'd0;
+wire [1:0] csrbank1_wrphase0_w;
+wire csrbank1_sel;
+wire [13:0] interface2_bank_bus_adr;
+wire interface2_bank_bus_we;
+wire [31:0] interface2_bank_bus_dat_w;
+reg [31:0] interface2_bank_bus_dat_r = 32'd0;
+reg csrbank2_dfii_control0_re = 1'd0;
+wire [3:0] csrbank2_dfii_control0_r;
+reg csrbank2_dfii_control0_we = 1'd0;
+wire [3:0] csrbank2_dfii_control0_w;
+reg csrbank2_dfii_pi0_command0_re = 1'd0;
+wire [5:0] csrbank2_dfii_pi0_command0_r;
+reg csrbank2_dfii_pi0_command0_we = 1'd0;
+wire [5:0] csrbank2_dfii_pi0_command0_w;
+reg csrbank2_dfii_pi0_address0_re = 1'd0;
+wire [14:0] csrbank2_dfii_pi0_address0_r;
+reg csrbank2_dfii_pi0_address0_we = 1'd0;
+wire [14:0] csrbank2_dfii_pi0_address0_w;
+reg csrbank2_dfii_pi0_baddress0_re = 1'd0;
+wire [2:0] csrbank2_dfii_pi0_baddress0_r;
+reg csrbank2_dfii_pi0_baddress0_we = 1'd0;
+wire [2:0] csrbank2_dfii_pi0_baddress0_w;
+reg csrbank2_dfii_pi0_wrdata1_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_wrdata1_r;
+reg csrbank2_dfii_pi0_wrdata1_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_wrdata1_w;
+reg csrbank2_dfii_pi0_wrdata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_wrdata0_r;
+reg csrbank2_dfii_pi0_wrdata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_wrdata0_w;
+reg csrbank2_dfii_pi0_rddata1_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_rddata1_r;
+reg csrbank2_dfii_pi0_rddata1_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_rddata1_w;
+reg csrbank2_dfii_pi0_rddata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_rddata0_r;
+reg csrbank2_dfii_pi0_rddata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_rddata0_w;
+reg csrbank2_dfii_pi1_command0_re = 1'd0;
+wire [5:0] csrbank2_dfii_pi1_command0_r;
+reg csrbank2_dfii_pi1_command0_we = 1'd0;
+wire [5:0] csrbank2_dfii_pi1_command0_w;
+reg csrbank2_dfii_pi1_address0_re = 1'd0;
+wire [14:0] csrbank2_dfii_pi1_address0_r;
+reg csrbank2_dfii_pi1_address0_we = 1'd0;
+wire [14:0] csrbank2_dfii_pi1_address0_w;
+reg csrbank2_dfii_pi1_baddress0_re = 1'd0;
+wire [2:0] csrbank2_dfii_pi1_baddress0_r;
+reg csrbank2_dfii_pi1_baddress0_we = 1'd0;
+wire [2:0] csrbank2_dfii_pi1_baddress0_w;
+reg csrbank2_dfii_pi1_wrdata1_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_wrdata1_r;
+reg csrbank2_dfii_pi1_wrdata1_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_wrdata1_w;
+reg csrbank2_dfii_pi1_wrdata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_wrdata0_r;
+reg csrbank2_dfii_pi1_wrdata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_wrdata0_w;
+reg csrbank2_dfii_pi1_rddata1_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_rddata1_r;
+reg csrbank2_dfii_pi1_rddata1_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_rddata1_w;
+reg csrbank2_dfii_pi1_rddata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_rddata0_r;
+reg csrbank2_dfii_pi1_rddata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_rddata0_w;
+reg csrbank2_dfii_pi2_command0_re = 1'd0;
+wire [5:0] csrbank2_dfii_pi2_command0_r;
+reg csrbank2_dfii_pi2_command0_we = 1'd0;
+wire [5:0] csrbank2_dfii_pi2_command0_w;
+reg csrbank2_dfii_pi2_address0_re = 1'd0;
+wire [14:0] csrbank2_dfii_pi2_address0_r;
+reg csrbank2_dfii_pi2_address0_we = 1'd0;
+wire [14:0] csrbank2_dfii_pi2_address0_w;
+reg csrbank2_dfii_pi2_baddress0_re = 1'd0;
+wire [2:0] csrbank2_dfii_pi2_baddress0_r;
+reg csrbank2_dfii_pi2_baddress0_we = 1'd0;
+wire [2:0] csrbank2_dfii_pi2_baddress0_w;
+reg csrbank2_dfii_pi2_wrdata1_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_wrdata1_r;
+reg csrbank2_dfii_pi2_wrdata1_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_wrdata1_w;
+reg csrbank2_dfii_pi2_wrdata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_wrdata0_r;
+reg csrbank2_dfii_pi2_wrdata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_wrdata0_w;
+reg csrbank2_dfii_pi2_rddata1_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_rddata1_r;
+reg csrbank2_dfii_pi2_rddata1_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_rddata1_w;
+reg csrbank2_dfii_pi2_rddata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_rddata0_r;
+reg csrbank2_dfii_pi2_rddata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_rddata0_w;
+reg csrbank2_dfii_pi3_command0_re = 1'd0;
+wire [5:0] csrbank2_dfii_pi3_command0_r;
+reg csrbank2_dfii_pi3_command0_we = 1'd0;
+wire [5:0] csrbank2_dfii_pi3_command0_w;
+reg csrbank2_dfii_pi3_address0_re = 1'd0;
+wire [14:0] csrbank2_dfii_pi3_address0_r;
+reg csrbank2_dfii_pi3_address0_we = 1'd0;
+wire [14:0] csrbank2_dfii_pi3_address0_w;
+reg csrbank2_dfii_pi3_baddress0_re = 1'd0;
+wire [2:0] csrbank2_dfii_pi3_baddress0_r;
+reg csrbank2_dfii_pi3_baddress0_we = 1'd0;
+wire [2:0] csrbank2_dfii_pi3_baddress0_w;
+reg csrbank2_dfii_pi3_wrdata1_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_wrdata1_r;
+reg csrbank2_dfii_pi3_wrdata1_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_wrdata1_w;
+reg csrbank2_dfii_pi3_wrdata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_wrdata0_r;
+reg csrbank2_dfii_pi3_wrdata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_wrdata0_w;
+reg csrbank2_dfii_pi3_rddata1_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_rddata1_r;
+reg csrbank2_dfii_pi3_rddata1_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_rddata1_w;
+reg csrbank2_dfii_pi3_rddata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_rddata0_r;
+reg csrbank2_dfii_pi3_rddata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_rddata0_w;
+wire csrbank2_sel;
+wire [13:0] csr_interconnect_adr;
+wire csr_interconnect_we;
+wire [31:0] csr_interconnect_dat_w;
+wire [31:0] csr_interconnect_dat_r;
+wire litedramcore_reset0;
+wire litedramcore_reset1;
+wire litedramcore_reset2;
+wire litedramcore_reset3;
+wire litedramcore_reset4;
+wire litedramcore_reset5;
+wire litedramcore_reset6;
+wire litedramcore_reset7;
+wire litedramcore_pll_fb;
+reg [1:0] litedramcore_refresher_state = 2'd0;
+reg [1:0] litedramcore_refresher_next_state = 2'd0;
+reg [3:0] litedramcore_bankmachine0_state = 4'd0;
+reg [3:0] litedramcore_bankmachine0_next_state = 4'd0;
+reg [3:0] litedramcore_bankmachine1_state = 4'd0;
+reg [3:0] litedramcore_bankmachine1_next_state = 4'd0;
+reg [3:0] litedramcore_bankmachine2_state = 4'd0;
+reg [3:0] litedramcore_bankmachine2_next_state = 4'd0;
+reg [3:0] litedramcore_bankmachine3_state = 4'd0;
+reg [3:0] litedramcore_bankmachine3_next_state = 4'd0;
+reg [3:0] litedramcore_bankmachine4_state = 4'd0;
+reg [3:0] litedramcore_bankmachine4_next_state = 4'd0;
+reg [3:0] litedramcore_bankmachine5_state = 4'd0;
+reg [3:0] litedramcore_bankmachine5_next_state = 4'd0;
+reg [3:0] litedramcore_bankmachine6_state = 4'd0;
+reg [3:0] litedramcore_bankmachine6_next_state = 4'd0;
+reg [3:0] litedramcore_bankmachine7_state = 4'd0;
+reg [3:0] litedramcore_bankmachine7_next_state = 4'd0;
+reg [3:0] litedramcore_multiplexer_state = 4'd0;
+reg [3:0] litedramcore_multiplexer_next_state = 4'd0;
+wire litedramcore_roundrobin0_request;
+wire litedramcore_roundrobin0_grant;
+wire litedramcore_roundrobin0_ce;
+wire litedramcore_roundrobin1_request;
+wire litedramcore_roundrobin1_grant;
+wire litedramcore_roundrobin1_ce;
+wire litedramcore_roundrobin2_request;
+wire litedramcore_roundrobin2_grant;
+wire litedramcore_roundrobin2_ce;
+wire litedramcore_roundrobin3_request;
+wire litedramcore_roundrobin3_grant;
+wire litedramcore_roundrobin3_ce;
+wire litedramcore_roundrobin4_request;
+wire litedramcore_roundrobin4_grant;
+wire litedramcore_roundrobin4_ce;
+wire litedramcore_roundrobin5_request;
+wire litedramcore_roundrobin5_grant;
+wire litedramcore_roundrobin5_ce;
+wire litedramcore_roundrobin6_request;
+wire litedramcore_roundrobin6_grant;
+wire litedramcore_roundrobin6_ce;
+wire litedramcore_roundrobin7_request;
+wire litedramcore_roundrobin7_grant;
+wire litedramcore_roundrobin7_ce;
+reg litedramcore_locked0 = 1'd0;
+reg litedramcore_locked1 = 1'd0;
+reg litedramcore_locked2 = 1'd0;
+reg litedramcore_locked3 = 1'd0;
+reg litedramcore_locked4 = 1'd0;
+reg litedramcore_locked5 = 1'd0;
+reg litedramcore_locked6 = 1'd0;
+reg litedramcore_locked7 = 1'd0;
+reg litedramcore_new_master_wdata_ready0 = 1'd0;
+reg litedramcore_new_master_wdata_ready1 = 1'd0;
+reg litedramcore_new_master_rdata_valid0 = 1'd0;
+reg litedramcore_new_master_rdata_valid1 = 1'd0;
+reg litedramcore_new_master_rdata_valid2 = 1'd0;
+reg litedramcore_new_master_rdata_valid3 = 1'd0;
+reg litedramcore_new_master_rdata_valid4 = 1'd0;
+reg litedramcore_new_master_rdata_valid5 = 1'd0;
+reg litedramcore_new_master_rdata_valid6 = 1'd0;
+reg litedramcore_new_master_rdata_valid7 = 1'd0;
+reg litedramcore_new_master_rdata_valid8 = 1'd0;
+reg [1:0] litedramcore_state = 2'd0;
+reg [1:0] litedramcore_next_state = 2'd0;
+reg [31:0] litedramcore_dat_w_next_value0 = 32'd0;
+reg litedramcore_dat_w_next_value_ce0 = 1'd0;
+reg [13:0] litedramcore_adr_next_value1 = 14'd0;
+reg litedramcore_adr_next_value_ce1 = 1'd0;
+reg litedramcore_we_next_value2 = 1'd0;
+reg litedramcore_we_next_value_ce2 = 1'd0;
+reg rhs_array_muxed0 = 1'd0;
+reg [14:0] rhs_array_muxed1 = 15'd0;
+reg [2:0] rhs_array_muxed2 = 3'd0;
+reg rhs_array_muxed3 = 1'd0;
+reg rhs_array_muxed4 = 1'd0;
+reg rhs_array_muxed5 = 1'd0;
+reg t_array_muxed0 = 1'd0;
+reg t_array_muxed1 = 1'd0;
+reg t_array_muxed2 = 1'd0;
+reg rhs_array_muxed6 = 1'd0;
+reg [14:0] rhs_array_muxed7 = 15'd0;
+reg [2:0] rhs_array_muxed8 = 3'd0;
+reg rhs_array_muxed9 = 1'd0;
+reg rhs_array_muxed10 = 1'd0;
+reg rhs_array_muxed11 = 1'd0;
+reg t_array_muxed3 = 1'd0;
+reg t_array_muxed4 = 1'd0;
+reg t_array_muxed5 = 1'd0;
+reg [21:0] rhs_array_muxed12 = 22'd0;
+reg rhs_array_muxed13 = 1'd0;
+reg rhs_array_muxed14 = 1'd0;
+reg [21:0] rhs_array_muxed15 = 22'd0;
+reg rhs_array_muxed16 = 1'd0;
+reg rhs_array_muxed17 = 1'd0;
+reg [21:0] rhs_array_muxed18 = 22'd0;
+reg rhs_array_muxed19 = 1'd0;
+reg rhs_array_muxed20 = 1'd0;
+reg [21:0] rhs_array_muxed21 = 22'd0;
+reg rhs_array_muxed22 = 1'd0;
+reg rhs_array_muxed23 = 1'd0;
+reg [21:0] rhs_array_muxed24 = 22'd0;
+reg rhs_array_muxed25 = 1'd0;
+reg rhs_array_muxed26 = 1'd0;
+reg [21:0] rhs_array_muxed27 = 22'd0;
+reg rhs_array_muxed28 = 1'd0;
+reg rhs_array_muxed29 = 1'd0;
+reg [21:0] rhs_array_muxed30 = 22'd0;
+reg rhs_array_muxed31 = 1'd0;
+reg rhs_array_muxed32 = 1'd0;
+reg [21:0] rhs_array_muxed33 = 22'd0;
+reg rhs_array_muxed34 = 1'd0;
+reg rhs_array_muxed35 = 1'd0;
+reg [2:0] array_muxed0 = 3'd0;
+reg [14:0] array_muxed1 = 15'd0;
+reg array_muxed2 = 1'd0;
+reg array_muxed3 = 1'd0;
+reg array_muxed4 = 1'd0;
+reg array_muxed5 = 1'd0;
+reg array_muxed6 = 1'd0;
+reg [2:0] array_muxed7 = 3'd0;
+reg [14:0] array_muxed8 = 15'd0;
+reg array_muxed9 = 1'd0;
+reg array_muxed10 = 1'd0;
+reg array_muxed11 = 1'd0;
+reg array_muxed12 = 1'd0;
+reg array_muxed13 = 1'd0;
+reg [2:0] array_muxed14 = 3'd0;
+reg [14:0] array_muxed15 = 15'd0;
+reg array_muxed16 = 1'd0;
+reg array_muxed17 = 1'd0;
+reg array_muxed18 = 1'd0;
+reg array_muxed19 = 1'd0;
+reg array_muxed20 = 1'd0;
+reg [2:0] array_muxed21 = 3'd0;
+reg [14:0] array_muxed22 = 15'd0;
+reg array_muxed23 = 1'd0;
+reg array_muxed24 = 1'd0;
+reg array_muxed25 = 1'd0;
+reg array_muxed26 = 1'd0;
+reg array_muxed27 = 1'd0;
+wire xilinxasyncresetsynchronizerimpl0;
+wire xilinxasyncresetsynchronizerimpl0_rst_meta;
+wire xilinxasyncresetsynchronizerimpl1;
+wire xilinxasyncresetsynchronizerimpl1_rst_meta;
+wire xilinxasyncresetsynchronizerimpl2;
+wire xilinxasyncresetsynchronizerimpl2_rst_meta;
+wire xilinxasyncresetsynchronizerimpl2_expr;
+wire xilinxasyncresetsynchronizerimpl3;
+wire xilinxasyncresetsynchronizerimpl3_rst_meta;
+wire xilinxasyncresetsynchronizerimpl3_expr;
//------------------------------------------------------------------------------
// Combinatorial Logic
assign k7ddrphy_dqs_oe_delay_tappeddelayline = ((k7ddrphy_dqs_preamble | k7ddrphy_dqs_oe) | k7ddrphy_dqs_postamble);
assign k7ddrphy_dq_oe_delay_tappeddelayline = ((k7ddrphy_dqs_preamble | k7ddrphy_dq_oe) | k7ddrphy_dqs_postamble);
always @(*) begin
- k7ddrphy_dfi_p0_rddata <= 64'd0;
- k7ddrphy_dfi_p0_rddata[0] <= k7ddrphy_bitslip04[0];
- k7ddrphy_dfi_p0_rddata[32] <= k7ddrphy_bitslip04[1];
- k7ddrphy_dfi_p0_rddata[1] <= k7ddrphy_bitslip14[0];
- k7ddrphy_dfi_p0_rddata[33] <= k7ddrphy_bitslip14[1];
- k7ddrphy_dfi_p0_rddata[2] <= k7ddrphy_bitslip24[0];
- k7ddrphy_dfi_p0_rddata[34] <= k7ddrphy_bitslip24[1];
- k7ddrphy_dfi_p0_rddata[3] <= k7ddrphy_bitslip34[0];
- k7ddrphy_dfi_p0_rddata[35] <= k7ddrphy_bitslip34[1];
- k7ddrphy_dfi_p0_rddata[4] <= k7ddrphy_bitslip42[0];
- k7ddrphy_dfi_p0_rddata[36] <= k7ddrphy_bitslip42[1];
- k7ddrphy_dfi_p0_rddata[5] <= k7ddrphy_bitslip52[0];
- k7ddrphy_dfi_p0_rddata[37] <= k7ddrphy_bitslip52[1];
- k7ddrphy_dfi_p0_rddata[6] <= k7ddrphy_bitslip62[0];
- k7ddrphy_dfi_p0_rddata[38] <= k7ddrphy_bitslip62[1];
- k7ddrphy_dfi_p0_rddata[7] <= k7ddrphy_bitslip72[0];
- k7ddrphy_dfi_p0_rddata[39] <= k7ddrphy_bitslip72[1];
- k7ddrphy_dfi_p0_rddata[8] <= k7ddrphy_bitslip82[0];
- k7ddrphy_dfi_p0_rddata[40] <= k7ddrphy_bitslip82[1];
- k7ddrphy_dfi_p0_rddata[9] <= k7ddrphy_bitslip92[0];
- k7ddrphy_dfi_p0_rddata[41] <= k7ddrphy_bitslip92[1];
- k7ddrphy_dfi_p0_rddata[10] <= k7ddrphy_bitslip102[0];
- k7ddrphy_dfi_p0_rddata[42] <= k7ddrphy_bitslip102[1];
- k7ddrphy_dfi_p0_rddata[11] <= k7ddrphy_bitslip112[0];
- k7ddrphy_dfi_p0_rddata[43] <= k7ddrphy_bitslip112[1];
- k7ddrphy_dfi_p0_rddata[12] <= k7ddrphy_bitslip122[0];
- k7ddrphy_dfi_p0_rddata[44] <= k7ddrphy_bitslip122[1];
- k7ddrphy_dfi_p0_rddata[13] <= k7ddrphy_bitslip132[0];
- k7ddrphy_dfi_p0_rddata[45] <= k7ddrphy_bitslip132[1];
- k7ddrphy_dfi_p0_rddata[14] <= k7ddrphy_bitslip142[0];
- k7ddrphy_dfi_p0_rddata[46] <= k7ddrphy_bitslip142[1];
- k7ddrphy_dfi_p0_rddata[15] <= k7ddrphy_bitslip152[0];
- k7ddrphy_dfi_p0_rddata[47] <= k7ddrphy_bitslip152[1];
- k7ddrphy_dfi_p0_rddata[16] <= k7ddrphy_bitslip162[0];
- k7ddrphy_dfi_p0_rddata[48] <= k7ddrphy_bitslip162[1];
- k7ddrphy_dfi_p0_rddata[17] <= k7ddrphy_bitslip172[0];
- k7ddrphy_dfi_p0_rddata[49] <= k7ddrphy_bitslip172[1];
- k7ddrphy_dfi_p0_rddata[18] <= k7ddrphy_bitslip182[0];
- k7ddrphy_dfi_p0_rddata[50] <= k7ddrphy_bitslip182[1];
- k7ddrphy_dfi_p0_rddata[19] <= k7ddrphy_bitslip192[0];
- k7ddrphy_dfi_p0_rddata[51] <= k7ddrphy_bitslip192[1];
- k7ddrphy_dfi_p0_rddata[20] <= k7ddrphy_bitslip202[0];
- k7ddrphy_dfi_p0_rddata[52] <= k7ddrphy_bitslip202[1];
- k7ddrphy_dfi_p0_rddata[21] <= k7ddrphy_bitslip212[0];
- k7ddrphy_dfi_p0_rddata[53] <= k7ddrphy_bitslip212[1];
- k7ddrphy_dfi_p0_rddata[22] <= k7ddrphy_bitslip222[0];
- k7ddrphy_dfi_p0_rddata[54] <= k7ddrphy_bitslip222[1];
- k7ddrphy_dfi_p0_rddata[23] <= k7ddrphy_bitslip232[0];
- k7ddrphy_dfi_p0_rddata[55] <= k7ddrphy_bitslip232[1];
- k7ddrphy_dfi_p0_rddata[24] <= k7ddrphy_bitslip242[0];
- k7ddrphy_dfi_p0_rddata[56] <= k7ddrphy_bitslip242[1];
- k7ddrphy_dfi_p0_rddata[25] <= k7ddrphy_bitslip252[0];
- k7ddrphy_dfi_p0_rddata[57] <= k7ddrphy_bitslip252[1];
- k7ddrphy_dfi_p0_rddata[26] <= k7ddrphy_bitslip262[0];
- k7ddrphy_dfi_p0_rddata[58] <= k7ddrphy_bitslip262[1];
- k7ddrphy_dfi_p0_rddata[27] <= k7ddrphy_bitslip272[0];
- k7ddrphy_dfi_p0_rddata[59] <= k7ddrphy_bitslip272[1];
- k7ddrphy_dfi_p0_rddata[28] <= k7ddrphy_bitslip282[0];
- k7ddrphy_dfi_p0_rddata[60] <= k7ddrphy_bitslip282[1];
- k7ddrphy_dfi_p0_rddata[29] <= k7ddrphy_bitslip292[0];
- k7ddrphy_dfi_p0_rddata[61] <= k7ddrphy_bitslip292[1];
- k7ddrphy_dfi_p0_rddata[30] <= k7ddrphy_bitslip302[0];
- k7ddrphy_dfi_p0_rddata[62] <= k7ddrphy_bitslip302[1];
- k7ddrphy_dfi_p0_rddata[31] <= k7ddrphy_bitslip312[0];
- k7ddrphy_dfi_p0_rddata[63] <= k7ddrphy_bitslip312[1];
-end
-always @(*) begin
- k7ddrphy_dfi_p1_rddata <= 64'd0;
- k7ddrphy_dfi_p1_rddata[0] <= k7ddrphy_bitslip04[2];
- k7ddrphy_dfi_p1_rddata[32] <= k7ddrphy_bitslip04[3];
- k7ddrphy_dfi_p1_rddata[1] <= k7ddrphy_bitslip14[2];
- k7ddrphy_dfi_p1_rddata[33] <= k7ddrphy_bitslip14[3];
- k7ddrphy_dfi_p1_rddata[2] <= k7ddrphy_bitslip24[2];
- k7ddrphy_dfi_p1_rddata[34] <= k7ddrphy_bitslip24[3];
- k7ddrphy_dfi_p1_rddata[3] <= k7ddrphy_bitslip34[2];
- k7ddrphy_dfi_p1_rddata[35] <= k7ddrphy_bitslip34[3];
- k7ddrphy_dfi_p1_rddata[4] <= k7ddrphy_bitslip42[2];
- k7ddrphy_dfi_p1_rddata[36] <= k7ddrphy_bitslip42[3];
- k7ddrphy_dfi_p1_rddata[5] <= k7ddrphy_bitslip52[2];
- k7ddrphy_dfi_p1_rddata[37] <= k7ddrphy_bitslip52[3];
- k7ddrphy_dfi_p1_rddata[6] <= k7ddrphy_bitslip62[2];
- k7ddrphy_dfi_p1_rddata[38] <= k7ddrphy_bitslip62[3];
- k7ddrphy_dfi_p1_rddata[7] <= k7ddrphy_bitslip72[2];
- k7ddrphy_dfi_p1_rddata[39] <= k7ddrphy_bitslip72[3];
- k7ddrphy_dfi_p1_rddata[8] <= k7ddrphy_bitslip82[2];
- k7ddrphy_dfi_p1_rddata[40] <= k7ddrphy_bitslip82[3];
- k7ddrphy_dfi_p1_rddata[9] <= k7ddrphy_bitslip92[2];
- k7ddrphy_dfi_p1_rddata[41] <= k7ddrphy_bitslip92[3];
- k7ddrphy_dfi_p1_rddata[10] <= k7ddrphy_bitslip102[2];
- k7ddrphy_dfi_p1_rddata[42] <= k7ddrphy_bitslip102[3];
- k7ddrphy_dfi_p1_rddata[11] <= k7ddrphy_bitslip112[2];
- k7ddrphy_dfi_p1_rddata[43] <= k7ddrphy_bitslip112[3];
- k7ddrphy_dfi_p1_rddata[12] <= k7ddrphy_bitslip122[2];
- k7ddrphy_dfi_p1_rddata[44] <= k7ddrphy_bitslip122[3];
- k7ddrphy_dfi_p1_rddata[13] <= k7ddrphy_bitslip132[2];
- k7ddrphy_dfi_p1_rddata[45] <= k7ddrphy_bitslip132[3];
- k7ddrphy_dfi_p1_rddata[14] <= k7ddrphy_bitslip142[2];
- k7ddrphy_dfi_p1_rddata[46] <= k7ddrphy_bitslip142[3];
- k7ddrphy_dfi_p1_rddata[15] <= k7ddrphy_bitslip152[2];
- k7ddrphy_dfi_p1_rddata[47] <= k7ddrphy_bitslip152[3];
- k7ddrphy_dfi_p1_rddata[16] <= k7ddrphy_bitslip162[2];
- k7ddrphy_dfi_p1_rddata[48] <= k7ddrphy_bitslip162[3];
- k7ddrphy_dfi_p1_rddata[17] <= k7ddrphy_bitslip172[2];
- k7ddrphy_dfi_p1_rddata[49] <= k7ddrphy_bitslip172[3];
- k7ddrphy_dfi_p1_rddata[18] <= k7ddrphy_bitslip182[2];
- k7ddrphy_dfi_p1_rddata[50] <= k7ddrphy_bitslip182[3];
- k7ddrphy_dfi_p1_rddata[19] <= k7ddrphy_bitslip192[2];
- k7ddrphy_dfi_p1_rddata[51] <= k7ddrphy_bitslip192[3];
- k7ddrphy_dfi_p1_rddata[20] <= k7ddrphy_bitslip202[2];
- k7ddrphy_dfi_p1_rddata[52] <= k7ddrphy_bitslip202[3];
- k7ddrphy_dfi_p1_rddata[21] <= k7ddrphy_bitslip212[2];
- k7ddrphy_dfi_p1_rddata[53] <= k7ddrphy_bitslip212[3];
- k7ddrphy_dfi_p1_rddata[22] <= k7ddrphy_bitslip222[2];
- k7ddrphy_dfi_p1_rddata[54] <= k7ddrphy_bitslip222[3];
- k7ddrphy_dfi_p1_rddata[23] <= k7ddrphy_bitslip232[2];
- k7ddrphy_dfi_p1_rddata[55] <= k7ddrphy_bitslip232[3];
- k7ddrphy_dfi_p1_rddata[24] <= k7ddrphy_bitslip242[2];
- k7ddrphy_dfi_p1_rddata[56] <= k7ddrphy_bitslip242[3];
- k7ddrphy_dfi_p1_rddata[25] <= k7ddrphy_bitslip252[2];
- k7ddrphy_dfi_p1_rddata[57] <= k7ddrphy_bitslip252[3];
- k7ddrphy_dfi_p1_rddata[26] <= k7ddrphy_bitslip262[2];
- k7ddrphy_dfi_p1_rddata[58] <= k7ddrphy_bitslip262[3];
- k7ddrphy_dfi_p1_rddata[27] <= k7ddrphy_bitslip272[2];
- k7ddrphy_dfi_p1_rddata[59] <= k7ddrphy_bitslip272[3];
- k7ddrphy_dfi_p1_rddata[28] <= k7ddrphy_bitslip282[2];
- k7ddrphy_dfi_p1_rddata[60] <= k7ddrphy_bitslip282[3];
- k7ddrphy_dfi_p1_rddata[29] <= k7ddrphy_bitslip292[2];
- k7ddrphy_dfi_p1_rddata[61] <= k7ddrphy_bitslip292[3];
- k7ddrphy_dfi_p1_rddata[30] <= k7ddrphy_bitslip302[2];
- k7ddrphy_dfi_p1_rddata[62] <= k7ddrphy_bitslip302[3];
- k7ddrphy_dfi_p1_rddata[31] <= k7ddrphy_bitslip312[2];
- k7ddrphy_dfi_p1_rddata[63] <= k7ddrphy_bitslip312[3];
-end
-always @(*) begin
- k7ddrphy_dfi_p2_rddata <= 64'd0;
- k7ddrphy_dfi_p2_rddata[0] <= k7ddrphy_bitslip04[4];
- k7ddrphy_dfi_p2_rddata[32] <= k7ddrphy_bitslip04[5];
- k7ddrphy_dfi_p2_rddata[1] <= k7ddrphy_bitslip14[4];
- k7ddrphy_dfi_p2_rddata[33] <= k7ddrphy_bitslip14[5];
- k7ddrphy_dfi_p2_rddata[2] <= k7ddrphy_bitslip24[4];
- k7ddrphy_dfi_p2_rddata[34] <= k7ddrphy_bitslip24[5];
- k7ddrphy_dfi_p2_rddata[3] <= k7ddrphy_bitslip34[4];
- k7ddrphy_dfi_p2_rddata[35] <= k7ddrphy_bitslip34[5];
- k7ddrphy_dfi_p2_rddata[4] <= k7ddrphy_bitslip42[4];
- k7ddrphy_dfi_p2_rddata[36] <= k7ddrphy_bitslip42[5];
- k7ddrphy_dfi_p2_rddata[5] <= k7ddrphy_bitslip52[4];
- k7ddrphy_dfi_p2_rddata[37] <= k7ddrphy_bitslip52[5];
- k7ddrphy_dfi_p2_rddata[6] <= k7ddrphy_bitslip62[4];
- k7ddrphy_dfi_p2_rddata[38] <= k7ddrphy_bitslip62[5];
- k7ddrphy_dfi_p2_rddata[7] <= k7ddrphy_bitslip72[4];
- k7ddrphy_dfi_p2_rddata[39] <= k7ddrphy_bitslip72[5];
- k7ddrphy_dfi_p2_rddata[8] <= k7ddrphy_bitslip82[4];
- k7ddrphy_dfi_p2_rddata[40] <= k7ddrphy_bitslip82[5];
- k7ddrphy_dfi_p2_rddata[9] <= k7ddrphy_bitslip92[4];
- k7ddrphy_dfi_p2_rddata[41] <= k7ddrphy_bitslip92[5];
- k7ddrphy_dfi_p2_rddata[10] <= k7ddrphy_bitslip102[4];
- k7ddrphy_dfi_p2_rddata[42] <= k7ddrphy_bitslip102[5];
- k7ddrphy_dfi_p2_rddata[11] <= k7ddrphy_bitslip112[4];
- k7ddrphy_dfi_p2_rddata[43] <= k7ddrphy_bitslip112[5];
- k7ddrphy_dfi_p2_rddata[12] <= k7ddrphy_bitslip122[4];
- k7ddrphy_dfi_p2_rddata[44] <= k7ddrphy_bitslip122[5];
- k7ddrphy_dfi_p2_rddata[13] <= k7ddrphy_bitslip132[4];
- k7ddrphy_dfi_p2_rddata[45] <= k7ddrphy_bitslip132[5];
- k7ddrphy_dfi_p2_rddata[14] <= k7ddrphy_bitslip142[4];
- k7ddrphy_dfi_p2_rddata[46] <= k7ddrphy_bitslip142[5];
- k7ddrphy_dfi_p2_rddata[15] <= k7ddrphy_bitslip152[4];
- k7ddrphy_dfi_p2_rddata[47] <= k7ddrphy_bitslip152[5];
- k7ddrphy_dfi_p2_rddata[16] <= k7ddrphy_bitslip162[4];
- k7ddrphy_dfi_p2_rddata[48] <= k7ddrphy_bitslip162[5];
- k7ddrphy_dfi_p2_rddata[17] <= k7ddrphy_bitslip172[4];
- k7ddrphy_dfi_p2_rddata[49] <= k7ddrphy_bitslip172[5];
- k7ddrphy_dfi_p2_rddata[18] <= k7ddrphy_bitslip182[4];
- k7ddrphy_dfi_p2_rddata[50] <= k7ddrphy_bitslip182[5];
- k7ddrphy_dfi_p2_rddata[19] <= k7ddrphy_bitslip192[4];
- k7ddrphy_dfi_p2_rddata[51] <= k7ddrphy_bitslip192[5];
- k7ddrphy_dfi_p2_rddata[20] <= k7ddrphy_bitslip202[4];
- k7ddrphy_dfi_p2_rddata[52] <= k7ddrphy_bitslip202[5];
- k7ddrphy_dfi_p2_rddata[21] <= k7ddrphy_bitslip212[4];
- k7ddrphy_dfi_p2_rddata[53] <= k7ddrphy_bitslip212[5];
- k7ddrphy_dfi_p2_rddata[22] <= k7ddrphy_bitslip222[4];
- k7ddrphy_dfi_p2_rddata[54] <= k7ddrphy_bitslip222[5];
- k7ddrphy_dfi_p2_rddata[23] <= k7ddrphy_bitslip232[4];
- k7ddrphy_dfi_p2_rddata[55] <= k7ddrphy_bitslip232[5];
- k7ddrphy_dfi_p2_rddata[24] <= k7ddrphy_bitslip242[4];
- k7ddrphy_dfi_p2_rddata[56] <= k7ddrphy_bitslip242[5];
- k7ddrphy_dfi_p2_rddata[25] <= k7ddrphy_bitslip252[4];
- k7ddrphy_dfi_p2_rddata[57] <= k7ddrphy_bitslip252[5];
- k7ddrphy_dfi_p2_rddata[26] <= k7ddrphy_bitslip262[4];
- k7ddrphy_dfi_p2_rddata[58] <= k7ddrphy_bitslip262[5];
- k7ddrphy_dfi_p2_rddata[27] <= k7ddrphy_bitslip272[4];
- k7ddrphy_dfi_p2_rddata[59] <= k7ddrphy_bitslip272[5];
- k7ddrphy_dfi_p2_rddata[28] <= k7ddrphy_bitslip282[4];
- k7ddrphy_dfi_p2_rddata[60] <= k7ddrphy_bitslip282[5];
- k7ddrphy_dfi_p2_rddata[29] <= k7ddrphy_bitslip292[4];
- k7ddrphy_dfi_p2_rddata[61] <= k7ddrphy_bitslip292[5];
- k7ddrphy_dfi_p2_rddata[30] <= k7ddrphy_bitslip302[4];
- k7ddrphy_dfi_p2_rddata[62] <= k7ddrphy_bitslip302[5];
- k7ddrphy_dfi_p2_rddata[31] <= k7ddrphy_bitslip312[4];
- k7ddrphy_dfi_p2_rddata[63] <= k7ddrphy_bitslip312[5];
-end
-always @(*) begin
- k7ddrphy_dfi_p3_rddata <= 64'd0;
- k7ddrphy_dfi_p3_rddata[0] <= k7ddrphy_bitslip04[6];
- k7ddrphy_dfi_p3_rddata[32] <= k7ddrphy_bitslip04[7];
- k7ddrphy_dfi_p3_rddata[1] <= k7ddrphy_bitslip14[6];
- k7ddrphy_dfi_p3_rddata[33] <= k7ddrphy_bitslip14[7];
- k7ddrphy_dfi_p3_rddata[2] <= k7ddrphy_bitslip24[6];
- k7ddrphy_dfi_p3_rddata[34] <= k7ddrphy_bitslip24[7];
- k7ddrphy_dfi_p3_rddata[3] <= k7ddrphy_bitslip34[6];
- k7ddrphy_dfi_p3_rddata[35] <= k7ddrphy_bitslip34[7];
- k7ddrphy_dfi_p3_rddata[4] <= k7ddrphy_bitslip42[6];
- k7ddrphy_dfi_p3_rddata[36] <= k7ddrphy_bitslip42[7];
- k7ddrphy_dfi_p3_rddata[5] <= k7ddrphy_bitslip52[6];
- k7ddrphy_dfi_p3_rddata[37] <= k7ddrphy_bitslip52[7];
- k7ddrphy_dfi_p3_rddata[6] <= k7ddrphy_bitslip62[6];
- k7ddrphy_dfi_p3_rddata[38] <= k7ddrphy_bitslip62[7];
- k7ddrphy_dfi_p3_rddata[7] <= k7ddrphy_bitslip72[6];
- k7ddrphy_dfi_p3_rddata[39] <= k7ddrphy_bitslip72[7];
- k7ddrphy_dfi_p3_rddata[8] <= k7ddrphy_bitslip82[6];
- k7ddrphy_dfi_p3_rddata[40] <= k7ddrphy_bitslip82[7];
- k7ddrphy_dfi_p3_rddata[9] <= k7ddrphy_bitslip92[6];
- k7ddrphy_dfi_p3_rddata[41] <= k7ddrphy_bitslip92[7];
- k7ddrphy_dfi_p3_rddata[10] <= k7ddrphy_bitslip102[6];
- k7ddrphy_dfi_p3_rddata[42] <= k7ddrphy_bitslip102[7];
- k7ddrphy_dfi_p3_rddata[11] <= k7ddrphy_bitslip112[6];
- k7ddrphy_dfi_p3_rddata[43] <= k7ddrphy_bitslip112[7];
- k7ddrphy_dfi_p3_rddata[12] <= k7ddrphy_bitslip122[6];
- k7ddrphy_dfi_p3_rddata[44] <= k7ddrphy_bitslip122[7];
- k7ddrphy_dfi_p3_rddata[13] <= k7ddrphy_bitslip132[6];
- k7ddrphy_dfi_p3_rddata[45] <= k7ddrphy_bitslip132[7];
- k7ddrphy_dfi_p3_rddata[14] <= k7ddrphy_bitslip142[6];
- k7ddrphy_dfi_p3_rddata[46] <= k7ddrphy_bitslip142[7];
- k7ddrphy_dfi_p3_rddata[15] <= k7ddrphy_bitslip152[6];
- k7ddrphy_dfi_p3_rddata[47] <= k7ddrphy_bitslip152[7];
- k7ddrphy_dfi_p3_rddata[16] <= k7ddrphy_bitslip162[6];
- k7ddrphy_dfi_p3_rddata[48] <= k7ddrphy_bitslip162[7];
- k7ddrphy_dfi_p3_rddata[17] <= k7ddrphy_bitslip172[6];
- k7ddrphy_dfi_p3_rddata[49] <= k7ddrphy_bitslip172[7];
- k7ddrphy_dfi_p3_rddata[18] <= k7ddrphy_bitslip182[6];
- k7ddrphy_dfi_p3_rddata[50] <= k7ddrphy_bitslip182[7];
- k7ddrphy_dfi_p3_rddata[19] <= k7ddrphy_bitslip192[6];
- k7ddrphy_dfi_p3_rddata[51] <= k7ddrphy_bitslip192[7];
- k7ddrphy_dfi_p3_rddata[20] <= k7ddrphy_bitslip202[6];
- k7ddrphy_dfi_p3_rddata[52] <= k7ddrphy_bitslip202[7];
- k7ddrphy_dfi_p3_rddata[21] <= k7ddrphy_bitslip212[6];
- k7ddrphy_dfi_p3_rddata[53] <= k7ddrphy_bitslip212[7];
- k7ddrphy_dfi_p3_rddata[22] <= k7ddrphy_bitslip222[6];
- k7ddrphy_dfi_p3_rddata[54] <= k7ddrphy_bitslip222[7];
- k7ddrphy_dfi_p3_rddata[23] <= k7ddrphy_bitslip232[6];
- k7ddrphy_dfi_p3_rddata[55] <= k7ddrphy_bitslip232[7];
- k7ddrphy_dfi_p3_rddata[24] <= k7ddrphy_bitslip242[6];
- k7ddrphy_dfi_p3_rddata[56] <= k7ddrphy_bitslip242[7];
- k7ddrphy_dfi_p3_rddata[25] <= k7ddrphy_bitslip252[6];
- k7ddrphy_dfi_p3_rddata[57] <= k7ddrphy_bitslip252[7];
- k7ddrphy_dfi_p3_rddata[26] <= k7ddrphy_bitslip262[6];
- k7ddrphy_dfi_p3_rddata[58] <= k7ddrphy_bitslip262[7];
- k7ddrphy_dfi_p3_rddata[27] <= k7ddrphy_bitslip272[6];
- k7ddrphy_dfi_p3_rddata[59] <= k7ddrphy_bitslip272[7];
- k7ddrphy_dfi_p3_rddata[28] <= k7ddrphy_bitslip282[6];
- k7ddrphy_dfi_p3_rddata[60] <= k7ddrphy_bitslip282[7];
- k7ddrphy_dfi_p3_rddata[29] <= k7ddrphy_bitslip292[6];
- k7ddrphy_dfi_p3_rddata[61] <= k7ddrphy_bitslip292[7];
- k7ddrphy_dfi_p3_rddata[30] <= k7ddrphy_bitslip302[6];
- k7ddrphy_dfi_p3_rddata[62] <= k7ddrphy_bitslip302[7];
- k7ddrphy_dfi_p3_rddata[31] <= k7ddrphy_bitslip312[6];
- k7ddrphy_dfi_p3_rddata[63] <= k7ddrphy_bitslip312[7];
+ k7ddrphy_dfi_p0_rddata <= 64'd0;
+ k7ddrphy_dfi_p0_rddata[0] <= k7ddrphy_bitslip04[0];
+ k7ddrphy_dfi_p0_rddata[32] <= k7ddrphy_bitslip04[1];
+ k7ddrphy_dfi_p0_rddata[1] <= k7ddrphy_bitslip14[0];
+ k7ddrphy_dfi_p0_rddata[33] <= k7ddrphy_bitslip14[1];
+ k7ddrphy_dfi_p0_rddata[2] <= k7ddrphy_bitslip24[0];
+ k7ddrphy_dfi_p0_rddata[34] <= k7ddrphy_bitslip24[1];
+ k7ddrphy_dfi_p0_rddata[3] <= k7ddrphy_bitslip34[0];
+ k7ddrphy_dfi_p0_rddata[35] <= k7ddrphy_bitslip34[1];
+ k7ddrphy_dfi_p0_rddata[4] <= k7ddrphy_bitslip42[0];
+ k7ddrphy_dfi_p0_rddata[36] <= k7ddrphy_bitslip42[1];
+ k7ddrphy_dfi_p0_rddata[5] <= k7ddrphy_bitslip52[0];
+ k7ddrphy_dfi_p0_rddata[37] <= k7ddrphy_bitslip52[1];
+ k7ddrphy_dfi_p0_rddata[6] <= k7ddrphy_bitslip62[0];
+ k7ddrphy_dfi_p0_rddata[38] <= k7ddrphy_bitslip62[1];
+ k7ddrphy_dfi_p0_rddata[7] <= k7ddrphy_bitslip72[0];
+ k7ddrphy_dfi_p0_rddata[39] <= k7ddrphy_bitslip72[1];
+ k7ddrphy_dfi_p0_rddata[8] <= k7ddrphy_bitslip82[0];
+ k7ddrphy_dfi_p0_rddata[40] <= k7ddrphy_bitslip82[1];
+ k7ddrphy_dfi_p0_rddata[9] <= k7ddrphy_bitslip92[0];
+ k7ddrphy_dfi_p0_rddata[41] <= k7ddrphy_bitslip92[1];
+ k7ddrphy_dfi_p0_rddata[10] <= k7ddrphy_bitslip102[0];
+ k7ddrphy_dfi_p0_rddata[42] <= k7ddrphy_bitslip102[1];
+ k7ddrphy_dfi_p0_rddata[11] <= k7ddrphy_bitslip112[0];
+ k7ddrphy_dfi_p0_rddata[43] <= k7ddrphy_bitslip112[1];
+ k7ddrphy_dfi_p0_rddata[12] <= k7ddrphy_bitslip122[0];
+ k7ddrphy_dfi_p0_rddata[44] <= k7ddrphy_bitslip122[1];
+ k7ddrphy_dfi_p0_rddata[13] <= k7ddrphy_bitslip132[0];
+ k7ddrphy_dfi_p0_rddata[45] <= k7ddrphy_bitslip132[1];
+ k7ddrphy_dfi_p0_rddata[14] <= k7ddrphy_bitslip142[0];
+ k7ddrphy_dfi_p0_rddata[46] <= k7ddrphy_bitslip142[1];
+ k7ddrphy_dfi_p0_rddata[15] <= k7ddrphy_bitslip152[0];
+ k7ddrphy_dfi_p0_rddata[47] <= k7ddrphy_bitslip152[1];
+ k7ddrphy_dfi_p0_rddata[16] <= k7ddrphy_bitslip162[0];
+ k7ddrphy_dfi_p0_rddata[48] <= k7ddrphy_bitslip162[1];
+ k7ddrphy_dfi_p0_rddata[17] <= k7ddrphy_bitslip172[0];
+ k7ddrphy_dfi_p0_rddata[49] <= k7ddrphy_bitslip172[1];
+ k7ddrphy_dfi_p0_rddata[18] <= k7ddrphy_bitslip182[0];
+ k7ddrphy_dfi_p0_rddata[50] <= k7ddrphy_bitslip182[1];
+ k7ddrphy_dfi_p0_rddata[19] <= k7ddrphy_bitslip192[0];
+ k7ddrphy_dfi_p0_rddata[51] <= k7ddrphy_bitslip192[1];
+ k7ddrphy_dfi_p0_rddata[20] <= k7ddrphy_bitslip202[0];
+ k7ddrphy_dfi_p0_rddata[52] <= k7ddrphy_bitslip202[1];
+ k7ddrphy_dfi_p0_rddata[21] <= k7ddrphy_bitslip212[0];
+ k7ddrphy_dfi_p0_rddata[53] <= k7ddrphy_bitslip212[1];
+ k7ddrphy_dfi_p0_rddata[22] <= k7ddrphy_bitslip222[0];
+ k7ddrphy_dfi_p0_rddata[54] <= k7ddrphy_bitslip222[1];
+ k7ddrphy_dfi_p0_rddata[23] <= k7ddrphy_bitslip232[0];
+ k7ddrphy_dfi_p0_rddata[55] <= k7ddrphy_bitslip232[1];
+ k7ddrphy_dfi_p0_rddata[24] <= k7ddrphy_bitslip242[0];
+ k7ddrphy_dfi_p0_rddata[56] <= k7ddrphy_bitslip242[1];
+ k7ddrphy_dfi_p0_rddata[25] <= k7ddrphy_bitslip252[0];
+ k7ddrphy_dfi_p0_rddata[57] <= k7ddrphy_bitslip252[1];
+ k7ddrphy_dfi_p0_rddata[26] <= k7ddrphy_bitslip262[0];
+ k7ddrphy_dfi_p0_rddata[58] <= k7ddrphy_bitslip262[1];
+ k7ddrphy_dfi_p0_rddata[27] <= k7ddrphy_bitslip272[0];
+ k7ddrphy_dfi_p0_rddata[59] <= k7ddrphy_bitslip272[1];
+ k7ddrphy_dfi_p0_rddata[28] <= k7ddrphy_bitslip282[0];
+ k7ddrphy_dfi_p0_rddata[60] <= k7ddrphy_bitslip282[1];
+ k7ddrphy_dfi_p0_rddata[29] <= k7ddrphy_bitslip292[0];
+ k7ddrphy_dfi_p0_rddata[61] <= k7ddrphy_bitslip292[1];
+ k7ddrphy_dfi_p0_rddata[30] <= k7ddrphy_bitslip302[0];
+ k7ddrphy_dfi_p0_rddata[62] <= k7ddrphy_bitslip302[1];
+ k7ddrphy_dfi_p0_rddata[31] <= k7ddrphy_bitslip312[0];
+ k7ddrphy_dfi_p0_rddata[63] <= k7ddrphy_bitslip312[1];
+end
+always @(*) begin
+ k7ddrphy_dfi_p1_rddata <= 64'd0;
+ k7ddrphy_dfi_p1_rddata[0] <= k7ddrphy_bitslip04[2];
+ k7ddrphy_dfi_p1_rddata[32] <= k7ddrphy_bitslip04[3];
+ k7ddrphy_dfi_p1_rddata[1] <= k7ddrphy_bitslip14[2];
+ k7ddrphy_dfi_p1_rddata[33] <= k7ddrphy_bitslip14[3];
+ k7ddrphy_dfi_p1_rddata[2] <= k7ddrphy_bitslip24[2];
+ k7ddrphy_dfi_p1_rddata[34] <= k7ddrphy_bitslip24[3];
+ k7ddrphy_dfi_p1_rddata[3] <= k7ddrphy_bitslip34[2];
+ k7ddrphy_dfi_p1_rddata[35] <= k7ddrphy_bitslip34[3];
+ k7ddrphy_dfi_p1_rddata[4] <= k7ddrphy_bitslip42[2];
+ k7ddrphy_dfi_p1_rddata[36] <= k7ddrphy_bitslip42[3];
+ k7ddrphy_dfi_p1_rddata[5] <= k7ddrphy_bitslip52[2];
+ k7ddrphy_dfi_p1_rddata[37] <= k7ddrphy_bitslip52[3];
+ k7ddrphy_dfi_p1_rddata[6] <= k7ddrphy_bitslip62[2];
+ k7ddrphy_dfi_p1_rddata[38] <= k7ddrphy_bitslip62[3];
+ k7ddrphy_dfi_p1_rddata[7] <= k7ddrphy_bitslip72[2];
+ k7ddrphy_dfi_p1_rddata[39] <= k7ddrphy_bitslip72[3];
+ k7ddrphy_dfi_p1_rddata[8] <= k7ddrphy_bitslip82[2];
+ k7ddrphy_dfi_p1_rddata[40] <= k7ddrphy_bitslip82[3];
+ k7ddrphy_dfi_p1_rddata[9] <= k7ddrphy_bitslip92[2];
+ k7ddrphy_dfi_p1_rddata[41] <= k7ddrphy_bitslip92[3];
+ k7ddrphy_dfi_p1_rddata[10] <= k7ddrphy_bitslip102[2];
+ k7ddrphy_dfi_p1_rddata[42] <= k7ddrphy_bitslip102[3];
+ k7ddrphy_dfi_p1_rddata[11] <= k7ddrphy_bitslip112[2];
+ k7ddrphy_dfi_p1_rddata[43] <= k7ddrphy_bitslip112[3];
+ k7ddrphy_dfi_p1_rddata[12] <= k7ddrphy_bitslip122[2];
+ k7ddrphy_dfi_p1_rddata[44] <= k7ddrphy_bitslip122[3];
+ k7ddrphy_dfi_p1_rddata[13] <= k7ddrphy_bitslip132[2];
+ k7ddrphy_dfi_p1_rddata[45] <= k7ddrphy_bitslip132[3];
+ k7ddrphy_dfi_p1_rddata[14] <= k7ddrphy_bitslip142[2];
+ k7ddrphy_dfi_p1_rddata[46] <= k7ddrphy_bitslip142[3];
+ k7ddrphy_dfi_p1_rddata[15] <= k7ddrphy_bitslip152[2];
+ k7ddrphy_dfi_p1_rddata[47] <= k7ddrphy_bitslip152[3];
+ k7ddrphy_dfi_p1_rddata[16] <= k7ddrphy_bitslip162[2];
+ k7ddrphy_dfi_p1_rddata[48] <= k7ddrphy_bitslip162[3];
+ k7ddrphy_dfi_p1_rddata[17] <= k7ddrphy_bitslip172[2];
+ k7ddrphy_dfi_p1_rddata[49] <= k7ddrphy_bitslip172[3];
+ k7ddrphy_dfi_p1_rddata[18] <= k7ddrphy_bitslip182[2];
+ k7ddrphy_dfi_p1_rddata[50] <= k7ddrphy_bitslip182[3];
+ k7ddrphy_dfi_p1_rddata[19] <= k7ddrphy_bitslip192[2];
+ k7ddrphy_dfi_p1_rddata[51] <= k7ddrphy_bitslip192[3];
+ k7ddrphy_dfi_p1_rddata[20] <= k7ddrphy_bitslip202[2];
+ k7ddrphy_dfi_p1_rddata[52] <= k7ddrphy_bitslip202[3];
+ k7ddrphy_dfi_p1_rddata[21] <= k7ddrphy_bitslip212[2];
+ k7ddrphy_dfi_p1_rddata[53] <= k7ddrphy_bitslip212[3];
+ k7ddrphy_dfi_p1_rddata[22] <= k7ddrphy_bitslip222[2];
+ k7ddrphy_dfi_p1_rddata[54] <= k7ddrphy_bitslip222[3];
+ k7ddrphy_dfi_p1_rddata[23] <= k7ddrphy_bitslip232[2];
+ k7ddrphy_dfi_p1_rddata[55] <= k7ddrphy_bitslip232[3];
+ k7ddrphy_dfi_p1_rddata[24] <= k7ddrphy_bitslip242[2];
+ k7ddrphy_dfi_p1_rddata[56] <= k7ddrphy_bitslip242[3];
+ k7ddrphy_dfi_p1_rddata[25] <= k7ddrphy_bitslip252[2];
+ k7ddrphy_dfi_p1_rddata[57] <= k7ddrphy_bitslip252[3];
+ k7ddrphy_dfi_p1_rddata[26] <= k7ddrphy_bitslip262[2];
+ k7ddrphy_dfi_p1_rddata[58] <= k7ddrphy_bitslip262[3];
+ k7ddrphy_dfi_p1_rddata[27] <= k7ddrphy_bitslip272[2];
+ k7ddrphy_dfi_p1_rddata[59] <= k7ddrphy_bitslip272[3];
+ k7ddrphy_dfi_p1_rddata[28] <= k7ddrphy_bitslip282[2];
+ k7ddrphy_dfi_p1_rddata[60] <= k7ddrphy_bitslip282[3];
+ k7ddrphy_dfi_p1_rddata[29] <= k7ddrphy_bitslip292[2];
+ k7ddrphy_dfi_p1_rddata[61] <= k7ddrphy_bitslip292[3];
+ k7ddrphy_dfi_p1_rddata[30] <= k7ddrphy_bitslip302[2];
+ k7ddrphy_dfi_p1_rddata[62] <= k7ddrphy_bitslip302[3];
+ k7ddrphy_dfi_p1_rddata[31] <= k7ddrphy_bitslip312[2];
+ k7ddrphy_dfi_p1_rddata[63] <= k7ddrphy_bitslip312[3];
+end
+always @(*) begin
+ k7ddrphy_dfi_p2_rddata <= 64'd0;
+ k7ddrphy_dfi_p2_rddata[0] <= k7ddrphy_bitslip04[4];
+ k7ddrphy_dfi_p2_rddata[32] <= k7ddrphy_bitslip04[5];
+ k7ddrphy_dfi_p2_rddata[1] <= k7ddrphy_bitslip14[4];
+ k7ddrphy_dfi_p2_rddata[33] <= k7ddrphy_bitslip14[5];
+ k7ddrphy_dfi_p2_rddata[2] <= k7ddrphy_bitslip24[4];
+ k7ddrphy_dfi_p2_rddata[34] <= k7ddrphy_bitslip24[5];
+ k7ddrphy_dfi_p2_rddata[3] <= k7ddrphy_bitslip34[4];
+ k7ddrphy_dfi_p2_rddata[35] <= k7ddrphy_bitslip34[5];
+ k7ddrphy_dfi_p2_rddata[4] <= k7ddrphy_bitslip42[4];
+ k7ddrphy_dfi_p2_rddata[36] <= k7ddrphy_bitslip42[5];
+ k7ddrphy_dfi_p2_rddata[5] <= k7ddrphy_bitslip52[4];
+ k7ddrphy_dfi_p2_rddata[37] <= k7ddrphy_bitslip52[5];
+ k7ddrphy_dfi_p2_rddata[6] <= k7ddrphy_bitslip62[4];
+ k7ddrphy_dfi_p2_rddata[38] <= k7ddrphy_bitslip62[5];
+ k7ddrphy_dfi_p2_rddata[7] <= k7ddrphy_bitslip72[4];
+ k7ddrphy_dfi_p2_rddata[39] <= k7ddrphy_bitslip72[5];
+ k7ddrphy_dfi_p2_rddata[8] <= k7ddrphy_bitslip82[4];
+ k7ddrphy_dfi_p2_rddata[40] <= k7ddrphy_bitslip82[5];
+ k7ddrphy_dfi_p2_rddata[9] <= k7ddrphy_bitslip92[4];
+ k7ddrphy_dfi_p2_rddata[41] <= k7ddrphy_bitslip92[5];
+ k7ddrphy_dfi_p2_rddata[10] <= k7ddrphy_bitslip102[4];
+ k7ddrphy_dfi_p2_rddata[42] <= k7ddrphy_bitslip102[5];
+ k7ddrphy_dfi_p2_rddata[11] <= k7ddrphy_bitslip112[4];
+ k7ddrphy_dfi_p2_rddata[43] <= k7ddrphy_bitslip112[5];
+ k7ddrphy_dfi_p2_rddata[12] <= k7ddrphy_bitslip122[4];
+ k7ddrphy_dfi_p2_rddata[44] <= k7ddrphy_bitslip122[5];
+ k7ddrphy_dfi_p2_rddata[13] <= k7ddrphy_bitslip132[4];
+ k7ddrphy_dfi_p2_rddata[45] <= k7ddrphy_bitslip132[5];
+ k7ddrphy_dfi_p2_rddata[14] <= k7ddrphy_bitslip142[4];
+ k7ddrphy_dfi_p2_rddata[46] <= k7ddrphy_bitslip142[5];
+ k7ddrphy_dfi_p2_rddata[15] <= k7ddrphy_bitslip152[4];
+ k7ddrphy_dfi_p2_rddata[47] <= k7ddrphy_bitslip152[5];
+ k7ddrphy_dfi_p2_rddata[16] <= k7ddrphy_bitslip162[4];
+ k7ddrphy_dfi_p2_rddata[48] <= k7ddrphy_bitslip162[5];
+ k7ddrphy_dfi_p2_rddata[17] <= k7ddrphy_bitslip172[4];
+ k7ddrphy_dfi_p2_rddata[49] <= k7ddrphy_bitslip172[5];
+ k7ddrphy_dfi_p2_rddata[18] <= k7ddrphy_bitslip182[4];
+ k7ddrphy_dfi_p2_rddata[50] <= k7ddrphy_bitslip182[5];
+ k7ddrphy_dfi_p2_rddata[19] <= k7ddrphy_bitslip192[4];
+ k7ddrphy_dfi_p2_rddata[51] <= k7ddrphy_bitslip192[5];
+ k7ddrphy_dfi_p2_rddata[20] <= k7ddrphy_bitslip202[4];
+ k7ddrphy_dfi_p2_rddata[52] <= k7ddrphy_bitslip202[5];
+ k7ddrphy_dfi_p2_rddata[21] <= k7ddrphy_bitslip212[4];
+ k7ddrphy_dfi_p2_rddata[53] <= k7ddrphy_bitslip212[5];
+ k7ddrphy_dfi_p2_rddata[22] <= k7ddrphy_bitslip222[4];
+ k7ddrphy_dfi_p2_rddata[54] <= k7ddrphy_bitslip222[5];
+ k7ddrphy_dfi_p2_rddata[23] <= k7ddrphy_bitslip232[4];
+ k7ddrphy_dfi_p2_rddata[55] <= k7ddrphy_bitslip232[5];
+ k7ddrphy_dfi_p2_rddata[24] <= k7ddrphy_bitslip242[4];
+ k7ddrphy_dfi_p2_rddata[56] <= k7ddrphy_bitslip242[5];
+ k7ddrphy_dfi_p2_rddata[25] <= k7ddrphy_bitslip252[4];
+ k7ddrphy_dfi_p2_rddata[57] <= k7ddrphy_bitslip252[5];
+ k7ddrphy_dfi_p2_rddata[26] <= k7ddrphy_bitslip262[4];
+ k7ddrphy_dfi_p2_rddata[58] <= k7ddrphy_bitslip262[5];
+ k7ddrphy_dfi_p2_rddata[27] <= k7ddrphy_bitslip272[4];
+ k7ddrphy_dfi_p2_rddata[59] <= k7ddrphy_bitslip272[5];
+ k7ddrphy_dfi_p2_rddata[28] <= k7ddrphy_bitslip282[4];
+ k7ddrphy_dfi_p2_rddata[60] <= k7ddrphy_bitslip282[5];
+ k7ddrphy_dfi_p2_rddata[29] <= k7ddrphy_bitslip292[4];
+ k7ddrphy_dfi_p2_rddata[61] <= k7ddrphy_bitslip292[5];
+ k7ddrphy_dfi_p2_rddata[30] <= k7ddrphy_bitslip302[4];
+ k7ddrphy_dfi_p2_rddata[62] <= k7ddrphy_bitslip302[5];
+ k7ddrphy_dfi_p2_rddata[31] <= k7ddrphy_bitslip312[4];
+ k7ddrphy_dfi_p2_rddata[63] <= k7ddrphy_bitslip312[5];
+end
+always @(*) begin
+ k7ddrphy_dfi_p3_rddata <= 64'd0;
+ k7ddrphy_dfi_p3_rddata[0] <= k7ddrphy_bitslip04[6];
+ k7ddrphy_dfi_p3_rddata[32] <= k7ddrphy_bitslip04[7];
+ k7ddrphy_dfi_p3_rddata[1] <= k7ddrphy_bitslip14[6];
+ k7ddrphy_dfi_p3_rddata[33] <= k7ddrphy_bitslip14[7];
+ k7ddrphy_dfi_p3_rddata[2] <= k7ddrphy_bitslip24[6];
+ k7ddrphy_dfi_p3_rddata[34] <= k7ddrphy_bitslip24[7];
+ k7ddrphy_dfi_p3_rddata[3] <= k7ddrphy_bitslip34[6];
+ k7ddrphy_dfi_p3_rddata[35] <= k7ddrphy_bitslip34[7];
+ k7ddrphy_dfi_p3_rddata[4] <= k7ddrphy_bitslip42[6];
+ k7ddrphy_dfi_p3_rddata[36] <= k7ddrphy_bitslip42[7];
+ k7ddrphy_dfi_p3_rddata[5] <= k7ddrphy_bitslip52[6];
+ k7ddrphy_dfi_p3_rddata[37] <= k7ddrphy_bitslip52[7];
+ k7ddrphy_dfi_p3_rddata[6] <= k7ddrphy_bitslip62[6];
+ k7ddrphy_dfi_p3_rddata[38] <= k7ddrphy_bitslip62[7];
+ k7ddrphy_dfi_p3_rddata[7] <= k7ddrphy_bitslip72[6];
+ k7ddrphy_dfi_p3_rddata[39] <= k7ddrphy_bitslip72[7];
+ k7ddrphy_dfi_p3_rddata[8] <= k7ddrphy_bitslip82[6];
+ k7ddrphy_dfi_p3_rddata[40] <= k7ddrphy_bitslip82[7];
+ k7ddrphy_dfi_p3_rddata[9] <= k7ddrphy_bitslip92[6];
+ k7ddrphy_dfi_p3_rddata[41] <= k7ddrphy_bitslip92[7];
+ k7ddrphy_dfi_p3_rddata[10] <= k7ddrphy_bitslip102[6];
+ k7ddrphy_dfi_p3_rddata[42] <= k7ddrphy_bitslip102[7];
+ k7ddrphy_dfi_p3_rddata[11] <= k7ddrphy_bitslip112[6];
+ k7ddrphy_dfi_p3_rddata[43] <= k7ddrphy_bitslip112[7];
+ k7ddrphy_dfi_p3_rddata[12] <= k7ddrphy_bitslip122[6];
+ k7ddrphy_dfi_p3_rddata[44] <= k7ddrphy_bitslip122[7];
+ k7ddrphy_dfi_p3_rddata[13] <= k7ddrphy_bitslip132[6];
+ k7ddrphy_dfi_p3_rddata[45] <= k7ddrphy_bitslip132[7];
+ k7ddrphy_dfi_p3_rddata[14] <= k7ddrphy_bitslip142[6];
+ k7ddrphy_dfi_p3_rddata[46] <= k7ddrphy_bitslip142[7];
+ k7ddrphy_dfi_p3_rddata[15] <= k7ddrphy_bitslip152[6];
+ k7ddrphy_dfi_p3_rddata[47] <= k7ddrphy_bitslip152[7];
+ k7ddrphy_dfi_p3_rddata[16] <= k7ddrphy_bitslip162[6];
+ k7ddrphy_dfi_p3_rddata[48] <= k7ddrphy_bitslip162[7];
+ k7ddrphy_dfi_p3_rddata[17] <= k7ddrphy_bitslip172[6];
+ k7ddrphy_dfi_p3_rddata[49] <= k7ddrphy_bitslip172[7];
+ k7ddrphy_dfi_p3_rddata[18] <= k7ddrphy_bitslip182[6];
+ k7ddrphy_dfi_p3_rddata[50] <= k7ddrphy_bitslip182[7];
+ k7ddrphy_dfi_p3_rddata[19] <= k7ddrphy_bitslip192[6];
+ k7ddrphy_dfi_p3_rddata[51] <= k7ddrphy_bitslip192[7];
+ k7ddrphy_dfi_p3_rddata[20] <= k7ddrphy_bitslip202[6];
+ k7ddrphy_dfi_p3_rddata[52] <= k7ddrphy_bitslip202[7];
+ k7ddrphy_dfi_p3_rddata[21] <= k7ddrphy_bitslip212[6];
+ k7ddrphy_dfi_p3_rddata[53] <= k7ddrphy_bitslip212[7];
+ k7ddrphy_dfi_p3_rddata[22] <= k7ddrphy_bitslip222[6];
+ k7ddrphy_dfi_p3_rddata[54] <= k7ddrphy_bitslip222[7];
+ k7ddrphy_dfi_p3_rddata[23] <= k7ddrphy_bitslip232[6];
+ k7ddrphy_dfi_p3_rddata[55] <= k7ddrphy_bitslip232[7];
+ k7ddrphy_dfi_p3_rddata[24] <= k7ddrphy_bitslip242[6];
+ k7ddrphy_dfi_p3_rddata[56] <= k7ddrphy_bitslip242[7];
+ k7ddrphy_dfi_p3_rddata[25] <= k7ddrphy_bitslip252[6];
+ k7ddrphy_dfi_p3_rddata[57] <= k7ddrphy_bitslip252[7];
+ k7ddrphy_dfi_p3_rddata[26] <= k7ddrphy_bitslip262[6];
+ k7ddrphy_dfi_p3_rddata[58] <= k7ddrphy_bitslip262[7];
+ k7ddrphy_dfi_p3_rddata[27] <= k7ddrphy_bitslip272[6];
+ k7ddrphy_dfi_p3_rddata[59] <= k7ddrphy_bitslip272[7];
+ k7ddrphy_dfi_p3_rddata[28] <= k7ddrphy_bitslip282[6];
+ k7ddrphy_dfi_p3_rddata[60] <= k7ddrphy_bitslip282[7];
+ k7ddrphy_dfi_p3_rddata[29] <= k7ddrphy_bitslip292[6];
+ k7ddrphy_dfi_p3_rddata[61] <= k7ddrphy_bitslip292[7];
+ k7ddrphy_dfi_p3_rddata[30] <= k7ddrphy_bitslip302[6];
+ k7ddrphy_dfi_p3_rddata[62] <= k7ddrphy_bitslip302[7];
+ k7ddrphy_dfi_p3_rddata[31] <= k7ddrphy_bitslip312[6];
+ k7ddrphy_dfi_p3_rddata[63] <= k7ddrphy_bitslip312[7];
end
assign k7ddrphy_dfi_p0_rddata_valid = (k7ddrphy_rddata_en_tappeddelayline7 | k7ddrphy_wlevel_en_storage);
assign k7ddrphy_dfi_p1_rddata_valid = (k7ddrphy_rddata_en_tappeddelayline7 | k7ddrphy_wlevel_en_storage);
assign k7ddrphy_dfi_p3_rddata_valid = (k7ddrphy_rddata_en_tappeddelayline7 | k7ddrphy_wlevel_en_storage);
assign k7ddrphy_dq_oe = k7ddrphy_wrdata_en_tappeddelayline1;
always @(*) begin
- k7ddrphy_dqs_oe <= 1'd0;
- if (k7ddrphy_wlevel_en_storage) begin
- k7ddrphy_dqs_oe <= 1'd1;
- end else begin
- k7ddrphy_dqs_oe <= k7ddrphy_dq_oe;
- end
+ k7ddrphy_dqs_oe <= 1'd0;
+ if (k7ddrphy_wlevel_en_storage) begin
+ k7ddrphy_dqs_oe <= 1'd1;
+ end else begin
+ k7ddrphy_dqs_oe <= k7ddrphy_dq_oe;
+ end
end
assign k7ddrphy_dqs_preamble = (k7ddrphy_wrdata_en_tappeddelayline0 & (~k7ddrphy_wrdata_en_tappeddelayline1));
assign k7ddrphy_dqs_postamble = (k7ddrphy_wrdata_en_tappeddelayline2 & (~k7ddrphy_wrdata_en_tappeddelayline1));
always @(*) begin
- k7ddrphy_dqspattern_o <= 8'd0;
- k7ddrphy_dqspattern_o <= 7'd85;
- if (k7ddrphy_dqspattern0) begin
- k7ddrphy_dqspattern_o <= 5'd21;
- end
- if (k7ddrphy_dqspattern1) begin
- k7ddrphy_dqspattern_o <= 7'd84;
- end
- if (k7ddrphy_wlevel_en_storage) begin
- k7ddrphy_dqspattern_o <= 1'd0;
- if (k7ddrphy_wlevel_strobe_re) begin
- k7ddrphy_dqspattern_o <= 1'd1;
- end
- end
-end
-always @(*) begin
- k7ddrphy_bitslip00 <= 8'd0;
- case (k7ddrphy_bitslip0_value0)
- 1'd0: begin
- k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip10 <= 8'd0;
- case (k7ddrphy_bitslip1_value0)
- 1'd0: begin
- k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip20 <= 8'd0;
- case (k7ddrphy_bitslip2_value0)
- 1'd0: begin
- k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip30 <= 8'd0;
- case (k7ddrphy_bitslip3_value0)
- 1'd0: begin
- k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip01 <= 8'd0;
- case (k7ddrphy_bitslip0_value1)
- 1'd0: begin
- k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip11 <= 8'd0;
- case (k7ddrphy_bitslip1_value1)
- 1'd0: begin
- k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip21 <= 8'd0;
- case (k7ddrphy_bitslip2_value1)
- 1'd0: begin
- k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip31 <= 8'd0;
- case (k7ddrphy_bitslip3_value1)
- 1'd0: begin
- k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip02 <= 8'd0;
- case (k7ddrphy_bitslip0_value2)
- 1'd0: begin
- k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip04 <= 8'd0;
- case (k7ddrphy_bitslip0_value3)
- 1'd0: begin
- k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip12 <= 8'd0;
- case (k7ddrphy_bitslip1_value2)
- 1'd0: begin
- k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip14 <= 8'd0;
- case (k7ddrphy_bitslip1_value3)
- 1'd0: begin
- k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip22 <= 8'd0;
- case (k7ddrphy_bitslip2_value2)
- 1'd0: begin
- k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip24 <= 8'd0;
- case (k7ddrphy_bitslip2_value3)
- 1'd0: begin
- k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip32 <= 8'd0;
- case (k7ddrphy_bitslip3_value2)
- 1'd0: begin
- k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip34 <= 8'd0;
- case (k7ddrphy_bitslip3_value3)
- 1'd0: begin
- k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip40 <= 8'd0;
- case (k7ddrphy_bitslip4_value0)
- 1'd0: begin
- k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip42 <= 8'd0;
- case (k7ddrphy_bitslip4_value1)
- 1'd0: begin
- k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip50 <= 8'd0;
- case (k7ddrphy_bitslip5_value0)
- 1'd0: begin
- k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip52 <= 8'd0;
- case (k7ddrphy_bitslip5_value1)
- 1'd0: begin
- k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip60 <= 8'd0;
- case (k7ddrphy_bitslip6_value0)
- 1'd0: begin
- k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip62 <= 8'd0;
- case (k7ddrphy_bitslip6_value1)
- 1'd0: begin
- k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip70 <= 8'd0;
- case (k7ddrphy_bitslip7_value0)
- 1'd0: begin
- k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip72 <= 8'd0;
- case (k7ddrphy_bitslip7_value1)
- 1'd0: begin
- k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip80 <= 8'd0;
- case (k7ddrphy_bitslip8_value0)
- 1'd0: begin
- k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip82 <= 8'd0;
- case (k7ddrphy_bitslip8_value1)
- 1'd0: begin
- k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip90 <= 8'd0;
- case (k7ddrphy_bitslip9_value0)
- 1'd0: begin
- k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip92 <= 8'd0;
- case (k7ddrphy_bitslip9_value1)
- 1'd0: begin
- k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip100 <= 8'd0;
- case (k7ddrphy_bitslip10_value0)
- 1'd0: begin
- k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip102 <= 8'd0;
- case (k7ddrphy_bitslip10_value1)
- 1'd0: begin
- k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip110 <= 8'd0;
- case (k7ddrphy_bitslip11_value0)
- 1'd0: begin
- k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip112 <= 8'd0;
- case (k7ddrphy_bitslip11_value1)
- 1'd0: begin
- k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip120 <= 8'd0;
- case (k7ddrphy_bitslip12_value0)
- 1'd0: begin
- k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip122 <= 8'd0;
- case (k7ddrphy_bitslip12_value1)
- 1'd0: begin
- k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip130 <= 8'd0;
- case (k7ddrphy_bitslip13_value0)
- 1'd0: begin
- k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip132 <= 8'd0;
- case (k7ddrphy_bitslip13_value1)
- 1'd0: begin
- k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip140 <= 8'd0;
- case (k7ddrphy_bitslip14_value0)
- 1'd0: begin
- k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip142 <= 8'd0;
- case (k7ddrphy_bitslip14_value1)
- 1'd0: begin
- k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip150 <= 8'd0;
- case (k7ddrphy_bitslip15_value0)
- 1'd0: begin
- k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip152 <= 8'd0;
- case (k7ddrphy_bitslip15_value1)
- 1'd0: begin
- k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip160 <= 8'd0;
- case (k7ddrphy_bitslip16_value0)
- 1'd0: begin
- k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip162 <= 8'd0;
- case (k7ddrphy_bitslip16_value1)
- 1'd0: begin
- k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip170 <= 8'd0;
- case (k7ddrphy_bitslip17_value0)
- 1'd0: begin
- k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip172 <= 8'd0;
- case (k7ddrphy_bitslip17_value1)
- 1'd0: begin
- k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip180 <= 8'd0;
- case (k7ddrphy_bitslip18_value0)
- 1'd0: begin
- k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip182 <= 8'd0;
- case (k7ddrphy_bitslip18_value1)
- 1'd0: begin
- k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip190 <= 8'd0;
- case (k7ddrphy_bitslip19_value0)
- 1'd0: begin
- k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip192 <= 8'd0;
- case (k7ddrphy_bitslip19_value1)
- 1'd0: begin
- k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip200 <= 8'd0;
- case (k7ddrphy_bitslip20_value0)
- 1'd0: begin
- k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip202 <= 8'd0;
- case (k7ddrphy_bitslip20_value1)
- 1'd0: begin
- k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip210 <= 8'd0;
- case (k7ddrphy_bitslip21_value0)
- 1'd0: begin
- k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip212 <= 8'd0;
- case (k7ddrphy_bitslip21_value1)
- 1'd0: begin
- k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip220 <= 8'd0;
- case (k7ddrphy_bitslip22_value0)
- 1'd0: begin
- k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip222 <= 8'd0;
- case (k7ddrphy_bitslip22_value1)
- 1'd0: begin
- k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip230 <= 8'd0;
- case (k7ddrphy_bitslip23_value0)
- 1'd0: begin
- k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip232 <= 8'd0;
- case (k7ddrphy_bitslip23_value1)
- 1'd0: begin
- k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip240 <= 8'd0;
- case (k7ddrphy_bitslip24_value0)
- 1'd0: begin
- k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip242 <= 8'd0;
- case (k7ddrphy_bitslip24_value1)
- 1'd0: begin
- k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip250 <= 8'd0;
- case (k7ddrphy_bitslip25_value0)
- 1'd0: begin
- k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip252 <= 8'd0;
- case (k7ddrphy_bitslip25_value1)
- 1'd0: begin
- k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip260 <= 8'd0;
- case (k7ddrphy_bitslip26_value0)
- 1'd0: begin
- k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip262 <= 8'd0;
- case (k7ddrphy_bitslip26_value1)
- 1'd0: begin
- k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip270 <= 8'd0;
- case (k7ddrphy_bitslip27_value0)
- 1'd0: begin
- k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip272 <= 8'd0;
- case (k7ddrphy_bitslip27_value1)
- 1'd0: begin
- k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip280 <= 8'd0;
- case (k7ddrphy_bitslip28_value0)
- 1'd0: begin
- k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip282 <= 8'd0;
- case (k7ddrphy_bitslip28_value1)
- 1'd0: begin
- k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip290 <= 8'd0;
- case (k7ddrphy_bitslip29_value0)
- 1'd0: begin
- k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip292 <= 8'd0;
- case (k7ddrphy_bitslip29_value1)
- 1'd0: begin
- k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip300 <= 8'd0;
- case (k7ddrphy_bitslip30_value0)
- 1'd0: begin
- k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip302 <= 8'd0;
- case (k7ddrphy_bitslip30_value1)
- 1'd0: begin
- k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip310 <= 8'd0;
- case (k7ddrphy_bitslip31_value0)
- 1'd0: begin
- k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- k7ddrphy_bitslip312 <= 8'd0;
- case (k7ddrphy_bitslip31_value1)
- 1'd0: begin
- k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[8:1];
- end
- 1'd1: begin
- k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[9:2];
- end
- 2'd2: begin
- k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[10:3];
- end
- 2'd3: begin
- k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[11:4];
- end
- 3'd4: begin
- k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[12:5];
- end
- 3'd5: begin
- k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[13:6];
- end
- 3'd6: begin
- k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[14:7];
- end
- 3'd7: begin
- k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[15:8];
- end
- endcase
+ k7ddrphy_dqspattern_o <= 8'd0;
+ k7ddrphy_dqspattern_o <= 7'd85;
+ if (k7ddrphy_dqspattern0) begin
+ k7ddrphy_dqspattern_o <= 5'd21;
+ end
+ if (k7ddrphy_dqspattern1) begin
+ k7ddrphy_dqspattern_o <= 7'd84;
+ end
+ if (k7ddrphy_wlevel_en_storage) begin
+ k7ddrphy_dqspattern_o <= 1'd0;
+ if (k7ddrphy_wlevel_strobe_re) begin
+ k7ddrphy_dqspattern_o <= 1'd1;
+ end
+ end
+end
+always @(*) begin
+ k7ddrphy_bitslip00 <= 8'd0;
+ case (k7ddrphy_bitslip0_value0)
+ 1'd0: begin
+ k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip00 <= k7ddrphy_bitslip0_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip10 <= 8'd0;
+ case (k7ddrphy_bitslip1_value0)
+ 1'd0: begin
+ k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip10 <= k7ddrphy_bitslip1_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip20 <= 8'd0;
+ case (k7ddrphy_bitslip2_value0)
+ 1'd0: begin
+ k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip20 <= k7ddrphy_bitslip2_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip30 <= 8'd0;
+ case (k7ddrphy_bitslip3_value0)
+ 1'd0: begin
+ k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip30 <= k7ddrphy_bitslip3_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip01 <= 8'd0;
+ case (k7ddrphy_bitslip0_value1)
+ 1'd0: begin
+ k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip01 <= k7ddrphy_bitslip0_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip11 <= 8'd0;
+ case (k7ddrphy_bitslip1_value1)
+ 1'd0: begin
+ k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip11 <= k7ddrphy_bitslip1_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip21 <= 8'd0;
+ case (k7ddrphy_bitslip2_value1)
+ 1'd0: begin
+ k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip21 <= k7ddrphy_bitslip2_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip31 <= 8'd0;
+ case (k7ddrphy_bitslip3_value1)
+ 1'd0: begin
+ k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip31 <= k7ddrphy_bitslip3_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip02 <= 8'd0;
+ case (k7ddrphy_bitslip0_value2)
+ 1'd0: begin
+ k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip02 <= k7ddrphy_bitslip0_r2[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip04 <= 8'd0;
+ case (k7ddrphy_bitslip0_value3)
+ 1'd0: begin
+ k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip04 <= k7ddrphy_bitslip0_r3[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip12 <= 8'd0;
+ case (k7ddrphy_bitslip1_value2)
+ 1'd0: begin
+ k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip12 <= k7ddrphy_bitslip1_r2[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip14 <= 8'd0;
+ case (k7ddrphy_bitslip1_value3)
+ 1'd0: begin
+ k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip14 <= k7ddrphy_bitslip1_r3[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip22 <= 8'd0;
+ case (k7ddrphy_bitslip2_value2)
+ 1'd0: begin
+ k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip22 <= k7ddrphy_bitslip2_r2[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip24 <= 8'd0;
+ case (k7ddrphy_bitslip2_value3)
+ 1'd0: begin
+ k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip24 <= k7ddrphy_bitslip2_r3[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip32 <= 8'd0;
+ case (k7ddrphy_bitslip3_value2)
+ 1'd0: begin
+ k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip32 <= k7ddrphy_bitslip3_r2[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip34 <= 8'd0;
+ case (k7ddrphy_bitslip3_value3)
+ 1'd0: begin
+ k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip34 <= k7ddrphy_bitslip3_r3[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip40 <= 8'd0;
+ case (k7ddrphy_bitslip4_value0)
+ 1'd0: begin
+ k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip40 <= k7ddrphy_bitslip4_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip42 <= 8'd0;
+ case (k7ddrphy_bitslip4_value1)
+ 1'd0: begin
+ k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip42 <= k7ddrphy_bitslip4_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip50 <= 8'd0;
+ case (k7ddrphy_bitslip5_value0)
+ 1'd0: begin
+ k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip50 <= k7ddrphy_bitslip5_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip52 <= 8'd0;
+ case (k7ddrphy_bitslip5_value1)
+ 1'd0: begin
+ k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip52 <= k7ddrphy_bitslip5_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip60 <= 8'd0;
+ case (k7ddrphy_bitslip6_value0)
+ 1'd0: begin
+ k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip60 <= k7ddrphy_bitslip6_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip62 <= 8'd0;
+ case (k7ddrphy_bitslip6_value1)
+ 1'd0: begin
+ k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip62 <= k7ddrphy_bitslip6_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip70 <= 8'd0;
+ case (k7ddrphy_bitslip7_value0)
+ 1'd0: begin
+ k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip70 <= k7ddrphy_bitslip7_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip72 <= 8'd0;
+ case (k7ddrphy_bitslip7_value1)
+ 1'd0: begin
+ k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip72 <= k7ddrphy_bitslip7_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip80 <= 8'd0;
+ case (k7ddrphy_bitslip8_value0)
+ 1'd0: begin
+ k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip80 <= k7ddrphy_bitslip8_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip82 <= 8'd0;
+ case (k7ddrphy_bitslip8_value1)
+ 1'd0: begin
+ k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip82 <= k7ddrphy_bitslip8_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip90 <= 8'd0;
+ case (k7ddrphy_bitslip9_value0)
+ 1'd0: begin
+ k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip90 <= k7ddrphy_bitslip9_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip92 <= 8'd0;
+ case (k7ddrphy_bitslip9_value1)
+ 1'd0: begin
+ k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip92 <= k7ddrphy_bitslip9_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip100 <= 8'd0;
+ case (k7ddrphy_bitslip10_value0)
+ 1'd0: begin
+ k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip100 <= k7ddrphy_bitslip10_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip102 <= 8'd0;
+ case (k7ddrphy_bitslip10_value1)
+ 1'd0: begin
+ k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip102 <= k7ddrphy_bitslip10_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip110 <= 8'd0;
+ case (k7ddrphy_bitslip11_value0)
+ 1'd0: begin
+ k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip110 <= k7ddrphy_bitslip11_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip112 <= 8'd0;
+ case (k7ddrphy_bitslip11_value1)
+ 1'd0: begin
+ k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip112 <= k7ddrphy_bitslip11_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip120 <= 8'd0;
+ case (k7ddrphy_bitslip12_value0)
+ 1'd0: begin
+ k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip120 <= k7ddrphy_bitslip12_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip122 <= 8'd0;
+ case (k7ddrphy_bitslip12_value1)
+ 1'd0: begin
+ k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip122 <= k7ddrphy_bitslip12_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip130 <= 8'd0;
+ case (k7ddrphy_bitslip13_value0)
+ 1'd0: begin
+ k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip130 <= k7ddrphy_bitslip13_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip132 <= 8'd0;
+ case (k7ddrphy_bitslip13_value1)
+ 1'd0: begin
+ k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip132 <= k7ddrphy_bitslip13_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip140 <= 8'd0;
+ case (k7ddrphy_bitslip14_value0)
+ 1'd0: begin
+ k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip140 <= k7ddrphy_bitslip14_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip142 <= 8'd0;
+ case (k7ddrphy_bitslip14_value1)
+ 1'd0: begin
+ k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip142 <= k7ddrphy_bitslip14_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip150 <= 8'd0;
+ case (k7ddrphy_bitslip15_value0)
+ 1'd0: begin
+ k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip150 <= k7ddrphy_bitslip15_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip152 <= 8'd0;
+ case (k7ddrphy_bitslip15_value1)
+ 1'd0: begin
+ k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip152 <= k7ddrphy_bitslip15_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip160 <= 8'd0;
+ case (k7ddrphy_bitslip16_value0)
+ 1'd0: begin
+ k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip160 <= k7ddrphy_bitslip16_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip162 <= 8'd0;
+ case (k7ddrphy_bitslip16_value1)
+ 1'd0: begin
+ k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip162 <= k7ddrphy_bitslip16_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip170 <= 8'd0;
+ case (k7ddrphy_bitslip17_value0)
+ 1'd0: begin
+ k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip170 <= k7ddrphy_bitslip17_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip172 <= 8'd0;
+ case (k7ddrphy_bitslip17_value1)
+ 1'd0: begin
+ k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip172 <= k7ddrphy_bitslip17_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip180 <= 8'd0;
+ case (k7ddrphy_bitslip18_value0)
+ 1'd0: begin
+ k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip180 <= k7ddrphy_bitslip18_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip182 <= 8'd0;
+ case (k7ddrphy_bitslip18_value1)
+ 1'd0: begin
+ k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip182 <= k7ddrphy_bitslip18_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip190 <= 8'd0;
+ case (k7ddrphy_bitslip19_value0)
+ 1'd0: begin
+ k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip190 <= k7ddrphy_bitslip19_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip192 <= 8'd0;
+ case (k7ddrphy_bitslip19_value1)
+ 1'd0: begin
+ k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip192 <= k7ddrphy_bitslip19_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip200 <= 8'd0;
+ case (k7ddrphy_bitslip20_value0)
+ 1'd0: begin
+ k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip200 <= k7ddrphy_bitslip20_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip202 <= 8'd0;
+ case (k7ddrphy_bitslip20_value1)
+ 1'd0: begin
+ k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip202 <= k7ddrphy_bitslip20_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip210 <= 8'd0;
+ case (k7ddrphy_bitslip21_value0)
+ 1'd0: begin
+ k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip210 <= k7ddrphy_bitslip21_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip212 <= 8'd0;
+ case (k7ddrphy_bitslip21_value1)
+ 1'd0: begin
+ k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip212 <= k7ddrphy_bitslip21_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip220 <= 8'd0;
+ case (k7ddrphy_bitslip22_value0)
+ 1'd0: begin
+ k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip220 <= k7ddrphy_bitslip22_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip222 <= 8'd0;
+ case (k7ddrphy_bitslip22_value1)
+ 1'd0: begin
+ k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip222 <= k7ddrphy_bitslip22_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip230 <= 8'd0;
+ case (k7ddrphy_bitslip23_value0)
+ 1'd0: begin
+ k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip230 <= k7ddrphy_bitslip23_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip232 <= 8'd0;
+ case (k7ddrphy_bitslip23_value1)
+ 1'd0: begin
+ k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip232 <= k7ddrphy_bitslip23_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip240 <= 8'd0;
+ case (k7ddrphy_bitslip24_value0)
+ 1'd0: begin
+ k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip240 <= k7ddrphy_bitslip24_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip242 <= 8'd0;
+ case (k7ddrphy_bitslip24_value1)
+ 1'd0: begin
+ k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip242 <= k7ddrphy_bitslip24_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip250 <= 8'd0;
+ case (k7ddrphy_bitslip25_value0)
+ 1'd0: begin
+ k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip250 <= k7ddrphy_bitslip25_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip252 <= 8'd0;
+ case (k7ddrphy_bitslip25_value1)
+ 1'd0: begin
+ k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip252 <= k7ddrphy_bitslip25_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip260 <= 8'd0;
+ case (k7ddrphy_bitslip26_value0)
+ 1'd0: begin
+ k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip260 <= k7ddrphy_bitslip26_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip262 <= 8'd0;
+ case (k7ddrphy_bitslip26_value1)
+ 1'd0: begin
+ k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip262 <= k7ddrphy_bitslip26_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip270 <= 8'd0;
+ case (k7ddrphy_bitslip27_value0)
+ 1'd0: begin
+ k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip270 <= k7ddrphy_bitslip27_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip272 <= 8'd0;
+ case (k7ddrphy_bitslip27_value1)
+ 1'd0: begin
+ k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip272 <= k7ddrphy_bitslip27_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip280 <= 8'd0;
+ case (k7ddrphy_bitslip28_value0)
+ 1'd0: begin
+ k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip280 <= k7ddrphy_bitslip28_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip282 <= 8'd0;
+ case (k7ddrphy_bitslip28_value1)
+ 1'd0: begin
+ k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip282 <= k7ddrphy_bitslip28_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip290 <= 8'd0;
+ case (k7ddrphy_bitslip29_value0)
+ 1'd0: begin
+ k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip290 <= k7ddrphy_bitslip29_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip292 <= 8'd0;
+ case (k7ddrphy_bitslip29_value1)
+ 1'd0: begin
+ k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip292 <= k7ddrphy_bitslip29_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip300 <= 8'd0;
+ case (k7ddrphy_bitslip30_value0)
+ 1'd0: begin
+ k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip300 <= k7ddrphy_bitslip30_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip302 <= 8'd0;
+ case (k7ddrphy_bitslip30_value1)
+ 1'd0: begin
+ k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip302 <= k7ddrphy_bitslip30_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip310 <= 8'd0;
+ case (k7ddrphy_bitslip31_value0)
+ 1'd0: begin
+ k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip310 <= k7ddrphy_bitslip31_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ k7ddrphy_bitslip312 <= 8'd0;
+ case (k7ddrphy_bitslip31_value1)
+ 1'd0: begin
+ k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[8:1];
+ end
+ 1'd1: begin
+ k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[9:2];
+ end
+ 2'd2: begin
+ k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[10:3];
+ end
+ 2'd3: begin
+ k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[11:4];
+ end
+ 3'd4: begin
+ k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[12:5];
+ end
+ 3'd5: begin
+ k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[13:6];
+ end
+ 3'd6: begin
+ k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[14:7];
+ end
+ 3'd7: begin
+ k7ddrphy_bitslip312 <= k7ddrphy_bitslip31_r1[15:8];
+ end
+ endcase
end
assign k7ddrphy_dfi_p0_address = litedramcore_master_p0_address;
assign k7ddrphy_dfi_p0_bank = litedramcore_master_p0_bank;
assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata;
assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid;
always @(*) begin
- litedramcore_csr_dfi_p0_rddata <= 64'd0;
- if (litedramcore_sel) begin
- end else begin
- litedramcore_csr_dfi_p0_rddata <= litedramcore_master_p0_rddata;
- end
+ litedramcore_csr_dfi_p0_rddata <= 64'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_csr_dfi_p0_rddata <= litedramcore_master_p0_rddata;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p0_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- end else begin
- litedramcore_csr_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
- end
-end
-always @(*) begin
- litedramcore_csr_dfi_p1_rddata <= 64'd0;
- if (litedramcore_sel) begin
- end else begin
- litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata;
- end
-end
-always @(*) begin
- litedramcore_csr_dfi_p1_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- end else begin
- litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
- end
-end
-always @(*) begin
- litedramcore_csr_dfi_p2_rddata <= 64'd0;
- if (litedramcore_sel) begin
- end else begin
- litedramcore_csr_dfi_p2_rddata <= litedramcore_master_p2_rddata;
- end
-end
-always @(*) begin
- litedramcore_csr_dfi_p2_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- end else begin
- litedramcore_csr_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
- end
-end
-always @(*) begin
- litedramcore_csr_dfi_p3_rddata <= 64'd0;
- if (litedramcore_sel) begin
- end else begin
- litedramcore_csr_dfi_p3_rddata <= litedramcore_master_p3_rddata;
- end
-end
-always @(*) begin
- litedramcore_csr_dfi_p3_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- end else begin
- litedramcore_csr_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
- end
-end
-always @(*) begin
- litedramcore_ext_dfi_p0_rddata <= 64'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_ext_dfi_p0_rddata <= litedramcore_master_p0_rddata;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_ext_dfi_p0_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_ext_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_ext_dfi_p1_rddata <= 64'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_ext_dfi_p1_rddata <= litedramcore_master_p1_rddata;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_ext_dfi_p1_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_ext_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_ext_dfi_p2_rddata <= 64'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_ext_dfi_p2_rddata <= litedramcore_master_p2_rddata;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_ext_dfi_p2_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_ext_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_slave_p0_rddata <= 64'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- end else begin
- litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata;
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_slave_p0_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- end else begin
- litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_ext_dfi_p3_rddata <= 64'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_ext_dfi_p3_rddata <= litedramcore_master_p3_rddata;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_ext_dfi_p3_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_ext_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_slave_p1_rddata <= 64'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- end else begin
- litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata;
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_slave_p1_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- end else begin
- litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_slave_p2_rddata <= 64'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- end else begin
- litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata;
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_slave_p2_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- end else begin
- litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_slave_p3_rddata <= 64'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- end else begin
- litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata;
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_slave_p3_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- end else begin
- litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_master_p0_address <= 15'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_address <= litedramcore_ext_dfi_p0_address;
- end else begin
- litedramcore_master_p0_address <= litedramcore_slave_p0_address;
- end
- end else begin
- litedramcore_master_p0_address <= litedramcore_csr_dfi_p0_address;
- end
-end
-always @(*) begin
- litedramcore_master_p0_bank <= 3'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_bank <= litedramcore_ext_dfi_p0_bank;
- end else begin
- litedramcore_master_p0_bank <= litedramcore_slave_p0_bank;
- end
- end else begin
- litedramcore_master_p0_bank <= litedramcore_csr_dfi_p0_bank;
- end
-end
-always @(*) begin
- litedramcore_master_p0_cas_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_cas_n <= litedramcore_ext_dfi_p0_cas_n;
- end else begin
- litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n;
- end
- end else begin
- litedramcore_master_p0_cas_n <= litedramcore_csr_dfi_p0_cas_n;
- end
-end
-always @(*) begin
- litedramcore_master_p0_cs_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n;
- end else begin
- litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n;
- end
- end else begin
- litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n;
- end
-end
-always @(*) begin
- litedramcore_master_p0_ras_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n;
- end else begin
- litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n;
- end
- end else begin
- litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n;
- end
-end
-always @(*) begin
- litedramcore_master_p0_we_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n;
- end else begin
- litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n;
- end
- end else begin
- litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n;
- end
-end
-always @(*) begin
- litedramcore_master_p0_cke <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_cke <= litedramcore_ext_dfi_p0_cke;
- end else begin
- litedramcore_master_p0_cke <= litedramcore_slave_p0_cke;
- end
- end else begin
- litedramcore_master_p0_cke <= litedramcore_csr_dfi_p0_cke;
- end
-end
-always @(*) begin
- litedramcore_master_p0_odt <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_odt <= litedramcore_ext_dfi_p0_odt;
- end else begin
- litedramcore_master_p0_odt <= litedramcore_slave_p0_odt;
- end
- end else begin
- litedramcore_master_p0_odt <= litedramcore_csr_dfi_p0_odt;
- end
-end
-always @(*) begin
- litedramcore_master_p0_reset_n <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_reset_n <= litedramcore_ext_dfi_p0_reset_n;
- end else begin
- litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n;
- end
- end else begin
- litedramcore_master_p0_reset_n <= litedramcore_csr_dfi_p0_reset_n;
- end
-end
-always @(*) begin
- litedramcore_master_p0_act_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_act_n <= litedramcore_ext_dfi_p0_act_n;
- end else begin
- litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n;
- end
- end else begin
- litedramcore_master_p0_act_n <= litedramcore_csr_dfi_p0_act_n;
- end
-end
-always @(*) begin
- litedramcore_master_p0_wrdata <= 64'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_wrdata <= litedramcore_ext_dfi_p0_wrdata;
- end else begin
- litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata;
- end
- end else begin
- litedramcore_master_p0_wrdata <= litedramcore_csr_dfi_p0_wrdata;
- end
-end
-always @(*) begin
- litedramcore_master_p0_wrdata_en <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_wrdata_en <= litedramcore_ext_dfi_p0_wrdata_en;
- end else begin
- litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en;
- end
- end else begin
- litedramcore_master_p0_wrdata_en <= litedramcore_csr_dfi_p0_wrdata_en;
- end
-end
-always @(*) begin
- litedramcore_master_p0_wrdata_mask <= 8'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_wrdata_mask <= litedramcore_ext_dfi_p0_wrdata_mask;
- end else begin
- litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask;
- end
- end else begin
- litedramcore_master_p0_wrdata_mask <= litedramcore_csr_dfi_p0_wrdata_mask;
- end
-end
-always @(*) begin
- litedramcore_master_p0_rddata_en <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_rddata_en <= litedramcore_ext_dfi_p0_rddata_en;
- end else begin
- litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en;
- end
- end else begin
- litedramcore_master_p0_rddata_en <= litedramcore_csr_dfi_p0_rddata_en;
- end
-end
-always @(*) begin
- litedramcore_master_p1_address <= 15'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_address <= litedramcore_ext_dfi_p1_address;
- end else begin
- litedramcore_master_p1_address <= litedramcore_slave_p1_address;
- end
- end else begin
- litedramcore_master_p1_address <= litedramcore_csr_dfi_p1_address;
- end
-end
-always @(*) begin
- litedramcore_master_p1_bank <= 3'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_bank <= litedramcore_ext_dfi_p1_bank;
- end else begin
- litedramcore_master_p1_bank <= litedramcore_slave_p1_bank;
- end
- end else begin
- litedramcore_master_p1_bank <= litedramcore_csr_dfi_p1_bank;
- end
-end
-always @(*) begin
- litedramcore_master_p1_cas_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_cas_n <= litedramcore_ext_dfi_p1_cas_n;
- end else begin
- litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n;
- end
- end else begin
- litedramcore_master_p1_cas_n <= litedramcore_csr_dfi_p1_cas_n;
- end
-end
-always @(*) begin
- litedramcore_master_p1_cs_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_cs_n <= litedramcore_ext_dfi_p1_cs_n;
- end else begin
- litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n;
- end
- end else begin
- litedramcore_master_p1_cs_n <= litedramcore_csr_dfi_p1_cs_n;
- end
-end
-always @(*) begin
- litedramcore_master_p1_ras_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_ras_n <= litedramcore_ext_dfi_p1_ras_n;
- end else begin
- litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n;
- end
- end else begin
- litedramcore_master_p1_ras_n <= litedramcore_csr_dfi_p1_ras_n;
- end
-end
-always @(*) begin
- litedramcore_master_p1_we_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_we_n <= litedramcore_ext_dfi_p1_we_n;
- end else begin
- litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n;
- end
- end else begin
- litedramcore_master_p1_we_n <= litedramcore_csr_dfi_p1_we_n;
- end
-end
-always @(*) begin
- litedramcore_master_p1_cke <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_cke <= litedramcore_ext_dfi_p1_cke;
- end else begin
- litedramcore_master_p1_cke <= litedramcore_slave_p1_cke;
- end
- end else begin
- litedramcore_master_p1_cke <= litedramcore_csr_dfi_p1_cke;
- end
-end
-always @(*) begin
- litedramcore_master_p1_odt <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_odt <= litedramcore_ext_dfi_p1_odt;
- end else begin
- litedramcore_master_p1_odt <= litedramcore_slave_p1_odt;
- end
- end else begin
- litedramcore_master_p1_odt <= litedramcore_csr_dfi_p1_odt;
- end
-end
-always @(*) begin
- litedramcore_master_p1_reset_n <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_reset_n <= litedramcore_ext_dfi_p1_reset_n;
- end else begin
- litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n;
- end
- end else begin
- litedramcore_master_p1_reset_n <= litedramcore_csr_dfi_p1_reset_n;
- end
-end
-always @(*) begin
- litedramcore_master_p1_act_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_act_n <= litedramcore_ext_dfi_p1_act_n;
- end else begin
- litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n;
- end
- end else begin
- litedramcore_master_p1_act_n <= litedramcore_csr_dfi_p1_act_n;
- end
-end
-always @(*) begin
- litedramcore_master_p1_wrdata <= 64'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_wrdata <= litedramcore_ext_dfi_p1_wrdata;
- end else begin
- litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata;
- end
- end else begin
- litedramcore_master_p1_wrdata <= litedramcore_csr_dfi_p1_wrdata;
- end
-end
-always @(*) begin
- litedramcore_master_p1_wrdata_en <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_wrdata_en <= litedramcore_ext_dfi_p1_wrdata_en;
- end else begin
- litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en;
- end
- end else begin
- litedramcore_master_p1_wrdata_en <= litedramcore_csr_dfi_p1_wrdata_en;
- end
-end
-always @(*) begin
- litedramcore_master_p1_wrdata_mask <= 8'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_wrdata_mask <= litedramcore_ext_dfi_p1_wrdata_mask;
- end else begin
- litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask;
- end
- end else begin
- litedramcore_master_p1_wrdata_mask <= litedramcore_csr_dfi_p1_wrdata_mask;
- end
-end
-always @(*) begin
- litedramcore_master_p1_rddata_en <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_rddata_en <= litedramcore_ext_dfi_p1_rddata_en;
- end else begin
- litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en;
- end
- end else begin
- litedramcore_master_p1_rddata_en <= litedramcore_csr_dfi_p1_rddata_en;
- end
-end
-always @(*) begin
- litedramcore_master_p2_address <= 15'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_address <= litedramcore_ext_dfi_p2_address;
- end else begin
- litedramcore_master_p2_address <= litedramcore_slave_p2_address;
- end
- end else begin
- litedramcore_master_p2_address <= litedramcore_csr_dfi_p2_address;
- end
-end
-always @(*) begin
- litedramcore_master_p2_bank <= 3'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_bank <= litedramcore_ext_dfi_p2_bank;
- end else begin
- litedramcore_master_p2_bank <= litedramcore_slave_p2_bank;
- end
- end else begin
- litedramcore_master_p2_bank <= litedramcore_csr_dfi_p2_bank;
- end
-end
-always @(*) begin
- litedramcore_master_p2_cas_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_cas_n <= litedramcore_ext_dfi_p2_cas_n;
- end else begin
- litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n;
- end
- end else begin
- litedramcore_master_p2_cas_n <= litedramcore_csr_dfi_p2_cas_n;
- end
-end
-always @(*) begin
- litedramcore_master_p2_cs_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_cs_n <= litedramcore_ext_dfi_p2_cs_n;
- end else begin
- litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n;
- end
- end else begin
- litedramcore_master_p2_cs_n <= litedramcore_csr_dfi_p2_cs_n;
- end
-end
-always @(*) begin
- litedramcore_master_p2_ras_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_ras_n <= litedramcore_ext_dfi_p2_ras_n;
- end else begin
- litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n;
- end
- end else begin
- litedramcore_master_p2_ras_n <= litedramcore_csr_dfi_p2_ras_n;
- end
-end
-always @(*) begin
- litedramcore_master_p2_we_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_we_n <= litedramcore_ext_dfi_p2_we_n;
- end else begin
- litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n;
- end
- end else begin
- litedramcore_master_p2_we_n <= litedramcore_csr_dfi_p2_we_n;
- end
-end
-always @(*) begin
- litedramcore_master_p2_cke <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_cke <= litedramcore_ext_dfi_p2_cke;
- end else begin
- litedramcore_master_p2_cke <= litedramcore_slave_p2_cke;
- end
- end else begin
- litedramcore_master_p2_cke <= litedramcore_csr_dfi_p2_cke;
- end
-end
-always @(*) begin
- litedramcore_master_p2_odt <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_odt <= litedramcore_ext_dfi_p2_odt;
- end else begin
- litedramcore_master_p2_odt <= litedramcore_slave_p2_odt;
- end
- end else begin
- litedramcore_master_p2_odt <= litedramcore_csr_dfi_p2_odt;
- end
-end
-always @(*) begin
- litedramcore_master_p2_reset_n <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_reset_n <= litedramcore_ext_dfi_p2_reset_n;
- end else begin
- litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n;
- end
- end else begin
- litedramcore_master_p2_reset_n <= litedramcore_csr_dfi_p2_reset_n;
- end
-end
-always @(*) begin
- litedramcore_master_p2_act_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_act_n <= litedramcore_ext_dfi_p2_act_n;
- end else begin
- litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n;
- end
- end else begin
- litedramcore_master_p2_act_n <= litedramcore_csr_dfi_p2_act_n;
- end
-end
-always @(*) begin
- litedramcore_master_p2_wrdata <= 64'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_wrdata <= litedramcore_ext_dfi_p2_wrdata;
- end else begin
- litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata;
- end
- end else begin
- litedramcore_master_p2_wrdata <= litedramcore_csr_dfi_p2_wrdata;
- end
-end
-always @(*) begin
- litedramcore_master_p2_wrdata_en <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_wrdata_en <= litedramcore_ext_dfi_p2_wrdata_en;
- end else begin
- litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en;
- end
- end else begin
- litedramcore_master_p2_wrdata_en <= litedramcore_csr_dfi_p2_wrdata_en;
- end
-end
-always @(*) begin
- litedramcore_master_p2_wrdata_mask <= 8'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_wrdata_mask <= litedramcore_ext_dfi_p2_wrdata_mask;
- end else begin
- litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask;
- end
- end else begin
- litedramcore_master_p2_wrdata_mask <= litedramcore_csr_dfi_p2_wrdata_mask;
- end
-end
-always @(*) begin
- litedramcore_master_p2_rddata_en <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_rddata_en <= litedramcore_ext_dfi_p2_rddata_en;
- end else begin
- litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en;
- end
- end else begin
- litedramcore_master_p2_rddata_en <= litedramcore_csr_dfi_p2_rddata_en;
- end
-end
-always @(*) begin
- litedramcore_master_p3_address <= 15'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_address <= litedramcore_ext_dfi_p3_address;
- end else begin
- litedramcore_master_p3_address <= litedramcore_slave_p3_address;
- end
- end else begin
- litedramcore_master_p3_address <= litedramcore_csr_dfi_p3_address;
- end
-end
-always @(*) begin
- litedramcore_master_p3_bank <= 3'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_bank <= litedramcore_ext_dfi_p3_bank;
- end else begin
- litedramcore_master_p3_bank <= litedramcore_slave_p3_bank;
- end
- end else begin
- litedramcore_master_p3_bank <= litedramcore_csr_dfi_p3_bank;
- end
-end
-always @(*) begin
- litedramcore_master_p3_cas_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_cas_n <= litedramcore_ext_dfi_p3_cas_n;
- end else begin
- litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n;
- end
- end else begin
- litedramcore_master_p3_cas_n <= litedramcore_csr_dfi_p3_cas_n;
- end
-end
-always @(*) begin
- litedramcore_master_p3_cs_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_cs_n <= litedramcore_ext_dfi_p3_cs_n;
- end else begin
- litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n;
- end
- end else begin
- litedramcore_master_p3_cs_n <= litedramcore_csr_dfi_p3_cs_n;
- end
-end
-always @(*) begin
- litedramcore_master_p3_ras_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_ras_n <= litedramcore_ext_dfi_p3_ras_n;
- end else begin
- litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n;
- end
- end else begin
- litedramcore_master_p3_ras_n <= litedramcore_csr_dfi_p3_ras_n;
- end
-end
-always @(*) begin
- litedramcore_master_p3_we_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_we_n <= litedramcore_ext_dfi_p3_we_n;
- end else begin
- litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n;
- end
- end else begin
- litedramcore_master_p3_we_n <= litedramcore_csr_dfi_p3_we_n;
- end
-end
-always @(*) begin
- litedramcore_master_p3_cke <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_cke <= litedramcore_ext_dfi_p3_cke;
- end else begin
- litedramcore_master_p3_cke <= litedramcore_slave_p3_cke;
- end
- end else begin
- litedramcore_master_p3_cke <= litedramcore_csr_dfi_p3_cke;
- end
-end
-always @(*) begin
- litedramcore_master_p3_odt <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_odt <= litedramcore_ext_dfi_p3_odt;
- end else begin
- litedramcore_master_p3_odt <= litedramcore_slave_p3_odt;
- end
- end else begin
- litedramcore_master_p3_odt <= litedramcore_csr_dfi_p3_odt;
- end
-end
-always @(*) begin
- litedramcore_master_p3_reset_n <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_reset_n <= litedramcore_ext_dfi_p3_reset_n;
- end else begin
- litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n;
- end
- end else begin
- litedramcore_master_p3_reset_n <= litedramcore_csr_dfi_p3_reset_n;
- end
-end
-always @(*) begin
- litedramcore_master_p3_act_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_act_n <= litedramcore_ext_dfi_p3_act_n;
- end else begin
- litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n;
- end
- end else begin
- litedramcore_master_p3_act_n <= litedramcore_csr_dfi_p3_act_n;
- end
-end
-always @(*) begin
- litedramcore_master_p3_wrdata <= 64'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_wrdata <= litedramcore_ext_dfi_p3_wrdata;
- end else begin
- litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata;
- end
- end else begin
- litedramcore_master_p3_wrdata <= litedramcore_csr_dfi_p3_wrdata;
- end
-end
-always @(*) begin
- litedramcore_master_p3_wrdata_en <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_wrdata_en <= litedramcore_ext_dfi_p3_wrdata_en;
- end else begin
- litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en;
- end
- end else begin
- litedramcore_master_p3_wrdata_en <= litedramcore_csr_dfi_p3_wrdata_en;
- end
-end
-always @(*) begin
- litedramcore_master_p3_wrdata_mask <= 8'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_wrdata_mask <= litedramcore_ext_dfi_p3_wrdata_mask;
- end else begin
- litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask;
- end
- end else begin
- litedramcore_master_p3_wrdata_mask <= litedramcore_csr_dfi_p3_wrdata_mask;
- end
-end
-always @(*) begin
- litedramcore_master_p3_rddata_en <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_rddata_en <= litedramcore_ext_dfi_p3_rddata_en;
- end else begin
- litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en;
- end
- end else begin
- litedramcore_master_p3_rddata_en <= litedramcore_csr_dfi_p3_rddata_en;
- end
+ litedramcore_csr_dfi_p0_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_csr_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+ end
+end
+always @(*) begin
+ litedramcore_csr_dfi_p1_rddata <= 64'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata;
+ end
+end
+always @(*) begin
+ litedramcore_csr_dfi_p1_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+ end
+end
+always @(*) begin
+ litedramcore_csr_dfi_p2_rddata <= 64'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_csr_dfi_p2_rddata <= litedramcore_master_p2_rddata;
+ end
+end
+always @(*) begin
+ litedramcore_csr_dfi_p2_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_csr_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+ end
+end
+always @(*) begin
+ litedramcore_csr_dfi_p3_rddata <= 64'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_csr_dfi_p3_rddata <= litedramcore_master_p3_rddata;
+ end
+end
+always @(*) begin
+ litedramcore_csr_dfi_p3_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_csr_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+ end
+end
+always @(*) begin
+ litedramcore_ext_dfi_p0_rddata <= 64'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_ext_dfi_p0_rddata <= litedramcore_master_p0_rddata;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_ext_dfi_p0_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_ext_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_ext_dfi_p1_rddata <= 64'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_ext_dfi_p1_rddata <= litedramcore_master_p1_rddata;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_ext_dfi_p1_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_ext_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_ext_dfi_p2_rddata <= 64'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_ext_dfi_p2_rddata <= litedramcore_master_p2_rddata;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_ext_dfi_p2_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_ext_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p0_rddata <= 64'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ end else begin
+ litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p0_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ end else begin
+ litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_ext_dfi_p3_rddata <= 64'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_ext_dfi_p3_rddata <= litedramcore_master_p3_rddata;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_ext_dfi_p3_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_ext_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p1_rddata <= 64'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ end else begin
+ litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p1_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ end else begin
+ litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p2_rddata <= 64'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ end else begin
+ litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p2_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ end else begin
+ litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p3_rddata <= 64'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ end else begin
+ litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p3_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ end else begin
+ litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_address <= 15'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_address <= litedramcore_ext_dfi_p0_address;
+ end else begin
+ litedramcore_master_p0_address <= litedramcore_slave_p0_address;
+ end
+ end else begin
+ litedramcore_master_p0_address <= litedramcore_csr_dfi_p0_address;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_bank <= 3'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_bank <= litedramcore_ext_dfi_p0_bank;
+ end else begin
+ litedramcore_master_p0_bank <= litedramcore_slave_p0_bank;
+ end
+ end else begin
+ litedramcore_master_p0_bank <= litedramcore_csr_dfi_p0_bank;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_cas_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_cas_n <= litedramcore_ext_dfi_p0_cas_n;
+ end else begin
+ litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n;
+ end
+ end else begin
+ litedramcore_master_p0_cas_n <= litedramcore_csr_dfi_p0_cas_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_cs_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n;
+ end else begin
+ litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n;
+ end
+ end else begin
+ litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_ras_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n;
+ end else begin
+ litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n;
+ end
+ end else begin
+ litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_we_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n;
+ end else begin
+ litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n;
+ end
+ end else begin
+ litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_cke <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_cke <= litedramcore_ext_dfi_p0_cke;
+ end else begin
+ litedramcore_master_p0_cke <= litedramcore_slave_p0_cke;
+ end
+ end else begin
+ litedramcore_master_p0_cke <= litedramcore_csr_dfi_p0_cke;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_odt <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_odt <= litedramcore_ext_dfi_p0_odt;
+ end else begin
+ litedramcore_master_p0_odt <= litedramcore_slave_p0_odt;
+ end
+ end else begin
+ litedramcore_master_p0_odt <= litedramcore_csr_dfi_p0_odt;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_reset_n <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_reset_n <= litedramcore_ext_dfi_p0_reset_n;
+ end else begin
+ litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n;
+ end
+ end else begin
+ litedramcore_master_p0_reset_n <= litedramcore_csr_dfi_p0_reset_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_act_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_act_n <= litedramcore_ext_dfi_p0_act_n;
+ end else begin
+ litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n;
+ end
+ end else begin
+ litedramcore_master_p0_act_n <= litedramcore_csr_dfi_p0_act_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_wrdata <= 64'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_wrdata <= litedramcore_ext_dfi_p0_wrdata;
+ end else begin
+ litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata;
+ end
+ end else begin
+ litedramcore_master_p0_wrdata <= litedramcore_csr_dfi_p0_wrdata;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_wrdata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_wrdata_en <= litedramcore_ext_dfi_p0_wrdata_en;
+ end else begin
+ litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en;
+ end
+ end else begin
+ litedramcore_master_p0_wrdata_en <= litedramcore_csr_dfi_p0_wrdata_en;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_wrdata_mask <= 8'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_wrdata_mask <= litedramcore_ext_dfi_p0_wrdata_mask;
+ end else begin
+ litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask;
+ end
+ end else begin
+ litedramcore_master_p0_wrdata_mask <= litedramcore_csr_dfi_p0_wrdata_mask;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_rddata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_rddata_en <= litedramcore_ext_dfi_p0_rddata_en;
+ end else begin
+ litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en;
+ end
+ end else begin
+ litedramcore_master_p0_rddata_en <= litedramcore_csr_dfi_p0_rddata_en;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_address <= 15'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_address <= litedramcore_ext_dfi_p1_address;
+ end else begin
+ litedramcore_master_p1_address <= litedramcore_slave_p1_address;
+ end
+ end else begin
+ litedramcore_master_p1_address <= litedramcore_csr_dfi_p1_address;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_bank <= 3'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_bank <= litedramcore_ext_dfi_p1_bank;
+ end else begin
+ litedramcore_master_p1_bank <= litedramcore_slave_p1_bank;
+ end
+ end else begin
+ litedramcore_master_p1_bank <= litedramcore_csr_dfi_p1_bank;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_cas_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_cas_n <= litedramcore_ext_dfi_p1_cas_n;
+ end else begin
+ litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n;
+ end
+ end else begin
+ litedramcore_master_p1_cas_n <= litedramcore_csr_dfi_p1_cas_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_cs_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_cs_n <= litedramcore_ext_dfi_p1_cs_n;
+ end else begin
+ litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n;
+ end
+ end else begin
+ litedramcore_master_p1_cs_n <= litedramcore_csr_dfi_p1_cs_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_ras_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_ras_n <= litedramcore_ext_dfi_p1_ras_n;
+ end else begin
+ litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n;
+ end
+ end else begin
+ litedramcore_master_p1_ras_n <= litedramcore_csr_dfi_p1_ras_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_we_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_we_n <= litedramcore_ext_dfi_p1_we_n;
+ end else begin
+ litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n;
+ end
+ end else begin
+ litedramcore_master_p1_we_n <= litedramcore_csr_dfi_p1_we_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_cke <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_cke <= litedramcore_ext_dfi_p1_cke;
+ end else begin
+ litedramcore_master_p1_cke <= litedramcore_slave_p1_cke;
+ end
+ end else begin
+ litedramcore_master_p1_cke <= litedramcore_csr_dfi_p1_cke;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_odt <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_odt <= litedramcore_ext_dfi_p1_odt;
+ end else begin
+ litedramcore_master_p1_odt <= litedramcore_slave_p1_odt;
+ end
+ end else begin
+ litedramcore_master_p1_odt <= litedramcore_csr_dfi_p1_odt;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_reset_n <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_reset_n <= litedramcore_ext_dfi_p1_reset_n;
+ end else begin
+ litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n;
+ end
+ end else begin
+ litedramcore_master_p1_reset_n <= litedramcore_csr_dfi_p1_reset_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_act_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_act_n <= litedramcore_ext_dfi_p1_act_n;
+ end else begin
+ litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n;
+ end
+ end else begin
+ litedramcore_master_p1_act_n <= litedramcore_csr_dfi_p1_act_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_wrdata <= 64'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_wrdata <= litedramcore_ext_dfi_p1_wrdata;
+ end else begin
+ litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata;
+ end
+ end else begin
+ litedramcore_master_p1_wrdata <= litedramcore_csr_dfi_p1_wrdata;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_wrdata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_wrdata_en <= litedramcore_ext_dfi_p1_wrdata_en;
+ end else begin
+ litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en;
+ end
+ end else begin
+ litedramcore_master_p1_wrdata_en <= litedramcore_csr_dfi_p1_wrdata_en;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_wrdata_mask <= 8'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_wrdata_mask <= litedramcore_ext_dfi_p1_wrdata_mask;
+ end else begin
+ litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask;
+ end
+ end else begin
+ litedramcore_master_p1_wrdata_mask <= litedramcore_csr_dfi_p1_wrdata_mask;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_rddata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_rddata_en <= litedramcore_ext_dfi_p1_rddata_en;
+ end else begin
+ litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en;
+ end
+ end else begin
+ litedramcore_master_p1_rddata_en <= litedramcore_csr_dfi_p1_rddata_en;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_address <= 15'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_address <= litedramcore_ext_dfi_p2_address;
+ end else begin
+ litedramcore_master_p2_address <= litedramcore_slave_p2_address;
+ end
+ end else begin
+ litedramcore_master_p2_address <= litedramcore_csr_dfi_p2_address;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_bank <= 3'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_bank <= litedramcore_ext_dfi_p2_bank;
+ end else begin
+ litedramcore_master_p2_bank <= litedramcore_slave_p2_bank;
+ end
+ end else begin
+ litedramcore_master_p2_bank <= litedramcore_csr_dfi_p2_bank;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_cas_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_cas_n <= litedramcore_ext_dfi_p2_cas_n;
+ end else begin
+ litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n;
+ end
+ end else begin
+ litedramcore_master_p2_cas_n <= litedramcore_csr_dfi_p2_cas_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_cs_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_cs_n <= litedramcore_ext_dfi_p2_cs_n;
+ end else begin
+ litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n;
+ end
+ end else begin
+ litedramcore_master_p2_cs_n <= litedramcore_csr_dfi_p2_cs_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_ras_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_ras_n <= litedramcore_ext_dfi_p2_ras_n;
+ end else begin
+ litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n;
+ end
+ end else begin
+ litedramcore_master_p2_ras_n <= litedramcore_csr_dfi_p2_ras_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_we_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_we_n <= litedramcore_ext_dfi_p2_we_n;
+ end else begin
+ litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n;
+ end
+ end else begin
+ litedramcore_master_p2_we_n <= litedramcore_csr_dfi_p2_we_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_cke <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_cke <= litedramcore_ext_dfi_p2_cke;
+ end else begin
+ litedramcore_master_p2_cke <= litedramcore_slave_p2_cke;
+ end
+ end else begin
+ litedramcore_master_p2_cke <= litedramcore_csr_dfi_p2_cke;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_odt <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_odt <= litedramcore_ext_dfi_p2_odt;
+ end else begin
+ litedramcore_master_p2_odt <= litedramcore_slave_p2_odt;
+ end
+ end else begin
+ litedramcore_master_p2_odt <= litedramcore_csr_dfi_p2_odt;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_reset_n <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_reset_n <= litedramcore_ext_dfi_p2_reset_n;
+ end else begin
+ litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n;
+ end
+ end else begin
+ litedramcore_master_p2_reset_n <= litedramcore_csr_dfi_p2_reset_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_act_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_act_n <= litedramcore_ext_dfi_p2_act_n;
+ end else begin
+ litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n;
+ end
+ end else begin
+ litedramcore_master_p2_act_n <= litedramcore_csr_dfi_p2_act_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_wrdata <= 64'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_wrdata <= litedramcore_ext_dfi_p2_wrdata;
+ end else begin
+ litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata;
+ end
+ end else begin
+ litedramcore_master_p2_wrdata <= litedramcore_csr_dfi_p2_wrdata;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_wrdata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_wrdata_en <= litedramcore_ext_dfi_p2_wrdata_en;
+ end else begin
+ litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en;
+ end
+ end else begin
+ litedramcore_master_p2_wrdata_en <= litedramcore_csr_dfi_p2_wrdata_en;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_wrdata_mask <= 8'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_wrdata_mask <= litedramcore_ext_dfi_p2_wrdata_mask;
+ end else begin
+ litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask;
+ end
+ end else begin
+ litedramcore_master_p2_wrdata_mask <= litedramcore_csr_dfi_p2_wrdata_mask;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_rddata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_rddata_en <= litedramcore_ext_dfi_p2_rddata_en;
+ end else begin
+ litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en;
+ end
+ end else begin
+ litedramcore_master_p2_rddata_en <= litedramcore_csr_dfi_p2_rddata_en;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_address <= 15'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_address <= litedramcore_ext_dfi_p3_address;
+ end else begin
+ litedramcore_master_p3_address <= litedramcore_slave_p3_address;
+ end
+ end else begin
+ litedramcore_master_p3_address <= litedramcore_csr_dfi_p3_address;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_bank <= 3'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_bank <= litedramcore_ext_dfi_p3_bank;
+ end else begin
+ litedramcore_master_p3_bank <= litedramcore_slave_p3_bank;
+ end
+ end else begin
+ litedramcore_master_p3_bank <= litedramcore_csr_dfi_p3_bank;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_cas_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_cas_n <= litedramcore_ext_dfi_p3_cas_n;
+ end else begin
+ litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n;
+ end
+ end else begin
+ litedramcore_master_p3_cas_n <= litedramcore_csr_dfi_p3_cas_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_cs_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_cs_n <= litedramcore_ext_dfi_p3_cs_n;
+ end else begin
+ litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n;
+ end
+ end else begin
+ litedramcore_master_p3_cs_n <= litedramcore_csr_dfi_p3_cs_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_ras_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_ras_n <= litedramcore_ext_dfi_p3_ras_n;
+ end else begin
+ litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n;
+ end
+ end else begin
+ litedramcore_master_p3_ras_n <= litedramcore_csr_dfi_p3_ras_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_we_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_we_n <= litedramcore_ext_dfi_p3_we_n;
+ end else begin
+ litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n;
+ end
+ end else begin
+ litedramcore_master_p3_we_n <= litedramcore_csr_dfi_p3_we_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_cke <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_cke <= litedramcore_ext_dfi_p3_cke;
+ end else begin
+ litedramcore_master_p3_cke <= litedramcore_slave_p3_cke;
+ end
+ end else begin
+ litedramcore_master_p3_cke <= litedramcore_csr_dfi_p3_cke;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_odt <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_odt <= litedramcore_ext_dfi_p3_odt;
+ end else begin
+ litedramcore_master_p3_odt <= litedramcore_slave_p3_odt;
+ end
+ end else begin
+ litedramcore_master_p3_odt <= litedramcore_csr_dfi_p3_odt;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_reset_n <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_reset_n <= litedramcore_ext_dfi_p3_reset_n;
+ end else begin
+ litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n;
+ end
+ end else begin
+ litedramcore_master_p3_reset_n <= litedramcore_csr_dfi_p3_reset_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_act_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_act_n <= litedramcore_ext_dfi_p3_act_n;
+ end else begin
+ litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n;
+ end
+ end else begin
+ litedramcore_master_p3_act_n <= litedramcore_csr_dfi_p3_act_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_wrdata <= 64'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_wrdata <= litedramcore_ext_dfi_p3_wrdata;
+ end else begin
+ litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata;
+ end
+ end else begin
+ litedramcore_master_p3_wrdata <= litedramcore_csr_dfi_p3_wrdata;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_wrdata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_wrdata_en <= litedramcore_ext_dfi_p3_wrdata_en;
+ end else begin
+ litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en;
+ end
+ end else begin
+ litedramcore_master_p3_wrdata_en <= litedramcore_csr_dfi_p3_wrdata_en;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_wrdata_mask <= 8'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_wrdata_mask <= litedramcore_ext_dfi_p3_wrdata_mask;
+ end else begin
+ litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask;
+ end
+ end else begin
+ litedramcore_master_p3_wrdata_mask <= litedramcore_csr_dfi_p3_wrdata_mask;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_rddata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_rddata_en <= litedramcore_ext_dfi_p3_rddata_en;
+ end else begin
+ litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en;
+ end
+ end else begin
+ litedramcore_master_p3_rddata_en <= litedramcore_csr_dfi_p3_rddata_en;
+ end
end
assign litedramcore_csr_dfi_p0_cke = litedramcore_cke;
assign litedramcore_csr_dfi_p1_cke = litedramcore_cke;
assign litedramcore_csr_dfi_p2_reset_n = litedramcore_reset_n;
assign litedramcore_csr_dfi_p3_reset_n = litedramcore_reset_n;
always @(*) begin
- litedramcore_csr_dfi_p0_cs_n <= 1'd1;
- if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}};
- end else begin
- litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}};
- end
+ litedramcore_csr_dfi_p0_cs_n <= 1'd1;
+ if (litedramcore_phaseinjector0_command_issue_re) begin
+ litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}};
+ end else begin
+ litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}};
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p0_ras_n <= 1'd1;
- if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_csr_dfi_p0_ras_n <= (~litedramcore_phaseinjector0_csrfield_ras);
- end else begin
- litedramcore_csr_dfi_p0_ras_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p0_ras_n <= 1'd1;
+ if (litedramcore_phaseinjector0_command_issue_re) begin
+ litedramcore_csr_dfi_p0_ras_n <= (~litedramcore_phaseinjector0_csrfield_ras);
+ end else begin
+ litedramcore_csr_dfi_p0_ras_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p0_we_n <= 1'd1;
- if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we);
- end else begin
- litedramcore_csr_dfi_p0_we_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p0_we_n <= 1'd1;
+ if (litedramcore_phaseinjector0_command_issue_re) begin
+ litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we);
+ end else begin
+ litedramcore_csr_dfi_p0_we_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p0_cas_n <= 1'd1;
- if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_csr_dfi_p0_cas_n <= (~litedramcore_phaseinjector0_csrfield_cas);
- end else begin
- litedramcore_csr_dfi_p0_cas_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p0_cas_n <= 1'd1;
+ if (litedramcore_phaseinjector0_command_issue_re) begin
+ litedramcore_csr_dfi_p0_cas_n <= (~litedramcore_phaseinjector0_csrfield_cas);
+ end else begin
+ litedramcore_csr_dfi_p0_cas_n <= 1'd1;
+ end
end
assign litedramcore_csr_dfi_p0_address = litedramcore_phaseinjector0_address_storage;
assign litedramcore_csr_dfi_p0_bank = litedramcore_phaseinjector0_baddress_storage;
assign litedramcore_csr_dfi_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage;
assign litedramcore_csr_dfi_p0_wrdata_mask = 1'd0;
always @(*) begin
- litedramcore_csr_dfi_p1_cs_n <= 1'd1;
- if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}};
- end else begin
- litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}};
- end
+ litedramcore_csr_dfi_p1_cs_n <= 1'd1;
+ if (litedramcore_phaseinjector1_command_issue_re) begin
+ litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}};
+ end else begin
+ litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}};
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p1_ras_n <= 1'd1;
- if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_csr_dfi_p1_ras_n <= (~litedramcore_phaseinjector1_csrfield_ras);
- end else begin
- litedramcore_csr_dfi_p1_ras_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p1_ras_n <= 1'd1;
+ if (litedramcore_phaseinjector1_command_issue_re) begin
+ litedramcore_csr_dfi_p1_ras_n <= (~litedramcore_phaseinjector1_csrfield_ras);
+ end else begin
+ litedramcore_csr_dfi_p1_ras_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p1_we_n <= 1'd1;
- if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we);
- end else begin
- litedramcore_csr_dfi_p1_we_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p1_we_n <= 1'd1;
+ if (litedramcore_phaseinjector1_command_issue_re) begin
+ litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we);
+ end else begin
+ litedramcore_csr_dfi_p1_we_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p1_cas_n <= 1'd1;
- if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_csr_dfi_p1_cas_n <= (~litedramcore_phaseinjector1_csrfield_cas);
- end else begin
- litedramcore_csr_dfi_p1_cas_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p1_cas_n <= 1'd1;
+ if (litedramcore_phaseinjector1_command_issue_re) begin
+ litedramcore_csr_dfi_p1_cas_n <= (~litedramcore_phaseinjector1_csrfield_cas);
+ end else begin
+ litedramcore_csr_dfi_p1_cas_n <= 1'd1;
+ end
end
assign litedramcore_csr_dfi_p1_address = litedramcore_phaseinjector1_address_storage;
assign litedramcore_csr_dfi_p1_bank = litedramcore_phaseinjector1_baddress_storage;
assign litedramcore_csr_dfi_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage;
assign litedramcore_csr_dfi_p1_wrdata_mask = 1'd0;
always @(*) begin
- litedramcore_csr_dfi_p2_cs_n <= 1'd1;
- if (litedramcore_phaseinjector2_command_issue_re) begin
- litedramcore_csr_dfi_p2_cs_n <= {1{(~litedramcore_phaseinjector2_csrfield_cs)}};
- end else begin
- litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}};
- end
+ litedramcore_csr_dfi_p2_cs_n <= 1'd1;
+ if (litedramcore_phaseinjector2_command_issue_re) begin
+ litedramcore_csr_dfi_p2_cs_n <= {1{(~litedramcore_phaseinjector2_csrfield_cs)}};
+ end else begin
+ litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}};
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p2_ras_n <= 1'd1;
- if (litedramcore_phaseinjector2_command_issue_re) begin
- litedramcore_csr_dfi_p2_ras_n <= (~litedramcore_phaseinjector2_csrfield_ras);
- end else begin
- litedramcore_csr_dfi_p2_ras_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p2_ras_n <= 1'd1;
+ if (litedramcore_phaseinjector2_command_issue_re) begin
+ litedramcore_csr_dfi_p2_ras_n <= (~litedramcore_phaseinjector2_csrfield_ras);
+ end else begin
+ litedramcore_csr_dfi_p2_ras_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p2_we_n <= 1'd1;
- if (litedramcore_phaseinjector2_command_issue_re) begin
- litedramcore_csr_dfi_p2_we_n <= (~litedramcore_phaseinjector2_csrfield_we);
- end else begin
- litedramcore_csr_dfi_p2_we_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p2_we_n <= 1'd1;
+ if (litedramcore_phaseinjector2_command_issue_re) begin
+ litedramcore_csr_dfi_p2_we_n <= (~litedramcore_phaseinjector2_csrfield_we);
+ end else begin
+ litedramcore_csr_dfi_p2_we_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p2_cas_n <= 1'd1;
- if (litedramcore_phaseinjector2_command_issue_re) begin
- litedramcore_csr_dfi_p2_cas_n <= (~litedramcore_phaseinjector2_csrfield_cas);
- end else begin
- litedramcore_csr_dfi_p2_cas_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p2_cas_n <= 1'd1;
+ if (litedramcore_phaseinjector2_command_issue_re) begin
+ litedramcore_csr_dfi_p2_cas_n <= (~litedramcore_phaseinjector2_csrfield_cas);
+ end else begin
+ litedramcore_csr_dfi_p2_cas_n <= 1'd1;
+ end
end
assign litedramcore_csr_dfi_p2_address = litedramcore_phaseinjector2_address_storage;
assign litedramcore_csr_dfi_p2_bank = litedramcore_phaseinjector2_baddress_storage;
assign litedramcore_csr_dfi_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage;
assign litedramcore_csr_dfi_p2_wrdata_mask = 1'd0;
always @(*) begin
- litedramcore_csr_dfi_p3_cs_n <= 1'd1;
- if (litedramcore_phaseinjector3_command_issue_re) begin
- litedramcore_csr_dfi_p3_cs_n <= {1{(~litedramcore_phaseinjector3_csrfield_cs)}};
- end else begin
- litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}};
- end
+ litedramcore_csr_dfi_p3_cs_n <= 1'd1;
+ if (litedramcore_phaseinjector3_command_issue_re) begin
+ litedramcore_csr_dfi_p3_cs_n <= {1{(~litedramcore_phaseinjector3_csrfield_cs)}};
+ end else begin
+ litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}};
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p3_ras_n <= 1'd1;
- if (litedramcore_phaseinjector3_command_issue_re) begin
- litedramcore_csr_dfi_p3_ras_n <= (~litedramcore_phaseinjector3_csrfield_ras);
- end else begin
- litedramcore_csr_dfi_p3_ras_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p3_ras_n <= 1'd1;
+ if (litedramcore_phaseinjector3_command_issue_re) begin
+ litedramcore_csr_dfi_p3_ras_n <= (~litedramcore_phaseinjector3_csrfield_ras);
+ end else begin
+ litedramcore_csr_dfi_p3_ras_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p3_we_n <= 1'd1;
- if (litedramcore_phaseinjector3_command_issue_re) begin
- litedramcore_csr_dfi_p3_we_n <= (~litedramcore_phaseinjector3_csrfield_we);
- end else begin
- litedramcore_csr_dfi_p3_we_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p3_we_n <= 1'd1;
+ if (litedramcore_phaseinjector3_command_issue_re) begin
+ litedramcore_csr_dfi_p3_we_n <= (~litedramcore_phaseinjector3_csrfield_we);
+ end else begin
+ litedramcore_csr_dfi_p3_we_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p3_cas_n <= 1'd1;
- if (litedramcore_phaseinjector3_command_issue_re) begin
- litedramcore_csr_dfi_p3_cas_n <= (~litedramcore_phaseinjector3_csrfield_cas);
- end else begin
- litedramcore_csr_dfi_p3_cas_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p3_cas_n <= 1'd1;
+ if (litedramcore_phaseinjector3_command_issue_re) begin
+ litedramcore_csr_dfi_p3_cas_n <= (~litedramcore_phaseinjector3_csrfield_cas);
+ end else begin
+ litedramcore_csr_dfi_p3_cas_n <= 1'd1;
+ end
end
assign litedramcore_csr_dfi_p3_address = litedramcore_phaseinjector3_address_storage;
assign litedramcore_csr_dfi_p3_bank = litedramcore_phaseinjector3_baddress_storage;
assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1;
assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1;
always @(*) begin
- litedramcore_refresher_next_state <= 2'd0;
- litedramcore_refresher_next_state <= litedramcore_refresher_state;
- case (litedramcore_refresher_state)
- 1'd1: begin
- if (litedramcore_cmd_ready) begin
- litedramcore_refresher_next_state <= 2'd2;
- end
- end
- 2'd2: begin
- if (litedramcore_sequencer_done0) begin
- if (litedramcore_wants_zqcs) begin
- litedramcore_refresher_next_state <= 2'd3;
- end else begin
- litedramcore_refresher_next_state <= 1'd0;
- end
- end
- end
- 2'd3: begin
- if (litedramcore_zqcs_executer_done) begin
- litedramcore_refresher_next_state <= 1'd0;
- end
- end
- default: begin
- if (1'd1) begin
- if (litedramcore_wants_refresh) begin
- litedramcore_refresher_next_state <= 1'd1;
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_cmd_valid <= 1'd0;
- case (litedramcore_refresher_state)
- 1'd1: begin
- litedramcore_cmd_valid <= 1'd1;
- end
- 2'd2: begin
- litedramcore_cmd_valid <= 1'd1;
- if (litedramcore_sequencer_done0) begin
- if (litedramcore_wants_zqcs) begin
- end else begin
- litedramcore_cmd_valid <= 1'd0;
- end
- end
- end
- 2'd3: begin
- litedramcore_cmd_valid <= 1'd1;
- if (litedramcore_zqcs_executer_done) begin
- litedramcore_cmd_valid <= 1'd0;
- end
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_zqcs_executer_start <= 1'd0;
- case (litedramcore_refresher_state)
- 1'd1: begin
- end
- 2'd2: begin
- if (litedramcore_sequencer_done0) begin
- if (litedramcore_wants_zqcs) begin
- litedramcore_zqcs_executer_start <= 1'd1;
- end else begin
- end
- end
- end
- 2'd3: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_cmd_last <= 1'd0;
- case (litedramcore_refresher_state)
- 1'd1: begin
- end
- 2'd2: begin
- if (litedramcore_sequencer_done0) begin
- if (litedramcore_wants_zqcs) begin
- end else begin
- litedramcore_cmd_last <= 1'd1;
- end
- end
- end
- 2'd3: begin
- if (litedramcore_zqcs_executer_done) begin
- litedramcore_cmd_last <= 1'd1;
- end
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_sequencer_start0 <= 1'd0;
- case (litedramcore_refresher_state)
- 1'd1: begin
- if (litedramcore_cmd_ready) begin
- litedramcore_sequencer_start0 <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- default: begin
- end
- endcase
-end
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine0_req_valid;
-assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine0_req_we;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine0_req_addr;
-assign litedramcore_bankmachine0_cmd_buffer_sink_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine0_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine0_cmd_buffer_sink_first = litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine0_cmd_buffer_sink_last = litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine0_cmd_buffer_sink_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine0_cmd_buffer_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid);
-assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine0_cmd_buffer_source_valid);
-assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]);
+ litedramcore_refresher_next_state <= 2'd0;
+ litedramcore_refresher_next_state <= litedramcore_refresher_state;
+ case (litedramcore_refresher_state)
+ 1'd1: begin
+ if (litedramcore_cmd_ready) begin
+ litedramcore_refresher_next_state <= 2'd2;
+ end
+ end
+ 2'd2: begin
+ if (litedramcore_sequencer_done0) begin
+ if (litedramcore_wants_zqcs) begin
+ litedramcore_refresher_next_state <= 2'd3;
+ end else begin
+ litedramcore_refresher_next_state <= 1'd0;
+ end
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_zqcs_executer_done) begin
+ litedramcore_refresher_next_state <= 1'd0;
+ end
+ end
+ default: begin
+ if (1'd1) begin
+ if (litedramcore_wants_refresh) begin
+ litedramcore_refresher_next_state <= 1'd1;
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_cmd_valid <= 1'd0;
+ case (litedramcore_refresher_state)
+ 1'd1: begin
+ litedramcore_cmd_valid <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_cmd_valid <= 1'd1;
+ if (litedramcore_sequencer_done0) begin
+ if (litedramcore_wants_zqcs) begin
+ end else begin
+ litedramcore_cmd_valid <= 1'd0;
+ end
+ end
+ end
+ 2'd3: begin
+ litedramcore_cmd_valid <= 1'd1;
+ if (litedramcore_zqcs_executer_done) begin
+ litedramcore_cmd_valid <= 1'd0;
+ end
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_zqcs_executer_start <= 1'd0;
+ case (litedramcore_refresher_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ if (litedramcore_sequencer_done0) begin
+ if (litedramcore_wants_zqcs) begin
+ litedramcore_zqcs_executer_start <= 1'd1;
+ end else begin
+ end
+ end
+ end
+ 2'd3: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_cmd_last <= 1'd0;
+ case (litedramcore_refresher_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ if (litedramcore_sequencer_done0) begin
+ if (litedramcore_wants_zqcs) begin
+ end else begin
+ litedramcore_cmd_last <= 1'd1;
+ end
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_zqcs_executer_done) begin
+ litedramcore_cmd_last <= 1'd1;
+ end
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_sequencer_start0 <= 1'd0;
+ case (litedramcore_refresher_state)
+ 1'd1: begin
+ if (litedramcore_cmd_ready) begin
+ litedramcore_sequencer_start0 <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ default: begin
+ end
+ endcase
+end
+assign litedramcore_bankmachine0_sink_valid = litedramcore_bankmachine0_req_valid;
+assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_sink_ready;
+assign litedramcore_bankmachine0_sink_payload_we = litedramcore_bankmachine0_req_we;
+assign litedramcore_bankmachine0_sink_payload_addr = litedramcore_bankmachine0_req_addr;
+assign litedramcore_bankmachine0_sink_sink_valid = litedramcore_bankmachine0_source_valid;
+assign litedramcore_bankmachine0_source_ready = litedramcore_bankmachine0_sink_sink_ready;
+assign litedramcore_bankmachine0_sink_sink_first = litedramcore_bankmachine0_source_first;
+assign litedramcore_bankmachine0_sink_sink_last = litedramcore_bankmachine0_source_last;
+assign litedramcore_bankmachine0_sink_sink_payload_we = litedramcore_bankmachine0_source_payload_we;
+assign litedramcore_bankmachine0_sink_sink_payload_addr = litedramcore_bankmachine0_source_payload_addr;
+assign litedramcore_bankmachine0_source_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid);
+assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_source_valid | litedramcore_bankmachine0_source_source_valid);
+assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_source_source_payload_addr[21:7]);
assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
always @(*) begin
- litedramcore_bankmachine0_cmd_payload_a <= 15'd0;
- if (litedramcore_bankmachine0_row_col_n_addr_sel) begin
- litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7];
- end else begin
- litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine0_cmd_payload_a <= 15'd0;
+ if (litedramcore_bankmachine0_row_col_n_addr_sel) begin
+ litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_source_source_payload_addr[21:7];
+ end else begin
+ litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write);
assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
always @(*) begin
- litedramcore_bankmachine0_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine0_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7])) begin
- litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine0_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | litedramcore_bankmachine0_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re);
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine0_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine0_next_state <= 4'd0;
- litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- if (litedramcore_bankmachine0_cmd_ready) begin
- litedramcore_bankmachine0_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- if (litedramcore_bankmachine0_cmd_ready) begin
- litedramcore_bankmachine0_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine0_refresh_req)) begin
- litedramcore_bankmachine0_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine0_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine0_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine0_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine0_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- litedramcore_bankmachine0_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin
- litedramcore_bankmachine0_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine0_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine0_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine0_twtpcon_ready) begin
- litedramcore_bankmachine0_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- litedramcore_bankmachine0_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_row_open <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_row_close <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- litedramcore_bankmachine0_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine0_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine0_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine1_req_valid;
-assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine1_req_we;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine1_req_addr;
-assign litedramcore_bankmachine1_cmd_buffer_sink_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine1_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine1_cmd_buffer_sink_first = litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine1_cmd_buffer_sink_last = litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine1_cmd_buffer_sink_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine1_cmd_buffer_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid);
-assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine1_cmd_buffer_source_valid);
-assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]);
+ litedramcore_bankmachine0_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine0_source_valid & litedramcore_bankmachine0_source_source_valid)) begin
+ if ((litedramcore_bankmachine0_source_payload_addr[21:7] != litedramcore_bankmachine0_source_source_payload_addr[21:7])) begin
+ litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine0_syncfifo0_din = {litedramcore_bankmachine0_fifo_in_last, litedramcore_bankmachine0_fifo_in_first, litedramcore_bankmachine0_fifo_in_payload_addr, litedramcore_bankmachine0_fifo_in_payload_we};
+assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout;
+assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout;
+assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout;
+assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout;
+assign litedramcore_bankmachine0_sink_ready = litedramcore_bankmachine0_syncfifo0_writable;
+assign litedramcore_bankmachine0_syncfifo0_we = litedramcore_bankmachine0_sink_valid;
+assign litedramcore_bankmachine0_fifo_in_first = litedramcore_bankmachine0_sink_first;
+assign litedramcore_bankmachine0_fifo_in_last = litedramcore_bankmachine0_sink_last;
+assign litedramcore_bankmachine0_fifo_in_payload_we = litedramcore_bankmachine0_sink_payload_we;
+assign litedramcore_bankmachine0_fifo_in_payload_addr = litedramcore_bankmachine0_sink_payload_addr;
+assign litedramcore_bankmachine0_source_valid = litedramcore_bankmachine0_syncfifo0_readable;
+assign litedramcore_bankmachine0_source_first = litedramcore_bankmachine0_fifo_out_first;
+assign litedramcore_bankmachine0_source_last = litedramcore_bankmachine0_fifo_out_last;
+assign litedramcore_bankmachine0_source_payload_we = litedramcore_bankmachine0_fifo_out_payload_we;
+assign litedramcore_bankmachine0_source_payload_addr = litedramcore_bankmachine0_fifo_out_payload_addr;
+assign litedramcore_bankmachine0_syncfifo0_re = litedramcore_bankmachine0_source_ready;
+always @(*) begin
+ litedramcore_bankmachine0_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine0_replace) begin
+ litedramcore_bankmachine0_wrport_adr <= (litedramcore_bankmachine0_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine0_wrport_adr <= litedramcore_bankmachine0_produce;
+ end
+end
+assign litedramcore_bankmachine0_wrport_dat_w = litedramcore_bankmachine0_syncfifo0_din;
+assign litedramcore_bankmachine0_wrport_we = (litedramcore_bankmachine0_syncfifo0_we & (litedramcore_bankmachine0_syncfifo0_writable | litedramcore_bankmachine0_replace));
+assign litedramcore_bankmachine0_do_read = (litedramcore_bankmachine0_syncfifo0_readable & litedramcore_bankmachine0_syncfifo0_re);
+assign litedramcore_bankmachine0_rdport_adr = litedramcore_bankmachine0_consume;
+assign litedramcore_bankmachine0_syncfifo0_dout = litedramcore_bankmachine0_rdport_dat_r;
+assign litedramcore_bankmachine0_syncfifo0_writable = (litedramcore_bankmachine0_level != 5'd16);
+assign litedramcore_bankmachine0_syncfifo0_readable = (litedramcore_bankmachine0_level != 1'd0);
+assign litedramcore_bankmachine0_pipe_valid_sink_ready = ((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready);
+assign litedramcore_bankmachine0_pipe_valid_sink_valid = litedramcore_bankmachine0_sink_sink_valid;
+assign litedramcore_bankmachine0_sink_sink_ready = litedramcore_bankmachine0_pipe_valid_sink_ready;
+assign litedramcore_bankmachine0_pipe_valid_sink_first = litedramcore_bankmachine0_sink_sink_first;
+assign litedramcore_bankmachine0_pipe_valid_sink_last = litedramcore_bankmachine0_sink_sink_last;
+assign litedramcore_bankmachine0_pipe_valid_sink_payload_we = litedramcore_bankmachine0_sink_sink_payload_we;
+assign litedramcore_bankmachine0_pipe_valid_sink_payload_addr = litedramcore_bankmachine0_sink_sink_payload_addr;
+assign litedramcore_bankmachine0_source_source_valid = litedramcore_bankmachine0_pipe_valid_source_valid;
+assign litedramcore_bankmachine0_pipe_valid_source_ready = litedramcore_bankmachine0_source_source_ready;
+assign litedramcore_bankmachine0_source_source_first = litedramcore_bankmachine0_pipe_valid_source_first;
+assign litedramcore_bankmachine0_source_source_last = litedramcore_bankmachine0_pipe_valid_source_last;
+assign litedramcore_bankmachine0_source_source_payload_we = litedramcore_bankmachine0_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine0_source_source_payload_addr = litedramcore_bankmachine0_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine0_next_state <= 4'd0;
+ litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ if (litedramcore_bankmachine0_cmd_ready) begin
+ litedramcore_bankmachine0_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ if (litedramcore_bankmachine0_cmd_ready) begin
+ litedramcore_bankmachine0_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine0_refresh_req)) begin
+ litedramcore_bankmachine0_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine0_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine0_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine0_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine0_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ litedramcore_bankmachine0_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin
+ litedramcore_bankmachine0_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine0_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine0_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if (litedramcore_bankmachine0_source_source_payload_we) begin
+ litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if (litedramcore_bankmachine0_source_source_payload_we) begin
+ litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if (litedramcore_bankmachine0_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine0_twtpcon_ready) begin
+ litedramcore_bankmachine0_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_row_open <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ litedramcore_bankmachine0_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_row_close <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ litedramcore_bankmachine0_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine0_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine0_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if (litedramcore_bankmachine0_source_source_payload_we) begin
+ litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if (litedramcore_bankmachine0_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+assign litedramcore_bankmachine1_sink_valid = litedramcore_bankmachine1_req_valid;
+assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_sink_ready;
+assign litedramcore_bankmachine1_sink_payload_we = litedramcore_bankmachine1_req_we;
+assign litedramcore_bankmachine1_sink_payload_addr = litedramcore_bankmachine1_req_addr;
+assign litedramcore_bankmachine1_sink_sink_valid = litedramcore_bankmachine1_source_valid;
+assign litedramcore_bankmachine1_source_ready = litedramcore_bankmachine1_sink_sink_ready;
+assign litedramcore_bankmachine1_sink_sink_first = litedramcore_bankmachine1_source_first;
+assign litedramcore_bankmachine1_sink_sink_last = litedramcore_bankmachine1_source_last;
+assign litedramcore_bankmachine1_sink_sink_payload_we = litedramcore_bankmachine1_source_payload_we;
+assign litedramcore_bankmachine1_sink_sink_payload_addr = litedramcore_bankmachine1_source_payload_addr;
+assign litedramcore_bankmachine1_source_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid);
+assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_source_valid | litedramcore_bankmachine1_source_source_valid);
+assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_source_source_payload_addr[21:7]);
assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
always @(*) begin
- litedramcore_bankmachine1_cmd_payload_a <= 15'd0;
- if (litedramcore_bankmachine1_row_col_n_addr_sel) begin
- litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7];
- end else begin
- litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine1_cmd_payload_a <= 15'd0;
+ if (litedramcore_bankmachine1_row_col_n_addr_sel) begin
+ litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_source_source_payload_addr[21:7];
+ end else begin
+ litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write);
assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
always @(*) begin
- litedramcore_bankmachine1_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine1_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7])) begin
- litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine1_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | litedramcore_bankmachine1_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re);
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine1_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine1_next_state <= 4'd0;
- litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- if (litedramcore_bankmachine1_cmd_ready) begin
- litedramcore_bankmachine1_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- if (litedramcore_bankmachine1_cmd_ready) begin
- litedramcore_bankmachine1_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine1_refresh_req)) begin
- litedramcore_bankmachine1_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine1_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine1_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine1_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine1_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- litedramcore_bankmachine1_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin
- litedramcore_bankmachine1_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine1_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine1_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine1_twtpcon_ready) begin
- litedramcore_bankmachine1_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_row_open <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_row_close <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- litedramcore_bankmachine1_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine1_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine1_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine2_req_valid;
-assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine2_req_we;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine2_req_addr;
-assign litedramcore_bankmachine2_cmd_buffer_sink_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine2_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine2_cmd_buffer_sink_first = litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine2_cmd_buffer_sink_last = litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine2_cmd_buffer_sink_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine2_cmd_buffer_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid);
-assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine2_cmd_buffer_source_valid);
-assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]);
+ litedramcore_bankmachine1_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine1_source_valid & litedramcore_bankmachine1_source_source_valid)) begin
+ if ((litedramcore_bankmachine1_source_payload_addr[21:7] != litedramcore_bankmachine1_source_source_payload_addr[21:7])) begin
+ litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine1_syncfifo1_din = {litedramcore_bankmachine1_fifo_in_last, litedramcore_bankmachine1_fifo_in_first, litedramcore_bankmachine1_fifo_in_payload_addr, litedramcore_bankmachine1_fifo_in_payload_we};
+assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout;
+assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout;
+assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout;
+assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout;
+assign litedramcore_bankmachine1_sink_ready = litedramcore_bankmachine1_syncfifo1_writable;
+assign litedramcore_bankmachine1_syncfifo1_we = litedramcore_bankmachine1_sink_valid;
+assign litedramcore_bankmachine1_fifo_in_first = litedramcore_bankmachine1_sink_first;
+assign litedramcore_bankmachine1_fifo_in_last = litedramcore_bankmachine1_sink_last;
+assign litedramcore_bankmachine1_fifo_in_payload_we = litedramcore_bankmachine1_sink_payload_we;
+assign litedramcore_bankmachine1_fifo_in_payload_addr = litedramcore_bankmachine1_sink_payload_addr;
+assign litedramcore_bankmachine1_source_valid = litedramcore_bankmachine1_syncfifo1_readable;
+assign litedramcore_bankmachine1_source_first = litedramcore_bankmachine1_fifo_out_first;
+assign litedramcore_bankmachine1_source_last = litedramcore_bankmachine1_fifo_out_last;
+assign litedramcore_bankmachine1_source_payload_we = litedramcore_bankmachine1_fifo_out_payload_we;
+assign litedramcore_bankmachine1_source_payload_addr = litedramcore_bankmachine1_fifo_out_payload_addr;
+assign litedramcore_bankmachine1_syncfifo1_re = litedramcore_bankmachine1_source_ready;
+always @(*) begin
+ litedramcore_bankmachine1_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine1_replace) begin
+ litedramcore_bankmachine1_wrport_adr <= (litedramcore_bankmachine1_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine1_wrport_adr <= litedramcore_bankmachine1_produce;
+ end
+end
+assign litedramcore_bankmachine1_wrport_dat_w = litedramcore_bankmachine1_syncfifo1_din;
+assign litedramcore_bankmachine1_wrport_we = (litedramcore_bankmachine1_syncfifo1_we & (litedramcore_bankmachine1_syncfifo1_writable | litedramcore_bankmachine1_replace));
+assign litedramcore_bankmachine1_do_read = (litedramcore_bankmachine1_syncfifo1_readable & litedramcore_bankmachine1_syncfifo1_re);
+assign litedramcore_bankmachine1_rdport_adr = litedramcore_bankmachine1_consume;
+assign litedramcore_bankmachine1_syncfifo1_dout = litedramcore_bankmachine1_rdport_dat_r;
+assign litedramcore_bankmachine1_syncfifo1_writable = (litedramcore_bankmachine1_level != 5'd16);
+assign litedramcore_bankmachine1_syncfifo1_readable = (litedramcore_bankmachine1_level != 1'd0);
+assign litedramcore_bankmachine1_pipe_valid_sink_ready = ((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready);
+assign litedramcore_bankmachine1_pipe_valid_sink_valid = litedramcore_bankmachine1_sink_sink_valid;
+assign litedramcore_bankmachine1_sink_sink_ready = litedramcore_bankmachine1_pipe_valid_sink_ready;
+assign litedramcore_bankmachine1_pipe_valid_sink_first = litedramcore_bankmachine1_sink_sink_first;
+assign litedramcore_bankmachine1_pipe_valid_sink_last = litedramcore_bankmachine1_sink_sink_last;
+assign litedramcore_bankmachine1_pipe_valid_sink_payload_we = litedramcore_bankmachine1_sink_sink_payload_we;
+assign litedramcore_bankmachine1_pipe_valid_sink_payload_addr = litedramcore_bankmachine1_sink_sink_payload_addr;
+assign litedramcore_bankmachine1_source_source_valid = litedramcore_bankmachine1_pipe_valid_source_valid;
+assign litedramcore_bankmachine1_pipe_valid_source_ready = litedramcore_bankmachine1_source_source_ready;
+assign litedramcore_bankmachine1_source_source_first = litedramcore_bankmachine1_pipe_valid_source_first;
+assign litedramcore_bankmachine1_source_source_last = litedramcore_bankmachine1_pipe_valid_source_last;
+assign litedramcore_bankmachine1_source_source_payload_we = litedramcore_bankmachine1_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine1_source_source_payload_addr = litedramcore_bankmachine1_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine1_next_state <= 4'd0;
+ litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ if (litedramcore_bankmachine1_cmd_ready) begin
+ litedramcore_bankmachine1_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ if (litedramcore_bankmachine1_cmd_ready) begin
+ litedramcore_bankmachine1_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine1_refresh_req)) begin
+ litedramcore_bankmachine1_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine1_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine1_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine1_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine1_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ litedramcore_bankmachine1_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin
+ litedramcore_bankmachine1_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine1_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine1_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_row_open <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ litedramcore_bankmachine1_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_row_close <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ litedramcore_bankmachine1_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine1_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine1_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine1_twtpcon_ready) begin
+ litedramcore_bankmachine1_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if (litedramcore_bankmachine1_source_source_payload_we) begin
+ litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if (litedramcore_bankmachine1_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if (litedramcore_bankmachine1_source_source_payload_we) begin
+ litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if (litedramcore_bankmachine1_source_source_payload_we) begin
+ litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if (litedramcore_bankmachine1_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+assign litedramcore_bankmachine2_sink_valid = litedramcore_bankmachine2_req_valid;
+assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_sink_ready;
+assign litedramcore_bankmachine2_sink_payload_we = litedramcore_bankmachine2_req_we;
+assign litedramcore_bankmachine2_sink_payload_addr = litedramcore_bankmachine2_req_addr;
+assign litedramcore_bankmachine2_sink_sink_valid = litedramcore_bankmachine2_source_valid;
+assign litedramcore_bankmachine2_source_ready = litedramcore_bankmachine2_sink_sink_ready;
+assign litedramcore_bankmachine2_sink_sink_first = litedramcore_bankmachine2_source_first;
+assign litedramcore_bankmachine2_sink_sink_last = litedramcore_bankmachine2_source_last;
+assign litedramcore_bankmachine2_sink_sink_payload_we = litedramcore_bankmachine2_source_payload_we;
+assign litedramcore_bankmachine2_sink_sink_payload_addr = litedramcore_bankmachine2_source_payload_addr;
+assign litedramcore_bankmachine2_source_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid);
+assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_source_valid | litedramcore_bankmachine2_source_source_valid);
+assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_source_source_payload_addr[21:7]);
assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
always @(*) begin
- litedramcore_bankmachine2_cmd_payload_a <= 15'd0;
- if (litedramcore_bankmachine2_row_col_n_addr_sel) begin
- litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7];
- end else begin
- litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine2_cmd_payload_a <= 15'd0;
+ if (litedramcore_bankmachine2_row_col_n_addr_sel) begin
+ litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_source_source_payload_addr[21:7];
+ end else begin
+ litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write);
assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
always @(*) begin
- litedramcore_bankmachine2_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine2_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7])) begin
- litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine2_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | litedramcore_bankmachine2_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re);
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine2_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine2_next_state <= 4'd0;
- litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- if (litedramcore_bankmachine2_cmd_ready) begin
- litedramcore_bankmachine2_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- if (litedramcore_bankmachine2_cmd_ready) begin
- litedramcore_bankmachine2_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine2_refresh_req)) begin
- litedramcore_bankmachine2_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine2_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine2_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine2_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine2_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- litedramcore_bankmachine2_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin
- litedramcore_bankmachine2_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine2_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine2_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine2_twtpcon_ready) begin
- litedramcore_bankmachine2_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- litedramcore_bankmachine2_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_row_open <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_row_close <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- litedramcore_bankmachine2_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine2_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine2_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine3_req_valid;
-assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine3_req_we;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine3_req_addr;
-assign litedramcore_bankmachine3_cmd_buffer_sink_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine3_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine3_cmd_buffer_sink_first = litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine3_cmd_buffer_sink_last = litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine3_cmd_buffer_sink_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine3_cmd_buffer_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid);
-assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine3_cmd_buffer_source_valid);
-assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]);
+ litedramcore_bankmachine2_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine2_source_valid & litedramcore_bankmachine2_source_source_valid)) begin
+ if ((litedramcore_bankmachine2_source_payload_addr[21:7] != litedramcore_bankmachine2_source_source_payload_addr[21:7])) begin
+ litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine2_syncfifo2_din = {litedramcore_bankmachine2_fifo_in_last, litedramcore_bankmachine2_fifo_in_first, litedramcore_bankmachine2_fifo_in_payload_addr, litedramcore_bankmachine2_fifo_in_payload_we};
+assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout;
+assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout;
+assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout;
+assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout;
+assign litedramcore_bankmachine2_sink_ready = litedramcore_bankmachine2_syncfifo2_writable;
+assign litedramcore_bankmachine2_syncfifo2_we = litedramcore_bankmachine2_sink_valid;
+assign litedramcore_bankmachine2_fifo_in_first = litedramcore_bankmachine2_sink_first;
+assign litedramcore_bankmachine2_fifo_in_last = litedramcore_bankmachine2_sink_last;
+assign litedramcore_bankmachine2_fifo_in_payload_we = litedramcore_bankmachine2_sink_payload_we;
+assign litedramcore_bankmachine2_fifo_in_payload_addr = litedramcore_bankmachine2_sink_payload_addr;
+assign litedramcore_bankmachine2_source_valid = litedramcore_bankmachine2_syncfifo2_readable;
+assign litedramcore_bankmachine2_source_first = litedramcore_bankmachine2_fifo_out_first;
+assign litedramcore_bankmachine2_source_last = litedramcore_bankmachine2_fifo_out_last;
+assign litedramcore_bankmachine2_source_payload_we = litedramcore_bankmachine2_fifo_out_payload_we;
+assign litedramcore_bankmachine2_source_payload_addr = litedramcore_bankmachine2_fifo_out_payload_addr;
+assign litedramcore_bankmachine2_syncfifo2_re = litedramcore_bankmachine2_source_ready;
+always @(*) begin
+ litedramcore_bankmachine2_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine2_replace) begin
+ litedramcore_bankmachine2_wrport_adr <= (litedramcore_bankmachine2_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine2_wrport_adr <= litedramcore_bankmachine2_produce;
+ end
+end
+assign litedramcore_bankmachine2_wrport_dat_w = litedramcore_bankmachine2_syncfifo2_din;
+assign litedramcore_bankmachine2_wrport_we = (litedramcore_bankmachine2_syncfifo2_we & (litedramcore_bankmachine2_syncfifo2_writable | litedramcore_bankmachine2_replace));
+assign litedramcore_bankmachine2_do_read = (litedramcore_bankmachine2_syncfifo2_readable & litedramcore_bankmachine2_syncfifo2_re);
+assign litedramcore_bankmachine2_rdport_adr = litedramcore_bankmachine2_consume;
+assign litedramcore_bankmachine2_syncfifo2_dout = litedramcore_bankmachine2_rdport_dat_r;
+assign litedramcore_bankmachine2_syncfifo2_writable = (litedramcore_bankmachine2_level != 5'd16);
+assign litedramcore_bankmachine2_syncfifo2_readable = (litedramcore_bankmachine2_level != 1'd0);
+assign litedramcore_bankmachine2_pipe_valid_sink_ready = ((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready);
+assign litedramcore_bankmachine2_pipe_valid_sink_valid = litedramcore_bankmachine2_sink_sink_valid;
+assign litedramcore_bankmachine2_sink_sink_ready = litedramcore_bankmachine2_pipe_valid_sink_ready;
+assign litedramcore_bankmachine2_pipe_valid_sink_first = litedramcore_bankmachine2_sink_sink_first;
+assign litedramcore_bankmachine2_pipe_valid_sink_last = litedramcore_bankmachine2_sink_sink_last;
+assign litedramcore_bankmachine2_pipe_valid_sink_payload_we = litedramcore_bankmachine2_sink_sink_payload_we;
+assign litedramcore_bankmachine2_pipe_valid_sink_payload_addr = litedramcore_bankmachine2_sink_sink_payload_addr;
+assign litedramcore_bankmachine2_source_source_valid = litedramcore_bankmachine2_pipe_valid_source_valid;
+assign litedramcore_bankmachine2_pipe_valid_source_ready = litedramcore_bankmachine2_source_source_ready;
+assign litedramcore_bankmachine2_source_source_first = litedramcore_bankmachine2_pipe_valid_source_first;
+assign litedramcore_bankmachine2_source_source_last = litedramcore_bankmachine2_pipe_valid_source_last;
+assign litedramcore_bankmachine2_source_source_payload_we = litedramcore_bankmachine2_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine2_source_source_payload_addr = litedramcore_bankmachine2_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine2_next_state <= 4'd0;
+ litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ if (litedramcore_bankmachine2_cmd_ready) begin
+ litedramcore_bankmachine2_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ if (litedramcore_bankmachine2_cmd_ready) begin
+ litedramcore_bankmachine2_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine2_refresh_req)) begin
+ litedramcore_bankmachine2_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine2_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine2_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine2_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine2_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ litedramcore_bankmachine2_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin
+ litedramcore_bankmachine2_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine2_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine2_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if (litedramcore_bankmachine2_source_source_payload_we) begin
+ litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if (litedramcore_bankmachine2_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if (litedramcore_bankmachine2_source_source_payload_we) begin
+ litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if (litedramcore_bankmachine2_source_source_payload_we) begin
+ litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if (litedramcore_bankmachine2_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine2_twtpcon_ready) begin
+ litedramcore_bankmachine2_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_row_open <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ litedramcore_bankmachine2_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_row_close <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ litedramcore_bankmachine2_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine2_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine2_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+assign litedramcore_bankmachine3_sink_valid = litedramcore_bankmachine3_req_valid;
+assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_sink_ready;
+assign litedramcore_bankmachine3_sink_payload_we = litedramcore_bankmachine3_req_we;
+assign litedramcore_bankmachine3_sink_payload_addr = litedramcore_bankmachine3_req_addr;
+assign litedramcore_bankmachine3_sink_sink_valid = litedramcore_bankmachine3_source_valid;
+assign litedramcore_bankmachine3_source_ready = litedramcore_bankmachine3_sink_sink_ready;
+assign litedramcore_bankmachine3_sink_sink_first = litedramcore_bankmachine3_source_first;
+assign litedramcore_bankmachine3_sink_sink_last = litedramcore_bankmachine3_source_last;
+assign litedramcore_bankmachine3_sink_sink_payload_we = litedramcore_bankmachine3_source_payload_we;
+assign litedramcore_bankmachine3_sink_sink_payload_addr = litedramcore_bankmachine3_source_payload_addr;
+assign litedramcore_bankmachine3_source_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid);
+assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_source_valid | litedramcore_bankmachine3_source_source_valid);
+assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_source_source_payload_addr[21:7]);
assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
always @(*) begin
- litedramcore_bankmachine3_cmd_payload_a <= 15'd0;
- if (litedramcore_bankmachine3_row_col_n_addr_sel) begin
- litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7];
- end else begin
- litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine3_cmd_payload_a <= 15'd0;
+ if (litedramcore_bankmachine3_row_col_n_addr_sel) begin
+ litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_source_source_payload_addr[21:7];
+ end else begin
+ litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write);
assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
always @(*) begin
- litedramcore_bankmachine3_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine3_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7])) begin
- litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine3_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | litedramcore_bankmachine3_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re);
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine3_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine3_next_state <= 4'd0;
- litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- if (litedramcore_bankmachine3_cmd_ready) begin
- litedramcore_bankmachine3_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- if (litedramcore_bankmachine3_cmd_ready) begin
- litedramcore_bankmachine3_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine3_refresh_req)) begin
- litedramcore_bankmachine3_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine3_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine3_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine3_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine3_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- litedramcore_bankmachine3_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin
- litedramcore_bankmachine3_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine3_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine3_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine3_twtpcon_ready) begin
- litedramcore_bankmachine3_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- litedramcore_bankmachine3_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_row_open <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_row_close <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- litedramcore_bankmachine3_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine3_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine3_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine4_req_valid;
-assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine4_req_we;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine4_req_addr;
-assign litedramcore_bankmachine4_cmd_buffer_sink_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine4_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine4_cmd_buffer_sink_first = litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine4_cmd_buffer_sink_last = litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine4_cmd_buffer_sink_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine4_cmd_buffer_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid);
-assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine4_cmd_buffer_source_valid);
-assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]);
+ litedramcore_bankmachine3_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine3_source_valid & litedramcore_bankmachine3_source_source_valid)) begin
+ if ((litedramcore_bankmachine3_source_payload_addr[21:7] != litedramcore_bankmachine3_source_source_payload_addr[21:7])) begin
+ litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine3_syncfifo3_din = {litedramcore_bankmachine3_fifo_in_last, litedramcore_bankmachine3_fifo_in_first, litedramcore_bankmachine3_fifo_in_payload_addr, litedramcore_bankmachine3_fifo_in_payload_we};
+assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout;
+assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout;
+assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout;
+assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout;
+assign litedramcore_bankmachine3_sink_ready = litedramcore_bankmachine3_syncfifo3_writable;
+assign litedramcore_bankmachine3_syncfifo3_we = litedramcore_bankmachine3_sink_valid;
+assign litedramcore_bankmachine3_fifo_in_first = litedramcore_bankmachine3_sink_first;
+assign litedramcore_bankmachine3_fifo_in_last = litedramcore_bankmachine3_sink_last;
+assign litedramcore_bankmachine3_fifo_in_payload_we = litedramcore_bankmachine3_sink_payload_we;
+assign litedramcore_bankmachine3_fifo_in_payload_addr = litedramcore_bankmachine3_sink_payload_addr;
+assign litedramcore_bankmachine3_source_valid = litedramcore_bankmachine3_syncfifo3_readable;
+assign litedramcore_bankmachine3_source_first = litedramcore_bankmachine3_fifo_out_first;
+assign litedramcore_bankmachine3_source_last = litedramcore_bankmachine3_fifo_out_last;
+assign litedramcore_bankmachine3_source_payload_we = litedramcore_bankmachine3_fifo_out_payload_we;
+assign litedramcore_bankmachine3_source_payload_addr = litedramcore_bankmachine3_fifo_out_payload_addr;
+assign litedramcore_bankmachine3_syncfifo3_re = litedramcore_bankmachine3_source_ready;
+always @(*) begin
+ litedramcore_bankmachine3_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine3_replace) begin
+ litedramcore_bankmachine3_wrport_adr <= (litedramcore_bankmachine3_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine3_wrport_adr <= litedramcore_bankmachine3_produce;
+ end
+end
+assign litedramcore_bankmachine3_wrport_dat_w = litedramcore_bankmachine3_syncfifo3_din;
+assign litedramcore_bankmachine3_wrport_we = (litedramcore_bankmachine3_syncfifo3_we & (litedramcore_bankmachine3_syncfifo3_writable | litedramcore_bankmachine3_replace));
+assign litedramcore_bankmachine3_do_read = (litedramcore_bankmachine3_syncfifo3_readable & litedramcore_bankmachine3_syncfifo3_re);
+assign litedramcore_bankmachine3_rdport_adr = litedramcore_bankmachine3_consume;
+assign litedramcore_bankmachine3_syncfifo3_dout = litedramcore_bankmachine3_rdport_dat_r;
+assign litedramcore_bankmachine3_syncfifo3_writable = (litedramcore_bankmachine3_level != 5'd16);
+assign litedramcore_bankmachine3_syncfifo3_readable = (litedramcore_bankmachine3_level != 1'd0);
+assign litedramcore_bankmachine3_pipe_valid_sink_ready = ((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready);
+assign litedramcore_bankmachine3_pipe_valid_sink_valid = litedramcore_bankmachine3_sink_sink_valid;
+assign litedramcore_bankmachine3_sink_sink_ready = litedramcore_bankmachine3_pipe_valid_sink_ready;
+assign litedramcore_bankmachine3_pipe_valid_sink_first = litedramcore_bankmachine3_sink_sink_first;
+assign litedramcore_bankmachine3_pipe_valid_sink_last = litedramcore_bankmachine3_sink_sink_last;
+assign litedramcore_bankmachine3_pipe_valid_sink_payload_we = litedramcore_bankmachine3_sink_sink_payload_we;
+assign litedramcore_bankmachine3_pipe_valid_sink_payload_addr = litedramcore_bankmachine3_sink_sink_payload_addr;
+assign litedramcore_bankmachine3_source_source_valid = litedramcore_bankmachine3_pipe_valid_source_valid;
+assign litedramcore_bankmachine3_pipe_valid_source_ready = litedramcore_bankmachine3_source_source_ready;
+assign litedramcore_bankmachine3_source_source_first = litedramcore_bankmachine3_pipe_valid_source_first;
+assign litedramcore_bankmachine3_source_source_last = litedramcore_bankmachine3_pipe_valid_source_last;
+assign litedramcore_bankmachine3_source_source_payload_we = litedramcore_bankmachine3_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine3_source_source_payload_addr = litedramcore_bankmachine3_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine3_next_state <= 4'd0;
+ litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ if (litedramcore_bankmachine3_cmd_ready) begin
+ litedramcore_bankmachine3_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ if (litedramcore_bankmachine3_cmd_ready) begin
+ litedramcore_bankmachine3_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine3_refresh_req)) begin
+ litedramcore_bankmachine3_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine3_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine3_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine3_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine3_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ litedramcore_bankmachine3_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin
+ litedramcore_bankmachine3_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine3_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine3_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if (litedramcore_bankmachine3_source_source_payload_we) begin
+ litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if (litedramcore_bankmachine3_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if (litedramcore_bankmachine3_source_source_payload_we) begin
+ litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if (litedramcore_bankmachine3_source_source_payload_we) begin
+ litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if (litedramcore_bankmachine3_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine3_twtpcon_ready) begin
+ litedramcore_bankmachine3_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_row_open <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ litedramcore_bankmachine3_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_row_close <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ litedramcore_bankmachine3_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine3_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine3_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+assign litedramcore_bankmachine4_sink_valid = litedramcore_bankmachine4_req_valid;
+assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_sink_ready;
+assign litedramcore_bankmachine4_sink_payload_we = litedramcore_bankmachine4_req_we;
+assign litedramcore_bankmachine4_sink_payload_addr = litedramcore_bankmachine4_req_addr;
+assign litedramcore_bankmachine4_sink_sink_valid = litedramcore_bankmachine4_source_valid;
+assign litedramcore_bankmachine4_source_ready = litedramcore_bankmachine4_sink_sink_ready;
+assign litedramcore_bankmachine4_sink_sink_first = litedramcore_bankmachine4_source_first;
+assign litedramcore_bankmachine4_sink_sink_last = litedramcore_bankmachine4_source_last;
+assign litedramcore_bankmachine4_sink_sink_payload_we = litedramcore_bankmachine4_source_payload_we;
+assign litedramcore_bankmachine4_sink_sink_payload_addr = litedramcore_bankmachine4_source_payload_addr;
+assign litedramcore_bankmachine4_source_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid);
+assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_source_valid | litedramcore_bankmachine4_source_source_valid);
+assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_source_source_payload_addr[21:7]);
assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
always @(*) begin
- litedramcore_bankmachine4_cmd_payload_a <= 15'd0;
- if (litedramcore_bankmachine4_row_col_n_addr_sel) begin
- litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7];
- end else begin
- litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine4_cmd_payload_a <= 15'd0;
+ if (litedramcore_bankmachine4_row_col_n_addr_sel) begin
+ litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_source_source_payload_addr[21:7];
+ end else begin
+ litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write);
assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
always @(*) begin
- litedramcore_bankmachine4_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine4_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7])) begin
- litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine4_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | litedramcore_bankmachine4_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re);
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine4_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine4_next_state <= 4'd0;
- litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- if (litedramcore_bankmachine4_cmd_ready) begin
- litedramcore_bankmachine4_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- if (litedramcore_bankmachine4_cmd_ready) begin
- litedramcore_bankmachine4_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine4_refresh_req)) begin
- litedramcore_bankmachine4_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine4_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine4_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine4_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine4_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- litedramcore_bankmachine4_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin
- litedramcore_bankmachine4_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine4_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine4_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine4_twtpcon_ready) begin
- litedramcore_bankmachine4_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- litedramcore_bankmachine4_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_row_open <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_row_close <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- litedramcore_bankmachine4_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine4_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine4_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine5_req_valid;
-assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine5_req_we;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine5_req_addr;
-assign litedramcore_bankmachine5_cmd_buffer_sink_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine5_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine5_cmd_buffer_sink_first = litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine5_cmd_buffer_sink_last = litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine5_cmd_buffer_sink_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine5_cmd_buffer_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid);
-assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine5_cmd_buffer_source_valid);
-assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]);
+ litedramcore_bankmachine4_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine4_source_valid & litedramcore_bankmachine4_source_source_valid)) begin
+ if ((litedramcore_bankmachine4_source_payload_addr[21:7] != litedramcore_bankmachine4_source_source_payload_addr[21:7])) begin
+ litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine4_syncfifo4_din = {litedramcore_bankmachine4_fifo_in_last, litedramcore_bankmachine4_fifo_in_first, litedramcore_bankmachine4_fifo_in_payload_addr, litedramcore_bankmachine4_fifo_in_payload_we};
+assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout;
+assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout;
+assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout;
+assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout;
+assign litedramcore_bankmachine4_sink_ready = litedramcore_bankmachine4_syncfifo4_writable;
+assign litedramcore_bankmachine4_syncfifo4_we = litedramcore_bankmachine4_sink_valid;
+assign litedramcore_bankmachine4_fifo_in_first = litedramcore_bankmachine4_sink_first;
+assign litedramcore_bankmachine4_fifo_in_last = litedramcore_bankmachine4_sink_last;
+assign litedramcore_bankmachine4_fifo_in_payload_we = litedramcore_bankmachine4_sink_payload_we;
+assign litedramcore_bankmachine4_fifo_in_payload_addr = litedramcore_bankmachine4_sink_payload_addr;
+assign litedramcore_bankmachine4_source_valid = litedramcore_bankmachine4_syncfifo4_readable;
+assign litedramcore_bankmachine4_source_first = litedramcore_bankmachine4_fifo_out_first;
+assign litedramcore_bankmachine4_source_last = litedramcore_bankmachine4_fifo_out_last;
+assign litedramcore_bankmachine4_source_payload_we = litedramcore_bankmachine4_fifo_out_payload_we;
+assign litedramcore_bankmachine4_source_payload_addr = litedramcore_bankmachine4_fifo_out_payload_addr;
+assign litedramcore_bankmachine4_syncfifo4_re = litedramcore_bankmachine4_source_ready;
+always @(*) begin
+ litedramcore_bankmachine4_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine4_replace) begin
+ litedramcore_bankmachine4_wrport_adr <= (litedramcore_bankmachine4_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine4_wrport_adr <= litedramcore_bankmachine4_produce;
+ end
+end
+assign litedramcore_bankmachine4_wrport_dat_w = litedramcore_bankmachine4_syncfifo4_din;
+assign litedramcore_bankmachine4_wrport_we = (litedramcore_bankmachine4_syncfifo4_we & (litedramcore_bankmachine4_syncfifo4_writable | litedramcore_bankmachine4_replace));
+assign litedramcore_bankmachine4_do_read = (litedramcore_bankmachine4_syncfifo4_readable & litedramcore_bankmachine4_syncfifo4_re);
+assign litedramcore_bankmachine4_rdport_adr = litedramcore_bankmachine4_consume;
+assign litedramcore_bankmachine4_syncfifo4_dout = litedramcore_bankmachine4_rdport_dat_r;
+assign litedramcore_bankmachine4_syncfifo4_writable = (litedramcore_bankmachine4_level != 5'd16);
+assign litedramcore_bankmachine4_syncfifo4_readable = (litedramcore_bankmachine4_level != 1'd0);
+assign litedramcore_bankmachine4_pipe_valid_sink_ready = ((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready);
+assign litedramcore_bankmachine4_pipe_valid_sink_valid = litedramcore_bankmachine4_sink_sink_valid;
+assign litedramcore_bankmachine4_sink_sink_ready = litedramcore_bankmachine4_pipe_valid_sink_ready;
+assign litedramcore_bankmachine4_pipe_valid_sink_first = litedramcore_bankmachine4_sink_sink_first;
+assign litedramcore_bankmachine4_pipe_valid_sink_last = litedramcore_bankmachine4_sink_sink_last;
+assign litedramcore_bankmachine4_pipe_valid_sink_payload_we = litedramcore_bankmachine4_sink_sink_payload_we;
+assign litedramcore_bankmachine4_pipe_valid_sink_payload_addr = litedramcore_bankmachine4_sink_sink_payload_addr;
+assign litedramcore_bankmachine4_source_source_valid = litedramcore_bankmachine4_pipe_valid_source_valid;
+assign litedramcore_bankmachine4_pipe_valid_source_ready = litedramcore_bankmachine4_source_source_ready;
+assign litedramcore_bankmachine4_source_source_first = litedramcore_bankmachine4_pipe_valid_source_first;
+assign litedramcore_bankmachine4_source_source_last = litedramcore_bankmachine4_pipe_valid_source_last;
+assign litedramcore_bankmachine4_source_source_payload_we = litedramcore_bankmachine4_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine4_source_source_payload_addr = litedramcore_bankmachine4_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine4_next_state <= 4'd0;
+ litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ if (litedramcore_bankmachine4_cmd_ready) begin
+ litedramcore_bankmachine4_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ if (litedramcore_bankmachine4_cmd_ready) begin
+ litedramcore_bankmachine4_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine4_refresh_req)) begin
+ litedramcore_bankmachine4_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine4_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine4_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine4_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine4_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ litedramcore_bankmachine4_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin
+ litedramcore_bankmachine4_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine4_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine4_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if (litedramcore_bankmachine4_source_source_payload_we) begin
+ litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if (litedramcore_bankmachine4_source_source_payload_we) begin
+ litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if (litedramcore_bankmachine4_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine4_twtpcon_ready) begin
+ litedramcore_bankmachine4_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_row_open <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ litedramcore_bankmachine4_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ litedramcore_bankmachine4_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ litedramcore_bankmachine4_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_row_close <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ litedramcore_bankmachine4_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine4_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine4_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if (litedramcore_bankmachine4_source_source_payload_we) begin
+ litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if (litedramcore_bankmachine4_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+assign litedramcore_bankmachine5_sink_valid = litedramcore_bankmachine5_req_valid;
+assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_sink_ready;
+assign litedramcore_bankmachine5_sink_payload_we = litedramcore_bankmachine5_req_we;
+assign litedramcore_bankmachine5_sink_payload_addr = litedramcore_bankmachine5_req_addr;
+assign litedramcore_bankmachine5_sink_sink_valid = litedramcore_bankmachine5_source_valid;
+assign litedramcore_bankmachine5_source_ready = litedramcore_bankmachine5_sink_sink_ready;
+assign litedramcore_bankmachine5_sink_sink_first = litedramcore_bankmachine5_source_first;
+assign litedramcore_bankmachine5_sink_sink_last = litedramcore_bankmachine5_source_last;
+assign litedramcore_bankmachine5_sink_sink_payload_we = litedramcore_bankmachine5_source_payload_we;
+assign litedramcore_bankmachine5_sink_sink_payload_addr = litedramcore_bankmachine5_source_payload_addr;
+assign litedramcore_bankmachine5_source_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid);
+assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_source_valid | litedramcore_bankmachine5_source_source_valid);
+assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_source_source_payload_addr[21:7]);
assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
always @(*) begin
- litedramcore_bankmachine5_cmd_payload_a <= 15'd0;
- if (litedramcore_bankmachine5_row_col_n_addr_sel) begin
- litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7];
- end else begin
- litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine5_cmd_payload_a <= 15'd0;
+ if (litedramcore_bankmachine5_row_col_n_addr_sel) begin
+ litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_source_source_payload_addr[21:7];
+ end else begin
+ litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write);
assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
always @(*) begin
- litedramcore_bankmachine5_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine5_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7])) begin
- litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine5_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | litedramcore_bankmachine5_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re);
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine5_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine5_next_state <= 4'd0;
- litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- if (litedramcore_bankmachine5_cmd_ready) begin
- litedramcore_bankmachine5_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- if (litedramcore_bankmachine5_cmd_ready) begin
- litedramcore_bankmachine5_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine5_refresh_req)) begin
- litedramcore_bankmachine5_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine5_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine5_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine5_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine5_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- litedramcore_bankmachine5_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin
- litedramcore_bankmachine5_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine5_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine5_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine5_twtpcon_ready) begin
- litedramcore_bankmachine5_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_row_open <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_row_close <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- litedramcore_bankmachine5_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine5_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine5_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine6_req_valid;
-assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine6_req_we;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine6_req_addr;
-assign litedramcore_bankmachine6_cmd_buffer_sink_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine6_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine6_cmd_buffer_sink_first = litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine6_cmd_buffer_sink_last = litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine6_cmd_buffer_sink_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine6_cmd_buffer_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid);
-assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine6_cmd_buffer_source_valid);
-assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]);
+ litedramcore_bankmachine5_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine5_source_valid & litedramcore_bankmachine5_source_source_valid)) begin
+ if ((litedramcore_bankmachine5_source_payload_addr[21:7] != litedramcore_bankmachine5_source_source_payload_addr[21:7])) begin
+ litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine5_syncfifo5_din = {litedramcore_bankmachine5_fifo_in_last, litedramcore_bankmachine5_fifo_in_first, litedramcore_bankmachine5_fifo_in_payload_addr, litedramcore_bankmachine5_fifo_in_payload_we};
+assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout;
+assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout;
+assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout;
+assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout;
+assign litedramcore_bankmachine5_sink_ready = litedramcore_bankmachine5_syncfifo5_writable;
+assign litedramcore_bankmachine5_syncfifo5_we = litedramcore_bankmachine5_sink_valid;
+assign litedramcore_bankmachine5_fifo_in_first = litedramcore_bankmachine5_sink_first;
+assign litedramcore_bankmachine5_fifo_in_last = litedramcore_bankmachine5_sink_last;
+assign litedramcore_bankmachine5_fifo_in_payload_we = litedramcore_bankmachine5_sink_payload_we;
+assign litedramcore_bankmachine5_fifo_in_payload_addr = litedramcore_bankmachine5_sink_payload_addr;
+assign litedramcore_bankmachine5_source_valid = litedramcore_bankmachine5_syncfifo5_readable;
+assign litedramcore_bankmachine5_source_first = litedramcore_bankmachine5_fifo_out_first;
+assign litedramcore_bankmachine5_source_last = litedramcore_bankmachine5_fifo_out_last;
+assign litedramcore_bankmachine5_source_payload_we = litedramcore_bankmachine5_fifo_out_payload_we;
+assign litedramcore_bankmachine5_source_payload_addr = litedramcore_bankmachine5_fifo_out_payload_addr;
+assign litedramcore_bankmachine5_syncfifo5_re = litedramcore_bankmachine5_source_ready;
+always @(*) begin
+ litedramcore_bankmachine5_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine5_replace) begin
+ litedramcore_bankmachine5_wrport_adr <= (litedramcore_bankmachine5_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine5_wrport_adr <= litedramcore_bankmachine5_produce;
+ end
+end
+assign litedramcore_bankmachine5_wrport_dat_w = litedramcore_bankmachine5_syncfifo5_din;
+assign litedramcore_bankmachine5_wrport_we = (litedramcore_bankmachine5_syncfifo5_we & (litedramcore_bankmachine5_syncfifo5_writable | litedramcore_bankmachine5_replace));
+assign litedramcore_bankmachine5_do_read = (litedramcore_bankmachine5_syncfifo5_readable & litedramcore_bankmachine5_syncfifo5_re);
+assign litedramcore_bankmachine5_rdport_adr = litedramcore_bankmachine5_consume;
+assign litedramcore_bankmachine5_syncfifo5_dout = litedramcore_bankmachine5_rdport_dat_r;
+assign litedramcore_bankmachine5_syncfifo5_writable = (litedramcore_bankmachine5_level != 5'd16);
+assign litedramcore_bankmachine5_syncfifo5_readable = (litedramcore_bankmachine5_level != 1'd0);
+assign litedramcore_bankmachine5_pipe_valid_sink_ready = ((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready);
+assign litedramcore_bankmachine5_pipe_valid_sink_valid = litedramcore_bankmachine5_sink_sink_valid;
+assign litedramcore_bankmachine5_sink_sink_ready = litedramcore_bankmachine5_pipe_valid_sink_ready;
+assign litedramcore_bankmachine5_pipe_valid_sink_first = litedramcore_bankmachine5_sink_sink_first;
+assign litedramcore_bankmachine5_pipe_valid_sink_last = litedramcore_bankmachine5_sink_sink_last;
+assign litedramcore_bankmachine5_pipe_valid_sink_payload_we = litedramcore_bankmachine5_sink_sink_payload_we;
+assign litedramcore_bankmachine5_pipe_valid_sink_payload_addr = litedramcore_bankmachine5_sink_sink_payload_addr;
+assign litedramcore_bankmachine5_source_source_valid = litedramcore_bankmachine5_pipe_valid_source_valid;
+assign litedramcore_bankmachine5_pipe_valid_source_ready = litedramcore_bankmachine5_source_source_ready;
+assign litedramcore_bankmachine5_source_source_first = litedramcore_bankmachine5_pipe_valid_source_first;
+assign litedramcore_bankmachine5_source_source_last = litedramcore_bankmachine5_pipe_valid_source_last;
+assign litedramcore_bankmachine5_source_source_payload_we = litedramcore_bankmachine5_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine5_source_source_payload_addr = litedramcore_bankmachine5_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine5_next_state <= 4'd0;
+ litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ if (litedramcore_bankmachine5_cmd_ready) begin
+ litedramcore_bankmachine5_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ if (litedramcore_bankmachine5_cmd_ready) begin
+ litedramcore_bankmachine5_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine5_refresh_req)) begin
+ litedramcore_bankmachine5_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine5_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine5_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine5_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine5_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ litedramcore_bankmachine5_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin
+ litedramcore_bankmachine5_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine5_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine5_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_row_open <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_row_close <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ litedramcore_bankmachine5_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine5_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine5_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine5_twtpcon_ready) begin
+ litedramcore_bankmachine5_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if (litedramcore_bankmachine5_source_source_payload_we) begin
+ litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if (litedramcore_bankmachine5_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if (litedramcore_bankmachine5_source_source_payload_we) begin
+ litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if (litedramcore_bankmachine5_source_source_payload_we) begin
+ litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if (litedramcore_bankmachine5_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+assign litedramcore_bankmachine6_sink_valid = litedramcore_bankmachine6_req_valid;
+assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_sink_ready;
+assign litedramcore_bankmachine6_sink_payload_we = litedramcore_bankmachine6_req_we;
+assign litedramcore_bankmachine6_sink_payload_addr = litedramcore_bankmachine6_req_addr;
+assign litedramcore_bankmachine6_sink_sink_valid = litedramcore_bankmachine6_source_valid;
+assign litedramcore_bankmachine6_source_ready = litedramcore_bankmachine6_sink_sink_ready;
+assign litedramcore_bankmachine6_sink_sink_first = litedramcore_bankmachine6_source_first;
+assign litedramcore_bankmachine6_sink_sink_last = litedramcore_bankmachine6_source_last;
+assign litedramcore_bankmachine6_sink_sink_payload_we = litedramcore_bankmachine6_source_payload_we;
+assign litedramcore_bankmachine6_sink_sink_payload_addr = litedramcore_bankmachine6_source_payload_addr;
+assign litedramcore_bankmachine6_source_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid);
+assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_source_valid | litedramcore_bankmachine6_source_source_valid);
+assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_source_source_payload_addr[21:7]);
assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
always @(*) begin
- litedramcore_bankmachine6_cmd_payload_a <= 15'd0;
- if (litedramcore_bankmachine6_row_col_n_addr_sel) begin
- litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7];
- end else begin
- litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine6_cmd_payload_a <= 15'd0;
+ if (litedramcore_bankmachine6_row_col_n_addr_sel) begin
+ litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_source_source_payload_addr[21:7];
+ end else begin
+ litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write);
assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
always @(*) begin
- litedramcore_bankmachine6_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine6_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7])) begin
- litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine6_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | litedramcore_bankmachine6_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re);
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine6_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine6_next_state <= 4'd0;
- litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- if (litedramcore_bankmachine6_cmd_ready) begin
- litedramcore_bankmachine6_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- if (litedramcore_bankmachine6_cmd_ready) begin
- litedramcore_bankmachine6_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine6_refresh_req)) begin
- litedramcore_bankmachine6_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine6_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine6_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine6_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine6_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- litedramcore_bankmachine6_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin
- litedramcore_bankmachine6_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine6_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine6_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine6_twtpcon_ready) begin
- litedramcore_bankmachine6_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- litedramcore_bankmachine6_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_row_open <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_row_close <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- litedramcore_bankmachine6_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine6_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine6_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine7_req_valid;
-assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine7_req_we;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine7_req_addr;
-assign litedramcore_bankmachine7_cmd_buffer_sink_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine7_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine7_cmd_buffer_sink_first = litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine7_cmd_buffer_sink_last = litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine7_cmd_buffer_sink_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine7_cmd_buffer_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid);
-assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine7_cmd_buffer_source_valid);
-assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]);
+ litedramcore_bankmachine6_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine6_source_valid & litedramcore_bankmachine6_source_source_valid)) begin
+ if ((litedramcore_bankmachine6_source_payload_addr[21:7] != litedramcore_bankmachine6_source_source_payload_addr[21:7])) begin
+ litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine6_syncfifo6_din = {litedramcore_bankmachine6_fifo_in_last, litedramcore_bankmachine6_fifo_in_first, litedramcore_bankmachine6_fifo_in_payload_addr, litedramcore_bankmachine6_fifo_in_payload_we};
+assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout;
+assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout;
+assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout;
+assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout;
+assign litedramcore_bankmachine6_sink_ready = litedramcore_bankmachine6_syncfifo6_writable;
+assign litedramcore_bankmachine6_syncfifo6_we = litedramcore_bankmachine6_sink_valid;
+assign litedramcore_bankmachine6_fifo_in_first = litedramcore_bankmachine6_sink_first;
+assign litedramcore_bankmachine6_fifo_in_last = litedramcore_bankmachine6_sink_last;
+assign litedramcore_bankmachine6_fifo_in_payload_we = litedramcore_bankmachine6_sink_payload_we;
+assign litedramcore_bankmachine6_fifo_in_payload_addr = litedramcore_bankmachine6_sink_payload_addr;
+assign litedramcore_bankmachine6_source_valid = litedramcore_bankmachine6_syncfifo6_readable;
+assign litedramcore_bankmachine6_source_first = litedramcore_bankmachine6_fifo_out_first;
+assign litedramcore_bankmachine6_source_last = litedramcore_bankmachine6_fifo_out_last;
+assign litedramcore_bankmachine6_source_payload_we = litedramcore_bankmachine6_fifo_out_payload_we;
+assign litedramcore_bankmachine6_source_payload_addr = litedramcore_bankmachine6_fifo_out_payload_addr;
+assign litedramcore_bankmachine6_syncfifo6_re = litedramcore_bankmachine6_source_ready;
+always @(*) begin
+ litedramcore_bankmachine6_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine6_replace) begin
+ litedramcore_bankmachine6_wrport_adr <= (litedramcore_bankmachine6_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine6_wrport_adr <= litedramcore_bankmachine6_produce;
+ end
+end
+assign litedramcore_bankmachine6_wrport_dat_w = litedramcore_bankmachine6_syncfifo6_din;
+assign litedramcore_bankmachine6_wrport_we = (litedramcore_bankmachine6_syncfifo6_we & (litedramcore_bankmachine6_syncfifo6_writable | litedramcore_bankmachine6_replace));
+assign litedramcore_bankmachine6_do_read = (litedramcore_bankmachine6_syncfifo6_readable & litedramcore_bankmachine6_syncfifo6_re);
+assign litedramcore_bankmachine6_rdport_adr = litedramcore_bankmachine6_consume;
+assign litedramcore_bankmachine6_syncfifo6_dout = litedramcore_bankmachine6_rdport_dat_r;
+assign litedramcore_bankmachine6_syncfifo6_writable = (litedramcore_bankmachine6_level != 5'd16);
+assign litedramcore_bankmachine6_syncfifo6_readable = (litedramcore_bankmachine6_level != 1'd0);
+assign litedramcore_bankmachine6_pipe_valid_sink_ready = ((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready);
+assign litedramcore_bankmachine6_pipe_valid_sink_valid = litedramcore_bankmachine6_sink_sink_valid;
+assign litedramcore_bankmachine6_sink_sink_ready = litedramcore_bankmachine6_pipe_valid_sink_ready;
+assign litedramcore_bankmachine6_pipe_valid_sink_first = litedramcore_bankmachine6_sink_sink_first;
+assign litedramcore_bankmachine6_pipe_valid_sink_last = litedramcore_bankmachine6_sink_sink_last;
+assign litedramcore_bankmachine6_pipe_valid_sink_payload_we = litedramcore_bankmachine6_sink_sink_payload_we;
+assign litedramcore_bankmachine6_pipe_valid_sink_payload_addr = litedramcore_bankmachine6_sink_sink_payload_addr;
+assign litedramcore_bankmachine6_source_source_valid = litedramcore_bankmachine6_pipe_valid_source_valid;
+assign litedramcore_bankmachine6_pipe_valid_source_ready = litedramcore_bankmachine6_source_source_ready;
+assign litedramcore_bankmachine6_source_source_first = litedramcore_bankmachine6_pipe_valid_source_first;
+assign litedramcore_bankmachine6_source_source_last = litedramcore_bankmachine6_pipe_valid_source_last;
+assign litedramcore_bankmachine6_source_source_payload_we = litedramcore_bankmachine6_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine6_source_source_payload_addr = litedramcore_bankmachine6_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine6_next_state <= 4'd0;
+ litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ if (litedramcore_bankmachine6_cmd_ready) begin
+ litedramcore_bankmachine6_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ if (litedramcore_bankmachine6_cmd_ready) begin
+ litedramcore_bankmachine6_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine6_refresh_req)) begin
+ litedramcore_bankmachine6_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine6_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine6_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine6_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine6_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ litedramcore_bankmachine6_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin
+ litedramcore_bankmachine6_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine6_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine6_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if (litedramcore_bankmachine6_source_source_payload_we) begin
+ litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if (litedramcore_bankmachine6_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if (litedramcore_bankmachine6_source_source_payload_we) begin
+ litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if (litedramcore_bankmachine6_source_source_payload_we) begin
+ litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if (litedramcore_bankmachine6_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine6_twtpcon_ready) begin
+ litedramcore_bankmachine6_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_row_open <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ litedramcore_bankmachine6_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_row_close <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ litedramcore_bankmachine6_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine6_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine6_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+assign litedramcore_bankmachine7_sink_valid = litedramcore_bankmachine7_req_valid;
+assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_sink_ready;
+assign litedramcore_bankmachine7_sink_payload_we = litedramcore_bankmachine7_req_we;
+assign litedramcore_bankmachine7_sink_payload_addr = litedramcore_bankmachine7_req_addr;
+assign litedramcore_bankmachine7_sink_sink_valid = litedramcore_bankmachine7_source_valid;
+assign litedramcore_bankmachine7_source_ready = litedramcore_bankmachine7_sink_sink_ready;
+assign litedramcore_bankmachine7_sink_sink_first = litedramcore_bankmachine7_source_first;
+assign litedramcore_bankmachine7_sink_sink_last = litedramcore_bankmachine7_source_last;
+assign litedramcore_bankmachine7_sink_sink_payload_we = litedramcore_bankmachine7_source_payload_we;
+assign litedramcore_bankmachine7_sink_sink_payload_addr = litedramcore_bankmachine7_source_payload_addr;
+assign litedramcore_bankmachine7_source_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid);
+assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_source_valid | litedramcore_bankmachine7_source_source_valid);
+assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_source_source_payload_addr[21:7]);
assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
always @(*) begin
- litedramcore_bankmachine7_cmd_payload_a <= 15'd0;
- if (litedramcore_bankmachine7_row_col_n_addr_sel) begin
- litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7];
- end else begin
- litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine7_cmd_payload_a <= 15'd0;
+ if (litedramcore_bankmachine7_row_col_n_addr_sel) begin
+ litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_source_source_payload_addr[21:7];
+ end else begin
+ litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write);
assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
always @(*) begin
- litedramcore_bankmachine7_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine7_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7])) begin
- litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine7_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | litedramcore_bankmachine7_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re);
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine7_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine7_next_state <= 4'd0;
- litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- if (litedramcore_bankmachine7_cmd_ready) begin
- litedramcore_bankmachine7_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- if (litedramcore_bankmachine7_cmd_ready) begin
- litedramcore_bankmachine7_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine7_refresh_req)) begin
- litedramcore_bankmachine7_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine7_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine7_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine7_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine7_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- litedramcore_bankmachine7_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin
- litedramcore_bankmachine7_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine7_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine7_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine7_twtpcon_ready) begin
- litedramcore_bankmachine7_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- litedramcore_bankmachine7_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_row_open <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_row_close <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- litedramcore_bankmachine7_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine7_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine7_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
+ litedramcore_bankmachine7_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine7_source_valid & litedramcore_bankmachine7_source_source_valid)) begin
+ if ((litedramcore_bankmachine7_source_payload_addr[21:7] != litedramcore_bankmachine7_source_source_payload_addr[21:7])) begin
+ litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine7_syncfifo7_din = {litedramcore_bankmachine7_fifo_in_last, litedramcore_bankmachine7_fifo_in_first, litedramcore_bankmachine7_fifo_in_payload_addr, litedramcore_bankmachine7_fifo_in_payload_we};
+assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout;
+assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout;
+assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout;
+assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout;
+assign litedramcore_bankmachine7_sink_ready = litedramcore_bankmachine7_syncfifo7_writable;
+assign litedramcore_bankmachine7_syncfifo7_we = litedramcore_bankmachine7_sink_valid;
+assign litedramcore_bankmachine7_fifo_in_first = litedramcore_bankmachine7_sink_first;
+assign litedramcore_bankmachine7_fifo_in_last = litedramcore_bankmachine7_sink_last;
+assign litedramcore_bankmachine7_fifo_in_payload_we = litedramcore_bankmachine7_sink_payload_we;
+assign litedramcore_bankmachine7_fifo_in_payload_addr = litedramcore_bankmachine7_sink_payload_addr;
+assign litedramcore_bankmachine7_source_valid = litedramcore_bankmachine7_syncfifo7_readable;
+assign litedramcore_bankmachine7_source_first = litedramcore_bankmachine7_fifo_out_first;
+assign litedramcore_bankmachine7_source_last = litedramcore_bankmachine7_fifo_out_last;
+assign litedramcore_bankmachine7_source_payload_we = litedramcore_bankmachine7_fifo_out_payload_we;
+assign litedramcore_bankmachine7_source_payload_addr = litedramcore_bankmachine7_fifo_out_payload_addr;
+assign litedramcore_bankmachine7_syncfifo7_re = litedramcore_bankmachine7_source_ready;
+always @(*) begin
+ litedramcore_bankmachine7_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine7_replace) begin
+ litedramcore_bankmachine7_wrport_adr <= (litedramcore_bankmachine7_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine7_wrport_adr <= litedramcore_bankmachine7_produce;
+ end
+end
+assign litedramcore_bankmachine7_wrport_dat_w = litedramcore_bankmachine7_syncfifo7_din;
+assign litedramcore_bankmachine7_wrport_we = (litedramcore_bankmachine7_syncfifo7_we & (litedramcore_bankmachine7_syncfifo7_writable | litedramcore_bankmachine7_replace));
+assign litedramcore_bankmachine7_do_read = (litedramcore_bankmachine7_syncfifo7_readable & litedramcore_bankmachine7_syncfifo7_re);
+assign litedramcore_bankmachine7_rdport_adr = litedramcore_bankmachine7_consume;
+assign litedramcore_bankmachine7_syncfifo7_dout = litedramcore_bankmachine7_rdport_dat_r;
+assign litedramcore_bankmachine7_syncfifo7_writable = (litedramcore_bankmachine7_level != 5'd16);
+assign litedramcore_bankmachine7_syncfifo7_readable = (litedramcore_bankmachine7_level != 1'd0);
+assign litedramcore_bankmachine7_pipe_valid_sink_ready = ((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready);
+assign litedramcore_bankmachine7_pipe_valid_sink_valid = litedramcore_bankmachine7_sink_sink_valid;
+assign litedramcore_bankmachine7_sink_sink_ready = litedramcore_bankmachine7_pipe_valid_sink_ready;
+assign litedramcore_bankmachine7_pipe_valid_sink_first = litedramcore_bankmachine7_sink_sink_first;
+assign litedramcore_bankmachine7_pipe_valid_sink_last = litedramcore_bankmachine7_sink_sink_last;
+assign litedramcore_bankmachine7_pipe_valid_sink_payload_we = litedramcore_bankmachine7_sink_sink_payload_we;
+assign litedramcore_bankmachine7_pipe_valid_sink_payload_addr = litedramcore_bankmachine7_sink_sink_payload_addr;
+assign litedramcore_bankmachine7_source_source_valid = litedramcore_bankmachine7_pipe_valid_source_valid;
+assign litedramcore_bankmachine7_pipe_valid_source_ready = litedramcore_bankmachine7_source_source_ready;
+assign litedramcore_bankmachine7_source_source_first = litedramcore_bankmachine7_pipe_valid_source_first;
+assign litedramcore_bankmachine7_source_source_last = litedramcore_bankmachine7_pipe_valid_source_last;
+assign litedramcore_bankmachine7_source_source_payload_we = litedramcore_bankmachine7_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine7_source_source_payload_addr = litedramcore_bankmachine7_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine7_next_state <= 4'd0;
+ litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ if (litedramcore_bankmachine7_cmd_ready) begin
+ litedramcore_bankmachine7_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ if (litedramcore_bankmachine7_cmd_ready) begin
+ litedramcore_bankmachine7_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine7_refresh_req)) begin
+ litedramcore_bankmachine7_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine7_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine7_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine7_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine7_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ litedramcore_bankmachine7_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin
+ litedramcore_bankmachine7_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine7_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine7_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if (litedramcore_bankmachine7_source_source_payload_we) begin
+ litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if (litedramcore_bankmachine7_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if (litedramcore_bankmachine7_source_source_payload_we) begin
+ litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if (litedramcore_bankmachine7_source_source_payload_we) begin
+ litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if (litedramcore_bankmachine7_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine7_twtpcon_ready) begin
+ litedramcore_bankmachine7_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_row_open <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ litedramcore_bankmachine7_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_row_close <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ litedramcore_bankmachine7_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine7_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine7_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
end
assign litedramcore_rdcmdphase = (k7ddrphy_rdphase_storage - 1'd1);
assign litedramcore_wrcmdphase = (k7ddrphy_wrphase_storage - 1'd1);
assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
always @(*) begin
- litedramcore_choose_cmd_valids <= 8'd0;
- litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids <= 8'd0;
+ litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
end
assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids;
assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0;
assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4;
assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5;
always @(*) begin
- litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
- if (litedramcore_choose_cmd_cmd_valid) begin
- litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0;
- end
+ litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
+ if (litedramcore_choose_cmd_cmd_valid) begin
+ litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0;
+ end
end
always @(*) begin
- litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
- if (litedramcore_choose_cmd_cmd_valid) begin
- litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1;
- end
+ litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
+ if (litedramcore_choose_cmd_cmd_valid) begin
+ litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1;
+ end
end
always @(*) begin
- litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
- if (litedramcore_choose_cmd_cmd_valid) begin
- litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2;
- end
+ litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
+ if (litedramcore_choose_cmd_cmd_valid) begin
+ litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2;
+ end
end
always @(*) begin
- litedramcore_bankmachine0_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin
- litedramcore_bankmachine0_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin
- litedramcore_bankmachine0_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine0_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin
+ litedramcore_bankmachine0_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin
+ litedramcore_bankmachine0_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_bankmachine1_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin
- litedramcore_bankmachine1_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin
- litedramcore_bankmachine1_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine1_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin
+ litedramcore_bankmachine1_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin
+ litedramcore_bankmachine1_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_bankmachine2_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin
- litedramcore_bankmachine2_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin
- litedramcore_bankmachine2_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine2_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin
+ litedramcore_bankmachine2_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin
+ litedramcore_bankmachine2_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_bankmachine3_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin
- litedramcore_bankmachine3_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin
- litedramcore_bankmachine3_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine3_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin
+ litedramcore_bankmachine3_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin
+ litedramcore_bankmachine3_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_bankmachine4_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin
- litedramcore_bankmachine4_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin
- litedramcore_bankmachine4_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine4_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin
+ litedramcore_bankmachine4_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin
+ litedramcore_bankmachine4_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_bankmachine5_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin
- litedramcore_bankmachine5_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin
- litedramcore_bankmachine5_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine5_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin
+ litedramcore_bankmachine5_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin
+ litedramcore_bankmachine5_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_bankmachine6_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin
- litedramcore_bankmachine6_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin
- litedramcore_bankmachine6_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine6_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin
+ litedramcore_bankmachine6_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin
+ litedramcore_bankmachine6_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_bankmachine7_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin
- litedramcore_bankmachine7_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin
- litedramcore_bankmachine7_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine7_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin
+ litedramcore_bankmachine7_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin
+ litedramcore_bankmachine7_cmd_ready <= 1'd1;
+ end
end
assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid));
always @(*) begin
- litedramcore_choose_req_valids <= 8'd0;
- litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids <= 8'd0;
+ litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
end
assign litedramcore_choose_req_request = litedramcore_choose_req_valids;
assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6;
assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10;
assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11;
always @(*) begin
- litedramcore_choose_req_cmd_payload_cas <= 1'd0;
- if (litedramcore_choose_req_cmd_valid) begin
- litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3;
- end
+ litedramcore_choose_req_cmd_payload_cas <= 1'd0;
+ if (litedramcore_choose_req_cmd_valid) begin
+ litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3;
+ end
end
always @(*) begin
- litedramcore_choose_req_cmd_payload_ras <= 1'd0;
- if (litedramcore_choose_req_cmd_valid) begin
- litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4;
- end
+ litedramcore_choose_req_cmd_payload_ras <= 1'd0;
+ if (litedramcore_choose_req_cmd_valid) begin
+ litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4;
+ end
end
always @(*) begin
- litedramcore_choose_req_cmd_payload_we <= 1'd0;
- if (litedramcore_choose_req_cmd_valid) begin
- litedramcore_choose_req_cmd_payload_we <= t_array_muxed5;
- end
+ litedramcore_choose_req_cmd_payload_we <= 1'd0;
+ if (litedramcore_choose_req_cmd_valid) begin
+ litedramcore_choose_req_cmd_payload_we <= t_array_muxed5;
+ end
end
assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid));
assign litedramcore_dfi_p0_reset_n = 1'd1;
assign litedramcore_dfi_p3_odt = {1{litedramcore_steerer7}};
assign litedramcore_tfawcon_count = ((((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]) + litedramcore_tfawcon_window[3]) + litedramcore_tfawcon_window[4]);
always @(*) begin
- litedramcore_multiplexer_next_state <= 4'd0;
- litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- if (litedramcore_read_available) begin
- if (((~litedramcore_write_available) | litedramcore_max_time1)) begin
- litedramcore_multiplexer_next_state <= 2'd3;
- end
- end
- if (litedramcore_go_to_refresh) begin
- litedramcore_multiplexer_next_state <= 2'd2;
- end
- end
- 2'd2: begin
- if (litedramcore_cmd_last) begin
- litedramcore_multiplexer_next_state <= 1'd0;
- end
- end
- 2'd3: begin
- if (litedramcore_twtrcon_ready) begin
- litedramcore_multiplexer_next_state <= 1'd0;
- end
- end
- 3'd4: begin
- litedramcore_multiplexer_next_state <= 3'd5;
- end
- 3'd5: begin
- litedramcore_multiplexer_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_multiplexer_next_state <= 3'd7;
- end
- 3'd7: begin
- litedramcore_multiplexer_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_multiplexer_next_state <= 4'd9;
- end
- 4'd9: begin
- litedramcore_multiplexer_next_state <= 4'd10;
- end
- 4'd10: begin
- litedramcore_multiplexer_next_state <= 1'd1;
- end
- default: begin
- if (litedramcore_write_available) begin
- if (((~litedramcore_read_available) | litedramcore_max_time0)) begin
- litedramcore_multiplexer_next_state <= 3'd4;
- end
- end
- if (litedramcore_go_to_refresh) begin
- litedramcore_multiplexer_next_state <= 2'd2;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_steerer_sel0 <= 2'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- litedramcore_steerer_sel0 <= 1'd0;
- if ((k7ddrphy_wrphase_storage == 1'd0)) begin
- litedramcore_steerer_sel0 <= 2'd2;
- end
- if ((litedramcore_wrcmdphase == 1'd0)) begin
- litedramcore_steerer_sel0 <= 1'd1;
- end
- end
- 2'd2: begin
- litedramcore_steerer_sel0 <= 2'd3;
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- litedramcore_steerer_sel0 <= 1'd0;
- if ((k7ddrphy_rdphase_storage == 1'd0)) begin
- litedramcore_steerer_sel0 <= 2'd2;
- end
- if ((litedramcore_rdcmdphase == 1'd0)) begin
- litedramcore_steerer_sel0 <= 1'd1;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_cmd_ready <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- end
- 2'd2: begin
- litedramcore_cmd_ready <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_steerer_sel1 <= 2'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- litedramcore_steerer_sel1 <= 1'd0;
- if ((k7ddrphy_wrphase_storage == 1'd1)) begin
- litedramcore_steerer_sel1 <= 2'd2;
- end
- if ((litedramcore_wrcmdphase == 1'd1)) begin
- litedramcore_steerer_sel1 <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- litedramcore_steerer_sel1 <= 1'd0;
- if ((k7ddrphy_rdphase_storage == 1'd1)) begin
- litedramcore_steerer_sel1 <= 2'd2;
- end
- if ((litedramcore_rdcmdphase == 1'd1)) begin
- litedramcore_steerer_sel1 <= 1'd1;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_en1 <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- litedramcore_en1 <= 1'd1;
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_steerer_sel2 <= 2'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- litedramcore_steerer_sel2 <= 1'd0;
- if ((k7ddrphy_wrphase_storage == 2'd2)) begin
- litedramcore_steerer_sel2 <= 2'd2;
- end
- if ((litedramcore_wrcmdphase == 2'd2)) begin
- litedramcore_steerer_sel2 <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- litedramcore_steerer_sel2 <= 1'd0;
- if ((k7ddrphy_rdphase_storage == 2'd2)) begin
- litedramcore_steerer_sel2 <= 2'd2;
- end
- if ((litedramcore_rdcmdphase == 2'd2)) begin
- litedramcore_steerer_sel2 <= 1'd1;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_choose_cmd_want_activates <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_steerer_sel3 <= 2'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- litedramcore_steerer_sel3 <= 1'd0;
- if ((k7ddrphy_wrphase_storage == 2'd3)) begin
- litedramcore_steerer_sel3 <= 2'd2;
- end
- if ((litedramcore_wrcmdphase == 2'd3)) begin
- litedramcore_steerer_sel3 <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- litedramcore_steerer_sel3 <= 1'd0;
- if ((k7ddrphy_rdphase_storage == 2'd3)) begin
- litedramcore_steerer_sel3 <= 2'd2;
- end
- if ((litedramcore_rdcmdphase == 2'd3)) begin
- litedramcore_steerer_sel3 <= 1'd1;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_en0 <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- litedramcore_en0 <= 1'd1;
- end
- endcase
-end
-always @(*) begin
- litedramcore_choose_cmd_cmd_ready <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_choose_req_want_reads <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- litedramcore_choose_req_want_reads <= 1'd1;
- end
- endcase
-end
-always @(*) begin
- litedramcore_choose_req_want_writes <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- litedramcore_choose_req_want_writes <= 1'd1;
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_choose_req_cmd_ready <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- if (1'd0) begin
- litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
- end else begin
- litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- if (1'd0) begin
- litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
- end else begin
- litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
- end
- end
- endcase
+ litedramcore_multiplexer_next_state <= 4'd0;
+ litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ if (litedramcore_read_available) begin
+ if (((~litedramcore_write_available) | litedramcore_max_time1)) begin
+ litedramcore_multiplexer_next_state <= 2'd3;
+ end
+ end
+ if (litedramcore_go_to_refresh) begin
+ litedramcore_multiplexer_next_state <= 2'd2;
+ end
+ end
+ 2'd2: begin
+ if (litedramcore_cmd_last) begin
+ litedramcore_multiplexer_next_state <= 1'd0;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_twtrcon_ready) begin
+ litedramcore_multiplexer_next_state <= 1'd0;
+ end
+ end
+ 3'd4: begin
+ litedramcore_multiplexer_next_state <= 3'd5;
+ end
+ 3'd5: begin
+ litedramcore_multiplexer_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_multiplexer_next_state <= 3'd7;
+ end
+ 3'd7: begin
+ litedramcore_multiplexer_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_multiplexer_next_state <= 4'd9;
+ end
+ 4'd9: begin
+ litedramcore_multiplexer_next_state <= 4'd10;
+ end
+ 4'd10: begin
+ litedramcore_multiplexer_next_state <= 1'd1;
+ end
+ default: begin
+ if (litedramcore_write_available) begin
+ if (((~litedramcore_read_available) | litedramcore_max_time0)) begin
+ litedramcore_multiplexer_next_state <= 3'd4;
+ end
+ end
+ if (litedramcore_go_to_refresh) begin
+ litedramcore_multiplexer_next_state <= 2'd2;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_steerer_sel0 <= 2'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ litedramcore_steerer_sel0 <= 1'd0;
+ if ((k7ddrphy_wrphase_storage == 1'd0)) begin
+ litedramcore_steerer_sel0 <= 2'd2;
+ end
+ if ((litedramcore_wrcmdphase == 1'd0)) begin
+ litedramcore_steerer_sel0 <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ litedramcore_steerer_sel0 <= 2'd3;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ litedramcore_steerer_sel0 <= 1'd0;
+ if ((k7ddrphy_rdphase_storage == 1'd0)) begin
+ litedramcore_steerer_sel0 <= 2'd2;
+ end
+ if ((litedramcore_rdcmdphase == 1'd0)) begin
+ litedramcore_steerer_sel0 <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_cmd_ready <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ litedramcore_cmd_ready <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_steerer_sel1 <= 2'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ litedramcore_steerer_sel1 <= 1'd0;
+ if ((k7ddrphy_wrphase_storage == 1'd1)) begin
+ litedramcore_steerer_sel1 <= 2'd2;
+ end
+ if ((litedramcore_wrcmdphase == 1'd1)) begin
+ litedramcore_steerer_sel1 <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ litedramcore_steerer_sel1 <= 1'd0;
+ if ((k7ddrphy_rdphase_storage == 1'd1)) begin
+ litedramcore_steerer_sel1 <= 2'd2;
+ end
+ if ((litedramcore_rdcmdphase == 1'd1)) begin
+ litedramcore_steerer_sel1 <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_steerer_sel2 <= 2'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ litedramcore_steerer_sel2 <= 1'd0;
+ if ((k7ddrphy_wrphase_storage == 2'd2)) begin
+ litedramcore_steerer_sel2 <= 2'd2;
+ end
+ if ((litedramcore_wrcmdphase == 2'd2)) begin
+ litedramcore_steerer_sel2 <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ litedramcore_steerer_sel2 <= 1'd0;
+ if ((k7ddrphy_rdphase_storage == 2'd2)) begin
+ litedramcore_steerer_sel2 <= 2'd2;
+ end
+ if ((litedramcore_rdcmdphase == 2'd2)) begin
+ litedramcore_steerer_sel2 <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_choose_cmd_want_activates <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ if (1'd0) begin
+ end else begin
+ litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ if (1'd0) begin
+ end else begin
+ litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_steerer_sel3 <= 2'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ litedramcore_steerer_sel3 <= 1'd0;
+ if ((k7ddrphy_wrphase_storage == 2'd3)) begin
+ litedramcore_steerer_sel3 <= 2'd2;
+ end
+ if ((litedramcore_wrcmdphase == 2'd3)) begin
+ litedramcore_steerer_sel3 <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ litedramcore_steerer_sel3 <= 1'd0;
+ if ((k7ddrphy_rdphase_storage == 2'd3)) begin
+ litedramcore_steerer_sel3 <= 2'd2;
+ end
+ if ((litedramcore_rdcmdphase == 2'd3)) begin
+ litedramcore_steerer_sel3 <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_en0 <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ litedramcore_en0 <= 1'd1;
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_en1 <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ litedramcore_en1 <= 1'd1;
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_choose_cmd_cmd_ready <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ if (1'd0) begin
+ end else begin
+ litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ if (1'd0) begin
+ end else begin
+ litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_choose_req_want_reads <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ litedramcore_choose_req_want_reads <= 1'd1;
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_choose_req_want_writes <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ litedramcore_choose_req_want_writes <= 1'd1;
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_choose_req_cmd_ready <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ if (1'd0) begin
+ litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+ end else begin
+ litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ if (1'd0) begin
+ litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+ end else begin
+ litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+ end
+ end
+ endcase
end
assign litedramcore_roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
assign litedramcore_roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock));
assign user_port_wdata_ready = litedramcore_new_master_wdata_ready1;
assign user_port_rdata_valid = litedramcore_new_master_rdata_valid8;
always @(*) begin
- litedramcore_interface_wdata <= 256'd0;
- case ({litedramcore_new_master_wdata_ready1})
- 1'd1: begin
- litedramcore_interface_wdata <= user_port_wdata_payload_data;
- end
- default: begin
- litedramcore_interface_wdata <= 1'd0;
- end
- endcase
-end
-always @(*) begin
- litedramcore_interface_wdata_we <= 32'd0;
- case ({litedramcore_new_master_wdata_ready1})
- 1'd1: begin
- litedramcore_interface_wdata_we <= user_port_wdata_payload_we;
- end
- default: begin
- litedramcore_interface_wdata_we <= 1'd0;
- end
- endcase
+ litedramcore_interface_wdata <= 256'd0;
+ case ({litedramcore_new_master_wdata_ready1})
+ 1'd1: begin
+ litedramcore_interface_wdata <= user_port_wdata_payload_data;
+ end
+ default: begin
+ litedramcore_interface_wdata <= 1'd0;
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_interface_wdata_we <= 32'd0;
+ case ({litedramcore_new_master_wdata_ready1})
+ 1'd1: begin
+ litedramcore_interface_wdata_we <= user_port_wdata_payload_we;
+ end
+ default: begin
+ litedramcore_interface_wdata_we <= 1'd0;
+ end
+ endcase
end
assign user_port_rdata_payload_data = litedramcore_interface_rdata;
assign litedramcore_roundrobin0_grant = 1'd0;
assign litedramcore_roundrobin6_grant = 1'd0;
assign litedramcore_roundrobin7_grant = 1'd0;
always @(*) begin
- litedramcore_next_state <= 2'd0;
- litedramcore_next_state <= litedramcore_state;
- case (litedramcore_state)
- 1'd1: begin
- litedramcore_next_state <= 2'd2;
- end
- 2'd2: begin
- litedramcore_next_state <= 1'd0;
- end
- default: begin
- if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_next_state <= 1'd1;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_wishbone_dat_r <= 32'd0;
- case (litedramcore_state)
- 1'd1: begin
- end
- 2'd2: begin
- litedramcore_wishbone_dat_r <= litedramcore_dat_r;
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_wishbone_ack <= 1'd0;
- case (litedramcore_state)
- 1'd1: begin
- end
- 2'd2: begin
- litedramcore_wishbone_ack <= 1'd1;
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_dat_w_next_value0 <= 32'd0;
- case (litedramcore_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- default: begin
- litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w;
- end
- endcase
-end
-always @(*) begin
- litedramcore_dat_w_next_value_ce0 <= 1'd0;
- case (litedramcore_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- default: begin
- litedramcore_dat_w_next_value_ce0 <= 1'd1;
- end
- endcase
-end
-always @(*) begin
- litedramcore_adr_next_value1 <= 14'd0;
- case (litedramcore_state)
- 1'd1: begin
- litedramcore_adr_next_value1 <= 1'd0;
- end
- 2'd2: begin
- end
- default: begin
- if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_adr_next_value1 <= litedramcore_wishbone_adr;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_adr_next_value_ce1 <= 1'd0;
- case (litedramcore_state)
- 1'd1: begin
- litedramcore_adr_next_value_ce1 <= 1'd1;
- end
- 2'd2: begin
- end
- default: begin
- if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_adr_next_value_ce1 <= 1'd1;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_we_next_value2 <= 1'd0;
- case (litedramcore_state)
- 1'd1: begin
- litedramcore_we_next_value2 <= 1'd0;
- end
- 2'd2: begin
- end
- default: begin
- if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_we_next_value_ce2 <= 1'd0;
- case (litedramcore_state)
- 1'd1: begin
- litedramcore_we_next_value_ce2 <= 1'd1;
- end
- 2'd2: begin
- end
- default: begin
- if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_we_next_value_ce2 <= 1'd1;
- end
- end
- endcase
+ litedramcore_next_state <= 2'd0;
+ litedramcore_next_state <= litedramcore_state;
+ case (litedramcore_state)
+ 1'd1: begin
+ litedramcore_next_state <= 2'd2;
+ end
+ 2'd2: begin
+ litedramcore_next_state <= 1'd0;
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_next_state <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_wishbone_dat_r <= 32'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ litedramcore_wishbone_dat_r <= litedramcore_dat_r;
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_wishbone_ack <= 1'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ litedramcore_wishbone_ack <= 1'd1;
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_dat_w_next_value0 <= 32'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ default: begin
+ litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w;
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_dat_w_next_value_ce0 <= 1'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ default: begin
+ litedramcore_dat_w_next_value_ce0 <= 1'd1;
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_adr_next_value1 <= 14'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ litedramcore_adr_next_value1 <= 1'd0;
+ end
+ 2'd2: begin
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_adr_next_value1 <= litedramcore_wishbone_adr;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_adr_next_value_ce1 <= 1'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ litedramcore_adr_next_value_ce1 <= 1'd1;
+ end
+ 2'd2: begin
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_adr_next_value_ce1 <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_we_next_value2 <= 1'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ litedramcore_we_next_value2 <= 1'd0;
+ end
+ 2'd2: begin
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_we_next_value_ce2 <= 1'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ litedramcore_we_next_value_ce2 <= 1'd1;
+ end
+ 2'd2: begin
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_we_next_value_ce2 <= 1'd1;
+ end
+ end
+ endcase
end
assign litedramcore_wishbone_adr = wb_bus_adr;
assign litedramcore_wishbone_dat_w = wb_bus_dat_w;
assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0);
assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
always @(*) begin
- csrbank0_init_done0_re <= 1'd0;
- if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
- csrbank0_init_done0_re <= interface0_bank_bus_we;
- end
+ csrbank0_init_done0_re <= 1'd0;
+ if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank0_init_done0_re <= interface0_bank_bus_we;
+ end
end
always @(*) begin
- csrbank0_init_done0_we <= 1'd0;
- if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
- csrbank0_init_done0_we <= (~interface0_bank_bus_we);
- end
+ csrbank0_init_done0_we <= 1'd0;
+ if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank0_init_done0_we <= (~interface0_bank_bus_we);
+ end
end
assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0];
always @(*) begin
- csrbank0_init_error0_we <= 1'd0;
- if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
- csrbank0_init_error0_we <= (~interface0_bank_bus_we);
- end
+ csrbank0_init_error0_we <= 1'd0;
+ if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
+ csrbank0_init_error0_we <= (~interface0_bank_bus_we);
+ end
end
always @(*) begin
- csrbank0_init_error0_re <= 1'd0;
- if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
- csrbank0_init_error0_re <= interface0_bank_bus_we;
- end
+ csrbank0_init_error0_re <= 1'd0;
+ if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
+ csrbank0_init_error0_re <= interface0_bank_bus_we;
+ end
end
assign csrbank0_init_done0_w = init_done_storage;
assign csrbank0_init_error0_w = init_error_storage;
assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1);
assign csrbank1_rst0_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- csrbank1_rst0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
- csrbank1_rst0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_rst0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank1_rst0_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- csrbank1_rst0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
- csrbank1_rst0_re <= interface1_bank_bus_we;
- end
+ csrbank1_rst0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank1_rst0_re <= interface1_bank_bus_we;
+ end
end
assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[3:0];
always @(*) begin
- csrbank1_dly_sel0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
- csrbank1_dly_sel0_re <= interface1_bank_bus_we;
- end
+ csrbank1_dly_sel0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
+ csrbank1_dly_sel0_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- csrbank1_dly_sel0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
- csrbank1_dly_sel0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_dly_sel0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
+ csrbank1_dly_sel0_we <= (~interface1_bank_bus_we);
+ end
end
assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0];
always @(*) begin
- csrbank1_half_sys8x_taps0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
- csrbank1_half_sys8x_taps0_re <= interface1_bank_bus_we;
- end
+ csrbank1_half_sys8x_taps0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
+ csrbank1_half_sys8x_taps0_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- csrbank1_half_sys8x_taps0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
- csrbank1_half_sys8x_taps0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_half_sys8x_taps0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
+ csrbank1_half_sys8x_taps0_we <= (~interface1_bank_bus_we);
+ end
end
assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- csrbank1_wlevel_en0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
- csrbank1_wlevel_en0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_wlevel_en0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
+ csrbank1_wlevel_en0_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- csrbank1_wlevel_en0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
- csrbank1_wlevel_en0_re <= interface1_bank_bus_we;
- end
+ csrbank1_wlevel_en0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
+ csrbank1_wlevel_en0_re <= interface1_bank_bus_we;
+ end
end
assign k7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- k7ddrphy_wlevel_strobe_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
- k7ddrphy_wlevel_strobe_re <= interface1_bank_bus_we;
- end
+ k7ddrphy_wlevel_strobe_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
+ k7ddrphy_wlevel_strobe_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- k7ddrphy_wlevel_strobe_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
- k7ddrphy_wlevel_strobe_we <= (~interface1_bank_bus_we);
- end
+ k7ddrphy_wlevel_strobe_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
+ k7ddrphy_wlevel_strobe_we <= (~interface1_bank_bus_we);
+ end
end
assign k7ddrphy_cdly_rst_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- k7ddrphy_cdly_rst_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
- k7ddrphy_cdly_rst_we <= (~interface1_bank_bus_we);
- end
+ k7ddrphy_cdly_rst_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
+ k7ddrphy_cdly_rst_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- k7ddrphy_cdly_rst_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
- k7ddrphy_cdly_rst_re <= interface1_bank_bus_we;
- end
+ k7ddrphy_cdly_rst_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
+ k7ddrphy_cdly_rst_re <= interface1_bank_bus_we;
+ end
end
assign k7ddrphy_cdly_inc_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- k7ddrphy_cdly_inc_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
- k7ddrphy_cdly_inc_we <= (~interface1_bank_bus_we);
- end
+ k7ddrphy_cdly_inc_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
+ k7ddrphy_cdly_inc_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- k7ddrphy_cdly_inc_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
- k7ddrphy_cdly_inc_re <= interface1_bank_bus_we;
- end
+ k7ddrphy_cdly_inc_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
+ k7ddrphy_cdly_inc_re <= interface1_bank_bus_we;
+ end
end
assign k7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- k7ddrphy_rdly_dq_rst_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
- k7ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we);
- end
+ k7ddrphy_rdly_dq_rst_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
+ k7ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- k7ddrphy_rdly_dq_rst_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
- k7ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we;
- end
+ k7ddrphy_rdly_dq_rst_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
+ k7ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we;
+ end
end
assign k7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- k7ddrphy_rdly_dq_inc_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
- k7ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we);
- end
+ k7ddrphy_rdly_dq_inc_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
+ k7ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- k7ddrphy_rdly_dq_inc_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
- k7ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we;
- end
+ k7ddrphy_rdly_dq_inc_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
+ k7ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we;
+ end
end
assign k7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- k7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
- k7ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
- end
+ k7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
+ k7ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- k7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
- k7ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
- end
+ k7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
+ k7ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
+ end
end
assign k7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- k7ddrphy_rdly_dq_bitslip_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
- k7ddrphy_rdly_dq_bitslip_re <= interface1_bank_bus_we;
- end
+ k7ddrphy_rdly_dq_bitslip_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
+ k7ddrphy_rdly_dq_bitslip_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- k7ddrphy_rdly_dq_bitslip_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
- k7ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we);
- end
+ k7ddrphy_rdly_dq_bitslip_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
+ k7ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we);
+ end
end
assign k7ddrphy_wdly_dq_rst_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- k7ddrphy_wdly_dq_rst_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
- k7ddrphy_wdly_dq_rst_re <= interface1_bank_bus_we;
- end
+ k7ddrphy_wdly_dq_rst_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
+ k7ddrphy_wdly_dq_rst_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- k7ddrphy_wdly_dq_rst_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
- k7ddrphy_wdly_dq_rst_we <= (~interface1_bank_bus_we);
- end
+ k7ddrphy_wdly_dq_rst_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
+ k7ddrphy_wdly_dq_rst_we <= (~interface1_bank_bus_we);
+ end
end
assign k7ddrphy_wdly_dq_inc_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- k7ddrphy_wdly_dq_inc_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
- k7ddrphy_wdly_dq_inc_re <= interface1_bank_bus_we;
- end
+ k7ddrphy_wdly_dq_inc_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
+ k7ddrphy_wdly_dq_inc_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- k7ddrphy_wdly_dq_inc_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
- k7ddrphy_wdly_dq_inc_we <= (~interface1_bank_bus_we);
- end
+ k7ddrphy_wdly_dq_inc_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
+ k7ddrphy_wdly_dq_inc_we <= (~interface1_bank_bus_we);
+ end
end
assign k7ddrphy_wdly_dqs_rst_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- k7ddrphy_wdly_dqs_rst_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin
- k7ddrphy_wdly_dqs_rst_we <= (~interface1_bank_bus_we);
- end
+ k7ddrphy_wdly_dqs_rst_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin
+ k7ddrphy_wdly_dqs_rst_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- k7ddrphy_wdly_dqs_rst_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin
- k7ddrphy_wdly_dqs_rst_re <= interface1_bank_bus_we;
- end
+ k7ddrphy_wdly_dqs_rst_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin
+ k7ddrphy_wdly_dqs_rst_re <= interface1_bank_bus_we;
+ end
end
assign k7ddrphy_wdly_dqs_inc_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- k7ddrphy_wdly_dqs_inc_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin
- k7ddrphy_wdly_dqs_inc_we <= (~interface1_bank_bus_we);
- end
+ k7ddrphy_wdly_dqs_inc_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin
+ k7ddrphy_wdly_dqs_inc_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- k7ddrphy_wdly_dqs_inc_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin
- k7ddrphy_wdly_dqs_inc_re <= interface1_bank_bus_we;
- end
+ k7ddrphy_wdly_dqs_inc_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin
+ k7ddrphy_wdly_dqs_inc_re <= interface1_bank_bus_we;
+ end
end
assign k7ddrphy_wdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- k7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin
- k7ddrphy_wdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
- end
+ k7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin
+ k7ddrphy_wdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- k7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin
- k7ddrphy_wdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
- end
+ k7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin
+ k7ddrphy_wdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
+ end
end
assign k7ddrphy_wdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- k7ddrphy_wdly_dq_bitslip_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd16))) begin
- k7ddrphy_wdly_dq_bitslip_we <= (~interface1_bank_bus_we);
- end
+ k7ddrphy_wdly_dq_bitslip_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd16))) begin
+ k7ddrphy_wdly_dq_bitslip_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- k7ddrphy_wdly_dq_bitslip_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd16))) begin
- k7ddrphy_wdly_dq_bitslip_re <= interface1_bank_bus_we;
- end
+ k7ddrphy_wdly_dq_bitslip_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd16))) begin
+ k7ddrphy_wdly_dq_bitslip_re <= interface1_bank_bus_we;
+ end
end
assign csrbank1_rdphase0_r = interface1_bank_bus_dat_w[1:0];
always @(*) begin
- csrbank1_rdphase0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd17))) begin
- csrbank1_rdphase0_re <= interface1_bank_bus_we;
- end
+ csrbank1_rdphase0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd17))) begin
+ csrbank1_rdphase0_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- csrbank1_rdphase0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd17))) begin
- csrbank1_rdphase0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_rdphase0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd17))) begin
+ csrbank1_rdphase0_we <= (~interface1_bank_bus_we);
+ end
end
assign csrbank1_wrphase0_r = interface1_bank_bus_dat_w[1:0];
always @(*) begin
- csrbank1_wrphase0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd18))) begin
- csrbank1_wrphase0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_wrphase0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd18))) begin
+ csrbank1_wrphase0_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- csrbank1_wrphase0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd18))) begin
- csrbank1_wrphase0_re <= interface1_bank_bus_we;
- end
+ csrbank1_wrphase0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd18))) begin
+ csrbank1_wrphase0_re <= interface1_bank_bus_we;
+ end
end
assign csrbank1_rst0_w = k7ddrphy_rst_storage;
assign csrbank1_dly_sel0_w = k7ddrphy_dly_sel_storage[3:0];
assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2);
assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0];
always @(*) begin
- csrbank2_dfii_control0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
- csrbank2_dfii_control0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_control0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank2_dfii_control0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_control0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
- csrbank2_dfii_control0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_control0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank2_dfii_control0_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0];
always @(*) begin
- csrbank2_dfii_pi0_command0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
- csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi0_command0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
+ csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi0_command0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
- csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi0_command0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
+ csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we;
+ end
end
assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0];
always @(*) begin
- litedramcore_phaseinjector0_command_issue_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
- litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we);
- end
+ litedramcore_phaseinjector0_command_issue_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
+ litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- litedramcore_phaseinjector0_command_issue_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
- litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we;
- end
+ litedramcore_phaseinjector0_command_issue_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
+ litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[14:0];
always @(*) begin
- csrbank2_dfii_pi0_address0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
- csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi0_address0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
+ csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi0_address0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
- csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi0_address0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
+ csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0];
always @(*) begin
- csrbank2_dfii_pi0_baddress0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
- csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi0_baddress0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
+ csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi0_baddress0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
- csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi0_baddress0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
+ csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi0_wrdata1_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi0_wrdata1_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
- csrbank2_dfii_pi0_wrdata1_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi0_wrdata1_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
+ csrbank2_dfii_pi0_wrdata1_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi0_wrdata1_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
- csrbank2_dfii_pi0_wrdata1_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi0_wrdata1_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
+ csrbank2_dfii_pi0_wrdata1_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
- csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
+ csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
- csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
+ csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi0_rddata1_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi0_rddata1_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
- csrbank2_dfii_pi0_rddata1_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi0_rddata1_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
+ csrbank2_dfii_pi0_rddata1_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi0_rddata1_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
- csrbank2_dfii_pi0_rddata1_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi0_rddata1_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
+ csrbank2_dfii_pi0_rddata1_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi0_rddata0_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi0_rddata0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
- csrbank2_dfii_pi0_rddata0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi0_rddata0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
+ csrbank2_dfii_pi0_rddata0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi0_rddata0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
- csrbank2_dfii_pi0_rddata0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi0_rddata0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
+ csrbank2_dfii_pi0_rddata0_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0];
always @(*) begin
- csrbank2_dfii_pi1_command0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
- csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi1_command0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
+ csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi1_command0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
- csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi1_command0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
+ csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we);
+ end
end
assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0];
always @(*) begin
- litedramcore_phaseinjector1_command_issue_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
- litedramcore_phaseinjector1_command_issue_re <= interface2_bank_bus_we;
- end
+ litedramcore_phaseinjector1_command_issue_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
+ litedramcore_phaseinjector1_command_issue_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- litedramcore_phaseinjector1_command_issue_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
- litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we);
- end
+ litedramcore_phaseinjector1_command_issue_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
+ litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[14:0];
always @(*) begin
- csrbank2_dfii_pi1_address0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
- csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi1_address0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
+ csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi1_address0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
- csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi1_address0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
+ csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0];
always @(*) begin
- csrbank2_dfii_pi1_baddress0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
- csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi1_baddress0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
+ csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi1_baddress0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
- csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi1_baddress0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
+ csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi1_wrdata1_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi1_wrdata1_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
- csrbank2_dfii_pi1_wrdata1_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi1_wrdata1_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
+ csrbank2_dfii_pi1_wrdata1_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi1_wrdata1_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
- csrbank2_dfii_pi1_wrdata1_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi1_wrdata1_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
+ csrbank2_dfii_pi1_wrdata1_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
- csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
+ csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
- csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
+ csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi1_rddata1_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi1_rddata1_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
- csrbank2_dfii_pi1_rddata1_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi1_rddata1_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
+ csrbank2_dfii_pi1_rddata1_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi1_rddata1_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
- csrbank2_dfii_pi1_rddata1_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi1_rddata1_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
+ csrbank2_dfii_pi1_rddata1_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi1_rddata0_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi1_rddata0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
- csrbank2_dfii_pi1_rddata0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi1_rddata0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
+ csrbank2_dfii_pi1_rddata0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi1_rddata0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
- csrbank2_dfii_pi1_rddata0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi1_rddata0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
+ csrbank2_dfii_pi1_rddata0_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0];
always @(*) begin
- csrbank2_dfii_pi2_command0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
- csrbank2_dfii_pi2_command0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi2_command0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
+ csrbank2_dfii_pi2_command0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi2_command0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
- csrbank2_dfii_pi2_command0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi2_command0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
+ csrbank2_dfii_pi2_command0_re <= interface2_bank_bus_we;
+ end
end
assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0];
always @(*) begin
- litedramcore_phaseinjector2_command_issue_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
- litedramcore_phaseinjector2_command_issue_re <= interface2_bank_bus_we;
- end
+ litedramcore_phaseinjector2_command_issue_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
+ litedramcore_phaseinjector2_command_issue_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- litedramcore_phaseinjector2_command_issue_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
- litedramcore_phaseinjector2_command_issue_we <= (~interface2_bank_bus_we);
- end
+ litedramcore_phaseinjector2_command_issue_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
+ litedramcore_phaseinjector2_command_issue_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[14:0];
always @(*) begin
- csrbank2_dfii_pi2_address0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin
- csrbank2_dfii_pi2_address0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi2_address0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin
+ csrbank2_dfii_pi2_address0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi2_address0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin
- csrbank2_dfii_pi2_address0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi2_address0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin
+ csrbank2_dfii_pi2_address0_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0];
always @(*) begin
- csrbank2_dfii_pi2_baddress0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin
- csrbank2_dfii_pi2_baddress0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi2_baddress0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin
+ csrbank2_dfii_pi2_baddress0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi2_baddress0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin
- csrbank2_dfii_pi2_baddress0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi2_baddress0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin
+ csrbank2_dfii_pi2_baddress0_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi2_wrdata1_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi2_wrdata1_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin
- csrbank2_dfii_pi2_wrdata1_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi2_wrdata1_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin
+ csrbank2_dfii_pi2_wrdata1_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi2_wrdata1_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin
- csrbank2_dfii_pi2_wrdata1_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi2_wrdata1_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin
+ csrbank2_dfii_pi2_wrdata1_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin
- csrbank2_dfii_pi2_wrdata0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin
+ csrbank2_dfii_pi2_wrdata0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin
- csrbank2_dfii_pi2_wrdata0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin
+ csrbank2_dfii_pi2_wrdata0_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi2_rddata1_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi2_rddata1_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin
- csrbank2_dfii_pi2_rddata1_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi2_rddata1_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin
+ csrbank2_dfii_pi2_rddata1_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi2_rddata1_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin
- csrbank2_dfii_pi2_rddata1_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi2_rddata1_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin
+ csrbank2_dfii_pi2_rddata1_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi2_rddata0_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi2_rddata0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin
- csrbank2_dfii_pi2_rddata0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi2_rddata0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin
+ csrbank2_dfii_pi2_rddata0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi2_rddata0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin
- csrbank2_dfii_pi2_rddata0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi2_rddata0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin
+ csrbank2_dfii_pi2_rddata0_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0];
always @(*) begin
- csrbank2_dfii_pi3_command0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd25))) begin
- csrbank2_dfii_pi3_command0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi3_command0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd25))) begin
+ csrbank2_dfii_pi3_command0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi3_command0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd25))) begin
- csrbank2_dfii_pi3_command0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi3_command0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd25))) begin
+ csrbank2_dfii_pi3_command0_re <= interface2_bank_bus_we;
+ end
end
assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0];
always @(*) begin
- litedramcore_phaseinjector3_command_issue_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd26))) begin
- litedramcore_phaseinjector3_command_issue_we <= (~interface2_bank_bus_we);
- end
+ litedramcore_phaseinjector3_command_issue_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd26))) begin
+ litedramcore_phaseinjector3_command_issue_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- litedramcore_phaseinjector3_command_issue_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd26))) begin
- litedramcore_phaseinjector3_command_issue_re <= interface2_bank_bus_we;
- end
+ litedramcore_phaseinjector3_command_issue_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd26))) begin
+ litedramcore_phaseinjector3_command_issue_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[14:0];
always @(*) begin
- csrbank2_dfii_pi3_address0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd27))) begin
- csrbank2_dfii_pi3_address0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi3_address0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd27))) begin
+ csrbank2_dfii_pi3_address0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi3_address0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd27))) begin
- csrbank2_dfii_pi3_address0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi3_address0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd27))) begin
+ csrbank2_dfii_pi3_address0_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0];
always @(*) begin
- csrbank2_dfii_pi3_baddress0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd28))) begin
- csrbank2_dfii_pi3_baddress0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi3_baddress0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd28))) begin
+ csrbank2_dfii_pi3_baddress0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi3_baddress0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd28))) begin
- csrbank2_dfii_pi3_baddress0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi3_baddress0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd28))) begin
+ csrbank2_dfii_pi3_baddress0_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi3_wrdata1_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi3_wrdata1_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd29))) begin
- csrbank2_dfii_pi3_wrdata1_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi3_wrdata1_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd29))) begin
+ csrbank2_dfii_pi3_wrdata1_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi3_wrdata1_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd29))) begin
- csrbank2_dfii_pi3_wrdata1_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi3_wrdata1_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd29))) begin
+ csrbank2_dfii_pi3_wrdata1_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi3_wrdata0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd30))) begin
- csrbank2_dfii_pi3_wrdata0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi3_wrdata0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd30))) begin
+ csrbank2_dfii_pi3_wrdata0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd30))) begin
- csrbank2_dfii_pi3_wrdata0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd30))) begin
+ csrbank2_dfii_pi3_wrdata0_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi3_rddata1_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi3_rddata1_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd31))) begin
- csrbank2_dfii_pi3_rddata1_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi3_rddata1_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd31))) begin
+ csrbank2_dfii_pi3_rddata1_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi3_rddata1_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd31))) begin
- csrbank2_dfii_pi3_rddata1_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi3_rddata1_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd31))) begin
+ csrbank2_dfii_pi3_rddata1_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi3_rddata0_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi3_rddata0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 6'd32))) begin
- csrbank2_dfii_pi3_rddata0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi3_rddata0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 6'd32))) begin
+ csrbank2_dfii_pi3_rddata0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi3_rddata0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 6'd32))) begin
- csrbank2_dfii_pi3_rddata0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi3_rddata0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 6'd32))) begin
+ csrbank2_dfii_pi3_rddata0_we <= (~interface2_bank_bus_we);
+ end
end
assign litedramcore_sel = litedramcore_storage[0];
assign litedramcore_cke = litedramcore_storage[1];
assign interface2_bank_bus_dat_w = csr_interconnect_dat_w;
assign csr_interconnect_dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r);
always @(*) begin
- rhs_array_muxed0 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0];
- end
- 1'd1: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1];
- end
- 2'd2: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2];
- end
- 2'd3: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3];
- end
- 3'd4: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4];
- end
- 3'd5: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5];
- end
- 3'd6: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6];
- end
- default: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7];
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed1 <= 15'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a;
- end
- 1'd1: begin
- rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a;
- end
- 2'd2: begin
- rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a;
- end
- 2'd3: begin
- rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a;
- end
- 3'd4: begin
- rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a;
- end
- 3'd5: begin
- rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a;
- end
- 3'd6: begin
- rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a;
- end
- default: begin
- rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed2 <= 3'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba;
- end
- 1'd1: begin
- rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba;
- end
- 2'd2: begin
- rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba;
- end
- 2'd3: begin
- rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba;
- end
- 3'd4: begin
- rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba;
- end
- 3'd5: begin
- rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba;
- end
- 3'd6: begin
- rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba;
- end
- default: begin
- rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed3 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read;
- end
- 1'd1: begin
- rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read;
- end
- 2'd2: begin
- rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read;
- end
- 2'd3: begin
- rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read;
- end
- 3'd4: begin
- rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read;
- end
- 3'd5: begin
- rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read;
- end
- 3'd6: begin
- rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read;
- end
- default: begin
- rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed4 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write;
- end
- 1'd1: begin
- rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write;
- end
- 2'd2: begin
- rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write;
- end
- 2'd3: begin
- rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write;
- end
- 3'd4: begin
- rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write;
- end
- 3'd5: begin
- rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write;
- end
- 3'd6: begin
- rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write;
- end
- default: begin
- rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed5 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
- end
- 1'd1: begin
- rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
- end
- 2'd2: begin
- rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
- end
- 2'd3: begin
- rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
- end
- 3'd4: begin
- rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
- end
- 3'd5: begin
- rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
- end
- 3'd6: begin
- rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
- end
- default: begin
- rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
- end
- endcase
-end
-always @(*) begin
- t_array_muxed0 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas;
- end
- 1'd1: begin
- t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas;
- end
- 2'd2: begin
- t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas;
- end
- 2'd3: begin
- t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas;
- end
- 3'd4: begin
- t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas;
- end
- 3'd5: begin
- t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas;
- end
- 3'd6: begin
- t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas;
- end
- default: begin
- t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas;
- end
- endcase
-end
-always @(*) begin
- t_array_muxed1 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras;
- end
- 1'd1: begin
- t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras;
- end
- 2'd2: begin
- t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras;
- end
- 2'd3: begin
- t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras;
- end
- 3'd4: begin
- t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras;
- end
- 3'd5: begin
- t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras;
- end
- 3'd6: begin
- t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras;
- end
- default: begin
- t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras;
- end
- endcase
-end
-always @(*) begin
- t_array_muxed2 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we;
- end
- 1'd1: begin
- t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we;
- end
- 2'd2: begin
- t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we;
- end
- 2'd3: begin
- t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we;
- end
- 3'd4: begin
- t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we;
- end
- 3'd5: begin
- t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we;
- end
- 3'd6: begin
- t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we;
- end
- default: begin
- t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed6 <= 1'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[0];
- end
- 1'd1: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[1];
- end
- 2'd2: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[2];
- end
- 2'd3: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[3];
- end
- 3'd4: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[4];
- end
- 3'd5: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[5];
- end
- 3'd6: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[6];
- end
- default: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[7];
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed7 <= 15'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a;
- end
- 1'd1: begin
- rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a;
- end
- 2'd2: begin
- rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a;
- end
- 2'd3: begin
- rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a;
- end
- 3'd4: begin
- rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a;
- end
- 3'd5: begin
- rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a;
- end
- 3'd6: begin
- rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a;
- end
- default: begin
- rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed8 <= 3'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba;
- end
- 1'd1: begin
- rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba;
- end
- 2'd2: begin
- rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba;
- end
- 2'd3: begin
- rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba;
- end
- 3'd4: begin
- rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba;
- end
- 3'd5: begin
- rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba;
- end
- 3'd6: begin
- rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba;
- end
- default: begin
- rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed9 <= 1'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read;
- end
- 1'd1: begin
- rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read;
- end
- 2'd2: begin
- rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read;
- end
- 2'd3: begin
- rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read;
- end
- 3'd4: begin
- rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read;
- end
- 3'd5: begin
- rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read;
- end
- 3'd6: begin
- rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read;
- end
- default: begin
- rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed10 <= 1'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write;
- end
- 1'd1: begin
- rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write;
- end
- 2'd2: begin
- rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write;
- end
- 2'd3: begin
- rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write;
- end
- 3'd4: begin
- rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write;
- end
- 3'd5: begin
- rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write;
- end
- 3'd6: begin
- rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write;
- end
- default: begin
- rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed11 <= 1'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
- end
- 1'd1: begin
- rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
- end
- 2'd2: begin
- rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
- end
- 2'd3: begin
- rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
- end
- 3'd4: begin
- rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
- end
- 3'd5: begin
- rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
- end
- 3'd6: begin
- rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
- end
- default: begin
- rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
- end
- endcase
-end
-always @(*) begin
- t_array_muxed3 <= 1'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas;
- end
- 1'd1: begin
- t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas;
- end
- 2'd2: begin
- t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas;
- end
- 2'd3: begin
- t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas;
- end
- 3'd4: begin
- t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas;
- end
- 3'd5: begin
- t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas;
- end
- 3'd6: begin
- t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas;
- end
- default: begin
- t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas;
- end
- endcase
-end
-always @(*) begin
- t_array_muxed4 <= 1'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras;
- end
- 1'd1: begin
- t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras;
- end
- 2'd2: begin
- t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras;
- end
- 2'd3: begin
- t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras;
- end
- 3'd4: begin
- t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras;
- end
- 3'd5: begin
- t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras;
- end
- 3'd6: begin
- t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras;
- end
- default: begin
- t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras;
- end
- endcase
-end
-always @(*) begin
- t_array_muxed5 <= 1'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we;
- end
- 1'd1: begin
- t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we;
- end
- 2'd2: begin
- t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we;
- end
- 2'd3: begin
- t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we;
- end
- 3'd4: begin
- t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we;
- end
- 3'd5: begin
- t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we;
- end
- 3'd6: begin
- t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we;
- end
- default: begin
- t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed12 <= 22'd0;
- case (litedramcore_roundrobin0_grant)
- default: begin
- rhs_array_muxed12 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed13 <= 1'd0;
- case (litedramcore_roundrobin0_grant)
- default: begin
- rhs_array_muxed13 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed14 <= 1'd0;
- case (litedramcore_roundrobin0_grant)
- default: begin
- rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed15 <= 22'd0;
- case (litedramcore_roundrobin1_grant)
- default: begin
- rhs_array_muxed15 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed16 <= 1'd0;
- case (litedramcore_roundrobin1_grant)
- default: begin
- rhs_array_muxed16 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed17 <= 1'd0;
- case (litedramcore_roundrobin1_grant)
- default: begin
- rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed18 <= 22'd0;
- case (litedramcore_roundrobin2_grant)
- default: begin
- rhs_array_muxed18 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed19 <= 1'd0;
- case (litedramcore_roundrobin2_grant)
- default: begin
- rhs_array_muxed19 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed20 <= 1'd0;
- case (litedramcore_roundrobin2_grant)
- default: begin
- rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed21 <= 22'd0;
- case (litedramcore_roundrobin3_grant)
- default: begin
- rhs_array_muxed21 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed22 <= 1'd0;
- case (litedramcore_roundrobin3_grant)
- default: begin
- rhs_array_muxed22 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed23 <= 1'd0;
- case (litedramcore_roundrobin3_grant)
- default: begin
- rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
+ rhs_array_muxed0 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0];
+ end
+ 1'd1: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1];
+ end
+ 2'd2: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2];
+ end
+ 2'd3: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3];
+ end
+ 3'd4: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4];
+ end
+ 3'd5: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5];
+ end
+ 3'd6: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6];
+ end
+ default: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7];
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed1 <= 15'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a;
+ end
+ 1'd1: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a;
+ end
+ 2'd2: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a;
+ end
+ 2'd3: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a;
+ end
+ 3'd4: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a;
+ end
+ 3'd5: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a;
+ end
+ 3'd6: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a;
+ end
+ default: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed2 <= 3'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba;
+ end
+ 1'd1: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba;
+ end
+ 2'd2: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba;
+ end
+ 2'd3: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba;
+ end
+ 3'd4: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba;
+ end
+ 3'd5: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba;
+ end
+ 3'd6: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba;
+ end
+ default: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed3 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read;
+ end
+ 1'd1: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read;
+ end
+ 2'd2: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read;
+ end
+ 2'd3: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read;
+ end
+ 3'd4: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read;
+ end
+ 3'd5: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read;
+ end
+ 3'd6: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read;
+ end
+ default: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed4 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write;
+ end
+ 1'd1: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write;
+ end
+ 2'd2: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write;
+ end
+ 2'd3: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write;
+ end
+ 3'd4: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write;
+ end
+ 3'd5: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write;
+ end
+ 3'd6: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write;
+ end
+ default: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed5 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
+ end
+ 1'd1: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
+ end
+ 2'd2: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
+ end
+ 2'd3: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
+ end
+ 3'd4: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
+ end
+ 3'd5: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
+ end
+ 3'd6: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
+ end
+ default: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed0 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas;
+ end
+ 1'd1: begin
+ t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas;
+ end
+ 2'd2: begin
+ t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas;
+ end
+ 2'd3: begin
+ t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas;
+ end
+ 3'd4: begin
+ t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas;
+ end
+ 3'd5: begin
+ t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas;
+ end
+ 3'd6: begin
+ t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas;
+ end
+ default: begin
+ t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed1 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras;
+ end
+ 1'd1: begin
+ t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras;
+ end
+ 2'd2: begin
+ t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras;
+ end
+ 2'd3: begin
+ t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras;
+ end
+ 3'd4: begin
+ t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras;
+ end
+ 3'd5: begin
+ t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras;
+ end
+ 3'd6: begin
+ t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras;
+ end
+ default: begin
+ t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed2 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we;
+ end
+ 1'd1: begin
+ t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we;
+ end
+ 2'd2: begin
+ t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we;
+ end
+ 2'd3: begin
+ t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we;
+ end
+ 3'd4: begin
+ t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we;
+ end
+ 3'd5: begin
+ t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we;
+ end
+ 3'd6: begin
+ t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we;
+ end
+ default: begin
+ t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed6 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[0];
+ end
+ 1'd1: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[1];
+ end
+ 2'd2: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[2];
+ end
+ 2'd3: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[3];
+ end
+ 3'd4: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[4];
+ end
+ 3'd5: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[5];
+ end
+ 3'd6: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[6];
+ end
+ default: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[7];
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed7 <= 15'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a;
+ end
+ 1'd1: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a;
+ end
+ 2'd2: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a;
+ end
+ 2'd3: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a;
+ end
+ 3'd4: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a;
+ end
+ 3'd5: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a;
+ end
+ 3'd6: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a;
+ end
+ default: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed8 <= 3'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba;
+ end
+ 1'd1: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba;
+ end
+ 2'd2: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba;
+ end
+ 2'd3: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba;
+ end
+ 3'd4: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba;
+ end
+ 3'd5: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba;
+ end
+ 3'd6: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba;
+ end
+ default: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed9 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read;
+ end
+ 1'd1: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read;
+ end
+ 2'd2: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read;
+ end
+ 2'd3: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read;
+ end
+ 3'd4: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read;
+ end
+ 3'd5: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read;
+ end
+ 3'd6: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read;
+ end
+ default: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed10 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write;
+ end
+ 1'd1: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write;
+ end
+ 2'd2: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write;
+ end
+ 2'd3: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write;
+ end
+ 3'd4: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write;
+ end
+ 3'd5: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write;
+ end
+ 3'd6: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write;
+ end
+ default: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed11 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
+ end
+ 1'd1: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
+ end
+ 2'd2: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
+ end
+ 2'd3: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
+ end
+ 3'd4: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
+ end
+ 3'd5: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
+ end
+ 3'd6: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
+ end
+ default: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed3 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas;
+ end
+ 1'd1: begin
+ t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas;
+ end
+ 2'd2: begin
+ t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas;
+ end
+ 2'd3: begin
+ t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas;
+ end
+ 3'd4: begin
+ t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas;
+ end
+ 3'd5: begin
+ t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas;
+ end
+ 3'd6: begin
+ t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas;
+ end
+ default: begin
+ t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed4 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras;
+ end
+ 1'd1: begin
+ t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras;
+ end
+ 2'd2: begin
+ t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras;
+ end
+ 2'd3: begin
+ t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras;
+ end
+ 3'd4: begin
+ t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras;
+ end
+ 3'd5: begin
+ t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras;
+ end
+ 3'd6: begin
+ t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras;
+ end
+ default: begin
+ t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed5 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we;
+ end
+ 1'd1: begin
+ t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we;
+ end
+ 2'd2: begin
+ t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we;
+ end
+ 2'd3: begin
+ t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we;
+ end
+ 3'd4: begin
+ t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we;
+ end
+ 3'd5: begin
+ t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we;
+ end
+ 3'd6: begin
+ t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we;
+ end
+ default: begin
+ t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed12 <= 22'd0;
+ case (litedramcore_roundrobin0_grant)
+ default: begin
+ rhs_array_muxed12 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed13 <= 1'd0;
+ case (litedramcore_roundrobin0_grant)
+ default: begin
+ rhs_array_muxed13 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed14 <= 1'd0;
+ case (litedramcore_roundrobin0_grant)
+ default: begin
+ rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed15 <= 22'd0;
+ case (litedramcore_roundrobin1_grant)
+ default: begin
+ rhs_array_muxed15 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed16 <= 1'd0;
+ case (litedramcore_roundrobin1_grant)
+ default: begin
+ rhs_array_muxed16 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed17 <= 1'd0;
+ case (litedramcore_roundrobin1_grant)
+ default: begin
+ rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed18 <= 22'd0;
+ case (litedramcore_roundrobin2_grant)
+ default: begin
+ rhs_array_muxed18 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed19 <= 1'd0;
+ case (litedramcore_roundrobin2_grant)
+ default: begin
+ rhs_array_muxed19 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed20 <= 1'd0;
+ case (litedramcore_roundrobin2_grant)
+ default: begin
+ rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed21 <= 22'd0;
+ case (litedramcore_roundrobin3_grant)
+ default: begin
+ rhs_array_muxed21 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed22 <= 1'd0;
+ case (litedramcore_roundrobin3_grant)
+ default: begin
+ rhs_array_muxed22 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed23 <= 1'd0;
+ case (litedramcore_roundrobin3_grant)
+ default: begin
+ rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
end
always @(*) begin
- rhs_array_muxed24 <= 22'd0;
- case (litedramcore_roundrobin4_grant)
- default: begin
- rhs_array_muxed24 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed25 <= 1'd0;
- case (litedramcore_roundrobin4_grant)
- default: begin
- rhs_array_muxed25 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed26 <= 1'd0;
- case (litedramcore_roundrobin4_grant)
- default: begin
- rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed27 <= 22'd0;
- case (litedramcore_roundrobin5_grant)
- default: begin
- rhs_array_muxed27 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed28 <= 1'd0;
- case (litedramcore_roundrobin5_grant)
- default: begin
- rhs_array_muxed28 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed29 <= 1'd0;
- case (litedramcore_roundrobin5_grant)
- default: begin
- rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed30 <= 22'd0;
- case (litedramcore_roundrobin6_grant)
- default: begin
- rhs_array_muxed30 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed31 <= 1'd0;
- case (litedramcore_roundrobin6_grant)
- default: begin
- rhs_array_muxed31 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed32 <= 1'd0;
- case (litedramcore_roundrobin6_grant)
- default: begin
- rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed33 <= 22'd0;
- case (litedramcore_roundrobin7_grant)
- default: begin
- rhs_array_muxed33 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed34 <= 1'd0;
- case (litedramcore_roundrobin7_grant)
- default: begin
- rhs_array_muxed34 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed35 <= 1'd0;
- case (litedramcore_roundrobin7_grant)
- default: begin
- rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- array_muxed0 <= 3'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed0 <= litedramcore_nop_ba[2:0];
- end
- 1'd1: begin
- array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
- end
- 2'd2: begin
- array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0];
- end
- default: begin
- array_muxed0 <= litedramcore_cmd_payload_ba[2:0];
- end
- endcase
-end
-always @(*) begin
- array_muxed1 <= 15'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed1 <= litedramcore_nop_a;
- end
- 1'd1: begin
- array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a;
- end
- 2'd2: begin
- array_muxed1 <= litedramcore_choose_req_cmd_payload_a;
- end
- default: begin
- array_muxed1 <= litedramcore_cmd_payload_a;
- end
- endcase
-end
-always @(*) begin
- array_muxed2 <= 1'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed2 <= 1'd0;
- end
- 1'd1: begin
- array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
- end
- 2'd2: begin
- array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
- end
- default: begin
- array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
- end
- endcase
-end
-always @(*) begin
- array_muxed3 <= 1'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed3 <= 1'd0;
- end
- 1'd1: begin
- array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
- end
- 2'd2: begin
- array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
- end
- default: begin
- array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
- end
- endcase
-end
-always @(*) begin
- array_muxed4 <= 1'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed4 <= 1'd0;
- end
- 1'd1: begin
- array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
- end
- 2'd2: begin
- array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
- end
- default: begin
- array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
- end
- endcase
-end
-always @(*) begin
- array_muxed5 <= 1'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed5 <= 1'd0;
- end
- 1'd1: begin
- array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
- end
- 2'd2: begin
- array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
- end
- default: begin
- array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
- end
- endcase
-end
-always @(*) begin
- array_muxed6 <= 1'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed6 <= 1'd0;
- end
- 1'd1: begin
- array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
- end
- 2'd2: begin
- array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
- end
- default: begin
- array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
- end
- endcase
-end
-always @(*) begin
- array_muxed7 <= 3'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed7 <= litedramcore_nop_ba[2:0];
- end
- 1'd1: begin
- array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
- end
- 2'd2: begin
- array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0];
- end
- default: begin
- array_muxed7 <= litedramcore_cmd_payload_ba[2:0];
- end
- endcase
-end
-always @(*) begin
- array_muxed8 <= 15'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed8 <= litedramcore_nop_a;
- end
- 1'd1: begin
- array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a;
- end
- 2'd2: begin
- array_muxed8 <= litedramcore_choose_req_cmd_payload_a;
- end
- default: begin
- array_muxed8 <= litedramcore_cmd_payload_a;
- end
- endcase
-end
-always @(*) begin
- array_muxed9 <= 1'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed9 <= 1'd0;
- end
- 1'd1: begin
- array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
- end
- 2'd2: begin
- array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
- end
- default: begin
- array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
- end
- endcase
-end
-always @(*) begin
- array_muxed10 <= 1'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed10 <= 1'd0;
- end
- 1'd1: begin
- array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
- end
- 2'd2: begin
- array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
- end
- default: begin
- array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
- end
- endcase
-end
-always @(*) begin
- array_muxed11 <= 1'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed11 <= 1'd0;
- end
- 1'd1: begin
- array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
- end
- 2'd2: begin
- array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
- end
- default: begin
- array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
- end
- endcase
-end
-always @(*) begin
- array_muxed12 <= 1'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed12 <= 1'd0;
- end
- 1'd1: begin
- array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
- end
- 2'd2: begin
- array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
- end
- default: begin
- array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
- end
- endcase
-end
-always @(*) begin
- array_muxed13 <= 1'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed13 <= 1'd0;
- end
- 1'd1: begin
- array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
- end
- 2'd2: begin
- array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
- end
- default: begin
- array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
- end
- endcase
-end
-always @(*) begin
- array_muxed14 <= 3'd0;
- case (litedramcore_steerer_sel2)
- 1'd0: begin
- array_muxed14 <= litedramcore_nop_ba[2:0];
- end
- 1'd1: begin
- array_muxed14 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
- end
- 2'd2: begin
- array_muxed14 <= litedramcore_choose_req_cmd_payload_ba[2:0];
- end
- default: begin
- array_muxed14 <= litedramcore_cmd_payload_ba[2:0];
- end
- endcase
-end
-always @(*) begin
- array_muxed15 <= 15'd0;
- case (litedramcore_steerer_sel2)
- 1'd0: begin
- array_muxed15 <= litedramcore_nop_a;
- end
- 1'd1: begin
- array_muxed15 <= litedramcore_choose_cmd_cmd_payload_a;
- end
- 2'd2: begin
- array_muxed15 <= litedramcore_choose_req_cmd_payload_a;
- end
- default: begin
- array_muxed15 <= litedramcore_cmd_payload_a;
- end
- endcase
-end
-always @(*) begin
- array_muxed16 <= 1'd0;
- case (litedramcore_steerer_sel2)
- 1'd0: begin
- array_muxed16 <= 1'd0;
- end
- 1'd1: begin
- array_muxed16 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
- end
- 2'd2: begin
- array_muxed16 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
- end
- default: begin
- array_muxed16 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
- end
- endcase
-end
-always @(*) begin
- array_muxed17 <= 1'd0;
- case (litedramcore_steerer_sel2)
- 1'd0: begin
- array_muxed17 <= 1'd0;
- end
- 1'd1: begin
- array_muxed17 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
- end
- 2'd2: begin
- array_muxed17 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
- end
- default: begin
- array_muxed17 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
- end
- endcase
-end
-always @(*) begin
- array_muxed18 <= 1'd0;
- case (litedramcore_steerer_sel2)
- 1'd0: begin
- array_muxed18 <= 1'd0;
- end
- 1'd1: begin
- array_muxed18 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
- end
- 2'd2: begin
- array_muxed18 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
- end
- default: begin
- array_muxed18 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
- end
- endcase
-end
-always @(*) begin
- array_muxed19 <= 1'd0;
- case (litedramcore_steerer_sel2)
- 1'd0: begin
- array_muxed19 <= 1'd0;
- end
- 1'd1: begin
- array_muxed19 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
- end
- 2'd2: begin
- array_muxed19 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
- end
- default: begin
- array_muxed19 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
- end
- endcase
-end
-always @(*) begin
- array_muxed20 <= 1'd0;
- case (litedramcore_steerer_sel2)
- 1'd0: begin
- array_muxed20 <= 1'd0;
- end
- 1'd1: begin
- array_muxed20 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
- end
- 2'd2: begin
- array_muxed20 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
- end
- default: begin
- array_muxed20 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
- end
- endcase
-end
-always @(*) begin
- array_muxed21 <= 3'd0;
- case (litedramcore_steerer_sel3)
- 1'd0: begin
- array_muxed21 <= litedramcore_nop_ba[2:0];
- end
- 1'd1: begin
- array_muxed21 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
- end
- 2'd2: begin
- array_muxed21 <= litedramcore_choose_req_cmd_payload_ba[2:0];
- end
- default: begin
- array_muxed21 <= litedramcore_cmd_payload_ba[2:0];
- end
- endcase
-end
-always @(*) begin
- array_muxed22 <= 15'd0;
- case (litedramcore_steerer_sel3)
- 1'd0: begin
- array_muxed22 <= litedramcore_nop_a;
- end
- 1'd1: begin
- array_muxed22 <= litedramcore_choose_cmd_cmd_payload_a;
- end
- 2'd2: begin
- array_muxed22 <= litedramcore_choose_req_cmd_payload_a;
- end
- default: begin
- array_muxed22 <= litedramcore_cmd_payload_a;
- end
- endcase
-end
-always @(*) begin
- array_muxed23 <= 1'd0;
- case (litedramcore_steerer_sel3)
- 1'd0: begin
- array_muxed23 <= 1'd0;
- end
- 1'd1: begin
- array_muxed23 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
- end
- 2'd2: begin
- array_muxed23 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
- end
- default: begin
- array_muxed23 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
- end
- endcase
-end
-always @(*) begin
- array_muxed24 <= 1'd0;
- case (litedramcore_steerer_sel3)
- 1'd0: begin
- array_muxed24 <= 1'd0;
- end
- 1'd1: begin
- array_muxed24 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
- end
- 2'd2: begin
- array_muxed24 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
- end
- default: begin
- array_muxed24 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
- end
- endcase
-end
-always @(*) begin
- array_muxed25 <= 1'd0;
- case (litedramcore_steerer_sel3)
- 1'd0: begin
- array_muxed25 <= 1'd0;
- end
- 1'd1: begin
- array_muxed25 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
- end
- 2'd2: begin
- array_muxed25 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
- end
- default: begin
- array_muxed25 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
- end
- endcase
-end
-always @(*) begin
- array_muxed26 <= 1'd0;
- case (litedramcore_steerer_sel3)
- 1'd0: begin
- array_muxed26 <= 1'd0;
- end
- 1'd1: begin
- array_muxed26 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
- end
- 2'd2: begin
- array_muxed26 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
- end
- default: begin
- array_muxed26 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
- end
- endcase
-end
-always @(*) begin
- array_muxed27 <= 1'd0;
- case (litedramcore_steerer_sel3)
- 1'd0: begin
- array_muxed27 <= 1'd0;
- end
- 1'd1: begin
- array_muxed27 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
- end
- 2'd2: begin
- array_muxed27 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
- end
- default: begin
- array_muxed27 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
- end
- endcase
+ rhs_array_muxed24 <= 22'd0;
+ case (litedramcore_roundrobin4_grant)
+ default: begin
+ rhs_array_muxed24 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed25 <= 1'd0;
+ case (litedramcore_roundrobin4_grant)
+ default: begin
+ rhs_array_muxed25 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed26 <= 1'd0;
+ case (litedramcore_roundrobin4_grant)
+ default: begin
+ rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed27 <= 22'd0;
+ case (litedramcore_roundrobin5_grant)
+ default: begin
+ rhs_array_muxed27 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed28 <= 1'd0;
+ case (litedramcore_roundrobin5_grant)
+ default: begin
+ rhs_array_muxed28 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed29 <= 1'd0;
+ case (litedramcore_roundrobin5_grant)
+ default: begin
+ rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed30 <= 22'd0;
+ case (litedramcore_roundrobin6_grant)
+ default: begin
+ rhs_array_muxed30 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed31 <= 1'd0;
+ case (litedramcore_roundrobin6_grant)
+ default: begin
+ rhs_array_muxed31 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed32 <= 1'd0;
+ case (litedramcore_roundrobin6_grant)
+ default: begin
+ rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed33 <= 22'd0;
+ case (litedramcore_roundrobin7_grant)
+ default: begin
+ rhs_array_muxed33 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed34 <= 1'd0;
+ case (litedramcore_roundrobin7_grant)
+ default: begin
+ rhs_array_muxed34 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed35 <= 1'd0;
+ case (litedramcore_roundrobin7_grant)
+ default: begin
+ rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed0 <= 3'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed0 <= litedramcore_nop_ba[2:0];
+ end
+ 1'd1: begin
+ array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+ end
+ 2'd2: begin
+ array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+ end
+ default: begin
+ array_muxed0 <= litedramcore_cmd_payload_ba[2:0];
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed1 <= 15'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed1 <= litedramcore_nop_a;
+ end
+ 1'd1: begin
+ array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a;
+ end
+ 2'd2: begin
+ array_muxed1 <= litedramcore_choose_req_cmd_payload_a;
+ end
+ default: begin
+ array_muxed1 <= litedramcore_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed2 <= 1'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed2 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+ end
+ 2'd2: begin
+ array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+ end
+ default: begin
+ array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed3 <= 1'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed3 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+ end
+ 2'd2: begin
+ array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+ end
+ default: begin
+ array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed4 <= 1'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed4 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+ end
+ 2'd2: begin
+ array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+ end
+ default: begin
+ array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed5 <= 1'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed5 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+ end
+ 2'd2: begin
+ array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+ end
+ default: begin
+ array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed6 <= 1'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed6 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+ end
+ 2'd2: begin
+ array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+ end
+ default: begin
+ array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed7 <= 3'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed7 <= litedramcore_nop_ba[2:0];
+ end
+ 1'd1: begin
+ array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+ end
+ 2'd2: begin
+ array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+ end
+ default: begin
+ array_muxed7 <= litedramcore_cmd_payload_ba[2:0];
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed8 <= 15'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed8 <= litedramcore_nop_a;
+ end
+ 1'd1: begin
+ array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a;
+ end
+ 2'd2: begin
+ array_muxed8 <= litedramcore_choose_req_cmd_payload_a;
+ end
+ default: begin
+ array_muxed8 <= litedramcore_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed9 <= 1'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed9 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+ end
+ 2'd2: begin
+ array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+ end
+ default: begin
+ array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed10 <= 1'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed10 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+ end
+ 2'd2: begin
+ array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+ end
+ default: begin
+ array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed11 <= 1'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed11 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+ end
+ 2'd2: begin
+ array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+ end
+ default: begin
+ array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed12 <= 1'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed12 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+ end
+ 2'd2: begin
+ array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+ end
+ default: begin
+ array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed13 <= 1'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed13 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+ end
+ 2'd2: begin
+ array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+ end
+ default: begin
+ array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed14 <= 3'd0;
+ case (litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed14 <= litedramcore_nop_ba[2:0];
+ end
+ 1'd1: begin
+ array_muxed14 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+ end
+ 2'd2: begin
+ array_muxed14 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+ end
+ default: begin
+ array_muxed14 <= litedramcore_cmd_payload_ba[2:0];
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed15 <= 15'd0;
+ case (litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed15 <= litedramcore_nop_a;
+ end
+ 1'd1: begin
+ array_muxed15 <= litedramcore_choose_cmd_cmd_payload_a;
+ end
+ 2'd2: begin
+ array_muxed15 <= litedramcore_choose_req_cmd_payload_a;
+ end
+ default: begin
+ array_muxed15 <= litedramcore_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed16 <= 1'd0;
+ case (litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed16 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed16 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+ end
+ 2'd2: begin
+ array_muxed16 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+ end
+ default: begin
+ array_muxed16 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed17 <= 1'd0;
+ case (litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed17 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed17 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+ end
+ 2'd2: begin
+ array_muxed17 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+ end
+ default: begin
+ array_muxed17 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed18 <= 1'd0;
+ case (litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed18 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed18 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+ end
+ 2'd2: begin
+ array_muxed18 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+ end
+ default: begin
+ array_muxed18 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed19 <= 1'd0;
+ case (litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed19 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed19 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+ end
+ 2'd2: begin
+ array_muxed19 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+ end
+ default: begin
+ array_muxed19 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed20 <= 1'd0;
+ case (litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed20 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed20 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+ end
+ 2'd2: begin
+ array_muxed20 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+ end
+ default: begin
+ array_muxed20 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed21 <= 3'd0;
+ case (litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed21 <= litedramcore_nop_ba[2:0];
+ end
+ 1'd1: begin
+ array_muxed21 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+ end
+ 2'd2: begin
+ array_muxed21 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+ end
+ default: begin
+ array_muxed21 <= litedramcore_cmd_payload_ba[2:0];
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed22 <= 15'd0;
+ case (litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed22 <= litedramcore_nop_a;
+ end
+ 1'd1: begin
+ array_muxed22 <= litedramcore_choose_cmd_cmd_payload_a;
+ end
+ 2'd2: begin
+ array_muxed22 <= litedramcore_choose_req_cmd_payload_a;
+ end
+ default: begin
+ array_muxed22 <= litedramcore_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed23 <= 1'd0;
+ case (litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed23 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed23 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+ end
+ 2'd2: begin
+ array_muxed23 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+ end
+ default: begin
+ array_muxed23 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed24 <= 1'd0;
+ case (litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed24 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed24 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+ end
+ 2'd2: begin
+ array_muxed24 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+ end
+ default: begin
+ array_muxed24 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed25 <= 1'd0;
+ case (litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed25 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed25 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+ end
+ 2'd2: begin
+ array_muxed25 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+ end
+ default: begin
+ array_muxed25 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed26 <= 1'd0;
+ case (litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed26 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed26 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+ end
+ 2'd2: begin
+ array_muxed26 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+ end
+ default: begin
+ array_muxed26 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed27 <= 1'd0;
+ case (litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed27 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed27 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+ end
+ 2'd2: begin
+ array_muxed27 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+ end
+ default: begin
+ array_muxed27 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+ end
+ endcase
end
assign xilinxasyncresetsynchronizerimpl0 = (~locked);
assign xilinxasyncresetsynchronizerimpl1 = (~locked);
//------------------------------------------------------------------------------
always @(posedge iodelay_clk) begin
- if ((reset_counter != 1'd0)) begin
- reset_counter <= (reset_counter - 1'd1);
- end else begin
- ic_reset <= 1'd0;
- end
- if (iodelay_rst) begin
- reset_counter <= 4'd15;
- ic_reset <= 1'd1;
- end
+ if ((reset_counter != 1'd0)) begin
+ reset_counter <= (reset_counter - 1'd1);
+ end else begin
+ ic_reset <= 1'd0;
+ end
+ if (iodelay_rst) begin
+ reset_counter <= 4'd15;
+ ic_reset <= 1'd1;
+ end
end
always @(posedge sys_clk) begin
- k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= k7ddrphy_dqs_oe_delay_tappeddelayline;
- k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0;
- if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip0_value0 <= (k7ddrphy_bitslip0_value0 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip0_value0 <= 3'd7;
- end
- k7ddrphy_bitslip0_r0 <= {k7ddrphy_dqspattern_o, k7ddrphy_bitslip0_r0[15:8]};
- if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip1_value0 <= (k7ddrphy_bitslip1_value0 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip1_value0 <= 3'd7;
- end
- k7ddrphy_bitslip1_r0 <= {k7ddrphy_dqspattern_o, k7ddrphy_bitslip1_r0[15:8]};
- if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip2_value0 <= (k7ddrphy_bitslip2_value0 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip2_value0 <= 3'd7;
- end
- k7ddrphy_bitslip2_r0 <= {k7ddrphy_dqspattern_o, k7ddrphy_bitslip2_r0[15:8]};
- if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip3_value0 <= (k7ddrphy_bitslip3_value0 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip3_value0 <= 3'd7;
- end
- k7ddrphy_bitslip3_r0 <= {k7ddrphy_dqspattern_o, k7ddrphy_bitslip3_r0[15:8]};
- if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip0_value1 <= (k7ddrphy_bitslip0_value1 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip0_value1 <= 3'd7;
- end
- k7ddrphy_bitslip0_r1 <= {{k7ddrphy_dfi_p3_wrdata_mask[4], k7ddrphy_dfi_p3_wrdata_mask[0], k7ddrphy_dfi_p2_wrdata_mask[4], k7ddrphy_dfi_p2_wrdata_mask[0], k7ddrphy_dfi_p1_wrdata_mask[4], k7ddrphy_dfi_p1_wrdata_mask[0], k7ddrphy_dfi_p0_wrdata_mask[4], k7ddrphy_dfi_p0_wrdata_mask[0]}, k7ddrphy_bitslip0_r1[15:8]};
- if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip1_value1 <= (k7ddrphy_bitslip1_value1 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip1_value1 <= 3'd7;
- end
- k7ddrphy_bitslip1_r1 <= {{k7ddrphy_dfi_p3_wrdata_mask[5], k7ddrphy_dfi_p3_wrdata_mask[1], k7ddrphy_dfi_p2_wrdata_mask[5], k7ddrphy_dfi_p2_wrdata_mask[1], k7ddrphy_dfi_p1_wrdata_mask[5], k7ddrphy_dfi_p1_wrdata_mask[1], k7ddrphy_dfi_p0_wrdata_mask[5], k7ddrphy_dfi_p0_wrdata_mask[1]}, k7ddrphy_bitslip1_r1[15:8]};
- if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip2_value1 <= (k7ddrphy_bitslip2_value1 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip2_value1 <= 3'd7;
- end
- k7ddrphy_bitslip2_r1 <= {{k7ddrphy_dfi_p3_wrdata_mask[6], k7ddrphy_dfi_p3_wrdata_mask[2], k7ddrphy_dfi_p2_wrdata_mask[6], k7ddrphy_dfi_p2_wrdata_mask[2], k7ddrphy_dfi_p1_wrdata_mask[6], k7ddrphy_dfi_p1_wrdata_mask[2], k7ddrphy_dfi_p0_wrdata_mask[6], k7ddrphy_dfi_p0_wrdata_mask[2]}, k7ddrphy_bitslip2_r1[15:8]};
- if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip3_value1 <= (k7ddrphy_bitslip3_value1 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip3_value1 <= 3'd7;
- end
- k7ddrphy_bitslip3_r1 <= {{k7ddrphy_dfi_p3_wrdata_mask[7], k7ddrphy_dfi_p3_wrdata_mask[3], k7ddrphy_dfi_p2_wrdata_mask[7], k7ddrphy_dfi_p2_wrdata_mask[3], k7ddrphy_dfi_p1_wrdata_mask[7], k7ddrphy_dfi_p1_wrdata_mask[3], k7ddrphy_dfi_p0_wrdata_mask[7], k7ddrphy_dfi_p0_wrdata_mask[3]}, k7ddrphy_bitslip3_r1[15:8]};
- k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= k7ddrphy_dq_oe_delay_tappeddelayline;
- k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0;
- if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip0_value2 <= (k7ddrphy_bitslip0_value2 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip0_value2 <= 3'd7;
- end
- k7ddrphy_bitslip0_r2 <= {{k7ddrphy_dfi_p3_wrdata[32], k7ddrphy_dfi_p3_wrdata[0], k7ddrphy_dfi_p2_wrdata[32], k7ddrphy_dfi_p2_wrdata[0], k7ddrphy_dfi_p1_wrdata[32], k7ddrphy_dfi_p1_wrdata[0], k7ddrphy_dfi_p0_wrdata[32], k7ddrphy_dfi_p0_wrdata[0]}, k7ddrphy_bitslip0_r2[15:8]};
- if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip0_value3 <= (k7ddrphy_bitslip0_value3 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip0_value3 <= 3'd7;
- end
- k7ddrphy_bitslip0_r3 <= {k7ddrphy_bitslip03, k7ddrphy_bitslip0_r3[15:8]};
- if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip1_value2 <= (k7ddrphy_bitslip1_value2 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip1_value2 <= 3'd7;
- end
- k7ddrphy_bitslip1_r2 <= {{k7ddrphy_dfi_p3_wrdata[33], k7ddrphy_dfi_p3_wrdata[1], k7ddrphy_dfi_p2_wrdata[33], k7ddrphy_dfi_p2_wrdata[1], k7ddrphy_dfi_p1_wrdata[33], k7ddrphy_dfi_p1_wrdata[1], k7ddrphy_dfi_p0_wrdata[33], k7ddrphy_dfi_p0_wrdata[1]}, k7ddrphy_bitslip1_r2[15:8]};
- if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip1_value3 <= (k7ddrphy_bitslip1_value3 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip1_value3 <= 3'd7;
- end
- k7ddrphy_bitslip1_r3 <= {k7ddrphy_bitslip13, k7ddrphy_bitslip1_r3[15:8]};
- if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip2_value2 <= (k7ddrphy_bitslip2_value2 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip2_value2 <= 3'd7;
- end
- k7ddrphy_bitslip2_r2 <= {{k7ddrphy_dfi_p3_wrdata[34], k7ddrphy_dfi_p3_wrdata[2], k7ddrphy_dfi_p2_wrdata[34], k7ddrphy_dfi_p2_wrdata[2], k7ddrphy_dfi_p1_wrdata[34], k7ddrphy_dfi_p1_wrdata[2], k7ddrphy_dfi_p0_wrdata[34], k7ddrphy_dfi_p0_wrdata[2]}, k7ddrphy_bitslip2_r2[15:8]};
- if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip2_value3 <= (k7ddrphy_bitslip2_value3 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip2_value3 <= 3'd7;
- end
- k7ddrphy_bitslip2_r3 <= {k7ddrphy_bitslip23, k7ddrphy_bitslip2_r3[15:8]};
- if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip3_value2 <= (k7ddrphy_bitslip3_value2 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip3_value2 <= 3'd7;
- end
- k7ddrphy_bitslip3_r2 <= {{k7ddrphy_dfi_p3_wrdata[35], k7ddrphy_dfi_p3_wrdata[3], k7ddrphy_dfi_p2_wrdata[35], k7ddrphy_dfi_p2_wrdata[3], k7ddrphy_dfi_p1_wrdata[35], k7ddrphy_dfi_p1_wrdata[3], k7ddrphy_dfi_p0_wrdata[35], k7ddrphy_dfi_p0_wrdata[3]}, k7ddrphy_bitslip3_r2[15:8]};
- if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip3_value3 <= (k7ddrphy_bitslip3_value3 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip3_value3 <= 3'd7;
- end
- k7ddrphy_bitslip3_r3 <= {k7ddrphy_bitslip33, k7ddrphy_bitslip3_r3[15:8]};
- if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip4_value0 <= (k7ddrphy_bitslip4_value0 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip4_value0 <= 3'd7;
- end
- k7ddrphy_bitslip4_r0 <= {{k7ddrphy_dfi_p3_wrdata[36], k7ddrphy_dfi_p3_wrdata[4], k7ddrphy_dfi_p2_wrdata[36], k7ddrphy_dfi_p2_wrdata[4], k7ddrphy_dfi_p1_wrdata[36], k7ddrphy_dfi_p1_wrdata[4], k7ddrphy_dfi_p0_wrdata[36], k7ddrphy_dfi_p0_wrdata[4]}, k7ddrphy_bitslip4_r0[15:8]};
- if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip4_value1 <= (k7ddrphy_bitslip4_value1 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip4_value1 <= 3'd7;
- end
- k7ddrphy_bitslip4_r1 <= {k7ddrphy_bitslip41, k7ddrphy_bitslip4_r1[15:8]};
- if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip5_value0 <= (k7ddrphy_bitslip5_value0 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip5_value0 <= 3'd7;
- end
- k7ddrphy_bitslip5_r0 <= {{k7ddrphy_dfi_p3_wrdata[37], k7ddrphy_dfi_p3_wrdata[5], k7ddrphy_dfi_p2_wrdata[37], k7ddrphy_dfi_p2_wrdata[5], k7ddrphy_dfi_p1_wrdata[37], k7ddrphy_dfi_p1_wrdata[5], k7ddrphy_dfi_p0_wrdata[37], k7ddrphy_dfi_p0_wrdata[5]}, k7ddrphy_bitslip5_r0[15:8]};
- if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip5_value1 <= (k7ddrphy_bitslip5_value1 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip5_value1 <= 3'd7;
- end
- k7ddrphy_bitslip5_r1 <= {k7ddrphy_bitslip51, k7ddrphy_bitslip5_r1[15:8]};
- if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip6_value0 <= (k7ddrphy_bitslip6_value0 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip6_value0 <= 3'd7;
- end
- k7ddrphy_bitslip6_r0 <= {{k7ddrphy_dfi_p3_wrdata[38], k7ddrphy_dfi_p3_wrdata[6], k7ddrphy_dfi_p2_wrdata[38], k7ddrphy_dfi_p2_wrdata[6], k7ddrphy_dfi_p1_wrdata[38], k7ddrphy_dfi_p1_wrdata[6], k7ddrphy_dfi_p0_wrdata[38], k7ddrphy_dfi_p0_wrdata[6]}, k7ddrphy_bitslip6_r0[15:8]};
- if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip6_value1 <= (k7ddrphy_bitslip6_value1 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip6_value1 <= 3'd7;
- end
- k7ddrphy_bitslip6_r1 <= {k7ddrphy_bitslip61, k7ddrphy_bitslip6_r1[15:8]};
- if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip7_value0 <= (k7ddrphy_bitslip7_value0 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip7_value0 <= 3'd7;
- end
- k7ddrphy_bitslip7_r0 <= {{k7ddrphy_dfi_p3_wrdata[39], k7ddrphy_dfi_p3_wrdata[7], k7ddrphy_dfi_p2_wrdata[39], k7ddrphy_dfi_p2_wrdata[7], k7ddrphy_dfi_p1_wrdata[39], k7ddrphy_dfi_p1_wrdata[7], k7ddrphy_dfi_p0_wrdata[39], k7ddrphy_dfi_p0_wrdata[7]}, k7ddrphy_bitslip7_r0[15:8]};
- if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip7_value1 <= (k7ddrphy_bitslip7_value1 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip7_value1 <= 3'd7;
- end
- k7ddrphy_bitslip7_r1 <= {k7ddrphy_bitslip71, k7ddrphy_bitslip7_r1[15:8]};
- if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip8_value0 <= (k7ddrphy_bitslip8_value0 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip8_value0 <= 3'd7;
- end
- k7ddrphy_bitslip8_r0 <= {{k7ddrphy_dfi_p3_wrdata[40], k7ddrphy_dfi_p3_wrdata[8], k7ddrphy_dfi_p2_wrdata[40], k7ddrphy_dfi_p2_wrdata[8], k7ddrphy_dfi_p1_wrdata[40], k7ddrphy_dfi_p1_wrdata[8], k7ddrphy_dfi_p0_wrdata[40], k7ddrphy_dfi_p0_wrdata[8]}, k7ddrphy_bitslip8_r0[15:8]};
- if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip8_value1 <= (k7ddrphy_bitslip8_value1 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip8_value1 <= 3'd7;
- end
- k7ddrphy_bitslip8_r1 <= {k7ddrphy_bitslip81, k7ddrphy_bitslip8_r1[15:8]};
- if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip9_value0 <= (k7ddrphy_bitslip9_value0 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip9_value0 <= 3'd7;
- end
- k7ddrphy_bitslip9_r0 <= {{k7ddrphy_dfi_p3_wrdata[41], k7ddrphy_dfi_p3_wrdata[9], k7ddrphy_dfi_p2_wrdata[41], k7ddrphy_dfi_p2_wrdata[9], k7ddrphy_dfi_p1_wrdata[41], k7ddrphy_dfi_p1_wrdata[9], k7ddrphy_dfi_p0_wrdata[41], k7ddrphy_dfi_p0_wrdata[9]}, k7ddrphy_bitslip9_r0[15:8]};
- if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip9_value1 <= (k7ddrphy_bitslip9_value1 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip9_value1 <= 3'd7;
- end
- k7ddrphy_bitslip9_r1 <= {k7ddrphy_bitslip91, k7ddrphy_bitslip9_r1[15:8]};
- if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip10_value0 <= (k7ddrphy_bitslip10_value0 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip10_value0 <= 3'd7;
- end
- k7ddrphy_bitslip10_r0 <= {{k7ddrphy_dfi_p3_wrdata[42], k7ddrphy_dfi_p3_wrdata[10], k7ddrphy_dfi_p2_wrdata[42], k7ddrphy_dfi_p2_wrdata[10], k7ddrphy_dfi_p1_wrdata[42], k7ddrphy_dfi_p1_wrdata[10], k7ddrphy_dfi_p0_wrdata[42], k7ddrphy_dfi_p0_wrdata[10]}, k7ddrphy_bitslip10_r0[15:8]};
- if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip10_value1 <= (k7ddrphy_bitslip10_value1 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip10_value1 <= 3'd7;
- end
- k7ddrphy_bitslip10_r1 <= {k7ddrphy_bitslip101, k7ddrphy_bitslip10_r1[15:8]};
- if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip11_value0 <= (k7ddrphy_bitslip11_value0 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip11_value0 <= 3'd7;
- end
- k7ddrphy_bitslip11_r0 <= {{k7ddrphy_dfi_p3_wrdata[43], k7ddrphy_dfi_p3_wrdata[11], k7ddrphy_dfi_p2_wrdata[43], k7ddrphy_dfi_p2_wrdata[11], k7ddrphy_dfi_p1_wrdata[43], k7ddrphy_dfi_p1_wrdata[11], k7ddrphy_dfi_p0_wrdata[43], k7ddrphy_dfi_p0_wrdata[11]}, k7ddrphy_bitslip11_r0[15:8]};
- if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip11_value1 <= (k7ddrphy_bitslip11_value1 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip11_value1 <= 3'd7;
- end
- k7ddrphy_bitslip11_r1 <= {k7ddrphy_bitslip111, k7ddrphy_bitslip11_r1[15:8]};
- if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip12_value0 <= (k7ddrphy_bitslip12_value0 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip12_value0 <= 3'd7;
- end
- k7ddrphy_bitslip12_r0 <= {{k7ddrphy_dfi_p3_wrdata[44], k7ddrphy_dfi_p3_wrdata[12], k7ddrphy_dfi_p2_wrdata[44], k7ddrphy_dfi_p2_wrdata[12], k7ddrphy_dfi_p1_wrdata[44], k7ddrphy_dfi_p1_wrdata[12], k7ddrphy_dfi_p0_wrdata[44], k7ddrphy_dfi_p0_wrdata[12]}, k7ddrphy_bitslip12_r0[15:8]};
- if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip12_value1 <= (k7ddrphy_bitslip12_value1 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip12_value1 <= 3'd7;
- end
- k7ddrphy_bitslip12_r1 <= {k7ddrphy_bitslip121, k7ddrphy_bitslip12_r1[15:8]};
- if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip13_value0 <= (k7ddrphy_bitslip13_value0 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip13_value0 <= 3'd7;
- end
- k7ddrphy_bitslip13_r0 <= {{k7ddrphy_dfi_p3_wrdata[45], k7ddrphy_dfi_p3_wrdata[13], k7ddrphy_dfi_p2_wrdata[45], k7ddrphy_dfi_p2_wrdata[13], k7ddrphy_dfi_p1_wrdata[45], k7ddrphy_dfi_p1_wrdata[13], k7ddrphy_dfi_p0_wrdata[45], k7ddrphy_dfi_p0_wrdata[13]}, k7ddrphy_bitslip13_r0[15:8]};
- if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip13_value1 <= (k7ddrphy_bitslip13_value1 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip13_value1 <= 3'd7;
- end
- k7ddrphy_bitslip13_r1 <= {k7ddrphy_bitslip131, k7ddrphy_bitslip13_r1[15:8]};
- if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip14_value0 <= (k7ddrphy_bitslip14_value0 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip14_value0 <= 3'd7;
- end
- k7ddrphy_bitslip14_r0 <= {{k7ddrphy_dfi_p3_wrdata[46], k7ddrphy_dfi_p3_wrdata[14], k7ddrphy_dfi_p2_wrdata[46], k7ddrphy_dfi_p2_wrdata[14], k7ddrphy_dfi_p1_wrdata[46], k7ddrphy_dfi_p1_wrdata[14], k7ddrphy_dfi_p0_wrdata[46], k7ddrphy_dfi_p0_wrdata[14]}, k7ddrphy_bitslip14_r0[15:8]};
- if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip14_value1 <= (k7ddrphy_bitslip14_value1 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip14_value1 <= 3'd7;
- end
- k7ddrphy_bitslip14_r1 <= {k7ddrphy_bitslip141, k7ddrphy_bitslip14_r1[15:8]};
- if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip15_value0 <= (k7ddrphy_bitslip15_value0 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip15_value0 <= 3'd7;
- end
- k7ddrphy_bitslip15_r0 <= {{k7ddrphy_dfi_p3_wrdata[47], k7ddrphy_dfi_p3_wrdata[15], k7ddrphy_dfi_p2_wrdata[47], k7ddrphy_dfi_p2_wrdata[15], k7ddrphy_dfi_p1_wrdata[47], k7ddrphy_dfi_p1_wrdata[15], k7ddrphy_dfi_p0_wrdata[47], k7ddrphy_dfi_p0_wrdata[15]}, k7ddrphy_bitslip15_r0[15:8]};
- if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip15_value1 <= (k7ddrphy_bitslip15_value1 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip15_value1 <= 3'd7;
- end
- k7ddrphy_bitslip15_r1 <= {k7ddrphy_bitslip151, k7ddrphy_bitslip15_r1[15:8]};
- if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip16_value0 <= (k7ddrphy_bitslip16_value0 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip16_value0 <= 3'd7;
- end
- k7ddrphy_bitslip16_r0 <= {{k7ddrphy_dfi_p3_wrdata[48], k7ddrphy_dfi_p3_wrdata[16], k7ddrphy_dfi_p2_wrdata[48], k7ddrphy_dfi_p2_wrdata[16], k7ddrphy_dfi_p1_wrdata[48], k7ddrphy_dfi_p1_wrdata[16], k7ddrphy_dfi_p0_wrdata[48], k7ddrphy_dfi_p0_wrdata[16]}, k7ddrphy_bitslip16_r0[15:8]};
- if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip16_value1 <= (k7ddrphy_bitslip16_value1 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip16_value1 <= 3'd7;
- end
- k7ddrphy_bitslip16_r1 <= {k7ddrphy_bitslip161, k7ddrphy_bitslip16_r1[15:8]};
- if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip17_value0 <= (k7ddrphy_bitslip17_value0 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip17_value0 <= 3'd7;
- end
- k7ddrphy_bitslip17_r0 <= {{k7ddrphy_dfi_p3_wrdata[49], k7ddrphy_dfi_p3_wrdata[17], k7ddrphy_dfi_p2_wrdata[49], k7ddrphy_dfi_p2_wrdata[17], k7ddrphy_dfi_p1_wrdata[49], k7ddrphy_dfi_p1_wrdata[17], k7ddrphy_dfi_p0_wrdata[49], k7ddrphy_dfi_p0_wrdata[17]}, k7ddrphy_bitslip17_r0[15:8]};
- if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip17_value1 <= (k7ddrphy_bitslip17_value1 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip17_value1 <= 3'd7;
- end
- k7ddrphy_bitslip17_r1 <= {k7ddrphy_bitslip171, k7ddrphy_bitslip17_r1[15:8]};
- if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip18_value0 <= (k7ddrphy_bitslip18_value0 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip18_value0 <= 3'd7;
- end
- k7ddrphy_bitslip18_r0 <= {{k7ddrphy_dfi_p3_wrdata[50], k7ddrphy_dfi_p3_wrdata[18], k7ddrphy_dfi_p2_wrdata[50], k7ddrphy_dfi_p2_wrdata[18], k7ddrphy_dfi_p1_wrdata[50], k7ddrphy_dfi_p1_wrdata[18], k7ddrphy_dfi_p0_wrdata[50], k7ddrphy_dfi_p0_wrdata[18]}, k7ddrphy_bitslip18_r0[15:8]};
- if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip18_value1 <= (k7ddrphy_bitslip18_value1 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip18_value1 <= 3'd7;
- end
- k7ddrphy_bitslip18_r1 <= {k7ddrphy_bitslip181, k7ddrphy_bitslip18_r1[15:8]};
- if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip19_value0 <= (k7ddrphy_bitslip19_value0 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip19_value0 <= 3'd7;
- end
- k7ddrphy_bitslip19_r0 <= {{k7ddrphy_dfi_p3_wrdata[51], k7ddrphy_dfi_p3_wrdata[19], k7ddrphy_dfi_p2_wrdata[51], k7ddrphy_dfi_p2_wrdata[19], k7ddrphy_dfi_p1_wrdata[51], k7ddrphy_dfi_p1_wrdata[19], k7ddrphy_dfi_p0_wrdata[51], k7ddrphy_dfi_p0_wrdata[19]}, k7ddrphy_bitslip19_r0[15:8]};
- if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip19_value1 <= (k7ddrphy_bitslip19_value1 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip19_value1 <= 3'd7;
- end
- k7ddrphy_bitslip19_r1 <= {k7ddrphy_bitslip191, k7ddrphy_bitslip19_r1[15:8]};
- if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip20_value0 <= (k7ddrphy_bitslip20_value0 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip20_value0 <= 3'd7;
- end
- k7ddrphy_bitslip20_r0 <= {{k7ddrphy_dfi_p3_wrdata[52], k7ddrphy_dfi_p3_wrdata[20], k7ddrphy_dfi_p2_wrdata[52], k7ddrphy_dfi_p2_wrdata[20], k7ddrphy_dfi_p1_wrdata[52], k7ddrphy_dfi_p1_wrdata[20], k7ddrphy_dfi_p0_wrdata[52], k7ddrphy_dfi_p0_wrdata[20]}, k7ddrphy_bitslip20_r0[15:8]};
- if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip20_value1 <= (k7ddrphy_bitslip20_value1 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip20_value1 <= 3'd7;
- end
- k7ddrphy_bitslip20_r1 <= {k7ddrphy_bitslip201, k7ddrphy_bitslip20_r1[15:8]};
- if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip21_value0 <= (k7ddrphy_bitslip21_value0 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip21_value0 <= 3'd7;
- end
- k7ddrphy_bitslip21_r0 <= {{k7ddrphy_dfi_p3_wrdata[53], k7ddrphy_dfi_p3_wrdata[21], k7ddrphy_dfi_p2_wrdata[53], k7ddrphy_dfi_p2_wrdata[21], k7ddrphy_dfi_p1_wrdata[53], k7ddrphy_dfi_p1_wrdata[21], k7ddrphy_dfi_p0_wrdata[53], k7ddrphy_dfi_p0_wrdata[21]}, k7ddrphy_bitslip21_r0[15:8]};
- if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip21_value1 <= (k7ddrphy_bitslip21_value1 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip21_value1 <= 3'd7;
- end
- k7ddrphy_bitslip21_r1 <= {k7ddrphy_bitslip211, k7ddrphy_bitslip21_r1[15:8]};
- if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip22_value0 <= (k7ddrphy_bitslip22_value0 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip22_value0 <= 3'd7;
- end
- k7ddrphy_bitslip22_r0 <= {{k7ddrphy_dfi_p3_wrdata[54], k7ddrphy_dfi_p3_wrdata[22], k7ddrphy_dfi_p2_wrdata[54], k7ddrphy_dfi_p2_wrdata[22], k7ddrphy_dfi_p1_wrdata[54], k7ddrphy_dfi_p1_wrdata[22], k7ddrphy_dfi_p0_wrdata[54], k7ddrphy_dfi_p0_wrdata[22]}, k7ddrphy_bitslip22_r0[15:8]};
- if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip22_value1 <= (k7ddrphy_bitslip22_value1 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip22_value1 <= 3'd7;
- end
- k7ddrphy_bitslip22_r1 <= {k7ddrphy_bitslip221, k7ddrphy_bitslip22_r1[15:8]};
- if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip23_value0 <= (k7ddrphy_bitslip23_value0 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip23_value0 <= 3'd7;
- end
- k7ddrphy_bitslip23_r0 <= {{k7ddrphy_dfi_p3_wrdata[55], k7ddrphy_dfi_p3_wrdata[23], k7ddrphy_dfi_p2_wrdata[55], k7ddrphy_dfi_p2_wrdata[23], k7ddrphy_dfi_p1_wrdata[55], k7ddrphy_dfi_p1_wrdata[23], k7ddrphy_dfi_p0_wrdata[55], k7ddrphy_dfi_p0_wrdata[23]}, k7ddrphy_bitslip23_r0[15:8]};
- if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip23_value1 <= (k7ddrphy_bitslip23_value1 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip23_value1 <= 3'd7;
- end
- k7ddrphy_bitslip23_r1 <= {k7ddrphy_bitslip231, k7ddrphy_bitslip23_r1[15:8]};
- if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip24_value0 <= (k7ddrphy_bitslip24_value0 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip24_value0 <= 3'd7;
- end
- k7ddrphy_bitslip24_r0 <= {{k7ddrphy_dfi_p3_wrdata[56], k7ddrphy_dfi_p3_wrdata[24], k7ddrphy_dfi_p2_wrdata[56], k7ddrphy_dfi_p2_wrdata[24], k7ddrphy_dfi_p1_wrdata[56], k7ddrphy_dfi_p1_wrdata[24], k7ddrphy_dfi_p0_wrdata[56], k7ddrphy_dfi_p0_wrdata[24]}, k7ddrphy_bitslip24_r0[15:8]};
- if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip24_value1 <= (k7ddrphy_bitslip24_value1 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip24_value1 <= 3'd7;
- end
- k7ddrphy_bitslip24_r1 <= {k7ddrphy_bitslip241, k7ddrphy_bitslip24_r1[15:8]};
- if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip25_value0 <= (k7ddrphy_bitslip25_value0 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip25_value0 <= 3'd7;
- end
- k7ddrphy_bitslip25_r0 <= {{k7ddrphy_dfi_p3_wrdata[57], k7ddrphy_dfi_p3_wrdata[25], k7ddrphy_dfi_p2_wrdata[57], k7ddrphy_dfi_p2_wrdata[25], k7ddrphy_dfi_p1_wrdata[57], k7ddrphy_dfi_p1_wrdata[25], k7ddrphy_dfi_p0_wrdata[57], k7ddrphy_dfi_p0_wrdata[25]}, k7ddrphy_bitslip25_r0[15:8]};
- if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip25_value1 <= (k7ddrphy_bitslip25_value1 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip25_value1 <= 3'd7;
- end
- k7ddrphy_bitslip25_r1 <= {k7ddrphy_bitslip251, k7ddrphy_bitslip25_r1[15:8]};
- if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip26_value0 <= (k7ddrphy_bitslip26_value0 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip26_value0 <= 3'd7;
- end
- k7ddrphy_bitslip26_r0 <= {{k7ddrphy_dfi_p3_wrdata[58], k7ddrphy_dfi_p3_wrdata[26], k7ddrphy_dfi_p2_wrdata[58], k7ddrphy_dfi_p2_wrdata[26], k7ddrphy_dfi_p1_wrdata[58], k7ddrphy_dfi_p1_wrdata[26], k7ddrphy_dfi_p0_wrdata[58], k7ddrphy_dfi_p0_wrdata[26]}, k7ddrphy_bitslip26_r0[15:8]};
- if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip26_value1 <= (k7ddrphy_bitslip26_value1 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip26_value1 <= 3'd7;
- end
- k7ddrphy_bitslip26_r1 <= {k7ddrphy_bitslip261, k7ddrphy_bitslip26_r1[15:8]};
- if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip27_value0 <= (k7ddrphy_bitslip27_value0 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip27_value0 <= 3'd7;
- end
- k7ddrphy_bitslip27_r0 <= {{k7ddrphy_dfi_p3_wrdata[59], k7ddrphy_dfi_p3_wrdata[27], k7ddrphy_dfi_p2_wrdata[59], k7ddrphy_dfi_p2_wrdata[27], k7ddrphy_dfi_p1_wrdata[59], k7ddrphy_dfi_p1_wrdata[27], k7ddrphy_dfi_p0_wrdata[59], k7ddrphy_dfi_p0_wrdata[27]}, k7ddrphy_bitslip27_r0[15:8]};
- if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip27_value1 <= (k7ddrphy_bitslip27_value1 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip27_value1 <= 3'd7;
- end
- k7ddrphy_bitslip27_r1 <= {k7ddrphy_bitslip271, k7ddrphy_bitslip27_r1[15:8]};
- if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip28_value0 <= (k7ddrphy_bitslip28_value0 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip28_value0 <= 3'd7;
- end
- k7ddrphy_bitslip28_r0 <= {{k7ddrphy_dfi_p3_wrdata[60], k7ddrphy_dfi_p3_wrdata[28], k7ddrphy_dfi_p2_wrdata[60], k7ddrphy_dfi_p2_wrdata[28], k7ddrphy_dfi_p1_wrdata[60], k7ddrphy_dfi_p1_wrdata[28], k7ddrphy_dfi_p0_wrdata[60], k7ddrphy_dfi_p0_wrdata[28]}, k7ddrphy_bitslip28_r0[15:8]};
- if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip28_value1 <= (k7ddrphy_bitslip28_value1 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip28_value1 <= 3'd7;
- end
- k7ddrphy_bitslip28_r1 <= {k7ddrphy_bitslip281, k7ddrphy_bitslip28_r1[15:8]};
- if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip29_value0 <= (k7ddrphy_bitslip29_value0 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip29_value0 <= 3'd7;
- end
- k7ddrphy_bitslip29_r0 <= {{k7ddrphy_dfi_p3_wrdata[61], k7ddrphy_dfi_p3_wrdata[29], k7ddrphy_dfi_p2_wrdata[61], k7ddrphy_dfi_p2_wrdata[29], k7ddrphy_dfi_p1_wrdata[61], k7ddrphy_dfi_p1_wrdata[29], k7ddrphy_dfi_p0_wrdata[61], k7ddrphy_dfi_p0_wrdata[29]}, k7ddrphy_bitslip29_r0[15:8]};
- if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip29_value1 <= (k7ddrphy_bitslip29_value1 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip29_value1 <= 3'd7;
- end
- k7ddrphy_bitslip29_r1 <= {k7ddrphy_bitslip291, k7ddrphy_bitslip29_r1[15:8]};
- if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip30_value0 <= (k7ddrphy_bitslip30_value0 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip30_value0 <= 3'd7;
- end
- k7ddrphy_bitslip30_r0 <= {{k7ddrphy_dfi_p3_wrdata[62], k7ddrphy_dfi_p3_wrdata[30], k7ddrphy_dfi_p2_wrdata[62], k7ddrphy_dfi_p2_wrdata[30], k7ddrphy_dfi_p1_wrdata[62], k7ddrphy_dfi_p1_wrdata[30], k7ddrphy_dfi_p0_wrdata[62], k7ddrphy_dfi_p0_wrdata[30]}, k7ddrphy_bitslip30_r0[15:8]};
- if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip30_value1 <= (k7ddrphy_bitslip30_value1 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip30_value1 <= 3'd7;
- end
- k7ddrphy_bitslip30_r1 <= {k7ddrphy_bitslip301, k7ddrphy_bitslip30_r1[15:8]};
- if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip31_value0 <= (k7ddrphy_bitslip31_value0 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip31_value0 <= 3'd7;
- end
- k7ddrphy_bitslip31_r0 <= {{k7ddrphy_dfi_p3_wrdata[63], k7ddrphy_dfi_p3_wrdata[31], k7ddrphy_dfi_p2_wrdata[63], k7ddrphy_dfi_p2_wrdata[31], k7ddrphy_dfi_p1_wrdata[63], k7ddrphy_dfi_p1_wrdata[31], k7ddrphy_dfi_p0_wrdata[63], k7ddrphy_dfi_p0_wrdata[31]}, k7ddrphy_bitslip31_r0[15:8]};
- if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin
- k7ddrphy_bitslip31_value1 <= (k7ddrphy_bitslip31_value1 + 1'd1);
- end
- if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
- k7ddrphy_bitslip31_value1 <= 3'd7;
- end
- k7ddrphy_bitslip31_r1 <= {k7ddrphy_bitslip311, k7ddrphy_bitslip31_r1[15:8]};
- k7ddrphy_rddata_en_tappeddelayline0 <= (((k7ddrphy_dfi_p0_rddata_en | k7ddrphy_dfi_p1_rddata_en) | k7ddrphy_dfi_p2_rddata_en) | k7ddrphy_dfi_p3_rddata_en);
- k7ddrphy_rddata_en_tappeddelayline1 <= k7ddrphy_rddata_en_tappeddelayline0;
- k7ddrphy_rddata_en_tappeddelayline2 <= k7ddrphy_rddata_en_tappeddelayline1;
- k7ddrphy_rddata_en_tappeddelayline3 <= k7ddrphy_rddata_en_tappeddelayline2;
- k7ddrphy_rddata_en_tappeddelayline4 <= k7ddrphy_rddata_en_tappeddelayline3;
- k7ddrphy_rddata_en_tappeddelayline5 <= k7ddrphy_rddata_en_tappeddelayline4;
- k7ddrphy_rddata_en_tappeddelayline6 <= k7ddrphy_rddata_en_tappeddelayline5;
- k7ddrphy_rddata_en_tappeddelayline7 <= k7ddrphy_rddata_en_tappeddelayline6;
- k7ddrphy_wrdata_en_tappeddelayline0 <= (((k7ddrphy_dfi_p0_wrdata_en | k7ddrphy_dfi_p1_wrdata_en) | k7ddrphy_dfi_p2_wrdata_en) | k7ddrphy_dfi_p3_wrdata_en);
- k7ddrphy_wrdata_en_tappeddelayline1 <= k7ddrphy_wrdata_en_tappeddelayline0;
- k7ddrphy_wrdata_en_tappeddelayline2 <= k7ddrphy_wrdata_en_tappeddelayline1;
- if (litedramcore_csr_dfi_p0_rddata_valid) begin
- litedramcore_phaseinjector0_rddata_status <= litedramcore_csr_dfi_p0_rddata;
- end
- if (litedramcore_csr_dfi_p1_rddata_valid) begin
- litedramcore_phaseinjector1_rddata_status <= litedramcore_csr_dfi_p1_rddata;
- end
- if (litedramcore_csr_dfi_p2_rddata_valid) begin
- litedramcore_phaseinjector2_rddata_status <= litedramcore_csr_dfi_p2_rddata;
- end
- if (litedramcore_csr_dfi_p3_rddata_valid) begin
- litedramcore_phaseinjector3_rddata_status <= litedramcore_csr_dfi_p3_rddata;
- end
- if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin
- litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1);
- end else begin
- litedramcore_timer_count1 <= 10'd781;
- end
- litedramcore_postponer_req_o <= 1'd0;
- if (litedramcore_postponer_req_i) begin
- litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1);
- if ((litedramcore_postponer_count == 1'd0)) begin
- litedramcore_postponer_count <= 1'd0;
- litedramcore_postponer_req_o <= 1'd1;
- end
- end
- if (litedramcore_sequencer_start0) begin
- litedramcore_sequencer_count <= 1'd0;
- end else begin
- if (litedramcore_sequencer_done1) begin
- if ((litedramcore_sequencer_count != 1'd0)) begin
- litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1);
- end
- end
- end
- litedramcore_cmd_payload_a <= 1'd0;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd0;
- litedramcore_cmd_payload_we <= 1'd0;
- litedramcore_sequencer_done1 <= 1'd0;
- if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin
- litedramcore_cmd_payload_a <= 11'd1024;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd1;
- litedramcore_cmd_payload_we <= 1'd1;
- end
- if ((litedramcore_sequencer_counter == 2'd3)) begin
- litedramcore_cmd_payload_a <= 11'd1024;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd1;
- litedramcore_cmd_payload_ras <= 1'd1;
- litedramcore_cmd_payload_we <= 1'd0;
- end
- if ((litedramcore_sequencer_counter == 6'd55)) begin
- litedramcore_cmd_payload_a <= 1'd0;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd0;
- litedramcore_cmd_payload_we <= 1'd0;
- litedramcore_sequencer_done1 <= 1'd1;
- end
- if ((litedramcore_sequencer_counter == 6'd55)) begin
- litedramcore_sequencer_counter <= 1'd0;
- end else begin
- if ((litedramcore_sequencer_counter != 1'd0)) begin
- litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1);
- end else begin
- if (litedramcore_sequencer_start1) begin
- litedramcore_sequencer_counter <= 1'd1;
- end
- end
- end
- if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin
- litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1);
- end else begin
- litedramcore_zqcs_timer_count1 <= 27'd99999999;
- end
- litedramcore_zqcs_executer_done <= 1'd0;
- if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin
- litedramcore_cmd_payload_a <= 11'd1024;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd1;
- litedramcore_cmd_payload_we <= 1'd1;
- end
- if ((litedramcore_zqcs_executer_counter == 2'd3)) begin
- litedramcore_cmd_payload_a <= 1'd0;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd0;
- litedramcore_cmd_payload_we <= 1'd1;
- end
- if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
- litedramcore_cmd_payload_a <= 1'd0;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd0;
- litedramcore_cmd_payload_we <= 1'd0;
- litedramcore_zqcs_executer_done <= 1'd1;
- end
- if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
- litedramcore_zqcs_executer_counter <= 1'd0;
- end else begin
- if ((litedramcore_zqcs_executer_counter != 1'd0)) begin
- litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1);
- end else begin
- if (litedramcore_zqcs_executer_start) begin
- litedramcore_zqcs_executer_counter <= 1'd1;
- end
- end
- end
- litedramcore_refresher_state <= litedramcore_refresher_next_state;
- if (litedramcore_bankmachine0_row_close) begin
- litedramcore_bankmachine0_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine0_row_open) begin
- litedramcore_bankmachine0_row_opened <= 1'd1;
- litedramcore_bankmachine0_row <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7];
- end
- end
- if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine0_cmd_buffer_source_valid <= litedramcore_bankmachine0_cmd_buffer_sink_valid;
- litedramcore_bankmachine0_cmd_buffer_source_first <= litedramcore_bankmachine0_cmd_buffer_sink_first;
- litedramcore_bankmachine0_cmd_buffer_source_last <= litedramcore_bankmachine0_cmd_buffer_sink_last;
- litedramcore_bankmachine0_cmd_buffer_source_payload_we <= litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine0_twtpcon_valid) begin
- litedramcore_bankmachine0_twtpcon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine0_twtpcon_ready)) begin
- litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine0_trccon_valid) begin
- litedramcore_bankmachine0_trccon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine0_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine0_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine0_trccon_ready)) begin
- litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1);
- if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin
- litedramcore_bankmachine0_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine0_trascon_valid) begin
- litedramcore_bankmachine0_trascon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_bankmachine0_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine0_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1);
- if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin
- litedramcore_bankmachine0_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state;
- if (litedramcore_bankmachine1_row_close) begin
- litedramcore_bankmachine1_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine1_row_open) begin
- litedramcore_bankmachine1_row_opened <= 1'd1;
- litedramcore_bankmachine1_row <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7];
- end
- end
- if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine1_cmd_buffer_source_valid <= litedramcore_bankmachine1_cmd_buffer_sink_valid;
- litedramcore_bankmachine1_cmd_buffer_source_first <= litedramcore_bankmachine1_cmd_buffer_sink_first;
- litedramcore_bankmachine1_cmd_buffer_source_last <= litedramcore_bankmachine1_cmd_buffer_sink_last;
- litedramcore_bankmachine1_cmd_buffer_source_payload_we <= litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine1_twtpcon_valid) begin
- litedramcore_bankmachine1_twtpcon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine1_twtpcon_ready)) begin
- litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine1_trccon_valid) begin
- litedramcore_bankmachine1_trccon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine1_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine1_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine1_trccon_ready)) begin
- litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1);
- if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin
- litedramcore_bankmachine1_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine1_trascon_valid) begin
- litedramcore_bankmachine1_trascon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_bankmachine1_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine1_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1);
- if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin
- litedramcore_bankmachine1_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state;
- if (litedramcore_bankmachine2_row_close) begin
- litedramcore_bankmachine2_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine2_row_open) begin
- litedramcore_bankmachine2_row_opened <= 1'd1;
- litedramcore_bankmachine2_row <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7];
- end
- end
- if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine2_cmd_buffer_source_valid <= litedramcore_bankmachine2_cmd_buffer_sink_valid;
- litedramcore_bankmachine2_cmd_buffer_source_first <= litedramcore_bankmachine2_cmd_buffer_sink_first;
- litedramcore_bankmachine2_cmd_buffer_source_last <= litedramcore_bankmachine2_cmd_buffer_sink_last;
- litedramcore_bankmachine2_cmd_buffer_source_payload_we <= litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine2_twtpcon_valid) begin
- litedramcore_bankmachine2_twtpcon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine2_twtpcon_ready)) begin
- litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine2_trccon_valid) begin
- litedramcore_bankmachine2_trccon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine2_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine2_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine2_trccon_ready)) begin
- litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1);
- if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin
- litedramcore_bankmachine2_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine2_trascon_valid) begin
- litedramcore_bankmachine2_trascon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_bankmachine2_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine2_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1);
- if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin
- litedramcore_bankmachine2_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state;
- if (litedramcore_bankmachine3_row_close) begin
- litedramcore_bankmachine3_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine3_row_open) begin
- litedramcore_bankmachine3_row_opened <= 1'd1;
- litedramcore_bankmachine3_row <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7];
- end
- end
- if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine3_cmd_buffer_source_valid <= litedramcore_bankmachine3_cmd_buffer_sink_valid;
- litedramcore_bankmachine3_cmd_buffer_source_first <= litedramcore_bankmachine3_cmd_buffer_sink_first;
- litedramcore_bankmachine3_cmd_buffer_source_last <= litedramcore_bankmachine3_cmd_buffer_sink_last;
- litedramcore_bankmachine3_cmd_buffer_source_payload_we <= litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine3_twtpcon_valid) begin
- litedramcore_bankmachine3_twtpcon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine3_twtpcon_ready)) begin
- litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine3_trccon_valid) begin
- litedramcore_bankmachine3_trccon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine3_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine3_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine3_trccon_ready)) begin
- litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1);
- if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin
- litedramcore_bankmachine3_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine3_trascon_valid) begin
- litedramcore_bankmachine3_trascon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_bankmachine3_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine3_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1);
- if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin
- litedramcore_bankmachine3_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state;
- if (litedramcore_bankmachine4_row_close) begin
- litedramcore_bankmachine4_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine4_row_open) begin
- litedramcore_bankmachine4_row_opened <= 1'd1;
- litedramcore_bankmachine4_row <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7];
- end
- end
- if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine4_cmd_buffer_source_valid <= litedramcore_bankmachine4_cmd_buffer_sink_valid;
- litedramcore_bankmachine4_cmd_buffer_source_first <= litedramcore_bankmachine4_cmd_buffer_sink_first;
- litedramcore_bankmachine4_cmd_buffer_source_last <= litedramcore_bankmachine4_cmd_buffer_sink_last;
- litedramcore_bankmachine4_cmd_buffer_source_payload_we <= litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine4_twtpcon_valid) begin
- litedramcore_bankmachine4_twtpcon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine4_twtpcon_ready)) begin
- litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine4_trccon_valid) begin
- litedramcore_bankmachine4_trccon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine4_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine4_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine4_trccon_ready)) begin
- litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1);
- if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin
- litedramcore_bankmachine4_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine4_trascon_valid) begin
- litedramcore_bankmachine4_trascon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_bankmachine4_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine4_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1);
- if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin
- litedramcore_bankmachine4_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state;
- if (litedramcore_bankmachine5_row_close) begin
- litedramcore_bankmachine5_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine5_row_open) begin
- litedramcore_bankmachine5_row_opened <= 1'd1;
- litedramcore_bankmachine5_row <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7];
- end
- end
- if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine5_cmd_buffer_source_valid <= litedramcore_bankmachine5_cmd_buffer_sink_valid;
- litedramcore_bankmachine5_cmd_buffer_source_first <= litedramcore_bankmachine5_cmd_buffer_sink_first;
- litedramcore_bankmachine5_cmd_buffer_source_last <= litedramcore_bankmachine5_cmd_buffer_sink_last;
- litedramcore_bankmachine5_cmd_buffer_source_payload_we <= litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine5_twtpcon_valid) begin
- litedramcore_bankmachine5_twtpcon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine5_twtpcon_ready)) begin
- litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine5_trccon_valid) begin
- litedramcore_bankmachine5_trccon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine5_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine5_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine5_trccon_ready)) begin
- litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1);
- if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin
- litedramcore_bankmachine5_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine5_trascon_valid) begin
- litedramcore_bankmachine5_trascon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_bankmachine5_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine5_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1);
- if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin
- litedramcore_bankmachine5_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state;
- if (litedramcore_bankmachine6_row_close) begin
- litedramcore_bankmachine6_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine6_row_open) begin
- litedramcore_bankmachine6_row_opened <= 1'd1;
- litedramcore_bankmachine6_row <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7];
- end
- end
- if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine6_cmd_buffer_source_valid <= litedramcore_bankmachine6_cmd_buffer_sink_valid;
- litedramcore_bankmachine6_cmd_buffer_source_first <= litedramcore_bankmachine6_cmd_buffer_sink_first;
- litedramcore_bankmachine6_cmd_buffer_source_last <= litedramcore_bankmachine6_cmd_buffer_sink_last;
- litedramcore_bankmachine6_cmd_buffer_source_payload_we <= litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine6_twtpcon_valid) begin
- litedramcore_bankmachine6_twtpcon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine6_twtpcon_ready)) begin
- litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine6_trccon_valid) begin
- litedramcore_bankmachine6_trccon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine6_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine6_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine6_trccon_ready)) begin
- litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1);
- if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin
- litedramcore_bankmachine6_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine6_trascon_valid) begin
- litedramcore_bankmachine6_trascon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_bankmachine6_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine6_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1);
- if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin
- litedramcore_bankmachine6_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state;
- if (litedramcore_bankmachine7_row_close) begin
- litedramcore_bankmachine7_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine7_row_open) begin
- litedramcore_bankmachine7_row_opened <= 1'd1;
- litedramcore_bankmachine7_row <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7];
- end
- end
- if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine7_cmd_buffer_source_valid <= litedramcore_bankmachine7_cmd_buffer_sink_valid;
- litedramcore_bankmachine7_cmd_buffer_source_first <= litedramcore_bankmachine7_cmd_buffer_sink_first;
- litedramcore_bankmachine7_cmd_buffer_source_last <= litedramcore_bankmachine7_cmd_buffer_sink_last;
- litedramcore_bankmachine7_cmd_buffer_source_payload_we <= litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine7_twtpcon_valid) begin
- litedramcore_bankmachine7_twtpcon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine7_twtpcon_ready)) begin
- litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine7_trccon_valid) begin
- litedramcore_bankmachine7_trccon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine7_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine7_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine7_trccon_ready)) begin
- litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1);
- if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin
- litedramcore_bankmachine7_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine7_trascon_valid) begin
- litedramcore_bankmachine7_trascon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_bankmachine7_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine7_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1);
- if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin
- litedramcore_bankmachine7_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state;
- if ((~litedramcore_en0)) begin
- litedramcore_time0 <= 5'd31;
- end else begin
- if ((~litedramcore_max_time0)) begin
- litedramcore_time0 <= (litedramcore_time0 - 1'd1);
- end
- end
- if ((~litedramcore_en1)) begin
- litedramcore_time1 <= 4'd15;
- end else begin
- if ((~litedramcore_max_time1)) begin
- litedramcore_time1 <= (litedramcore_time1 - 1'd1);
- end
- end
- if (litedramcore_choose_cmd_ce) begin
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
- end
- end
- end
- end
- end
- end
- end
- end
- 1'd1: begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
- end
- end
- end
- end
- end
- end
- end
- end
- 2'd2: begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
- end
- end
- end
- end
- end
- end
- end
- end
- 2'd3: begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd4: begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd5: begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd6: begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd7: begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
- end
- end
- end
- end
- end
- end
- end
- end
- endcase
- end
- if (litedramcore_choose_req_ce) begin
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
- end
- end
- end
- end
- end
- end
- end
- end
- 1'd1: begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
- end
- end
- end
- end
- end
- end
- end
- end
- 2'd2: begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
- end
- end
- end
- end
- end
- end
- end
- end
- 2'd3: begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd4: begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd5: begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd6: begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd7: begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
- end
- end
- end
- end
- end
- end
- end
- end
- endcase
- end
- litedramcore_dfi_p0_cs_n <= 1'd0;
- litedramcore_dfi_p0_bank <= array_muxed0;
- litedramcore_dfi_p0_address <= array_muxed1;
- litedramcore_dfi_p0_cas_n <= (~array_muxed2);
- litedramcore_dfi_p0_ras_n <= (~array_muxed3);
- litedramcore_dfi_p0_we_n <= (~array_muxed4);
- litedramcore_dfi_p0_rddata_en <= array_muxed5;
- litedramcore_dfi_p0_wrdata_en <= array_muxed6;
- litedramcore_dfi_p1_cs_n <= 1'd0;
- litedramcore_dfi_p1_bank <= array_muxed7;
- litedramcore_dfi_p1_address <= array_muxed8;
- litedramcore_dfi_p1_cas_n <= (~array_muxed9);
- litedramcore_dfi_p1_ras_n <= (~array_muxed10);
- litedramcore_dfi_p1_we_n <= (~array_muxed11);
- litedramcore_dfi_p1_rddata_en <= array_muxed12;
- litedramcore_dfi_p1_wrdata_en <= array_muxed13;
- litedramcore_dfi_p2_cs_n <= 1'd0;
- litedramcore_dfi_p2_bank <= array_muxed14;
- litedramcore_dfi_p2_address <= array_muxed15;
- litedramcore_dfi_p2_cas_n <= (~array_muxed16);
- litedramcore_dfi_p2_ras_n <= (~array_muxed17);
- litedramcore_dfi_p2_we_n <= (~array_muxed18);
- litedramcore_dfi_p2_rddata_en <= array_muxed19;
- litedramcore_dfi_p2_wrdata_en <= array_muxed20;
- litedramcore_dfi_p3_cs_n <= 1'd0;
- litedramcore_dfi_p3_bank <= array_muxed21;
- litedramcore_dfi_p3_address <= array_muxed22;
- litedramcore_dfi_p3_cas_n <= (~array_muxed23);
- litedramcore_dfi_p3_ras_n <= (~array_muxed24);
- litedramcore_dfi_p3_we_n <= (~array_muxed25);
- litedramcore_dfi_p3_rddata_en <= array_muxed26;
- litedramcore_dfi_p3_wrdata_en <= array_muxed27;
- if (litedramcore_trrdcon_valid) begin
- litedramcore_trrdcon_count <= 1'd1;
- if (1'd0) begin
- litedramcore_trrdcon_ready <= 1'd1;
- end else begin
- litedramcore_trrdcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_trrdcon_ready)) begin
- litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1);
- if ((litedramcore_trrdcon_count == 1'd1)) begin
- litedramcore_trrdcon_ready <= 1'd1;
- end
- end
- end
- litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid};
- if ((litedramcore_tfawcon_count < 3'd4)) begin
- if ((litedramcore_tfawcon_count == 2'd3)) begin
- litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid);
- end else begin
- litedramcore_tfawcon_ready <= 1'd1;
- end
- end
- if (litedramcore_tccdcon_valid) begin
- litedramcore_tccdcon_count <= 1'd0;
- if (1'd1) begin
- litedramcore_tccdcon_ready <= 1'd1;
- end else begin
- litedramcore_tccdcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_tccdcon_ready)) begin
- litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1);
- if ((litedramcore_tccdcon_count == 1'd1)) begin
- litedramcore_tccdcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_twtrcon_valid) begin
- litedramcore_twtrcon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_twtrcon_ready <= 1'd1;
- end else begin
- litedramcore_twtrcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_twtrcon_ready)) begin
- litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1);
- if ((litedramcore_twtrcon_count == 1'd1)) begin
- litedramcore_twtrcon_ready <= 1'd1;
- end
- end
- end
- litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state;
- litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready));
- litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0;
- litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid));
- litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0;
- litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1;
- litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2;
- litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3;
- litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4;
- litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5;
- litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6;
- litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7;
- litedramcore_state <= litedramcore_next_state;
- if (litedramcore_dat_w_next_value_ce0) begin
- litedramcore_dat_w <= litedramcore_dat_w_next_value0;
- end
- if (litedramcore_adr_next_value_ce1) begin
- litedramcore_adr <= litedramcore_adr_next_value1;
- end
- if (litedramcore_we_next_value_ce2) begin
- litedramcore_we <= litedramcore_we_next_value2;
- end
- interface0_bank_bus_dat_r <= 1'd0;
- if (csrbank0_sel) begin
- case (interface0_bank_bus_adr[8:0])
- 1'd0: begin
- interface0_bank_bus_dat_r <= csrbank0_init_done0_w;
- end
- 1'd1: begin
- interface0_bank_bus_dat_r <= csrbank0_init_error0_w;
- end
- endcase
- end
- if (csrbank0_init_done0_re) begin
- init_done_storage <= csrbank0_init_done0_r;
- end
- init_done_re <= csrbank0_init_done0_re;
- if (csrbank0_init_error0_re) begin
- init_error_storage <= csrbank0_init_error0_r;
- end
- init_error_re <= csrbank0_init_error0_re;
- interface1_bank_bus_dat_r <= 1'd0;
- if (csrbank1_sel) begin
- case (interface1_bank_bus_adr[8:0])
- 1'd0: begin
- interface1_bank_bus_dat_r <= csrbank1_rst0_w;
- end
- 1'd1: begin
- interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w;
- end
- 2'd2: begin
- interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w;
- end
- 2'd3: begin
- interface1_bank_bus_dat_r <= csrbank1_wlevel_en0_w;
- end
- 3'd4: begin
- interface1_bank_bus_dat_r <= k7ddrphy_wlevel_strobe_w;
- end
- 3'd5: begin
- interface1_bank_bus_dat_r <= k7ddrphy_cdly_rst_w;
- end
- 3'd6: begin
- interface1_bank_bus_dat_r <= k7ddrphy_cdly_inc_w;
- end
- 3'd7: begin
- interface1_bank_bus_dat_r <= k7ddrphy_rdly_dq_rst_w;
- end
- 4'd8: begin
- interface1_bank_bus_dat_r <= k7ddrphy_rdly_dq_inc_w;
- end
- 4'd9: begin
- interface1_bank_bus_dat_r <= k7ddrphy_rdly_dq_bitslip_rst_w;
- end
- 4'd10: begin
- interface1_bank_bus_dat_r <= k7ddrphy_rdly_dq_bitslip_w;
- end
- 4'd11: begin
- interface1_bank_bus_dat_r <= k7ddrphy_wdly_dq_rst_w;
- end
- 4'd12: begin
- interface1_bank_bus_dat_r <= k7ddrphy_wdly_dq_inc_w;
- end
- 4'd13: begin
- interface1_bank_bus_dat_r <= k7ddrphy_wdly_dqs_rst_w;
- end
- 4'd14: begin
- interface1_bank_bus_dat_r <= k7ddrphy_wdly_dqs_inc_w;
- end
- 4'd15: begin
- interface1_bank_bus_dat_r <= k7ddrphy_wdly_dq_bitslip_rst_w;
- end
- 5'd16: begin
- interface1_bank_bus_dat_r <= k7ddrphy_wdly_dq_bitslip_w;
- end
- 5'd17: begin
- interface1_bank_bus_dat_r <= csrbank1_rdphase0_w;
- end
- 5'd18: begin
- interface1_bank_bus_dat_r <= csrbank1_wrphase0_w;
- end
- endcase
- end
- if (csrbank1_rst0_re) begin
- k7ddrphy_rst_storage <= csrbank1_rst0_r;
- end
- k7ddrphy_rst_re <= csrbank1_rst0_re;
- if (csrbank1_dly_sel0_re) begin
- k7ddrphy_dly_sel_storage[3:0] <= csrbank1_dly_sel0_r;
- end
- k7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re;
- if (csrbank1_half_sys8x_taps0_re) begin
- k7ddrphy_half_sys8x_taps_storage[4:0] <= csrbank1_half_sys8x_taps0_r;
- end
- k7ddrphy_half_sys8x_taps_re <= csrbank1_half_sys8x_taps0_re;
- if (csrbank1_wlevel_en0_re) begin
- k7ddrphy_wlevel_en_storage <= csrbank1_wlevel_en0_r;
- end
- k7ddrphy_wlevel_en_re <= csrbank1_wlevel_en0_re;
- if (csrbank1_rdphase0_re) begin
- k7ddrphy_rdphase_storage[1:0] <= csrbank1_rdphase0_r;
- end
- k7ddrphy_rdphase_re <= csrbank1_rdphase0_re;
- if (csrbank1_wrphase0_re) begin
- k7ddrphy_wrphase_storage[1:0] <= csrbank1_wrphase0_r;
- end
- k7ddrphy_wrphase_re <= csrbank1_wrphase0_re;
- interface2_bank_bus_dat_r <= 1'd0;
- if (csrbank2_sel) begin
- case (interface2_bank_bus_adr[8:0])
- 1'd0: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w;
- end
- 1'd1: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w;
- end
- 2'd2: begin
- interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w;
- end
- 2'd3: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w;
- end
- 3'd4: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w;
- end
- 3'd5: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata1_w;
- end
- 3'd6: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w;
- end
- 3'd7: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata1_w;
- end
- 4'd8: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata0_w;
- end
- 4'd9: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w;
- end
- 4'd10: begin
- interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w;
- end
- 4'd11: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w;
- end
- 4'd12: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w;
- end
- 4'd13: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata1_w;
- end
- 4'd14: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w;
- end
- 4'd15: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata1_w;
- end
- 5'd16: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata0_w;
- end
- 5'd17: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w;
- end
- 5'd18: begin
- interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w;
- end
- 5'd19: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w;
- end
- 5'd20: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w;
- end
- 5'd21: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata1_w;
- end
- 5'd22: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w;
- end
- 5'd23: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata1_w;
- end
- 5'd24: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata0_w;
- end
- 5'd25: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w;
- end
- 5'd26: begin
- interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w;
- end
- 5'd27: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w;
- end
- 5'd28: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w;
- end
- 5'd29: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata1_w;
- end
- 5'd30: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w;
- end
- 5'd31: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata1_w;
- end
- 6'd32: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata0_w;
- end
- endcase
- end
- if (csrbank2_dfii_control0_re) begin
- litedramcore_storage[3:0] <= csrbank2_dfii_control0_r;
- end
- litedramcore_re <= csrbank2_dfii_control0_re;
- if (csrbank2_dfii_pi0_command0_re) begin
- litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r;
- end
- litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re;
- if (csrbank2_dfii_pi0_address0_re) begin
- litedramcore_phaseinjector0_address_storage[14:0] <= csrbank2_dfii_pi0_address0_r;
- end
- litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re;
- if (csrbank2_dfii_pi0_baddress0_re) begin
- litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r;
- end
- litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re;
- if (csrbank2_dfii_pi0_wrdata1_re) begin
- litedramcore_phaseinjector0_wrdata_storage[63:32] <= csrbank2_dfii_pi0_wrdata1_r;
- end
- if (csrbank2_dfii_pi0_wrdata0_re) begin
- litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r;
- end
- litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re;
- litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata0_re;
- if (csrbank2_dfii_pi1_command0_re) begin
- litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r;
- end
- litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re;
- if (csrbank2_dfii_pi1_address0_re) begin
- litedramcore_phaseinjector1_address_storage[14:0] <= csrbank2_dfii_pi1_address0_r;
- end
- litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re;
- if (csrbank2_dfii_pi1_baddress0_re) begin
- litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r;
- end
- litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re;
- if (csrbank2_dfii_pi1_wrdata1_re) begin
- litedramcore_phaseinjector1_wrdata_storage[63:32] <= csrbank2_dfii_pi1_wrdata1_r;
- end
- if (csrbank2_dfii_pi1_wrdata0_re) begin
- litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r;
- end
- litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re;
- litedramcore_phaseinjector1_rddata_re <= csrbank2_dfii_pi1_rddata0_re;
- if (csrbank2_dfii_pi2_command0_re) begin
- litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r;
- end
- litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re;
- if (csrbank2_dfii_pi2_address0_re) begin
- litedramcore_phaseinjector2_address_storage[14:0] <= csrbank2_dfii_pi2_address0_r;
- end
- litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re;
- if (csrbank2_dfii_pi2_baddress0_re) begin
- litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r;
- end
- litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re;
- if (csrbank2_dfii_pi2_wrdata1_re) begin
- litedramcore_phaseinjector2_wrdata_storage[63:32] <= csrbank2_dfii_pi2_wrdata1_r;
- end
- if (csrbank2_dfii_pi2_wrdata0_re) begin
- litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r;
- end
- litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re;
- litedramcore_phaseinjector2_rddata_re <= csrbank2_dfii_pi2_rddata0_re;
- if (csrbank2_dfii_pi3_command0_re) begin
- litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r;
- end
- litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re;
- if (csrbank2_dfii_pi3_address0_re) begin
- litedramcore_phaseinjector3_address_storage[14:0] <= csrbank2_dfii_pi3_address0_r;
- end
- litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re;
- if (csrbank2_dfii_pi3_baddress0_re) begin
- litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r;
- end
- litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re;
- if (csrbank2_dfii_pi3_wrdata1_re) begin
- litedramcore_phaseinjector3_wrdata_storage[63:32] <= csrbank2_dfii_pi3_wrdata1_r;
- end
- if (csrbank2_dfii_pi3_wrdata0_re) begin
- litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r;
- end
- litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re;
- litedramcore_phaseinjector3_rddata_re <= csrbank2_dfii_pi3_rddata0_re;
- if (sys_rst) begin
- k7ddrphy_rst_storage <= 1'd0;
- k7ddrphy_rst_re <= 1'd0;
- k7ddrphy_dly_sel_storage <= 4'd0;
- k7ddrphy_dly_sel_re <= 1'd0;
- k7ddrphy_half_sys8x_taps_storage <= 5'd8;
- k7ddrphy_half_sys8x_taps_re <= 1'd0;
- k7ddrphy_wlevel_en_storage <= 1'd0;
- k7ddrphy_wlevel_en_re <= 1'd0;
- k7ddrphy_rdphase_storage <= 2'd1;
- k7ddrphy_rdphase_re <= 1'd0;
- k7ddrphy_wrphase_storage <= 2'd2;
- k7ddrphy_wrphase_re <= 1'd0;
- k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
- k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
- k7ddrphy_bitslip0_value0 <= 3'd7;
- k7ddrphy_bitslip1_value0 <= 3'd7;
- k7ddrphy_bitslip2_value0 <= 3'd7;
- k7ddrphy_bitslip3_value0 <= 3'd7;
- k7ddrphy_bitslip0_value1 <= 3'd7;
- k7ddrphy_bitslip1_value1 <= 3'd7;
- k7ddrphy_bitslip2_value1 <= 3'd7;
- k7ddrphy_bitslip3_value1 <= 3'd7;
- k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
- k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
- k7ddrphy_bitslip0_value2 <= 3'd7;
- k7ddrphy_bitslip0_value3 <= 3'd7;
- k7ddrphy_bitslip1_value2 <= 3'd7;
- k7ddrphy_bitslip1_value3 <= 3'd7;
- k7ddrphy_bitslip2_value2 <= 3'd7;
- k7ddrphy_bitslip2_value3 <= 3'd7;
- k7ddrphy_bitslip3_value2 <= 3'd7;
- k7ddrphy_bitslip3_value3 <= 3'd7;
- k7ddrphy_bitslip4_value0 <= 3'd7;
- k7ddrphy_bitslip4_value1 <= 3'd7;
- k7ddrphy_bitslip5_value0 <= 3'd7;
- k7ddrphy_bitslip5_value1 <= 3'd7;
- k7ddrphy_bitslip6_value0 <= 3'd7;
- k7ddrphy_bitslip6_value1 <= 3'd7;
- k7ddrphy_bitslip7_value0 <= 3'd7;
- k7ddrphy_bitslip7_value1 <= 3'd7;
- k7ddrphy_bitslip8_value0 <= 3'd7;
- k7ddrphy_bitslip8_value1 <= 3'd7;
- k7ddrphy_bitslip9_value0 <= 3'd7;
- k7ddrphy_bitslip9_value1 <= 3'd7;
- k7ddrphy_bitslip10_value0 <= 3'd7;
- k7ddrphy_bitslip10_value1 <= 3'd7;
- k7ddrphy_bitslip11_value0 <= 3'd7;
- k7ddrphy_bitslip11_value1 <= 3'd7;
- k7ddrphy_bitslip12_value0 <= 3'd7;
- k7ddrphy_bitslip12_value1 <= 3'd7;
- k7ddrphy_bitslip13_value0 <= 3'd7;
- k7ddrphy_bitslip13_value1 <= 3'd7;
- k7ddrphy_bitslip14_value0 <= 3'd7;
- k7ddrphy_bitslip14_value1 <= 3'd7;
- k7ddrphy_bitslip15_value0 <= 3'd7;
- k7ddrphy_bitslip15_value1 <= 3'd7;
- k7ddrphy_bitslip16_value0 <= 3'd7;
- k7ddrphy_bitslip16_value1 <= 3'd7;
- k7ddrphy_bitslip17_value0 <= 3'd7;
- k7ddrphy_bitslip17_value1 <= 3'd7;
- k7ddrphy_bitslip18_value0 <= 3'd7;
- k7ddrphy_bitslip18_value1 <= 3'd7;
- k7ddrphy_bitslip19_value0 <= 3'd7;
- k7ddrphy_bitslip19_value1 <= 3'd7;
- k7ddrphy_bitslip20_value0 <= 3'd7;
- k7ddrphy_bitslip20_value1 <= 3'd7;
- k7ddrphy_bitslip21_value0 <= 3'd7;
- k7ddrphy_bitslip21_value1 <= 3'd7;
- k7ddrphy_bitslip22_value0 <= 3'd7;
- k7ddrphy_bitslip22_value1 <= 3'd7;
- k7ddrphy_bitslip23_value0 <= 3'd7;
- k7ddrphy_bitslip23_value1 <= 3'd7;
- k7ddrphy_bitslip24_value0 <= 3'd7;
- k7ddrphy_bitslip24_value1 <= 3'd7;
- k7ddrphy_bitslip25_value0 <= 3'd7;
- k7ddrphy_bitslip25_value1 <= 3'd7;
- k7ddrphy_bitslip26_value0 <= 3'd7;
- k7ddrphy_bitslip26_value1 <= 3'd7;
- k7ddrphy_bitslip27_value0 <= 3'd7;
- k7ddrphy_bitslip27_value1 <= 3'd7;
- k7ddrphy_bitslip28_value0 <= 3'd7;
- k7ddrphy_bitslip28_value1 <= 3'd7;
- k7ddrphy_bitslip29_value0 <= 3'd7;
- k7ddrphy_bitslip29_value1 <= 3'd7;
- k7ddrphy_bitslip30_value0 <= 3'd7;
- k7ddrphy_bitslip30_value1 <= 3'd7;
- k7ddrphy_bitslip31_value0 <= 3'd7;
- k7ddrphy_bitslip31_value1 <= 3'd7;
- k7ddrphy_rddata_en_tappeddelayline0 <= 1'd0;
- k7ddrphy_rddata_en_tappeddelayline1 <= 1'd0;
- k7ddrphy_rddata_en_tappeddelayline2 <= 1'd0;
- k7ddrphy_rddata_en_tappeddelayline3 <= 1'd0;
- k7ddrphy_rddata_en_tappeddelayline4 <= 1'd0;
- k7ddrphy_rddata_en_tappeddelayline5 <= 1'd0;
- k7ddrphy_rddata_en_tappeddelayline6 <= 1'd0;
- k7ddrphy_rddata_en_tappeddelayline7 <= 1'd0;
- k7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0;
- k7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0;
- k7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0;
- litedramcore_storage <= 4'd1;
- litedramcore_re <= 1'd0;
- litedramcore_phaseinjector0_command_storage <= 6'd0;
- litedramcore_phaseinjector0_command_re <= 1'd0;
- litedramcore_phaseinjector0_address_re <= 1'd0;
- litedramcore_phaseinjector0_baddress_re <= 1'd0;
- litedramcore_phaseinjector0_wrdata_re <= 1'd0;
- litedramcore_phaseinjector0_rddata_status <= 64'd0;
- litedramcore_phaseinjector0_rddata_re <= 1'd0;
- litedramcore_phaseinjector1_command_storage <= 6'd0;
- litedramcore_phaseinjector1_command_re <= 1'd0;
- litedramcore_phaseinjector1_address_re <= 1'd0;
- litedramcore_phaseinjector1_baddress_re <= 1'd0;
- litedramcore_phaseinjector1_wrdata_re <= 1'd0;
- litedramcore_phaseinjector1_rddata_status <= 64'd0;
- litedramcore_phaseinjector1_rddata_re <= 1'd0;
- litedramcore_phaseinjector2_command_storage <= 6'd0;
- litedramcore_phaseinjector2_command_re <= 1'd0;
- litedramcore_phaseinjector2_address_re <= 1'd0;
- litedramcore_phaseinjector2_baddress_re <= 1'd0;
- litedramcore_phaseinjector2_wrdata_re <= 1'd0;
- litedramcore_phaseinjector2_rddata_status <= 64'd0;
- litedramcore_phaseinjector2_rddata_re <= 1'd0;
- litedramcore_phaseinjector3_command_storage <= 6'd0;
- litedramcore_phaseinjector3_command_re <= 1'd0;
- litedramcore_phaseinjector3_address_re <= 1'd0;
- litedramcore_phaseinjector3_baddress_re <= 1'd0;
- litedramcore_phaseinjector3_wrdata_re <= 1'd0;
- litedramcore_phaseinjector3_rddata_status <= 64'd0;
- litedramcore_phaseinjector3_rddata_re <= 1'd0;
- litedramcore_dfi_p0_address <= 15'd0;
- litedramcore_dfi_p0_bank <= 3'd0;
- litedramcore_dfi_p0_cas_n <= 1'd1;
- litedramcore_dfi_p0_cs_n <= 1'd1;
- litedramcore_dfi_p0_ras_n <= 1'd1;
- litedramcore_dfi_p0_we_n <= 1'd1;
- litedramcore_dfi_p0_wrdata_en <= 1'd0;
- litedramcore_dfi_p0_rddata_en <= 1'd0;
- litedramcore_dfi_p1_address <= 15'd0;
- litedramcore_dfi_p1_bank <= 3'd0;
- litedramcore_dfi_p1_cas_n <= 1'd1;
- litedramcore_dfi_p1_cs_n <= 1'd1;
- litedramcore_dfi_p1_ras_n <= 1'd1;
- litedramcore_dfi_p1_we_n <= 1'd1;
- litedramcore_dfi_p1_wrdata_en <= 1'd0;
- litedramcore_dfi_p1_rddata_en <= 1'd0;
- litedramcore_dfi_p2_address <= 15'd0;
- litedramcore_dfi_p2_bank <= 3'd0;
- litedramcore_dfi_p2_cas_n <= 1'd1;
- litedramcore_dfi_p2_cs_n <= 1'd1;
- litedramcore_dfi_p2_ras_n <= 1'd1;
- litedramcore_dfi_p2_we_n <= 1'd1;
- litedramcore_dfi_p2_wrdata_en <= 1'd0;
- litedramcore_dfi_p2_rddata_en <= 1'd0;
- litedramcore_dfi_p3_address <= 15'd0;
- litedramcore_dfi_p3_bank <= 3'd0;
- litedramcore_dfi_p3_cas_n <= 1'd1;
- litedramcore_dfi_p3_cs_n <= 1'd1;
- litedramcore_dfi_p3_ras_n <= 1'd1;
- litedramcore_dfi_p3_we_n <= 1'd1;
- litedramcore_dfi_p3_wrdata_en <= 1'd0;
- litedramcore_dfi_p3_rddata_en <= 1'd0;
- litedramcore_cmd_payload_a <= 15'd0;
- litedramcore_cmd_payload_ba <= 3'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd0;
- litedramcore_cmd_payload_we <= 1'd0;
- litedramcore_timer_count1 <= 10'd781;
- litedramcore_postponer_req_o <= 1'd0;
- litedramcore_postponer_count <= 1'd0;
- litedramcore_sequencer_done1 <= 1'd0;
- litedramcore_sequencer_counter <= 6'd0;
- litedramcore_sequencer_count <= 1'd0;
- litedramcore_zqcs_timer_count1 <= 27'd99999999;
- litedramcore_zqcs_executer_done <= 1'd0;
- litedramcore_zqcs_executer_counter <= 5'd0;
- litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine0_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= 22'd0;
- litedramcore_bankmachine0_row <= 15'd0;
- litedramcore_bankmachine0_row_opened <= 1'd0;
- litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine0_twtpcon_count <= 3'd0;
- litedramcore_bankmachine0_trccon_ready <= 1'd0;
- litedramcore_bankmachine0_trccon_count <= 3'd0;
- litedramcore_bankmachine0_trascon_ready <= 1'd0;
- litedramcore_bankmachine0_trascon_count <= 3'd0;
- litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine1_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= 22'd0;
- litedramcore_bankmachine1_row <= 15'd0;
- litedramcore_bankmachine1_row_opened <= 1'd0;
- litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine1_twtpcon_count <= 3'd0;
- litedramcore_bankmachine1_trccon_ready <= 1'd0;
- litedramcore_bankmachine1_trccon_count <= 3'd0;
- litedramcore_bankmachine1_trascon_ready <= 1'd0;
- litedramcore_bankmachine1_trascon_count <= 3'd0;
- litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine2_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= 22'd0;
- litedramcore_bankmachine2_row <= 15'd0;
- litedramcore_bankmachine2_row_opened <= 1'd0;
- litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine2_twtpcon_count <= 3'd0;
- litedramcore_bankmachine2_trccon_ready <= 1'd0;
- litedramcore_bankmachine2_trccon_count <= 3'd0;
- litedramcore_bankmachine2_trascon_ready <= 1'd0;
- litedramcore_bankmachine2_trascon_count <= 3'd0;
- litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine3_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= 22'd0;
- litedramcore_bankmachine3_row <= 15'd0;
- litedramcore_bankmachine3_row_opened <= 1'd0;
- litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine3_twtpcon_count <= 3'd0;
- litedramcore_bankmachine3_trccon_ready <= 1'd0;
- litedramcore_bankmachine3_trccon_count <= 3'd0;
- litedramcore_bankmachine3_trascon_ready <= 1'd0;
- litedramcore_bankmachine3_trascon_count <= 3'd0;
- litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine4_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= 22'd0;
- litedramcore_bankmachine4_row <= 15'd0;
- litedramcore_bankmachine4_row_opened <= 1'd0;
- litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine4_twtpcon_count <= 3'd0;
- litedramcore_bankmachine4_trccon_ready <= 1'd0;
- litedramcore_bankmachine4_trccon_count <= 3'd0;
- litedramcore_bankmachine4_trascon_ready <= 1'd0;
- litedramcore_bankmachine4_trascon_count <= 3'd0;
- litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine5_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= 22'd0;
- litedramcore_bankmachine5_row <= 15'd0;
- litedramcore_bankmachine5_row_opened <= 1'd0;
- litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine5_twtpcon_count <= 3'd0;
- litedramcore_bankmachine5_trccon_ready <= 1'd0;
- litedramcore_bankmachine5_trccon_count <= 3'd0;
- litedramcore_bankmachine5_trascon_ready <= 1'd0;
- litedramcore_bankmachine5_trascon_count <= 3'd0;
- litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine6_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= 22'd0;
- litedramcore_bankmachine6_row <= 15'd0;
- litedramcore_bankmachine6_row_opened <= 1'd0;
- litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine6_twtpcon_count <= 3'd0;
- litedramcore_bankmachine6_trccon_ready <= 1'd0;
- litedramcore_bankmachine6_trccon_count <= 3'd0;
- litedramcore_bankmachine6_trascon_ready <= 1'd0;
- litedramcore_bankmachine6_trascon_count <= 3'd0;
- litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine7_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= 22'd0;
- litedramcore_bankmachine7_row <= 15'd0;
- litedramcore_bankmachine7_row_opened <= 1'd0;
- litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine7_twtpcon_count <= 3'd0;
- litedramcore_bankmachine7_trccon_ready <= 1'd0;
- litedramcore_bankmachine7_trccon_count <= 3'd0;
- litedramcore_bankmachine7_trascon_ready <= 1'd0;
- litedramcore_bankmachine7_trascon_count <= 3'd0;
- litedramcore_choose_cmd_grant <= 3'd0;
- litedramcore_choose_req_grant <= 3'd0;
- litedramcore_trrdcon_ready <= 1'd0;
- litedramcore_trrdcon_count <= 1'd0;
- litedramcore_tfawcon_ready <= 1'd1;
- litedramcore_tfawcon_window <= 5'd0;
- litedramcore_tccdcon_ready <= 1'd0;
- litedramcore_tccdcon_count <= 1'd0;
- litedramcore_twtrcon_ready <= 1'd0;
- litedramcore_twtrcon_count <= 3'd0;
- litedramcore_time0 <= 5'd0;
- litedramcore_time1 <= 4'd0;
- init_done_storage <= 1'd0;
- init_done_re <= 1'd0;
- init_error_storage <= 1'd0;
- init_error_re <= 1'd0;
- litedramcore_we <= 1'd0;
- litedramcore_refresher_state <= 2'd0;
- litedramcore_bankmachine0_state <= 4'd0;
- litedramcore_bankmachine1_state <= 4'd0;
- litedramcore_bankmachine2_state <= 4'd0;
- litedramcore_bankmachine3_state <= 4'd0;
- litedramcore_bankmachine4_state <= 4'd0;
- litedramcore_bankmachine5_state <= 4'd0;
- litedramcore_bankmachine6_state <= 4'd0;
- litedramcore_bankmachine7_state <= 4'd0;
- litedramcore_multiplexer_state <= 4'd0;
- litedramcore_new_master_wdata_ready0 <= 1'd0;
- litedramcore_new_master_wdata_ready1 <= 1'd0;
- litedramcore_new_master_rdata_valid0 <= 1'd0;
- litedramcore_new_master_rdata_valid1 <= 1'd0;
- litedramcore_new_master_rdata_valid2 <= 1'd0;
- litedramcore_new_master_rdata_valid3 <= 1'd0;
- litedramcore_new_master_rdata_valid4 <= 1'd0;
- litedramcore_new_master_rdata_valid5 <= 1'd0;
- litedramcore_new_master_rdata_valid6 <= 1'd0;
- litedramcore_new_master_rdata_valid7 <= 1'd0;
- litedramcore_new_master_rdata_valid8 <= 1'd0;
- litedramcore_state <= 2'd0;
- end
+ k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= k7ddrphy_dqs_oe_delay_tappeddelayline;
+ k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0;
+ if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip0_value0 <= (k7ddrphy_bitslip0_value0 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip0_value0 <= 3'd7;
+ end
+ k7ddrphy_bitslip0_r0 <= {k7ddrphy_dqspattern_o, k7ddrphy_bitslip0_r0[15:8]};
+ if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip1_value0 <= (k7ddrphy_bitslip1_value0 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip1_value0 <= 3'd7;
+ end
+ k7ddrphy_bitslip1_r0 <= {k7ddrphy_dqspattern_o, k7ddrphy_bitslip1_r0[15:8]};
+ if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip2_value0 <= (k7ddrphy_bitslip2_value0 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip2_value0 <= 3'd7;
+ end
+ k7ddrphy_bitslip2_r0 <= {k7ddrphy_dqspattern_o, k7ddrphy_bitslip2_r0[15:8]};
+ if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip3_value0 <= (k7ddrphy_bitslip3_value0 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip3_value0 <= 3'd7;
+ end
+ k7ddrphy_bitslip3_r0 <= {k7ddrphy_dqspattern_o, k7ddrphy_bitslip3_r0[15:8]};
+ if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip0_value1 <= (k7ddrphy_bitslip0_value1 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip0_value1 <= 3'd7;
+ end
+ k7ddrphy_bitslip0_r1 <= {{k7ddrphy_dfi_p3_wrdata_mask[4], k7ddrphy_dfi_p3_wrdata_mask[0], k7ddrphy_dfi_p2_wrdata_mask[4], k7ddrphy_dfi_p2_wrdata_mask[0], k7ddrphy_dfi_p1_wrdata_mask[4], k7ddrphy_dfi_p1_wrdata_mask[0], k7ddrphy_dfi_p0_wrdata_mask[4], k7ddrphy_dfi_p0_wrdata_mask[0]}, k7ddrphy_bitslip0_r1[15:8]};
+ if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip1_value1 <= (k7ddrphy_bitslip1_value1 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip1_value1 <= 3'd7;
+ end
+ k7ddrphy_bitslip1_r1 <= {{k7ddrphy_dfi_p3_wrdata_mask[5], k7ddrphy_dfi_p3_wrdata_mask[1], k7ddrphy_dfi_p2_wrdata_mask[5], k7ddrphy_dfi_p2_wrdata_mask[1], k7ddrphy_dfi_p1_wrdata_mask[5], k7ddrphy_dfi_p1_wrdata_mask[1], k7ddrphy_dfi_p0_wrdata_mask[5], k7ddrphy_dfi_p0_wrdata_mask[1]}, k7ddrphy_bitslip1_r1[15:8]};
+ if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip2_value1 <= (k7ddrphy_bitslip2_value1 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip2_value1 <= 3'd7;
+ end
+ k7ddrphy_bitslip2_r1 <= {{k7ddrphy_dfi_p3_wrdata_mask[6], k7ddrphy_dfi_p3_wrdata_mask[2], k7ddrphy_dfi_p2_wrdata_mask[6], k7ddrphy_dfi_p2_wrdata_mask[2], k7ddrphy_dfi_p1_wrdata_mask[6], k7ddrphy_dfi_p1_wrdata_mask[2], k7ddrphy_dfi_p0_wrdata_mask[6], k7ddrphy_dfi_p0_wrdata_mask[2]}, k7ddrphy_bitslip2_r1[15:8]};
+ if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip3_value1 <= (k7ddrphy_bitslip3_value1 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip3_value1 <= 3'd7;
+ end
+ k7ddrphy_bitslip3_r1 <= {{k7ddrphy_dfi_p3_wrdata_mask[7], k7ddrphy_dfi_p3_wrdata_mask[3], k7ddrphy_dfi_p2_wrdata_mask[7], k7ddrphy_dfi_p2_wrdata_mask[3], k7ddrphy_dfi_p1_wrdata_mask[7], k7ddrphy_dfi_p1_wrdata_mask[3], k7ddrphy_dfi_p0_wrdata_mask[7], k7ddrphy_dfi_p0_wrdata_mask[3]}, k7ddrphy_bitslip3_r1[15:8]};
+ k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= k7ddrphy_dq_oe_delay_tappeddelayline;
+ k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0;
+ if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip0_value2 <= (k7ddrphy_bitslip0_value2 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip0_value2 <= 3'd7;
+ end
+ k7ddrphy_bitslip0_r2 <= {{k7ddrphy_dfi_p3_wrdata[32], k7ddrphy_dfi_p3_wrdata[0], k7ddrphy_dfi_p2_wrdata[32], k7ddrphy_dfi_p2_wrdata[0], k7ddrphy_dfi_p1_wrdata[32], k7ddrphy_dfi_p1_wrdata[0], k7ddrphy_dfi_p0_wrdata[32], k7ddrphy_dfi_p0_wrdata[0]}, k7ddrphy_bitslip0_r2[15:8]};
+ if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip0_value3 <= (k7ddrphy_bitslip0_value3 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip0_value3 <= 3'd7;
+ end
+ k7ddrphy_bitslip0_r3 <= {k7ddrphy_bitslip03, k7ddrphy_bitslip0_r3[15:8]};
+ if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip1_value2 <= (k7ddrphy_bitslip1_value2 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip1_value2 <= 3'd7;
+ end
+ k7ddrphy_bitslip1_r2 <= {{k7ddrphy_dfi_p3_wrdata[33], k7ddrphy_dfi_p3_wrdata[1], k7ddrphy_dfi_p2_wrdata[33], k7ddrphy_dfi_p2_wrdata[1], k7ddrphy_dfi_p1_wrdata[33], k7ddrphy_dfi_p1_wrdata[1], k7ddrphy_dfi_p0_wrdata[33], k7ddrphy_dfi_p0_wrdata[1]}, k7ddrphy_bitslip1_r2[15:8]};
+ if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip1_value3 <= (k7ddrphy_bitslip1_value3 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip1_value3 <= 3'd7;
+ end
+ k7ddrphy_bitslip1_r3 <= {k7ddrphy_bitslip13, k7ddrphy_bitslip1_r3[15:8]};
+ if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip2_value2 <= (k7ddrphy_bitslip2_value2 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip2_value2 <= 3'd7;
+ end
+ k7ddrphy_bitslip2_r2 <= {{k7ddrphy_dfi_p3_wrdata[34], k7ddrphy_dfi_p3_wrdata[2], k7ddrphy_dfi_p2_wrdata[34], k7ddrphy_dfi_p2_wrdata[2], k7ddrphy_dfi_p1_wrdata[34], k7ddrphy_dfi_p1_wrdata[2], k7ddrphy_dfi_p0_wrdata[34], k7ddrphy_dfi_p0_wrdata[2]}, k7ddrphy_bitslip2_r2[15:8]};
+ if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip2_value3 <= (k7ddrphy_bitslip2_value3 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip2_value3 <= 3'd7;
+ end
+ k7ddrphy_bitslip2_r3 <= {k7ddrphy_bitslip23, k7ddrphy_bitslip2_r3[15:8]};
+ if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip3_value2 <= (k7ddrphy_bitslip3_value2 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip3_value2 <= 3'd7;
+ end
+ k7ddrphy_bitslip3_r2 <= {{k7ddrphy_dfi_p3_wrdata[35], k7ddrphy_dfi_p3_wrdata[3], k7ddrphy_dfi_p2_wrdata[35], k7ddrphy_dfi_p2_wrdata[3], k7ddrphy_dfi_p1_wrdata[35], k7ddrphy_dfi_p1_wrdata[3], k7ddrphy_dfi_p0_wrdata[35], k7ddrphy_dfi_p0_wrdata[3]}, k7ddrphy_bitslip3_r2[15:8]};
+ if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip3_value3 <= (k7ddrphy_bitslip3_value3 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip3_value3 <= 3'd7;
+ end
+ k7ddrphy_bitslip3_r3 <= {k7ddrphy_bitslip33, k7ddrphy_bitslip3_r3[15:8]};
+ if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip4_value0 <= (k7ddrphy_bitslip4_value0 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip4_value0 <= 3'd7;
+ end
+ k7ddrphy_bitslip4_r0 <= {{k7ddrphy_dfi_p3_wrdata[36], k7ddrphy_dfi_p3_wrdata[4], k7ddrphy_dfi_p2_wrdata[36], k7ddrphy_dfi_p2_wrdata[4], k7ddrphy_dfi_p1_wrdata[36], k7ddrphy_dfi_p1_wrdata[4], k7ddrphy_dfi_p0_wrdata[36], k7ddrphy_dfi_p0_wrdata[4]}, k7ddrphy_bitslip4_r0[15:8]};
+ if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip4_value1 <= (k7ddrphy_bitslip4_value1 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip4_value1 <= 3'd7;
+ end
+ k7ddrphy_bitslip4_r1 <= {k7ddrphy_bitslip41, k7ddrphy_bitslip4_r1[15:8]};
+ if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip5_value0 <= (k7ddrphy_bitslip5_value0 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip5_value0 <= 3'd7;
+ end
+ k7ddrphy_bitslip5_r0 <= {{k7ddrphy_dfi_p3_wrdata[37], k7ddrphy_dfi_p3_wrdata[5], k7ddrphy_dfi_p2_wrdata[37], k7ddrphy_dfi_p2_wrdata[5], k7ddrphy_dfi_p1_wrdata[37], k7ddrphy_dfi_p1_wrdata[5], k7ddrphy_dfi_p0_wrdata[37], k7ddrphy_dfi_p0_wrdata[5]}, k7ddrphy_bitslip5_r0[15:8]};
+ if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip5_value1 <= (k7ddrphy_bitslip5_value1 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip5_value1 <= 3'd7;
+ end
+ k7ddrphy_bitslip5_r1 <= {k7ddrphy_bitslip51, k7ddrphy_bitslip5_r1[15:8]};
+ if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip6_value0 <= (k7ddrphy_bitslip6_value0 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip6_value0 <= 3'd7;
+ end
+ k7ddrphy_bitslip6_r0 <= {{k7ddrphy_dfi_p3_wrdata[38], k7ddrphy_dfi_p3_wrdata[6], k7ddrphy_dfi_p2_wrdata[38], k7ddrphy_dfi_p2_wrdata[6], k7ddrphy_dfi_p1_wrdata[38], k7ddrphy_dfi_p1_wrdata[6], k7ddrphy_dfi_p0_wrdata[38], k7ddrphy_dfi_p0_wrdata[6]}, k7ddrphy_bitslip6_r0[15:8]};
+ if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip6_value1 <= (k7ddrphy_bitslip6_value1 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip6_value1 <= 3'd7;
+ end
+ k7ddrphy_bitslip6_r1 <= {k7ddrphy_bitslip61, k7ddrphy_bitslip6_r1[15:8]};
+ if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip7_value0 <= (k7ddrphy_bitslip7_value0 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip7_value0 <= 3'd7;
+ end
+ k7ddrphy_bitslip7_r0 <= {{k7ddrphy_dfi_p3_wrdata[39], k7ddrphy_dfi_p3_wrdata[7], k7ddrphy_dfi_p2_wrdata[39], k7ddrphy_dfi_p2_wrdata[7], k7ddrphy_dfi_p1_wrdata[39], k7ddrphy_dfi_p1_wrdata[7], k7ddrphy_dfi_p0_wrdata[39], k7ddrphy_dfi_p0_wrdata[7]}, k7ddrphy_bitslip7_r0[15:8]};
+ if ((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip7_value1 <= (k7ddrphy_bitslip7_value1 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[0] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip7_value1 <= 3'd7;
+ end
+ k7ddrphy_bitslip7_r1 <= {k7ddrphy_bitslip71, k7ddrphy_bitslip7_r1[15:8]};
+ if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip8_value0 <= (k7ddrphy_bitslip8_value0 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip8_value0 <= 3'd7;
+ end
+ k7ddrphy_bitslip8_r0 <= {{k7ddrphy_dfi_p3_wrdata[40], k7ddrphy_dfi_p3_wrdata[8], k7ddrphy_dfi_p2_wrdata[40], k7ddrphy_dfi_p2_wrdata[8], k7ddrphy_dfi_p1_wrdata[40], k7ddrphy_dfi_p1_wrdata[8], k7ddrphy_dfi_p0_wrdata[40], k7ddrphy_dfi_p0_wrdata[8]}, k7ddrphy_bitslip8_r0[15:8]};
+ if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip8_value1 <= (k7ddrphy_bitslip8_value1 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip8_value1 <= 3'd7;
+ end
+ k7ddrphy_bitslip8_r1 <= {k7ddrphy_bitslip81, k7ddrphy_bitslip8_r1[15:8]};
+ if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip9_value0 <= (k7ddrphy_bitslip9_value0 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip9_value0 <= 3'd7;
+ end
+ k7ddrphy_bitslip9_r0 <= {{k7ddrphy_dfi_p3_wrdata[41], k7ddrphy_dfi_p3_wrdata[9], k7ddrphy_dfi_p2_wrdata[41], k7ddrphy_dfi_p2_wrdata[9], k7ddrphy_dfi_p1_wrdata[41], k7ddrphy_dfi_p1_wrdata[9], k7ddrphy_dfi_p0_wrdata[41], k7ddrphy_dfi_p0_wrdata[9]}, k7ddrphy_bitslip9_r0[15:8]};
+ if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip9_value1 <= (k7ddrphy_bitslip9_value1 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip9_value1 <= 3'd7;
+ end
+ k7ddrphy_bitslip9_r1 <= {k7ddrphy_bitslip91, k7ddrphy_bitslip9_r1[15:8]};
+ if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip10_value0 <= (k7ddrphy_bitslip10_value0 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip10_value0 <= 3'd7;
+ end
+ k7ddrphy_bitslip10_r0 <= {{k7ddrphy_dfi_p3_wrdata[42], k7ddrphy_dfi_p3_wrdata[10], k7ddrphy_dfi_p2_wrdata[42], k7ddrphy_dfi_p2_wrdata[10], k7ddrphy_dfi_p1_wrdata[42], k7ddrphy_dfi_p1_wrdata[10], k7ddrphy_dfi_p0_wrdata[42], k7ddrphy_dfi_p0_wrdata[10]}, k7ddrphy_bitslip10_r0[15:8]};
+ if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip10_value1 <= (k7ddrphy_bitslip10_value1 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip10_value1 <= 3'd7;
+ end
+ k7ddrphy_bitslip10_r1 <= {k7ddrphy_bitslip101, k7ddrphy_bitslip10_r1[15:8]};
+ if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip11_value0 <= (k7ddrphy_bitslip11_value0 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip11_value0 <= 3'd7;
+ end
+ k7ddrphy_bitslip11_r0 <= {{k7ddrphy_dfi_p3_wrdata[43], k7ddrphy_dfi_p3_wrdata[11], k7ddrphy_dfi_p2_wrdata[43], k7ddrphy_dfi_p2_wrdata[11], k7ddrphy_dfi_p1_wrdata[43], k7ddrphy_dfi_p1_wrdata[11], k7ddrphy_dfi_p0_wrdata[43], k7ddrphy_dfi_p0_wrdata[11]}, k7ddrphy_bitslip11_r0[15:8]};
+ if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip11_value1 <= (k7ddrphy_bitslip11_value1 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip11_value1 <= 3'd7;
+ end
+ k7ddrphy_bitslip11_r1 <= {k7ddrphy_bitslip111, k7ddrphy_bitslip11_r1[15:8]};
+ if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip12_value0 <= (k7ddrphy_bitslip12_value0 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip12_value0 <= 3'd7;
+ end
+ k7ddrphy_bitslip12_r0 <= {{k7ddrphy_dfi_p3_wrdata[44], k7ddrphy_dfi_p3_wrdata[12], k7ddrphy_dfi_p2_wrdata[44], k7ddrphy_dfi_p2_wrdata[12], k7ddrphy_dfi_p1_wrdata[44], k7ddrphy_dfi_p1_wrdata[12], k7ddrphy_dfi_p0_wrdata[44], k7ddrphy_dfi_p0_wrdata[12]}, k7ddrphy_bitslip12_r0[15:8]};
+ if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip12_value1 <= (k7ddrphy_bitslip12_value1 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip12_value1 <= 3'd7;
+ end
+ k7ddrphy_bitslip12_r1 <= {k7ddrphy_bitslip121, k7ddrphy_bitslip12_r1[15:8]};
+ if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip13_value0 <= (k7ddrphy_bitslip13_value0 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip13_value0 <= 3'd7;
+ end
+ k7ddrphy_bitslip13_r0 <= {{k7ddrphy_dfi_p3_wrdata[45], k7ddrphy_dfi_p3_wrdata[13], k7ddrphy_dfi_p2_wrdata[45], k7ddrphy_dfi_p2_wrdata[13], k7ddrphy_dfi_p1_wrdata[45], k7ddrphy_dfi_p1_wrdata[13], k7ddrphy_dfi_p0_wrdata[45], k7ddrphy_dfi_p0_wrdata[13]}, k7ddrphy_bitslip13_r0[15:8]};
+ if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip13_value1 <= (k7ddrphy_bitslip13_value1 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip13_value1 <= 3'd7;
+ end
+ k7ddrphy_bitslip13_r1 <= {k7ddrphy_bitslip131, k7ddrphy_bitslip13_r1[15:8]};
+ if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip14_value0 <= (k7ddrphy_bitslip14_value0 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip14_value0 <= 3'd7;
+ end
+ k7ddrphy_bitslip14_r0 <= {{k7ddrphy_dfi_p3_wrdata[46], k7ddrphy_dfi_p3_wrdata[14], k7ddrphy_dfi_p2_wrdata[46], k7ddrphy_dfi_p2_wrdata[14], k7ddrphy_dfi_p1_wrdata[46], k7ddrphy_dfi_p1_wrdata[14], k7ddrphy_dfi_p0_wrdata[46], k7ddrphy_dfi_p0_wrdata[14]}, k7ddrphy_bitslip14_r0[15:8]};
+ if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip14_value1 <= (k7ddrphy_bitslip14_value1 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip14_value1 <= 3'd7;
+ end
+ k7ddrphy_bitslip14_r1 <= {k7ddrphy_bitslip141, k7ddrphy_bitslip14_r1[15:8]};
+ if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip15_value0 <= (k7ddrphy_bitslip15_value0 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip15_value0 <= 3'd7;
+ end
+ k7ddrphy_bitslip15_r0 <= {{k7ddrphy_dfi_p3_wrdata[47], k7ddrphy_dfi_p3_wrdata[15], k7ddrphy_dfi_p2_wrdata[47], k7ddrphy_dfi_p2_wrdata[15], k7ddrphy_dfi_p1_wrdata[47], k7ddrphy_dfi_p1_wrdata[15], k7ddrphy_dfi_p0_wrdata[47], k7ddrphy_dfi_p0_wrdata[15]}, k7ddrphy_bitslip15_r0[15:8]};
+ if ((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip15_value1 <= (k7ddrphy_bitslip15_value1 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[1] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip15_value1 <= 3'd7;
+ end
+ k7ddrphy_bitslip15_r1 <= {k7ddrphy_bitslip151, k7ddrphy_bitslip15_r1[15:8]};
+ if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip16_value0 <= (k7ddrphy_bitslip16_value0 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip16_value0 <= 3'd7;
+ end
+ k7ddrphy_bitslip16_r0 <= {{k7ddrphy_dfi_p3_wrdata[48], k7ddrphy_dfi_p3_wrdata[16], k7ddrphy_dfi_p2_wrdata[48], k7ddrphy_dfi_p2_wrdata[16], k7ddrphy_dfi_p1_wrdata[48], k7ddrphy_dfi_p1_wrdata[16], k7ddrphy_dfi_p0_wrdata[48], k7ddrphy_dfi_p0_wrdata[16]}, k7ddrphy_bitslip16_r0[15:8]};
+ if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip16_value1 <= (k7ddrphy_bitslip16_value1 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip16_value1 <= 3'd7;
+ end
+ k7ddrphy_bitslip16_r1 <= {k7ddrphy_bitslip161, k7ddrphy_bitslip16_r1[15:8]};
+ if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip17_value0 <= (k7ddrphy_bitslip17_value0 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip17_value0 <= 3'd7;
+ end
+ k7ddrphy_bitslip17_r0 <= {{k7ddrphy_dfi_p3_wrdata[49], k7ddrphy_dfi_p3_wrdata[17], k7ddrphy_dfi_p2_wrdata[49], k7ddrphy_dfi_p2_wrdata[17], k7ddrphy_dfi_p1_wrdata[49], k7ddrphy_dfi_p1_wrdata[17], k7ddrphy_dfi_p0_wrdata[49], k7ddrphy_dfi_p0_wrdata[17]}, k7ddrphy_bitslip17_r0[15:8]};
+ if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip17_value1 <= (k7ddrphy_bitslip17_value1 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip17_value1 <= 3'd7;
+ end
+ k7ddrphy_bitslip17_r1 <= {k7ddrphy_bitslip171, k7ddrphy_bitslip17_r1[15:8]};
+ if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip18_value0 <= (k7ddrphy_bitslip18_value0 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip18_value0 <= 3'd7;
+ end
+ k7ddrphy_bitslip18_r0 <= {{k7ddrphy_dfi_p3_wrdata[50], k7ddrphy_dfi_p3_wrdata[18], k7ddrphy_dfi_p2_wrdata[50], k7ddrphy_dfi_p2_wrdata[18], k7ddrphy_dfi_p1_wrdata[50], k7ddrphy_dfi_p1_wrdata[18], k7ddrphy_dfi_p0_wrdata[50], k7ddrphy_dfi_p0_wrdata[18]}, k7ddrphy_bitslip18_r0[15:8]};
+ if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip18_value1 <= (k7ddrphy_bitslip18_value1 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip18_value1 <= 3'd7;
+ end
+ k7ddrphy_bitslip18_r1 <= {k7ddrphy_bitslip181, k7ddrphy_bitslip18_r1[15:8]};
+ if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip19_value0 <= (k7ddrphy_bitslip19_value0 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip19_value0 <= 3'd7;
+ end
+ k7ddrphy_bitslip19_r0 <= {{k7ddrphy_dfi_p3_wrdata[51], k7ddrphy_dfi_p3_wrdata[19], k7ddrphy_dfi_p2_wrdata[51], k7ddrphy_dfi_p2_wrdata[19], k7ddrphy_dfi_p1_wrdata[51], k7ddrphy_dfi_p1_wrdata[19], k7ddrphy_dfi_p0_wrdata[51], k7ddrphy_dfi_p0_wrdata[19]}, k7ddrphy_bitslip19_r0[15:8]};
+ if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip19_value1 <= (k7ddrphy_bitslip19_value1 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip19_value1 <= 3'd7;
+ end
+ k7ddrphy_bitslip19_r1 <= {k7ddrphy_bitslip191, k7ddrphy_bitslip19_r1[15:8]};
+ if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip20_value0 <= (k7ddrphy_bitslip20_value0 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip20_value0 <= 3'd7;
+ end
+ k7ddrphy_bitslip20_r0 <= {{k7ddrphy_dfi_p3_wrdata[52], k7ddrphy_dfi_p3_wrdata[20], k7ddrphy_dfi_p2_wrdata[52], k7ddrphy_dfi_p2_wrdata[20], k7ddrphy_dfi_p1_wrdata[52], k7ddrphy_dfi_p1_wrdata[20], k7ddrphy_dfi_p0_wrdata[52], k7ddrphy_dfi_p0_wrdata[20]}, k7ddrphy_bitslip20_r0[15:8]};
+ if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip20_value1 <= (k7ddrphy_bitslip20_value1 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip20_value1 <= 3'd7;
+ end
+ k7ddrphy_bitslip20_r1 <= {k7ddrphy_bitslip201, k7ddrphy_bitslip20_r1[15:8]};
+ if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip21_value0 <= (k7ddrphy_bitslip21_value0 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip21_value0 <= 3'd7;
+ end
+ k7ddrphy_bitslip21_r0 <= {{k7ddrphy_dfi_p3_wrdata[53], k7ddrphy_dfi_p3_wrdata[21], k7ddrphy_dfi_p2_wrdata[53], k7ddrphy_dfi_p2_wrdata[21], k7ddrphy_dfi_p1_wrdata[53], k7ddrphy_dfi_p1_wrdata[21], k7ddrphy_dfi_p0_wrdata[53], k7ddrphy_dfi_p0_wrdata[21]}, k7ddrphy_bitslip21_r0[15:8]};
+ if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip21_value1 <= (k7ddrphy_bitslip21_value1 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip21_value1 <= 3'd7;
+ end
+ k7ddrphy_bitslip21_r1 <= {k7ddrphy_bitslip211, k7ddrphy_bitslip21_r1[15:8]};
+ if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip22_value0 <= (k7ddrphy_bitslip22_value0 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip22_value0 <= 3'd7;
+ end
+ k7ddrphy_bitslip22_r0 <= {{k7ddrphy_dfi_p3_wrdata[54], k7ddrphy_dfi_p3_wrdata[22], k7ddrphy_dfi_p2_wrdata[54], k7ddrphy_dfi_p2_wrdata[22], k7ddrphy_dfi_p1_wrdata[54], k7ddrphy_dfi_p1_wrdata[22], k7ddrphy_dfi_p0_wrdata[54], k7ddrphy_dfi_p0_wrdata[22]}, k7ddrphy_bitslip22_r0[15:8]};
+ if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip22_value1 <= (k7ddrphy_bitslip22_value1 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip22_value1 <= 3'd7;
+ end
+ k7ddrphy_bitslip22_r1 <= {k7ddrphy_bitslip221, k7ddrphy_bitslip22_r1[15:8]};
+ if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip23_value0 <= (k7ddrphy_bitslip23_value0 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip23_value0 <= 3'd7;
+ end
+ k7ddrphy_bitslip23_r0 <= {{k7ddrphy_dfi_p3_wrdata[55], k7ddrphy_dfi_p3_wrdata[23], k7ddrphy_dfi_p2_wrdata[55], k7ddrphy_dfi_p2_wrdata[23], k7ddrphy_dfi_p1_wrdata[55], k7ddrphy_dfi_p1_wrdata[23], k7ddrphy_dfi_p0_wrdata[55], k7ddrphy_dfi_p0_wrdata[23]}, k7ddrphy_bitslip23_r0[15:8]};
+ if ((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip23_value1 <= (k7ddrphy_bitslip23_value1 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[2] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip23_value1 <= 3'd7;
+ end
+ k7ddrphy_bitslip23_r1 <= {k7ddrphy_bitslip231, k7ddrphy_bitslip23_r1[15:8]};
+ if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip24_value0 <= (k7ddrphy_bitslip24_value0 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip24_value0 <= 3'd7;
+ end
+ k7ddrphy_bitslip24_r0 <= {{k7ddrphy_dfi_p3_wrdata[56], k7ddrphy_dfi_p3_wrdata[24], k7ddrphy_dfi_p2_wrdata[56], k7ddrphy_dfi_p2_wrdata[24], k7ddrphy_dfi_p1_wrdata[56], k7ddrphy_dfi_p1_wrdata[24], k7ddrphy_dfi_p0_wrdata[56], k7ddrphy_dfi_p0_wrdata[24]}, k7ddrphy_bitslip24_r0[15:8]};
+ if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip24_value1 <= (k7ddrphy_bitslip24_value1 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip24_value1 <= 3'd7;
+ end
+ k7ddrphy_bitslip24_r1 <= {k7ddrphy_bitslip241, k7ddrphy_bitslip24_r1[15:8]};
+ if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip25_value0 <= (k7ddrphy_bitslip25_value0 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip25_value0 <= 3'd7;
+ end
+ k7ddrphy_bitslip25_r0 <= {{k7ddrphy_dfi_p3_wrdata[57], k7ddrphy_dfi_p3_wrdata[25], k7ddrphy_dfi_p2_wrdata[57], k7ddrphy_dfi_p2_wrdata[25], k7ddrphy_dfi_p1_wrdata[57], k7ddrphy_dfi_p1_wrdata[25], k7ddrphy_dfi_p0_wrdata[57], k7ddrphy_dfi_p0_wrdata[25]}, k7ddrphy_bitslip25_r0[15:8]};
+ if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip25_value1 <= (k7ddrphy_bitslip25_value1 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip25_value1 <= 3'd7;
+ end
+ k7ddrphy_bitslip25_r1 <= {k7ddrphy_bitslip251, k7ddrphy_bitslip25_r1[15:8]};
+ if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip26_value0 <= (k7ddrphy_bitslip26_value0 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip26_value0 <= 3'd7;
+ end
+ k7ddrphy_bitslip26_r0 <= {{k7ddrphy_dfi_p3_wrdata[58], k7ddrphy_dfi_p3_wrdata[26], k7ddrphy_dfi_p2_wrdata[58], k7ddrphy_dfi_p2_wrdata[26], k7ddrphy_dfi_p1_wrdata[58], k7ddrphy_dfi_p1_wrdata[26], k7ddrphy_dfi_p0_wrdata[58], k7ddrphy_dfi_p0_wrdata[26]}, k7ddrphy_bitslip26_r0[15:8]};
+ if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip26_value1 <= (k7ddrphy_bitslip26_value1 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip26_value1 <= 3'd7;
+ end
+ k7ddrphy_bitslip26_r1 <= {k7ddrphy_bitslip261, k7ddrphy_bitslip26_r1[15:8]};
+ if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip27_value0 <= (k7ddrphy_bitslip27_value0 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip27_value0 <= 3'd7;
+ end
+ k7ddrphy_bitslip27_r0 <= {{k7ddrphy_dfi_p3_wrdata[59], k7ddrphy_dfi_p3_wrdata[27], k7ddrphy_dfi_p2_wrdata[59], k7ddrphy_dfi_p2_wrdata[27], k7ddrphy_dfi_p1_wrdata[59], k7ddrphy_dfi_p1_wrdata[27], k7ddrphy_dfi_p0_wrdata[59], k7ddrphy_dfi_p0_wrdata[27]}, k7ddrphy_bitslip27_r0[15:8]};
+ if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip27_value1 <= (k7ddrphy_bitslip27_value1 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip27_value1 <= 3'd7;
+ end
+ k7ddrphy_bitslip27_r1 <= {k7ddrphy_bitslip271, k7ddrphy_bitslip27_r1[15:8]};
+ if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip28_value0 <= (k7ddrphy_bitslip28_value0 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip28_value0 <= 3'd7;
+ end
+ k7ddrphy_bitslip28_r0 <= {{k7ddrphy_dfi_p3_wrdata[60], k7ddrphy_dfi_p3_wrdata[28], k7ddrphy_dfi_p2_wrdata[60], k7ddrphy_dfi_p2_wrdata[28], k7ddrphy_dfi_p1_wrdata[60], k7ddrphy_dfi_p1_wrdata[28], k7ddrphy_dfi_p0_wrdata[60], k7ddrphy_dfi_p0_wrdata[28]}, k7ddrphy_bitslip28_r0[15:8]};
+ if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip28_value1 <= (k7ddrphy_bitslip28_value1 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip28_value1 <= 3'd7;
+ end
+ k7ddrphy_bitslip28_r1 <= {k7ddrphy_bitslip281, k7ddrphy_bitslip28_r1[15:8]};
+ if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip29_value0 <= (k7ddrphy_bitslip29_value0 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip29_value0 <= 3'd7;
+ end
+ k7ddrphy_bitslip29_r0 <= {{k7ddrphy_dfi_p3_wrdata[61], k7ddrphy_dfi_p3_wrdata[29], k7ddrphy_dfi_p2_wrdata[61], k7ddrphy_dfi_p2_wrdata[29], k7ddrphy_dfi_p1_wrdata[61], k7ddrphy_dfi_p1_wrdata[29], k7ddrphy_dfi_p0_wrdata[61], k7ddrphy_dfi_p0_wrdata[29]}, k7ddrphy_bitslip29_r0[15:8]};
+ if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip29_value1 <= (k7ddrphy_bitslip29_value1 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip29_value1 <= 3'd7;
+ end
+ k7ddrphy_bitslip29_r1 <= {k7ddrphy_bitslip291, k7ddrphy_bitslip29_r1[15:8]};
+ if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip30_value0 <= (k7ddrphy_bitslip30_value0 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip30_value0 <= 3'd7;
+ end
+ k7ddrphy_bitslip30_r0 <= {{k7ddrphy_dfi_p3_wrdata[62], k7ddrphy_dfi_p3_wrdata[30], k7ddrphy_dfi_p2_wrdata[62], k7ddrphy_dfi_p2_wrdata[30], k7ddrphy_dfi_p1_wrdata[62], k7ddrphy_dfi_p1_wrdata[30], k7ddrphy_dfi_p0_wrdata[62], k7ddrphy_dfi_p0_wrdata[30]}, k7ddrphy_bitslip30_r0[15:8]};
+ if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip30_value1 <= (k7ddrphy_bitslip30_value1 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip30_value1 <= 3'd7;
+ end
+ k7ddrphy_bitslip30_r1 <= {k7ddrphy_bitslip301, k7ddrphy_bitslip30_r1[15:8]};
+ if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip31_value0 <= (k7ddrphy_bitslip31_value0 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_wdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip31_value0 <= 3'd7;
+ end
+ k7ddrphy_bitslip31_r0 <= {{k7ddrphy_dfi_p3_wrdata[63], k7ddrphy_dfi_p3_wrdata[31], k7ddrphy_dfi_p2_wrdata[63], k7ddrphy_dfi_p2_wrdata[31], k7ddrphy_dfi_p1_wrdata[63], k7ddrphy_dfi_p1_wrdata[31], k7ddrphy_dfi_p0_wrdata[63], k7ddrphy_dfi_p0_wrdata[31]}, k7ddrphy_bitslip31_r0[15:8]};
+ if ((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_re)) begin
+ k7ddrphy_bitslip31_value1 <= (k7ddrphy_bitslip31_value1 + 1'd1);
+ end
+ if (((k7ddrphy_dly_sel_storage[3] & k7ddrphy_rdly_dq_bitslip_rst_re) | k7ddrphy_rst_storage)) begin
+ k7ddrphy_bitslip31_value1 <= 3'd7;
+ end
+ k7ddrphy_bitslip31_r1 <= {k7ddrphy_bitslip311, k7ddrphy_bitslip31_r1[15:8]};
+ k7ddrphy_rddata_en_tappeddelayline0 <= (((k7ddrphy_dfi_p0_rddata_en | k7ddrphy_dfi_p1_rddata_en) | k7ddrphy_dfi_p2_rddata_en) | k7ddrphy_dfi_p3_rddata_en);
+ k7ddrphy_rddata_en_tappeddelayline1 <= k7ddrphy_rddata_en_tappeddelayline0;
+ k7ddrphy_rddata_en_tappeddelayline2 <= k7ddrphy_rddata_en_tappeddelayline1;
+ k7ddrphy_rddata_en_tappeddelayline3 <= k7ddrphy_rddata_en_tappeddelayline2;
+ k7ddrphy_rddata_en_tappeddelayline4 <= k7ddrphy_rddata_en_tappeddelayline3;
+ k7ddrphy_rddata_en_tappeddelayline5 <= k7ddrphy_rddata_en_tappeddelayline4;
+ k7ddrphy_rddata_en_tappeddelayline6 <= k7ddrphy_rddata_en_tappeddelayline5;
+ k7ddrphy_rddata_en_tappeddelayline7 <= k7ddrphy_rddata_en_tappeddelayline6;
+ k7ddrphy_wrdata_en_tappeddelayline0 <= (((k7ddrphy_dfi_p0_wrdata_en | k7ddrphy_dfi_p1_wrdata_en) | k7ddrphy_dfi_p2_wrdata_en) | k7ddrphy_dfi_p3_wrdata_en);
+ k7ddrphy_wrdata_en_tappeddelayline1 <= k7ddrphy_wrdata_en_tappeddelayline0;
+ k7ddrphy_wrdata_en_tappeddelayline2 <= k7ddrphy_wrdata_en_tappeddelayline1;
+ if (litedramcore_csr_dfi_p0_rddata_valid) begin
+ litedramcore_phaseinjector0_rddata_status <= litedramcore_csr_dfi_p0_rddata;
+ end
+ if (litedramcore_csr_dfi_p1_rddata_valid) begin
+ litedramcore_phaseinjector1_rddata_status <= litedramcore_csr_dfi_p1_rddata;
+ end
+ if (litedramcore_csr_dfi_p2_rddata_valid) begin
+ litedramcore_phaseinjector2_rddata_status <= litedramcore_csr_dfi_p2_rddata;
+ end
+ if (litedramcore_csr_dfi_p3_rddata_valid) begin
+ litedramcore_phaseinjector3_rddata_status <= litedramcore_csr_dfi_p3_rddata;
+ end
+ if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin
+ litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1);
+ end else begin
+ litedramcore_timer_count1 <= 10'd781;
+ end
+ litedramcore_postponer_req_o <= 1'd0;
+ if (litedramcore_postponer_req_i) begin
+ litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1);
+ if ((litedramcore_postponer_count == 1'd0)) begin
+ litedramcore_postponer_count <= 1'd0;
+ litedramcore_postponer_req_o <= 1'd1;
+ end
+ end
+ if (litedramcore_sequencer_start0) begin
+ litedramcore_sequencer_count <= 1'd0;
+ end else begin
+ if (litedramcore_sequencer_done1) begin
+ if ((litedramcore_sequencer_count != 1'd0)) begin
+ litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1);
+ end
+ end
+ end
+ litedramcore_cmd_payload_a <= 1'd0;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd0;
+ litedramcore_cmd_payload_we <= 1'd0;
+ litedramcore_sequencer_done1 <= 1'd0;
+ if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin
+ litedramcore_cmd_payload_a <= 11'd1024;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd1;
+ litedramcore_cmd_payload_we <= 1'd1;
+ end
+ if ((litedramcore_sequencer_counter == 2'd3)) begin
+ litedramcore_cmd_payload_a <= 11'd1024;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd1;
+ litedramcore_cmd_payload_ras <= 1'd1;
+ litedramcore_cmd_payload_we <= 1'd0;
+ end
+ if ((litedramcore_sequencer_counter == 6'd55)) begin
+ litedramcore_cmd_payload_a <= 1'd0;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd0;
+ litedramcore_cmd_payload_we <= 1'd0;
+ litedramcore_sequencer_done1 <= 1'd1;
+ end
+ if ((litedramcore_sequencer_counter == 6'd55)) begin
+ litedramcore_sequencer_counter <= 1'd0;
+ end else begin
+ if ((litedramcore_sequencer_counter != 1'd0)) begin
+ litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1);
+ end else begin
+ if (litedramcore_sequencer_start1) begin
+ litedramcore_sequencer_counter <= 1'd1;
+ end
+ end
+ end
+ if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin
+ litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1);
+ end else begin
+ litedramcore_zqcs_timer_count1 <= 27'd99999999;
+ end
+ litedramcore_zqcs_executer_done <= 1'd0;
+ if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin
+ litedramcore_cmd_payload_a <= 11'd1024;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd1;
+ litedramcore_cmd_payload_we <= 1'd1;
+ end
+ if ((litedramcore_zqcs_executer_counter == 2'd3)) begin
+ litedramcore_cmd_payload_a <= 1'd0;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd0;
+ litedramcore_cmd_payload_we <= 1'd1;
+ end
+ if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
+ litedramcore_cmd_payload_a <= 1'd0;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd0;
+ litedramcore_cmd_payload_we <= 1'd0;
+ litedramcore_zqcs_executer_done <= 1'd1;
+ end
+ if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
+ litedramcore_zqcs_executer_counter <= 1'd0;
+ end else begin
+ if ((litedramcore_zqcs_executer_counter != 1'd0)) begin
+ litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1);
+ end else begin
+ if (litedramcore_zqcs_executer_start) begin
+ litedramcore_zqcs_executer_counter <= 1'd1;
+ end
+ end
+ end
+ litedramcore_refresher_state <= litedramcore_refresher_next_state;
+ if (litedramcore_bankmachine0_row_close) begin
+ litedramcore_bankmachine0_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine0_row_open) begin
+ litedramcore_bankmachine0_row_opened <= 1'd1;
+ litedramcore_bankmachine0_row <= litedramcore_bankmachine0_source_source_payload_addr[21:7];
+ end
+ end
+ if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin
+ litedramcore_bankmachine0_produce <= (litedramcore_bankmachine0_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine0_do_read) begin
+ litedramcore_bankmachine0_consume <= (litedramcore_bankmachine0_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin
+ if ((~litedramcore_bankmachine0_do_read)) begin
+ litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine0_do_read) begin
+ litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine0_pipe_valid_source_valid <= litedramcore_bankmachine0_pipe_valid_sink_valid;
+ litedramcore_bankmachine0_pipe_valid_source_first <= litedramcore_bankmachine0_pipe_valid_sink_first;
+ litedramcore_bankmachine0_pipe_valid_source_last <= litedramcore_bankmachine0_pipe_valid_sink_last;
+ litedramcore_bankmachine0_pipe_valid_source_payload_we <= litedramcore_bankmachine0_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine0_pipe_valid_source_payload_addr <= litedramcore_bankmachine0_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine0_twtpcon_valid) begin
+ litedramcore_bankmachine0_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine0_twtpcon_ready)) begin
+ litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine0_trccon_valid) begin
+ litedramcore_bankmachine0_trccon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine0_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine0_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine0_trccon_ready)) begin
+ litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine0_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine0_trascon_valid) begin
+ litedramcore_bankmachine0_trascon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_bankmachine0_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine0_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine0_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state;
+ if (litedramcore_bankmachine1_row_close) begin
+ litedramcore_bankmachine1_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine1_row_open) begin
+ litedramcore_bankmachine1_row_opened <= 1'd1;
+ litedramcore_bankmachine1_row <= litedramcore_bankmachine1_source_source_payload_addr[21:7];
+ end
+ end
+ if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin
+ litedramcore_bankmachine1_produce <= (litedramcore_bankmachine1_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine1_do_read) begin
+ litedramcore_bankmachine1_consume <= (litedramcore_bankmachine1_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin
+ if ((~litedramcore_bankmachine1_do_read)) begin
+ litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine1_do_read) begin
+ litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine1_pipe_valid_source_valid <= litedramcore_bankmachine1_pipe_valid_sink_valid;
+ litedramcore_bankmachine1_pipe_valid_source_first <= litedramcore_bankmachine1_pipe_valid_sink_first;
+ litedramcore_bankmachine1_pipe_valid_source_last <= litedramcore_bankmachine1_pipe_valid_sink_last;
+ litedramcore_bankmachine1_pipe_valid_source_payload_we <= litedramcore_bankmachine1_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine1_pipe_valid_source_payload_addr <= litedramcore_bankmachine1_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine1_twtpcon_valid) begin
+ litedramcore_bankmachine1_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine1_twtpcon_ready)) begin
+ litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine1_trccon_valid) begin
+ litedramcore_bankmachine1_trccon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine1_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine1_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine1_trccon_ready)) begin
+ litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine1_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine1_trascon_valid) begin
+ litedramcore_bankmachine1_trascon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_bankmachine1_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine1_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine1_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state;
+ if (litedramcore_bankmachine2_row_close) begin
+ litedramcore_bankmachine2_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine2_row_open) begin
+ litedramcore_bankmachine2_row_opened <= 1'd1;
+ litedramcore_bankmachine2_row <= litedramcore_bankmachine2_source_source_payload_addr[21:7];
+ end
+ end
+ if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin
+ litedramcore_bankmachine2_produce <= (litedramcore_bankmachine2_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine2_do_read) begin
+ litedramcore_bankmachine2_consume <= (litedramcore_bankmachine2_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin
+ if ((~litedramcore_bankmachine2_do_read)) begin
+ litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine2_do_read) begin
+ litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine2_pipe_valid_source_valid <= litedramcore_bankmachine2_pipe_valid_sink_valid;
+ litedramcore_bankmachine2_pipe_valid_source_first <= litedramcore_bankmachine2_pipe_valid_sink_first;
+ litedramcore_bankmachine2_pipe_valid_source_last <= litedramcore_bankmachine2_pipe_valid_sink_last;
+ litedramcore_bankmachine2_pipe_valid_source_payload_we <= litedramcore_bankmachine2_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine2_pipe_valid_source_payload_addr <= litedramcore_bankmachine2_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine2_twtpcon_valid) begin
+ litedramcore_bankmachine2_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine2_twtpcon_ready)) begin
+ litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine2_trccon_valid) begin
+ litedramcore_bankmachine2_trccon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine2_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine2_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine2_trccon_ready)) begin
+ litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine2_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine2_trascon_valid) begin
+ litedramcore_bankmachine2_trascon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_bankmachine2_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine2_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine2_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state;
+ if (litedramcore_bankmachine3_row_close) begin
+ litedramcore_bankmachine3_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine3_row_open) begin
+ litedramcore_bankmachine3_row_opened <= 1'd1;
+ litedramcore_bankmachine3_row <= litedramcore_bankmachine3_source_source_payload_addr[21:7];
+ end
+ end
+ if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin
+ litedramcore_bankmachine3_produce <= (litedramcore_bankmachine3_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine3_do_read) begin
+ litedramcore_bankmachine3_consume <= (litedramcore_bankmachine3_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin
+ if ((~litedramcore_bankmachine3_do_read)) begin
+ litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine3_do_read) begin
+ litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine3_pipe_valid_source_valid <= litedramcore_bankmachine3_pipe_valid_sink_valid;
+ litedramcore_bankmachine3_pipe_valid_source_first <= litedramcore_bankmachine3_pipe_valid_sink_first;
+ litedramcore_bankmachine3_pipe_valid_source_last <= litedramcore_bankmachine3_pipe_valid_sink_last;
+ litedramcore_bankmachine3_pipe_valid_source_payload_we <= litedramcore_bankmachine3_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine3_pipe_valid_source_payload_addr <= litedramcore_bankmachine3_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine3_twtpcon_valid) begin
+ litedramcore_bankmachine3_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine3_twtpcon_ready)) begin
+ litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine3_trccon_valid) begin
+ litedramcore_bankmachine3_trccon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine3_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine3_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine3_trccon_ready)) begin
+ litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine3_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine3_trascon_valid) begin
+ litedramcore_bankmachine3_trascon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_bankmachine3_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine3_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine3_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state;
+ if (litedramcore_bankmachine4_row_close) begin
+ litedramcore_bankmachine4_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine4_row_open) begin
+ litedramcore_bankmachine4_row_opened <= 1'd1;
+ litedramcore_bankmachine4_row <= litedramcore_bankmachine4_source_source_payload_addr[21:7];
+ end
+ end
+ if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin
+ litedramcore_bankmachine4_produce <= (litedramcore_bankmachine4_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine4_do_read) begin
+ litedramcore_bankmachine4_consume <= (litedramcore_bankmachine4_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin
+ if ((~litedramcore_bankmachine4_do_read)) begin
+ litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine4_do_read) begin
+ litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine4_pipe_valid_source_valid <= litedramcore_bankmachine4_pipe_valid_sink_valid;
+ litedramcore_bankmachine4_pipe_valid_source_first <= litedramcore_bankmachine4_pipe_valid_sink_first;
+ litedramcore_bankmachine4_pipe_valid_source_last <= litedramcore_bankmachine4_pipe_valid_sink_last;
+ litedramcore_bankmachine4_pipe_valid_source_payload_we <= litedramcore_bankmachine4_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine4_pipe_valid_source_payload_addr <= litedramcore_bankmachine4_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine4_twtpcon_valid) begin
+ litedramcore_bankmachine4_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine4_twtpcon_ready)) begin
+ litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine4_trccon_valid) begin
+ litedramcore_bankmachine4_trccon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine4_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine4_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine4_trccon_ready)) begin
+ litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine4_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine4_trascon_valid) begin
+ litedramcore_bankmachine4_trascon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_bankmachine4_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine4_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine4_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state;
+ if (litedramcore_bankmachine5_row_close) begin
+ litedramcore_bankmachine5_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine5_row_open) begin
+ litedramcore_bankmachine5_row_opened <= 1'd1;
+ litedramcore_bankmachine5_row <= litedramcore_bankmachine5_source_source_payload_addr[21:7];
+ end
+ end
+ if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin
+ litedramcore_bankmachine5_produce <= (litedramcore_bankmachine5_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine5_do_read) begin
+ litedramcore_bankmachine5_consume <= (litedramcore_bankmachine5_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin
+ if ((~litedramcore_bankmachine5_do_read)) begin
+ litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine5_do_read) begin
+ litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine5_pipe_valid_source_valid <= litedramcore_bankmachine5_pipe_valid_sink_valid;
+ litedramcore_bankmachine5_pipe_valid_source_first <= litedramcore_bankmachine5_pipe_valid_sink_first;
+ litedramcore_bankmachine5_pipe_valid_source_last <= litedramcore_bankmachine5_pipe_valid_sink_last;
+ litedramcore_bankmachine5_pipe_valid_source_payload_we <= litedramcore_bankmachine5_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine5_pipe_valid_source_payload_addr <= litedramcore_bankmachine5_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine5_twtpcon_valid) begin
+ litedramcore_bankmachine5_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine5_twtpcon_ready)) begin
+ litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine5_trccon_valid) begin
+ litedramcore_bankmachine5_trccon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine5_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine5_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine5_trccon_ready)) begin
+ litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine5_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine5_trascon_valid) begin
+ litedramcore_bankmachine5_trascon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_bankmachine5_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine5_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine5_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state;
+ if (litedramcore_bankmachine6_row_close) begin
+ litedramcore_bankmachine6_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine6_row_open) begin
+ litedramcore_bankmachine6_row_opened <= 1'd1;
+ litedramcore_bankmachine6_row <= litedramcore_bankmachine6_source_source_payload_addr[21:7];
+ end
+ end
+ if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin
+ litedramcore_bankmachine6_produce <= (litedramcore_bankmachine6_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine6_do_read) begin
+ litedramcore_bankmachine6_consume <= (litedramcore_bankmachine6_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin
+ if ((~litedramcore_bankmachine6_do_read)) begin
+ litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine6_do_read) begin
+ litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine6_pipe_valid_source_valid <= litedramcore_bankmachine6_pipe_valid_sink_valid;
+ litedramcore_bankmachine6_pipe_valid_source_first <= litedramcore_bankmachine6_pipe_valid_sink_first;
+ litedramcore_bankmachine6_pipe_valid_source_last <= litedramcore_bankmachine6_pipe_valid_sink_last;
+ litedramcore_bankmachine6_pipe_valid_source_payload_we <= litedramcore_bankmachine6_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine6_pipe_valid_source_payload_addr <= litedramcore_bankmachine6_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine6_twtpcon_valid) begin
+ litedramcore_bankmachine6_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine6_twtpcon_ready)) begin
+ litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine6_trccon_valid) begin
+ litedramcore_bankmachine6_trccon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine6_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine6_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine6_trccon_ready)) begin
+ litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine6_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine6_trascon_valid) begin
+ litedramcore_bankmachine6_trascon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_bankmachine6_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine6_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine6_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state;
+ if (litedramcore_bankmachine7_row_close) begin
+ litedramcore_bankmachine7_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine7_row_open) begin
+ litedramcore_bankmachine7_row_opened <= 1'd1;
+ litedramcore_bankmachine7_row <= litedramcore_bankmachine7_source_source_payload_addr[21:7];
+ end
+ end
+ if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin
+ litedramcore_bankmachine7_produce <= (litedramcore_bankmachine7_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine7_do_read) begin
+ litedramcore_bankmachine7_consume <= (litedramcore_bankmachine7_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin
+ if ((~litedramcore_bankmachine7_do_read)) begin
+ litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine7_do_read) begin
+ litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine7_pipe_valid_source_valid <= litedramcore_bankmachine7_pipe_valid_sink_valid;
+ litedramcore_bankmachine7_pipe_valid_source_first <= litedramcore_bankmachine7_pipe_valid_sink_first;
+ litedramcore_bankmachine7_pipe_valid_source_last <= litedramcore_bankmachine7_pipe_valid_sink_last;
+ litedramcore_bankmachine7_pipe_valid_source_payload_we <= litedramcore_bankmachine7_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine7_pipe_valid_source_payload_addr <= litedramcore_bankmachine7_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine7_twtpcon_valid) begin
+ litedramcore_bankmachine7_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine7_twtpcon_ready)) begin
+ litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine7_trccon_valid) begin
+ litedramcore_bankmachine7_trccon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine7_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine7_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine7_trccon_ready)) begin
+ litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine7_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine7_trascon_valid) begin
+ litedramcore_bankmachine7_trascon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_bankmachine7_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine7_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine7_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state;
+ if ((~litedramcore_en0)) begin
+ litedramcore_time0 <= 5'd31;
+ end else begin
+ if ((~litedramcore_max_time0)) begin
+ litedramcore_time0 <= (litedramcore_time0 - 1'd1);
+ end
+ end
+ if ((~litedramcore_en1)) begin
+ litedramcore_time1 <= 4'd15;
+ end else begin
+ if ((~litedramcore_max_time1)) begin
+ litedramcore_time1 <= (litedramcore_time1 - 1'd1);
+ end
+ end
+ if (litedramcore_choose_cmd_ce) begin
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 1'd1: begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 2'd2: begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd4: begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd5: begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd6: begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd7: begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ endcase
+ end
+ if (litedramcore_choose_req_ce) begin
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 1'd1: begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 2'd2: begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd4: begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd5: begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd6: begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd7: begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ endcase
+ end
+ litedramcore_dfi_p0_cs_n <= 1'd0;
+ litedramcore_dfi_p0_bank <= array_muxed0;
+ litedramcore_dfi_p0_address <= array_muxed1;
+ litedramcore_dfi_p0_cas_n <= (~array_muxed2);
+ litedramcore_dfi_p0_ras_n <= (~array_muxed3);
+ litedramcore_dfi_p0_we_n <= (~array_muxed4);
+ litedramcore_dfi_p0_rddata_en <= array_muxed5;
+ litedramcore_dfi_p0_wrdata_en <= array_muxed6;
+ litedramcore_dfi_p1_cs_n <= 1'd0;
+ litedramcore_dfi_p1_bank <= array_muxed7;
+ litedramcore_dfi_p1_address <= array_muxed8;
+ litedramcore_dfi_p1_cas_n <= (~array_muxed9);
+ litedramcore_dfi_p1_ras_n <= (~array_muxed10);
+ litedramcore_dfi_p1_we_n <= (~array_muxed11);
+ litedramcore_dfi_p1_rddata_en <= array_muxed12;
+ litedramcore_dfi_p1_wrdata_en <= array_muxed13;
+ litedramcore_dfi_p2_cs_n <= 1'd0;
+ litedramcore_dfi_p2_bank <= array_muxed14;
+ litedramcore_dfi_p2_address <= array_muxed15;
+ litedramcore_dfi_p2_cas_n <= (~array_muxed16);
+ litedramcore_dfi_p2_ras_n <= (~array_muxed17);
+ litedramcore_dfi_p2_we_n <= (~array_muxed18);
+ litedramcore_dfi_p2_rddata_en <= array_muxed19;
+ litedramcore_dfi_p2_wrdata_en <= array_muxed20;
+ litedramcore_dfi_p3_cs_n <= 1'd0;
+ litedramcore_dfi_p3_bank <= array_muxed21;
+ litedramcore_dfi_p3_address <= array_muxed22;
+ litedramcore_dfi_p3_cas_n <= (~array_muxed23);
+ litedramcore_dfi_p3_ras_n <= (~array_muxed24);
+ litedramcore_dfi_p3_we_n <= (~array_muxed25);
+ litedramcore_dfi_p3_rddata_en <= array_muxed26;
+ litedramcore_dfi_p3_wrdata_en <= array_muxed27;
+ if (litedramcore_trrdcon_valid) begin
+ litedramcore_trrdcon_count <= 1'd1;
+ if (1'd0) begin
+ litedramcore_trrdcon_ready <= 1'd1;
+ end else begin
+ litedramcore_trrdcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_trrdcon_ready)) begin
+ litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1);
+ if ((litedramcore_trrdcon_count == 1'd1)) begin
+ litedramcore_trrdcon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid};
+ if ((litedramcore_tfawcon_count < 3'd4)) begin
+ if ((litedramcore_tfawcon_count == 2'd3)) begin
+ litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid);
+ end else begin
+ litedramcore_tfawcon_ready <= 1'd1;
+ end
+ end
+ if (litedramcore_tccdcon_valid) begin
+ litedramcore_tccdcon_count <= 1'd0;
+ if (1'd1) begin
+ litedramcore_tccdcon_ready <= 1'd1;
+ end else begin
+ litedramcore_tccdcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_tccdcon_ready)) begin
+ litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1);
+ if ((litedramcore_tccdcon_count == 1'd1)) begin
+ litedramcore_tccdcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_twtrcon_valid) begin
+ litedramcore_twtrcon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_twtrcon_ready <= 1'd1;
+ end else begin
+ litedramcore_twtrcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_twtrcon_ready)) begin
+ litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1);
+ if ((litedramcore_twtrcon_count == 1'd1)) begin
+ litedramcore_twtrcon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state;
+ litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready));
+ litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0;
+ litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid));
+ litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0;
+ litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1;
+ litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2;
+ litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3;
+ litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4;
+ litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5;
+ litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6;
+ litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7;
+ litedramcore_state <= litedramcore_next_state;
+ if (litedramcore_dat_w_next_value_ce0) begin
+ litedramcore_dat_w <= litedramcore_dat_w_next_value0;
+ end
+ if (litedramcore_adr_next_value_ce1) begin
+ litedramcore_adr <= litedramcore_adr_next_value1;
+ end
+ if (litedramcore_we_next_value_ce2) begin
+ litedramcore_we <= litedramcore_we_next_value2;
+ end
+ interface0_bank_bus_dat_r <= 1'd0;
+ if (csrbank0_sel) begin
+ case (interface0_bank_bus_adr[8:0])
+ 1'd0: begin
+ interface0_bank_bus_dat_r <= csrbank0_init_done0_w;
+ end
+ 1'd1: begin
+ interface0_bank_bus_dat_r <= csrbank0_init_error0_w;
+ end
+ endcase
+ end
+ if (csrbank0_init_done0_re) begin
+ init_done_storage <= csrbank0_init_done0_r;
+ end
+ init_done_re <= csrbank0_init_done0_re;
+ if (csrbank0_init_error0_re) begin
+ init_error_storage <= csrbank0_init_error0_r;
+ end
+ init_error_re <= csrbank0_init_error0_re;
+ interface1_bank_bus_dat_r <= 1'd0;
+ if (csrbank1_sel) begin
+ case (interface1_bank_bus_adr[8:0])
+ 1'd0: begin
+ interface1_bank_bus_dat_r <= csrbank1_rst0_w;
+ end
+ 1'd1: begin
+ interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w;
+ end
+ 2'd2: begin
+ interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w;
+ end
+ 2'd3: begin
+ interface1_bank_bus_dat_r <= csrbank1_wlevel_en0_w;
+ end
+ 3'd4: begin
+ interface1_bank_bus_dat_r <= k7ddrphy_wlevel_strobe_w;
+ end
+ 3'd5: begin
+ interface1_bank_bus_dat_r <= k7ddrphy_cdly_rst_w;
+ end
+ 3'd6: begin
+ interface1_bank_bus_dat_r <= k7ddrphy_cdly_inc_w;
+ end
+ 3'd7: begin
+ interface1_bank_bus_dat_r <= k7ddrphy_rdly_dq_rst_w;
+ end
+ 4'd8: begin
+ interface1_bank_bus_dat_r <= k7ddrphy_rdly_dq_inc_w;
+ end
+ 4'd9: begin
+ interface1_bank_bus_dat_r <= k7ddrphy_rdly_dq_bitslip_rst_w;
+ end
+ 4'd10: begin
+ interface1_bank_bus_dat_r <= k7ddrphy_rdly_dq_bitslip_w;
+ end
+ 4'd11: begin
+ interface1_bank_bus_dat_r <= k7ddrphy_wdly_dq_rst_w;
+ end
+ 4'd12: begin
+ interface1_bank_bus_dat_r <= k7ddrphy_wdly_dq_inc_w;
+ end
+ 4'd13: begin
+ interface1_bank_bus_dat_r <= k7ddrphy_wdly_dqs_rst_w;
+ end
+ 4'd14: begin
+ interface1_bank_bus_dat_r <= k7ddrphy_wdly_dqs_inc_w;
+ end
+ 4'd15: begin
+ interface1_bank_bus_dat_r <= k7ddrphy_wdly_dq_bitslip_rst_w;
+ end
+ 5'd16: begin
+ interface1_bank_bus_dat_r <= k7ddrphy_wdly_dq_bitslip_w;
+ end
+ 5'd17: begin
+ interface1_bank_bus_dat_r <= csrbank1_rdphase0_w;
+ end
+ 5'd18: begin
+ interface1_bank_bus_dat_r <= csrbank1_wrphase0_w;
+ end
+ endcase
+ end
+ if (csrbank1_rst0_re) begin
+ k7ddrphy_rst_storage <= csrbank1_rst0_r;
+ end
+ k7ddrphy_rst_re <= csrbank1_rst0_re;
+ if (csrbank1_dly_sel0_re) begin
+ k7ddrphy_dly_sel_storage[3:0] <= csrbank1_dly_sel0_r;
+ end
+ k7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re;
+ if (csrbank1_half_sys8x_taps0_re) begin
+ k7ddrphy_half_sys8x_taps_storage[4:0] <= csrbank1_half_sys8x_taps0_r;
+ end
+ k7ddrphy_half_sys8x_taps_re <= csrbank1_half_sys8x_taps0_re;
+ if (csrbank1_wlevel_en0_re) begin
+ k7ddrphy_wlevel_en_storage <= csrbank1_wlevel_en0_r;
+ end
+ k7ddrphy_wlevel_en_re <= csrbank1_wlevel_en0_re;
+ if (csrbank1_rdphase0_re) begin
+ k7ddrphy_rdphase_storage[1:0] <= csrbank1_rdphase0_r;
+ end
+ k7ddrphy_rdphase_re <= csrbank1_rdphase0_re;
+ if (csrbank1_wrphase0_re) begin
+ k7ddrphy_wrphase_storage[1:0] <= csrbank1_wrphase0_r;
+ end
+ k7ddrphy_wrphase_re <= csrbank1_wrphase0_re;
+ interface2_bank_bus_dat_r <= 1'd0;
+ if (csrbank2_sel) begin
+ case (interface2_bank_bus_adr[8:0])
+ 1'd0: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w;
+ end
+ 1'd1: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w;
+ end
+ 2'd2: begin
+ interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w;
+ end
+ 2'd3: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w;
+ end
+ 3'd4: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w;
+ end
+ 3'd5: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata1_w;
+ end
+ 3'd6: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w;
+ end
+ 3'd7: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata1_w;
+ end
+ 4'd8: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata0_w;
+ end
+ 4'd9: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w;
+ end
+ 4'd10: begin
+ interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w;
+ end
+ 4'd11: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w;
+ end
+ 4'd12: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w;
+ end
+ 4'd13: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata1_w;
+ end
+ 4'd14: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w;
+ end
+ 4'd15: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata1_w;
+ end
+ 5'd16: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata0_w;
+ end
+ 5'd17: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w;
+ end
+ 5'd18: begin
+ interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w;
+ end
+ 5'd19: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w;
+ end
+ 5'd20: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w;
+ end
+ 5'd21: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata1_w;
+ end
+ 5'd22: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w;
+ end
+ 5'd23: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata1_w;
+ end
+ 5'd24: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata0_w;
+ end
+ 5'd25: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w;
+ end
+ 5'd26: begin
+ interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w;
+ end
+ 5'd27: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w;
+ end
+ 5'd28: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w;
+ end
+ 5'd29: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata1_w;
+ end
+ 5'd30: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w;
+ end
+ 5'd31: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata1_w;
+ end
+ 6'd32: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata0_w;
+ end
+ endcase
+ end
+ if (csrbank2_dfii_control0_re) begin
+ litedramcore_storage[3:0] <= csrbank2_dfii_control0_r;
+ end
+ litedramcore_re <= csrbank2_dfii_control0_re;
+ if (csrbank2_dfii_pi0_command0_re) begin
+ litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r;
+ end
+ litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re;
+ if (csrbank2_dfii_pi0_address0_re) begin
+ litedramcore_phaseinjector0_address_storage[14:0] <= csrbank2_dfii_pi0_address0_r;
+ end
+ litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re;
+ if (csrbank2_dfii_pi0_baddress0_re) begin
+ litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r;
+ end
+ litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re;
+ if (csrbank2_dfii_pi0_wrdata1_re) begin
+ litedramcore_phaseinjector0_wrdata_storage[63:32] <= csrbank2_dfii_pi0_wrdata1_r;
+ end
+ if (csrbank2_dfii_pi0_wrdata0_re) begin
+ litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r;
+ end
+ litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re;
+ litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata0_re;
+ if (csrbank2_dfii_pi1_command0_re) begin
+ litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r;
+ end
+ litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re;
+ if (csrbank2_dfii_pi1_address0_re) begin
+ litedramcore_phaseinjector1_address_storage[14:0] <= csrbank2_dfii_pi1_address0_r;
+ end
+ litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re;
+ if (csrbank2_dfii_pi1_baddress0_re) begin
+ litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r;
+ end
+ litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re;
+ if (csrbank2_dfii_pi1_wrdata1_re) begin
+ litedramcore_phaseinjector1_wrdata_storage[63:32] <= csrbank2_dfii_pi1_wrdata1_r;
+ end
+ if (csrbank2_dfii_pi1_wrdata0_re) begin
+ litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r;
+ end
+ litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re;
+ litedramcore_phaseinjector1_rddata_re <= csrbank2_dfii_pi1_rddata0_re;
+ if (csrbank2_dfii_pi2_command0_re) begin
+ litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r;
+ end
+ litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re;
+ if (csrbank2_dfii_pi2_address0_re) begin
+ litedramcore_phaseinjector2_address_storage[14:0] <= csrbank2_dfii_pi2_address0_r;
+ end
+ litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re;
+ if (csrbank2_dfii_pi2_baddress0_re) begin
+ litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r;
+ end
+ litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re;
+ if (csrbank2_dfii_pi2_wrdata1_re) begin
+ litedramcore_phaseinjector2_wrdata_storage[63:32] <= csrbank2_dfii_pi2_wrdata1_r;
+ end
+ if (csrbank2_dfii_pi2_wrdata0_re) begin
+ litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r;
+ end
+ litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re;
+ litedramcore_phaseinjector2_rddata_re <= csrbank2_dfii_pi2_rddata0_re;
+ if (csrbank2_dfii_pi3_command0_re) begin
+ litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r;
+ end
+ litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re;
+ if (csrbank2_dfii_pi3_address0_re) begin
+ litedramcore_phaseinjector3_address_storage[14:0] <= csrbank2_dfii_pi3_address0_r;
+ end
+ litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re;
+ if (csrbank2_dfii_pi3_baddress0_re) begin
+ litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r;
+ end
+ litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re;
+ if (csrbank2_dfii_pi3_wrdata1_re) begin
+ litedramcore_phaseinjector3_wrdata_storage[63:32] <= csrbank2_dfii_pi3_wrdata1_r;
+ end
+ if (csrbank2_dfii_pi3_wrdata0_re) begin
+ litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r;
+ end
+ litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re;
+ litedramcore_phaseinjector3_rddata_re <= csrbank2_dfii_pi3_rddata0_re;
+ if (sys_rst) begin
+ k7ddrphy_rst_storage <= 1'd0;
+ k7ddrphy_rst_re <= 1'd0;
+ k7ddrphy_dly_sel_storage <= 4'd0;
+ k7ddrphy_dly_sel_re <= 1'd0;
+ k7ddrphy_half_sys8x_taps_storage <= 5'd8;
+ k7ddrphy_half_sys8x_taps_re <= 1'd0;
+ k7ddrphy_wlevel_en_storage <= 1'd0;
+ k7ddrphy_wlevel_en_re <= 1'd0;
+ k7ddrphy_rdphase_storage <= 2'd1;
+ k7ddrphy_rdphase_re <= 1'd0;
+ k7ddrphy_wrphase_storage <= 2'd2;
+ k7ddrphy_wrphase_re <= 1'd0;
+ k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
+ k7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
+ k7ddrphy_bitslip0_value0 <= 3'd7;
+ k7ddrphy_bitslip1_value0 <= 3'd7;
+ k7ddrphy_bitslip2_value0 <= 3'd7;
+ k7ddrphy_bitslip3_value0 <= 3'd7;
+ k7ddrphy_bitslip0_value1 <= 3'd7;
+ k7ddrphy_bitslip1_value1 <= 3'd7;
+ k7ddrphy_bitslip2_value1 <= 3'd7;
+ k7ddrphy_bitslip3_value1 <= 3'd7;
+ k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
+ k7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
+ k7ddrphy_bitslip0_value2 <= 3'd7;
+ k7ddrphy_bitslip0_value3 <= 3'd7;
+ k7ddrphy_bitslip1_value2 <= 3'd7;
+ k7ddrphy_bitslip1_value3 <= 3'd7;
+ k7ddrphy_bitslip2_value2 <= 3'd7;
+ k7ddrphy_bitslip2_value3 <= 3'd7;
+ k7ddrphy_bitslip3_value2 <= 3'd7;
+ k7ddrphy_bitslip3_value3 <= 3'd7;
+ k7ddrphy_bitslip4_value0 <= 3'd7;
+ k7ddrphy_bitslip4_value1 <= 3'd7;
+ k7ddrphy_bitslip5_value0 <= 3'd7;
+ k7ddrphy_bitslip5_value1 <= 3'd7;
+ k7ddrphy_bitslip6_value0 <= 3'd7;
+ k7ddrphy_bitslip6_value1 <= 3'd7;
+ k7ddrphy_bitslip7_value0 <= 3'd7;
+ k7ddrphy_bitslip7_value1 <= 3'd7;
+ k7ddrphy_bitslip8_value0 <= 3'd7;
+ k7ddrphy_bitslip8_value1 <= 3'd7;
+ k7ddrphy_bitslip9_value0 <= 3'd7;
+ k7ddrphy_bitslip9_value1 <= 3'd7;
+ k7ddrphy_bitslip10_value0 <= 3'd7;
+ k7ddrphy_bitslip10_value1 <= 3'd7;
+ k7ddrphy_bitslip11_value0 <= 3'd7;
+ k7ddrphy_bitslip11_value1 <= 3'd7;
+ k7ddrphy_bitslip12_value0 <= 3'd7;
+ k7ddrphy_bitslip12_value1 <= 3'd7;
+ k7ddrphy_bitslip13_value0 <= 3'd7;
+ k7ddrphy_bitslip13_value1 <= 3'd7;
+ k7ddrphy_bitslip14_value0 <= 3'd7;
+ k7ddrphy_bitslip14_value1 <= 3'd7;
+ k7ddrphy_bitslip15_value0 <= 3'd7;
+ k7ddrphy_bitslip15_value1 <= 3'd7;
+ k7ddrphy_bitslip16_value0 <= 3'd7;
+ k7ddrphy_bitslip16_value1 <= 3'd7;
+ k7ddrphy_bitslip17_value0 <= 3'd7;
+ k7ddrphy_bitslip17_value1 <= 3'd7;
+ k7ddrphy_bitslip18_value0 <= 3'd7;
+ k7ddrphy_bitslip18_value1 <= 3'd7;
+ k7ddrphy_bitslip19_value0 <= 3'd7;
+ k7ddrphy_bitslip19_value1 <= 3'd7;
+ k7ddrphy_bitslip20_value0 <= 3'd7;
+ k7ddrphy_bitslip20_value1 <= 3'd7;
+ k7ddrphy_bitslip21_value0 <= 3'd7;
+ k7ddrphy_bitslip21_value1 <= 3'd7;
+ k7ddrphy_bitslip22_value0 <= 3'd7;
+ k7ddrphy_bitslip22_value1 <= 3'd7;
+ k7ddrphy_bitslip23_value0 <= 3'd7;
+ k7ddrphy_bitslip23_value1 <= 3'd7;
+ k7ddrphy_bitslip24_value0 <= 3'd7;
+ k7ddrphy_bitslip24_value1 <= 3'd7;
+ k7ddrphy_bitslip25_value0 <= 3'd7;
+ k7ddrphy_bitslip25_value1 <= 3'd7;
+ k7ddrphy_bitslip26_value0 <= 3'd7;
+ k7ddrphy_bitslip26_value1 <= 3'd7;
+ k7ddrphy_bitslip27_value0 <= 3'd7;
+ k7ddrphy_bitslip27_value1 <= 3'd7;
+ k7ddrphy_bitslip28_value0 <= 3'd7;
+ k7ddrphy_bitslip28_value1 <= 3'd7;
+ k7ddrphy_bitslip29_value0 <= 3'd7;
+ k7ddrphy_bitslip29_value1 <= 3'd7;
+ k7ddrphy_bitslip30_value0 <= 3'd7;
+ k7ddrphy_bitslip30_value1 <= 3'd7;
+ k7ddrphy_bitslip31_value0 <= 3'd7;
+ k7ddrphy_bitslip31_value1 <= 3'd7;
+ k7ddrphy_rddata_en_tappeddelayline0 <= 1'd0;
+ k7ddrphy_rddata_en_tappeddelayline1 <= 1'd0;
+ k7ddrphy_rddata_en_tappeddelayline2 <= 1'd0;
+ k7ddrphy_rddata_en_tappeddelayline3 <= 1'd0;
+ k7ddrphy_rddata_en_tappeddelayline4 <= 1'd0;
+ k7ddrphy_rddata_en_tappeddelayline5 <= 1'd0;
+ k7ddrphy_rddata_en_tappeddelayline6 <= 1'd0;
+ k7ddrphy_rddata_en_tappeddelayline7 <= 1'd0;
+ k7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0;
+ k7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0;
+ k7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0;
+ litedramcore_storage <= 4'd1;
+ litedramcore_re <= 1'd0;
+ litedramcore_phaseinjector0_command_storage <= 6'd0;
+ litedramcore_phaseinjector0_command_re <= 1'd0;
+ litedramcore_phaseinjector0_address_re <= 1'd0;
+ litedramcore_phaseinjector0_baddress_re <= 1'd0;
+ litedramcore_phaseinjector0_wrdata_re <= 1'd0;
+ litedramcore_phaseinjector0_rddata_status <= 64'd0;
+ litedramcore_phaseinjector0_rddata_re <= 1'd0;
+ litedramcore_phaseinjector1_command_storage <= 6'd0;
+ litedramcore_phaseinjector1_command_re <= 1'd0;
+ litedramcore_phaseinjector1_address_re <= 1'd0;
+ litedramcore_phaseinjector1_baddress_re <= 1'd0;
+ litedramcore_phaseinjector1_wrdata_re <= 1'd0;
+ litedramcore_phaseinjector1_rddata_status <= 64'd0;
+ litedramcore_phaseinjector1_rddata_re <= 1'd0;
+ litedramcore_phaseinjector2_command_storage <= 6'd0;
+ litedramcore_phaseinjector2_command_re <= 1'd0;
+ litedramcore_phaseinjector2_address_re <= 1'd0;
+ litedramcore_phaseinjector2_baddress_re <= 1'd0;
+ litedramcore_phaseinjector2_wrdata_re <= 1'd0;
+ litedramcore_phaseinjector2_rddata_status <= 64'd0;
+ litedramcore_phaseinjector2_rddata_re <= 1'd0;
+ litedramcore_phaseinjector3_command_storage <= 6'd0;
+ litedramcore_phaseinjector3_command_re <= 1'd0;
+ litedramcore_phaseinjector3_address_re <= 1'd0;
+ litedramcore_phaseinjector3_baddress_re <= 1'd0;
+ litedramcore_phaseinjector3_wrdata_re <= 1'd0;
+ litedramcore_phaseinjector3_rddata_status <= 64'd0;
+ litedramcore_phaseinjector3_rddata_re <= 1'd0;
+ litedramcore_dfi_p0_address <= 15'd0;
+ litedramcore_dfi_p0_bank <= 3'd0;
+ litedramcore_dfi_p0_cas_n <= 1'd1;
+ litedramcore_dfi_p0_cs_n <= 1'd1;
+ litedramcore_dfi_p0_ras_n <= 1'd1;
+ litedramcore_dfi_p0_we_n <= 1'd1;
+ litedramcore_dfi_p0_wrdata_en <= 1'd0;
+ litedramcore_dfi_p0_rddata_en <= 1'd0;
+ litedramcore_dfi_p1_address <= 15'd0;
+ litedramcore_dfi_p1_bank <= 3'd0;
+ litedramcore_dfi_p1_cas_n <= 1'd1;
+ litedramcore_dfi_p1_cs_n <= 1'd1;
+ litedramcore_dfi_p1_ras_n <= 1'd1;
+ litedramcore_dfi_p1_we_n <= 1'd1;
+ litedramcore_dfi_p1_wrdata_en <= 1'd0;
+ litedramcore_dfi_p1_rddata_en <= 1'd0;
+ litedramcore_dfi_p2_address <= 15'd0;
+ litedramcore_dfi_p2_bank <= 3'd0;
+ litedramcore_dfi_p2_cas_n <= 1'd1;
+ litedramcore_dfi_p2_cs_n <= 1'd1;
+ litedramcore_dfi_p2_ras_n <= 1'd1;
+ litedramcore_dfi_p2_we_n <= 1'd1;
+ litedramcore_dfi_p2_wrdata_en <= 1'd0;
+ litedramcore_dfi_p2_rddata_en <= 1'd0;
+ litedramcore_dfi_p3_address <= 15'd0;
+ litedramcore_dfi_p3_bank <= 3'd0;
+ litedramcore_dfi_p3_cas_n <= 1'd1;
+ litedramcore_dfi_p3_cs_n <= 1'd1;
+ litedramcore_dfi_p3_ras_n <= 1'd1;
+ litedramcore_dfi_p3_we_n <= 1'd1;
+ litedramcore_dfi_p3_wrdata_en <= 1'd0;
+ litedramcore_dfi_p3_rddata_en <= 1'd0;
+ litedramcore_cmd_payload_a <= 15'd0;
+ litedramcore_cmd_payload_ba <= 3'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd0;
+ litedramcore_cmd_payload_we <= 1'd0;
+ litedramcore_timer_count1 <= 10'd781;
+ litedramcore_postponer_req_o <= 1'd0;
+ litedramcore_postponer_count <= 1'd0;
+ litedramcore_sequencer_done1 <= 1'd0;
+ litedramcore_sequencer_counter <= 6'd0;
+ litedramcore_sequencer_count <= 1'd0;
+ litedramcore_zqcs_timer_count1 <= 27'd99999999;
+ litedramcore_zqcs_executer_done <= 1'd0;
+ litedramcore_zqcs_executer_counter <= 5'd0;
+ litedramcore_bankmachine0_level <= 5'd0;
+ litedramcore_bankmachine0_produce <= 4'd0;
+ litedramcore_bankmachine0_consume <= 4'd0;
+ litedramcore_bankmachine0_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine0_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine0_pipe_valid_source_payload_addr <= 22'd0;
+ litedramcore_bankmachine0_row <= 15'd0;
+ litedramcore_bankmachine0_row_opened <= 1'd0;
+ litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine0_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine0_trccon_ready <= 1'd0;
+ litedramcore_bankmachine0_trccon_count <= 3'd0;
+ litedramcore_bankmachine0_trascon_ready <= 1'd0;
+ litedramcore_bankmachine0_trascon_count <= 3'd0;
+ litedramcore_bankmachine1_level <= 5'd0;
+ litedramcore_bankmachine1_produce <= 4'd0;
+ litedramcore_bankmachine1_consume <= 4'd0;
+ litedramcore_bankmachine1_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine1_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine1_pipe_valid_source_payload_addr <= 22'd0;
+ litedramcore_bankmachine1_row <= 15'd0;
+ litedramcore_bankmachine1_row_opened <= 1'd0;
+ litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine1_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine1_trccon_ready <= 1'd0;
+ litedramcore_bankmachine1_trccon_count <= 3'd0;
+ litedramcore_bankmachine1_trascon_ready <= 1'd0;
+ litedramcore_bankmachine1_trascon_count <= 3'd0;
+ litedramcore_bankmachine2_level <= 5'd0;
+ litedramcore_bankmachine2_produce <= 4'd0;
+ litedramcore_bankmachine2_consume <= 4'd0;
+ litedramcore_bankmachine2_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine2_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine2_pipe_valid_source_payload_addr <= 22'd0;
+ litedramcore_bankmachine2_row <= 15'd0;
+ litedramcore_bankmachine2_row_opened <= 1'd0;
+ litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine2_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine2_trccon_ready <= 1'd0;
+ litedramcore_bankmachine2_trccon_count <= 3'd0;
+ litedramcore_bankmachine2_trascon_ready <= 1'd0;
+ litedramcore_bankmachine2_trascon_count <= 3'd0;
+ litedramcore_bankmachine3_level <= 5'd0;
+ litedramcore_bankmachine3_produce <= 4'd0;
+ litedramcore_bankmachine3_consume <= 4'd0;
+ litedramcore_bankmachine3_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine3_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine3_pipe_valid_source_payload_addr <= 22'd0;
+ litedramcore_bankmachine3_row <= 15'd0;
+ litedramcore_bankmachine3_row_opened <= 1'd0;
+ litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine3_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine3_trccon_ready <= 1'd0;
+ litedramcore_bankmachine3_trccon_count <= 3'd0;
+ litedramcore_bankmachine3_trascon_ready <= 1'd0;
+ litedramcore_bankmachine3_trascon_count <= 3'd0;
+ litedramcore_bankmachine4_level <= 5'd0;
+ litedramcore_bankmachine4_produce <= 4'd0;
+ litedramcore_bankmachine4_consume <= 4'd0;
+ litedramcore_bankmachine4_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine4_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine4_pipe_valid_source_payload_addr <= 22'd0;
+ litedramcore_bankmachine4_row <= 15'd0;
+ litedramcore_bankmachine4_row_opened <= 1'd0;
+ litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine4_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine4_trccon_ready <= 1'd0;
+ litedramcore_bankmachine4_trccon_count <= 3'd0;
+ litedramcore_bankmachine4_trascon_ready <= 1'd0;
+ litedramcore_bankmachine4_trascon_count <= 3'd0;
+ litedramcore_bankmachine5_level <= 5'd0;
+ litedramcore_bankmachine5_produce <= 4'd0;
+ litedramcore_bankmachine5_consume <= 4'd0;
+ litedramcore_bankmachine5_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine5_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine5_pipe_valid_source_payload_addr <= 22'd0;
+ litedramcore_bankmachine5_row <= 15'd0;
+ litedramcore_bankmachine5_row_opened <= 1'd0;
+ litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine5_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine5_trccon_ready <= 1'd0;
+ litedramcore_bankmachine5_trccon_count <= 3'd0;
+ litedramcore_bankmachine5_trascon_ready <= 1'd0;
+ litedramcore_bankmachine5_trascon_count <= 3'd0;
+ litedramcore_bankmachine6_level <= 5'd0;
+ litedramcore_bankmachine6_produce <= 4'd0;
+ litedramcore_bankmachine6_consume <= 4'd0;
+ litedramcore_bankmachine6_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine6_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine6_pipe_valid_source_payload_addr <= 22'd0;
+ litedramcore_bankmachine6_row <= 15'd0;
+ litedramcore_bankmachine6_row_opened <= 1'd0;
+ litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine6_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine6_trccon_ready <= 1'd0;
+ litedramcore_bankmachine6_trccon_count <= 3'd0;
+ litedramcore_bankmachine6_trascon_ready <= 1'd0;
+ litedramcore_bankmachine6_trascon_count <= 3'd0;
+ litedramcore_bankmachine7_level <= 5'd0;
+ litedramcore_bankmachine7_produce <= 4'd0;
+ litedramcore_bankmachine7_consume <= 4'd0;
+ litedramcore_bankmachine7_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine7_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine7_pipe_valid_source_payload_addr <= 22'd0;
+ litedramcore_bankmachine7_row <= 15'd0;
+ litedramcore_bankmachine7_row_opened <= 1'd0;
+ litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine7_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine7_trccon_ready <= 1'd0;
+ litedramcore_bankmachine7_trccon_count <= 3'd0;
+ litedramcore_bankmachine7_trascon_ready <= 1'd0;
+ litedramcore_bankmachine7_trascon_count <= 3'd0;
+ litedramcore_choose_cmd_grant <= 3'd0;
+ litedramcore_choose_req_grant <= 3'd0;
+ litedramcore_trrdcon_ready <= 1'd0;
+ litedramcore_trrdcon_count <= 1'd0;
+ litedramcore_tfawcon_ready <= 1'd1;
+ litedramcore_tfawcon_window <= 5'd0;
+ litedramcore_tccdcon_ready <= 1'd0;
+ litedramcore_tccdcon_count <= 1'd0;
+ litedramcore_twtrcon_ready <= 1'd0;
+ litedramcore_twtrcon_count <= 3'd0;
+ litedramcore_time0 <= 5'd0;
+ litedramcore_time1 <= 4'd0;
+ init_done_storage <= 1'd0;
+ init_done_re <= 1'd0;
+ init_error_storage <= 1'd0;
+ init_error_re <= 1'd0;
+ litedramcore_we <= 1'd0;
+ litedramcore_refresher_state <= 2'd0;
+ litedramcore_bankmachine0_state <= 4'd0;
+ litedramcore_bankmachine1_state <= 4'd0;
+ litedramcore_bankmachine2_state <= 4'd0;
+ litedramcore_bankmachine3_state <= 4'd0;
+ litedramcore_bankmachine4_state <= 4'd0;
+ litedramcore_bankmachine5_state <= 4'd0;
+ litedramcore_bankmachine6_state <= 4'd0;
+ litedramcore_bankmachine7_state <= 4'd0;
+ litedramcore_multiplexer_state <= 4'd0;
+ litedramcore_new_master_wdata_ready0 <= 1'd0;
+ litedramcore_new_master_wdata_ready1 <= 1'd0;
+ litedramcore_new_master_rdata_valid0 <= 1'd0;
+ litedramcore_new_master_rdata_valid1 <= 1'd0;
+ litedramcore_new_master_rdata_valid2 <= 1'd0;
+ litedramcore_new_master_rdata_valid3 <= 1'd0;
+ litedramcore_new_master_rdata_valid4 <= 1'd0;
+ litedramcore_new_master_rdata_valid5 <= 1'd0;
+ litedramcore_new_master_rdata_valid6 <= 1'd0;
+ litedramcore_new_master_rdata_valid7 <= 1'd0;
+ litedramcore_new_master_rdata_valid8 <= 1'd0;
+ litedramcore_state <= 2'd0;
+ end
end
reg [24:0] storage[0:15];
reg [24:0] storage_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we)
- storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
- storage_dat0 <= storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine0_wrport_we)
+ storage[litedramcore_bankmachine0_wrport_adr] <= litedramcore_bankmachine0_wrport_dat_w;
+ storage_dat0 <= storage[litedramcore_bankmachine0_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = storage_dat0;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine0_wrport_dat_r = storage_dat0;
+assign litedramcore_bankmachine0_rdport_dat_r = storage[litedramcore_bankmachine0_rdport_adr];
//------------------------------------------------------------------------------
reg [24:0] storage_1[0:15];
reg [24:0] storage_1_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we)
- storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
- storage_1_dat0 <= storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine1_wrport_we)
+ storage_1[litedramcore_bankmachine1_wrport_adr] <= litedramcore_bankmachine1_wrport_dat_w;
+ storage_1_dat0 <= storage_1[litedramcore_bankmachine1_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = storage_1_dat0;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine1_wrport_dat_r = storage_1_dat0;
+assign litedramcore_bankmachine1_rdport_dat_r = storage_1[litedramcore_bankmachine1_rdport_adr];
//------------------------------------------------------------------------------
reg [24:0] storage_2[0:15];
reg [24:0] storage_2_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we)
- storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
- storage_2_dat0 <= storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine2_wrport_we)
+ storage_2[litedramcore_bankmachine2_wrport_adr] <= litedramcore_bankmachine2_wrport_dat_w;
+ storage_2_dat0 <= storage_2[litedramcore_bankmachine2_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = storage_2_dat0;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine2_wrport_dat_r = storage_2_dat0;
+assign litedramcore_bankmachine2_rdport_dat_r = storage_2[litedramcore_bankmachine2_rdport_adr];
//------------------------------------------------------------------------------
reg [24:0] storage_3[0:15];
reg [24:0] storage_3_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we)
- storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
- storage_3_dat0 <= storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine3_wrport_we)
+ storage_3[litedramcore_bankmachine3_wrport_adr] <= litedramcore_bankmachine3_wrport_dat_w;
+ storage_3_dat0 <= storage_3[litedramcore_bankmachine3_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = storage_3_dat0;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine3_wrport_dat_r = storage_3_dat0;
+assign litedramcore_bankmachine3_rdport_dat_r = storage_3[litedramcore_bankmachine3_rdport_adr];
//------------------------------------------------------------------------------
reg [24:0] storage_4[0:15];
reg [24:0] storage_4_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we)
- storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
- storage_4_dat0 <= storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine4_wrport_we)
+ storage_4[litedramcore_bankmachine4_wrport_adr] <= litedramcore_bankmachine4_wrport_dat_w;
+ storage_4_dat0 <= storage_4[litedramcore_bankmachine4_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = storage_4_dat0;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine4_wrport_dat_r = storage_4_dat0;
+assign litedramcore_bankmachine4_rdport_dat_r = storage_4[litedramcore_bankmachine4_rdport_adr];
//------------------------------------------------------------------------------
reg [24:0] storage_5[0:15];
reg [24:0] storage_5_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we)
- storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
- storage_5_dat0 <= storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine5_wrport_we)
+ storage_5[litedramcore_bankmachine5_wrport_adr] <= litedramcore_bankmachine5_wrport_dat_w;
+ storage_5_dat0 <= storage_5[litedramcore_bankmachine5_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = storage_5_dat0;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine5_wrport_dat_r = storage_5_dat0;
+assign litedramcore_bankmachine5_rdport_dat_r = storage_5[litedramcore_bankmachine5_rdport_adr];
//------------------------------------------------------------------------------
reg [24:0] storage_6[0:15];
reg [24:0] storage_6_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we)
- storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
- storage_6_dat0 <= storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine6_wrport_we)
+ storage_6[litedramcore_bankmachine6_wrport_adr] <= litedramcore_bankmachine6_wrport_dat_w;
+ storage_6_dat0 <= storage_6[litedramcore_bankmachine6_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = storage_6_dat0;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine6_wrport_dat_r = storage_6_dat0;
+assign litedramcore_bankmachine6_rdport_dat_r = storage_6[litedramcore_bankmachine6_rdport_adr];
//------------------------------------------------------------------------------
reg [24:0] storage_7[0:15];
reg [24:0] storage_7_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we)
- storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
- storage_7_dat0 <= storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine7_wrport_we)
+ storage_7[litedramcore_bankmachine7_wrport_adr] <= litedramcore_bankmachine7_wrport_dat_w;
+ storage_7_dat0 <= storage_7[litedramcore_bankmachine7_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = storage_7_dat0;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine7_wrport_dat_r = storage_7_dat0;
+assign litedramcore_bankmachine7_rdport_dat_r = storage_7[litedramcore_bankmachine7_rdport_adr];
FDCE FDCE(
.LOCKED(locked)
);
-(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
+(* ars_ff1 = "true", async_reg = "true" *)
+FDPE #(
.INIT(1'd1)
) FDPE (
.C(iodelay_clk),
.Q(xilinxasyncresetsynchronizerimpl0_rst_meta)
);
-(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
+(* ars_ff2 = "true", async_reg = "true" *)
+FDPE #(
.INIT(1'd1)
) FDPE_1 (
.C(iodelay_clk),
.Q(iodelay_rst)
);
-(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
+(* ars_ff1 = "true", async_reg = "true" *)
+FDPE #(
.INIT(1'd1)
) FDPE_2 (
.C(sys_clk),
.Q(xilinxasyncresetsynchronizerimpl1_rst_meta)
);
-(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
+(* ars_ff2 = "true", async_reg = "true" *)
+FDPE #(
.INIT(1'd1)
) FDPE_3 (
.C(sys_clk),
.Q(sys_rst)
);
-(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
+(* ars_ff1 = "true", async_reg = "true" *)
+FDPE #(
.INIT(1'd1)
) FDPE_4 (
.C(sys4x_clk),
.Q(xilinxasyncresetsynchronizerimpl2_rst_meta)
);
-(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
+(* ars_ff2 = "true", async_reg = "true" *)
+FDPE #(
.INIT(1'd1)
) FDPE_5 (
.C(sys4x_clk),
.Q(xilinxasyncresetsynchronizerimpl2_expr)
);
-(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
+(* ars_ff1 = "true", async_reg = "true" *)
+FDPE #(
.INIT(1'd1)
) FDPE_6 (
.C(sys4x_dqs_clk),
.Q(xilinxasyncresetsynchronizerimpl3_rst_meta)
);
-(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
+(* ars_ff2 = "true", async_reg = "true" *)
+FDPE #(
.INIT(1'd1)
) FDPE_7 (
.C(sys4x_dqs_clk),
endmodule
// -----------------------------------------------------------------------------
-// Auto-Generated by LiteX on 2022-08-04 21:06:58.
+// Auto-Generated by LiteX on 2022-10-28 19:01:22.
//------------------------------------------------------------------------------
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//
// Filename : litedram_core.v
// Device :
-// LiteX sha1 : 6932fc51
-// Date : 2022-08-04 21:06:57
+// LiteX sha1 : --------
+// Date : 2022-10-28 19:01:20
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
module litedram_core (
- input wire clk,
- input wire rst,
- output wire pll_locked,
- output wire [14:0] ddram_a,
- output wire [2:0] ddram_ba,
- output wire ddram_ras_n,
- output wire ddram_cas_n,
- output wire ddram_we_n,
- output wire ddram_cs_n,
- output wire [1:0] ddram_dm,
- inout wire [15:0] ddram_dq,
- inout wire [1:0] ddram_dqs_p,
- inout wire [1:0] ddram_dqs_n,
- output wire ddram_clk_p,
- output wire ddram_clk_n,
- output wire ddram_cke,
- output wire ddram_odt,
- output wire ddram_reset_n,
- output wire init_done,
- output wire init_error,
- input wire [29:0] wb_ctrl_adr,
- input wire [31:0] wb_ctrl_dat_w,
- output wire [31:0] wb_ctrl_dat_r,
- input wire [3:0] wb_ctrl_sel,
- input wire wb_ctrl_cyc,
- input wire wb_ctrl_stb,
- output wire wb_ctrl_ack,
- input wire wb_ctrl_we,
- input wire [2:0] wb_ctrl_cti,
- input wire [1:0] wb_ctrl_bte,
- output wire wb_ctrl_err,
- output wire user_clk,
- output wire user_rst,
- input wire user_port_native_0_cmd_valid,
- output wire user_port_native_0_cmd_ready,
- input wire user_port_native_0_cmd_we,
- input wire [24:0] user_port_native_0_cmd_addr,
- input wire user_port_native_0_wdata_valid,
- output wire user_port_native_0_wdata_ready,
- input wire [15:0] user_port_native_0_wdata_we,
- input wire [127:0] user_port_native_0_wdata_data,
- output wire user_port_native_0_rdata_valid,
- input wire user_port_native_0_rdata_ready,
- output wire [127:0] user_port_native_0_rdata_data
+ input wire clk,
+ input wire rst,
+ output wire pll_locked,
+ output wire [14:0] ddram_a,
+ output wire [2:0] ddram_ba,
+ output wire ddram_ras_n,
+ output wire ddram_cas_n,
+ output wire ddram_we_n,
+ output wire ddram_cs_n,
+ output wire [1:0] ddram_dm,
+ inout wire [15:0] ddram_dq,
+ inout wire [1:0] ddram_dqs_p,
+ inout wire [1:0] ddram_dqs_n,
+ output wire ddram_clk_p,
+ output wire ddram_clk_n,
+ output wire ddram_cke,
+ output wire ddram_odt,
+ output wire ddram_reset_n,
+ output wire init_done,
+ output wire init_error,
+ input wire [29:0] wb_ctrl_adr,
+ input wire [31:0] wb_ctrl_dat_w,
+ output wire [31:0] wb_ctrl_dat_r,
+ input wire [3:0] wb_ctrl_sel,
+ input wire wb_ctrl_cyc,
+ input wire wb_ctrl_stb,
+ output wire wb_ctrl_ack,
+ input wire wb_ctrl_we,
+ input wire [2:0] wb_ctrl_cti,
+ input wire [1:0] wb_ctrl_bte,
+ output wire wb_ctrl_err,
+ output wire user_clk,
+ output wire user_rst,
+ input wire user_port_native_0_cmd_valid,
+ output wire user_port_native_0_cmd_ready,
+ input wire user_port_native_0_cmd_we,
+ input wire [24:0] user_port_native_0_cmd_addr,
+ input wire user_port_native_0_wdata_valid,
+ output wire user_port_native_0_wdata_ready,
+ input wire [15:0] user_port_native_0_wdata_we,
+ input wire [127:0] user_port_native_0_wdata_data,
+ output wire user_port_native_0_rdata_valid,
+ input wire user_port_native_0_rdata_ready,
+ output wire [127:0] user_port_native_0_rdata_data
);
// Signals
//------------------------------------------------------------------------------
-reg rst_1 = 1'd0;
-wire sys_clk;
-wire sys_rst;
-wire sys4x_clk;
-wire sys4x_dqs_clk;
-wire iodelay_clk;
-wire iodelay_rst;
-wire reset;
-reg power_down = 1'd0;
-wire locked;
-wire clkin;
-wire clkout0;
-wire clkout_buf0;
-wire clkout1;
-wire clkout_buf1;
-wire clkout2;
-wire clkout_buf2;
-wire clkout3;
-wire clkout_buf3;
-reg [3:0] reset_counter = 4'd15;
-reg ic_reset = 1'd1;
-reg a7ddrphy_rst_storage = 1'd0;
-reg a7ddrphy_rst_re = 1'd0;
-reg [1:0] a7ddrphy_dly_sel_storage = 2'd0;
-reg a7ddrphy_dly_sel_re = 1'd0;
-reg [4:0] a7ddrphy_half_sys8x_taps_storage = 5'd8;
-reg a7ddrphy_half_sys8x_taps_re = 1'd0;
-reg a7ddrphy_wlevel_en_storage = 1'd0;
-reg a7ddrphy_wlevel_en_re = 1'd0;
-reg a7ddrphy_wlevel_strobe_re = 1'd0;
-wire a7ddrphy_wlevel_strobe_r;
-reg a7ddrphy_wlevel_strobe_we = 1'd0;
-reg a7ddrphy_wlevel_strobe_w = 1'd0;
-reg a7ddrphy_rdly_dq_rst_re = 1'd0;
-wire a7ddrphy_rdly_dq_rst_r;
-reg a7ddrphy_rdly_dq_rst_we = 1'd0;
-reg a7ddrphy_rdly_dq_rst_w = 1'd0;
-reg a7ddrphy_rdly_dq_inc_re = 1'd0;
-wire a7ddrphy_rdly_dq_inc_r;
-reg a7ddrphy_rdly_dq_inc_we = 1'd0;
-reg a7ddrphy_rdly_dq_inc_w = 1'd0;
-reg a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
-wire a7ddrphy_rdly_dq_bitslip_rst_r;
-reg a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
-reg a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
-reg a7ddrphy_rdly_dq_bitslip_re = 1'd0;
-wire a7ddrphy_rdly_dq_bitslip_r;
-reg a7ddrphy_rdly_dq_bitslip_we = 1'd0;
-reg a7ddrphy_rdly_dq_bitslip_w = 1'd0;
-reg a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0;
-wire a7ddrphy_wdly_dq_bitslip_rst_r;
-reg a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0;
-reg a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0;
-reg a7ddrphy_wdly_dq_bitslip_re = 1'd0;
-wire a7ddrphy_wdly_dq_bitslip_r;
-reg a7ddrphy_wdly_dq_bitslip_we = 1'd0;
-reg a7ddrphy_wdly_dq_bitslip_w = 1'd0;
-reg [1:0] a7ddrphy_rdphase_storage = 2'd2;
-reg a7ddrphy_rdphase_re = 1'd0;
-reg [1:0] a7ddrphy_wrphase_storage = 2'd3;
-reg a7ddrphy_wrphase_re = 1'd0;
-wire [14:0] a7ddrphy_dfi_p0_address;
-wire [2:0] a7ddrphy_dfi_p0_bank;
-wire a7ddrphy_dfi_p0_cas_n;
-wire a7ddrphy_dfi_p0_cs_n;
-wire a7ddrphy_dfi_p0_ras_n;
-wire a7ddrphy_dfi_p0_we_n;
-wire a7ddrphy_dfi_p0_cke;
-wire a7ddrphy_dfi_p0_odt;
-wire a7ddrphy_dfi_p0_reset_n;
-wire a7ddrphy_dfi_p0_act_n;
-wire [31:0] a7ddrphy_dfi_p0_wrdata;
-wire a7ddrphy_dfi_p0_wrdata_en;
-wire [3:0] a7ddrphy_dfi_p0_wrdata_mask;
-wire a7ddrphy_dfi_p0_rddata_en;
-reg [31:0] a7ddrphy_dfi_p0_rddata = 32'd0;
-wire a7ddrphy_dfi_p0_rddata_valid;
-wire [14:0] a7ddrphy_dfi_p1_address;
-wire [2:0] a7ddrphy_dfi_p1_bank;
-wire a7ddrphy_dfi_p1_cas_n;
-wire a7ddrphy_dfi_p1_cs_n;
-wire a7ddrphy_dfi_p1_ras_n;
-wire a7ddrphy_dfi_p1_we_n;
-wire a7ddrphy_dfi_p1_cke;
-wire a7ddrphy_dfi_p1_odt;
-wire a7ddrphy_dfi_p1_reset_n;
-wire a7ddrphy_dfi_p1_act_n;
-wire [31:0] a7ddrphy_dfi_p1_wrdata;
-wire a7ddrphy_dfi_p1_wrdata_en;
-wire [3:0] a7ddrphy_dfi_p1_wrdata_mask;
-wire a7ddrphy_dfi_p1_rddata_en;
-reg [31:0] a7ddrphy_dfi_p1_rddata = 32'd0;
-wire a7ddrphy_dfi_p1_rddata_valid;
-wire [14:0] a7ddrphy_dfi_p2_address;
-wire [2:0] a7ddrphy_dfi_p2_bank;
-wire a7ddrphy_dfi_p2_cas_n;
-wire a7ddrphy_dfi_p2_cs_n;
-wire a7ddrphy_dfi_p2_ras_n;
-wire a7ddrphy_dfi_p2_we_n;
-wire a7ddrphy_dfi_p2_cke;
-wire a7ddrphy_dfi_p2_odt;
-wire a7ddrphy_dfi_p2_reset_n;
-wire a7ddrphy_dfi_p2_act_n;
-wire [31:0] a7ddrphy_dfi_p2_wrdata;
-wire a7ddrphy_dfi_p2_wrdata_en;
-wire [3:0] a7ddrphy_dfi_p2_wrdata_mask;
-wire a7ddrphy_dfi_p2_rddata_en;
-reg [31:0] a7ddrphy_dfi_p2_rddata = 32'd0;
-wire a7ddrphy_dfi_p2_rddata_valid;
-wire [14:0] a7ddrphy_dfi_p3_address;
-wire [2:0] a7ddrphy_dfi_p3_bank;
-wire a7ddrphy_dfi_p3_cas_n;
-wire a7ddrphy_dfi_p3_cs_n;
-wire a7ddrphy_dfi_p3_ras_n;
-wire a7ddrphy_dfi_p3_we_n;
-wire a7ddrphy_dfi_p3_cke;
-wire a7ddrphy_dfi_p3_odt;
-wire a7ddrphy_dfi_p3_reset_n;
-wire a7ddrphy_dfi_p3_act_n;
-wire [31:0] a7ddrphy_dfi_p3_wrdata;
-wire a7ddrphy_dfi_p3_wrdata_en;
-wire [3:0] a7ddrphy_dfi_p3_wrdata_mask;
-wire a7ddrphy_dfi_p3_rddata_en;
-reg [31:0] a7ddrphy_dfi_p3_rddata = 32'd0;
-wire a7ddrphy_dfi_p3_rddata_valid;
-wire a7ddrphy_sd_clk_se_nodelay;
-wire [2:0] a7ddrphy_pads_ba;
-reg a7ddrphy_dqs_oe = 1'd0;
-wire a7ddrphy_dqs_preamble;
-wire a7ddrphy_dqs_postamble;
-wire a7ddrphy_dqs_oe_delay_tappeddelayline;
-reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
-reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
-reg a7ddrphy_dqspattern0 = 1'd0;
-reg a7ddrphy_dqspattern1 = 1'd0;
-reg [7:0] a7ddrphy_dqspattern_o0 = 8'd0;
-reg [7:0] a7ddrphy_dqspattern_o1 = 8'd0;
-wire a7ddrphy_dqs_o_no_delay0;
-wire a7ddrphy_dqs_t0;
-reg [7:0] a7ddrphy_bitslip00 = 8'd0;
-reg [2:0] a7ddrphy_bitslip0_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip0_r0 = 16'd0;
-wire a7ddrphy0;
-wire a7ddrphy_dqs_o_no_delay1;
-wire a7ddrphy_dqs_t1;
-reg [7:0] a7ddrphy_bitslip10 = 8'd0;
-reg [2:0] a7ddrphy_bitslip1_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip1_r0 = 16'd0;
-wire a7ddrphy1;
-reg [7:0] a7ddrphy_bitslip01 = 8'd0;
-reg [2:0] a7ddrphy_bitslip0_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip0_r1 = 16'd0;
-reg [7:0] a7ddrphy_bitslip11 = 8'd0;
-reg [2:0] a7ddrphy_bitslip1_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip1_r1 = 16'd0;
-wire a7ddrphy_dq_oe;
-wire a7ddrphy_dq_oe_delay_tappeddelayline;
-reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
-reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
-wire a7ddrphy_dq_o_nodelay0;
-wire a7ddrphy_dq_i_nodelay0;
-wire a7ddrphy_dq_i_delayed0;
-wire a7ddrphy_dq_t0;
-reg [7:0] a7ddrphy_bitslip02 = 8'd0;
-reg [2:0] a7ddrphy_bitslip0_value2 = 3'd7;
-reg [15:0] a7ddrphy_bitslip0_r2 = 16'd0;
-wire [7:0] a7ddrphy_bitslip03;
-reg [7:0] a7ddrphy_bitslip04 = 8'd0;
-reg [2:0] a7ddrphy_bitslip0_value3 = 3'd7;
-reg [15:0] a7ddrphy_bitslip0_r3 = 16'd0;
-wire a7ddrphy_dq_o_nodelay1;
-wire a7ddrphy_dq_i_nodelay1;
-wire a7ddrphy_dq_i_delayed1;
-wire a7ddrphy_dq_t1;
-reg [7:0] a7ddrphy_bitslip12 = 8'd0;
-reg [2:0] a7ddrphy_bitslip1_value2 = 3'd7;
-reg [15:0] a7ddrphy_bitslip1_r2 = 16'd0;
-wire [7:0] a7ddrphy_bitslip13;
-reg [7:0] a7ddrphy_bitslip14 = 8'd0;
-reg [2:0] a7ddrphy_bitslip1_value3 = 3'd7;
-reg [15:0] a7ddrphy_bitslip1_r3 = 16'd0;
-wire a7ddrphy_dq_o_nodelay2;
-wire a7ddrphy_dq_i_nodelay2;
-wire a7ddrphy_dq_i_delayed2;
-wire a7ddrphy_dq_t2;
-reg [7:0] a7ddrphy_bitslip20 = 8'd0;
-reg [2:0] a7ddrphy_bitslip2_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip2_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip21;
-reg [7:0] a7ddrphy_bitslip22 = 8'd0;
-reg [2:0] a7ddrphy_bitslip2_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip2_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay3;
-wire a7ddrphy_dq_i_nodelay3;
-wire a7ddrphy_dq_i_delayed3;
-wire a7ddrphy_dq_t3;
-reg [7:0] a7ddrphy_bitslip30 = 8'd0;
-reg [2:0] a7ddrphy_bitslip3_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip3_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip31;
-reg [7:0] a7ddrphy_bitslip32 = 8'd0;
-reg [2:0] a7ddrphy_bitslip3_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip3_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay4;
-wire a7ddrphy_dq_i_nodelay4;
-wire a7ddrphy_dq_i_delayed4;
-wire a7ddrphy_dq_t4;
-reg [7:0] a7ddrphy_bitslip40 = 8'd0;
-reg [2:0] a7ddrphy_bitslip4_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip4_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip41;
-reg [7:0] a7ddrphy_bitslip42 = 8'd0;
-reg [2:0] a7ddrphy_bitslip4_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip4_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay5;
-wire a7ddrphy_dq_i_nodelay5;
-wire a7ddrphy_dq_i_delayed5;
-wire a7ddrphy_dq_t5;
-reg [7:0] a7ddrphy_bitslip50 = 8'd0;
-reg [2:0] a7ddrphy_bitslip5_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip5_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip51;
-reg [7:0] a7ddrphy_bitslip52 = 8'd0;
-reg [2:0] a7ddrphy_bitslip5_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip5_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay6;
-wire a7ddrphy_dq_i_nodelay6;
-wire a7ddrphy_dq_i_delayed6;
-wire a7ddrphy_dq_t6;
-reg [7:0] a7ddrphy_bitslip60 = 8'd0;
-reg [2:0] a7ddrphy_bitslip6_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip6_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip61;
-reg [7:0] a7ddrphy_bitslip62 = 8'd0;
-reg [2:0] a7ddrphy_bitslip6_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip6_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay7;
-wire a7ddrphy_dq_i_nodelay7;
-wire a7ddrphy_dq_i_delayed7;
-wire a7ddrphy_dq_t7;
-reg [7:0] a7ddrphy_bitslip70 = 8'd0;
-reg [2:0] a7ddrphy_bitslip7_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip7_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip71;
-reg [7:0] a7ddrphy_bitslip72 = 8'd0;
-reg [2:0] a7ddrphy_bitslip7_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip7_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay8;
-wire a7ddrphy_dq_i_nodelay8;
-wire a7ddrphy_dq_i_delayed8;
-wire a7ddrphy_dq_t8;
-reg [7:0] a7ddrphy_bitslip80 = 8'd0;
-reg [2:0] a7ddrphy_bitslip8_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip8_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip81;
-reg [7:0] a7ddrphy_bitslip82 = 8'd0;
-reg [2:0] a7ddrphy_bitslip8_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip8_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay9;
-wire a7ddrphy_dq_i_nodelay9;
-wire a7ddrphy_dq_i_delayed9;
-wire a7ddrphy_dq_t9;
-reg [7:0] a7ddrphy_bitslip90 = 8'd0;
-reg [2:0] a7ddrphy_bitslip9_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip9_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip91;
-reg [7:0] a7ddrphy_bitslip92 = 8'd0;
-reg [2:0] a7ddrphy_bitslip9_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip9_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay10;
-wire a7ddrphy_dq_i_nodelay10;
-wire a7ddrphy_dq_i_delayed10;
-wire a7ddrphy_dq_t10;
-reg [7:0] a7ddrphy_bitslip100 = 8'd0;
-reg [2:0] a7ddrphy_bitslip10_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip10_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip101;
-reg [7:0] a7ddrphy_bitslip102 = 8'd0;
-reg [2:0] a7ddrphy_bitslip10_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip10_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay11;
-wire a7ddrphy_dq_i_nodelay11;
-wire a7ddrphy_dq_i_delayed11;
-wire a7ddrphy_dq_t11;
-reg [7:0] a7ddrphy_bitslip110 = 8'd0;
-reg [2:0] a7ddrphy_bitslip11_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip11_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip111;
-reg [7:0] a7ddrphy_bitslip112 = 8'd0;
-reg [2:0] a7ddrphy_bitslip11_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip11_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay12;
-wire a7ddrphy_dq_i_nodelay12;
-wire a7ddrphy_dq_i_delayed12;
-wire a7ddrphy_dq_t12;
-reg [7:0] a7ddrphy_bitslip120 = 8'd0;
-reg [2:0] a7ddrphy_bitslip12_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip12_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip121;
-reg [7:0] a7ddrphy_bitslip122 = 8'd0;
-reg [2:0] a7ddrphy_bitslip12_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip12_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay13;
-wire a7ddrphy_dq_i_nodelay13;
-wire a7ddrphy_dq_i_delayed13;
-wire a7ddrphy_dq_t13;
-reg [7:0] a7ddrphy_bitslip130 = 8'd0;
-reg [2:0] a7ddrphy_bitslip13_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip13_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip131;
-reg [7:0] a7ddrphy_bitslip132 = 8'd0;
-reg [2:0] a7ddrphy_bitslip13_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip13_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay14;
-wire a7ddrphy_dq_i_nodelay14;
-wire a7ddrphy_dq_i_delayed14;
-wire a7ddrphy_dq_t14;
-reg [7:0] a7ddrphy_bitslip140 = 8'd0;
-reg [2:0] a7ddrphy_bitslip14_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip14_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip141;
-reg [7:0] a7ddrphy_bitslip142 = 8'd0;
-reg [2:0] a7ddrphy_bitslip14_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip14_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay15;
-wire a7ddrphy_dq_i_nodelay15;
-wire a7ddrphy_dq_i_delayed15;
-wire a7ddrphy_dq_t15;
-reg [7:0] a7ddrphy_bitslip150 = 8'd0;
-reg [2:0] a7ddrphy_bitslip15_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip15_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip151;
-reg [7:0] a7ddrphy_bitslip152 = 8'd0;
-reg [2:0] a7ddrphy_bitslip15_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip15_r1 = 16'd0;
-reg a7ddrphy_rddata_en_tappeddelayline0 = 1'd0;
-reg a7ddrphy_rddata_en_tappeddelayline1 = 1'd0;
-reg a7ddrphy_rddata_en_tappeddelayline2 = 1'd0;
-reg a7ddrphy_rddata_en_tappeddelayline3 = 1'd0;
-reg a7ddrphy_rddata_en_tappeddelayline4 = 1'd0;
-reg a7ddrphy_rddata_en_tappeddelayline5 = 1'd0;
-reg a7ddrphy_rddata_en_tappeddelayline6 = 1'd0;
-reg a7ddrphy_rddata_en_tappeddelayline7 = 1'd0;
-reg a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
-reg a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
-reg a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
-wire [14:0] litedramcore_slave_p0_address;
-wire [2:0] litedramcore_slave_p0_bank;
-wire litedramcore_slave_p0_cas_n;
-wire litedramcore_slave_p0_cs_n;
-wire litedramcore_slave_p0_ras_n;
-wire litedramcore_slave_p0_we_n;
-wire litedramcore_slave_p0_cke;
-wire litedramcore_slave_p0_odt;
-wire litedramcore_slave_p0_reset_n;
-wire litedramcore_slave_p0_act_n;
-wire [31:0] litedramcore_slave_p0_wrdata;
-wire litedramcore_slave_p0_wrdata_en;
-wire [3:0] litedramcore_slave_p0_wrdata_mask;
-wire litedramcore_slave_p0_rddata_en;
-reg [31:0] litedramcore_slave_p0_rddata = 32'd0;
-reg litedramcore_slave_p0_rddata_valid = 1'd0;
-wire [14:0] litedramcore_slave_p1_address;
-wire [2:0] litedramcore_slave_p1_bank;
-wire litedramcore_slave_p1_cas_n;
-wire litedramcore_slave_p1_cs_n;
-wire litedramcore_slave_p1_ras_n;
-wire litedramcore_slave_p1_we_n;
-wire litedramcore_slave_p1_cke;
-wire litedramcore_slave_p1_odt;
-wire litedramcore_slave_p1_reset_n;
-wire litedramcore_slave_p1_act_n;
-wire [31:0] litedramcore_slave_p1_wrdata;
-wire litedramcore_slave_p1_wrdata_en;
-wire [3:0] litedramcore_slave_p1_wrdata_mask;
-wire litedramcore_slave_p1_rddata_en;
-reg [31:0] litedramcore_slave_p1_rddata = 32'd0;
-reg litedramcore_slave_p1_rddata_valid = 1'd0;
-wire [14:0] litedramcore_slave_p2_address;
-wire [2:0] litedramcore_slave_p2_bank;
-wire litedramcore_slave_p2_cas_n;
-wire litedramcore_slave_p2_cs_n;
-wire litedramcore_slave_p2_ras_n;
-wire litedramcore_slave_p2_we_n;
-wire litedramcore_slave_p2_cke;
-wire litedramcore_slave_p2_odt;
-wire litedramcore_slave_p2_reset_n;
-wire litedramcore_slave_p2_act_n;
-wire [31:0] litedramcore_slave_p2_wrdata;
-wire litedramcore_slave_p2_wrdata_en;
-wire [3:0] litedramcore_slave_p2_wrdata_mask;
-wire litedramcore_slave_p2_rddata_en;
-reg [31:0] litedramcore_slave_p2_rddata = 32'd0;
-reg litedramcore_slave_p2_rddata_valid = 1'd0;
-wire [14:0] litedramcore_slave_p3_address;
-wire [2:0] litedramcore_slave_p3_bank;
-wire litedramcore_slave_p3_cas_n;
-wire litedramcore_slave_p3_cs_n;
-wire litedramcore_slave_p3_ras_n;
-wire litedramcore_slave_p3_we_n;
-wire litedramcore_slave_p3_cke;
-wire litedramcore_slave_p3_odt;
-wire litedramcore_slave_p3_reset_n;
-wire litedramcore_slave_p3_act_n;
-wire [31:0] litedramcore_slave_p3_wrdata;
-wire litedramcore_slave_p3_wrdata_en;
-wire [3:0] litedramcore_slave_p3_wrdata_mask;
-wire litedramcore_slave_p3_rddata_en;
-reg [31:0] litedramcore_slave_p3_rddata = 32'd0;
-reg litedramcore_slave_p3_rddata_valid = 1'd0;
-reg [14:0] litedramcore_master_p0_address = 15'd0;
-reg [2:0] litedramcore_master_p0_bank = 3'd0;
-reg litedramcore_master_p0_cas_n = 1'd1;
-reg litedramcore_master_p0_cs_n = 1'd1;
-reg litedramcore_master_p0_ras_n = 1'd1;
-reg litedramcore_master_p0_we_n = 1'd1;
-reg litedramcore_master_p0_cke = 1'd0;
-reg litedramcore_master_p0_odt = 1'd0;
-reg litedramcore_master_p0_reset_n = 1'd0;
-reg litedramcore_master_p0_act_n = 1'd1;
-reg [31:0] litedramcore_master_p0_wrdata = 32'd0;
-reg litedramcore_master_p0_wrdata_en = 1'd0;
-reg [3:0] litedramcore_master_p0_wrdata_mask = 4'd0;
-reg litedramcore_master_p0_rddata_en = 1'd0;
-wire [31:0] litedramcore_master_p0_rddata;
-wire litedramcore_master_p0_rddata_valid;
-reg [14:0] litedramcore_master_p1_address = 15'd0;
-reg [2:0] litedramcore_master_p1_bank = 3'd0;
-reg litedramcore_master_p1_cas_n = 1'd1;
-reg litedramcore_master_p1_cs_n = 1'd1;
-reg litedramcore_master_p1_ras_n = 1'd1;
-reg litedramcore_master_p1_we_n = 1'd1;
-reg litedramcore_master_p1_cke = 1'd0;
-reg litedramcore_master_p1_odt = 1'd0;
-reg litedramcore_master_p1_reset_n = 1'd0;
-reg litedramcore_master_p1_act_n = 1'd1;
-reg [31:0] litedramcore_master_p1_wrdata = 32'd0;
-reg litedramcore_master_p1_wrdata_en = 1'd0;
-reg [3:0] litedramcore_master_p1_wrdata_mask = 4'd0;
-reg litedramcore_master_p1_rddata_en = 1'd0;
-wire [31:0] litedramcore_master_p1_rddata;
-wire litedramcore_master_p1_rddata_valid;
-reg [14:0] litedramcore_master_p2_address = 15'd0;
-reg [2:0] litedramcore_master_p2_bank = 3'd0;
-reg litedramcore_master_p2_cas_n = 1'd1;
-reg litedramcore_master_p2_cs_n = 1'd1;
-reg litedramcore_master_p2_ras_n = 1'd1;
-reg litedramcore_master_p2_we_n = 1'd1;
-reg litedramcore_master_p2_cke = 1'd0;
-reg litedramcore_master_p2_odt = 1'd0;
-reg litedramcore_master_p2_reset_n = 1'd0;
-reg litedramcore_master_p2_act_n = 1'd1;
-reg [31:0] litedramcore_master_p2_wrdata = 32'd0;
-reg litedramcore_master_p2_wrdata_en = 1'd0;
-reg [3:0] litedramcore_master_p2_wrdata_mask = 4'd0;
-reg litedramcore_master_p2_rddata_en = 1'd0;
-wire [31:0] litedramcore_master_p2_rddata;
-wire litedramcore_master_p2_rddata_valid;
-reg [14:0] litedramcore_master_p3_address = 15'd0;
-reg [2:0] litedramcore_master_p3_bank = 3'd0;
-reg litedramcore_master_p3_cas_n = 1'd1;
-reg litedramcore_master_p3_cs_n = 1'd1;
-reg litedramcore_master_p3_ras_n = 1'd1;
-reg litedramcore_master_p3_we_n = 1'd1;
-reg litedramcore_master_p3_cke = 1'd0;
-reg litedramcore_master_p3_odt = 1'd0;
-reg litedramcore_master_p3_reset_n = 1'd0;
-reg litedramcore_master_p3_act_n = 1'd1;
-reg [31:0] litedramcore_master_p3_wrdata = 32'd0;
-reg litedramcore_master_p3_wrdata_en = 1'd0;
-reg [3:0] litedramcore_master_p3_wrdata_mask = 4'd0;
-reg litedramcore_master_p3_rddata_en = 1'd0;
-wire [31:0] litedramcore_master_p3_rddata;
-wire litedramcore_master_p3_rddata_valid;
-wire [14:0] litedramcore_csr_dfi_p0_address;
-wire [2:0] litedramcore_csr_dfi_p0_bank;
-reg litedramcore_csr_dfi_p0_cas_n = 1'd1;
-reg litedramcore_csr_dfi_p0_cs_n = 1'd1;
-reg litedramcore_csr_dfi_p0_ras_n = 1'd1;
-reg litedramcore_csr_dfi_p0_we_n = 1'd1;
-wire litedramcore_csr_dfi_p0_cke;
-wire litedramcore_csr_dfi_p0_odt;
-wire litedramcore_csr_dfi_p0_reset_n;
-reg litedramcore_csr_dfi_p0_act_n = 1'd1;
-wire [31:0] litedramcore_csr_dfi_p0_wrdata;
-wire litedramcore_csr_dfi_p0_wrdata_en;
-wire [3:0] litedramcore_csr_dfi_p0_wrdata_mask;
-wire litedramcore_csr_dfi_p0_rddata_en;
-reg [31:0] litedramcore_csr_dfi_p0_rddata = 32'd0;
-reg litedramcore_csr_dfi_p0_rddata_valid = 1'd0;
-wire [14:0] litedramcore_csr_dfi_p1_address;
-wire [2:0] litedramcore_csr_dfi_p1_bank;
-reg litedramcore_csr_dfi_p1_cas_n = 1'd1;
-reg litedramcore_csr_dfi_p1_cs_n = 1'd1;
-reg litedramcore_csr_dfi_p1_ras_n = 1'd1;
-reg litedramcore_csr_dfi_p1_we_n = 1'd1;
-wire litedramcore_csr_dfi_p1_cke;
-wire litedramcore_csr_dfi_p1_odt;
-wire litedramcore_csr_dfi_p1_reset_n;
-reg litedramcore_csr_dfi_p1_act_n = 1'd1;
-wire [31:0] litedramcore_csr_dfi_p1_wrdata;
-wire litedramcore_csr_dfi_p1_wrdata_en;
-wire [3:0] litedramcore_csr_dfi_p1_wrdata_mask;
-wire litedramcore_csr_dfi_p1_rddata_en;
-reg [31:0] litedramcore_csr_dfi_p1_rddata = 32'd0;
-reg litedramcore_csr_dfi_p1_rddata_valid = 1'd0;
-wire [14:0] litedramcore_csr_dfi_p2_address;
-wire [2:0] litedramcore_csr_dfi_p2_bank;
-reg litedramcore_csr_dfi_p2_cas_n = 1'd1;
-reg litedramcore_csr_dfi_p2_cs_n = 1'd1;
-reg litedramcore_csr_dfi_p2_ras_n = 1'd1;
-reg litedramcore_csr_dfi_p2_we_n = 1'd1;
-wire litedramcore_csr_dfi_p2_cke;
-wire litedramcore_csr_dfi_p2_odt;
-wire litedramcore_csr_dfi_p2_reset_n;
-reg litedramcore_csr_dfi_p2_act_n = 1'd1;
-wire [31:0] litedramcore_csr_dfi_p2_wrdata;
-wire litedramcore_csr_dfi_p2_wrdata_en;
-wire [3:0] litedramcore_csr_dfi_p2_wrdata_mask;
-wire litedramcore_csr_dfi_p2_rddata_en;
-reg [31:0] litedramcore_csr_dfi_p2_rddata = 32'd0;
-reg litedramcore_csr_dfi_p2_rddata_valid = 1'd0;
-wire [14:0] litedramcore_csr_dfi_p3_address;
-wire [2:0] litedramcore_csr_dfi_p3_bank;
-reg litedramcore_csr_dfi_p3_cas_n = 1'd1;
-reg litedramcore_csr_dfi_p3_cs_n = 1'd1;
-reg litedramcore_csr_dfi_p3_ras_n = 1'd1;
-reg litedramcore_csr_dfi_p3_we_n = 1'd1;
-wire litedramcore_csr_dfi_p3_cke;
-wire litedramcore_csr_dfi_p3_odt;
-wire litedramcore_csr_dfi_p3_reset_n;
-reg litedramcore_csr_dfi_p3_act_n = 1'd1;
-wire [31:0] litedramcore_csr_dfi_p3_wrdata;
-wire litedramcore_csr_dfi_p3_wrdata_en;
-wire [3:0] litedramcore_csr_dfi_p3_wrdata_mask;
-wire litedramcore_csr_dfi_p3_rddata_en;
-reg [31:0] litedramcore_csr_dfi_p3_rddata = 32'd0;
-reg litedramcore_csr_dfi_p3_rddata_valid = 1'd0;
-reg [14:0] litedramcore_ext_dfi_p0_address = 15'd0;
-reg [2:0] litedramcore_ext_dfi_p0_bank = 3'd0;
-reg litedramcore_ext_dfi_p0_cas_n = 1'd1;
-reg litedramcore_ext_dfi_p0_cs_n = 1'd1;
-reg litedramcore_ext_dfi_p0_ras_n = 1'd1;
-reg litedramcore_ext_dfi_p0_we_n = 1'd1;
-reg litedramcore_ext_dfi_p0_cke = 1'd0;
-reg litedramcore_ext_dfi_p0_odt = 1'd0;
-reg litedramcore_ext_dfi_p0_reset_n = 1'd0;
-reg litedramcore_ext_dfi_p0_act_n = 1'd1;
-reg [31:0] litedramcore_ext_dfi_p0_wrdata = 32'd0;
-reg litedramcore_ext_dfi_p0_wrdata_en = 1'd0;
-reg [3:0] litedramcore_ext_dfi_p0_wrdata_mask = 4'd0;
-reg litedramcore_ext_dfi_p0_rddata_en = 1'd0;
-reg [31:0] litedramcore_ext_dfi_p0_rddata = 32'd0;
-reg litedramcore_ext_dfi_p0_rddata_valid = 1'd0;
-reg [14:0] litedramcore_ext_dfi_p1_address = 15'd0;
-reg [2:0] litedramcore_ext_dfi_p1_bank = 3'd0;
-reg litedramcore_ext_dfi_p1_cas_n = 1'd1;
-reg litedramcore_ext_dfi_p1_cs_n = 1'd1;
-reg litedramcore_ext_dfi_p1_ras_n = 1'd1;
-reg litedramcore_ext_dfi_p1_we_n = 1'd1;
-reg litedramcore_ext_dfi_p1_cke = 1'd0;
-reg litedramcore_ext_dfi_p1_odt = 1'd0;
-reg litedramcore_ext_dfi_p1_reset_n = 1'd0;
-reg litedramcore_ext_dfi_p1_act_n = 1'd1;
-reg [31:0] litedramcore_ext_dfi_p1_wrdata = 32'd0;
-reg litedramcore_ext_dfi_p1_wrdata_en = 1'd0;
-reg [3:0] litedramcore_ext_dfi_p1_wrdata_mask = 4'd0;
-reg litedramcore_ext_dfi_p1_rddata_en = 1'd0;
-reg [31:0] litedramcore_ext_dfi_p1_rddata = 32'd0;
-reg litedramcore_ext_dfi_p1_rddata_valid = 1'd0;
-reg [14:0] litedramcore_ext_dfi_p2_address = 15'd0;
-reg [2:0] litedramcore_ext_dfi_p2_bank = 3'd0;
-reg litedramcore_ext_dfi_p2_cas_n = 1'd1;
-reg litedramcore_ext_dfi_p2_cs_n = 1'd1;
-reg litedramcore_ext_dfi_p2_ras_n = 1'd1;
-reg litedramcore_ext_dfi_p2_we_n = 1'd1;
-reg litedramcore_ext_dfi_p2_cke = 1'd0;
-reg litedramcore_ext_dfi_p2_odt = 1'd0;
-reg litedramcore_ext_dfi_p2_reset_n = 1'd0;
-reg litedramcore_ext_dfi_p2_act_n = 1'd1;
-reg [31:0] litedramcore_ext_dfi_p2_wrdata = 32'd0;
-reg litedramcore_ext_dfi_p2_wrdata_en = 1'd0;
-reg [3:0] litedramcore_ext_dfi_p2_wrdata_mask = 4'd0;
-reg litedramcore_ext_dfi_p2_rddata_en = 1'd0;
-reg [31:0] litedramcore_ext_dfi_p2_rddata = 32'd0;
-reg litedramcore_ext_dfi_p2_rddata_valid = 1'd0;
-reg [14:0] litedramcore_ext_dfi_p3_address = 15'd0;
-reg [2:0] litedramcore_ext_dfi_p3_bank = 3'd0;
-reg litedramcore_ext_dfi_p3_cas_n = 1'd1;
-reg litedramcore_ext_dfi_p3_cs_n = 1'd1;
-reg litedramcore_ext_dfi_p3_ras_n = 1'd1;
-reg litedramcore_ext_dfi_p3_we_n = 1'd1;
-reg litedramcore_ext_dfi_p3_cke = 1'd0;
-reg litedramcore_ext_dfi_p3_odt = 1'd0;
-reg litedramcore_ext_dfi_p3_reset_n = 1'd0;
-reg litedramcore_ext_dfi_p3_act_n = 1'd1;
-reg [31:0] litedramcore_ext_dfi_p3_wrdata = 32'd0;
-reg litedramcore_ext_dfi_p3_wrdata_en = 1'd0;
-reg [3:0] litedramcore_ext_dfi_p3_wrdata_mask = 4'd0;
-reg litedramcore_ext_dfi_p3_rddata_en = 1'd0;
-reg [31:0] litedramcore_ext_dfi_p3_rddata = 32'd0;
-reg litedramcore_ext_dfi_p3_rddata_valid = 1'd0;
-reg litedramcore_ext_dfi_sel = 1'd0;
-wire litedramcore_sel;
-wire litedramcore_cke;
-wire litedramcore_odt;
-wire litedramcore_reset_n;
-reg [3:0] litedramcore_storage = 4'd1;
-reg litedramcore_re = 1'd0;
-wire litedramcore_phaseinjector0_csrfield_cs;
-wire litedramcore_phaseinjector0_csrfield_we;
-wire litedramcore_phaseinjector0_csrfield_cas;
-wire litedramcore_phaseinjector0_csrfield_ras;
-wire litedramcore_phaseinjector0_csrfield_wren;
-wire litedramcore_phaseinjector0_csrfield_rden;
-reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0;
-reg litedramcore_phaseinjector0_command_re = 1'd0;
-reg litedramcore_phaseinjector0_command_issue_re = 1'd0;
-wire litedramcore_phaseinjector0_command_issue_r;
-reg litedramcore_phaseinjector0_command_issue_we = 1'd0;
-reg litedramcore_phaseinjector0_command_issue_w = 1'd0;
-reg [14:0] litedramcore_phaseinjector0_address_storage = 15'd0;
-reg litedramcore_phaseinjector0_address_re = 1'd0;
-reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0;
-reg litedramcore_phaseinjector0_baddress_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector0_wrdata_storage = 32'd0;
-reg litedramcore_phaseinjector0_wrdata_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector0_rddata_status = 32'd0;
-wire litedramcore_phaseinjector0_rddata_we;
-reg litedramcore_phaseinjector0_rddata_re = 1'd0;
-wire litedramcore_phaseinjector1_csrfield_cs;
-wire litedramcore_phaseinjector1_csrfield_we;
-wire litedramcore_phaseinjector1_csrfield_cas;
-wire litedramcore_phaseinjector1_csrfield_ras;
-wire litedramcore_phaseinjector1_csrfield_wren;
-wire litedramcore_phaseinjector1_csrfield_rden;
-reg [5:0] litedramcore_phaseinjector1_command_storage = 6'd0;
-reg litedramcore_phaseinjector1_command_re = 1'd0;
-reg litedramcore_phaseinjector1_command_issue_re = 1'd0;
-wire litedramcore_phaseinjector1_command_issue_r;
-reg litedramcore_phaseinjector1_command_issue_we = 1'd0;
-reg litedramcore_phaseinjector1_command_issue_w = 1'd0;
-reg [14:0] litedramcore_phaseinjector1_address_storage = 15'd0;
-reg litedramcore_phaseinjector1_address_re = 1'd0;
-reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0;
-reg litedramcore_phaseinjector1_baddress_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector1_wrdata_storage = 32'd0;
-reg litedramcore_phaseinjector1_wrdata_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector1_rddata_status = 32'd0;
-wire litedramcore_phaseinjector1_rddata_we;
-reg litedramcore_phaseinjector1_rddata_re = 1'd0;
-wire litedramcore_phaseinjector2_csrfield_cs;
-wire litedramcore_phaseinjector2_csrfield_we;
-wire litedramcore_phaseinjector2_csrfield_cas;
-wire litedramcore_phaseinjector2_csrfield_ras;
-wire litedramcore_phaseinjector2_csrfield_wren;
-wire litedramcore_phaseinjector2_csrfield_rden;
-reg [5:0] litedramcore_phaseinjector2_command_storage = 6'd0;
-reg litedramcore_phaseinjector2_command_re = 1'd0;
-reg litedramcore_phaseinjector2_command_issue_re = 1'd0;
-wire litedramcore_phaseinjector2_command_issue_r;
-reg litedramcore_phaseinjector2_command_issue_we = 1'd0;
-reg litedramcore_phaseinjector2_command_issue_w = 1'd0;
-reg [14:0] litedramcore_phaseinjector2_address_storage = 15'd0;
-reg litedramcore_phaseinjector2_address_re = 1'd0;
-reg [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0;
-reg litedramcore_phaseinjector2_baddress_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector2_wrdata_storage = 32'd0;
-reg litedramcore_phaseinjector2_wrdata_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector2_rddata_status = 32'd0;
-wire litedramcore_phaseinjector2_rddata_we;
-reg litedramcore_phaseinjector2_rddata_re = 1'd0;
-wire litedramcore_phaseinjector3_csrfield_cs;
-wire litedramcore_phaseinjector3_csrfield_we;
-wire litedramcore_phaseinjector3_csrfield_cas;
-wire litedramcore_phaseinjector3_csrfield_ras;
-wire litedramcore_phaseinjector3_csrfield_wren;
-wire litedramcore_phaseinjector3_csrfield_rden;
-reg [5:0] litedramcore_phaseinjector3_command_storage = 6'd0;
-reg litedramcore_phaseinjector3_command_re = 1'd0;
-reg litedramcore_phaseinjector3_command_issue_re = 1'd0;
-wire litedramcore_phaseinjector3_command_issue_r;
-reg litedramcore_phaseinjector3_command_issue_we = 1'd0;
-reg litedramcore_phaseinjector3_command_issue_w = 1'd0;
-reg [14:0] litedramcore_phaseinjector3_address_storage = 15'd0;
-reg litedramcore_phaseinjector3_address_re = 1'd0;
-reg [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0;
-reg litedramcore_phaseinjector3_baddress_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector3_wrdata_storage = 32'd0;
-reg litedramcore_phaseinjector3_wrdata_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector3_rddata_status = 32'd0;
-wire litedramcore_phaseinjector3_rddata_we;
-reg litedramcore_phaseinjector3_rddata_re = 1'd0;
-wire litedramcore_interface_bank0_valid;
-wire litedramcore_interface_bank0_ready;
-wire litedramcore_interface_bank0_we;
-wire [21:0] litedramcore_interface_bank0_addr;
-wire litedramcore_interface_bank0_lock;
-wire litedramcore_interface_bank0_wdata_ready;
-wire litedramcore_interface_bank0_rdata_valid;
-wire litedramcore_interface_bank1_valid;
-wire litedramcore_interface_bank1_ready;
-wire litedramcore_interface_bank1_we;
-wire [21:0] litedramcore_interface_bank1_addr;
-wire litedramcore_interface_bank1_lock;
-wire litedramcore_interface_bank1_wdata_ready;
-wire litedramcore_interface_bank1_rdata_valid;
-wire litedramcore_interface_bank2_valid;
-wire litedramcore_interface_bank2_ready;
-wire litedramcore_interface_bank2_we;
-wire [21:0] litedramcore_interface_bank2_addr;
-wire litedramcore_interface_bank2_lock;
-wire litedramcore_interface_bank2_wdata_ready;
-wire litedramcore_interface_bank2_rdata_valid;
-wire litedramcore_interface_bank3_valid;
-wire litedramcore_interface_bank3_ready;
-wire litedramcore_interface_bank3_we;
-wire [21:0] litedramcore_interface_bank3_addr;
-wire litedramcore_interface_bank3_lock;
-wire litedramcore_interface_bank3_wdata_ready;
-wire litedramcore_interface_bank3_rdata_valid;
-wire litedramcore_interface_bank4_valid;
-wire litedramcore_interface_bank4_ready;
-wire litedramcore_interface_bank4_we;
-wire [21:0] litedramcore_interface_bank4_addr;
-wire litedramcore_interface_bank4_lock;
-wire litedramcore_interface_bank4_wdata_ready;
-wire litedramcore_interface_bank4_rdata_valid;
-wire litedramcore_interface_bank5_valid;
-wire litedramcore_interface_bank5_ready;
-wire litedramcore_interface_bank5_we;
-wire [21:0] litedramcore_interface_bank5_addr;
-wire litedramcore_interface_bank5_lock;
-wire litedramcore_interface_bank5_wdata_ready;
-wire litedramcore_interface_bank5_rdata_valid;
-wire litedramcore_interface_bank6_valid;
-wire litedramcore_interface_bank6_ready;
-wire litedramcore_interface_bank6_we;
-wire [21:0] litedramcore_interface_bank6_addr;
-wire litedramcore_interface_bank6_lock;
-wire litedramcore_interface_bank6_wdata_ready;
-wire litedramcore_interface_bank6_rdata_valid;
-wire litedramcore_interface_bank7_valid;
-wire litedramcore_interface_bank7_ready;
-wire litedramcore_interface_bank7_we;
-wire [21:0] litedramcore_interface_bank7_addr;
-wire litedramcore_interface_bank7_lock;
-wire litedramcore_interface_bank7_wdata_ready;
-wire litedramcore_interface_bank7_rdata_valid;
-reg [127:0] litedramcore_interface_wdata = 128'd0;
-reg [15:0] litedramcore_interface_wdata_we = 16'd0;
-wire [127:0] litedramcore_interface_rdata;
-reg [14:0] litedramcore_dfi_p0_address = 15'd0;
-reg [2:0] litedramcore_dfi_p0_bank = 3'd0;
-reg litedramcore_dfi_p0_cas_n = 1'd1;
-reg litedramcore_dfi_p0_cs_n = 1'd1;
-reg litedramcore_dfi_p0_ras_n = 1'd1;
-reg litedramcore_dfi_p0_we_n = 1'd1;
-wire litedramcore_dfi_p0_cke;
-wire litedramcore_dfi_p0_odt;
-wire litedramcore_dfi_p0_reset_n;
-reg litedramcore_dfi_p0_act_n = 1'd1;
-wire [31:0] litedramcore_dfi_p0_wrdata;
-reg litedramcore_dfi_p0_wrdata_en = 1'd0;
-wire [3:0] litedramcore_dfi_p0_wrdata_mask;
-reg litedramcore_dfi_p0_rddata_en = 1'd0;
-wire [31:0] litedramcore_dfi_p0_rddata;
-wire litedramcore_dfi_p0_rddata_valid;
-reg [14:0] litedramcore_dfi_p1_address = 15'd0;
-reg [2:0] litedramcore_dfi_p1_bank = 3'd0;
-reg litedramcore_dfi_p1_cas_n = 1'd1;
-reg litedramcore_dfi_p1_cs_n = 1'd1;
-reg litedramcore_dfi_p1_ras_n = 1'd1;
-reg litedramcore_dfi_p1_we_n = 1'd1;
-wire litedramcore_dfi_p1_cke;
-wire litedramcore_dfi_p1_odt;
-wire litedramcore_dfi_p1_reset_n;
-reg litedramcore_dfi_p1_act_n = 1'd1;
-wire [31:0] litedramcore_dfi_p1_wrdata;
-reg litedramcore_dfi_p1_wrdata_en = 1'd0;
-wire [3:0] litedramcore_dfi_p1_wrdata_mask;
-reg litedramcore_dfi_p1_rddata_en = 1'd0;
-wire [31:0] litedramcore_dfi_p1_rddata;
-wire litedramcore_dfi_p1_rddata_valid;
-reg [14:0] litedramcore_dfi_p2_address = 15'd0;
-reg [2:0] litedramcore_dfi_p2_bank = 3'd0;
-reg litedramcore_dfi_p2_cas_n = 1'd1;
-reg litedramcore_dfi_p2_cs_n = 1'd1;
-reg litedramcore_dfi_p2_ras_n = 1'd1;
-reg litedramcore_dfi_p2_we_n = 1'd1;
-wire litedramcore_dfi_p2_cke;
-wire litedramcore_dfi_p2_odt;
-wire litedramcore_dfi_p2_reset_n;
-reg litedramcore_dfi_p2_act_n = 1'd1;
-wire [31:0] litedramcore_dfi_p2_wrdata;
-reg litedramcore_dfi_p2_wrdata_en = 1'd0;
-wire [3:0] litedramcore_dfi_p2_wrdata_mask;
-reg litedramcore_dfi_p2_rddata_en = 1'd0;
-wire [31:0] litedramcore_dfi_p2_rddata;
-wire litedramcore_dfi_p2_rddata_valid;
-reg [14:0] litedramcore_dfi_p3_address = 15'd0;
-reg [2:0] litedramcore_dfi_p3_bank = 3'd0;
-reg litedramcore_dfi_p3_cas_n = 1'd1;
-reg litedramcore_dfi_p3_cs_n = 1'd1;
-reg litedramcore_dfi_p3_ras_n = 1'd1;
-reg litedramcore_dfi_p3_we_n = 1'd1;
-wire litedramcore_dfi_p3_cke;
-wire litedramcore_dfi_p3_odt;
-wire litedramcore_dfi_p3_reset_n;
-reg litedramcore_dfi_p3_act_n = 1'd1;
-wire [31:0] litedramcore_dfi_p3_wrdata;
-reg litedramcore_dfi_p3_wrdata_en = 1'd0;
-wire [3:0] litedramcore_dfi_p3_wrdata_mask;
-reg litedramcore_dfi_p3_rddata_en = 1'd0;
-wire [31:0] litedramcore_dfi_p3_rddata;
-wire litedramcore_dfi_p3_rddata_valid;
-reg litedramcore_cmd_valid = 1'd0;
-reg litedramcore_cmd_ready = 1'd0;
-reg litedramcore_cmd_last = 1'd0;
-reg [14:0] litedramcore_cmd_payload_a = 15'd0;
-reg [2:0] litedramcore_cmd_payload_ba = 3'd0;
-reg litedramcore_cmd_payload_cas = 1'd0;
-reg litedramcore_cmd_payload_ras = 1'd0;
-reg litedramcore_cmd_payload_we = 1'd0;
-reg litedramcore_cmd_payload_is_read = 1'd0;
-reg litedramcore_cmd_payload_is_write = 1'd0;
-wire litedramcore_wants_refresh;
-wire litedramcore_wants_zqcs;
-wire litedramcore_timer_wait;
-wire litedramcore_timer_done0;
-wire [9:0] litedramcore_timer_count0;
-wire litedramcore_timer_done1;
-reg [9:0] litedramcore_timer_count1 = 10'd781;
-wire litedramcore_postponer_req_i;
-reg litedramcore_postponer_req_o = 1'd0;
-reg litedramcore_postponer_count = 1'd0;
-reg litedramcore_sequencer_start0 = 1'd0;
-wire litedramcore_sequencer_done0;
-wire litedramcore_sequencer_start1;
-reg litedramcore_sequencer_done1 = 1'd0;
-reg [5:0] litedramcore_sequencer_counter = 6'd0;
-reg litedramcore_sequencer_count = 1'd0;
-wire litedramcore_zqcs_timer_wait;
-wire litedramcore_zqcs_timer_done0;
-wire [26:0] litedramcore_zqcs_timer_count0;
-wire litedramcore_zqcs_timer_done1;
-reg [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999;
-reg litedramcore_zqcs_executer_start = 1'd0;
-reg litedramcore_zqcs_executer_done = 1'd0;
-reg [4:0] litedramcore_zqcs_executer_counter = 5'd0;
-wire litedramcore_bankmachine0_req_valid;
-wire litedramcore_bankmachine0_req_ready;
-wire litedramcore_bankmachine0_req_we;
-wire [21:0] litedramcore_bankmachine0_req_addr;
-wire litedramcore_bankmachine0_req_lock;
-reg litedramcore_bankmachine0_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine0_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine0_refresh_req;
-reg litedramcore_bankmachine0_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine0_cmd_valid = 1'd0;
-reg litedramcore_bankmachine0_cmd_ready = 1'd0;
-reg [14:0] litedramcore_bankmachine0_cmd_payload_a = 15'd0;
-wire [2:0] litedramcore_bankmachine0_cmd_payload_ba;
-reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine0_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine0_auto_precharge = 1'd0;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
-wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
-wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-reg [4:0] litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we;
-wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine0_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine0_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine0_cmd_buffer_sink_first;
-wire litedramcore_bankmachine0_cmd_buffer_sink_last;
-wire litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
-wire [21:0] litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine0_cmd_buffer_source_ready;
-reg litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] litedramcore_bankmachine0_row = 15'd0;
-reg litedramcore_bankmachine0_row_opened = 1'd0;
-wire litedramcore_bankmachine0_row_hit;
-reg litedramcore_bankmachine0_row_open = 1'd0;
-reg litedramcore_bankmachine0_row_close = 1'd0;
-reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine0_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine0_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine0_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine0_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine0_trccon_count = 3'd0;
-wire litedramcore_bankmachine0_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine0_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine0_trascon_count = 3'd0;
-wire litedramcore_bankmachine1_req_valid;
-wire litedramcore_bankmachine1_req_ready;
-wire litedramcore_bankmachine1_req_we;
-wire [21:0] litedramcore_bankmachine1_req_addr;
-wire litedramcore_bankmachine1_req_lock;
-reg litedramcore_bankmachine1_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine1_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine1_refresh_req;
-reg litedramcore_bankmachine1_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine1_cmd_valid = 1'd0;
-reg litedramcore_bankmachine1_cmd_ready = 1'd0;
-reg [14:0] litedramcore_bankmachine1_cmd_payload_a = 15'd0;
-wire [2:0] litedramcore_bankmachine1_cmd_payload_ba;
-reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine1_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine1_auto_precharge = 1'd0;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
-wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
-wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-reg [4:0] litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we;
-wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine1_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine1_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine1_cmd_buffer_sink_first;
-wire litedramcore_bankmachine1_cmd_buffer_sink_last;
-wire litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
-wire [21:0] litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine1_cmd_buffer_source_ready;
-reg litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] litedramcore_bankmachine1_row = 15'd0;
-reg litedramcore_bankmachine1_row_opened = 1'd0;
-wire litedramcore_bankmachine1_row_hit;
-reg litedramcore_bankmachine1_row_open = 1'd0;
-reg litedramcore_bankmachine1_row_close = 1'd0;
-reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine1_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine1_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine1_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine1_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine1_trccon_count = 3'd0;
-wire litedramcore_bankmachine1_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine1_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine1_trascon_count = 3'd0;
-wire litedramcore_bankmachine2_req_valid;
-wire litedramcore_bankmachine2_req_ready;
-wire litedramcore_bankmachine2_req_we;
-wire [21:0] litedramcore_bankmachine2_req_addr;
-wire litedramcore_bankmachine2_req_lock;
-reg litedramcore_bankmachine2_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine2_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine2_refresh_req;
-reg litedramcore_bankmachine2_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine2_cmd_valid = 1'd0;
-reg litedramcore_bankmachine2_cmd_ready = 1'd0;
-reg [14:0] litedramcore_bankmachine2_cmd_payload_a = 15'd0;
-wire [2:0] litedramcore_bankmachine2_cmd_payload_ba;
-reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine2_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine2_auto_precharge = 1'd0;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
-wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
-wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-reg [4:0] litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we;
-wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine2_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine2_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine2_cmd_buffer_sink_first;
-wire litedramcore_bankmachine2_cmd_buffer_sink_last;
-wire litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
-wire [21:0] litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine2_cmd_buffer_source_ready;
-reg litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] litedramcore_bankmachine2_row = 15'd0;
-reg litedramcore_bankmachine2_row_opened = 1'd0;
-wire litedramcore_bankmachine2_row_hit;
-reg litedramcore_bankmachine2_row_open = 1'd0;
-reg litedramcore_bankmachine2_row_close = 1'd0;
-reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine2_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine2_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine2_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine2_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine2_trccon_count = 3'd0;
-wire litedramcore_bankmachine2_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine2_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine2_trascon_count = 3'd0;
-wire litedramcore_bankmachine3_req_valid;
-wire litedramcore_bankmachine3_req_ready;
-wire litedramcore_bankmachine3_req_we;
-wire [21:0] litedramcore_bankmachine3_req_addr;
-wire litedramcore_bankmachine3_req_lock;
-reg litedramcore_bankmachine3_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine3_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine3_refresh_req;
-reg litedramcore_bankmachine3_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine3_cmd_valid = 1'd0;
-reg litedramcore_bankmachine3_cmd_ready = 1'd0;
-reg [14:0] litedramcore_bankmachine3_cmd_payload_a = 15'd0;
-wire [2:0] litedramcore_bankmachine3_cmd_payload_ba;
-reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine3_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine3_auto_precharge = 1'd0;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
-wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
-wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-reg [4:0] litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we;
-wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine3_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine3_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine3_cmd_buffer_sink_first;
-wire litedramcore_bankmachine3_cmd_buffer_sink_last;
-wire litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
-wire [21:0] litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine3_cmd_buffer_source_ready;
-reg litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] litedramcore_bankmachine3_row = 15'd0;
-reg litedramcore_bankmachine3_row_opened = 1'd0;
-wire litedramcore_bankmachine3_row_hit;
-reg litedramcore_bankmachine3_row_open = 1'd0;
-reg litedramcore_bankmachine3_row_close = 1'd0;
-reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine3_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine3_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine3_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine3_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine3_trccon_count = 3'd0;
-wire litedramcore_bankmachine3_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine3_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine3_trascon_count = 3'd0;
-wire litedramcore_bankmachine4_req_valid;
-wire litedramcore_bankmachine4_req_ready;
-wire litedramcore_bankmachine4_req_we;
-wire [21:0] litedramcore_bankmachine4_req_addr;
-wire litedramcore_bankmachine4_req_lock;
-reg litedramcore_bankmachine4_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine4_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine4_refresh_req;
-reg litedramcore_bankmachine4_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine4_cmd_valid = 1'd0;
-reg litedramcore_bankmachine4_cmd_ready = 1'd0;
-reg [14:0] litedramcore_bankmachine4_cmd_payload_a = 15'd0;
-wire [2:0] litedramcore_bankmachine4_cmd_payload_ba;
-reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine4_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine4_auto_precharge = 1'd0;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
-wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
-wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-reg [4:0] litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we;
-wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine4_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine4_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine4_cmd_buffer_sink_first;
-wire litedramcore_bankmachine4_cmd_buffer_sink_last;
-wire litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
-wire [21:0] litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine4_cmd_buffer_source_ready;
-reg litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] litedramcore_bankmachine4_row = 15'd0;
-reg litedramcore_bankmachine4_row_opened = 1'd0;
-wire litedramcore_bankmachine4_row_hit;
-reg litedramcore_bankmachine4_row_open = 1'd0;
-reg litedramcore_bankmachine4_row_close = 1'd0;
-reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine4_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine4_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine4_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine4_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine4_trccon_count = 3'd0;
-wire litedramcore_bankmachine4_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine4_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine4_trascon_count = 3'd0;
-wire litedramcore_bankmachine5_req_valid;
-wire litedramcore_bankmachine5_req_ready;
-wire litedramcore_bankmachine5_req_we;
-wire [21:0] litedramcore_bankmachine5_req_addr;
-wire litedramcore_bankmachine5_req_lock;
-reg litedramcore_bankmachine5_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine5_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine5_refresh_req;
-reg litedramcore_bankmachine5_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine5_cmd_valid = 1'd0;
-reg litedramcore_bankmachine5_cmd_ready = 1'd0;
-reg [14:0] litedramcore_bankmachine5_cmd_payload_a = 15'd0;
-wire [2:0] litedramcore_bankmachine5_cmd_payload_ba;
-reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine5_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine5_auto_precharge = 1'd0;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
-wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
-wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-reg [4:0] litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we;
-wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine5_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine5_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine5_cmd_buffer_sink_first;
-wire litedramcore_bankmachine5_cmd_buffer_sink_last;
-wire litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
-wire [21:0] litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine5_cmd_buffer_source_ready;
-reg litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] litedramcore_bankmachine5_row = 15'd0;
-reg litedramcore_bankmachine5_row_opened = 1'd0;
-wire litedramcore_bankmachine5_row_hit;
-reg litedramcore_bankmachine5_row_open = 1'd0;
-reg litedramcore_bankmachine5_row_close = 1'd0;
-reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine5_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine5_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine5_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine5_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine5_trccon_count = 3'd0;
-wire litedramcore_bankmachine5_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine5_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine5_trascon_count = 3'd0;
-wire litedramcore_bankmachine6_req_valid;
-wire litedramcore_bankmachine6_req_ready;
-wire litedramcore_bankmachine6_req_we;
-wire [21:0] litedramcore_bankmachine6_req_addr;
-wire litedramcore_bankmachine6_req_lock;
-reg litedramcore_bankmachine6_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine6_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine6_refresh_req;
-reg litedramcore_bankmachine6_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine6_cmd_valid = 1'd0;
-reg litedramcore_bankmachine6_cmd_ready = 1'd0;
-reg [14:0] litedramcore_bankmachine6_cmd_payload_a = 15'd0;
-wire [2:0] litedramcore_bankmachine6_cmd_payload_ba;
-reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine6_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine6_auto_precharge = 1'd0;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
-wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
-wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-reg [4:0] litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we;
-wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine6_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine6_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine6_cmd_buffer_sink_first;
-wire litedramcore_bankmachine6_cmd_buffer_sink_last;
-wire litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
-wire [21:0] litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine6_cmd_buffer_source_ready;
-reg litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] litedramcore_bankmachine6_row = 15'd0;
-reg litedramcore_bankmachine6_row_opened = 1'd0;
-wire litedramcore_bankmachine6_row_hit;
-reg litedramcore_bankmachine6_row_open = 1'd0;
-reg litedramcore_bankmachine6_row_close = 1'd0;
-reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine6_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine6_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine6_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine6_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine6_trccon_count = 3'd0;
-wire litedramcore_bankmachine6_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine6_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine6_trascon_count = 3'd0;
-wire litedramcore_bankmachine7_req_valid;
-wire litedramcore_bankmachine7_req_ready;
-wire litedramcore_bankmachine7_req_we;
-wire [21:0] litedramcore_bankmachine7_req_addr;
-wire litedramcore_bankmachine7_req_lock;
-reg litedramcore_bankmachine7_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine7_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine7_refresh_req;
-reg litedramcore_bankmachine7_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine7_cmd_valid = 1'd0;
-reg litedramcore_bankmachine7_cmd_ready = 1'd0;
-reg [14:0] litedramcore_bankmachine7_cmd_payload_a = 15'd0;
-wire [2:0] litedramcore_bankmachine7_cmd_payload_ba;
-reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine7_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine7_auto_precharge = 1'd0;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
-wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
-wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-reg [4:0] litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we;
-wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine7_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine7_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine7_cmd_buffer_sink_first;
-wire litedramcore_bankmachine7_cmd_buffer_sink_last;
-wire litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
-wire [21:0] litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine7_cmd_buffer_source_ready;
-reg litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] litedramcore_bankmachine7_row = 15'd0;
-reg litedramcore_bankmachine7_row_opened = 1'd0;
-wire litedramcore_bankmachine7_row_hit;
-reg litedramcore_bankmachine7_row_open = 1'd0;
-reg litedramcore_bankmachine7_row_close = 1'd0;
-reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine7_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine7_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine7_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine7_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine7_trccon_count = 3'd0;
-wire litedramcore_bankmachine7_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine7_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine7_trascon_count = 3'd0;
-wire litedramcore_ras_allowed;
-wire litedramcore_cas_allowed;
-wire [1:0] litedramcore_rdcmdphase;
-wire [1:0] litedramcore_wrcmdphase;
-reg litedramcore_choose_cmd_want_reads = 1'd0;
-reg litedramcore_choose_cmd_want_writes = 1'd0;
-reg litedramcore_choose_cmd_want_cmds = 1'd0;
-reg litedramcore_choose_cmd_want_activates = 1'd0;
-wire litedramcore_choose_cmd_cmd_valid;
-reg litedramcore_choose_cmd_cmd_ready = 1'd0;
-wire [14:0] litedramcore_choose_cmd_cmd_payload_a;
-wire [2:0] litedramcore_choose_cmd_cmd_payload_ba;
-reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
-reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
-reg litedramcore_choose_cmd_cmd_payload_we = 1'd0;
-wire litedramcore_choose_cmd_cmd_payload_is_cmd;
-wire litedramcore_choose_cmd_cmd_payload_is_read;
-wire litedramcore_choose_cmd_cmd_payload_is_write;
-reg [7:0] litedramcore_choose_cmd_valids = 8'd0;
-wire [7:0] litedramcore_choose_cmd_request;
-reg [2:0] litedramcore_choose_cmd_grant = 3'd0;
-wire litedramcore_choose_cmd_ce;
-reg litedramcore_choose_req_want_reads = 1'd0;
-reg litedramcore_choose_req_want_writes = 1'd0;
-reg litedramcore_choose_req_want_cmds = 1'd0;
-reg litedramcore_choose_req_want_activates = 1'd0;
-wire litedramcore_choose_req_cmd_valid;
-reg litedramcore_choose_req_cmd_ready = 1'd0;
-wire [14:0] litedramcore_choose_req_cmd_payload_a;
-wire [2:0] litedramcore_choose_req_cmd_payload_ba;
-reg litedramcore_choose_req_cmd_payload_cas = 1'd0;
-reg litedramcore_choose_req_cmd_payload_ras = 1'd0;
-reg litedramcore_choose_req_cmd_payload_we = 1'd0;
-wire litedramcore_choose_req_cmd_payload_is_cmd;
-wire litedramcore_choose_req_cmd_payload_is_read;
-wire litedramcore_choose_req_cmd_payload_is_write;
-reg [7:0] litedramcore_choose_req_valids = 8'd0;
-wire [7:0] litedramcore_choose_req_request;
-reg [2:0] litedramcore_choose_req_grant = 3'd0;
-wire litedramcore_choose_req_ce;
-reg [14:0] litedramcore_nop_a = 15'd0;
-reg [2:0] litedramcore_nop_ba = 3'd0;
-reg [1:0] litedramcore_steerer_sel0 = 2'd0;
-reg [1:0] litedramcore_steerer_sel1 = 2'd0;
-reg [1:0] litedramcore_steerer_sel2 = 2'd0;
-reg [1:0] litedramcore_steerer_sel3 = 2'd0;
-reg litedramcore_steerer0 = 1'd1;
-reg litedramcore_steerer1 = 1'd1;
-reg litedramcore_steerer2 = 1'd1;
-reg litedramcore_steerer3 = 1'd1;
-reg litedramcore_steerer4 = 1'd1;
-reg litedramcore_steerer5 = 1'd1;
-reg litedramcore_steerer6 = 1'd1;
-reg litedramcore_steerer7 = 1'd1;
-wire litedramcore_trrdcon_valid;
-(* dont_touch = "true" *) reg litedramcore_trrdcon_ready = 1'd0;
-reg litedramcore_trrdcon_count = 1'd0;
-wire litedramcore_tfawcon_valid;
-(* dont_touch = "true" *) reg litedramcore_tfawcon_ready = 1'd1;
-wire [2:0] litedramcore_tfawcon_count;
-reg [4:0] litedramcore_tfawcon_window = 5'd0;
-wire litedramcore_tccdcon_valid;
-(* dont_touch = "true" *) reg litedramcore_tccdcon_ready = 1'd0;
-reg litedramcore_tccdcon_count = 1'd0;
-wire litedramcore_twtrcon_valid;
-(* dont_touch = "true" *) reg litedramcore_twtrcon_ready = 1'd0;
-reg [2:0] litedramcore_twtrcon_count = 3'd0;
-wire litedramcore_read_available;
-wire litedramcore_write_available;
-reg litedramcore_en0 = 1'd0;
-wire litedramcore_max_time0;
-reg [4:0] litedramcore_time0 = 5'd0;
-reg litedramcore_en1 = 1'd0;
-wire litedramcore_max_time1;
-reg [3:0] litedramcore_time1 = 4'd0;
-wire litedramcore_go_to_refresh;
-reg init_done_storage = 1'd0;
-reg init_done_re = 1'd0;
-reg init_error_storage = 1'd0;
-reg init_error_re = 1'd0;
-wire [29:0] wb_bus_adr;
-wire [31:0] wb_bus_dat_w;
-wire [31:0] wb_bus_dat_r;
-wire [3:0] wb_bus_sel;
-wire wb_bus_cyc;
-wire wb_bus_stb;
-wire wb_bus_ack;
-wire wb_bus_we;
-wire [2:0] wb_bus_cti;
-wire [1:0] wb_bus_bte;
-wire wb_bus_err;
-wire user_enable;
-wire user_port_cmd_valid;
-wire user_port_cmd_ready;
-wire user_port_cmd_payload_we;
-wire [24:0] user_port_cmd_payload_addr;
-wire user_port_wdata_valid;
-wire user_port_wdata_ready;
-wire [127:0] user_port_wdata_payload_data;
-wire [15:0] user_port_wdata_payload_we;
-wire user_port_rdata_valid;
-wire user_port_rdata_ready;
-wire [127:0] user_port_rdata_payload_data;
-reg [13:0] litedramcore_adr = 14'd0;
-reg litedramcore_we = 1'd0;
-reg [31:0] litedramcore_dat_w = 32'd0;
-wire [31:0] litedramcore_dat_r;
-wire [29:0] litedramcore_wishbone_adr;
-wire [31:0] litedramcore_wishbone_dat_w;
-reg [31:0] litedramcore_wishbone_dat_r = 32'd0;
-wire [3:0] litedramcore_wishbone_sel;
-wire litedramcore_wishbone_cyc;
-wire litedramcore_wishbone_stb;
-reg litedramcore_wishbone_ack = 1'd0;
-wire litedramcore_wishbone_we;
-wire [2:0] litedramcore_wishbone_cti;
-wire [1:0] litedramcore_wishbone_bte;
-reg litedramcore_wishbone_err = 1'd0;
-wire [13:0] interface0_bank_bus_adr;
-wire interface0_bank_bus_we;
-wire [31:0] interface0_bank_bus_dat_w;
-reg [31:0] interface0_bank_bus_dat_r = 32'd0;
-reg csrbank0_init_done0_re = 1'd0;
-wire csrbank0_init_done0_r;
-reg csrbank0_init_done0_we = 1'd0;
-wire csrbank0_init_done0_w;
-reg csrbank0_init_error0_re = 1'd0;
-wire csrbank0_init_error0_r;
-reg csrbank0_init_error0_we = 1'd0;
-wire csrbank0_init_error0_w;
-wire csrbank0_sel;
-wire [13:0] interface1_bank_bus_adr;
-wire interface1_bank_bus_we;
-wire [31:0] interface1_bank_bus_dat_w;
-reg [31:0] interface1_bank_bus_dat_r = 32'd0;
-reg csrbank1_rst0_re = 1'd0;
-wire csrbank1_rst0_r;
-reg csrbank1_rst0_we = 1'd0;
-wire csrbank1_rst0_w;
-reg csrbank1_dly_sel0_re = 1'd0;
-wire [1:0] csrbank1_dly_sel0_r;
-reg csrbank1_dly_sel0_we = 1'd0;
-wire [1:0] csrbank1_dly_sel0_w;
-reg csrbank1_half_sys8x_taps0_re = 1'd0;
-wire [4:0] csrbank1_half_sys8x_taps0_r;
-reg csrbank1_half_sys8x_taps0_we = 1'd0;
-wire [4:0] csrbank1_half_sys8x_taps0_w;
-reg csrbank1_wlevel_en0_re = 1'd0;
-wire csrbank1_wlevel_en0_r;
-reg csrbank1_wlevel_en0_we = 1'd0;
-wire csrbank1_wlevel_en0_w;
-reg csrbank1_rdphase0_re = 1'd0;
-wire [1:0] csrbank1_rdphase0_r;
-reg csrbank1_rdphase0_we = 1'd0;
-wire [1:0] csrbank1_rdphase0_w;
-reg csrbank1_wrphase0_re = 1'd0;
-wire [1:0] csrbank1_wrphase0_r;
-reg csrbank1_wrphase0_we = 1'd0;
-wire [1:0] csrbank1_wrphase0_w;
-wire csrbank1_sel;
-wire [13:0] interface2_bank_bus_adr;
-wire interface2_bank_bus_we;
-wire [31:0] interface2_bank_bus_dat_w;
-reg [31:0] interface2_bank_bus_dat_r = 32'd0;
-reg csrbank2_dfii_control0_re = 1'd0;
-wire [3:0] csrbank2_dfii_control0_r;
-reg csrbank2_dfii_control0_we = 1'd0;
-wire [3:0] csrbank2_dfii_control0_w;
-reg csrbank2_dfii_pi0_command0_re = 1'd0;
-wire [5:0] csrbank2_dfii_pi0_command0_r;
-reg csrbank2_dfii_pi0_command0_we = 1'd0;
-wire [5:0] csrbank2_dfii_pi0_command0_w;
-reg csrbank2_dfii_pi0_address0_re = 1'd0;
-wire [14:0] csrbank2_dfii_pi0_address0_r;
-reg csrbank2_dfii_pi0_address0_we = 1'd0;
-wire [14:0] csrbank2_dfii_pi0_address0_w;
-reg csrbank2_dfii_pi0_baddress0_re = 1'd0;
-wire [2:0] csrbank2_dfii_pi0_baddress0_r;
-reg csrbank2_dfii_pi0_baddress0_we = 1'd0;
-wire [2:0] csrbank2_dfii_pi0_baddress0_w;
-reg csrbank2_dfii_pi0_wrdata0_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi0_wrdata0_r;
-reg csrbank2_dfii_pi0_wrdata0_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi0_wrdata0_w;
-reg csrbank2_dfii_pi0_rddata_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi0_rddata_r;
-reg csrbank2_dfii_pi0_rddata_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi0_rddata_w;
-reg csrbank2_dfii_pi1_command0_re = 1'd0;
-wire [5:0] csrbank2_dfii_pi1_command0_r;
-reg csrbank2_dfii_pi1_command0_we = 1'd0;
-wire [5:0] csrbank2_dfii_pi1_command0_w;
-reg csrbank2_dfii_pi1_address0_re = 1'd0;
-wire [14:0] csrbank2_dfii_pi1_address0_r;
-reg csrbank2_dfii_pi1_address0_we = 1'd0;
-wire [14:0] csrbank2_dfii_pi1_address0_w;
-reg csrbank2_dfii_pi1_baddress0_re = 1'd0;
-wire [2:0] csrbank2_dfii_pi1_baddress0_r;
-reg csrbank2_dfii_pi1_baddress0_we = 1'd0;
-wire [2:0] csrbank2_dfii_pi1_baddress0_w;
-reg csrbank2_dfii_pi1_wrdata0_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi1_wrdata0_r;
-reg csrbank2_dfii_pi1_wrdata0_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi1_wrdata0_w;
-reg csrbank2_dfii_pi1_rddata_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi1_rddata_r;
-reg csrbank2_dfii_pi1_rddata_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi1_rddata_w;
-reg csrbank2_dfii_pi2_command0_re = 1'd0;
-wire [5:0] csrbank2_dfii_pi2_command0_r;
-reg csrbank2_dfii_pi2_command0_we = 1'd0;
-wire [5:0] csrbank2_dfii_pi2_command0_w;
-reg csrbank2_dfii_pi2_address0_re = 1'd0;
-wire [14:0] csrbank2_dfii_pi2_address0_r;
-reg csrbank2_dfii_pi2_address0_we = 1'd0;
-wire [14:0] csrbank2_dfii_pi2_address0_w;
-reg csrbank2_dfii_pi2_baddress0_re = 1'd0;
-wire [2:0] csrbank2_dfii_pi2_baddress0_r;
-reg csrbank2_dfii_pi2_baddress0_we = 1'd0;
-wire [2:0] csrbank2_dfii_pi2_baddress0_w;
-reg csrbank2_dfii_pi2_wrdata0_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi2_wrdata0_r;
-reg csrbank2_dfii_pi2_wrdata0_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi2_wrdata0_w;
-reg csrbank2_dfii_pi2_rddata_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi2_rddata_r;
-reg csrbank2_dfii_pi2_rddata_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi2_rddata_w;
-reg csrbank2_dfii_pi3_command0_re = 1'd0;
-wire [5:0] csrbank2_dfii_pi3_command0_r;
-reg csrbank2_dfii_pi3_command0_we = 1'd0;
-wire [5:0] csrbank2_dfii_pi3_command0_w;
-reg csrbank2_dfii_pi3_address0_re = 1'd0;
-wire [14:0] csrbank2_dfii_pi3_address0_r;
-reg csrbank2_dfii_pi3_address0_we = 1'd0;
-wire [14:0] csrbank2_dfii_pi3_address0_w;
-reg csrbank2_dfii_pi3_baddress0_re = 1'd0;
-wire [2:0] csrbank2_dfii_pi3_baddress0_r;
-reg csrbank2_dfii_pi3_baddress0_we = 1'd0;
-wire [2:0] csrbank2_dfii_pi3_baddress0_w;
-reg csrbank2_dfii_pi3_wrdata0_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi3_wrdata0_r;
-reg csrbank2_dfii_pi3_wrdata0_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi3_wrdata0_w;
-reg csrbank2_dfii_pi3_rddata_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi3_rddata_r;
-reg csrbank2_dfii_pi3_rddata_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi3_rddata_w;
-wire csrbank2_sel;
-wire [13:0] csr_interconnect_adr;
-wire csr_interconnect_we;
-wire [31:0] csr_interconnect_dat_w;
-wire [31:0] csr_interconnect_dat_r;
-wire litedramcore_reset0;
-wire litedramcore_reset1;
-wire litedramcore_reset2;
-wire litedramcore_reset3;
-wire litedramcore_reset4;
-wire litedramcore_reset5;
-wire litedramcore_reset6;
-wire litedramcore_reset7;
-wire litedramcore_pll_fb;
-reg [1:0] litedramcore_refresher_state = 2'd0;
-reg [1:0] litedramcore_refresher_next_state = 2'd0;
-reg [3:0] litedramcore_bankmachine0_state = 4'd0;
-reg [3:0] litedramcore_bankmachine0_next_state = 4'd0;
-reg [3:0] litedramcore_bankmachine1_state = 4'd0;
-reg [3:0] litedramcore_bankmachine1_next_state = 4'd0;
-reg [3:0] litedramcore_bankmachine2_state = 4'd0;
-reg [3:0] litedramcore_bankmachine2_next_state = 4'd0;
-reg [3:0] litedramcore_bankmachine3_state = 4'd0;
-reg [3:0] litedramcore_bankmachine3_next_state = 4'd0;
-reg [3:0] litedramcore_bankmachine4_state = 4'd0;
-reg [3:0] litedramcore_bankmachine4_next_state = 4'd0;
-reg [3:0] litedramcore_bankmachine5_state = 4'd0;
-reg [3:0] litedramcore_bankmachine5_next_state = 4'd0;
-reg [3:0] litedramcore_bankmachine6_state = 4'd0;
-reg [3:0] litedramcore_bankmachine6_next_state = 4'd0;
-reg [3:0] litedramcore_bankmachine7_state = 4'd0;
-reg [3:0] litedramcore_bankmachine7_next_state = 4'd0;
-reg [3:0] litedramcore_multiplexer_state = 4'd0;
-reg [3:0] litedramcore_multiplexer_next_state = 4'd0;
-wire litedramcore_roundrobin0_request;
-wire litedramcore_roundrobin0_grant;
-wire litedramcore_roundrobin0_ce;
-wire litedramcore_roundrobin1_request;
-wire litedramcore_roundrobin1_grant;
-wire litedramcore_roundrobin1_ce;
-wire litedramcore_roundrobin2_request;
-wire litedramcore_roundrobin2_grant;
-wire litedramcore_roundrobin2_ce;
-wire litedramcore_roundrobin3_request;
-wire litedramcore_roundrobin3_grant;
-wire litedramcore_roundrobin3_ce;
-wire litedramcore_roundrobin4_request;
-wire litedramcore_roundrobin4_grant;
-wire litedramcore_roundrobin4_ce;
-wire litedramcore_roundrobin5_request;
-wire litedramcore_roundrobin5_grant;
-wire litedramcore_roundrobin5_ce;
-wire litedramcore_roundrobin6_request;
-wire litedramcore_roundrobin6_grant;
-wire litedramcore_roundrobin6_ce;
-wire litedramcore_roundrobin7_request;
-wire litedramcore_roundrobin7_grant;
-wire litedramcore_roundrobin7_ce;
-reg litedramcore_locked0 = 1'd0;
-reg litedramcore_locked1 = 1'd0;
-reg litedramcore_locked2 = 1'd0;
-reg litedramcore_locked3 = 1'd0;
-reg litedramcore_locked4 = 1'd0;
-reg litedramcore_locked5 = 1'd0;
-reg litedramcore_locked6 = 1'd0;
-reg litedramcore_locked7 = 1'd0;
-reg litedramcore_new_master_wdata_ready0 = 1'd0;
-reg litedramcore_new_master_wdata_ready1 = 1'd0;
-reg litedramcore_new_master_rdata_valid0 = 1'd0;
-reg litedramcore_new_master_rdata_valid1 = 1'd0;
-reg litedramcore_new_master_rdata_valid2 = 1'd0;
-reg litedramcore_new_master_rdata_valid3 = 1'd0;
-reg litedramcore_new_master_rdata_valid4 = 1'd0;
-reg litedramcore_new_master_rdata_valid5 = 1'd0;
-reg litedramcore_new_master_rdata_valid6 = 1'd0;
-reg litedramcore_new_master_rdata_valid7 = 1'd0;
-reg litedramcore_new_master_rdata_valid8 = 1'd0;
-reg [1:0] litedramcore_state = 2'd0;
-reg [1:0] litedramcore_next_state = 2'd0;
-reg [31:0] litedramcore_dat_w_next_value0 = 32'd0;
-reg litedramcore_dat_w_next_value_ce0 = 1'd0;
-reg [13:0] litedramcore_adr_next_value1 = 14'd0;
-reg litedramcore_adr_next_value_ce1 = 1'd0;
-reg litedramcore_we_next_value2 = 1'd0;
-reg litedramcore_we_next_value_ce2 = 1'd0;
-reg rhs_array_muxed0 = 1'd0;
-reg [14:0] rhs_array_muxed1 = 15'd0;
-reg [2:0] rhs_array_muxed2 = 3'd0;
-reg rhs_array_muxed3 = 1'd0;
-reg rhs_array_muxed4 = 1'd0;
-reg rhs_array_muxed5 = 1'd0;
-reg t_array_muxed0 = 1'd0;
-reg t_array_muxed1 = 1'd0;
-reg t_array_muxed2 = 1'd0;
-reg rhs_array_muxed6 = 1'd0;
-reg [14:0] rhs_array_muxed7 = 15'd0;
-reg [2:0] rhs_array_muxed8 = 3'd0;
-reg rhs_array_muxed9 = 1'd0;
-reg rhs_array_muxed10 = 1'd0;
-reg rhs_array_muxed11 = 1'd0;
-reg t_array_muxed3 = 1'd0;
-reg t_array_muxed4 = 1'd0;
-reg t_array_muxed5 = 1'd0;
-reg [21:0] rhs_array_muxed12 = 22'd0;
-reg rhs_array_muxed13 = 1'd0;
-reg rhs_array_muxed14 = 1'd0;
-reg [21:0] rhs_array_muxed15 = 22'd0;
-reg rhs_array_muxed16 = 1'd0;
-reg rhs_array_muxed17 = 1'd0;
-reg [21:0] rhs_array_muxed18 = 22'd0;
-reg rhs_array_muxed19 = 1'd0;
-reg rhs_array_muxed20 = 1'd0;
-reg [21:0] rhs_array_muxed21 = 22'd0;
-reg rhs_array_muxed22 = 1'd0;
-reg rhs_array_muxed23 = 1'd0;
-reg [21:0] rhs_array_muxed24 = 22'd0;
-reg rhs_array_muxed25 = 1'd0;
-reg rhs_array_muxed26 = 1'd0;
-reg [21:0] rhs_array_muxed27 = 22'd0;
-reg rhs_array_muxed28 = 1'd0;
-reg rhs_array_muxed29 = 1'd0;
-reg [21:0] rhs_array_muxed30 = 22'd0;
-reg rhs_array_muxed31 = 1'd0;
-reg rhs_array_muxed32 = 1'd0;
-reg [21:0] rhs_array_muxed33 = 22'd0;
-reg rhs_array_muxed34 = 1'd0;
-reg rhs_array_muxed35 = 1'd0;
-reg [2:0] array_muxed0 = 3'd0;
-reg [14:0] array_muxed1 = 15'd0;
-reg array_muxed2 = 1'd0;
-reg array_muxed3 = 1'd0;
-reg array_muxed4 = 1'd0;
-reg array_muxed5 = 1'd0;
-reg array_muxed6 = 1'd0;
-reg [2:0] array_muxed7 = 3'd0;
-reg [14:0] array_muxed8 = 15'd0;
-reg array_muxed9 = 1'd0;
-reg array_muxed10 = 1'd0;
-reg array_muxed11 = 1'd0;
-reg array_muxed12 = 1'd0;
-reg array_muxed13 = 1'd0;
-reg [2:0] array_muxed14 = 3'd0;
-reg [14:0] array_muxed15 = 15'd0;
-reg array_muxed16 = 1'd0;
-reg array_muxed17 = 1'd0;
-reg array_muxed18 = 1'd0;
-reg array_muxed19 = 1'd0;
-reg array_muxed20 = 1'd0;
-reg [2:0] array_muxed21 = 3'd0;
-reg [14:0] array_muxed22 = 15'd0;
-reg array_muxed23 = 1'd0;
-reg array_muxed24 = 1'd0;
-reg array_muxed25 = 1'd0;
-reg array_muxed26 = 1'd0;
-reg array_muxed27 = 1'd0;
-wire xilinxasyncresetsynchronizerimpl0;
-wire xilinxasyncresetsynchronizerimpl0_rst_meta;
-wire xilinxasyncresetsynchronizerimpl1;
-wire xilinxasyncresetsynchronizerimpl1_rst_meta;
-wire xilinxasyncresetsynchronizerimpl2;
-wire xilinxasyncresetsynchronizerimpl2_rst_meta;
-wire xilinxasyncresetsynchronizerimpl2_expr;
-wire xilinxasyncresetsynchronizerimpl3;
-wire xilinxasyncresetsynchronizerimpl3_rst_meta;
-wire xilinxasyncresetsynchronizerimpl3_expr;
+reg rst_1 = 1'd0;
+wire sys_clk;
+wire sys_rst;
+wire sys4x_clk;
+wire sys4x_dqs_clk;
+wire iodelay_clk;
+wire iodelay_rst;
+wire reset;
+reg power_down = 1'd0;
+wire locked;
+wire clkin;
+wire clkout0;
+wire clkout_buf0;
+wire clkout1;
+wire clkout_buf1;
+wire clkout2;
+wire clkout_buf2;
+wire clkout3;
+wire clkout_buf3;
+reg [3:0] reset_counter = 4'd15;
+reg ic_reset = 1'd1;
+reg a7ddrphy_rst_storage = 1'd0;
+reg a7ddrphy_rst_re = 1'd0;
+reg [1:0] a7ddrphy_dly_sel_storage = 2'd0;
+reg a7ddrphy_dly_sel_re = 1'd0;
+reg [4:0] a7ddrphy_half_sys8x_taps_storage = 5'd8;
+reg a7ddrphy_half_sys8x_taps_re = 1'd0;
+reg a7ddrphy_wlevel_en_storage = 1'd0;
+reg a7ddrphy_wlevel_en_re = 1'd0;
+reg a7ddrphy_wlevel_strobe_re = 1'd0;
+wire a7ddrphy_wlevel_strobe_r;
+reg a7ddrphy_wlevel_strobe_we = 1'd0;
+reg a7ddrphy_wlevel_strobe_w = 1'd0;
+reg a7ddrphy_rdly_dq_rst_re = 1'd0;
+wire a7ddrphy_rdly_dq_rst_r;
+reg a7ddrphy_rdly_dq_rst_we = 1'd0;
+reg a7ddrphy_rdly_dq_rst_w = 1'd0;
+reg a7ddrphy_rdly_dq_inc_re = 1'd0;
+wire a7ddrphy_rdly_dq_inc_r;
+reg a7ddrphy_rdly_dq_inc_we = 1'd0;
+reg a7ddrphy_rdly_dq_inc_w = 1'd0;
+reg a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
+wire a7ddrphy_rdly_dq_bitslip_rst_r;
+reg a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
+reg a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
+reg a7ddrphy_rdly_dq_bitslip_re = 1'd0;
+wire a7ddrphy_rdly_dq_bitslip_r;
+reg a7ddrphy_rdly_dq_bitslip_we = 1'd0;
+reg a7ddrphy_rdly_dq_bitslip_w = 1'd0;
+reg a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0;
+wire a7ddrphy_wdly_dq_bitslip_rst_r;
+reg a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0;
+reg a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0;
+reg a7ddrphy_wdly_dq_bitslip_re = 1'd0;
+wire a7ddrphy_wdly_dq_bitslip_r;
+reg a7ddrphy_wdly_dq_bitslip_we = 1'd0;
+reg a7ddrphy_wdly_dq_bitslip_w = 1'd0;
+reg [1:0] a7ddrphy_rdphase_storage = 2'd2;
+reg a7ddrphy_rdphase_re = 1'd0;
+reg [1:0] a7ddrphy_wrphase_storage = 2'd3;
+reg a7ddrphy_wrphase_re = 1'd0;
+wire [14:0] a7ddrphy_dfi_p0_address;
+wire [2:0] a7ddrphy_dfi_p0_bank;
+wire a7ddrphy_dfi_p0_cas_n;
+wire a7ddrphy_dfi_p0_cs_n;
+wire a7ddrphy_dfi_p0_ras_n;
+wire a7ddrphy_dfi_p0_we_n;
+wire a7ddrphy_dfi_p0_cke;
+wire a7ddrphy_dfi_p0_odt;
+wire a7ddrphy_dfi_p0_reset_n;
+wire a7ddrphy_dfi_p0_act_n;
+wire [31:0] a7ddrphy_dfi_p0_wrdata;
+wire a7ddrphy_dfi_p0_wrdata_en;
+wire [3:0] a7ddrphy_dfi_p0_wrdata_mask;
+wire a7ddrphy_dfi_p0_rddata_en;
+reg [31:0] a7ddrphy_dfi_p0_rddata = 32'd0;
+wire a7ddrphy_dfi_p0_rddata_valid;
+wire [14:0] a7ddrphy_dfi_p1_address;
+wire [2:0] a7ddrphy_dfi_p1_bank;
+wire a7ddrphy_dfi_p1_cas_n;
+wire a7ddrphy_dfi_p1_cs_n;
+wire a7ddrphy_dfi_p1_ras_n;
+wire a7ddrphy_dfi_p1_we_n;
+wire a7ddrphy_dfi_p1_cke;
+wire a7ddrphy_dfi_p1_odt;
+wire a7ddrphy_dfi_p1_reset_n;
+wire a7ddrphy_dfi_p1_act_n;
+wire [31:0] a7ddrphy_dfi_p1_wrdata;
+wire a7ddrphy_dfi_p1_wrdata_en;
+wire [3:0] a7ddrphy_dfi_p1_wrdata_mask;
+wire a7ddrphy_dfi_p1_rddata_en;
+reg [31:0] a7ddrphy_dfi_p1_rddata = 32'd0;
+wire a7ddrphy_dfi_p1_rddata_valid;
+wire [14:0] a7ddrphy_dfi_p2_address;
+wire [2:0] a7ddrphy_dfi_p2_bank;
+wire a7ddrphy_dfi_p2_cas_n;
+wire a7ddrphy_dfi_p2_cs_n;
+wire a7ddrphy_dfi_p2_ras_n;
+wire a7ddrphy_dfi_p2_we_n;
+wire a7ddrphy_dfi_p2_cke;
+wire a7ddrphy_dfi_p2_odt;
+wire a7ddrphy_dfi_p2_reset_n;
+wire a7ddrphy_dfi_p2_act_n;
+wire [31:0] a7ddrphy_dfi_p2_wrdata;
+wire a7ddrphy_dfi_p2_wrdata_en;
+wire [3:0] a7ddrphy_dfi_p2_wrdata_mask;
+wire a7ddrphy_dfi_p2_rddata_en;
+reg [31:0] a7ddrphy_dfi_p2_rddata = 32'd0;
+wire a7ddrphy_dfi_p2_rddata_valid;
+wire [14:0] a7ddrphy_dfi_p3_address;
+wire [2:0] a7ddrphy_dfi_p3_bank;
+wire a7ddrphy_dfi_p3_cas_n;
+wire a7ddrphy_dfi_p3_cs_n;
+wire a7ddrphy_dfi_p3_ras_n;
+wire a7ddrphy_dfi_p3_we_n;
+wire a7ddrphy_dfi_p3_cke;
+wire a7ddrphy_dfi_p3_odt;
+wire a7ddrphy_dfi_p3_reset_n;
+wire a7ddrphy_dfi_p3_act_n;
+wire [31:0] a7ddrphy_dfi_p3_wrdata;
+wire a7ddrphy_dfi_p3_wrdata_en;
+wire [3:0] a7ddrphy_dfi_p3_wrdata_mask;
+wire a7ddrphy_dfi_p3_rddata_en;
+reg [31:0] a7ddrphy_dfi_p3_rddata = 32'd0;
+wire a7ddrphy_dfi_p3_rddata_valid;
+wire a7ddrphy_sd_clk_se_nodelay;
+wire [2:0] a7ddrphy_pads_ba;
+reg a7ddrphy_dqs_oe = 1'd0;
+wire a7ddrphy_dqs_preamble;
+wire a7ddrphy_dqs_postamble;
+wire a7ddrphy_dqs_oe_delay_tappeddelayline;
+reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
+reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
+reg a7ddrphy_dqspattern0 = 1'd0;
+reg a7ddrphy_dqspattern1 = 1'd0;
+reg [7:0] a7ddrphy_dqspattern_o0 = 8'd0;
+reg [7:0] a7ddrphy_dqspattern_o1 = 8'd0;
+wire a7ddrphy_dqs_o_no_delay0;
+wire a7ddrphy_dqs_t0;
+reg [7:0] a7ddrphy_bitslip00 = 8'd0;
+reg [2:0] a7ddrphy_bitslip0_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip0_r0 = 16'd0;
+wire a7ddrphy0;
+wire a7ddrphy_dqs_o_no_delay1;
+wire a7ddrphy_dqs_t1;
+reg [7:0] a7ddrphy_bitslip10 = 8'd0;
+reg [2:0] a7ddrphy_bitslip1_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip1_r0 = 16'd0;
+wire a7ddrphy1;
+reg [7:0] a7ddrphy_bitslip01 = 8'd0;
+reg [2:0] a7ddrphy_bitslip0_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip0_r1 = 16'd0;
+reg [7:0] a7ddrphy_bitslip11 = 8'd0;
+reg [2:0] a7ddrphy_bitslip1_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip1_r1 = 16'd0;
+wire a7ddrphy_dq_oe;
+wire a7ddrphy_dq_oe_delay_tappeddelayline;
+reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
+reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
+wire a7ddrphy_dq_o_nodelay0;
+wire a7ddrphy_dq_i_nodelay0;
+wire a7ddrphy_dq_i_delayed0;
+wire a7ddrphy_dq_t0;
+reg [7:0] a7ddrphy_bitslip02 = 8'd0;
+reg [2:0] a7ddrphy_bitslip0_value2 = 3'd7;
+reg [15:0] a7ddrphy_bitslip0_r2 = 16'd0;
+wire [7:0] a7ddrphy_bitslip03;
+reg [7:0] a7ddrphy_bitslip04 = 8'd0;
+reg [2:0] a7ddrphy_bitslip0_value3 = 3'd7;
+reg [15:0] a7ddrphy_bitslip0_r3 = 16'd0;
+wire a7ddrphy_dq_o_nodelay1;
+wire a7ddrphy_dq_i_nodelay1;
+wire a7ddrphy_dq_i_delayed1;
+wire a7ddrphy_dq_t1;
+reg [7:0] a7ddrphy_bitslip12 = 8'd0;
+reg [2:0] a7ddrphy_bitslip1_value2 = 3'd7;
+reg [15:0] a7ddrphy_bitslip1_r2 = 16'd0;
+wire [7:0] a7ddrphy_bitslip13;
+reg [7:0] a7ddrphy_bitslip14 = 8'd0;
+reg [2:0] a7ddrphy_bitslip1_value3 = 3'd7;
+reg [15:0] a7ddrphy_bitslip1_r3 = 16'd0;
+wire a7ddrphy_dq_o_nodelay2;
+wire a7ddrphy_dq_i_nodelay2;
+wire a7ddrphy_dq_i_delayed2;
+wire a7ddrphy_dq_t2;
+reg [7:0] a7ddrphy_bitslip20 = 8'd0;
+reg [2:0] a7ddrphy_bitslip2_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip2_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip21;
+reg [7:0] a7ddrphy_bitslip22 = 8'd0;
+reg [2:0] a7ddrphy_bitslip2_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip2_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay3;
+wire a7ddrphy_dq_i_nodelay3;
+wire a7ddrphy_dq_i_delayed3;
+wire a7ddrphy_dq_t3;
+reg [7:0] a7ddrphy_bitslip30 = 8'd0;
+reg [2:0] a7ddrphy_bitslip3_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip3_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip31;
+reg [7:0] a7ddrphy_bitslip32 = 8'd0;
+reg [2:0] a7ddrphy_bitslip3_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip3_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay4;
+wire a7ddrphy_dq_i_nodelay4;
+wire a7ddrphy_dq_i_delayed4;
+wire a7ddrphy_dq_t4;
+reg [7:0] a7ddrphy_bitslip40 = 8'd0;
+reg [2:0] a7ddrphy_bitslip4_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip4_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip41;
+reg [7:0] a7ddrphy_bitslip42 = 8'd0;
+reg [2:0] a7ddrphy_bitslip4_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip4_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay5;
+wire a7ddrphy_dq_i_nodelay5;
+wire a7ddrphy_dq_i_delayed5;
+wire a7ddrphy_dq_t5;
+reg [7:0] a7ddrphy_bitslip50 = 8'd0;
+reg [2:0] a7ddrphy_bitslip5_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip5_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip51;
+reg [7:0] a7ddrphy_bitslip52 = 8'd0;
+reg [2:0] a7ddrphy_bitslip5_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip5_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay6;
+wire a7ddrphy_dq_i_nodelay6;
+wire a7ddrphy_dq_i_delayed6;
+wire a7ddrphy_dq_t6;
+reg [7:0] a7ddrphy_bitslip60 = 8'd0;
+reg [2:0] a7ddrphy_bitslip6_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip6_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip61;
+reg [7:0] a7ddrphy_bitslip62 = 8'd0;
+reg [2:0] a7ddrphy_bitslip6_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip6_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay7;
+wire a7ddrphy_dq_i_nodelay7;
+wire a7ddrphy_dq_i_delayed7;
+wire a7ddrphy_dq_t7;
+reg [7:0] a7ddrphy_bitslip70 = 8'd0;
+reg [2:0] a7ddrphy_bitslip7_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip7_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip71;
+reg [7:0] a7ddrphy_bitslip72 = 8'd0;
+reg [2:0] a7ddrphy_bitslip7_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip7_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay8;
+wire a7ddrphy_dq_i_nodelay8;
+wire a7ddrphy_dq_i_delayed8;
+wire a7ddrphy_dq_t8;
+reg [7:0] a7ddrphy_bitslip80 = 8'd0;
+reg [2:0] a7ddrphy_bitslip8_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip8_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip81;
+reg [7:0] a7ddrphy_bitslip82 = 8'd0;
+reg [2:0] a7ddrphy_bitslip8_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip8_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay9;
+wire a7ddrphy_dq_i_nodelay9;
+wire a7ddrphy_dq_i_delayed9;
+wire a7ddrphy_dq_t9;
+reg [7:0] a7ddrphy_bitslip90 = 8'd0;
+reg [2:0] a7ddrphy_bitslip9_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip9_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip91;
+reg [7:0] a7ddrphy_bitslip92 = 8'd0;
+reg [2:0] a7ddrphy_bitslip9_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip9_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay10;
+wire a7ddrphy_dq_i_nodelay10;
+wire a7ddrphy_dq_i_delayed10;
+wire a7ddrphy_dq_t10;
+reg [7:0] a7ddrphy_bitslip100 = 8'd0;
+reg [2:0] a7ddrphy_bitslip10_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip10_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip101;
+reg [7:0] a7ddrphy_bitslip102 = 8'd0;
+reg [2:0] a7ddrphy_bitslip10_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip10_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay11;
+wire a7ddrphy_dq_i_nodelay11;
+wire a7ddrphy_dq_i_delayed11;
+wire a7ddrphy_dq_t11;
+reg [7:0] a7ddrphy_bitslip110 = 8'd0;
+reg [2:0] a7ddrphy_bitslip11_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip11_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip111;
+reg [7:0] a7ddrphy_bitslip112 = 8'd0;
+reg [2:0] a7ddrphy_bitslip11_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip11_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay12;
+wire a7ddrphy_dq_i_nodelay12;
+wire a7ddrphy_dq_i_delayed12;
+wire a7ddrphy_dq_t12;
+reg [7:0] a7ddrphy_bitslip120 = 8'd0;
+reg [2:0] a7ddrphy_bitslip12_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip12_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip121;
+reg [7:0] a7ddrphy_bitslip122 = 8'd0;
+reg [2:0] a7ddrphy_bitslip12_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip12_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay13;
+wire a7ddrphy_dq_i_nodelay13;
+wire a7ddrphy_dq_i_delayed13;
+wire a7ddrphy_dq_t13;
+reg [7:0] a7ddrphy_bitslip130 = 8'd0;
+reg [2:0] a7ddrphy_bitslip13_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip13_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip131;
+reg [7:0] a7ddrphy_bitslip132 = 8'd0;
+reg [2:0] a7ddrphy_bitslip13_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip13_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay14;
+wire a7ddrphy_dq_i_nodelay14;
+wire a7ddrphy_dq_i_delayed14;
+wire a7ddrphy_dq_t14;
+reg [7:0] a7ddrphy_bitslip140 = 8'd0;
+reg [2:0] a7ddrphy_bitslip14_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip14_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip141;
+reg [7:0] a7ddrphy_bitslip142 = 8'd0;
+reg [2:0] a7ddrphy_bitslip14_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip14_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay15;
+wire a7ddrphy_dq_i_nodelay15;
+wire a7ddrphy_dq_i_delayed15;
+wire a7ddrphy_dq_t15;
+reg [7:0] a7ddrphy_bitslip150 = 8'd0;
+reg [2:0] a7ddrphy_bitslip15_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip15_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip151;
+reg [7:0] a7ddrphy_bitslip152 = 8'd0;
+reg [2:0] a7ddrphy_bitslip15_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip15_r1 = 16'd0;
+reg a7ddrphy_rddata_en_tappeddelayline0 = 1'd0;
+reg a7ddrphy_rddata_en_tappeddelayline1 = 1'd0;
+reg a7ddrphy_rddata_en_tappeddelayline2 = 1'd0;
+reg a7ddrphy_rddata_en_tappeddelayline3 = 1'd0;
+reg a7ddrphy_rddata_en_tappeddelayline4 = 1'd0;
+reg a7ddrphy_rddata_en_tappeddelayline5 = 1'd0;
+reg a7ddrphy_rddata_en_tappeddelayline6 = 1'd0;
+reg a7ddrphy_rddata_en_tappeddelayline7 = 1'd0;
+reg a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
+reg a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
+reg a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
+wire [14:0] litedramcore_slave_p0_address;
+wire [2:0] litedramcore_slave_p0_bank;
+wire litedramcore_slave_p0_cas_n;
+wire litedramcore_slave_p0_cs_n;
+wire litedramcore_slave_p0_ras_n;
+wire litedramcore_slave_p0_we_n;
+wire litedramcore_slave_p0_cke;
+wire litedramcore_slave_p0_odt;
+wire litedramcore_slave_p0_reset_n;
+wire litedramcore_slave_p0_act_n;
+wire [31:0] litedramcore_slave_p0_wrdata;
+wire litedramcore_slave_p0_wrdata_en;
+wire [3:0] litedramcore_slave_p0_wrdata_mask;
+wire litedramcore_slave_p0_rddata_en;
+reg [31:0] litedramcore_slave_p0_rddata = 32'd0;
+reg litedramcore_slave_p0_rddata_valid = 1'd0;
+wire [14:0] litedramcore_slave_p1_address;
+wire [2:0] litedramcore_slave_p1_bank;
+wire litedramcore_slave_p1_cas_n;
+wire litedramcore_slave_p1_cs_n;
+wire litedramcore_slave_p1_ras_n;
+wire litedramcore_slave_p1_we_n;
+wire litedramcore_slave_p1_cke;
+wire litedramcore_slave_p1_odt;
+wire litedramcore_slave_p1_reset_n;
+wire litedramcore_slave_p1_act_n;
+wire [31:0] litedramcore_slave_p1_wrdata;
+wire litedramcore_slave_p1_wrdata_en;
+wire [3:0] litedramcore_slave_p1_wrdata_mask;
+wire litedramcore_slave_p1_rddata_en;
+reg [31:0] litedramcore_slave_p1_rddata = 32'd0;
+reg litedramcore_slave_p1_rddata_valid = 1'd0;
+wire [14:0] litedramcore_slave_p2_address;
+wire [2:0] litedramcore_slave_p2_bank;
+wire litedramcore_slave_p2_cas_n;
+wire litedramcore_slave_p2_cs_n;
+wire litedramcore_slave_p2_ras_n;
+wire litedramcore_slave_p2_we_n;
+wire litedramcore_slave_p2_cke;
+wire litedramcore_slave_p2_odt;
+wire litedramcore_slave_p2_reset_n;
+wire litedramcore_slave_p2_act_n;
+wire [31:0] litedramcore_slave_p2_wrdata;
+wire litedramcore_slave_p2_wrdata_en;
+wire [3:0] litedramcore_slave_p2_wrdata_mask;
+wire litedramcore_slave_p2_rddata_en;
+reg [31:0] litedramcore_slave_p2_rddata = 32'd0;
+reg litedramcore_slave_p2_rddata_valid = 1'd0;
+wire [14:0] litedramcore_slave_p3_address;
+wire [2:0] litedramcore_slave_p3_bank;
+wire litedramcore_slave_p3_cas_n;
+wire litedramcore_slave_p3_cs_n;
+wire litedramcore_slave_p3_ras_n;
+wire litedramcore_slave_p3_we_n;
+wire litedramcore_slave_p3_cke;
+wire litedramcore_slave_p3_odt;
+wire litedramcore_slave_p3_reset_n;
+wire litedramcore_slave_p3_act_n;
+wire [31:0] litedramcore_slave_p3_wrdata;
+wire litedramcore_slave_p3_wrdata_en;
+wire [3:0] litedramcore_slave_p3_wrdata_mask;
+wire litedramcore_slave_p3_rddata_en;
+reg [31:0] litedramcore_slave_p3_rddata = 32'd0;
+reg litedramcore_slave_p3_rddata_valid = 1'd0;
+reg [14:0] litedramcore_master_p0_address = 15'd0;
+reg [2:0] litedramcore_master_p0_bank = 3'd0;
+reg litedramcore_master_p0_cas_n = 1'd1;
+reg litedramcore_master_p0_cs_n = 1'd1;
+reg litedramcore_master_p0_ras_n = 1'd1;
+reg litedramcore_master_p0_we_n = 1'd1;
+reg litedramcore_master_p0_cke = 1'd0;
+reg litedramcore_master_p0_odt = 1'd0;
+reg litedramcore_master_p0_reset_n = 1'd0;
+reg litedramcore_master_p0_act_n = 1'd1;
+reg [31:0] litedramcore_master_p0_wrdata = 32'd0;
+reg litedramcore_master_p0_wrdata_en = 1'd0;
+reg [3:0] litedramcore_master_p0_wrdata_mask = 4'd0;
+reg litedramcore_master_p0_rddata_en = 1'd0;
+wire [31:0] litedramcore_master_p0_rddata;
+wire litedramcore_master_p0_rddata_valid;
+reg [14:0] litedramcore_master_p1_address = 15'd0;
+reg [2:0] litedramcore_master_p1_bank = 3'd0;
+reg litedramcore_master_p1_cas_n = 1'd1;
+reg litedramcore_master_p1_cs_n = 1'd1;
+reg litedramcore_master_p1_ras_n = 1'd1;
+reg litedramcore_master_p1_we_n = 1'd1;
+reg litedramcore_master_p1_cke = 1'd0;
+reg litedramcore_master_p1_odt = 1'd0;
+reg litedramcore_master_p1_reset_n = 1'd0;
+reg litedramcore_master_p1_act_n = 1'd1;
+reg [31:0] litedramcore_master_p1_wrdata = 32'd0;
+reg litedramcore_master_p1_wrdata_en = 1'd0;
+reg [3:0] litedramcore_master_p1_wrdata_mask = 4'd0;
+reg litedramcore_master_p1_rddata_en = 1'd0;
+wire [31:0] litedramcore_master_p1_rddata;
+wire litedramcore_master_p1_rddata_valid;
+reg [14:0] litedramcore_master_p2_address = 15'd0;
+reg [2:0] litedramcore_master_p2_bank = 3'd0;
+reg litedramcore_master_p2_cas_n = 1'd1;
+reg litedramcore_master_p2_cs_n = 1'd1;
+reg litedramcore_master_p2_ras_n = 1'd1;
+reg litedramcore_master_p2_we_n = 1'd1;
+reg litedramcore_master_p2_cke = 1'd0;
+reg litedramcore_master_p2_odt = 1'd0;
+reg litedramcore_master_p2_reset_n = 1'd0;
+reg litedramcore_master_p2_act_n = 1'd1;
+reg [31:0] litedramcore_master_p2_wrdata = 32'd0;
+reg litedramcore_master_p2_wrdata_en = 1'd0;
+reg [3:0] litedramcore_master_p2_wrdata_mask = 4'd0;
+reg litedramcore_master_p2_rddata_en = 1'd0;
+wire [31:0] litedramcore_master_p2_rddata;
+wire litedramcore_master_p2_rddata_valid;
+reg [14:0] litedramcore_master_p3_address = 15'd0;
+reg [2:0] litedramcore_master_p3_bank = 3'd0;
+reg litedramcore_master_p3_cas_n = 1'd1;
+reg litedramcore_master_p3_cs_n = 1'd1;
+reg litedramcore_master_p3_ras_n = 1'd1;
+reg litedramcore_master_p3_we_n = 1'd1;
+reg litedramcore_master_p3_cke = 1'd0;
+reg litedramcore_master_p3_odt = 1'd0;
+reg litedramcore_master_p3_reset_n = 1'd0;
+reg litedramcore_master_p3_act_n = 1'd1;
+reg [31:0] litedramcore_master_p3_wrdata = 32'd0;
+reg litedramcore_master_p3_wrdata_en = 1'd0;
+reg [3:0] litedramcore_master_p3_wrdata_mask = 4'd0;
+reg litedramcore_master_p3_rddata_en = 1'd0;
+wire [31:0] litedramcore_master_p3_rddata;
+wire litedramcore_master_p3_rddata_valid;
+wire [14:0] litedramcore_csr_dfi_p0_address;
+wire [2:0] litedramcore_csr_dfi_p0_bank;
+reg litedramcore_csr_dfi_p0_cas_n = 1'd1;
+reg litedramcore_csr_dfi_p0_cs_n = 1'd1;
+reg litedramcore_csr_dfi_p0_ras_n = 1'd1;
+reg litedramcore_csr_dfi_p0_we_n = 1'd1;
+wire litedramcore_csr_dfi_p0_cke;
+wire litedramcore_csr_dfi_p0_odt;
+wire litedramcore_csr_dfi_p0_reset_n;
+reg litedramcore_csr_dfi_p0_act_n = 1'd1;
+wire [31:0] litedramcore_csr_dfi_p0_wrdata;
+wire litedramcore_csr_dfi_p0_wrdata_en;
+wire [3:0] litedramcore_csr_dfi_p0_wrdata_mask;
+wire litedramcore_csr_dfi_p0_rddata_en;
+reg [31:0] litedramcore_csr_dfi_p0_rddata = 32'd0;
+reg litedramcore_csr_dfi_p0_rddata_valid = 1'd0;
+wire [14:0] litedramcore_csr_dfi_p1_address;
+wire [2:0] litedramcore_csr_dfi_p1_bank;
+reg litedramcore_csr_dfi_p1_cas_n = 1'd1;
+reg litedramcore_csr_dfi_p1_cs_n = 1'd1;
+reg litedramcore_csr_dfi_p1_ras_n = 1'd1;
+reg litedramcore_csr_dfi_p1_we_n = 1'd1;
+wire litedramcore_csr_dfi_p1_cke;
+wire litedramcore_csr_dfi_p1_odt;
+wire litedramcore_csr_dfi_p1_reset_n;
+reg litedramcore_csr_dfi_p1_act_n = 1'd1;
+wire [31:0] litedramcore_csr_dfi_p1_wrdata;
+wire litedramcore_csr_dfi_p1_wrdata_en;
+wire [3:0] litedramcore_csr_dfi_p1_wrdata_mask;
+wire litedramcore_csr_dfi_p1_rddata_en;
+reg [31:0] litedramcore_csr_dfi_p1_rddata = 32'd0;
+reg litedramcore_csr_dfi_p1_rddata_valid = 1'd0;
+wire [14:0] litedramcore_csr_dfi_p2_address;
+wire [2:0] litedramcore_csr_dfi_p2_bank;
+reg litedramcore_csr_dfi_p2_cas_n = 1'd1;
+reg litedramcore_csr_dfi_p2_cs_n = 1'd1;
+reg litedramcore_csr_dfi_p2_ras_n = 1'd1;
+reg litedramcore_csr_dfi_p2_we_n = 1'd1;
+wire litedramcore_csr_dfi_p2_cke;
+wire litedramcore_csr_dfi_p2_odt;
+wire litedramcore_csr_dfi_p2_reset_n;
+reg litedramcore_csr_dfi_p2_act_n = 1'd1;
+wire [31:0] litedramcore_csr_dfi_p2_wrdata;
+wire litedramcore_csr_dfi_p2_wrdata_en;
+wire [3:0] litedramcore_csr_dfi_p2_wrdata_mask;
+wire litedramcore_csr_dfi_p2_rddata_en;
+reg [31:0] litedramcore_csr_dfi_p2_rddata = 32'd0;
+reg litedramcore_csr_dfi_p2_rddata_valid = 1'd0;
+wire [14:0] litedramcore_csr_dfi_p3_address;
+wire [2:0] litedramcore_csr_dfi_p3_bank;
+reg litedramcore_csr_dfi_p3_cas_n = 1'd1;
+reg litedramcore_csr_dfi_p3_cs_n = 1'd1;
+reg litedramcore_csr_dfi_p3_ras_n = 1'd1;
+reg litedramcore_csr_dfi_p3_we_n = 1'd1;
+wire litedramcore_csr_dfi_p3_cke;
+wire litedramcore_csr_dfi_p3_odt;
+wire litedramcore_csr_dfi_p3_reset_n;
+reg litedramcore_csr_dfi_p3_act_n = 1'd1;
+wire [31:0] litedramcore_csr_dfi_p3_wrdata;
+wire litedramcore_csr_dfi_p3_wrdata_en;
+wire [3:0] litedramcore_csr_dfi_p3_wrdata_mask;
+wire litedramcore_csr_dfi_p3_rddata_en;
+reg [31:0] litedramcore_csr_dfi_p3_rddata = 32'd0;
+reg litedramcore_csr_dfi_p3_rddata_valid = 1'd0;
+reg [14:0] litedramcore_ext_dfi_p0_address = 15'd0;
+reg [2:0] litedramcore_ext_dfi_p0_bank = 3'd0;
+reg litedramcore_ext_dfi_p0_cas_n = 1'd1;
+reg litedramcore_ext_dfi_p0_cs_n = 1'd1;
+reg litedramcore_ext_dfi_p0_ras_n = 1'd1;
+reg litedramcore_ext_dfi_p0_we_n = 1'd1;
+reg litedramcore_ext_dfi_p0_cke = 1'd0;
+reg litedramcore_ext_dfi_p0_odt = 1'd0;
+reg litedramcore_ext_dfi_p0_reset_n = 1'd0;
+reg litedramcore_ext_dfi_p0_act_n = 1'd1;
+reg [31:0] litedramcore_ext_dfi_p0_wrdata = 32'd0;
+reg litedramcore_ext_dfi_p0_wrdata_en = 1'd0;
+reg [3:0] litedramcore_ext_dfi_p0_wrdata_mask = 4'd0;
+reg litedramcore_ext_dfi_p0_rddata_en = 1'd0;
+reg [31:0] litedramcore_ext_dfi_p0_rddata = 32'd0;
+reg litedramcore_ext_dfi_p0_rddata_valid = 1'd0;
+reg [14:0] litedramcore_ext_dfi_p1_address = 15'd0;
+reg [2:0] litedramcore_ext_dfi_p1_bank = 3'd0;
+reg litedramcore_ext_dfi_p1_cas_n = 1'd1;
+reg litedramcore_ext_dfi_p1_cs_n = 1'd1;
+reg litedramcore_ext_dfi_p1_ras_n = 1'd1;
+reg litedramcore_ext_dfi_p1_we_n = 1'd1;
+reg litedramcore_ext_dfi_p1_cke = 1'd0;
+reg litedramcore_ext_dfi_p1_odt = 1'd0;
+reg litedramcore_ext_dfi_p1_reset_n = 1'd0;
+reg litedramcore_ext_dfi_p1_act_n = 1'd1;
+reg [31:0] litedramcore_ext_dfi_p1_wrdata = 32'd0;
+reg litedramcore_ext_dfi_p1_wrdata_en = 1'd0;
+reg [3:0] litedramcore_ext_dfi_p1_wrdata_mask = 4'd0;
+reg litedramcore_ext_dfi_p1_rddata_en = 1'd0;
+reg [31:0] litedramcore_ext_dfi_p1_rddata = 32'd0;
+reg litedramcore_ext_dfi_p1_rddata_valid = 1'd0;
+reg [14:0] litedramcore_ext_dfi_p2_address = 15'd0;
+reg [2:0] litedramcore_ext_dfi_p2_bank = 3'd0;
+reg litedramcore_ext_dfi_p2_cas_n = 1'd1;
+reg litedramcore_ext_dfi_p2_cs_n = 1'd1;
+reg litedramcore_ext_dfi_p2_ras_n = 1'd1;
+reg litedramcore_ext_dfi_p2_we_n = 1'd1;
+reg litedramcore_ext_dfi_p2_cke = 1'd0;
+reg litedramcore_ext_dfi_p2_odt = 1'd0;
+reg litedramcore_ext_dfi_p2_reset_n = 1'd0;
+reg litedramcore_ext_dfi_p2_act_n = 1'd1;
+reg [31:0] litedramcore_ext_dfi_p2_wrdata = 32'd0;
+reg litedramcore_ext_dfi_p2_wrdata_en = 1'd0;
+reg [3:0] litedramcore_ext_dfi_p2_wrdata_mask = 4'd0;
+reg litedramcore_ext_dfi_p2_rddata_en = 1'd0;
+reg [31:0] litedramcore_ext_dfi_p2_rddata = 32'd0;
+reg litedramcore_ext_dfi_p2_rddata_valid = 1'd0;
+reg [14:0] litedramcore_ext_dfi_p3_address = 15'd0;
+reg [2:0] litedramcore_ext_dfi_p3_bank = 3'd0;
+reg litedramcore_ext_dfi_p3_cas_n = 1'd1;
+reg litedramcore_ext_dfi_p3_cs_n = 1'd1;
+reg litedramcore_ext_dfi_p3_ras_n = 1'd1;
+reg litedramcore_ext_dfi_p3_we_n = 1'd1;
+reg litedramcore_ext_dfi_p3_cke = 1'd0;
+reg litedramcore_ext_dfi_p3_odt = 1'd0;
+reg litedramcore_ext_dfi_p3_reset_n = 1'd0;
+reg litedramcore_ext_dfi_p3_act_n = 1'd1;
+reg [31:0] litedramcore_ext_dfi_p3_wrdata = 32'd0;
+reg litedramcore_ext_dfi_p3_wrdata_en = 1'd0;
+reg [3:0] litedramcore_ext_dfi_p3_wrdata_mask = 4'd0;
+reg litedramcore_ext_dfi_p3_rddata_en = 1'd0;
+reg [31:0] litedramcore_ext_dfi_p3_rddata = 32'd0;
+reg litedramcore_ext_dfi_p3_rddata_valid = 1'd0;
+reg litedramcore_ext_dfi_sel = 1'd0;
+wire litedramcore_sel;
+wire litedramcore_cke;
+wire litedramcore_odt;
+wire litedramcore_reset_n;
+reg [3:0] litedramcore_storage = 4'd1;
+reg litedramcore_re = 1'd0;
+wire litedramcore_phaseinjector0_csrfield_cs;
+wire litedramcore_phaseinjector0_csrfield_we;
+wire litedramcore_phaseinjector0_csrfield_cas;
+wire litedramcore_phaseinjector0_csrfield_ras;
+wire litedramcore_phaseinjector0_csrfield_wren;
+wire litedramcore_phaseinjector0_csrfield_rden;
+reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0;
+reg litedramcore_phaseinjector0_command_re = 1'd0;
+reg litedramcore_phaseinjector0_command_issue_re = 1'd0;
+wire litedramcore_phaseinjector0_command_issue_r;
+reg litedramcore_phaseinjector0_command_issue_we = 1'd0;
+reg litedramcore_phaseinjector0_command_issue_w = 1'd0;
+reg [14:0] litedramcore_phaseinjector0_address_storage = 15'd0;
+reg litedramcore_phaseinjector0_address_re = 1'd0;
+reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0;
+reg litedramcore_phaseinjector0_baddress_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector0_wrdata_storage = 32'd0;
+reg litedramcore_phaseinjector0_wrdata_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector0_rddata_status = 32'd0;
+wire litedramcore_phaseinjector0_rddata_we;
+reg litedramcore_phaseinjector0_rddata_re = 1'd0;
+wire litedramcore_phaseinjector1_csrfield_cs;
+wire litedramcore_phaseinjector1_csrfield_we;
+wire litedramcore_phaseinjector1_csrfield_cas;
+wire litedramcore_phaseinjector1_csrfield_ras;
+wire litedramcore_phaseinjector1_csrfield_wren;
+wire litedramcore_phaseinjector1_csrfield_rden;
+reg [5:0] litedramcore_phaseinjector1_command_storage = 6'd0;
+reg litedramcore_phaseinjector1_command_re = 1'd0;
+reg litedramcore_phaseinjector1_command_issue_re = 1'd0;
+wire litedramcore_phaseinjector1_command_issue_r;
+reg litedramcore_phaseinjector1_command_issue_we = 1'd0;
+reg litedramcore_phaseinjector1_command_issue_w = 1'd0;
+reg [14:0] litedramcore_phaseinjector1_address_storage = 15'd0;
+reg litedramcore_phaseinjector1_address_re = 1'd0;
+reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0;
+reg litedramcore_phaseinjector1_baddress_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector1_wrdata_storage = 32'd0;
+reg litedramcore_phaseinjector1_wrdata_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector1_rddata_status = 32'd0;
+wire litedramcore_phaseinjector1_rddata_we;
+reg litedramcore_phaseinjector1_rddata_re = 1'd0;
+wire litedramcore_phaseinjector2_csrfield_cs;
+wire litedramcore_phaseinjector2_csrfield_we;
+wire litedramcore_phaseinjector2_csrfield_cas;
+wire litedramcore_phaseinjector2_csrfield_ras;
+wire litedramcore_phaseinjector2_csrfield_wren;
+wire litedramcore_phaseinjector2_csrfield_rden;
+reg [5:0] litedramcore_phaseinjector2_command_storage = 6'd0;
+reg litedramcore_phaseinjector2_command_re = 1'd0;
+reg litedramcore_phaseinjector2_command_issue_re = 1'd0;
+wire litedramcore_phaseinjector2_command_issue_r;
+reg litedramcore_phaseinjector2_command_issue_we = 1'd0;
+reg litedramcore_phaseinjector2_command_issue_w = 1'd0;
+reg [14:0] litedramcore_phaseinjector2_address_storage = 15'd0;
+reg litedramcore_phaseinjector2_address_re = 1'd0;
+reg [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0;
+reg litedramcore_phaseinjector2_baddress_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector2_wrdata_storage = 32'd0;
+reg litedramcore_phaseinjector2_wrdata_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector2_rddata_status = 32'd0;
+wire litedramcore_phaseinjector2_rddata_we;
+reg litedramcore_phaseinjector2_rddata_re = 1'd0;
+wire litedramcore_phaseinjector3_csrfield_cs;
+wire litedramcore_phaseinjector3_csrfield_we;
+wire litedramcore_phaseinjector3_csrfield_cas;
+wire litedramcore_phaseinjector3_csrfield_ras;
+wire litedramcore_phaseinjector3_csrfield_wren;
+wire litedramcore_phaseinjector3_csrfield_rden;
+reg [5:0] litedramcore_phaseinjector3_command_storage = 6'd0;
+reg litedramcore_phaseinjector3_command_re = 1'd0;
+reg litedramcore_phaseinjector3_command_issue_re = 1'd0;
+wire litedramcore_phaseinjector3_command_issue_r;
+reg litedramcore_phaseinjector3_command_issue_we = 1'd0;
+reg litedramcore_phaseinjector3_command_issue_w = 1'd0;
+reg [14:0] litedramcore_phaseinjector3_address_storage = 15'd0;
+reg litedramcore_phaseinjector3_address_re = 1'd0;
+reg [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0;
+reg litedramcore_phaseinjector3_baddress_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector3_wrdata_storage = 32'd0;
+reg litedramcore_phaseinjector3_wrdata_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector3_rddata_status = 32'd0;
+wire litedramcore_phaseinjector3_rddata_we;
+reg litedramcore_phaseinjector3_rddata_re = 1'd0;
+wire litedramcore_interface_bank0_valid;
+wire litedramcore_interface_bank0_ready;
+wire litedramcore_interface_bank0_we;
+wire [21:0] litedramcore_interface_bank0_addr;
+wire litedramcore_interface_bank0_lock;
+wire litedramcore_interface_bank0_wdata_ready;
+wire litedramcore_interface_bank0_rdata_valid;
+wire litedramcore_interface_bank1_valid;
+wire litedramcore_interface_bank1_ready;
+wire litedramcore_interface_bank1_we;
+wire [21:0] litedramcore_interface_bank1_addr;
+wire litedramcore_interface_bank1_lock;
+wire litedramcore_interface_bank1_wdata_ready;
+wire litedramcore_interface_bank1_rdata_valid;
+wire litedramcore_interface_bank2_valid;
+wire litedramcore_interface_bank2_ready;
+wire litedramcore_interface_bank2_we;
+wire [21:0] litedramcore_interface_bank2_addr;
+wire litedramcore_interface_bank2_lock;
+wire litedramcore_interface_bank2_wdata_ready;
+wire litedramcore_interface_bank2_rdata_valid;
+wire litedramcore_interface_bank3_valid;
+wire litedramcore_interface_bank3_ready;
+wire litedramcore_interface_bank3_we;
+wire [21:0] litedramcore_interface_bank3_addr;
+wire litedramcore_interface_bank3_lock;
+wire litedramcore_interface_bank3_wdata_ready;
+wire litedramcore_interface_bank3_rdata_valid;
+wire litedramcore_interface_bank4_valid;
+wire litedramcore_interface_bank4_ready;
+wire litedramcore_interface_bank4_we;
+wire [21:0] litedramcore_interface_bank4_addr;
+wire litedramcore_interface_bank4_lock;
+wire litedramcore_interface_bank4_wdata_ready;
+wire litedramcore_interface_bank4_rdata_valid;
+wire litedramcore_interface_bank5_valid;
+wire litedramcore_interface_bank5_ready;
+wire litedramcore_interface_bank5_we;
+wire [21:0] litedramcore_interface_bank5_addr;
+wire litedramcore_interface_bank5_lock;
+wire litedramcore_interface_bank5_wdata_ready;
+wire litedramcore_interface_bank5_rdata_valid;
+wire litedramcore_interface_bank6_valid;
+wire litedramcore_interface_bank6_ready;
+wire litedramcore_interface_bank6_we;
+wire [21:0] litedramcore_interface_bank6_addr;
+wire litedramcore_interface_bank6_lock;
+wire litedramcore_interface_bank6_wdata_ready;
+wire litedramcore_interface_bank6_rdata_valid;
+wire litedramcore_interface_bank7_valid;
+wire litedramcore_interface_bank7_ready;
+wire litedramcore_interface_bank7_we;
+wire [21:0] litedramcore_interface_bank7_addr;
+wire litedramcore_interface_bank7_lock;
+wire litedramcore_interface_bank7_wdata_ready;
+wire litedramcore_interface_bank7_rdata_valid;
+reg [127:0] litedramcore_interface_wdata = 128'd0;
+reg [15:0] litedramcore_interface_wdata_we = 16'd0;
+wire [127:0] litedramcore_interface_rdata;
+reg [14:0] litedramcore_dfi_p0_address = 15'd0;
+reg [2:0] litedramcore_dfi_p0_bank = 3'd0;
+reg litedramcore_dfi_p0_cas_n = 1'd1;
+reg litedramcore_dfi_p0_cs_n = 1'd1;
+reg litedramcore_dfi_p0_ras_n = 1'd1;
+reg litedramcore_dfi_p0_we_n = 1'd1;
+wire litedramcore_dfi_p0_cke;
+wire litedramcore_dfi_p0_odt;
+wire litedramcore_dfi_p0_reset_n;
+reg litedramcore_dfi_p0_act_n = 1'd1;
+wire [31:0] litedramcore_dfi_p0_wrdata;
+reg litedramcore_dfi_p0_wrdata_en = 1'd0;
+wire [3:0] litedramcore_dfi_p0_wrdata_mask;
+reg litedramcore_dfi_p0_rddata_en = 1'd0;
+wire [31:0] litedramcore_dfi_p0_rddata;
+wire litedramcore_dfi_p0_rddata_valid;
+reg [14:0] litedramcore_dfi_p1_address = 15'd0;
+reg [2:0] litedramcore_dfi_p1_bank = 3'd0;
+reg litedramcore_dfi_p1_cas_n = 1'd1;
+reg litedramcore_dfi_p1_cs_n = 1'd1;
+reg litedramcore_dfi_p1_ras_n = 1'd1;
+reg litedramcore_dfi_p1_we_n = 1'd1;
+wire litedramcore_dfi_p1_cke;
+wire litedramcore_dfi_p1_odt;
+wire litedramcore_dfi_p1_reset_n;
+reg litedramcore_dfi_p1_act_n = 1'd1;
+wire [31:0] litedramcore_dfi_p1_wrdata;
+reg litedramcore_dfi_p1_wrdata_en = 1'd0;
+wire [3:0] litedramcore_dfi_p1_wrdata_mask;
+reg litedramcore_dfi_p1_rddata_en = 1'd0;
+wire [31:0] litedramcore_dfi_p1_rddata;
+wire litedramcore_dfi_p1_rddata_valid;
+reg [14:0] litedramcore_dfi_p2_address = 15'd0;
+reg [2:0] litedramcore_dfi_p2_bank = 3'd0;
+reg litedramcore_dfi_p2_cas_n = 1'd1;
+reg litedramcore_dfi_p2_cs_n = 1'd1;
+reg litedramcore_dfi_p2_ras_n = 1'd1;
+reg litedramcore_dfi_p2_we_n = 1'd1;
+wire litedramcore_dfi_p2_cke;
+wire litedramcore_dfi_p2_odt;
+wire litedramcore_dfi_p2_reset_n;
+reg litedramcore_dfi_p2_act_n = 1'd1;
+wire [31:0] litedramcore_dfi_p2_wrdata;
+reg litedramcore_dfi_p2_wrdata_en = 1'd0;
+wire [3:0] litedramcore_dfi_p2_wrdata_mask;
+reg litedramcore_dfi_p2_rddata_en = 1'd0;
+wire [31:0] litedramcore_dfi_p2_rddata;
+wire litedramcore_dfi_p2_rddata_valid;
+reg [14:0] litedramcore_dfi_p3_address = 15'd0;
+reg [2:0] litedramcore_dfi_p3_bank = 3'd0;
+reg litedramcore_dfi_p3_cas_n = 1'd1;
+reg litedramcore_dfi_p3_cs_n = 1'd1;
+reg litedramcore_dfi_p3_ras_n = 1'd1;
+reg litedramcore_dfi_p3_we_n = 1'd1;
+wire litedramcore_dfi_p3_cke;
+wire litedramcore_dfi_p3_odt;
+wire litedramcore_dfi_p3_reset_n;
+reg litedramcore_dfi_p3_act_n = 1'd1;
+wire [31:0] litedramcore_dfi_p3_wrdata;
+reg litedramcore_dfi_p3_wrdata_en = 1'd0;
+wire [3:0] litedramcore_dfi_p3_wrdata_mask;
+reg litedramcore_dfi_p3_rddata_en = 1'd0;
+wire [31:0] litedramcore_dfi_p3_rddata;
+wire litedramcore_dfi_p3_rddata_valid;
+reg litedramcore_cmd_valid = 1'd0;
+reg litedramcore_cmd_ready = 1'd0;
+reg litedramcore_cmd_last = 1'd0;
+reg [14:0] litedramcore_cmd_payload_a = 15'd0;
+reg [2:0] litedramcore_cmd_payload_ba = 3'd0;
+reg litedramcore_cmd_payload_cas = 1'd0;
+reg litedramcore_cmd_payload_ras = 1'd0;
+reg litedramcore_cmd_payload_we = 1'd0;
+reg litedramcore_cmd_payload_is_read = 1'd0;
+reg litedramcore_cmd_payload_is_write = 1'd0;
+wire litedramcore_wants_refresh;
+wire litedramcore_wants_zqcs;
+wire litedramcore_timer_wait;
+wire litedramcore_timer_done0;
+wire [9:0] litedramcore_timer_count0;
+wire litedramcore_timer_done1;
+reg [9:0] litedramcore_timer_count1 = 10'd781;
+wire litedramcore_postponer_req_i;
+reg litedramcore_postponer_req_o = 1'd0;
+reg litedramcore_postponer_count = 1'd0;
+reg litedramcore_sequencer_start0 = 1'd0;
+wire litedramcore_sequencer_done0;
+wire litedramcore_sequencer_start1;
+reg litedramcore_sequencer_done1 = 1'd0;
+reg [5:0] litedramcore_sequencer_counter = 6'd0;
+reg litedramcore_sequencer_count = 1'd0;
+wire litedramcore_zqcs_timer_wait;
+wire litedramcore_zqcs_timer_done0;
+wire [26:0] litedramcore_zqcs_timer_count0;
+wire litedramcore_zqcs_timer_done1;
+reg [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999;
+reg litedramcore_zqcs_executer_start = 1'd0;
+reg litedramcore_zqcs_executer_done = 1'd0;
+reg [4:0] litedramcore_zqcs_executer_counter = 5'd0;
+wire litedramcore_bankmachine0_req_valid;
+wire litedramcore_bankmachine0_req_ready;
+wire litedramcore_bankmachine0_req_we;
+wire [21:0] litedramcore_bankmachine0_req_addr;
+wire litedramcore_bankmachine0_req_lock;
+reg litedramcore_bankmachine0_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine0_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine0_refresh_req;
+reg litedramcore_bankmachine0_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine0_cmd_valid = 1'd0;
+reg litedramcore_bankmachine0_cmd_ready = 1'd0;
+reg [14:0] litedramcore_bankmachine0_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine0_cmd_payload_ba;
+reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine0_auto_precharge = 1'd0;
+wire litedramcore_bankmachine0_sink_valid;
+wire litedramcore_bankmachine0_sink_ready;
+reg litedramcore_bankmachine0_sink_first = 1'd0;
+reg litedramcore_bankmachine0_sink_last = 1'd0;
+wire litedramcore_bankmachine0_sink_payload_we;
+wire [21:0] litedramcore_bankmachine0_sink_payload_addr;
+wire litedramcore_bankmachine0_source_valid;
+wire litedramcore_bankmachine0_source_ready;
+wire litedramcore_bankmachine0_source_first;
+wire litedramcore_bankmachine0_source_last;
+wire litedramcore_bankmachine0_source_payload_we;
+wire [21:0] litedramcore_bankmachine0_source_payload_addr;
+wire litedramcore_bankmachine0_syncfifo0_we;
+wire litedramcore_bankmachine0_syncfifo0_writable;
+wire litedramcore_bankmachine0_syncfifo0_re;
+wire litedramcore_bankmachine0_syncfifo0_readable;
+wire [24:0] litedramcore_bankmachine0_syncfifo0_din;
+wire [24:0] litedramcore_bankmachine0_syncfifo0_dout;
+reg [4:0] litedramcore_bankmachine0_level = 5'd0;
+reg litedramcore_bankmachine0_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine0_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine0_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine0_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine0_wrport_dat_r;
+wire litedramcore_bankmachine0_wrport_we;
+wire [24:0] litedramcore_bankmachine0_wrport_dat_w;
+wire litedramcore_bankmachine0_do_read;
+wire [3:0] litedramcore_bankmachine0_rdport_adr;
+wire [24:0] litedramcore_bankmachine0_rdport_dat_r;
+wire litedramcore_bankmachine0_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine0_fifo_in_payload_addr;
+wire litedramcore_bankmachine0_fifo_in_first;
+wire litedramcore_bankmachine0_fifo_in_last;
+wire litedramcore_bankmachine0_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine0_fifo_out_payload_addr;
+wire litedramcore_bankmachine0_fifo_out_first;
+wire litedramcore_bankmachine0_fifo_out_last;
+wire litedramcore_bankmachine0_sink_sink_valid;
+wire litedramcore_bankmachine0_sink_sink_ready;
+wire litedramcore_bankmachine0_sink_sink_first;
+wire litedramcore_bankmachine0_sink_sink_last;
+wire litedramcore_bankmachine0_sink_sink_payload_we;
+wire [21:0] litedramcore_bankmachine0_sink_sink_payload_addr;
+wire litedramcore_bankmachine0_source_source_valid;
+wire litedramcore_bankmachine0_source_source_ready;
+wire litedramcore_bankmachine0_source_source_first;
+wire litedramcore_bankmachine0_source_source_last;
+wire litedramcore_bankmachine0_source_source_payload_we;
+wire [21:0] litedramcore_bankmachine0_source_source_payload_addr;
+wire litedramcore_bankmachine0_pipe_valid_sink_valid;
+wire litedramcore_bankmachine0_pipe_valid_sink_ready;
+wire litedramcore_bankmachine0_pipe_valid_sink_first;
+wire litedramcore_bankmachine0_pipe_valid_sink_last;
+wire litedramcore_bankmachine0_pipe_valid_sink_payload_we;
+wire [21:0] litedramcore_bankmachine0_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine0_pipe_valid_source_ready;
+reg litedramcore_bankmachine0_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine0_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0;
+reg [21:0] litedramcore_bankmachine0_pipe_valid_source_payload_addr = 22'd0;
+reg [14:0] litedramcore_bankmachine0_row = 15'd0;
+reg litedramcore_bankmachine0_row_opened = 1'd0;
+wire litedramcore_bankmachine0_row_hit;
+reg litedramcore_bankmachine0_row_open = 1'd0;
+reg litedramcore_bankmachine0_row_close = 1'd0;
+reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine0_twtpcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine0_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine0_trccon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine0_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine0_trccon_count = 3'd0;
+wire litedramcore_bankmachine0_trascon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine0_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine0_trascon_count = 3'd0;
+wire litedramcore_bankmachine1_req_valid;
+wire litedramcore_bankmachine1_req_ready;
+wire litedramcore_bankmachine1_req_we;
+wire [21:0] litedramcore_bankmachine1_req_addr;
+wire litedramcore_bankmachine1_req_lock;
+reg litedramcore_bankmachine1_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine1_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine1_refresh_req;
+reg litedramcore_bankmachine1_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine1_cmd_valid = 1'd0;
+reg litedramcore_bankmachine1_cmd_ready = 1'd0;
+reg [14:0] litedramcore_bankmachine1_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine1_cmd_payload_ba;
+reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine1_auto_precharge = 1'd0;
+wire litedramcore_bankmachine1_sink_valid;
+wire litedramcore_bankmachine1_sink_ready;
+reg litedramcore_bankmachine1_sink_first = 1'd0;
+reg litedramcore_bankmachine1_sink_last = 1'd0;
+wire litedramcore_bankmachine1_sink_payload_we;
+wire [21:0] litedramcore_bankmachine1_sink_payload_addr;
+wire litedramcore_bankmachine1_source_valid;
+wire litedramcore_bankmachine1_source_ready;
+wire litedramcore_bankmachine1_source_first;
+wire litedramcore_bankmachine1_source_last;
+wire litedramcore_bankmachine1_source_payload_we;
+wire [21:0] litedramcore_bankmachine1_source_payload_addr;
+wire litedramcore_bankmachine1_syncfifo1_we;
+wire litedramcore_bankmachine1_syncfifo1_writable;
+wire litedramcore_bankmachine1_syncfifo1_re;
+wire litedramcore_bankmachine1_syncfifo1_readable;
+wire [24:0] litedramcore_bankmachine1_syncfifo1_din;
+wire [24:0] litedramcore_bankmachine1_syncfifo1_dout;
+reg [4:0] litedramcore_bankmachine1_level = 5'd0;
+reg litedramcore_bankmachine1_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine1_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine1_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine1_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine1_wrport_dat_r;
+wire litedramcore_bankmachine1_wrport_we;
+wire [24:0] litedramcore_bankmachine1_wrport_dat_w;
+wire litedramcore_bankmachine1_do_read;
+wire [3:0] litedramcore_bankmachine1_rdport_adr;
+wire [24:0] litedramcore_bankmachine1_rdport_dat_r;
+wire litedramcore_bankmachine1_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine1_fifo_in_payload_addr;
+wire litedramcore_bankmachine1_fifo_in_first;
+wire litedramcore_bankmachine1_fifo_in_last;
+wire litedramcore_bankmachine1_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine1_fifo_out_payload_addr;
+wire litedramcore_bankmachine1_fifo_out_first;
+wire litedramcore_bankmachine1_fifo_out_last;
+wire litedramcore_bankmachine1_sink_sink_valid;
+wire litedramcore_bankmachine1_sink_sink_ready;
+wire litedramcore_bankmachine1_sink_sink_first;
+wire litedramcore_bankmachine1_sink_sink_last;
+wire litedramcore_bankmachine1_sink_sink_payload_we;
+wire [21:0] litedramcore_bankmachine1_sink_sink_payload_addr;
+wire litedramcore_bankmachine1_source_source_valid;
+wire litedramcore_bankmachine1_source_source_ready;
+wire litedramcore_bankmachine1_source_source_first;
+wire litedramcore_bankmachine1_source_source_last;
+wire litedramcore_bankmachine1_source_source_payload_we;
+wire [21:0] litedramcore_bankmachine1_source_source_payload_addr;
+wire litedramcore_bankmachine1_pipe_valid_sink_valid;
+wire litedramcore_bankmachine1_pipe_valid_sink_ready;
+wire litedramcore_bankmachine1_pipe_valid_sink_first;
+wire litedramcore_bankmachine1_pipe_valid_sink_last;
+wire litedramcore_bankmachine1_pipe_valid_sink_payload_we;
+wire [21:0] litedramcore_bankmachine1_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine1_pipe_valid_source_ready;
+reg litedramcore_bankmachine1_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine1_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0;
+reg [21:0] litedramcore_bankmachine1_pipe_valid_source_payload_addr = 22'd0;
+reg [14:0] litedramcore_bankmachine1_row = 15'd0;
+reg litedramcore_bankmachine1_row_opened = 1'd0;
+wire litedramcore_bankmachine1_row_hit;
+reg litedramcore_bankmachine1_row_open = 1'd0;
+reg litedramcore_bankmachine1_row_close = 1'd0;
+reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine1_twtpcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine1_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine1_trccon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine1_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine1_trccon_count = 3'd0;
+wire litedramcore_bankmachine1_trascon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine1_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine1_trascon_count = 3'd0;
+wire litedramcore_bankmachine2_req_valid;
+wire litedramcore_bankmachine2_req_ready;
+wire litedramcore_bankmachine2_req_we;
+wire [21:0] litedramcore_bankmachine2_req_addr;
+wire litedramcore_bankmachine2_req_lock;
+reg litedramcore_bankmachine2_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine2_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine2_refresh_req;
+reg litedramcore_bankmachine2_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine2_cmd_valid = 1'd0;
+reg litedramcore_bankmachine2_cmd_ready = 1'd0;
+reg [14:0] litedramcore_bankmachine2_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine2_cmd_payload_ba;
+reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine2_auto_precharge = 1'd0;
+wire litedramcore_bankmachine2_sink_valid;
+wire litedramcore_bankmachine2_sink_ready;
+reg litedramcore_bankmachine2_sink_first = 1'd0;
+reg litedramcore_bankmachine2_sink_last = 1'd0;
+wire litedramcore_bankmachine2_sink_payload_we;
+wire [21:0] litedramcore_bankmachine2_sink_payload_addr;
+wire litedramcore_bankmachine2_source_valid;
+wire litedramcore_bankmachine2_source_ready;
+wire litedramcore_bankmachine2_source_first;
+wire litedramcore_bankmachine2_source_last;
+wire litedramcore_bankmachine2_source_payload_we;
+wire [21:0] litedramcore_bankmachine2_source_payload_addr;
+wire litedramcore_bankmachine2_syncfifo2_we;
+wire litedramcore_bankmachine2_syncfifo2_writable;
+wire litedramcore_bankmachine2_syncfifo2_re;
+wire litedramcore_bankmachine2_syncfifo2_readable;
+wire [24:0] litedramcore_bankmachine2_syncfifo2_din;
+wire [24:0] litedramcore_bankmachine2_syncfifo2_dout;
+reg [4:0] litedramcore_bankmachine2_level = 5'd0;
+reg litedramcore_bankmachine2_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine2_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine2_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine2_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine2_wrport_dat_r;
+wire litedramcore_bankmachine2_wrport_we;
+wire [24:0] litedramcore_bankmachine2_wrport_dat_w;
+wire litedramcore_bankmachine2_do_read;
+wire [3:0] litedramcore_bankmachine2_rdport_adr;
+wire [24:0] litedramcore_bankmachine2_rdport_dat_r;
+wire litedramcore_bankmachine2_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine2_fifo_in_payload_addr;
+wire litedramcore_bankmachine2_fifo_in_first;
+wire litedramcore_bankmachine2_fifo_in_last;
+wire litedramcore_bankmachine2_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine2_fifo_out_payload_addr;
+wire litedramcore_bankmachine2_fifo_out_first;
+wire litedramcore_bankmachine2_fifo_out_last;
+wire litedramcore_bankmachine2_sink_sink_valid;
+wire litedramcore_bankmachine2_sink_sink_ready;
+wire litedramcore_bankmachine2_sink_sink_first;
+wire litedramcore_bankmachine2_sink_sink_last;
+wire litedramcore_bankmachine2_sink_sink_payload_we;
+wire [21:0] litedramcore_bankmachine2_sink_sink_payload_addr;
+wire litedramcore_bankmachine2_source_source_valid;
+wire litedramcore_bankmachine2_source_source_ready;
+wire litedramcore_bankmachine2_source_source_first;
+wire litedramcore_bankmachine2_source_source_last;
+wire litedramcore_bankmachine2_source_source_payload_we;
+wire [21:0] litedramcore_bankmachine2_source_source_payload_addr;
+wire litedramcore_bankmachine2_pipe_valid_sink_valid;
+wire litedramcore_bankmachine2_pipe_valid_sink_ready;
+wire litedramcore_bankmachine2_pipe_valid_sink_first;
+wire litedramcore_bankmachine2_pipe_valid_sink_last;
+wire litedramcore_bankmachine2_pipe_valid_sink_payload_we;
+wire [21:0] litedramcore_bankmachine2_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine2_pipe_valid_source_ready;
+reg litedramcore_bankmachine2_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine2_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0;
+reg [21:0] litedramcore_bankmachine2_pipe_valid_source_payload_addr = 22'd0;
+reg [14:0] litedramcore_bankmachine2_row = 15'd0;
+reg litedramcore_bankmachine2_row_opened = 1'd0;
+wire litedramcore_bankmachine2_row_hit;
+reg litedramcore_bankmachine2_row_open = 1'd0;
+reg litedramcore_bankmachine2_row_close = 1'd0;
+reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine2_twtpcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine2_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine2_trccon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine2_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine2_trccon_count = 3'd0;
+wire litedramcore_bankmachine2_trascon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine2_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine2_trascon_count = 3'd0;
+wire litedramcore_bankmachine3_req_valid;
+wire litedramcore_bankmachine3_req_ready;
+wire litedramcore_bankmachine3_req_we;
+wire [21:0] litedramcore_bankmachine3_req_addr;
+wire litedramcore_bankmachine3_req_lock;
+reg litedramcore_bankmachine3_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine3_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine3_refresh_req;
+reg litedramcore_bankmachine3_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine3_cmd_valid = 1'd0;
+reg litedramcore_bankmachine3_cmd_ready = 1'd0;
+reg [14:0] litedramcore_bankmachine3_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine3_cmd_payload_ba;
+reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine3_auto_precharge = 1'd0;
+wire litedramcore_bankmachine3_sink_valid;
+wire litedramcore_bankmachine3_sink_ready;
+reg litedramcore_bankmachine3_sink_first = 1'd0;
+reg litedramcore_bankmachine3_sink_last = 1'd0;
+wire litedramcore_bankmachine3_sink_payload_we;
+wire [21:0] litedramcore_bankmachine3_sink_payload_addr;
+wire litedramcore_bankmachine3_source_valid;
+wire litedramcore_bankmachine3_source_ready;
+wire litedramcore_bankmachine3_source_first;
+wire litedramcore_bankmachine3_source_last;
+wire litedramcore_bankmachine3_source_payload_we;
+wire [21:0] litedramcore_bankmachine3_source_payload_addr;
+wire litedramcore_bankmachine3_syncfifo3_we;
+wire litedramcore_bankmachine3_syncfifo3_writable;
+wire litedramcore_bankmachine3_syncfifo3_re;
+wire litedramcore_bankmachine3_syncfifo3_readable;
+wire [24:0] litedramcore_bankmachine3_syncfifo3_din;
+wire [24:0] litedramcore_bankmachine3_syncfifo3_dout;
+reg [4:0] litedramcore_bankmachine3_level = 5'd0;
+reg litedramcore_bankmachine3_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine3_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine3_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine3_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine3_wrport_dat_r;
+wire litedramcore_bankmachine3_wrport_we;
+wire [24:0] litedramcore_bankmachine3_wrport_dat_w;
+wire litedramcore_bankmachine3_do_read;
+wire [3:0] litedramcore_bankmachine3_rdport_adr;
+wire [24:0] litedramcore_bankmachine3_rdport_dat_r;
+wire litedramcore_bankmachine3_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine3_fifo_in_payload_addr;
+wire litedramcore_bankmachine3_fifo_in_first;
+wire litedramcore_bankmachine3_fifo_in_last;
+wire litedramcore_bankmachine3_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine3_fifo_out_payload_addr;
+wire litedramcore_bankmachine3_fifo_out_first;
+wire litedramcore_bankmachine3_fifo_out_last;
+wire litedramcore_bankmachine3_sink_sink_valid;
+wire litedramcore_bankmachine3_sink_sink_ready;
+wire litedramcore_bankmachine3_sink_sink_first;
+wire litedramcore_bankmachine3_sink_sink_last;
+wire litedramcore_bankmachine3_sink_sink_payload_we;
+wire [21:0] litedramcore_bankmachine3_sink_sink_payload_addr;
+wire litedramcore_bankmachine3_source_source_valid;
+wire litedramcore_bankmachine3_source_source_ready;
+wire litedramcore_bankmachine3_source_source_first;
+wire litedramcore_bankmachine3_source_source_last;
+wire litedramcore_bankmachine3_source_source_payload_we;
+wire [21:0] litedramcore_bankmachine3_source_source_payload_addr;
+wire litedramcore_bankmachine3_pipe_valid_sink_valid;
+wire litedramcore_bankmachine3_pipe_valid_sink_ready;
+wire litedramcore_bankmachine3_pipe_valid_sink_first;
+wire litedramcore_bankmachine3_pipe_valid_sink_last;
+wire litedramcore_bankmachine3_pipe_valid_sink_payload_we;
+wire [21:0] litedramcore_bankmachine3_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine3_pipe_valid_source_ready;
+reg litedramcore_bankmachine3_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine3_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0;
+reg [21:0] litedramcore_bankmachine3_pipe_valid_source_payload_addr = 22'd0;
+reg [14:0] litedramcore_bankmachine3_row = 15'd0;
+reg litedramcore_bankmachine3_row_opened = 1'd0;
+wire litedramcore_bankmachine3_row_hit;
+reg litedramcore_bankmachine3_row_open = 1'd0;
+reg litedramcore_bankmachine3_row_close = 1'd0;
+reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine3_twtpcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine3_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine3_trccon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine3_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine3_trccon_count = 3'd0;
+wire litedramcore_bankmachine3_trascon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine3_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine3_trascon_count = 3'd0;
+wire litedramcore_bankmachine4_req_valid;
+wire litedramcore_bankmachine4_req_ready;
+wire litedramcore_bankmachine4_req_we;
+wire [21:0] litedramcore_bankmachine4_req_addr;
+wire litedramcore_bankmachine4_req_lock;
+reg litedramcore_bankmachine4_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine4_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine4_refresh_req;
+reg litedramcore_bankmachine4_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine4_cmd_valid = 1'd0;
+reg litedramcore_bankmachine4_cmd_ready = 1'd0;
+reg [14:0] litedramcore_bankmachine4_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine4_cmd_payload_ba;
+reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine4_auto_precharge = 1'd0;
+wire litedramcore_bankmachine4_sink_valid;
+wire litedramcore_bankmachine4_sink_ready;
+reg litedramcore_bankmachine4_sink_first = 1'd0;
+reg litedramcore_bankmachine4_sink_last = 1'd0;
+wire litedramcore_bankmachine4_sink_payload_we;
+wire [21:0] litedramcore_bankmachine4_sink_payload_addr;
+wire litedramcore_bankmachine4_source_valid;
+wire litedramcore_bankmachine4_source_ready;
+wire litedramcore_bankmachine4_source_first;
+wire litedramcore_bankmachine4_source_last;
+wire litedramcore_bankmachine4_source_payload_we;
+wire [21:0] litedramcore_bankmachine4_source_payload_addr;
+wire litedramcore_bankmachine4_syncfifo4_we;
+wire litedramcore_bankmachine4_syncfifo4_writable;
+wire litedramcore_bankmachine4_syncfifo4_re;
+wire litedramcore_bankmachine4_syncfifo4_readable;
+wire [24:0] litedramcore_bankmachine4_syncfifo4_din;
+wire [24:0] litedramcore_bankmachine4_syncfifo4_dout;
+reg [4:0] litedramcore_bankmachine4_level = 5'd0;
+reg litedramcore_bankmachine4_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine4_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine4_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine4_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine4_wrport_dat_r;
+wire litedramcore_bankmachine4_wrport_we;
+wire [24:0] litedramcore_bankmachine4_wrport_dat_w;
+wire litedramcore_bankmachine4_do_read;
+wire [3:0] litedramcore_bankmachine4_rdport_adr;
+wire [24:0] litedramcore_bankmachine4_rdport_dat_r;
+wire litedramcore_bankmachine4_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine4_fifo_in_payload_addr;
+wire litedramcore_bankmachine4_fifo_in_first;
+wire litedramcore_bankmachine4_fifo_in_last;
+wire litedramcore_bankmachine4_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine4_fifo_out_payload_addr;
+wire litedramcore_bankmachine4_fifo_out_first;
+wire litedramcore_bankmachine4_fifo_out_last;
+wire litedramcore_bankmachine4_sink_sink_valid;
+wire litedramcore_bankmachine4_sink_sink_ready;
+wire litedramcore_bankmachine4_sink_sink_first;
+wire litedramcore_bankmachine4_sink_sink_last;
+wire litedramcore_bankmachine4_sink_sink_payload_we;
+wire [21:0] litedramcore_bankmachine4_sink_sink_payload_addr;
+wire litedramcore_bankmachine4_source_source_valid;
+wire litedramcore_bankmachine4_source_source_ready;
+wire litedramcore_bankmachine4_source_source_first;
+wire litedramcore_bankmachine4_source_source_last;
+wire litedramcore_bankmachine4_source_source_payload_we;
+wire [21:0] litedramcore_bankmachine4_source_source_payload_addr;
+wire litedramcore_bankmachine4_pipe_valid_sink_valid;
+wire litedramcore_bankmachine4_pipe_valid_sink_ready;
+wire litedramcore_bankmachine4_pipe_valid_sink_first;
+wire litedramcore_bankmachine4_pipe_valid_sink_last;
+wire litedramcore_bankmachine4_pipe_valid_sink_payload_we;
+wire [21:0] litedramcore_bankmachine4_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine4_pipe_valid_source_ready;
+reg litedramcore_bankmachine4_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine4_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0;
+reg [21:0] litedramcore_bankmachine4_pipe_valid_source_payload_addr = 22'd0;
+reg [14:0] litedramcore_bankmachine4_row = 15'd0;
+reg litedramcore_bankmachine4_row_opened = 1'd0;
+wire litedramcore_bankmachine4_row_hit;
+reg litedramcore_bankmachine4_row_open = 1'd0;
+reg litedramcore_bankmachine4_row_close = 1'd0;
+reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine4_twtpcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine4_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine4_trccon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine4_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine4_trccon_count = 3'd0;
+wire litedramcore_bankmachine4_trascon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine4_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine4_trascon_count = 3'd0;
+wire litedramcore_bankmachine5_req_valid;
+wire litedramcore_bankmachine5_req_ready;
+wire litedramcore_bankmachine5_req_we;
+wire [21:0] litedramcore_bankmachine5_req_addr;
+wire litedramcore_bankmachine5_req_lock;
+reg litedramcore_bankmachine5_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine5_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine5_refresh_req;
+reg litedramcore_bankmachine5_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine5_cmd_valid = 1'd0;
+reg litedramcore_bankmachine5_cmd_ready = 1'd0;
+reg [14:0] litedramcore_bankmachine5_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine5_cmd_payload_ba;
+reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine5_auto_precharge = 1'd0;
+wire litedramcore_bankmachine5_sink_valid;
+wire litedramcore_bankmachine5_sink_ready;
+reg litedramcore_bankmachine5_sink_first = 1'd0;
+reg litedramcore_bankmachine5_sink_last = 1'd0;
+wire litedramcore_bankmachine5_sink_payload_we;
+wire [21:0] litedramcore_bankmachine5_sink_payload_addr;
+wire litedramcore_bankmachine5_source_valid;
+wire litedramcore_bankmachine5_source_ready;
+wire litedramcore_bankmachine5_source_first;
+wire litedramcore_bankmachine5_source_last;
+wire litedramcore_bankmachine5_source_payload_we;
+wire [21:0] litedramcore_bankmachine5_source_payload_addr;
+wire litedramcore_bankmachine5_syncfifo5_we;
+wire litedramcore_bankmachine5_syncfifo5_writable;
+wire litedramcore_bankmachine5_syncfifo5_re;
+wire litedramcore_bankmachine5_syncfifo5_readable;
+wire [24:0] litedramcore_bankmachine5_syncfifo5_din;
+wire [24:0] litedramcore_bankmachine5_syncfifo5_dout;
+reg [4:0] litedramcore_bankmachine5_level = 5'd0;
+reg litedramcore_bankmachine5_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine5_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine5_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine5_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine5_wrport_dat_r;
+wire litedramcore_bankmachine5_wrport_we;
+wire [24:0] litedramcore_bankmachine5_wrport_dat_w;
+wire litedramcore_bankmachine5_do_read;
+wire [3:0] litedramcore_bankmachine5_rdport_adr;
+wire [24:0] litedramcore_bankmachine5_rdport_dat_r;
+wire litedramcore_bankmachine5_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine5_fifo_in_payload_addr;
+wire litedramcore_bankmachine5_fifo_in_first;
+wire litedramcore_bankmachine5_fifo_in_last;
+wire litedramcore_bankmachine5_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine5_fifo_out_payload_addr;
+wire litedramcore_bankmachine5_fifo_out_first;
+wire litedramcore_bankmachine5_fifo_out_last;
+wire litedramcore_bankmachine5_sink_sink_valid;
+wire litedramcore_bankmachine5_sink_sink_ready;
+wire litedramcore_bankmachine5_sink_sink_first;
+wire litedramcore_bankmachine5_sink_sink_last;
+wire litedramcore_bankmachine5_sink_sink_payload_we;
+wire [21:0] litedramcore_bankmachine5_sink_sink_payload_addr;
+wire litedramcore_bankmachine5_source_source_valid;
+wire litedramcore_bankmachine5_source_source_ready;
+wire litedramcore_bankmachine5_source_source_first;
+wire litedramcore_bankmachine5_source_source_last;
+wire litedramcore_bankmachine5_source_source_payload_we;
+wire [21:0] litedramcore_bankmachine5_source_source_payload_addr;
+wire litedramcore_bankmachine5_pipe_valid_sink_valid;
+wire litedramcore_bankmachine5_pipe_valid_sink_ready;
+wire litedramcore_bankmachine5_pipe_valid_sink_first;
+wire litedramcore_bankmachine5_pipe_valid_sink_last;
+wire litedramcore_bankmachine5_pipe_valid_sink_payload_we;
+wire [21:0] litedramcore_bankmachine5_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine5_pipe_valid_source_ready;
+reg litedramcore_bankmachine5_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine5_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0;
+reg [21:0] litedramcore_bankmachine5_pipe_valid_source_payload_addr = 22'd0;
+reg [14:0] litedramcore_bankmachine5_row = 15'd0;
+reg litedramcore_bankmachine5_row_opened = 1'd0;
+wire litedramcore_bankmachine5_row_hit;
+reg litedramcore_bankmachine5_row_open = 1'd0;
+reg litedramcore_bankmachine5_row_close = 1'd0;
+reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine5_twtpcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine5_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine5_trccon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine5_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine5_trccon_count = 3'd0;
+wire litedramcore_bankmachine5_trascon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine5_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine5_trascon_count = 3'd0;
+wire litedramcore_bankmachine6_req_valid;
+wire litedramcore_bankmachine6_req_ready;
+wire litedramcore_bankmachine6_req_we;
+wire [21:0] litedramcore_bankmachine6_req_addr;
+wire litedramcore_bankmachine6_req_lock;
+reg litedramcore_bankmachine6_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine6_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine6_refresh_req;
+reg litedramcore_bankmachine6_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine6_cmd_valid = 1'd0;
+reg litedramcore_bankmachine6_cmd_ready = 1'd0;
+reg [14:0] litedramcore_bankmachine6_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine6_cmd_payload_ba;
+reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine6_auto_precharge = 1'd0;
+wire litedramcore_bankmachine6_sink_valid;
+wire litedramcore_bankmachine6_sink_ready;
+reg litedramcore_bankmachine6_sink_first = 1'd0;
+reg litedramcore_bankmachine6_sink_last = 1'd0;
+wire litedramcore_bankmachine6_sink_payload_we;
+wire [21:0] litedramcore_bankmachine6_sink_payload_addr;
+wire litedramcore_bankmachine6_source_valid;
+wire litedramcore_bankmachine6_source_ready;
+wire litedramcore_bankmachine6_source_first;
+wire litedramcore_bankmachine6_source_last;
+wire litedramcore_bankmachine6_source_payload_we;
+wire [21:0] litedramcore_bankmachine6_source_payload_addr;
+wire litedramcore_bankmachine6_syncfifo6_we;
+wire litedramcore_bankmachine6_syncfifo6_writable;
+wire litedramcore_bankmachine6_syncfifo6_re;
+wire litedramcore_bankmachine6_syncfifo6_readable;
+wire [24:0] litedramcore_bankmachine6_syncfifo6_din;
+wire [24:0] litedramcore_bankmachine6_syncfifo6_dout;
+reg [4:0] litedramcore_bankmachine6_level = 5'd0;
+reg litedramcore_bankmachine6_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine6_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine6_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine6_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine6_wrport_dat_r;
+wire litedramcore_bankmachine6_wrport_we;
+wire [24:0] litedramcore_bankmachine6_wrport_dat_w;
+wire litedramcore_bankmachine6_do_read;
+wire [3:0] litedramcore_bankmachine6_rdport_adr;
+wire [24:0] litedramcore_bankmachine6_rdport_dat_r;
+wire litedramcore_bankmachine6_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine6_fifo_in_payload_addr;
+wire litedramcore_bankmachine6_fifo_in_first;
+wire litedramcore_bankmachine6_fifo_in_last;
+wire litedramcore_bankmachine6_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine6_fifo_out_payload_addr;
+wire litedramcore_bankmachine6_fifo_out_first;
+wire litedramcore_bankmachine6_fifo_out_last;
+wire litedramcore_bankmachine6_sink_sink_valid;
+wire litedramcore_bankmachine6_sink_sink_ready;
+wire litedramcore_bankmachine6_sink_sink_first;
+wire litedramcore_bankmachine6_sink_sink_last;
+wire litedramcore_bankmachine6_sink_sink_payload_we;
+wire [21:0] litedramcore_bankmachine6_sink_sink_payload_addr;
+wire litedramcore_bankmachine6_source_source_valid;
+wire litedramcore_bankmachine6_source_source_ready;
+wire litedramcore_bankmachine6_source_source_first;
+wire litedramcore_bankmachine6_source_source_last;
+wire litedramcore_bankmachine6_source_source_payload_we;
+wire [21:0] litedramcore_bankmachine6_source_source_payload_addr;
+wire litedramcore_bankmachine6_pipe_valid_sink_valid;
+wire litedramcore_bankmachine6_pipe_valid_sink_ready;
+wire litedramcore_bankmachine6_pipe_valid_sink_first;
+wire litedramcore_bankmachine6_pipe_valid_sink_last;
+wire litedramcore_bankmachine6_pipe_valid_sink_payload_we;
+wire [21:0] litedramcore_bankmachine6_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine6_pipe_valid_source_ready;
+reg litedramcore_bankmachine6_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine6_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0;
+reg [21:0] litedramcore_bankmachine6_pipe_valid_source_payload_addr = 22'd0;
+reg [14:0] litedramcore_bankmachine6_row = 15'd0;
+reg litedramcore_bankmachine6_row_opened = 1'd0;
+wire litedramcore_bankmachine6_row_hit;
+reg litedramcore_bankmachine6_row_open = 1'd0;
+reg litedramcore_bankmachine6_row_close = 1'd0;
+reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine6_twtpcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine6_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine6_trccon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine6_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine6_trccon_count = 3'd0;
+wire litedramcore_bankmachine6_trascon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine6_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine6_trascon_count = 3'd0;
+wire litedramcore_bankmachine7_req_valid;
+wire litedramcore_bankmachine7_req_ready;
+wire litedramcore_bankmachine7_req_we;
+wire [21:0] litedramcore_bankmachine7_req_addr;
+wire litedramcore_bankmachine7_req_lock;
+reg litedramcore_bankmachine7_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine7_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine7_refresh_req;
+reg litedramcore_bankmachine7_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine7_cmd_valid = 1'd0;
+reg litedramcore_bankmachine7_cmd_ready = 1'd0;
+reg [14:0] litedramcore_bankmachine7_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine7_cmd_payload_ba;
+reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine7_auto_precharge = 1'd0;
+wire litedramcore_bankmachine7_sink_valid;
+wire litedramcore_bankmachine7_sink_ready;
+reg litedramcore_bankmachine7_sink_first = 1'd0;
+reg litedramcore_bankmachine7_sink_last = 1'd0;
+wire litedramcore_bankmachine7_sink_payload_we;
+wire [21:0] litedramcore_bankmachine7_sink_payload_addr;
+wire litedramcore_bankmachine7_source_valid;
+wire litedramcore_bankmachine7_source_ready;
+wire litedramcore_bankmachine7_source_first;
+wire litedramcore_bankmachine7_source_last;
+wire litedramcore_bankmachine7_source_payload_we;
+wire [21:0] litedramcore_bankmachine7_source_payload_addr;
+wire litedramcore_bankmachine7_syncfifo7_we;
+wire litedramcore_bankmachine7_syncfifo7_writable;
+wire litedramcore_bankmachine7_syncfifo7_re;
+wire litedramcore_bankmachine7_syncfifo7_readable;
+wire [24:0] litedramcore_bankmachine7_syncfifo7_din;
+wire [24:0] litedramcore_bankmachine7_syncfifo7_dout;
+reg [4:0] litedramcore_bankmachine7_level = 5'd0;
+reg litedramcore_bankmachine7_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine7_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine7_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine7_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine7_wrport_dat_r;
+wire litedramcore_bankmachine7_wrport_we;
+wire [24:0] litedramcore_bankmachine7_wrport_dat_w;
+wire litedramcore_bankmachine7_do_read;
+wire [3:0] litedramcore_bankmachine7_rdport_adr;
+wire [24:0] litedramcore_bankmachine7_rdport_dat_r;
+wire litedramcore_bankmachine7_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine7_fifo_in_payload_addr;
+wire litedramcore_bankmachine7_fifo_in_first;
+wire litedramcore_bankmachine7_fifo_in_last;
+wire litedramcore_bankmachine7_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine7_fifo_out_payload_addr;
+wire litedramcore_bankmachine7_fifo_out_first;
+wire litedramcore_bankmachine7_fifo_out_last;
+wire litedramcore_bankmachine7_sink_sink_valid;
+wire litedramcore_bankmachine7_sink_sink_ready;
+wire litedramcore_bankmachine7_sink_sink_first;
+wire litedramcore_bankmachine7_sink_sink_last;
+wire litedramcore_bankmachine7_sink_sink_payload_we;
+wire [21:0] litedramcore_bankmachine7_sink_sink_payload_addr;
+wire litedramcore_bankmachine7_source_source_valid;
+wire litedramcore_bankmachine7_source_source_ready;
+wire litedramcore_bankmachine7_source_source_first;
+wire litedramcore_bankmachine7_source_source_last;
+wire litedramcore_bankmachine7_source_source_payload_we;
+wire [21:0] litedramcore_bankmachine7_source_source_payload_addr;
+wire litedramcore_bankmachine7_pipe_valid_sink_valid;
+wire litedramcore_bankmachine7_pipe_valid_sink_ready;
+wire litedramcore_bankmachine7_pipe_valid_sink_first;
+wire litedramcore_bankmachine7_pipe_valid_sink_last;
+wire litedramcore_bankmachine7_pipe_valid_sink_payload_we;
+wire [21:0] litedramcore_bankmachine7_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine7_pipe_valid_source_ready;
+reg litedramcore_bankmachine7_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine7_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0;
+reg [21:0] litedramcore_bankmachine7_pipe_valid_source_payload_addr = 22'd0;
+reg [14:0] litedramcore_bankmachine7_row = 15'd0;
+reg litedramcore_bankmachine7_row_opened = 1'd0;
+wire litedramcore_bankmachine7_row_hit;
+reg litedramcore_bankmachine7_row_open = 1'd0;
+reg litedramcore_bankmachine7_row_close = 1'd0;
+reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine7_twtpcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine7_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine7_trccon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine7_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine7_trccon_count = 3'd0;
+wire litedramcore_bankmachine7_trascon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine7_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine7_trascon_count = 3'd0;
+wire litedramcore_ras_allowed;
+wire litedramcore_cas_allowed;
+wire [1:0] litedramcore_rdcmdphase;
+wire [1:0] litedramcore_wrcmdphase;
+reg litedramcore_choose_cmd_want_reads = 1'd0;
+reg litedramcore_choose_cmd_want_writes = 1'd0;
+reg litedramcore_choose_cmd_want_cmds = 1'd0;
+reg litedramcore_choose_cmd_want_activates = 1'd0;
+wire litedramcore_choose_cmd_cmd_valid;
+reg litedramcore_choose_cmd_cmd_ready = 1'd0;
+wire [14:0] litedramcore_choose_cmd_cmd_payload_a;
+wire [2:0] litedramcore_choose_cmd_cmd_payload_ba;
+reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
+reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
+reg litedramcore_choose_cmd_cmd_payload_we = 1'd0;
+wire litedramcore_choose_cmd_cmd_payload_is_cmd;
+wire litedramcore_choose_cmd_cmd_payload_is_read;
+wire litedramcore_choose_cmd_cmd_payload_is_write;
+reg [7:0] litedramcore_choose_cmd_valids = 8'd0;
+wire [7:0] litedramcore_choose_cmd_request;
+reg [2:0] litedramcore_choose_cmd_grant = 3'd0;
+wire litedramcore_choose_cmd_ce;
+reg litedramcore_choose_req_want_reads = 1'd0;
+reg litedramcore_choose_req_want_writes = 1'd0;
+reg litedramcore_choose_req_want_cmds = 1'd0;
+reg litedramcore_choose_req_want_activates = 1'd0;
+wire litedramcore_choose_req_cmd_valid;
+reg litedramcore_choose_req_cmd_ready = 1'd0;
+wire [14:0] litedramcore_choose_req_cmd_payload_a;
+wire [2:0] litedramcore_choose_req_cmd_payload_ba;
+reg litedramcore_choose_req_cmd_payload_cas = 1'd0;
+reg litedramcore_choose_req_cmd_payload_ras = 1'd0;
+reg litedramcore_choose_req_cmd_payload_we = 1'd0;
+wire litedramcore_choose_req_cmd_payload_is_cmd;
+wire litedramcore_choose_req_cmd_payload_is_read;
+wire litedramcore_choose_req_cmd_payload_is_write;
+reg [7:0] litedramcore_choose_req_valids = 8'd0;
+wire [7:0] litedramcore_choose_req_request;
+reg [2:0] litedramcore_choose_req_grant = 3'd0;
+wire litedramcore_choose_req_ce;
+reg [14:0] litedramcore_nop_a = 15'd0;
+reg [2:0] litedramcore_nop_ba = 3'd0;
+reg [1:0] litedramcore_steerer_sel0 = 2'd0;
+reg [1:0] litedramcore_steerer_sel1 = 2'd0;
+reg [1:0] litedramcore_steerer_sel2 = 2'd0;
+reg [1:0] litedramcore_steerer_sel3 = 2'd0;
+reg litedramcore_steerer0 = 1'd1;
+reg litedramcore_steerer1 = 1'd1;
+reg litedramcore_steerer2 = 1'd1;
+reg litedramcore_steerer3 = 1'd1;
+reg litedramcore_steerer4 = 1'd1;
+reg litedramcore_steerer5 = 1'd1;
+reg litedramcore_steerer6 = 1'd1;
+reg litedramcore_steerer7 = 1'd1;
+wire litedramcore_trrdcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_trrdcon_ready = 1'd0;
+reg litedramcore_trrdcon_count = 1'd0;
+wire litedramcore_tfawcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_tfawcon_ready = 1'd1;
+wire [2:0] litedramcore_tfawcon_count;
+reg [4:0] litedramcore_tfawcon_window = 5'd0;
+wire litedramcore_tccdcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_tccdcon_ready = 1'd0;
+reg litedramcore_tccdcon_count = 1'd0;
+wire litedramcore_twtrcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_twtrcon_ready = 1'd0;
+reg [2:0] litedramcore_twtrcon_count = 3'd0;
+wire litedramcore_read_available;
+wire litedramcore_write_available;
+reg litedramcore_en0 = 1'd0;
+wire litedramcore_max_time0;
+reg [4:0] litedramcore_time0 = 5'd0;
+reg litedramcore_en1 = 1'd0;
+wire litedramcore_max_time1;
+reg [3:0] litedramcore_time1 = 4'd0;
+wire litedramcore_go_to_refresh;
+reg init_done_storage = 1'd0;
+reg init_done_re = 1'd0;
+reg init_error_storage = 1'd0;
+reg init_error_re = 1'd0;
+wire [29:0] wb_bus_adr;
+wire [31:0] wb_bus_dat_w;
+wire [31:0] wb_bus_dat_r;
+wire [3:0] wb_bus_sel;
+wire wb_bus_cyc;
+wire wb_bus_stb;
+wire wb_bus_ack;
+wire wb_bus_we;
+wire [2:0] wb_bus_cti;
+wire [1:0] wb_bus_bte;
+wire wb_bus_err;
+wire user_enable;
+wire user_port_cmd_valid;
+wire user_port_cmd_ready;
+wire user_port_cmd_payload_we;
+wire [24:0] user_port_cmd_payload_addr;
+wire user_port_wdata_valid;
+wire user_port_wdata_ready;
+wire [127:0] user_port_wdata_payload_data;
+wire [15:0] user_port_wdata_payload_we;
+wire user_port_rdata_valid;
+wire user_port_rdata_ready;
+wire [127:0] user_port_rdata_payload_data;
+reg [13:0] litedramcore_adr = 14'd0;
+reg litedramcore_we = 1'd0;
+reg [31:0] litedramcore_dat_w = 32'd0;
+wire [31:0] litedramcore_dat_r;
+wire [29:0] litedramcore_wishbone_adr;
+wire [31:0] litedramcore_wishbone_dat_w;
+reg [31:0] litedramcore_wishbone_dat_r = 32'd0;
+wire [3:0] litedramcore_wishbone_sel;
+wire litedramcore_wishbone_cyc;
+wire litedramcore_wishbone_stb;
+reg litedramcore_wishbone_ack = 1'd0;
+wire litedramcore_wishbone_we;
+wire [2:0] litedramcore_wishbone_cti;
+wire [1:0] litedramcore_wishbone_bte;
+reg litedramcore_wishbone_err = 1'd0;
+wire [13:0] interface0_bank_bus_adr;
+wire interface0_bank_bus_we;
+wire [31:0] interface0_bank_bus_dat_w;
+reg [31:0] interface0_bank_bus_dat_r = 32'd0;
+reg csrbank0_init_done0_re = 1'd0;
+wire csrbank0_init_done0_r;
+reg csrbank0_init_done0_we = 1'd0;
+wire csrbank0_init_done0_w;
+reg csrbank0_init_error0_re = 1'd0;
+wire csrbank0_init_error0_r;
+reg csrbank0_init_error0_we = 1'd0;
+wire csrbank0_init_error0_w;
+wire csrbank0_sel;
+wire [13:0] interface1_bank_bus_adr;
+wire interface1_bank_bus_we;
+wire [31:0] interface1_bank_bus_dat_w;
+reg [31:0] interface1_bank_bus_dat_r = 32'd0;
+reg csrbank1_rst0_re = 1'd0;
+wire csrbank1_rst0_r;
+reg csrbank1_rst0_we = 1'd0;
+wire csrbank1_rst0_w;
+reg csrbank1_dly_sel0_re = 1'd0;
+wire [1:0] csrbank1_dly_sel0_r;
+reg csrbank1_dly_sel0_we = 1'd0;
+wire [1:0] csrbank1_dly_sel0_w;
+reg csrbank1_half_sys8x_taps0_re = 1'd0;
+wire [4:0] csrbank1_half_sys8x_taps0_r;
+reg csrbank1_half_sys8x_taps0_we = 1'd0;
+wire [4:0] csrbank1_half_sys8x_taps0_w;
+reg csrbank1_wlevel_en0_re = 1'd0;
+wire csrbank1_wlevel_en0_r;
+reg csrbank1_wlevel_en0_we = 1'd0;
+wire csrbank1_wlevel_en0_w;
+reg csrbank1_rdphase0_re = 1'd0;
+wire [1:0] csrbank1_rdphase0_r;
+reg csrbank1_rdphase0_we = 1'd0;
+wire [1:0] csrbank1_rdphase0_w;
+reg csrbank1_wrphase0_re = 1'd0;
+wire [1:0] csrbank1_wrphase0_r;
+reg csrbank1_wrphase0_we = 1'd0;
+wire [1:0] csrbank1_wrphase0_w;
+wire csrbank1_sel;
+wire [13:0] interface2_bank_bus_adr;
+wire interface2_bank_bus_we;
+wire [31:0] interface2_bank_bus_dat_w;
+reg [31:0] interface2_bank_bus_dat_r = 32'd0;
+reg csrbank2_dfii_control0_re = 1'd0;
+wire [3:0] csrbank2_dfii_control0_r;
+reg csrbank2_dfii_control0_we = 1'd0;
+wire [3:0] csrbank2_dfii_control0_w;
+reg csrbank2_dfii_pi0_command0_re = 1'd0;
+wire [5:0] csrbank2_dfii_pi0_command0_r;
+reg csrbank2_dfii_pi0_command0_we = 1'd0;
+wire [5:0] csrbank2_dfii_pi0_command0_w;
+reg csrbank2_dfii_pi0_address0_re = 1'd0;
+wire [14:0] csrbank2_dfii_pi0_address0_r;
+reg csrbank2_dfii_pi0_address0_we = 1'd0;
+wire [14:0] csrbank2_dfii_pi0_address0_w;
+reg csrbank2_dfii_pi0_baddress0_re = 1'd0;
+wire [2:0] csrbank2_dfii_pi0_baddress0_r;
+reg csrbank2_dfii_pi0_baddress0_we = 1'd0;
+wire [2:0] csrbank2_dfii_pi0_baddress0_w;
+reg csrbank2_dfii_pi0_wrdata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_wrdata0_r;
+reg csrbank2_dfii_pi0_wrdata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_wrdata0_w;
+reg csrbank2_dfii_pi0_rddata_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_rddata_r;
+reg csrbank2_dfii_pi0_rddata_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_rddata_w;
+reg csrbank2_dfii_pi1_command0_re = 1'd0;
+wire [5:0] csrbank2_dfii_pi1_command0_r;
+reg csrbank2_dfii_pi1_command0_we = 1'd0;
+wire [5:0] csrbank2_dfii_pi1_command0_w;
+reg csrbank2_dfii_pi1_address0_re = 1'd0;
+wire [14:0] csrbank2_dfii_pi1_address0_r;
+reg csrbank2_dfii_pi1_address0_we = 1'd0;
+wire [14:0] csrbank2_dfii_pi1_address0_w;
+reg csrbank2_dfii_pi1_baddress0_re = 1'd0;
+wire [2:0] csrbank2_dfii_pi1_baddress0_r;
+reg csrbank2_dfii_pi1_baddress0_we = 1'd0;
+wire [2:0] csrbank2_dfii_pi1_baddress0_w;
+reg csrbank2_dfii_pi1_wrdata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_wrdata0_r;
+reg csrbank2_dfii_pi1_wrdata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_wrdata0_w;
+reg csrbank2_dfii_pi1_rddata_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_rddata_r;
+reg csrbank2_dfii_pi1_rddata_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_rddata_w;
+reg csrbank2_dfii_pi2_command0_re = 1'd0;
+wire [5:0] csrbank2_dfii_pi2_command0_r;
+reg csrbank2_dfii_pi2_command0_we = 1'd0;
+wire [5:0] csrbank2_dfii_pi2_command0_w;
+reg csrbank2_dfii_pi2_address0_re = 1'd0;
+wire [14:0] csrbank2_dfii_pi2_address0_r;
+reg csrbank2_dfii_pi2_address0_we = 1'd0;
+wire [14:0] csrbank2_dfii_pi2_address0_w;
+reg csrbank2_dfii_pi2_baddress0_re = 1'd0;
+wire [2:0] csrbank2_dfii_pi2_baddress0_r;
+reg csrbank2_dfii_pi2_baddress0_we = 1'd0;
+wire [2:0] csrbank2_dfii_pi2_baddress0_w;
+reg csrbank2_dfii_pi2_wrdata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_wrdata0_r;
+reg csrbank2_dfii_pi2_wrdata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_wrdata0_w;
+reg csrbank2_dfii_pi2_rddata_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_rddata_r;
+reg csrbank2_dfii_pi2_rddata_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_rddata_w;
+reg csrbank2_dfii_pi3_command0_re = 1'd0;
+wire [5:0] csrbank2_dfii_pi3_command0_r;
+reg csrbank2_dfii_pi3_command0_we = 1'd0;
+wire [5:0] csrbank2_dfii_pi3_command0_w;
+reg csrbank2_dfii_pi3_address0_re = 1'd0;
+wire [14:0] csrbank2_dfii_pi3_address0_r;
+reg csrbank2_dfii_pi3_address0_we = 1'd0;
+wire [14:0] csrbank2_dfii_pi3_address0_w;
+reg csrbank2_dfii_pi3_baddress0_re = 1'd0;
+wire [2:0] csrbank2_dfii_pi3_baddress0_r;
+reg csrbank2_dfii_pi3_baddress0_we = 1'd0;
+wire [2:0] csrbank2_dfii_pi3_baddress0_w;
+reg csrbank2_dfii_pi3_wrdata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_wrdata0_r;
+reg csrbank2_dfii_pi3_wrdata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_wrdata0_w;
+reg csrbank2_dfii_pi3_rddata_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_rddata_r;
+reg csrbank2_dfii_pi3_rddata_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_rddata_w;
+wire csrbank2_sel;
+wire [13:0] csr_interconnect_adr;
+wire csr_interconnect_we;
+wire [31:0] csr_interconnect_dat_w;
+wire [31:0] csr_interconnect_dat_r;
+wire litedramcore_reset0;
+wire litedramcore_reset1;
+wire litedramcore_reset2;
+wire litedramcore_reset3;
+wire litedramcore_reset4;
+wire litedramcore_reset5;
+wire litedramcore_reset6;
+wire litedramcore_reset7;
+wire litedramcore_pll_fb;
+reg [1:0] litedramcore_refresher_state = 2'd0;
+reg [1:0] litedramcore_refresher_next_state = 2'd0;
+reg [3:0] litedramcore_bankmachine0_state = 4'd0;
+reg [3:0] litedramcore_bankmachine0_next_state = 4'd0;
+reg [3:0] litedramcore_bankmachine1_state = 4'd0;
+reg [3:0] litedramcore_bankmachine1_next_state = 4'd0;
+reg [3:0] litedramcore_bankmachine2_state = 4'd0;
+reg [3:0] litedramcore_bankmachine2_next_state = 4'd0;
+reg [3:0] litedramcore_bankmachine3_state = 4'd0;
+reg [3:0] litedramcore_bankmachine3_next_state = 4'd0;
+reg [3:0] litedramcore_bankmachine4_state = 4'd0;
+reg [3:0] litedramcore_bankmachine4_next_state = 4'd0;
+reg [3:0] litedramcore_bankmachine5_state = 4'd0;
+reg [3:0] litedramcore_bankmachine5_next_state = 4'd0;
+reg [3:0] litedramcore_bankmachine6_state = 4'd0;
+reg [3:0] litedramcore_bankmachine6_next_state = 4'd0;
+reg [3:0] litedramcore_bankmachine7_state = 4'd0;
+reg [3:0] litedramcore_bankmachine7_next_state = 4'd0;
+reg [3:0] litedramcore_multiplexer_state = 4'd0;
+reg [3:0] litedramcore_multiplexer_next_state = 4'd0;
+wire litedramcore_roundrobin0_request;
+wire litedramcore_roundrobin0_grant;
+wire litedramcore_roundrobin0_ce;
+wire litedramcore_roundrobin1_request;
+wire litedramcore_roundrobin1_grant;
+wire litedramcore_roundrobin1_ce;
+wire litedramcore_roundrobin2_request;
+wire litedramcore_roundrobin2_grant;
+wire litedramcore_roundrobin2_ce;
+wire litedramcore_roundrobin3_request;
+wire litedramcore_roundrobin3_grant;
+wire litedramcore_roundrobin3_ce;
+wire litedramcore_roundrobin4_request;
+wire litedramcore_roundrobin4_grant;
+wire litedramcore_roundrobin4_ce;
+wire litedramcore_roundrobin5_request;
+wire litedramcore_roundrobin5_grant;
+wire litedramcore_roundrobin5_ce;
+wire litedramcore_roundrobin6_request;
+wire litedramcore_roundrobin6_grant;
+wire litedramcore_roundrobin6_ce;
+wire litedramcore_roundrobin7_request;
+wire litedramcore_roundrobin7_grant;
+wire litedramcore_roundrobin7_ce;
+reg litedramcore_locked0 = 1'd0;
+reg litedramcore_locked1 = 1'd0;
+reg litedramcore_locked2 = 1'd0;
+reg litedramcore_locked3 = 1'd0;
+reg litedramcore_locked4 = 1'd0;
+reg litedramcore_locked5 = 1'd0;
+reg litedramcore_locked6 = 1'd0;
+reg litedramcore_locked7 = 1'd0;
+reg litedramcore_new_master_wdata_ready0 = 1'd0;
+reg litedramcore_new_master_wdata_ready1 = 1'd0;
+reg litedramcore_new_master_rdata_valid0 = 1'd0;
+reg litedramcore_new_master_rdata_valid1 = 1'd0;
+reg litedramcore_new_master_rdata_valid2 = 1'd0;
+reg litedramcore_new_master_rdata_valid3 = 1'd0;
+reg litedramcore_new_master_rdata_valid4 = 1'd0;
+reg litedramcore_new_master_rdata_valid5 = 1'd0;
+reg litedramcore_new_master_rdata_valid6 = 1'd0;
+reg litedramcore_new_master_rdata_valid7 = 1'd0;
+reg litedramcore_new_master_rdata_valid8 = 1'd0;
+reg [1:0] litedramcore_state = 2'd0;
+reg [1:0] litedramcore_next_state = 2'd0;
+reg [31:0] litedramcore_dat_w_next_value0 = 32'd0;
+reg litedramcore_dat_w_next_value_ce0 = 1'd0;
+reg [13:0] litedramcore_adr_next_value1 = 14'd0;
+reg litedramcore_adr_next_value_ce1 = 1'd0;
+reg litedramcore_we_next_value2 = 1'd0;
+reg litedramcore_we_next_value_ce2 = 1'd0;
+reg rhs_array_muxed0 = 1'd0;
+reg [14:0] rhs_array_muxed1 = 15'd0;
+reg [2:0] rhs_array_muxed2 = 3'd0;
+reg rhs_array_muxed3 = 1'd0;
+reg rhs_array_muxed4 = 1'd0;
+reg rhs_array_muxed5 = 1'd0;
+reg t_array_muxed0 = 1'd0;
+reg t_array_muxed1 = 1'd0;
+reg t_array_muxed2 = 1'd0;
+reg rhs_array_muxed6 = 1'd0;
+reg [14:0] rhs_array_muxed7 = 15'd0;
+reg [2:0] rhs_array_muxed8 = 3'd0;
+reg rhs_array_muxed9 = 1'd0;
+reg rhs_array_muxed10 = 1'd0;
+reg rhs_array_muxed11 = 1'd0;
+reg t_array_muxed3 = 1'd0;
+reg t_array_muxed4 = 1'd0;
+reg t_array_muxed5 = 1'd0;
+reg [21:0] rhs_array_muxed12 = 22'd0;
+reg rhs_array_muxed13 = 1'd0;
+reg rhs_array_muxed14 = 1'd0;
+reg [21:0] rhs_array_muxed15 = 22'd0;
+reg rhs_array_muxed16 = 1'd0;
+reg rhs_array_muxed17 = 1'd0;
+reg [21:0] rhs_array_muxed18 = 22'd0;
+reg rhs_array_muxed19 = 1'd0;
+reg rhs_array_muxed20 = 1'd0;
+reg [21:0] rhs_array_muxed21 = 22'd0;
+reg rhs_array_muxed22 = 1'd0;
+reg rhs_array_muxed23 = 1'd0;
+reg [21:0] rhs_array_muxed24 = 22'd0;
+reg rhs_array_muxed25 = 1'd0;
+reg rhs_array_muxed26 = 1'd0;
+reg [21:0] rhs_array_muxed27 = 22'd0;
+reg rhs_array_muxed28 = 1'd0;
+reg rhs_array_muxed29 = 1'd0;
+reg [21:0] rhs_array_muxed30 = 22'd0;
+reg rhs_array_muxed31 = 1'd0;
+reg rhs_array_muxed32 = 1'd0;
+reg [21:0] rhs_array_muxed33 = 22'd0;
+reg rhs_array_muxed34 = 1'd0;
+reg rhs_array_muxed35 = 1'd0;
+reg [2:0] array_muxed0 = 3'd0;
+reg [14:0] array_muxed1 = 15'd0;
+reg array_muxed2 = 1'd0;
+reg array_muxed3 = 1'd0;
+reg array_muxed4 = 1'd0;
+reg array_muxed5 = 1'd0;
+reg array_muxed6 = 1'd0;
+reg [2:0] array_muxed7 = 3'd0;
+reg [14:0] array_muxed8 = 15'd0;
+reg array_muxed9 = 1'd0;
+reg array_muxed10 = 1'd0;
+reg array_muxed11 = 1'd0;
+reg array_muxed12 = 1'd0;
+reg array_muxed13 = 1'd0;
+reg [2:0] array_muxed14 = 3'd0;
+reg [14:0] array_muxed15 = 15'd0;
+reg array_muxed16 = 1'd0;
+reg array_muxed17 = 1'd0;
+reg array_muxed18 = 1'd0;
+reg array_muxed19 = 1'd0;
+reg array_muxed20 = 1'd0;
+reg [2:0] array_muxed21 = 3'd0;
+reg [14:0] array_muxed22 = 15'd0;
+reg array_muxed23 = 1'd0;
+reg array_muxed24 = 1'd0;
+reg array_muxed25 = 1'd0;
+reg array_muxed26 = 1'd0;
+reg array_muxed27 = 1'd0;
+wire xilinxasyncresetsynchronizerimpl0;
+wire xilinxasyncresetsynchronizerimpl0_rst_meta;
+wire xilinxasyncresetsynchronizerimpl1;
+wire xilinxasyncresetsynchronizerimpl1_rst_meta;
+wire xilinxasyncresetsynchronizerimpl2;
+wire xilinxasyncresetsynchronizerimpl2_rst_meta;
+wire xilinxasyncresetsynchronizerimpl2_expr;
+wire xilinxasyncresetsynchronizerimpl3;
+wire xilinxasyncresetsynchronizerimpl3_rst_meta;
+wire xilinxasyncresetsynchronizerimpl3_expr;
//------------------------------------------------------------------------------
// Combinatorial Logic
assign a7ddrphy_dqs_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dqs_oe) | a7ddrphy_dqs_postamble);
assign a7ddrphy_dq_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dq_oe) | a7ddrphy_dqs_postamble);
always @(*) begin
- a7ddrphy_dfi_p0_rddata <= 32'd0;
- a7ddrphy_dfi_p0_rddata[0] <= a7ddrphy_bitslip04[0];
- a7ddrphy_dfi_p0_rddata[16] <= a7ddrphy_bitslip04[1];
- a7ddrphy_dfi_p0_rddata[1] <= a7ddrphy_bitslip14[0];
- a7ddrphy_dfi_p0_rddata[17] <= a7ddrphy_bitslip14[1];
- a7ddrphy_dfi_p0_rddata[2] <= a7ddrphy_bitslip22[0];
- a7ddrphy_dfi_p0_rddata[18] <= a7ddrphy_bitslip22[1];
- a7ddrphy_dfi_p0_rddata[3] <= a7ddrphy_bitslip32[0];
- a7ddrphy_dfi_p0_rddata[19] <= a7ddrphy_bitslip32[1];
- a7ddrphy_dfi_p0_rddata[4] <= a7ddrphy_bitslip42[0];
- a7ddrphy_dfi_p0_rddata[20] <= a7ddrphy_bitslip42[1];
- a7ddrphy_dfi_p0_rddata[5] <= a7ddrphy_bitslip52[0];
- a7ddrphy_dfi_p0_rddata[21] <= a7ddrphy_bitslip52[1];
- a7ddrphy_dfi_p0_rddata[6] <= a7ddrphy_bitslip62[0];
- a7ddrphy_dfi_p0_rddata[22] <= a7ddrphy_bitslip62[1];
- a7ddrphy_dfi_p0_rddata[7] <= a7ddrphy_bitslip72[0];
- a7ddrphy_dfi_p0_rddata[23] <= a7ddrphy_bitslip72[1];
- a7ddrphy_dfi_p0_rddata[8] <= a7ddrphy_bitslip82[0];
- a7ddrphy_dfi_p0_rddata[24] <= a7ddrphy_bitslip82[1];
- a7ddrphy_dfi_p0_rddata[9] <= a7ddrphy_bitslip92[0];
- a7ddrphy_dfi_p0_rddata[25] <= a7ddrphy_bitslip92[1];
- a7ddrphy_dfi_p0_rddata[10] <= a7ddrphy_bitslip102[0];
- a7ddrphy_dfi_p0_rddata[26] <= a7ddrphy_bitslip102[1];
- a7ddrphy_dfi_p0_rddata[11] <= a7ddrphy_bitslip112[0];
- a7ddrphy_dfi_p0_rddata[27] <= a7ddrphy_bitslip112[1];
- a7ddrphy_dfi_p0_rddata[12] <= a7ddrphy_bitslip122[0];
- a7ddrphy_dfi_p0_rddata[28] <= a7ddrphy_bitslip122[1];
- a7ddrphy_dfi_p0_rddata[13] <= a7ddrphy_bitslip132[0];
- a7ddrphy_dfi_p0_rddata[29] <= a7ddrphy_bitslip132[1];
- a7ddrphy_dfi_p0_rddata[14] <= a7ddrphy_bitslip142[0];
- a7ddrphy_dfi_p0_rddata[30] <= a7ddrphy_bitslip142[1];
- a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip152[0];
- a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip152[1];
-end
-always @(*) begin
- a7ddrphy_dfi_p1_rddata <= 32'd0;
- a7ddrphy_dfi_p1_rddata[0] <= a7ddrphy_bitslip04[2];
- a7ddrphy_dfi_p1_rddata[16] <= a7ddrphy_bitslip04[3];
- a7ddrphy_dfi_p1_rddata[1] <= a7ddrphy_bitslip14[2];
- a7ddrphy_dfi_p1_rddata[17] <= a7ddrphy_bitslip14[3];
- a7ddrphy_dfi_p1_rddata[2] <= a7ddrphy_bitslip22[2];
- a7ddrphy_dfi_p1_rddata[18] <= a7ddrphy_bitslip22[3];
- a7ddrphy_dfi_p1_rddata[3] <= a7ddrphy_bitslip32[2];
- a7ddrphy_dfi_p1_rddata[19] <= a7ddrphy_bitslip32[3];
- a7ddrphy_dfi_p1_rddata[4] <= a7ddrphy_bitslip42[2];
- a7ddrphy_dfi_p1_rddata[20] <= a7ddrphy_bitslip42[3];
- a7ddrphy_dfi_p1_rddata[5] <= a7ddrphy_bitslip52[2];
- a7ddrphy_dfi_p1_rddata[21] <= a7ddrphy_bitslip52[3];
- a7ddrphy_dfi_p1_rddata[6] <= a7ddrphy_bitslip62[2];
- a7ddrphy_dfi_p1_rddata[22] <= a7ddrphy_bitslip62[3];
- a7ddrphy_dfi_p1_rddata[7] <= a7ddrphy_bitslip72[2];
- a7ddrphy_dfi_p1_rddata[23] <= a7ddrphy_bitslip72[3];
- a7ddrphy_dfi_p1_rddata[8] <= a7ddrphy_bitslip82[2];
- a7ddrphy_dfi_p1_rddata[24] <= a7ddrphy_bitslip82[3];
- a7ddrphy_dfi_p1_rddata[9] <= a7ddrphy_bitslip92[2];
- a7ddrphy_dfi_p1_rddata[25] <= a7ddrphy_bitslip92[3];
- a7ddrphy_dfi_p1_rddata[10] <= a7ddrphy_bitslip102[2];
- a7ddrphy_dfi_p1_rddata[26] <= a7ddrphy_bitslip102[3];
- a7ddrphy_dfi_p1_rddata[11] <= a7ddrphy_bitslip112[2];
- a7ddrphy_dfi_p1_rddata[27] <= a7ddrphy_bitslip112[3];
- a7ddrphy_dfi_p1_rddata[12] <= a7ddrphy_bitslip122[2];
- a7ddrphy_dfi_p1_rddata[28] <= a7ddrphy_bitslip122[3];
- a7ddrphy_dfi_p1_rddata[13] <= a7ddrphy_bitslip132[2];
- a7ddrphy_dfi_p1_rddata[29] <= a7ddrphy_bitslip132[3];
- a7ddrphy_dfi_p1_rddata[14] <= a7ddrphy_bitslip142[2];
- a7ddrphy_dfi_p1_rddata[30] <= a7ddrphy_bitslip142[3];
- a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip152[2];
- a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip152[3];
-end
-always @(*) begin
- a7ddrphy_dfi_p2_rddata <= 32'd0;
- a7ddrphy_dfi_p2_rddata[0] <= a7ddrphy_bitslip04[4];
- a7ddrphy_dfi_p2_rddata[16] <= a7ddrphy_bitslip04[5];
- a7ddrphy_dfi_p2_rddata[1] <= a7ddrphy_bitslip14[4];
- a7ddrphy_dfi_p2_rddata[17] <= a7ddrphy_bitslip14[5];
- a7ddrphy_dfi_p2_rddata[2] <= a7ddrphy_bitslip22[4];
- a7ddrphy_dfi_p2_rddata[18] <= a7ddrphy_bitslip22[5];
- a7ddrphy_dfi_p2_rddata[3] <= a7ddrphy_bitslip32[4];
- a7ddrphy_dfi_p2_rddata[19] <= a7ddrphy_bitslip32[5];
- a7ddrphy_dfi_p2_rddata[4] <= a7ddrphy_bitslip42[4];
- a7ddrphy_dfi_p2_rddata[20] <= a7ddrphy_bitslip42[5];
- a7ddrphy_dfi_p2_rddata[5] <= a7ddrphy_bitslip52[4];
- a7ddrphy_dfi_p2_rddata[21] <= a7ddrphy_bitslip52[5];
- a7ddrphy_dfi_p2_rddata[6] <= a7ddrphy_bitslip62[4];
- a7ddrphy_dfi_p2_rddata[22] <= a7ddrphy_bitslip62[5];
- a7ddrphy_dfi_p2_rddata[7] <= a7ddrphy_bitslip72[4];
- a7ddrphy_dfi_p2_rddata[23] <= a7ddrphy_bitslip72[5];
- a7ddrphy_dfi_p2_rddata[8] <= a7ddrphy_bitslip82[4];
- a7ddrphy_dfi_p2_rddata[24] <= a7ddrphy_bitslip82[5];
- a7ddrphy_dfi_p2_rddata[9] <= a7ddrphy_bitslip92[4];
- a7ddrphy_dfi_p2_rddata[25] <= a7ddrphy_bitslip92[5];
- a7ddrphy_dfi_p2_rddata[10] <= a7ddrphy_bitslip102[4];
- a7ddrphy_dfi_p2_rddata[26] <= a7ddrphy_bitslip102[5];
- a7ddrphy_dfi_p2_rddata[11] <= a7ddrphy_bitslip112[4];
- a7ddrphy_dfi_p2_rddata[27] <= a7ddrphy_bitslip112[5];
- a7ddrphy_dfi_p2_rddata[12] <= a7ddrphy_bitslip122[4];
- a7ddrphy_dfi_p2_rddata[28] <= a7ddrphy_bitslip122[5];
- a7ddrphy_dfi_p2_rddata[13] <= a7ddrphy_bitslip132[4];
- a7ddrphy_dfi_p2_rddata[29] <= a7ddrphy_bitslip132[5];
- a7ddrphy_dfi_p2_rddata[14] <= a7ddrphy_bitslip142[4];
- a7ddrphy_dfi_p2_rddata[30] <= a7ddrphy_bitslip142[5];
- a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip152[4];
- a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip152[5];
-end
-always @(*) begin
- a7ddrphy_dfi_p3_rddata <= 32'd0;
- a7ddrphy_dfi_p3_rddata[0] <= a7ddrphy_bitslip04[6];
- a7ddrphy_dfi_p3_rddata[16] <= a7ddrphy_bitslip04[7];
- a7ddrphy_dfi_p3_rddata[1] <= a7ddrphy_bitslip14[6];
- a7ddrphy_dfi_p3_rddata[17] <= a7ddrphy_bitslip14[7];
- a7ddrphy_dfi_p3_rddata[2] <= a7ddrphy_bitslip22[6];
- a7ddrphy_dfi_p3_rddata[18] <= a7ddrphy_bitslip22[7];
- a7ddrphy_dfi_p3_rddata[3] <= a7ddrphy_bitslip32[6];
- a7ddrphy_dfi_p3_rddata[19] <= a7ddrphy_bitslip32[7];
- a7ddrphy_dfi_p3_rddata[4] <= a7ddrphy_bitslip42[6];
- a7ddrphy_dfi_p3_rddata[20] <= a7ddrphy_bitslip42[7];
- a7ddrphy_dfi_p3_rddata[5] <= a7ddrphy_bitslip52[6];
- a7ddrphy_dfi_p3_rddata[21] <= a7ddrphy_bitslip52[7];
- a7ddrphy_dfi_p3_rddata[6] <= a7ddrphy_bitslip62[6];
- a7ddrphy_dfi_p3_rddata[22] <= a7ddrphy_bitslip62[7];
- a7ddrphy_dfi_p3_rddata[7] <= a7ddrphy_bitslip72[6];
- a7ddrphy_dfi_p3_rddata[23] <= a7ddrphy_bitslip72[7];
- a7ddrphy_dfi_p3_rddata[8] <= a7ddrphy_bitslip82[6];
- a7ddrphy_dfi_p3_rddata[24] <= a7ddrphy_bitslip82[7];
- a7ddrphy_dfi_p3_rddata[9] <= a7ddrphy_bitslip92[6];
- a7ddrphy_dfi_p3_rddata[25] <= a7ddrphy_bitslip92[7];
- a7ddrphy_dfi_p3_rddata[10] <= a7ddrphy_bitslip102[6];
- a7ddrphy_dfi_p3_rddata[26] <= a7ddrphy_bitslip102[7];
- a7ddrphy_dfi_p3_rddata[11] <= a7ddrphy_bitslip112[6];
- a7ddrphy_dfi_p3_rddata[27] <= a7ddrphy_bitslip112[7];
- a7ddrphy_dfi_p3_rddata[12] <= a7ddrphy_bitslip122[6];
- a7ddrphy_dfi_p3_rddata[28] <= a7ddrphy_bitslip122[7];
- a7ddrphy_dfi_p3_rddata[13] <= a7ddrphy_bitslip132[6];
- a7ddrphy_dfi_p3_rddata[29] <= a7ddrphy_bitslip132[7];
- a7ddrphy_dfi_p3_rddata[14] <= a7ddrphy_bitslip142[6];
- a7ddrphy_dfi_p3_rddata[30] <= a7ddrphy_bitslip142[7];
- a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip152[6];
- a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip152[7];
+ a7ddrphy_dfi_p0_rddata <= 32'd0;
+ a7ddrphy_dfi_p0_rddata[0] <= a7ddrphy_bitslip04[0];
+ a7ddrphy_dfi_p0_rddata[16] <= a7ddrphy_bitslip04[1];
+ a7ddrphy_dfi_p0_rddata[1] <= a7ddrphy_bitslip14[0];
+ a7ddrphy_dfi_p0_rddata[17] <= a7ddrphy_bitslip14[1];
+ a7ddrphy_dfi_p0_rddata[2] <= a7ddrphy_bitslip22[0];
+ a7ddrphy_dfi_p0_rddata[18] <= a7ddrphy_bitslip22[1];
+ a7ddrphy_dfi_p0_rddata[3] <= a7ddrphy_bitslip32[0];
+ a7ddrphy_dfi_p0_rddata[19] <= a7ddrphy_bitslip32[1];
+ a7ddrphy_dfi_p0_rddata[4] <= a7ddrphy_bitslip42[0];
+ a7ddrphy_dfi_p0_rddata[20] <= a7ddrphy_bitslip42[1];
+ a7ddrphy_dfi_p0_rddata[5] <= a7ddrphy_bitslip52[0];
+ a7ddrphy_dfi_p0_rddata[21] <= a7ddrphy_bitslip52[1];
+ a7ddrphy_dfi_p0_rddata[6] <= a7ddrphy_bitslip62[0];
+ a7ddrphy_dfi_p0_rddata[22] <= a7ddrphy_bitslip62[1];
+ a7ddrphy_dfi_p0_rddata[7] <= a7ddrphy_bitslip72[0];
+ a7ddrphy_dfi_p0_rddata[23] <= a7ddrphy_bitslip72[1];
+ a7ddrphy_dfi_p0_rddata[8] <= a7ddrphy_bitslip82[0];
+ a7ddrphy_dfi_p0_rddata[24] <= a7ddrphy_bitslip82[1];
+ a7ddrphy_dfi_p0_rddata[9] <= a7ddrphy_bitslip92[0];
+ a7ddrphy_dfi_p0_rddata[25] <= a7ddrphy_bitslip92[1];
+ a7ddrphy_dfi_p0_rddata[10] <= a7ddrphy_bitslip102[0];
+ a7ddrphy_dfi_p0_rddata[26] <= a7ddrphy_bitslip102[1];
+ a7ddrphy_dfi_p0_rddata[11] <= a7ddrphy_bitslip112[0];
+ a7ddrphy_dfi_p0_rddata[27] <= a7ddrphy_bitslip112[1];
+ a7ddrphy_dfi_p0_rddata[12] <= a7ddrphy_bitslip122[0];
+ a7ddrphy_dfi_p0_rddata[28] <= a7ddrphy_bitslip122[1];
+ a7ddrphy_dfi_p0_rddata[13] <= a7ddrphy_bitslip132[0];
+ a7ddrphy_dfi_p0_rddata[29] <= a7ddrphy_bitslip132[1];
+ a7ddrphy_dfi_p0_rddata[14] <= a7ddrphy_bitslip142[0];
+ a7ddrphy_dfi_p0_rddata[30] <= a7ddrphy_bitslip142[1];
+ a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip152[0];
+ a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip152[1];
+end
+always @(*) begin
+ a7ddrphy_dfi_p1_rddata <= 32'd0;
+ a7ddrphy_dfi_p1_rddata[0] <= a7ddrphy_bitslip04[2];
+ a7ddrphy_dfi_p1_rddata[16] <= a7ddrphy_bitslip04[3];
+ a7ddrphy_dfi_p1_rddata[1] <= a7ddrphy_bitslip14[2];
+ a7ddrphy_dfi_p1_rddata[17] <= a7ddrphy_bitslip14[3];
+ a7ddrphy_dfi_p1_rddata[2] <= a7ddrphy_bitslip22[2];
+ a7ddrphy_dfi_p1_rddata[18] <= a7ddrphy_bitslip22[3];
+ a7ddrphy_dfi_p1_rddata[3] <= a7ddrphy_bitslip32[2];
+ a7ddrphy_dfi_p1_rddata[19] <= a7ddrphy_bitslip32[3];
+ a7ddrphy_dfi_p1_rddata[4] <= a7ddrphy_bitslip42[2];
+ a7ddrphy_dfi_p1_rddata[20] <= a7ddrphy_bitslip42[3];
+ a7ddrphy_dfi_p1_rddata[5] <= a7ddrphy_bitslip52[2];
+ a7ddrphy_dfi_p1_rddata[21] <= a7ddrphy_bitslip52[3];
+ a7ddrphy_dfi_p1_rddata[6] <= a7ddrphy_bitslip62[2];
+ a7ddrphy_dfi_p1_rddata[22] <= a7ddrphy_bitslip62[3];
+ a7ddrphy_dfi_p1_rddata[7] <= a7ddrphy_bitslip72[2];
+ a7ddrphy_dfi_p1_rddata[23] <= a7ddrphy_bitslip72[3];
+ a7ddrphy_dfi_p1_rddata[8] <= a7ddrphy_bitslip82[2];
+ a7ddrphy_dfi_p1_rddata[24] <= a7ddrphy_bitslip82[3];
+ a7ddrphy_dfi_p1_rddata[9] <= a7ddrphy_bitslip92[2];
+ a7ddrphy_dfi_p1_rddata[25] <= a7ddrphy_bitslip92[3];
+ a7ddrphy_dfi_p1_rddata[10] <= a7ddrphy_bitslip102[2];
+ a7ddrphy_dfi_p1_rddata[26] <= a7ddrphy_bitslip102[3];
+ a7ddrphy_dfi_p1_rddata[11] <= a7ddrphy_bitslip112[2];
+ a7ddrphy_dfi_p1_rddata[27] <= a7ddrphy_bitslip112[3];
+ a7ddrphy_dfi_p1_rddata[12] <= a7ddrphy_bitslip122[2];
+ a7ddrphy_dfi_p1_rddata[28] <= a7ddrphy_bitslip122[3];
+ a7ddrphy_dfi_p1_rddata[13] <= a7ddrphy_bitslip132[2];
+ a7ddrphy_dfi_p1_rddata[29] <= a7ddrphy_bitslip132[3];
+ a7ddrphy_dfi_p1_rddata[14] <= a7ddrphy_bitslip142[2];
+ a7ddrphy_dfi_p1_rddata[30] <= a7ddrphy_bitslip142[3];
+ a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip152[2];
+ a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip152[3];
+end
+always @(*) begin
+ a7ddrphy_dfi_p2_rddata <= 32'd0;
+ a7ddrphy_dfi_p2_rddata[0] <= a7ddrphy_bitslip04[4];
+ a7ddrphy_dfi_p2_rddata[16] <= a7ddrphy_bitslip04[5];
+ a7ddrphy_dfi_p2_rddata[1] <= a7ddrphy_bitslip14[4];
+ a7ddrphy_dfi_p2_rddata[17] <= a7ddrphy_bitslip14[5];
+ a7ddrphy_dfi_p2_rddata[2] <= a7ddrphy_bitslip22[4];
+ a7ddrphy_dfi_p2_rddata[18] <= a7ddrphy_bitslip22[5];
+ a7ddrphy_dfi_p2_rddata[3] <= a7ddrphy_bitslip32[4];
+ a7ddrphy_dfi_p2_rddata[19] <= a7ddrphy_bitslip32[5];
+ a7ddrphy_dfi_p2_rddata[4] <= a7ddrphy_bitslip42[4];
+ a7ddrphy_dfi_p2_rddata[20] <= a7ddrphy_bitslip42[5];
+ a7ddrphy_dfi_p2_rddata[5] <= a7ddrphy_bitslip52[4];
+ a7ddrphy_dfi_p2_rddata[21] <= a7ddrphy_bitslip52[5];
+ a7ddrphy_dfi_p2_rddata[6] <= a7ddrphy_bitslip62[4];
+ a7ddrphy_dfi_p2_rddata[22] <= a7ddrphy_bitslip62[5];
+ a7ddrphy_dfi_p2_rddata[7] <= a7ddrphy_bitslip72[4];
+ a7ddrphy_dfi_p2_rddata[23] <= a7ddrphy_bitslip72[5];
+ a7ddrphy_dfi_p2_rddata[8] <= a7ddrphy_bitslip82[4];
+ a7ddrphy_dfi_p2_rddata[24] <= a7ddrphy_bitslip82[5];
+ a7ddrphy_dfi_p2_rddata[9] <= a7ddrphy_bitslip92[4];
+ a7ddrphy_dfi_p2_rddata[25] <= a7ddrphy_bitslip92[5];
+ a7ddrphy_dfi_p2_rddata[10] <= a7ddrphy_bitslip102[4];
+ a7ddrphy_dfi_p2_rddata[26] <= a7ddrphy_bitslip102[5];
+ a7ddrphy_dfi_p2_rddata[11] <= a7ddrphy_bitslip112[4];
+ a7ddrphy_dfi_p2_rddata[27] <= a7ddrphy_bitslip112[5];
+ a7ddrphy_dfi_p2_rddata[12] <= a7ddrphy_bitslip122[4];
+ a7ddrphy_dfi_p2_rddata[28] <= a7ddrphy_bitslip122[5];
+ a7ddrphy_dfi_p2_rddata[13] <= a7ddrphy_bitslip132[4];
+ a7ddrphy_dfi_p2_rddata[29] <= a7ddrphy_bitslip132[5];
+ a7ddrphy_dfi_p2_rddata[14] <= a7ddrphy_bitslip142[4];
+ a7ddrphy_dfi_p2_rddata[30] <= a7ddrphy_bitslip142[5];
+ a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip152[4];
+ a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip152[5];
+end
+always @(*) begin
+ a7ddrphy_dfi_p3_rddata <= 32'd0;
+ a7ddrphy_dfi_p3_rddata[0] <= a7ddrphy_bitslip04[6];
+ a7ddrphy_dfi_p3_rddata[16] <= a7ddrphy_bitslip04[7];
+ a7ddrphy_dfi_p3_rddata[1] <= a7ddrphy_bitslip14[6];
+ a7ddrphy_dfi_p3_rddata[17] <= a7ddrphy_bitslip14[7];
+ a7ddrphy_dfi_p3_rddata[2] <= a7ddrphy_bitslip22[6];
+ a7ddrphy_dfi_p3_rddata[18] <= a7ddrphy_bitslip22[7];
+ a7ddrphy_dfi_p3_rddata[3] <= a7ddrphy_bitslip32[6];
+ a7ddrphy_dfi_p3_rddata[19] <= a7ddrphy_bitslip32[7];
+ a7ddrphy_dfi_p3_rddata[4] <= a7ddrphy_bitslip42[6];
+ a7ddrphy_dfi_p3_rddata[20] <= a7ddrphy_bitslip42[7];
+ a7ddrphy_dfi_p3_rddata[5] <= a7ddrphy_bitslip52[6];
+ a7ddrphy_dfi_p3_rddata[21] <= a7ddrphy_bitslip52[7];
+ a7ddrphy_dfi_p3_rddata[6] <= a7ddrphy_bitslip62[6];
+ a7ddrphy_dfi_p3_rddata[22] <= a7ddrphy_bitslip62[7];
+ a7ddrphy_dfi_p3_rddata[7] <= a7ddrphy_bitslip72[6];
+ a7ddrphy_dfi_p3_rddata[23] <= a7ddrphy_bitslip72[7];
+ a7ddrphy_dfi_p3_rddata[8] <= a7ddrphy_bitslip82[6];
+ a7ddrphy_dfi_p3_rddata[24] <= a7ddrphy_bitslip82[7];
+ a7ddrphy_dfi_p3_rddata[9] <= a7ddrphy_bitslip92[6];
+ a7ddrphy_dfi_p3_rddata[25] <= a7ddrphy_bitslip92[7];
+ a7ddrphy_dfi_p3_rddata[10] <= a7ddrphy_bitslip102[6];
+ a7ddrphy_dfi_p3_rddata[26] <= a7ddrphy_bitslip102[7];
+ a7ddrphy_dfi_p3_rddata[11] <= a7ddrphy_bitslip112[6];
+ a7ddrphy_dfi_p3_rddata[27] <= a7ddrphy_bitslip112[7];
+ a7ddrphy_dfi_p3_rddata[12] <= a7ddrphy_bitslip122[6];
+ a7ddrphy_dfi_p3_rddata[28] <= a7ddrphy_bitslip122[7];
+ a7ddrphy_dfi_p3_rddata[13] <= a7ddrphy_bitslip132[6];
+ a7ddrphy_dfi_p3_rddata[29] <= a7ddrphy_bitslip132[7];
+ a7ddrphy_dfi_p3_rddata[14] <= a7ddrphy_bitslip142[6];
+ a7ddrphy_dfi_p3_rddata[30] <= a7ddrphy_bitslip142[7];
+ a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip152[6];
+ a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip152[7];
end
assign a7ddrphy_dfi_p0_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage);
assign a7ddrphy_dfi_p1_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage);
assign a7ddrphy_dfi_p3_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage);
assign a7ddrphy_dq_oe = a7ddrphy_wrdata_en_tappeddelayline1;
always @(*) begin
- a7ddrphy_dqs_oe <= 1'd0;
- if (a7ddrphy_wlevel_en_storage) begin
- a7ddrphy_dqs_oe <= 1'd1;
- end else begin
- a7ddrphy_dqs_oe <= a7ddrphy_dq_oe;
- end
+ a7ddrphy_dqs_oe <= 1'd0;
+ if (a7ddrphy_wlevel_en_storage) begin
+ a7ddrphy_dqs_oe <= 1'd1;
+ end else begin
+ a7ddrphy_dqs_oe <= a7ddrphy_dq_oe;
+ end
end
assign a7ddrphy_dqs_preamble = (a7ddrphy_wrdata_en_tappeddelayline0 & (~a7ddrphy_wrdata_en_tappeddelayline1));
assign a7ddrphy_dqs_postamble = (a7ddrphy_wrdata_en_tappeddelayline2 & (~a7ddrphy_wrdata_en_tappeddelayline1));
always @(*) begin
- a7ddrphy_dqspattern_o0 <= 8'd0;
- a7ddrphy_dqspattern_o0 <= 7'd85;
- if (a7ddrphy_dqspattern0) begin
- a7ddrphy_dqspattern_o0 <= 5'd21;
- end
- if (a7ddrphy_dqspattern1) begin
- a7ddrphy_dqspattern_o0 <= 7'd84;
- end
- if (a7ddrphy_wlevel_en_storage) begin
- a7ddrphy_dqspattern_o0 <= 1'd0;
- if (a7ddrphy_wlevel_strobe_re) begin
- a7ddrphy_dqspattern_o0 <= 1'd1;
- end
- end
-end
-always @(*) begin
- a7ddrphy_bitslip00 <= 8'd0;
- case (a7ddrphy_bitslip0_value0)
- 1'd0: begin
- a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip10 <= 8'd0;
- case (a7ddrphy_bitslip1_value0)
- 1'd0: begin
- a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip01 <= 8'd0;
- case (a7ddrphy_bitslip0_value1)
- 1'd0: begin
- a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip11 <= 8'd0;
- case (a7ddrphy_bitslip1_value1)
- 1'd0: begin
- a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip02 <= 8'd0;
- case (a7ddrphy_bitslip0_value2)
- 1'd0: begin
- a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip04 <= 8'd0;
- case (a7ddrphy_bitslip0_value3)
- 1'd0: begin
- a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip12 <= 8'd0;
- case (a7ddrphy_bitslip1_value2)
- 1'd0: begin
- a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip14 <= 8'd0;
- case (a7ddrphy_bitslip1_value3)
- 1'd0: begin
- a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip20 <= 8'd0;
- case (a7ddrphy_bitslip2_value0)
- 1'd0: begin
- a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip22 <= 8'd0;
- case (a7ddrphy_bitslip2_value1)
- 1'd0: begin
- a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip30 <= 8'd0;
- case (a7ddrphy_bitslip3_value0)
- 1'd0: begin
- a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip32 <= 8'd0;
- case (a7ddrphy_bitslip3_value1)
- 1'd0: begin
- a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip40 <= 8'd0;
- case (a7ddrphy_bitslip4_value0)
- 1'd0: begin
- a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip42 <= 8'd0;
- case (a7ddrphy_bitslip4_value1)
- 1'd0: begin
- a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip50 <= 8'd0;
- case (a7ddrphy_bitslip5_value0)
- 1'd0: begin
- a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip52 <= 8'd0;
- case (a7ddrphy_bitslip5_value1)
- 1'd0: begin
- a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip60 <= 8'd0;
- case (a7ddrphy_bitslip6_value0)
- 1'd0: begin
- a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip62 <= 8'd0;
- case (a7ddrphy_bitslip6_value1)
- 1'd0: begin
- a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip70 <= 8'd0;
- case (a7ddrphy_bitslip7_value0)
- 1'd0: begin
- a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip72 <= 8'd0;
- case (a7ddrphy_bitslip7_value1)
- 1'd0: begin
- a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip80 <= 8'd0;
- case (a7ddrphy_bitslip8_value0)
- 1'd0: begin
- a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip82 <= 8'd0;
- case (a7ddrphy_bitslip8_value1)
- 1'd0: begin
- a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip90 <= 8'd0;
- case (a7ddrphy_bitslip9_value0)
- 1'd0: begin
- a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip92 <= 8'd0;
- case (a7ddrphy_bitslip9_value1)
- 1'd0: begin
- a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip100 <= 8'd0;
- case (a7ddrphy_bitslip10_value0)
- 1'd0: begin
- a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip102 <= 8'd0;
- case (a7ddrphy_bitslip10_value1)
- 1'd0: begin
- a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip110 <= 8'd0;
- case (a7ddrphy_bitslip11_value0)
- 1'd0: begin
- a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip112 <= 8'd0;
- case (a7ddrphy_bitslip11_value1)
- 1'd0: begin
- a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip120 <= 8'd0;
- case (a7ddrphy_bitslip12_value0)
- 1'd0: begin
- a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip122 <= 8'd0;
- case (a7ddrphy_bitslip12_value1)
- 1'd0: begin
- a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip130 <= 8'd0;
- case (a7ddrphy_bitslip13_value0)
- 1'd0: begin
- a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip132 <= 8'd0;
- case (a7ddrphy_bitslip13_value1)
- 1'd0: begin
- a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip140 <= 8'd0;
- case (a7ddrphy_bitslip14_value0)
- 1'd0: begin
- a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip142 <= 8'd0;
- case (a7ddrphy_bitslip14_value1)
- 1'd0: begin
- a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip150 <= 8'd0;
- case (a7ddrphy_bitslip15_value0)
- 1'd0: begin
- a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip152 <= 8'd0;
- case (a7ddrphy_bitslip15_value1)
- 1'd0: begin
- a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[15:8];
- end
- endcase
+ a7ddrphy_dqspattern_o0 <= 8'd0;
+ a7ddrphy_dqspattern_o0 <= 7'd85;
+ if (a7ddrphy_dqspattern0) begin
+ a7ddrphy_dqspattern_o0 <= 5'd21;
+ end
+ if (a7ddrphy_dqspattern1) begin
+ a7ddrphy_dqspattern_o0 <= 7'd84;
+ end
+ if (a7ddrphy_wlevel_en_storage) begin
+ a7ddrphy_dqspattern_o0 <= 1'd0;
+ if (a7ddrphy_wlevel_strobe_re) begin
+ a7ddrphy_dqspattern_o0 <= 1'd1;
+ end
+ end
+end
+always @(*) begin
+ a7ddrphy_bitslip00 <= 8'd0;
+ case (a7ddrphy_bitslip0_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip10 <= 8'd0;
+ case (a7ddrphy_bitslip1_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip01 <= 8'd0;
+ case (a7ddrphy_bitslip0_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip11 <= 8'd0;
+ case (a7ddrphy_bitslip1_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip02 <= 8'd0;
+ case (a7ddrphy_bitslip0_value2)
+ 1'd0: begin
+ a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip04 <= 8'd0;
+ case (a7ddrphy_bitslip0_value3)
+ 1'd0: begin
+ a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip12 <= 8'd0;
+ case (a7ddrphy_bitslip1_value2)
+ 1'd0: begin
+ a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip14 <= 8'd0;
+ case (a7ddrphy_bitslip1_value3)
+ 1'd0: begin
+ a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip20 <= 8'd0;
+ case (a7ddrphy_bitslip2_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip22 <= 8'd0;
+ case (a7ddrphy_bitslip2_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip30 <= 8'd0;
+ case (a7ddrphy_bitslip3_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip32 <= 8'd0;
+ case (a7ddrphy_bitslip3_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip40 <= 8'd0;
+ case (a7ddrphy_bitslip4_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip42 <= 8'd0;
+ case (a7ddrphy_bitslip4_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip50 <= 8'd0;
+ case (a7ddrphy_bitslip5_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip52 <= 8'd0;
+ case (a7ddrphy_bitslip5_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip60 <= 8'd0;
+ case (a7ddrphy_bitslip6_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip62 <= 8'd0;
+ case (a7ddrphy_bitslip6_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip70 <= 8'd0;
+ case (a7ddrphy_bitslip7_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip72 <= 8'd0;
+ case (a7ddrphy_bitslip7_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip80 <= 8'd0;
+ case (a7ddrphy_bitslip8_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip82 <= 8'd0;
+ case (a7ddrphy_bitslip8_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip90 <= 8'd0;
+ case (a7ddrphy_bitslip9_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip92 <= 8'd0;
+ case (a7ddrphy_bitslip9_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip100 <= 8'd0;
+ case (a7ddrphy_bitslip10_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip102 <= 8'd0;
+ case (a7ddrphy_bitslip10_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip110 <= 8'd0;
+ case (a7ddrphy_bitslip11_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip112 <= 8'd0;
+ case (a7ddrphy_bitslip11_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip120 <= 8'd0;
+ case (a7ddrphy_bitslip12_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip122 <= 8'd0;
+ case (a7ddrphy_bitslip12_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip130 <= 8'd0;
+ case (a7ddrphy_bitslip13_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip132 <= 8'd0;
+ case (a7ddrphy_bitslip13_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip140 <= 8'd0;
+ case (a7ddrphy_bitslip14_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip142 <= 8'd0;
+ case (a7ddrphy_bitslip14_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip150 <= 8'd0;
+ case (a7ddrphy_bitslip15_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip152 <= 8'd0;
+ case (a7ddrphy_bitslip15_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[15:8];
+ end
+ endcase
end
assign a7ddrphy_dfi_p0_address = litedramcore_master_p0_address;
assign a7ddrphy_dfi_p0_bank = litedramcore_master_p0_bank;
assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata;
assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid;
always @(*) begin
- litedramcore_csr_dfi_p0_rddata <= 32'd0;
- if (litedramcore_sel) begin
- end else begin
- litedramcore_csr_dfi_p0_rddata <= litedramcore_master_p0_rddata;
- end
+ litedramcore_csr_dfi_p0_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_csr_dfi_p0_rddata <= litedramcore_master_p0_rddata;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p0_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- end else begin
- litedramcore_csr_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
- end
-end
-always @(*) begin
- litedramcore_csr_dfi_p1_rddata <= 32'd0;
- if (litedramcore_sel) begin
- end else begin
- litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata;
- end
-end
-always @(*) begin
- litedramcore_csr_dfi_p1_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- end else begin
- litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
- end
-end
-always @(*) begin
- litedramcore_csr_dfi_p2_rddata <= 32'd0;
- if (litedramcore_sel) begin
- end else begin
- litedramcore_csr_dfi_p2_rddata <= litedramcore_master_p2_rddata;
- end
-end
-always @(*) begin
- litedramcore_csr_dfi_p2_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- end else begin
- litedramcore_csr_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
- end
-end
-always @(*) begin
- litedramcore_csr_dfi_p3_rddata <= 32'd0;
- if (litedramcore_sel) begin
- end else begin
- litedramcore_csr_dfi_p3_rddata <= litedramcore_master_p3_rddata;
- end
-end
-always @(*) begin
- litedramcore_csr_dfi_p3_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- end else begin
- litedramcore_csr_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
- end
-end
-always @(*) begin
- litedramcore_ext_dfi_p0_rddata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_ext_dfi_p0_rddata <= litedramcore_master_p0_rddata;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_ext_dfi_p0_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_ext_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_ext_dfi_p1_rddata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_ext_dfi_p1_rddata <= litedramcore_master_p1_rddata;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_ext_dfi_p1_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_ext_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_ext_dfi_p2_rddata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_ext_dfi_p2_rddata <= litedramcore_master_p2_rddata;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_ext_dfi_p2_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_ext_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_slave_p0_rddata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- end else begin
- litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata;
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_slave_p0_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- end else begin
- litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_ext_dfi_p3_rddata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_ext_dfi_p3_rddata <= litedramcore_master_p3_rddata;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_ext_dfi_p3_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_ext_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_slave_p1_rddata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- end else begin
- litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata;
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_slave_p1_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- end else begin
- litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_slave_p2_rddata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- end else begin
- litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata;
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_slave_p2_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- end else begin
- litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_slave_p3_rddata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- end else begin
- litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata;
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_slave_p3_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- end else begin
- litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_master_p0_address <= 15'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_address <= litedramcore_ext_dfi_p0_address;
- end else begin
- litedramcore_master_p0_address <= litedramcore_slave_p0_address;
- end
- end else begin
- litedramcore_master_p0_address <= litedramcore_csr_dfi_p0_address;
- end
-end
-always @(*) begin
- litedramcore_master_p0_bank <= 3'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_bank <= litedramcore_ext_dfi_p0_bank;
- end else begin
- litedramcore_master_p0_bank <= litedramcore_slave_p0_bank;
- end
- end else begin
- litedramcore_master_p0_bank <= litedramcore_csr_dfi_p0_bank;
- end
-end
-always @(*) begin
- litedramcore_master_p0_cas_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_cas_n <= litedramcore_ext_dfi_p0_cas_n;
- end else begin
- litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n;
- end
- end else begin
- litedramcore_master_p0_cas_n <= litedramcore_csr_dfi_p0_cas_n;
- end
-end
-always @(*) begin
- litedramcore_master_p0_cs_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n;
- end else begin
- litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n;
- end
- end else begin
- litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n;
- end
-end
-always @(*) begin
- litedramcore_master_p0_ras_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n;
- end else begin
- litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n;
- end
- end else begin
- litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n;
- end
-end
-always @(*) begin
- litedramcore_master_p0_we_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n;
- end else begin
- litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n;
- end
- end else begin
- litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n;
- end
-end
-always @(*) begin
- litedramcore_master_p0_cke <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_cke <= litedramcore_ext_dfi_p0_cke;
- end else begin
- litedramcore_master_p0_cke <= litedramcore_slave_p0_cke;
- end
- end else begin
- litedramcore_master_p0_cke <= litedramcore_csr_dfi_p0_cke;
- end
-end
-always @(*) begin
- litedramcore_master_p0_odt <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_odt <= litedramcore_ext_dfi_p0_odt;
- end else begin
- litedramcore_master_p0_odt <= litedramcore_slave_p0_odt;
- end
- end else begin
- litedramcore_master_p0_odt <= litedramcore_csr_dfi_p0_odt;
- end
-end
-always @(*) begin
- litedramcore_master_p0_reset_n <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_reset_n <= litedramcore_ext_dfi_p0_reset_n;
- end else begin
- litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n;
- end
- end else begin
- litedramcore_master_p0_reset_n <= litedramcore_csr_dfi_p0_reset_n;
- end
-end
-always @(*) begin
- litedramcore_master_p0_act_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_act_n <= litedramcore_ext_dfi_p0_act_n;
- end else begin
- litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n;
- end
- end else begin
- litedramcore_master_p0_act_n <= litedramcore_csr_dfi_p0_act_n;
- end
-end
-always @(*) begin
- litedramcore_master_p0_wrdata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_wrdata <= litedramcore_ext_dfi_p0_wrdata;
- end else begin
- litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata;
- end
- end else begin
- litedramcore_master_p0_wrdata <= litedramcore_csr_dfi_p0_wrdata;
- end
-end
-always @(*) begin
- litedramcore_master_p0_wrdata_en <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_wrdata_en <= litedramcore_ext_dfi_p0_wrdata_en;
- end else begin
- litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en;
- end
- end else begin
- litedramcore_master_p0_wrdata_en <= litedramcore_csr_dfi_p0_wrdata_en;
- end
-end
-always @(*) begin
- litedramcore_master_p0_wrdata_mask <= 4'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_wrdata_mask <= litedramcore_ext_dfi_p0_wrdata_mask;
- end else begin
- litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask;
- end
- end else begin
- litedramcore_master_p0_wrdata_mask <= litedramcore_csr_dfi_p0_wrdata_mask;
- end
-end
-always @(*) begin
- litedramcore_master_p0_rddata_en <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_rddata_en <= litedramcore_ext_dfi_p0_rddata_en;
- end else begin
- litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en;
- end
- end else begin
- litedramcore_master_p0_rddata_en <= litedramcore_csr_dfi_p0_rddata_en;
- end
-end
-always @(*) begin
- litedramcore_master_p1_address <= 15'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_address <= litedramcore_ext_dfi_p1_address;
- end else begin
- litedramcore_master_p1_address <= litedramcore_slave_p1_address;
- end
- end else begin
- litedramcore_master_p1_address <= litedramcore_csr_dfi_p1_address;
- end
-end
-always @(*) begin
- litedramcore_master_p1_bank <= 3'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_bank <= litedramcore_ext_dfi_p1_bank;
- end else begin
- litedramcore_master_p1_bank <= litedramcore_slave_p1_bank;
- end
- end else begin
- litedramcore_master_p1_bank <= litedramcore_csr_dfi_p1_bank;
- end
-end
-always @(*) begin
- litedramcore_master_p1_cas_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_cas_n <= litedramcore_ext_dfi_p1_cas_n;
- end else begin
- litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n;
- end
- end else begin
- litedramcore_master_p1_cas_n <= litedramcore_csr_dfi_p1_cas_n;
- end
-end
-always @(*) begin
- litedramcore_master_p1_cs_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_cs_n <= litedramcore_ext_dfi_p1_cs_n;
- end else begin
- litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n;
- end
- end else begin
- litedramcore_master_p1_cs_n <= litedramcore_csr_dfi_p1_cs_n;
- end
-end
-always @(*) begin
- litedramcore_master_p1_ras_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_ras_n <= litedramcore_ext_dfi_p1_ras_n;
- end else begin
- litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n;
- end
- end else begin
- litedramcore_master_p1_ras_n <= litedramcore_csr_dfi_p1_ras_n;
- end
-end
-always @(*) begin
- litedramcore_master_p1_we_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_we_n <= litedramcore_ext_dfi_p1_we_n;
- end else begin
- litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n;
- end
- end else begin
- litedramcore_master_p1_we_n <= litedramcore_csr_dfi_p1_we_n;
- end
-end
-always @(*) begin
- litedramcore_master_p1_cke <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_cke <= litedramcore_ext_dfi_p1_cke;
- end else begin
- litedramcore_master_p1_cke <= litedramcore_slave_p1_cke;
- end
- end else begin
- litedramcore_master_p1_cke <= litedramcore_csr_dfi_p1_cke;
- end
-end
-always @(*) begin
- litedramcore_master_p1_odt <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_odt <= litedramcore_ext_dfi_p1_odt;
- end else begin
- litedramcore_master_p1_odt <= litedramcore_slave_p1_odt;
- end
- end else begin
- litedramcore_master_p1_odt <= litedramcore_csr_dfi_p1_odt;
- end
-end
-always @(*) begin
- litedramcore_master_p1_reset_n <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_reset_n <= litedramcore_ext_dfi_p1_reset_n;
- end else begin
- litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n;
- end
- end else begin
- litedramcore_master_p1_reset_n <= litedramcore_csr_dfi_p1_reset_n;
- end
-end
-always @(*) begin
- litedramcore_master_p1_act_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_act_n <= litedramcore_ext_dfi_p1_act_n;
- end else begin
- litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n;
- end
- end else begin
- litedramcore_master_p1_act_n <= litedramcore_csr_dfi_p1_act_n;
- end
-end
-always @(*) begin
- litedramcore_master_p1_wrdata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_wrdata <= litedramcore_ext_dfi_p1_wrdata;
- end else begin
- litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata;
- end
- end else begin
- litedramcore_master_p1_wrdata <= litedramcore_csr_dfi_p1_wrdata;
- end
-end
-always @(*) begin
- litedramcore_master_p1_wrdata_en <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_wrdata_en <= litedramcore_ext_dfi_p1_wrdata_en;
- end else begin
- litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en;
- end
- end else begin
- litedramcore_master_p1_wrdata_en <= litedramcore_csr_dfi_p1_wrdata_en;
- end
-end
-always @(*) begin
- litedramcore_master_p1_wrdata_mask <= 4'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_wrdata_mask <= litedramcore_ext_dfi_p1_wrdata_mask;
- end else begin
- litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask;
- end
- end else begin
- litedramcore_master_p1_wrdata_mask <= litedramcore_csr_dfi_p1_wrdata_mask;
- end
-end
-always @(*) begin
- litedramcore_master_p1_rddata_en <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_rddata_en <= litedramcore_ext_dfi_p1_rddata_en;
- end else begin
- litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en;
- end
- end else begin
- litedramcore_master_p1_rddata_en <= litedramcore_csr_dfi_p1_rddata_en;
- end
-end
-always @(*) begin
- litedramcore_master_p2_address <= 15'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_address <= litedramcore_ext_dfi_p2_address;
- end else begin
- litedramcore_master_p2_address <= litedramcore_slave_p2_address;
- end
- end else begin
- litedramcore_master_p2_address <= litedramcore_csr_dfi_p2_address;
- end
-end
-always @(*) begin
- litedramcore_master_p2_bank <= 3'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_bank <= litedramcore_ext_dfi_p2_bank;
- end else begin
- litedramcore_master_p2_bank <= litedramcore_slave_p2_bank;
- end
- end else begin
- litedramcore_master_p2_bank <= litedramcore_csr_dfi_p2_bank;
- end
-end
-always @(*) begin
- litedramcore_master_p2_cas_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_cas_n <= litedramcore_ext_dfi_p2_cas_n;
- end else begin
- litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n;
- end
- end else begin
- litedramcore_master_p2_cas_n <= litedramcore_csr_dfi_p2_cas_n;
- end
-end
-always @(*) begin
- litedramcore_master_p2_cs_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_cs_n <= litedramcore_ext_dfi_p2_cs_n;
- end else begin
- litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n;
- end
- end else begin
- litedramcore_master_p2_cs_n <= litedramcore_csr_dfi_p2_cs_n;
- end
-end
-always @(*) begin
- litedramcore_master_p2_ras_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_ras_n <= litedramcore_ext_dfi_p2_ras_n;
- end else begin
- litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n;
- end
- end else begin
- litedramcore_master_p2_ras_n <= litedramcore_csr_dfi_p2_ras_n;
- end
-end
-always @(*) begin
- litedramcore_master_p2_we_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_we_n <= litedramcore_ext_dfi_p2_we_n;
- end else begin
- litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n;
- end
- end else begin
- litedramcore_master_p2_we_n <= litedramcore_csr_dfi_p2_we_n;
- end
-end
-always @(*) begin
- litedramcore_master_p2_cke <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_cke <= litedramcore_ext_dfi_p2_cke;
- end else begin
- litedramcore_master_p2_cke <= litedramcore_slave_p2_cke;
- end
- end else begin
- litedramcore_master_p2_cke <= litedramcore_csr_dfi_p2_cke;
- end
-end
-always @(*) begin
- litedramcore_master_p2_odt <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_odt <= litedramcore_ext_dfi_p2_odt;
- end else begin
- litedramcore_master_p2_odt <= litedramcore_slave_p2_odt;
- end
- end else begin
- litedramcore_master_p2_odt <= litedramcore_csr_dfi_p2_odt;
- end
-end
-always @(*) begin
- litedramcore_master_p2_reset_n <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_reset_n <= litedramcore_ext_dfi_p2_reset_n;
- end else begin
- litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n;
- end
- end else begin
- litedramcore_master_p2_reset_n <= litedramcore_csr_dfi_p2_reset_n;
- end
-end
-always @(*) begin
- litedramcore_master_p2_act_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_act_n <= litedramcore_ext_dfi_p2_act_n;
- end else begin
- litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n;
- end
- end else begin
- litedramcore_master_p2_act_n <= litedramcore_csr_dfi_p2_act_n;
- end
-end
-always @(*) begin
- litedramcore_master_p2_wrdata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_wrdata <= litedramcore_ext_dfi_p2_wrdata;
- end else begin
- litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata;
- end
- end else begin
- litedramcore_master_p2_wrdata <= litedramcore_csr_dfi_p2_wrdata;
- end
-end
-always @(*) begin
- litedramcore_master_p2_wrdata_en <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_wrdata_en <= litedramcore_ext_dfi_p2_wrdata_en;
- end else begin
- litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en;
- end
- end else begin
- litedramcore_master_p2_wrdata_en <= litedramcore_csr_dfi_p2_wrdata_en;
- end
-end
-always @(*) begin
- litedramcore_master_p2_wrdata_mask <= 4'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_wrdata_mask <= litedramcore_ext_dfi_p2_wrdata_mask;
- end else begin
- litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask;
- end
- end else begin
- litedramcore_master_p2_wrdata_mask <= litedramcore_csr_dfi_p2_wrdata_mask;
- end
-end
-always @(*) begin
- litedramcore_master_p2_rddata_en <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_rddata_en <= litedramcore_ext_dfi_p2_rddata_en;
- end else begin
- litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en;
- end
- end else begin
- litedramcore_master_p2_rddata_en <= litedramcore_csr_dfi_p2_rddata_en;
- end
-end
-always @(*) begin
- litedramcore_master_p3_address <= 15'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_address <= litedramcore_ext_dfi_p3_address;
- end else begin
- litedramcore_master_p3_address <= litedramcore_slave_p3_address;
- end
- end else begin
- litedramcore_master_p3_address <= litedramcore_csr_dfi_p3_address;
- end
-end
-always @(*) begin
- litedramcore_master_p3_bank <= 3'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_bank <= litedramcore_ext_dfi_p3_bank;
- end else begin
- litedramcore_master_p3_bank <= litedramcore_slave_p3_bank;
- end
- end else begin
- litedramcore_master_p3_bank <= litedramcore_csr_dfi_p3_bank;
- end
-end
-always @(*) begin
- litedramcore_master_p3_cas_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_cas_n <= litedramcore_ext_dfi_p3_cas_n;
- end else begin
- litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n;
- end
- end else begin
- litedramcore_master_p3_cas_n <= litedramcore_csr_dfi_p3_cas_n;
- end
-end
-always @(*) begin
- litedramcore_master_p3_cs_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_cs_n <= litedramcore_ext_dfi_p3_cs_n;
- end else begin
- litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n;
- end
- end else begin
- litedramcore_master_p3_cs_n <= litedramcore_csr_dfi_p3_cs_n;
- end
-end
-always @(*) begin
- litedramcore_master_p3_ras_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_ras_n <= litedramcore_ext_dfi_p3_ras_n;
- end else begin
- litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n;
- end
- end else begin
- litedramcore_master_p3_ras_n <= litedramcore_csr_dfi_p3_ras_n;
- end
-end
-always @(*) begin
- litedramcore_master_p3_we_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_we_n <= litedramcore_ext_dfi_p3_we_n;
- end else begin
- litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n;
- end
- end else begin
- litedramcore_master_p3_we_n <= litedramcore_csr_dfi_p3_we_n;
- end
-end
-always @(*) begin
- litedramcore_master_p3_cke <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_cke <= litedramcore_ext_dfi_p3_cke;
- end else begin
- litedramcore_master_p3_cke <= litedramcore_slave_p3_cke;
- end
- end else begin
- litedramcore_master_p3_cke <= litedramcore_csr_dfi_p3_cke;
- end
-end
-always @(*) begin
- litedramcore_master_p3_odt <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_odt <= litedramcore_ext_dfi_p3_odt;
- end else begin
- litedramcore_master_p3_odt <= litedramcore_slave_p3_odt;
- end
- end else begin
- litedramcore_master_p3_odt <= litedramcore_csr_dfi_p3_odt;
- end
-end
-always @(*) begin
- litedramcore_master_p3_reset_n <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_reset_n <= litedramcore_ext_dfi_p3_reset_n;
- end else begin
- litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n;
- end
- end else begin
- litedramcore_master_p3_reset_n <= litedramcore_csr_dfi_p3_reset_n;
- end
-end
-always @(*) begin
- litedramcore_master_p3_act_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_act_n <= litedramcore_ext_dfi_p3_act_n;
- end else begin
- litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n;
- end
- end else begin
- litedramcore_master_p3_act_n <= litedramcore_csr_dfi_p3_act_n;
- end
-end
-always @(*) begin
- litedramcore_master_p3_wrdata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_wrdata <= litedramcore_ext_dfi_p3_wrdata;
- end else begin
- litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata;
- end
- end else begin
- litedramcore_master_p3_wrdata <= litedramcore_csr_dfi_p3_wrdata;
- end
-end
-always @(*) begin
- litedramcore_master_p3_wrdata_en <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_wrdata_en <= litedramcore_ext_dfi_p3_wrdata_en;
- end else begin
- litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en;
- end
- end else begin
- litedramcore_master_p3_wrdata_en <= litedramcore_csr_dfi_p3_wrdata_en;
- end
-end
-always @(*) begin
- litedramcore_master_p3_wrdata_mask <= 4'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_wrdata_mask <= litedramcore_ext_dfi_p3_wrdata_mask;
- end else begin
- litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask;
- end
- end else begin
- litedramcore_master_p3_wrdata_mask <= litedramcore_csr_dfi_p3_wrdata_mask;
- end
-end
-always @(*) begin
- litedramcore_master_p3_rddata_en <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_rddata_en <= litedramcore_ext_dfi_p3_rddata_en;
- end else begin
- litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en;
- end
- end else begin
- litedramcore_master_p3_rddata_en <= litedramcore_csr_dfi_p3_rddata_en;
- end
+ litedramcore_csr_dfi_p0_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_csr_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+ end
+end
+always @(*) begin
+ litedramcore_csr_dfi_p1_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata;
+ end
+end
+always @(*) begin
+ litedramcore_csr_dfi_p1_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+ end
+end
+always @(*) begin
+ litedramcore_csr_dfi_p2_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_csr_dfi_p2_rddata <= litedramcore_master_p2_rddata;
+ end
+end
+always @(*) begin
+ litedramcore_csr_dfi_p2_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_csr_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+ end
+end
+always @(*) begin
+ litedramcore_csr_dfi_p3_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_csr_dfi_p3_rddata <= litedramcore_master_p3_rddata;
+ end
+end
+always @(*) begin
+ litedramcore_csr_dfi_p3_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_csr_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+ end
+end
+always @(*) begin
+ litedramcore_ext_dfi_p0_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_ext_dfi_p0_rddata <= litedramcore_master_p0_rddata;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_ext_dfi_p0_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_ext_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_ext_dfi_p1_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_ext_dfi_p1_rddata <= litedramcore_master_p1_rddata;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_ext_dfi_p1_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_ext_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_ext_dfi_p2_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_ext_dfi_p2_rddata <= litedramcore_master_p2_rddata;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_ext_dfi_p2_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_ext_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p0_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ end else begin
+ litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p0_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ end else begin
+ litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_ext_dfi_p3_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_ext_dfi_p3_rddata <= litedramcore_master_p3_rddata;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_ext_dfi_p3_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_ext_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p1_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ end else begin
+ litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p1_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ end else begin
+ litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p2_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ end else begin
+ litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p2_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ end else begin
+ litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p3_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ end else begin
+ litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p3_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ end else begin
+ litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_address <= 15'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_address <= litedramcore_ext_dfi_p0_address;
+ end else begin
+ litedramcore_master_p0_address <= litedramcore_slave_p0_address;
+ end
+ end else begin
+ litedramcore_master_p0_address <= litedramcore_csr_dfi_p0_address;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_bank <= 3'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_bank <= litedramcore_ext_dfi_p0_bank;
+ end else begin
+ litedramcore_master_p0_bank <= litedramcore_slave_p0_bank;
+ end
+ end else begin
+ litedramcore_master_p0_bank <= litedramcore_csr_dfi_p0_bank;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_cas_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_cas_n <= litedramcore_ext_dfi_p0_cas_n;
+ end else begin
+ litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n;
+ end
+ end else begin
+ litedramcore_master_p0_cas_n <= litedramcore_csr_dfi_p0_cas_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_cs_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n;
+ end else begin
+ litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n;
+ end
+ end else begin
+ litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_ras_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n;
+ end else begin
+ litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n;
+ end
+ end else begin
+ litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_we_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n;
+ end else begin
+ litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n;
+ end
+ end else begin
+ litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_cke <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_cke <= litedramcore_ext_dfi_p0_cke;
+ end else begin
+ litedramcore_master_p0_cke <= litedramcore_slave_p0_cke;
+ end
+ end else begin
+ litedramcore_master_p0_cke <= litedramcore_csr_dfi_p0_cke;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_odt <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_odt <= litedramcore_ext_dfi_p0_odt;
+ end else begin
+ litedramcore_master_p0_odt <= litedramcore_slave_p0_odt;
+ end
+ end else begin
+ litedramcore_master_p0_odt <= litedramcore_csr_dfi_p0_odt;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_reset_n <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_reset_n <= litedramcore_ext_dfi_p0_reset_n;
+ end else begin
+ litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n;
+ end
+ end else begin
+ litedramcore_master_p0_reset_n <= litedramcore_csr_dfi_p0_reset_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_act_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_act_n <= litedramcore_ext_dfi_p0_act_n;
+ end else begin
+ litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n;
+ end
+ end else begin
+ litedramcore_master_p0_act_n <= litedramcore_csr_dfi_p0_act_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_wrdata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_wrdata <= litedramcore_ext_dfi_p0_wrdata;
+ end else begin
+ litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata;
+ end
+ end else begin
+ litedramcore_master_p0_wrdata <= litedramcore_csr_dfi_p0_wrdata;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_wrdata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_wrdata_en <= litedramcore_ext_dfi_p0_wrdata_en;
+ end else begin
+ litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en;
+ end
+ end else begin
+ litedramcore_master_p0_wrdata_en <= litedramcore_csr_dfi_p0_wrdata_en;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_wrdata_mask <= 4'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_wrdata_mask <= litedramcore_ext_dfi_p0_wrdata_mask;
+ end else begin
+ litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask;
+ end
+ end else begin
+ litedramcore_master_p0_wrdata_mask <= litedramcore_csr_dfi_p0_wrdata_mask;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_rddata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_rddata_en <= litedramcore_ext_dfi_p0_rddata_en;
+ end else begin
+ litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en;
+ end
+ end else begin
+ litedramcore_master_p0_rddata_en <= litedramcore_csr_dfi_p0_rddata_en;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_address <= 15'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_address <= litedramcore_ext_dfi_p1_address;
+ end else begin
+ litedramcore_master_p1_address <= litedramcore_slave_p1_address;
+ end
+ end else begin
+ litedramcore_master_p1_address <= litedramcore_csr_dfi_p1_address;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_bank <= 3'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_bank <= litedramcore_ext_dfi_p1_bank;
+ end else begin
+ litedramcore_master_p1_bank <= litedramcore_slave_p1_bank;
+ end
+ end else begin
+ litedramcore_master_p1_bank <= litedramcore_csr_dfi_p1_bank;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_cas_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_cas_n <= litedramcore_ext_dfi_p1_cas_n;
+ end else begin
+ litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n;
+ end
+ end else begin
+ litedramcore_master_p1_cas_n <= litedramcore_csr_dfi_p1_cas_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_cs_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_cs_n <= litedramcore_ext_dfi_p1_cs_n;
+ end else begin
+ litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n;
+ end
+ end else begin
+ litedramcore_master_p1_cs_n <= litedramcore_csr_dfi_p1_cs_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_ras_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_ras_n <= litedramcore_ext_dfi_p1_ras_n;
+ end else begin
+ litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n;
+ end
+ end else begin
+ litedramcore_master_p1_ras_n <= litedramcore_csr_dfi_p1_ras_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_we_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_we_n <= litedramcore_ext_dfi_p1_we_n;
+ end else begin
+ litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n;
+ end
+ end else begin
+ litedramcore_master_p1_we_n <= litedramcore_csr_dfi_p1_we_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_cke <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_cke <= litedramcore_ext_dfi_p1_cke;
+ end else begin
+ litedramcore_master_p1_cke <= litedramcore_slave_p1_cke;
+ end
+ end else begin
+ litedramcore_master_p1_cke <= litedramcore_csr_dfi_p1_cke;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_odt <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_odt <= litedramcore_ext_dfi_p1_odt;
+ end else begin
+ litedramcore_master_p1_odt <= litedramcore_slave_p1_odt;
+ end
+ end else begin
+ litedramcore_master_p1_odt <= litedramcore_csr_dfi_p1_odt;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_reset_n <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_reset_n <= litedramcore_ext_dfi_p1_reset_n;
+ end else begin
+ litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n;
+ end
+ end else begin
+ litedramcore_master_p1_reset_n <= litedramcore_csr_dfi_p1_reset_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_act_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_act_n <= litedramcore_ext_dfi_p1_act_n;
+ end else begin
+ litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n;
+ end
+ end else begin
+ litedramcore_master_p1_act_n <= litedramcore_csr_dfi_p1_act_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_wrdata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_wrdata <= litedramcore_ext_dfi_p1_wrdata;
+ end else begin
+ litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata;
+ end
+ end else begin
+ litedramcore_master_p1_wrdata <= litedramcore_csr_dfi_p1_wrdata;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_wrdata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_wrdata_en <= litedramcore_ext_dfi_p1_wrdata_en;
+ end else begin
+ litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en;
+ end
+ end else begin
+ litedramcore_master_p1_wrdata_en <= litedramcore_csr_dfi_p1_wrdata_en;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_wrdata_mask <= 4'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_wrdata_mask <= litedramcore_ext_dfi_p1_wrdata_mask;
+ end else begin
+ litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask;
+ end
+ end else begin
+ litedramcore_master_p1_wrdata_mask <= litedramcore_csr_dfi_p1_wrdata_mask;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_rddata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_rddata_en <= litedramcore_ext_dfi_p1_rddata_en;
+ end else begin
+ litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en;
+ end
+ end else begin
+ litedramcore_master_p1_rddata_en <= litedramcore_csr_dfi_p1_rddata_en;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_address <= 15'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_address <= litedramcore_ext_dfi_p2_address;
+ end else begin
+ litedramcore_master_p2_address <= litedramcore_slave_p2_address;
+ end
+ end else begin
+ litedramcore_master_p2_address <= litedramcore_csr_dfi_p2_address;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_bank <= 3'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_bank <= litedramcore_ext_dfi_p2_bank;
+ end else begin
+ litedramcore_master_p2_bank <= litedramcore_slave_p2_bank;
+ end
+ end else begin
+ litedramcore_master_p2_bank <= litedramcore_csr_dfi_p2_bank;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_cas_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_cas_n <= litedramcore_ext_dfi_p2_cas_n;
+ end else begin
+ litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n;
+ end
+ end else begin
+ litedramcore_master_p2_cas_n <= litedramcore_csr_dfi_p2_cas_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_cs_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_cs_n <= litedramcore_ext_dfi_p2_cs_n;
+ end else begin
+ litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n;
+ end
+ end else begin
+ litedramcore_master_p2_cs_n <= litedramcore_csr_dfi_p2_cs_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_ras_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_ras_n <= litedramcore_ext_dfi_p2_ras_n;
+ end else begin
+ litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n;
+ end
+ end else begin
+ litedramcore_master_p2_ras_n <= litedramcore_csr_dfi_p2_ras_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_we_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_we_n <= litedramcore_ext_dfi_p2_we_n;
+ end else begin
+ litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n;
+ end
+ end else begin
+ litedramcore_master_p2_we_n <= litedramcore_csr_dfi_p2_we_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_cke <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_cke <= litedramcore_ext_dfi_p2_cke;
+ end else begin
+ litedramcore_master_p2_cke <= litedramcore_slave_p2_cke;
+ end
+ end else begin
+ litedramcore_master_p2_cke <= litedramcore_csr_dfi_p2_cke;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_odt <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_odt <= litedramcore_ext_dfi_p2_odt;
+ end else begin
+ litedramcore_master_p2_odt <= litedramcore_slave_p2_odt;
+ end
+ end else begin
+ litedramcore_master_p2_odt <= litedramcore_csr_dfi_p2_odt;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_reset_n <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_reset_n <= litedramcore_ext_dfi_p2_reset_n;
+ end else begin
+ litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n;
+ end
+ end else begin
+ litedramcore_master_p2_reset_n <= litedramcore_csr_dfi_p2_reset_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_act_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_act_n <= litedramcore_ext_dfi_p2_act_n;
+ end else begin
+ litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n;
+ end
+ end else begin
+ litedramcore_master_p2_act_n <= litedramcore_csr_dfi_p2_act_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_wrdata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_wrdata <= litedramcore_ext_dfi_p2_wrdata;
+ end else begin
+ litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata;
+ end
+ end else begin
+ litedramcore_master_p2_wrdata <= litedramcore_csr_dfi_p2_wrdata;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_wrdata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_wrdata_en <= litedramcore_ext_dfi_p2_wrdata_en;
+ end else begin
+ litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en;
+ end
+ end else begin
+ litedramcore_master_p2_wrdata_en <= litedramcore_csr_dfi_p2_wrdata_en;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_wrdata_mask <= 4'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_wrdata_mask <= litedramcore_ext_dfi_p2_wrdata_mask;
+ end else begin
+ litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask;
+ end
+ end else begin
+ litedramcore_master_p2_wrdata_mask <= litedramcore_csr_dfi_p2_wrdata_mask;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_rddata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_rddata_en <= litedramcore_ext_dfi_p2_rddata_en;
+ end else begin
+ litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en;
+ end
+ end else begin
+ litedramcore_master_p2_rddata_en <= litedramcore_csr_dfi_p2_rddata_en;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_address <= 15'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_address <= litedramcore_ext_dfi_p3_address;
+ end else begin
+ litedramcore_master_p3_address <= litedramcore_slave_p3_address;
+ end
+ end else begin
+ litedramcore_master_p3_address <= litedramcore_csr_dfi_p3_address;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_bank <= 3'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_bank <= litedramcore_ext_dfi_p3_bank;
+ end else begin
+ litedramcore_master_p3_bank <= litedramcore_slave_p3_bank;
+ end
+ end else begin
+ litedramcore_master_p3_bank <= litedramcore_csr_dfi_p3_bank;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_cas_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_cas_n <= litedramcore_ext_dfi_p3_cas_n;
+ end else begin
+ litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n;
+ end
+ end else begin
+ litedramcore_master_p3_cas_n <= litedramcore_csr_dfi_p3_cas_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_cs_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_cs_n <= litedramcore_ext_dfi_p3_cs_n;
+ end else begin
+ litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n;
+ end
+ end else begin
+ litedramcore_master_p3_cs_n <= litedramcore_csr_dfi_p3_cs_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_ras_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_ras_n <= litedramcore_ext_dfi_p3_ras_n;
+ end else begin
+ litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n;
+ end
+ end else begin
+ litedramcore_master_p3_ras_n <= litedramcore_csr_dfi_p3_ras_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_we_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_we_n <= litedramcore_ext_dfi_p3_we_n;
+ end else begin
+ litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n;
+ end
+ end else begin
+ litedramcore_master_p3_we_n <= litedramcore_csr_dfi_p3_we_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_cke <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_cke <= litedramcore_ext_dfi_p3_cke;
+ end else begin
+ litedramcore_master_p3_cke <= litedramcore_slave_p3_cke;
+ end
+ end else begin
+ litedramcore_master_p3_cke <= litedramcore_csr_dfi_p3_cke;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_odt <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_odt <= litedramcore_ext_dfi_p3_odt;
+ end else begin
+ litedramcore_master_p3_odt <= litedramcore_slave_p3_odt;
+ end
+ end else begin
+ litedramcore_master_p3_odt <= litedramcore_csr_dfi_p3_odt;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_reset_n <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_reset_n <= litedramcore_ext_dfi_p3_reset_n;
+ end else begin
+ litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n;
+ end
+ end else begin
+ litedramcore_master_p3_reset_n <= litedramcore_csr_dfi_p3_reset_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_act_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_act_n <= litedramcore_ext_dfi_p3_act_n;
+ end else begin
+ litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n;
+ end
+ end else begin
+ litedramcore_master_p3_act_n <= litedramcore_csr_dfi_p3_act_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_wrdata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_wrdata <= litedramcore_ext_dfi_p3_wrdata;
+ end else begin
+ litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata;
+ end
+ end else begin
+ litedramcore_master_p3_wrdata <= litedramcore_csr_dfi_p3_wrdata;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_wrdata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_wrdata_en <= litedramcore_ext_dfi_p3_wrdata_en;
+ end else begin
+ litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en;
+ end
+ end else begin
+ litedramcore_master_p3_wrdata_en <= litedramcore_csr_dfi_p3_wrdata_en;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_wrdata_mask <= 4'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_wrdata_mask <= litedramcore_ext_dfi_p3_wrdata_mask;
+ end else begin
+ litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask;
+ end
+ end else begin
+ litedramcore_master_p3_wrdata_mask <= litedramcore_csr_dfi_p3_wrdata_mask;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_rddata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_rddata_en <= litedramcore_ext_dfi_p3_rddata_en;
+ end else begin
+ litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en;
+ end
+ end else begin
+ litedramcore_master_p3_rddata_en <= litedramcore_csr_dfi_p3_rddata_en;
+ end
end
assign litedramcore_csr_dfi_p0_cke = litedramcore_cke;
assign litedramcore_csr_dfi_p1_cke = litedramcore_cke;
assign litedramcore_csr_dfi_p2_reset_n = litedramcore_reset_n;
assign litedramcore_csr_dfi_p3_reset_n = litedramcore_reset_n;
always @(*) begin
- litedramcore_csr_dfi_p0_ras_n <= 1'd1;
- if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_csr_dfi_p0_ras_n <= (~litedramcore_phaseinjector0_csrfield_ras);
- end else begin
- litedramcore_csr_dfi_p0_ras_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p0_ras_n <= 1'd1;
+ if (litedramcore_phaseinjector0_command_issue_re) begin
+ litedramcore_csr_dfi_p0_ras_n <= (~litedramcore_phaseinjector0_csrfield_ras);
+ end else begin
+ litedramcore_csr_dfi_p0_ras_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p0_we_n <= 1'd1;
- if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we);
- end else begin
- litedramcore_csr_dfi_p0_we_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p0_we_n <= 1'd1;
+ if (litedramcore_phaseinjector0_command_issue_re) begin
+ litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we);
+ end else begin
+ litedramcore_csr_dfi_p0_we_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p0_cas_n <= 1'd1;
- if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_csr_dfi_p0_cas_n <= (~litedramcore_phaseinjector0_csrfield_cas);
- end else begin
- litedramcore_csr_dfi_p0_cas_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p0_cas_n <= 1'd1;
+ if (litedramcore_phaseinjector0_command_issue_re) begin
+ litedramcore_csr_dfi_p0_cas_n <= (~litedramcore_phaseinjector0_csrfield_cas);
+ end else begin
+ litedramcore_csr_dfi_p0_cas_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p0_cs_n <= 1'd1;
- if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}};
- end else begin
- litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}};
- end
+ litedramcore_csr_dfi_p0_cs_n <= 1'd1;
+ if (litedramcore_phaseinjector0_command_issue_re) begin
+ litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}};
+ end else begin
+ litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}};
+ end
end
assign litedramcore_csr_dfi_p0_address = litedramcore_phaseinjector0_address_storage;
assign litedramcore_csr_dfi_p0_bank = litedramcore_phaseinjector0_baddress_storage;
assign litedramcore_csr_dfi_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage;
assign litedramcore_csr_dfi_p0_wrdata_mask = 1'd0;
always @(*) begin
- litedramcore_csr_dfi_p1_ras_n <= 1'd1;
- if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_csr_dfi_p1_ras_n <= (~litedramcore_phaseinjector1_csrfield_ras);
- end else begin
- litedramcore_csr_dfi_p1_ras_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p1_ras_n <= 1'd1;
+ if (litedramcore_phaseinjector1_command_issue_re) begin
+ litedramcore_csr_dfi_p1_ras_n <= (~litedramcore_phaseinjector1_csrfield_ras);
+ end else begin
+ litedramcore_csr_dfi_p1_ras_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p1_we_n <= 1'd1;
- if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we);
- end else begin
- litedramcore_csr_dfi_p1_we_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p1_we_n <= 1'd1;
+ if (litedramcore_phaseinjector1_command_issue_re) begin
+ litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we);
+ end else begin
+ litedramcore_csr_dfi_p1_we_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p1_cas_n <= 1'd1;
- if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_csr_dfi_p1_cas_n <= (~litedramcore_phaseinjector1_csrfield_cas);
- end else begin
- litedramcore_csr_dfi_p1_cas_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p1_cas_n <= 1'd1;
+ if (litedramcore_phaseinjector1_command_issue_re) begin
+ litedramcore_csr_dfi_p1_cas_n <= (~litedramcore_phaseinjector1_csrfield_cas);
+ end else begin
+ litedramcore_csr_dfi_p1_cas_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p1_cs_n <= 1'd1;
- if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}};
- end else begin
- litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}};
- end
+ litedramcore_csr_dfi_p1_cs_n <= 1'd1;
+ if (litedramcore_phaseinjector1_command_issue_re) begin
+ litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}};
+ end else begin
+ litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}};
+ end
end
assign litedramcore_csr_dfi_p1_address = litedramcore_phaseinjector1_address_storage;
assign litedramcore_csr_dfi_p1_bank = litedramcore_phaseinjector1_baddress_storage;
assign litedramcore_csr_dfi_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage;
assign litedramcore_csr_dfi_p1_wrdata_mask = 1'd0;
always @(*) begin
- litedramcore_csr_dfi_p2_ras_n <= 1'd1;
- if (litedramcore_phaseinjector2_command_issue_re) begin
- litedramcore_csr_dfi_p2_ras_n <= (~litedramcore_phaseinjector2_csrfield_ras);
- end else begin
- litedramcore_csr_dfi_p2_ras_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p2_ras_n <= 1'd1;
+ if (litedramcore_phaseinjector2_command_issue_re) begin
+ litedramcore_csr_dfi_p2_ras_n <= (~litedramcore_phaseinjector2_csrfield_ras);
+ end else begin
+ litedramcore_csr_dfi_p2_ras_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p2_we_n <= 1'd1;
- if (litedramcore_phaseinjector2_command_issue_re) begin
- litedramcore_csr_dfi_p2_we_n <= (~litedramcore_phaseinjector2_csrfield_we);
- end else begin
- litedramcore_csr_dfi_p2_we_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p2_we_n <= 1'd1;
+ if (litedramcore_phaseinjector2_command_issue_re) begin
+ litedramcore_csr_dfi_p2_we_n <= (~litedramcore_phaseinjector2_csrfield_we);
+ end else begin
+ litedramcore_csr_dfi_p2_we_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p2_cas_n <= 1'd1;
- if (litedramcore_phaseinjector2_command_issue_re) begin
- litedramcore_csr_dfi_p2_cas_n <= (~litedramcore_phaseinjector2_csrfield_cas);
- end else begin
- litedramcore_csr_dfi_p2_cas_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p2_cas_n <= 1'd1;
+ if (litedramcore_phaseinjector2_command_issue_re) begin
+ litedramcore_csr_dfi_p2_cas_n <= (~litedramcore_phaseinjector2_csrfield_cas);
+ end else begin
+ litedramcore_csr_dfi_p2_cas_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p2_cs_n <= 1'd1;
- if (litedramcore_phaseinjector2_command_issue_re) begin
- litedramcore_csr_dfi_p2_cs_n <= {1{(~litedramcore_phaseinjector2_csrfield_cs)}};
- end else begin
- litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}};
- end
+ litedramcore_csr_dfi_p2_cs_n <= 1'd1;
+ if (litedramcore_phaseinjector2_command_issue_re) begin
+ litedramcore_csr_dfi_p2_cs_n <= {1{(~litedramcore_phaseinjector2_csrfield_cs)}};
+ end else begin
+ litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}};
+ end
end
assign litedramcore_csr_dfi_p2_address = litedramcore_phaseinjector2_address_storage;
assign litedramcore_csr_dfi_p2_bank = litedramcore_phaseinjector2_baddress_storage;
assign litedramcore_csr_dfi_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage;
assign litedramcore_csr_dfi_p2_wrdata_mask = 1'd0;
always @(*) begin
- litedramcore_csr_dfi_p3_ras_n <= 1'd1;
- if (litedramcore_phaseinjector3_command_issue_re) begin
- litedramcore_csr_dfi_p3_ras_n <= (~litedramcore_phaseinjector3_csrfield_ras);
- end else begin
- litedramcore_csr_dfi_p3_ras_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p3_ras_n <= 1'd1;
+ if (litedramcore_phaseinjector3_command_issue_re) begin
+ litedramcore_csr_dfi_p3_ras_n <= (~litedramcore_phaseinjector3_csrfield_ras);
+ end else begin
+ litedramcore_csr_dfi_p3_ras_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p3_we_n <= 1'd1;
- if (litedramcore_phaseinjector3_command_issue_re) begin
- litedramcore_csr_dfi_p3_we_n <= (~litedramcore_phaseinjector3_csrfield_we);
- end else begin
- litedramcore_csr_dfi_p3_we_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p3_we_n <= 1'd1;
+ if (litedramcore_phaseinjector3_command_issue_re) begin
+ litedramcore_csr_dfi_p3_we_n <= (~litedramcore_phaseinjector3_csrfield_we);
+ end else begin
+ litedramcore_csr_dfi_p3_we_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p3_cas_n <= 1'd1;
- if (litedramcore_phaseinjector3_command_issue_re) begin
- litedramcore_csr_dfi_p3_cas_n <= (~litedramcore_phaseinjector3_csrfield_cas);
- end else begin
- litedramcore_csr_dfi_p3_cas_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p3_cas_n <= 1'd1;
+ if (litedramcore_phaseinjector3_command_issue_re) begin
+ litedramcore_csr_dfi_p3_cas_n <= (~litedramcore_phaseinjector3_csrfield_cas);
+ end else begin
+ litedramcore_csr_dfi_p3_cas_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p3_cs_n <= 1'd1;
- if (litedramcore_phaseinjector3_command_issue_re) begin
- litedramcore_csr_dfi_p3_cs_n <= {1{(~litedramcore_phaseinjector3_csrfield_cs)}};
- end else begin
- litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}};
- end
+ litedramcore_csr_dfi_p3_cs_n <= 1'd1;
+ if (litedramcore_phaseinjector3_command_issue_re) begin
+ litedramcore_csr_dfi_p3_cs_n <= {1{(~litedramcore_phaseinjector3_csrfield_cs)}};
+ end else begin
+ litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}};
+ end
end
assign litedramcore_csr_dfi_p3_address = litedramcore_phaseinjector3_address_storage;
assign litedramcore_csr_dfi_p3_bank = litedramcore_phaseinjector3_baddress_storage;
assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1;
assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1;
always @(*) begin
- litedramcore_refresher_next_state <= 2'd0;
- litedramcore_refresher_next_state <= litedramcore_refresher_state;
- case (litedramcore_refresher_state)
- 1'd1: begin
- if (litedramcore_cmd_ready) begin
- litedramcore_refresher_next_state <= 2'd2;
- end
- end
- 2'd2: begin
- if (litedramcore_sequencer_done0) begin
- if (litedramcore_wants_zqcs) begin
- litedramcore_refresher_next_state <= 2'd3;
- end else begin
- litedramcore_refresher_next_state <= 1'd0;
- end
- end
- end
- 2'd3: begin
- if (litedramcore_zqcs_executer_done) begin
- litedramcore_refresher_next_state <= 1'd0;
- end
- end
- default: begin
- if (1'd1) begin
- if (litedramcore_wants_refresh) begin
- litedramcore_refresher_next_state <= 1'd1;
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_sequencer_start0 <= 1'd0;
- case (litedramcore_refresher_state)
- 1'd1: begin
- if (litedramcore_cmd_ready) begin
- litedramcore_sequencer_start0 <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_cmd_valid <= 1'd0;
- case (litedramcore_refresher_state)
- 1'd1: begin
- litedramcore_cmd_valid <= 1'd1;
- end
- 2'd2: begin
- litedramcore_cmd_valid <= 1'd1;
- if (litedramcore_sequencer_done0) begin
- if (litedramcore_wants_zqcs) begin
- end else begin
- litedramcore_cmd_valid <= 1'd0;
- end
- end
- end
- 2'd3: begin
- litedramcore_cmd_valid <= 1'd1;
- if (litedramcore_zqcs_executer_done) begin
- litedramcore_cmd_valid <= 1'd0;
- end
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_zqcs_executer_start <= 1'd0;
- case (litedramcore_refresher_state)
- 1'd1: begin
- end
- 2'd2: begin
- if (litedramcore_sequencer_done0) begin
- if (litedramcore_wants_zqcs) begin
- litedramcore_zqcs_executer_start <= 1'd1;
- end else begin
- end
- end
- end
- 2'd3: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_cmd_last <= 1'd0;
- case (litedramcore_refresher_state)
- 1'd1: begin
- end
- 2'd2: begin
- if (litedramcore_sequencer_done0) begin
- if (litedramcore_wants_zqcs) begin
- end else begin
- litedramcore_cmd_last <= 1'd1;
- end
- end
- end
- 2'd3: begin
- if (litedramcore_zqcs_executer_done) begin
- litedramcore_cmd_last <= 1'd1;
- end
- end
- default: begin
- end
- endcase
-end
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine0_req_valid;
-assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine0_req_we;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine0_req_addr;
-assign litedramcore_bankmachine0_cmd_buffer_sink_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine0_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine0_cmd_buffer_sink_first = litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine0_cmd_buffer_sink_last = litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine0_cmd_buffer_sink_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine0_cmd_buffer_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid);
-assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine0_cmd_buffer_source_valid);
-assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]);
+ litedramcore_refresher_next_state <= 2'd0;
+ litedramcore_refresher_next_state <= litedramcore_refresher_state;
+ case (litedramcore_refresher_state)
+ 1'd1: begin
+ if (litedramcore_cmd_ready) begin
+ litedramcore_refresher_next_state <= 2'd2;
+ end
+ end
+ 2'd2: begin
+ if (litedramcore_sequencer_done0) begin
+ if (litedramcore_wants_zqcs) begin
+ litedramcore_refresher_next_state <= 2'd3;
+ end else begin
+ litedramcore_refresher_next_state <= 1'd0;
+ end
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_zqcs_executer_done) begin
+ litedramcore_refresher_next_state <= 1'd0;
+ end
+ end
+ default: begin
+ if (1'd1) begin
+ if (litedramcore_wants_refresh) begin
+ litedramcore_refresher_next_state <= 1'd1;
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_sequencer_start0 <= 1'd0;
+ case (litedramcore_refresher_state)
+ 1'd1: begin
+ if (litedramcore_cmd_ready) begin
+ litedramcore_sequencer_start0 <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_cmd_valid <= 1'd0;
+ case (litedramcore_refresher_state)
+ 1'd1: begin
+ litedramcore_cmd_valid <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_cmd_valid <= 1'd1;
+ if (litedramcore_sequencer_done0) begin
+ if (litedramcore_wants_zqcs) begin
+ end else begin
+ litedramcore_cmd_valid <= 1'd0;
+ end
+ end
+ end
+ 2'd3: begin
+ litedramcore_cmd_valid <= 1'd1;
+ if (litedramcore_zqcs_executer_done) begin
+ litedramcore_cmd_valid <= 1'd0;
+ end
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_zqcs_executer_start <= 1'd0;
+ case (litedramcore_refresher_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ if (litedramcore_sequencer_done0) begin
+ if (litedramcore_wants_zqcs) begin
+ litedramcore_zqcs_executer_start <= 1'd1;
+ end else begin
+ end
+ end
+ end
+ 2'd3: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_cmd_last <= 1'd0;
+ case (litedramcore_refresher_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ if (litedramcore_sequencer_done0) begin
+ if (litedramcore_wants_zqcs) begin
+ end else begin
+ litedramcore_cmd_last <= 1'd1;
+ end
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_zqcs_executer_done) begin
+ litedramcore_cmd_last <= 1'd1;
+ end
+ end
+ default: begin
+ end
+ endcase
+end
+assign litedramcore_bankmachine0_sink_valid = litedramcore_bankmachine0_req_valid;
+assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_sink_ready;
+assign litedramcore_bankmachine0_sink_payload_we = litedramcore_bankmachine0_req_we;
+assign litedramcore_bankmachine0_sink_payload_addr = litedramcore_bankmachine0_req_addr;
+assign litedramcore_bankmachine0_sink_sink_valid = litedramcore_bankmachine0_source_valid;
+assign litedramcore_bankmachine0_source_ready = litedramcore_bankmachine0_sink_sink_ready;
+assign litedramcore_bankmachine0_sink_sink_first = litedramcore_bankmachine0_source_first;
+assign litedramcore_bankmachine0_sink_sink_last = litedramcore_bankmachine0_source_last;
+assign litedramcore_bankmachine0_sink_sink_payload_we = litedramcore_bankmachine0_source_payload_we;
+assign litedramcore_bankmachine0_sink_sink_payload_addr = litedramcore_bankmachine0_source_payload_addr;
+assign litedramcore_bankmachine0_source_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid);
+assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_source_valid | litedramcore_bankmachine0_source_source_valid);
+assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_source_source_payload_addr[21:7]);
assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
always @(*) begin
- litedramcore_bankmachine0_cmd_payload_a <= 15'd0;
- if (litedramcore_bankmachine0_row_col_n_addr_sel) begin
- litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7];
- end else begin
- litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine0_cmd_payload_a <= 15'd0;
+ if (litedramcore_bankmachine0_row_col_n_addr_sel) begin
+ litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_source_source_payload_addr[21:7];
+ end else begin
+ litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write);
assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
always @(*) begin
- litedramcore_bankmachine0_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine0_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7])) begin
- litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine0_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | litedramcore_bankmachine0_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re);
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine0_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine0_next_state <= 4'd0;
- litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- if (litedramcore_bankmachine0_cmd_ready) begin
- litedramcore_bankmachine0_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- if (litedramcore_bankmachine0_cmd_ready) begin
- litedramcore_bankmachine0_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine0_refresh_req)) begin
- litedramcore_bankmachine0_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine0_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine0_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine0_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine0_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- litedramcore_bankmachine0_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin
- litedramcore_bankmachine0_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine0_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine0_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_row_open <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_row_close <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- litedramcore_bankmachine0_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine0_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine0_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine0_twtpcon_ready) begin
- litedramcore_bankmachine0_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- litedramcore_bankmachine0_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine1_req_valid;
-assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine1_req_we;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine1_req_addr;
-assign litedramcore_bankmachine1_cmd_buffer_sink_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine1_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine1_cmd_buffer_sink_first = litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine1_cmd_buffer_sink_last = litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine1_cmd_buffer_sink_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine1_cmd_buffer_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid);
-assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine1_cmd_buffer_source_valid);
-assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]);
+ litedramcore_bankmachine0_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine0_source_valid & litedramcore_bankmachine0_source_source_valid)) begin
+ if ((litedramcore_bankmachine0_source_payload_addr[21:7] != litedramcore_bankmachine0_source_source_payload_addr[21:7])) begin
+ litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine0_syncfifo0_din = {litedramcore_bankmachine0_fifo_in_last, litedramcore_bankmachine0_fifo_in_first, litedramcore_bankmachine0_fifo_in_payload_addr, litedramcore_bankmachine0_fifo_in_payload_we};
+assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout;
+assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout;
+assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout;
+assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout;
+assign litedramcore_bankmachine0_sink_ready = litedramcore_bankmachine0_syncfifo0_writable;
+assign litedramcore_bankmachine0_syncfifo0_we = litedramcore_bankmachine0_sink_valid;
+assign litedramcore_bankmachine0_fifo_in_first = litedramcore_bankmachine0_sink_first;
+assign litedramcore_bankmachine0_fifo_in_last = litedramcore_bankmachine0_sink_last;
+assign litedramcore_bankmachine0_fifo_in_payload_we = litedramcore_bankmachine0_sink_payload_we;
+assign litedramcore_bankmachine0_fifo_in_payload_addr = litedramcore_bankmachine0_sink_payload_addr;
+assign litedramcore_bankmachine0_source_valid = litedramcore_bankmachine0_syncfifo0_readable;
+assign litedramcore_bankmachine0_source_first = litedramcore_bankmachine0_fifo_out_first;
+assign litedramcore_bankmachine0_source_last = litedramcore_bankmachine0_fifo_out_last;
+assign litedramcore_bankmachine0_source_payload_we = litedramcore_bankmachine0_fifo_out_payload_we;
+assign litedramcore_bankmachine0_source_payload_addr = litedramcore_bankmachine0_fifo_out_payload_addr;
+assign litedramcore_bankmachine0_syncfifo0_re = litedramcore_bankmachine0_source_ready;
+always @(*) begin
+ litedramcore_bankmachine0_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine0_replace) begin
+ litedramcore_bankmachine0_wrport_adr <= (litedramcore_bankmachine0_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine0_wrport_adr <= litedramcore_bankmachine0_produce;
+ end
+end
+assign litedramcore_bankmachine0_wrport_dat_w = litedramcore_bankmachine0_syncfifo0_din;
+assign litedramcore_bankmachine0_wrport_we = (litedramcore_bankmachine0_syncfifo0_we & (litedramcore_bankmachine0_syncfifo0_writable | litedramcore_bankmachine0_replace));
+assign litedramcore_bankmachine0_do_read = (litedramcore_bankmachine0_syncfifo0_readable & litedramcore_bankmachine0_syncfifo0_re);
+assign litedramcore_bankmachine0_rdport_adr = litedramcore_bankmachine0_consume;
+assign litedramcore_bankmachine0_syncfifo0_dout = litedramcore_bankmachine0_rdport_dat_r;
+assign litedramcore_bankmachine0_syncfifo0_writable = (litedramcore_bankmachine0_level != 5'd16);
+assign litedramcore_bankmachine0_syncfifo0_readable = (litedramcore_bankmachine0_level != 1'd0);
+assign litedramcore_bankmachine0_pipe_valid_sink_ready = ((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready);
+assign litedramcore_bankmachine0_pipe_valid_sink_valid = litedramcore_bankmachine0_sink_sink_valid;
+assign litedramcore_bankmachine0_sink_sink_ready = litedramcore_bankmachine0_pipe_valid_sink_ready;
+assign litedramcore_bankmachine0_pipe_valid_sink_first = litedramcore_bankmachine0_sink_sink_first;
+assign litedramcore_bankmachine0_pipe_valid_sink_last = litedramcore_bankmachine0_sink_sink_last;
+assign litedramcore_bankmachine0_pipe_valid_sink_payload_we = litedramcore_bankmachine0_sink_sink_payload_we;
+assign litedramcore_bankmachine0_pipe_valid_sink_payload_addr = litedramcore_bankmachine0_sink_sink_payload_addr;
+assign litedramcore_bankmachine0_source_source_valid = litedramcore_bankmachine0_pipe_valid_source_valid;
+assign litedramcore_bankmachine0_pipe_valid_source_ready = litedramcore_bankmachine0_source_source_ready;
+assign litedramcore_bankmachine0_source_source_first = litedramcore_bankmachine0_pipe_valid_source_first;
+assign litedramcore_bankmachine0_source_source_last = litedramcore_bankmachine0_pipe_valid_source_last;
+assign litedramcore_bankmachine0_source_source_payload_we = litedramcore_bankmachine0_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine0_source_source_payload_addr = litedramcore_bankmachine0_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine0_next_state <= 4'd0;
+ litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ if (litedramcore_bankmachine0_cmd_ready) begin
+ litedramcore_bankmachine0_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ if (litedramcore_bankmachine0_cmd_ready) begin
+ litedramcore_bankmachine0_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine0_refresh_req)) begin
+ litedramcore_bankmachine0_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine0_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine0_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine0_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine0_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ litedramcore_bankmachine0_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin
+ litedramcore_bankmachine0_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine0_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine0_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if (litedramcore_bankmachine0_source_source_payload_we) begin
+ litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if (litedramcore_bankmachine0_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if (litedramcore_bankmachine0_source_source_payload_we) begin
+ litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if (litedramcore_bankmachine0_source_source_payload_we) begin
+ litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if (litedramcore_bankmachine0_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine0_twtpcon_ready) begin
+ litedramcore_bankmachine0_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_row_open <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_row_close <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ litedramcore_bankmachine0_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine0_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine0_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ litedramcore_bankmachine0_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+assign litedramcore_bankmachine1_sink_valid = litedramcore_bankmachine1_req_valid;
+assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_sink_ready;
+assign litedramcore_bankmachine1_sink_payload_we = litedramcore_bankmachine1_req_we;
+assign litedramcore_bankmachine1_sink_payload_addr = litedramcore_bankmachine1_req_addr;
+assign litedramcore_bankmachine1_sink_sink_valid = litedramcore_bankmachine1_source_valid;
+assign litedramcore_bankmachine1_source_ready = litedramcore_bankmachine1_sink_sink_ready;
+assign litedramcore_bankmachine1_sink_sink_first = litedramcore_bankmachine1_source_first;
+assign litedramcore_bankmachine1_sink_sink_last = litedramcore_bankmachine1_source_last;
+assign litedramcore_bankmachine1_sink_sink_payload_we = litedramcore_bankmachine1_source_payload_we;
+assign litedramcore_bankmachine1_sink_sink_payload_addr = litedramcore_bankmachine1_source_payload_addr;
+assign litedramcore_bankmachine1_source_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid);
+assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_source_valid | litedramcore_bankmachine1_source_source_valid);
+assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_source_source_payload_addr[21:7]);
assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
always @(*) begin
- litedramcore_bankmachine1_cmd_payload_a <= 15'd0;
- if (litedramcore_bankmachine1_row_col_n_addr_sel) begin
- litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7];
- end else begin
- litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine1_cmd_payload_a <= 15'd0;
+ if (litedramcore_bankmachine1_row_col_n_addr_sel) begin
+ litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_source_source_payload_addr[21:7];
+ end else begin
+ litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write);
assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
always @(*) begin
- litedramcore_bankmachine1_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine1_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7])) begin
- litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine1_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | litedramcore_bankmachine1_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re);
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine1_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine1_next_state <= 4'd0;
- litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- if (litedramcore_bankmachine1_cmd_ready) begin
- litedramcore_bankmachine1_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- if (litedramcore_bankmachine1_cmd_ready) begin
- litedramcore_bankmachine1_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine1_refresh_req)) begin
- litedramcore_bankmachine1_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine1_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine1_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine1_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine1_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- litedramcore_bankmachine1_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin
- litedramcore_bankmachine1_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine1_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine1_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_row_open <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_row_close <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- litedramcore_bankmachine1_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine1_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine1_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine1_twtpcon_ready) begin
- litedramcore_bankmachine1_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine2_req_valid;
-assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine2_req_we;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine2_req_addr;
-assign litedramcore_bankmachine2_cmd_buffer_sink_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine2_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine2_cmd_buffer_sink_first = litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine2_cmd_buffer_sink_last = litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine2_cmd_buffer_sink_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine2_cmd_buffer_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid);
-assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine2_cmd_buffer_source_valid);
-assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]);
+ litedramcore_bankmachine1_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine1_source_valid & litedramcore_bankmachine1_source_source_valid)) begin
+ if ((litedramcore_bankmachine1_source_payload_addr[21:7] != litedramcore_bankmachine1_source_source_payload_addr[21:7])) begin
+ litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine1_syncfifo1_din = {litedramcore_bankmachine1_fifo_in_last, litedramcore_bankmachine1_fifo_in_first, litedramcore_bankmachine1_fifo_in_payload_addr, litedramcore_bankmachine1_fifo_in_payload_we};
+assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout;
+assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout;
+assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout;
+assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout;
+assign litedramcore_bankmachine1_sink_ready = litedramcore_bankmachine1_syncfifo1_writable;
+assign litedramcore_bankmachine1_syncfifo1_we = litedramcore_bankmachine1_sink_valid;
+assign litedramcore_bankmachine1_fifo_in_first = litedramcore_bankmachine1_sink_first;
+assign litedramcore_bankmachine1_fifo_in_last = litedramcore_bankmachine1_sink_last;
+assign litedramcore_bankmachine1_fifo_in_payload_we = litedramcore_bankmachine1_sink_payload_we;
+assign litedramcore_bankmachine1_fifo_in_payload_addr = litedramcore_bankmachine1_sink_payload_addr;
+assign litedramcore_bankmachine1_source_valid = litedramcore_bankmachine1_syncfifo1_readable;
+assign litedramcore_bankmachine1_source_first = litedramcore_bankmachine1_fifo_out_first;
+assign litedramcore_bankmachine1_source_last = litedramcore_bankmachine1_fifo_out_last;
+assign litedramcore_bankmachine1_source_payload_we = litedramcore_bankmachine1_fifo_out_payload_we;
+assign litedramcore_bankmachine1_source_payload_addr = litedramcore_bankmachine1_fifo_out_payload_addr;
+assign litedramcore_bankmachine1_syncfifo1_re = litedramcore_bankmachine1_source_ready;
+always @(*) begin
+ litedramcore_bankmachine1_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine1_replace) begin
+ litedramcore_bankmachine1_wrport_adr <= (litedramcore_bankmachine1_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine1_wrport_adr <= litedramcore_bankmachine1_produce;
+ end
+end
+assign litedramcore_bankmachine1_wrport_dat_w = litedramcore_bankmachine1_syncfifo1_din;
+assign litedramcore_bankmachine1_wrport_we = (litedramcore_bankmachine1_syncfifo1_we & (litedramcore_bankmachine1_syncfifo1_writable | litedramcore_bankmachine1_replace));
+assign litedramcore_bankmachine1_do_read = (litedramcore_bankmachine1_syncfifo1_readable & litedramcore_bankmachine1_syncfifo1_re);
+assign litedramcore_bankmachine1_rdport_adr = litedramcore_bankmachine1_consume;
+assign litedramcore_bankmachine1_syncfifo1_dout = litedramcore_bankmachine1_rdport_dat_r;
+assign litedramcore_bankmachine1_syncfifo1_writable = (litedramcore_bankmachine1_level != 5'd16);
+assign litedramcore_bankmachine1_syncfifo1_readable = (litedramcore_bankmachine1_level != 1'd0);
+assign litedramcore_bankmachine1_pipe_valid_sink_ready = ((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready);
+assign litedramcore_bankmachine1_pipe_valid_sink_valid = litedramcore_bankmachine1_sink_sink_valid;
+assign litedramcore_bankmachine1_sink_sink_ready = litedramcore_bankmachine1_pipe_valid_sink_ready;
+assign litedramcore_bankmachine1_pipe_valid_sink_first = litedramcore_bankmachine1_sink_sink_first;
+assign litedramcore_bankmachine1_pipe_valid_sink_last = litedramcore_bankmachine1_sink_sink_last;
+assign litedramcore_bankmachine1_pipe_valid_sink_payload_we = litedramcore_bankmachine1_sink_sink_payload_we;
+assign litedramcore_bankmachine1_pipe_valid_sink_payload_addr = litedramcore_bankmachine1_sink_sink_payload_addr;
+assign litedramcore_bankmachine1_source_source_valid = litedramcore_bankmachine1_pipe_valid_source_valid;
+assign litedramcore_bankmachine1_pipe_valid_source_ready = litedramcore_bankmachine1_source_source_ready;
+assign litedramcore_bankmachine1_source_source_first = litedramcore_bankmachine1_pipe_valid_source_first;
+assign litedramcore_bankmachine1_source_source_last = litedramcore_bankmachine1_pipe_valid_source_last;
+assign litedramcore_bankmachine1_source_source_payload_we = litedramcore_bankmachine1_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine1_source_source_payload_addr = litedramcore_bankmachine1_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine1_next_state <= 4'd0;
+ litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ if (litedramcore_bankmachine1_cmd_ready) begin
+ litedramcore_bankmachine1_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ if (litedramcore_bankmachine1_cmd_ready) begin
+ litedramcore_bankmachine1_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine1_refresh_req)) begin
+ litedramcore_bankmachine1_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine1_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine1_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine1_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine1_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ litedramcore_bankmachine1_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin
+ litedramcore_bankmachine1_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine1_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine1_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if (litedramcore_bankmachine1_source_source_payload_we) begin
+ litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if (litedramcore_bankmachine1_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if (litedramcore_bankmachine1_source_source_payload_we) begin
+ litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if (litedramcore_bankmachine1_source_source_payload_we) begin
+ litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if (litedramcore_bankmachine1_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_row_open <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ litedramcore_bankmachine1_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_row_close <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ litedramcore_bankmachine1_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine1_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine1_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine1_twtpcon_ready) begin
+ litedramcore_bankmachine1_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+assign litedramcore_bankmachine2_sink_valid = litedramcore_bankmachine2_req_valid;
+assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_sink_ready;
+assign litedramcore_bankmachine2_sink_payload_we = litedramcore_bankmachine2_req_we;
+assign litedramcore_bankmachine2_sink_payload_addr = litedramcore_bankmachine2_req_addr;
+assign litedramcore_bankmachine2_sink_sink_valid = litedramcore_bankmachine2_source_valid;
+assign litedramcore_bankmachine2_source_ready = litedramcore_bankmachine2_sink_sink_ready;
+assign litedramcore_bankmachine2_sink_sink_first = litedramcore_bankmachine2_source_first;
+assign litedramcore_bankmachine2_sink_sink_last = litedramcore_bankmachine2_source_last;
+assign litedramcore_bankmachine2_sink_sink_payload_we = litedramcore_bankmachine2_source_payload_we;
+assign litedramcore_bankmachine2_sink_sink_payload_addr = litedramcore_bankmachine2_source_payload_addr;
+assign litedramcore_bankmachine2_source_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid);
+assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_source_valid | litedramcore_bankmachine2_source_source_valid);
+assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_source_source_payload_addr[21:7]);
assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
always @(*) begin
- litedramcore_bankmachine2_cmd_payload_a <= 15'd0;
- if (litedramcore_bankmachine2_row_col_n_addr_sel) begin
- litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7];
- end else begin
- litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine2_cmd_payload_a <= 15'd0;
+ if (litedramcore_bankmachine2_row_col_n_addr_sel) begin
+ litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_source_source_payload_addr[21:7];
+ end else begin
+ litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write);
assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
always @(*) begin
- litedramcore_bankmachine2_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine2_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7])) begin
- litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine2_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | litedramcore_bankmachine2_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re);
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine2_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine2_next_state <= 4'd0;
- litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- if (litedramcore_bankmachine2_cmd_ready) begin
- litedramcore_bankmachine2_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- if (litedramcore_bankmachine2_cmd_ready) begin
- litedramcore_bankmachine2_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine2_refresh_req)) begin
- litedramcore_bankmachine2_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine2_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine2_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine2_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine2_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- litedramcore_bankmachine2_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin
- litedramcore_bankmachine2_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine2_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine2_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_row_open <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_row_close <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- litedramcore_bankmachine2_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine2_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine2_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- litedramcore_bankmachine2_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine2_twtpcon_ready) begin
- litedramcore_bankmachine2_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine3_req_valid;
-assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine3_req_we;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine3_req_addr;
-assign litedramcore_bankmachine3_cmd_buffer_sink_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine3_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine3_cmd_buffer_sink_first = litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine3_cmd_buffer_sink_last = litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine3_cmd_buffer_sink_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine3_cmd_buffer_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid);
-assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine3_cmd_buffer_source_valid);
-assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]);
+ litedramcore_bankmachine2_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine2_source_valid & litedramcore_bankmachine2_source_source_valid)) begin
+ if ((litedramcore_bankmachine2_source_payload_addr[21:7] != litedramcore_bankmachine2_source_source_payload_addr[21:7])) begin
+ litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine2_syncfifo2_din = {litedramcore_bankmachine2_fifo_in_last, litedramcore_bankmachine2_fifo_in_first, litedramcore_bankmachine2_fifo_in_payload_addr, litedramcore_bankmachine2_fifo_in_payload_we};
+assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout;
+assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout;
+assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout;
+assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout;
+assign litedramcore_bankmachine2_sink_ready = litedramcore_bankmachine2_syncfifo2_writable;
+assign litedramcore_bankmachine2_syncfifo2_we = litedramcore_bankmachine2_sink_valid;
+assign litedramcore_bankmachine2_fifo_in_first = litedramcore_bankmachine2_sink_first;
+assign litedramcore_bankmachine2_fifo_in_last = litedramcore_bankmachine2_sink_last;
+assign litedramcore_bankmachine2_fifo_in_payload_we = litedramcore_bankmachine2_sink_payload_we;
+assign litedramcore_bankmachine2_fifo_in_payload_addr = litedramcore_bankmachine2_sink_payload_addr;
+assign litedramcore_bankmachine2_source_valid = litedramcore_bankmachine2_syncfifo2_readable;
+assign litedramcore_bankmachine2_source_first = litedramcore_bankmachine2_fifo_out_first;
+assign litedramcore_bankmachine2_source_last = litedramcore_bankmachine2_fifo_out_last;
+assign litedramcore_bankmachine2_source_payload_we = litedramcore_bankmachine2_fifo_out_payload_we;
+assign litedramcore_bankmachine2_source_payload_addr = litedramcore_bankmachine2_fifo_out_payload_addr;
+assign litedramcore_bankmachine2_syncfifo2_re = litedramcore_bankmachine2_source_ready;
+always @(*) begin
+ litedramcore_bankmachine2_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine2_replace) begin
+ litedramcore_bankmachine2_wrport_adr <= (litedramcore_bankmachine2_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine2_wrport_adr <= litedramcore_bankmachine2_produce;
+ end
+end
+assign litedramcore_bankmachine2_wrport_dat_w = litedramcore_bankmachine2_syncfifo2_din;
+assign litedramcore_bankmachine2_wrport_we = (litedramcore_bankmachine2_syncfifo2_we & (litedramcore_bankmachine2_syncfifo2_writable | litedramcore_bankmachine2_replace));
+assign litedramcore_bankmachine2_do_read = (litedramcore_bankmachine2_syncfifo2_readable & litedramcore_bankmachine2_syncfifo2_re);
+assign litedramcore_bankmachine2_rdport_adr = litedramcore_bankmachine2_consume;
+assign litedramcore_bankmachine2_syncfifo2_dout = litedramcore_bankmachine2_rdport_dat_r;
+assign litedramcore_bankmachine2_syncfifo2_writable = (litedramcore_bankmachine2_level != 5'd16);
+assign litedramcore_bankmachine2_syncfifo2_readable = (litedramcore_bankmachine2_level != 1'd0);
+assign litedramcore_bankmachine2_pipe_valid_sink_ready = ((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready);
+assign litedramcore_bankmachine2_pipe_valid_sink_valid = litedramcore_bankmachine2_sink_sink_valid;
+assign litedramcore_bankmachine2_sink_sink_ready = litedramcore_bankmachine2_pipe_valid_sink_ready;
+assign litedramcore_bankmachine2_pipe_valid_sink_first = litedramcore_bankmachine2_sink_sink_first;
+assign litedramcore_bankmachine2_pipe_valid_sink_last = litedramcore_bankmachine2_sink_sink_last;
+assign litedramcore_bankmachine2_pipe_valid_sink_payload_we = litedramcore_bankmachine2_sink_sink_payload_we;
+assign litedramcore_bankmachine2_pipe_valid_sink_payload_addr = litedramcore_bankmachine2_sink_sink_payload_addr;
+assign litedramcore_bankmachine2_source_source_valid = litedramcore_bankmachine2_pipe_valid_source_valid;
+assign litedramcore_bankmachine2_pipe_valid_source_ready = litedramcore_bankmachine2_source_source_ready;
+assign litedramcore_bankmachine2_source_source_first = litedramcore_bankmachine2_pipe_valid_source_first;
+assign litedramcore_bankmachine2_source_source_last = litedramcore_bankmachine2_pipe_valid_source_last;
+assign litedramcore_bankmachine2_source_source_payload_we = litedramcore_bankmachine2_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine2_source_source_payload_addr = litedramcore_bankmachine2_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine2_next_state <= 4'd0;
+ litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ if (litedramcore_bankmachine2_cmd_ready) begin
+ litedramcore_bankmachine2_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ if (litedramcore_bankmachine2_cmd_ready) begin
+ litedramcore_bankmachine2_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine2_refresh_req)) begin
+ litedramcore_bankmachine2_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine2_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine2_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine2_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine2_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ litedramcore_bankmachine2_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin
+ litedramcore_bankmachine2_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine2_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine2_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if (litedramcore_bankmachine2_source_source_payload_we) begin
+ litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if (litedramcore_bankmachine2_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine2_twtpcon_ready) begin
+ litedramcore_bankmachine2_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_row_open <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ litedramcore_bankmachine2_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_row_close <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ litedramcore_bankmachine2_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine2_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine2_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if (litedramcore_bankmachine2_source_source_payload_we) begin
+ litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if (litedramcore_bankmachine2_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if (litedramcore_bankmachine2_source_source_payload_we) begin
+ litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+assign litedramcore_bankmachine3_sink_valid = litedramcore_bankmachine3_req_valid;
+assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_sink_ready;
+assign litedramcore_bankmachine3_sink_payload_we = litedramcore_bankmachine3_req_we;
+assign litedramcore_bankmachine3_sink_payload_addr = litedramcore_bankmachine3_req_addr;
+assign litedramcore_bankmachine3_sink_sink_valid = litedramcore_bankmachine3_source_valid;
+assign litedramcore_bankmachine3_source_ready = litedramcore_bankmachine3_sink_sink_ready;
+assign litedramcore_bankmachine3_sink_sink_first = litedramcore_bankmachine3_source_first;
+assign litedramcore_bankmachine3_sink_sink_last = litedramcore_bankmachine3_source_last;
+assign litedramcore_bankmachine3_sink_sink_payload_we = litedramcore_bankmachine3_source_payload_we;
+assign litedramcore_bankmachine3_sink_sink_payload_addr = litedramcore_bankmachine3_source_payload_addr;
+assign litedramcore_bankmachine3_source_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid);
+assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_source_valid | litedramcore_bankmachine3_source_source_valid);
+assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_source_source_payload_addr[21:7]);
assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
always @(*) begin
- litedramcore_bankmachine3_cmd_payload_a <= 15'd0;
- if (litedramcore_bankmachine3_row_col_n_addr_sel) begin
- litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7];
- end else begin
- litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine3_cmd_payload_a <= 15'd0;
+ if (litedramcore_bankmachine3_row_col_n_addr_sel) begin
+ litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_source_source_payload_addr[21:7];
+ end else begin
+ litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write);
assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
always @(*) begin
- litedramcore_bankmachine3_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine3_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7])) begin
- litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine3_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | litedramcore_bankmachine3_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re);
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine3_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine3_next_state <= 4'd0;
- litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- if (litedramcore_bankmachine3_cmd_ready) begin
- litedramcore_bankmachine3_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- if (litedramcore_bankmachine3_cmd_ready) begin
- litedramcore_bankmachine3_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine3_refresh_req)) begin
- litedramcore_bankmachine3_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine3_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine3_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine3_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine3_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- litedramcore_bankmachine3_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin
- litedramcore_bankmachine3_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine3_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine3_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_row_open <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_row_close <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- litedramcore_bankmachine3_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine3_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine3_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine3_twtpcon_ready) begin
- litedramcore_bankmachine3_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- litedramcore_bankmachine3_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine4_req_valid;
-assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine4_req_we;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine4_req_addr;
-assign litedramcore_bankmachine4_cmd_buffer_sink_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine4_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine4_cmd_buffer_sink_first = litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine4_cmd_buffer_sink_last = litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine4_cmd_buffer_sink_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine4_cmd_buffer_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid);
-assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine4_cmd_buffer_source_valid);
-assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]);
+ litedramcore_bankmachine3_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine3_source_valid & litedramcore_bankmachine3_source_source_valid)) begin
+ if ((litedramcore_bankmachine3_source_payload_addr[21:7] != litedramcore_bankmachine3_source_source_payload_addr[21:7])) begin
+ litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine3_syncfifo3_din = {litedramcore_bankmachine3_fifo_in_last, litedramcore_bankmachine3_fifo_in_first, litedramcore_bankmachine3_fifo_in_payload_addr, litedramcore_bankmachine3_fifo_in_payload_we};
+assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout;
+assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout;
+assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout;
+assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout;
+assign litedramcore_bankmachine3_sink_ready = litedramcore_bankmachine3_syncfifo3_writable;
+assign litedramcore_bankmachine3_syncfifo3_we = litedramcore_bankmachine3_sink_valid;
+assign litedramcore_bankmachine3_fifo_in_first = litedramcore_bankmachine3_sink_first;
+assign litedramcore_bankmachine3_fifo_in_last = litedramcore_bankmachine3_sink_last;
+assign litedramcore_bankmachine3_fifo_in_payload_we = litedramcore_bankmachine3_sink_payload_we;
+assign litedramcore_bankmachine3_fifo_in_payload_addr = litedramcore_bankmachine3_sink_payload_addr;
+assign litedramcore_bankmachine3_source_valid = litedramcore_bankmachine3_syncfifo3_readable;
+assign litedramcore_bankmachine3_source_first = litedramcore_bankmachine3_fifo_out_first;
+assign litedramcore_bankmachine3_source_last = litedramcore_bankmachine3_fifo_out_last;
+assign litedramcore_bankmachine3_source_payload_we = litedramcore_bankmachine3_fifo_out_payload_we;
+assign litedramcore_bankmachine3_source_payload_addr = litedramcore_bankmachine3_fifo_out_payload_addr;
+assign litedramcore_bankmachine3_syncfifo3_re = litedramcore_bankmachine3_source_ready;
+always @(*) begin
+ litedramcore_bankmachine3_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine3_replace) begin
+ litedramcore_bankmachine3_wrport_adr <= (litedramcore_bankmachine3_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine3_wrport_adr <= litedramcore_bankmachine3_produce;
+ end
+end
+assign litedramcore_bankmachine3_wrport_dat_w = litedramcore_bankmachine3_syncfifo3_din;
+assign litedramcore_bankmachine3_wrport_we = (litedramcore_bankmachine3_syncfifo3_we & (litedramcore_bankmachine3_syncfifo3_writable | litedramcore_bankmachine3_replace));
+assign litedramcore_bankmachine3_do_read = (litedramcore_bankmachine3_syncfifo3_readable & litedramcore_bankmachine3_syncfifo3_re);
+assign litedramcore_bankmachine3_rdport_adr = litedramcore_bankmachine3_consume;
+assign litedramcore_bankmachine3_syncfifo3_dout = litedramcore_bankmachine3_rdport_dat_r;
+assign litedramcore_bankmachine3_syncfifo3_writable = (litedramcore_bankmachine3_level != 5'd16);
+assign litedramcore_bankmachine3_syncfifo3_readable = (litedramcore_bankmachine3_level != 1'd0);
+assign litedramcore_bankmachine3_pipe_valid_sink_ready = ((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready);
+assign litedramcore_bankmachine3_pipe_valid_sink_valid = litedramcore_bankmachine3_sink_sink_valid;
+assign litedramcore_bankmachine3_sink_sink_ready = litedramcore_bankmachine3_pipe_valid_sink_ready;
+assign litedramcore_bankmachine3_pipe_valid_sink_first = litedramcore_bankmachine3_sink_sink_first;
+assign litedramcore_bankmachine3_pipe_valid_sink_last = litedramcore_bankmachine3_sink_sink_last;
+assign litedramcore_bankmachine3_pipe_valid_sink_payload_we = litedramcore_bankmachine3_sink_sink_payload_we;
+assign litedramcore_bankmachine3_pipe_valid_sink_payload_addr = litedramcore_bankmachine3_sink_sink_payload_addr;
+assign litedramcore_bankmachine3_source_source_valid = litedramcore_bankmachine3_pipe_valid_source_valid;
+assign litedramcore_bankmachine3_pipe_valid_source_ready = litedramcore_bankmachine3_source_source_ready;
+assign litedramcore_bankmachine3_source_source_first = litedramcore_bankmachine3_pipe_valid_source_first;
+assign litedramcore_bankmachine3_source_source_last = litedramcore_bankmachine3_pipe_valid_source_last;
+assign litedramcore_bankmachine3_source_source_payload_we = litedramcore_bankmachine3_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine3_source_source_payload_addr = litedramcore_bankmachine3_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine3_next_state <= 4'd0;
+ litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ if (litedramcore_bankmachine3_cmd_ready) begin
+ litedramcore_bankmachine3_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ if (litedramcore_bankmachine3_cmd_ready) begin
+ litedramcore_bankmachine3_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine3_refresh_req)) begin
+ litedramcore_bankmachine3_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine3_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine3_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine3_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine3_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ litedramcore_bankmachine3_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin
+ litedramcore_bankmachine3_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine3_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine3_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_row_open <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ litedramcore_bankmachine3_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_row_close <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ litedramcore_bankmachine3_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine3_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine3_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if (litedramcore_bankmachine3_source_source_payload_we) begin
+ litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if (litedramcore_bankmachine3_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if (litedramcore_bankmachine3_source_source_payload_we) begin
+ litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if (litedramcore_bankmachine3_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if (litedramcore_bankmachine3_source_source_payload_we) begin
+ litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine3_twtpcon_ready) begin
+ litedramcore_bankmachine3_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+assign litedramcore_bankmachine4_sink_valid = litedramcore_bankmachine4_req_valid;
+assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_sink_ready;
+assign litedramcore_bankmachine4_sink_payload_we = litedramcore_bankmachine4_req_we;
+assign litedramcore_bankmachine4_sink_payload_addr = litedramcore_bankmachine4_req_addr;
+assign litedramcore_bankmachine4_sink_sink_valid = litedramcore_bankmachine4_source_valid;
+assign litedramcore_bankmachine4_source_ready = litedramcore_bankmachine4_sink_sink_ready;
+assign litedramcore_bankmachine4_sink_sink_first = litedramcore_bankmachine4_source_first;
+assign litedramcore_bankmachine4_sink_sink_last = litedramcore_bankmachine4_source_last;
+assign litedramcore_bankmachine4_sink_sink_payload_we = litedramcore_bankmachine4_source_payload_we;
+assign litedramcore_bankmachine4_sink_sink_payload_addr = litedramcore_bankmachine4_source_payload_addr;
+assign litedramcore_bankmachine4_source_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid);
+assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_source_valid | litedramcore_bankmachine4_source_source_valid);
+assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_source_source_payload_addr[21:7]);
assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
always @(*) begin
- litedramcore_bankmachine4_cmd_payload_a <= 15'd0;
- if (litedramcore_bankmachine4_row_col_n_addr_sel) begin
- litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7];
- end else begin
- litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine4_cmd_payload_a <= 15'd0;
+ if (litedramcore_bankmachine4_row_col_n_addr_sel) begin
+ litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_source_source_payload_addr[21:7];
+ end else begin
+ litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write);
assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
always @(*) begin
- litedramcore_bankmachine4_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine4_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7])) begin
- litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine4_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | litedramcore_bankmachine4_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re);
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine4_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine4_next_state <= 4'd0;
- litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- if (litedramcore_bankmachine4_cmd_ready) begin
- litedramcore_bankmachine4_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- if (litedramcore_bankmachine4_cmd_ready) begin
- litedramcore_bankmachine4_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine4_refresh_req)) begin
- litedramcore_bankmachine4_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine4_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine4_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine4_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine4_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- litedramcore_bankmachine4_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin
- litedramcore_bankmachine4_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine4_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine4_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_row_open <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_row_close <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- litedramcore_bankmachine4_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine4_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine4_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- litedramcore_bankmachine4_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine4_twtpcon_ready) begin
- litedramcore_bankmachine4_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine5_req_valid;
-assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine5_req_we;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine5_req_addr;
-assign litedramcore_bankmachine5_cmd_buffer_sink_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine5_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine5_cmd_buffer_sink_first = litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine5_cmd_buffer_sink_last = litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine5_cmd_buffer_sink_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine5_cmd_buffer_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid);
-assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine5_cmd_buffer_source_valid);
-assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]);
+ litedramcore_bankmachine4_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine4_source_valid & litedramcore_bankmachine4_source_source_valid)) begin
+ if ((litedramcore_bankmachine4_source_payload_addr[21:7] != litedramcore_bankmachine4_source_source_payload_addr[21:7])) begin
+ litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine4_syncfifo4_din = {litedramcore_bankmachine4_fifo_in_last, litedramcore_bankmachine4_fifo_in_first, litedramcore_bankmachine4_fifo_in_payload_addr, litedramcore_bankmachine4_fifo_in_payload_we};
+assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout;
+assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout;
+assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout;
+assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout;
+assign litedramcore_bankmachine4_sink_ready = litedramcore_bankmachine4_syncfifo4_writable;
+assign litedramcore_bankmachine4_syncfifo4_we = litedramcore_bankmachine4_sink_valid;
+assign litedramcore_bankmachine4_fifo_in_first = litedramcore_bankmachine4_sink_first;
+assign litedramcore_bankmachine4_fifo_in_last = litedramcore_bankmachine4_sink_last;
+assign litedramcore_bankmachine4_fifo_in_payload_we = litedramcore_bankmachine4_sink_payload_we;
+assign litedramcore_bankmachine4_fifo_in_payload_addr = litedramcore_bankmachine4_sink_payload_addr;
+assign litedramcore_bankmachine4_source_valid = litedramcore_bankmachine4_syncfifo4_readable;
+assign litedramcore_bankmachine4_source_first = litedramcore_bankmachine4_fifo_out_first;
+assign litedramcore_bankmachine4_source_last = litedramcore_bankmachine4_fifo_out_last;
+assign litedramcore_bankmachine4_source_payload_we = litedramcore_bankmachine4_fifo_out_payload_we;
+assign litedramcore_bankmachine4_source_payload_addr = litedramcore_bankmachine4_fifo_out_payload_addr;
+assign litedramcore_bankmachine4_syncfifo4_re = litedramcore_bankmachine4_source_ready;
+always @(*) begin
+ litedramcore_bankmachine4_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine4_replace) begin
+ litedramcore_bankmachine4_wrport_adr <= (litedramcore_bankmachine4_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine4_wrport_adr <= litedramcore_bankmachine4_produce;
+ end
+end
+assign litedramcore_bankmachine4_wrport_dat_w = litedramcore_bankmachine4_syncfifo4_din;
+assign litedramcore_bankmachine4_wrport_we = (litedramcore_bankmachine4_syncfifo4_we & (litedramcore_bankmachine4_syncfifo4_writable | litedramcore_bankmachine4_replace));
+assign litedramcore_bankmachine4_do_read = (litedramcore_bankmachine4_syncfifo4_readable & litedramcore_bankmachine4_syncfifo4_re);
+assign litedramcore_bankmachine4_rdport_adr = litedramcore_bankmachine4_consume;
+assign litedramcore_bankmachine4_syncfifo4_dout = litedramcore_bankmachine4_rdport_dat_r;
+assign litedramcore_bankmachine4_syncfifo4_writable = (litedramcore_bankmachine4_level != 5'd16);
+assign litedramcore_bankmachine4_syncfifo4_readable = (litedramcore_bankmachine4_level != 1'd0);
+assign litedramcore_bankmachine4_pipe_valid_sink_ready = ((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready);
+assign litedramcore_bankmachine4_pipe_valid_sink_valid = litedramcore_bankmachine4_sink_sink_valid;
+assign litedramcore_bankmachine4_sink_sink_ready = litedramcore_bankmachine4_pipe_valid_sink_ready;
+assign litedramcore_bankmachine4_pipe_valid_sink_first = litedramcore_bankmachine4_sink_sink_first;
+assign litedramcore_bankmachine4_pipe_valid_sink_last = litedramcore_bankmachine4_sink_sink_last;
+assign litedramcore_bankmachine4_pipe_valid_sink_payload_we = litedramcore_bankmachine4_sink_sink_payload_we;
+assign litedramcore_bankmachine4_pipe_valid_sink_payload_addr = litedramcore_bankmachine4_sink_sink_payload_addr;
+assign litedramcore_bankmachine4_source_source_valid = litedramcore_bankmachine4_pipe_valid_source_valid;
+assign litedramcore_bankmachine4_pipe_valid_source_ready = litedramcore_bankmachine4_source_source_ready;
+assign litedramcore_bankmachine4_source_source_first = litedramcore_bankmachine4_pipe_valid_source_first;
+assign litedramcore_bankmachine4_source_source_last = litedramcore_bankmachine4_pipe_valid_source_last;
+assign litedramcore_bankmachine4_source_source_payload_we = litedramcore_bankmachine4_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine4_source_source_payload_addr = litedramcore_bankmachine4_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine4_next_state <= 4'd0;
+ litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ if (litedramcore_bankmachine4_cmd_ready) begin
+ litedramcore_bankmachine4_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ if (litedramcore_bankmachine4_cmd_ready) begin
+ litedramcore_bankmachine4_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine4_refresh_req)) begin
+ litedramcore_bankmachine4_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine4_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine4_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine4_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine4_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ litedramcore_bankmachine4_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin
+ litedramcore_bankmachine4_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine4_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine4_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ litedramcore_bankmachine4_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ litedramcore_bankmachine4_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if (litedramcore_bankmachine4_source_source_payload_we) begin
+ litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if (litedramcore_bankmachine4_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if (litedramcore_bankmachine4_source_source_payload_we) begin
+ litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if (litedramcore_bankmachine4_source_source_payload_we) begin
+ litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if (litedramcore_bankmachine4_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine4_twtpcon_ready) begin
+ litedramcore_bankmachine4_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_row_open <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ litedramcore_bankmachine4_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_row_close <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ litedramcore_bankmachine4_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine4_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine4_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+assign litedramcore_bankmachine5_sink_valid = litedramcore_bankmachine5_req_valid;
+assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_sink_ready;
+assign litedramcore_bankmachine5_sink_payload_we = litedramcore_bankmachine5_req_we;
+assign litedramcore_bankmachine5_sink_payload_addr = litedramcore_bankmachine5_req_addr;
+assign litedramcore_bankmachine5_sink_sink_valid = litedramcore_bankmachine5_source_valid;
+assign litedramcore_bankmachine5_source_ready = litedramcore_bankmachine5_sink_sink_ready;
+assign litedramcore_bankmachine5_sink_sink_first = litedramcore_bankmachine5_source_first;
+assign litedramcore_bankmachine5_sink_sink_last = litedramcore_bankmachine5_source_last;
+assign litedramcore_bankmachine5_sink_sink_payload_we = litedramcore_bankmachine5_source_payload_we;
+assign litedramcore_bankmachine5_sink_sink_payload_addr = litedramcore_bankmachine5_source_payload_addr;
+assign litedramcore_bankmachine5_source_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid);
+assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_source_valid | litedramcore_bankmachine5_source_source_valid);
+assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_source_source_payload_addr[21:7]);
assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
always @(*) begin
- litedramcore_bankmachine5_cmd_payload_a <= 15'd0;
- if (litedramcore_bankmachine5_row_col_n_addr_sel) begin
- litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7];
- end else begin
- litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine5_cmd_payload_a <= 15'd0;
+ if (litedramcore_bankmachine5_row_col_n_addr_sel) begin
+ litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_source_source_payload_addr[21:7];
+ end else begin
+ litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write);
assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
always @(*) begin
- litedramcore_bankmachine5_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine5_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7])) begin
- litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine5_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | litedramcore_bankmachine5_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re);
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine5_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine5_next_state <= 4'd0;
- litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- if (litedramcore_bankmachine5_cmd_ready) begin
- litedramcore_bankmachine5_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- if (litedramcore_bankmachine5_cmd_ready) begin
- litedramcore_bankmachine5_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine5_refresh_req)) begin
- litedramcore_bankmachine5_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine5_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine5_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine5_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine5_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- litedramcore_bankmachine5_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin
- litedramcore_bankmachine5_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine5_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine5_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_row_open <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_row_close <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- litedramcore_bankmachine5_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine5_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine5_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine5_twtpcon_ready) begin
- litedramcore_bankmachine5_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine6_req_valid;
-assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine6_req_we;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine6_req_addr;
-assign litedramcore_bankmachine6_cmd_buffer_sink_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine6_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine6_cmd_buffer_sink_first = litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine6_cmd_buffer_sink_last = litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine6_cmd_buffer_sink_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine6_cmd_buffer_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid);
-assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine6_cmd_buffer_source_valid);
-assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]);
+ litedramcore_bankmachine5_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine5_source_valid & litedramcore_bankmachine5_source_source_valid)) begin
+ if ((litedramcore_bankmachine5_source_payload_addr[21:7] != litedramcore_bankmachine5_source_source_payload_addr[21:7])) begin
+ litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine5_syncfifo5_din = {litedramcore_bankmachine5_fifo_in_last, litedramcore_bankmachine5_fifo_in_first, litedramcore_bankmachine5_fifo_in_payload_addr, litedramcore_bankmachine5_fifo_in_payload_we};
+assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout;
+assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout;
+assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout;
+assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout;
+assign litedramcore_bankmachine5_sink_ready = litedramcore_bankmachine5_syncfifo5_writable;
+assign litedramcore_bankmachine5_syncfifo5_we = litedramcore_bankmachine5_sink_valid;
+assign litedramcore_bankmachine5_fifo_in_first = litedramcore_bankmachine5_sink_first;
+assign litedramcore_bankmachine5_fifo_in_last = litedramcore_bankmachine5_sink_last;
+assign litedramcore_bankmachine5_fifo_in_payload_we = litedramcore_bankmachine5_sink_payload_we;
+assign litedramcore_bankmachine5_fifo_in_payload_addr = litedramcore_bankmachine5_sink_payload_addr;
+assign litedramcore_bankmachine5_source_valid = litedramcore_bankmachine5_syncfifo5_readable;
+assign litedramcore_bankmachine5_source_first = litedramcore_bankmachine5_fifo_out_first;
+assign litedramcore_bankmachine5_source_last = litedramcore_bankmachine5_fifo_out_last;
+assign litedramcore_bankmachine5_source_payload_we = litedramcore_bankmachine5_fifo_out_payload_we;
+assign litedramcore_bankmachine5_source_payload_addr = litedramcore_bankmachine5_fifo_out_payload_addr;
+assign litedramcore_bankmachine5_syncfifo5_re = litedramcore_bankmachine5_source_ready;
+always @(*) begin
+ litedramcore_bankmachine5_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine5_replace) begin
+ litedramcore_bankmachine5_wrport_adr <= (litedramcore_bankmachine5_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine5_wrport_adr <= litedramcore_bankmachine5_produce;
+ end
+end
+assign litedramcore_bankmachine5_wrport_dat_w = litedramcore_bankmachine5_syncfifo5_din;
+assign litedramcore_bankmachine5_wrport_we = (litedramcore_bankmachine5_syncfifo5_we & (litedramcore_bankmachine5_syncfifo5_writable | litedramcore_bankmachine5_replace));
+assign litedramcore_bankmachine5_do_read = (litedramcore_bankmachine5_syncfifo5_readable & litedramcore_bankmachine5_syncfifo5_re);
+assign litedramcore_bankmachine5_rdport_adr = litedramcore_bankmachine5_consume;
+assign litedramcore_bankmachine5_syncfifo5_dout = litedramcore_bankmachine5_rdport_dat_r;
+assign litedramcore_bankmachine5_syncfifo5_writable = (litedramcore_bankmachine5_level != 5'd16);
+assign litedramcore_bankmachine5_syncfifo5_readable = (litedramcore_bankmachine5_level != 1'd0);
+assign litedramcore_bankmachine5_pipe_valid_sink_ready = ((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready);
+assign litedramcore_bankmachine5_pipe_valid_sink_valid = litedramcore_bankmachine5_sink_sink_valid;
+assign litedramcore_bankmachine5_sink_sink_ready = litedramcore_bankmachine5_pipe_valid_sink_ready;
+assign litedramcore_bankmachine5_pipe_valid_sink_first = litedramcore_bankmachine5_sink_sink_first;
+assign litedramcore_bankmachine5_pipe_valid_sink_last = litedramcore_bankmachine5_sink_sink_last;
+assign litedramcore_bankmachine5_pipe_valid_sink_payload_we = litedramcore_bankmachine5_sink_sink_payload_we;
+assign litedramcore_bankmachine5_pipe_valid_sink_payload_addr = litedramcore_bankmachine5_sink_sink_payload_addr;
+assign litedramcore_bankmachine5_source_source_valid = litedramcore_bankmachine5_pipe_valid_source_valid;
+assign litedramcore_bankmachine5_pipe_valid_source_ready = litedramcore_bankmachine5_source_source_ready;
+assign litedramcore_bankmachine5_source_source_first = litedramcore_bankmachine5_pipe_valid_source_first;
+assign litedramcore_bankmachine5_source_source_last = litedramcore_bankmachine5_pipe_valid_source_last;
+assign litedramcore_bankmachine5_source_source_payload_we = litedramcore_bankmachine5_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine5_source_source_payload_addr = litedramcore_bankmachine5_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine5_next_state <= 4'd0;
+ litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ if (litedramcore_bankmachine5_cmd_ready) begin
+ litedramcore_bankmachine5_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ if (litedramcore_bankmachine5_cmd_ready) begin
+ litedramcore_bankmachine5_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine5_refresh_req)) begin
+ litedramcore_bankmachine5_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine5_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine5_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine5_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine5_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ litedramcore_bankmachine5_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin
+ litedramcore_bankmachine5_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine5_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine5_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if (litedramcore_bankmachine5_source_source_payload_we) begin
+ litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if (litedramcore_bankmachine5_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if (litedramcore_bankmachine5_source_source_payload_we) begin
+ litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if (litedramcore_bankmachine5_source_source_payload_we) begin
+ litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if (litedramcore_bankmachine5_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine5_twtpcon_ready) begin
+ litedramcore_bankmachine5_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_row_open <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_row_close <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ litedramcore_bankmachine5_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine5_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine5_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+assign litedramcore_bankmachine6_sink_valid = litedramcore_bankmachine6_req_valid;
+assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_sink_ready;
+assign litedramcore_bankmachine6_sink_payload_we = litedramcore_bankmachine6_req_we;
+assign litedramcore_bankmachine6_sink_payload_addr = litedramcore_bankmachine6_req_addr;
+assign litedramcore_bankmachine6_sink_sink_valid = litedramcore_bankmachine6_source_valid;
+assign litedramcore_bankmachine6_source_ready = litedramcore_bankmachine6_sink_sink_ready;
+assign litedramcore_bankmachine6_sink_sink_first = litedramcore_bankmachine6_source_first;
+assign litedramcore_bankmachine6_sink_sink_last = litedramcore_bankmachine6_source_last;
+assign litedramcore_bankmachine6_sink_sink_payload_we = litedramcore_bankmachine6_source_payload_we;
+assign litedramcore_bankmachine6_sink_sink_payload_addr = litedramcore_bankmachine6_source_payload_addr;
+assign litedramcore_bankmachine6_source_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid);
+assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_source_valid | litedramcore_bankmachine6_source_source_valid);
+assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_source_source_payload_addr[21:7]);
assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
always @(*) begin
- litedramcore_bankmachine6_cmd_payload_a <= 15'd0;
- if (litedramcore_bankmachine6_row_col_n_addr_sel) begin
- litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7];
- end else begin
- litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine6_cmd_payload_a <= 15'd0;
+ if (litedramcore_bankmachine6_row_col_n_addr_sel) begin
+ litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_source_source_payload_addr[21:7];
+ end else begin
+ litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write);
assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
always @(*) begin
- litedramcore_bankmachine6_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine6_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7])) begin
- litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine6_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | litedramcore_bankmachine6_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re);
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine6_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine6_next_state <= 4'd0;
- litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- if (litedramcore_bankmachine6_cmd_ready) begin
- litedramcore_bankmachine6_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- if (litedramcore_bankmachine6_cmd_ready) begin
- litedramcore_bankmachine6_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine6_refresh_req)) begin
- litedramcore_bankmachine6_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine6_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine6_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine6_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine6_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- litedramcore_bankmachine6_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin
- litedramcore_bankmachine6_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine6_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine6_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_row_open <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_row_close <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- litedramcore_bankmachine6_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine6_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine6_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- litedramcore_bankmachine6_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine6_twtpcon_ready) begin
- litedramcore_bankmachine6_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine7_req_valid;
-assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine7_req_we;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine7_req_addr;
-assign litedramcore_bankmachine7_cmd_buffer_sink_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine7_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine7_cmd_buffer_sink_first = litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine7_cmd_buffer_sink_last = litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine7_cmd_buffer_sink_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine7_cmd_buffer_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid);
-assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine7_cmd_buffer_source_valid);
-assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]);
+ litedramcore_bankmachine6_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine6_source_valid & litedramcore_bankmachine6_source_source_valid)) begin
+ if ((litedramcore_bankmachine6_source_payload_addr[21:7] != litedramcore_bankmachine6_source_source_payload_addr[21:7])) begin
+ litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine6_syncfifo6_din = {litedramcore_bankmachine6_fifo_in_last, litedramcore_bankmachine6_fifo_in_first, litedramcore_bankmachine6_fifo_in_payload_addr, litedramcore_bankmachine6_fifo_in_payload_we};
+assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout;
+assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout;
+assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout;
+assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout;
+assign litedramcore_bankmachine6_sink_ready = litedramcore_bankmachine6_syncfifo6_writable;
+assign litedramcore_bankmachine6_syncfifo6_we = litedramcore_bankmachine6_sink_valid;
+assign litedramcore_bankmachine6_fifo_in_first = litedramcore_bankmachine6_sink_first;
+assign litedramcore_bankmachine6_fifo_in_last = litedramcore_bankmachine6_sink_last;
+assign litedramcore_bankmachine6_fifo_in_payload_we = litedramcore_bankmachine6_sink_payload_we;
+assign litedramcore_bankmachine6_fifo_in_payload_addr = litedramcore_bankmachine6_sink_payload_addr;
+assign litedramcore_bankmachine6_source_valid = litedramcore_bankmachine6_syncfifo6_readable;
+assign litedramcore_bankmachine6_source_first = litedramcore_bankmachine6_fifo_out_first;
+assign litedramcore_bankmachine6_source_last = litedramcore_bankmachine6_fifo_out_last;
+assign litedramcore_bankmachine6_source_payload_we = litedramcore_bankmachine6_fifo_out_payload_we;
+assign litedramcore_bankmachine6_source_payload_addr = litedramcore_bankmachine6_fifo_out_payload_addr;
+assign litedramcore_bankmachine6_syncfifo6_re = litedramcore_bankmachine6_source_ready;
+always @(*) begin
+ litedramcore_bankmachine6_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine6_replace) begin
+ litedramcore_bankmachine6_wrport_adr <= (litedramcore_bankmachine6_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine6_wrport_adr <= litedramcore_bankmachine6_produce;
+ end
+end
+assign litedramcore_bankmachine6_wrport_dat_w = litedramcore_bankmachine6_syncfifo6_din;
+assign litedramcore_bankmachine6_wrport_we = (litedramcore_bankmachine6_syncfifo6_we & (litedramcore_bankmachine6_syncfifo6_writable | litedramcore_bankmachine6_replace));
+assign litedramcore_bankmachine6_do_read = (litedramcore_bankmachine6_syncfifo6_readable & litedramcore_bankmachine6_syncfifo6_re);
+assign litedramcore_bankmachine6_rdport_adr = litedramcore_bankmachine6_consume;
+assign litedramcore_bankmachine6_syncfifo6_dout = litedramcore_bankmachine6_rdport_dat_r;
+assign litedramcore_bankmachine6_syncfifo6_writable = (litedramcore_bankmachine6_level != 5'd16);
+assign litedramcore_bankmachine6_syncfifo6_readable = (litedramcore_bankmachine6_level != 1'd0);
+assign litedramcore_bankmachine6_pipe_valid_sink_ready = ((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready);
+assign litedramcore_bankmachine6_pipe_valid_sink_valid = litedramcore_bankmachine6_sink_sink_valid;
+assign litedramcore_bankmachine6_sink_sink_ready = litedramcore_bankmachine6_pipe_valid_sink_ready;
+assign litedramcore_bankmachine6_pipe_valid_sink_first = litedramcore_bankmachine6_sink_sink_first;
+assign litedramcore_bankmachine6_pipe_valid_sink_last = litedramcore_bankmachine6_sink_sink_last;
+assign litedramcore_bankmachine6_pipe_valid_sink_payload_we = litedramcore_bankmachine6_sink_sink_payload_we;
+assign litedramcore_bankmachine6_pipe_valid_sink_payload_addr = litedramcore_bankmachine6_sink_sink_payload_addr;
+assign litedramcore_bankmachine6_source_source_valid = litedramcore_bankmachine6_pipe_valid_source_valid;
+assign litedramcore_bankmachine6_pipe_valid_source_ready = litedramcore_bankmachine6_source_source_ready;
+assign litedramcore_bankmachine6_source_source_first = litedramcore_bankmachine6_pipe_valid_source_first;
+assign litedramcore_bankmachine6_source_source_last = litedramcore_bankmachine6_pipe_valid_source_last;
+assign litedramcore_bankmachine6_source_source_payload_we = litedramcore_bankmachine6_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine6_source_source_payload_addr = litedramcore_bankmachine6_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine6_next_state <= 4'd0;
+ litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ if (litedramcore_bankmachine6_cmd_ready) begin
+ litedramcore_bankmachine6_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ if (litedramcore_bankmachine6_cmd_ready) begin
+ litedramcore_bankmachine6_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine6_refresh_req)) begin
+ litedramcore_bankmachine6_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine6_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine6_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine6_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine6_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ litedramcore_bankmachine6_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin
+ litedramcore_bankmachine6_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine6_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine6_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if (litedramcore_bankmachine6_source_source_payload_we) begin
+ litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if (litedramcore_bankmachine6_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine6_twtpcon_ready) begin
+ litedramcore_bankmachine6_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_row_open <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ litedramcore_bankmachine6_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_row_close <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ litedramcore_bankmachine6_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine6_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine6_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if (litedramcore_bankmachine6_source_source_payload_we) begin
+ litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if (litedramcore_bankmachine6_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if (litedramcore_bankmachine6_source_source_payload_we) begin
+ litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+assign litedramcore_bankmachine7_sink_valid = litedramcore_bankmachine7_req_valid;
+assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_sink_ready;
+assign litedramcore_bankmachine7_sink_payload_we = litedramcore_bankmachine7_req_we;
+assign litedramcore_bankmachine7_sink_payload_addr = litedramcore_bankmachine7_req_addr;
+assign litedramcore_bankmachine7_sink_sink_valid = litedramcore_bankmachine7_source_valid;
+assign litedramcore_bankmachine7_source_ready = litedramcore_bankmachine7_sink_sink_ready;
+assign litedramcore_bankmachine7_sink_sink_first = litedramcore_bankmachine7_source_first;
+assign litedramcore_bankmachine7_sink_sink_last = litedramcore_bankmachine7_source_last;
+assign litedramcore_bankmachine7_sink_sink_payload_we = litedramcore_bankmachine7_source_payload_we;
+assign litedramcore_bankmachine7_sink_sink_payload_addr = litedramcore_bankmachine7_source_payload_addr;
+assign litedramcore_bankmachine7_source_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid);
+assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_source_valid | litedramcore_bankmachine7_source_source_valid);
+assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_source_source_payload_addr[21:7]);
assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
always @(*) begin
- litedramcore_bankmachine7_cmd_payload_a <= 15'd0;
- if (litedramcore_bankmachine7_row_col_n_addr_sel) begin
- litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7];
- end else begin
- litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine7_cmd_payload_a <= 15'd0;
+ if (litedramcore_bankmachine7_row_col_n_addr_sel) begin
+ litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_source_source_payload_addr[21:7];
+ end else begin
+ litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write);
assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
always @(*) begin
- litedramcore_bankmachine7_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine7_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7])) begin
- litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine7_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | litedramcore_bankmachine7_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re);
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine7_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine7_next_state <= 4'd0;
- litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- if (litedramcore_bankmachine7_cmd_ready) begin
- litedramcore_bankmachine7_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- if (litedramcore_bankmachine7_cmd_ready) begin
- litedramcore_bankmachine7_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine7_refresh_req)) begin
- litedramcore_bankmachine7_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine7_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine7_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine7_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine7_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- litedramcore_bankmachine7_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin
- litedramcore_bankmachine7_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine7_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine7_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_row_open <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_row_close <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- litedramcore_bankmachine7_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine7_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine7_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine7_twtpcon_ready) begin
- litedramcore_bankmachine7_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- litedramcore_bankmachine7_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
+ litedramcore_bankmachine7_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine7_source_valid & litedramcore_bankmachine7_source_source_valid)) begin
+ if ((litedramcore_bankmachine7_source_payload_addr[21:7] != litedramcore_bankmachine7_source_source_payload_addr[21:7])) begin
+ litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine7_syncfifo7_din = {litedramcore_bankmachine7_fifo_in_last, litedramcore_bankmachine7_fifo_in_first, litedramcore_bankmachine7_fifo_in_payload_addr, litedramcore_bankmachine7_fifo_in_payload_we};
+assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout;
+assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout;
+assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout;
+assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout;
+assign litedramcore_bankmachine7_sink_ready = litedramcore_bankmachine7_syncfifo7_writable;
+assign litedramcore_bankmachine7_syncfifo7_we = litedramcore_bankmachine7_sink_valid;
+assign litedramcore_bankmachine7_fifo_in_first = litedramcore_bankmachine7_sink_first;
+assign litedramcore_bankmachine7_fifo_in_last = litedramcore_bankmachine7_sink_last;
+assign litedramcore_bankmachine7_fifo_in_payload_we = litedramcore_bankmachine7_sink_payload_we;
+assign litedramcore_bankmachine7_fifo_in_payload_addr = litedramcore_bankmachine7_sink_payload_addr;
+assign litedramcore_bankmachine7_source_valid = litedramcore_bankmachine7_syncfifo7_readable;
+assign litedramcore_bankmachine7_source_first = litedramcore_bankmachine7_fifo_out_first;
+assign litedramcore_bankmachine7_source_last = litedramcore_bankmachine7_fifo_out_last;
+assign litedramcore_bankmachine7_source_payload_we = litedramcore_bankmachine7_fifo_out_payload_we;
+assign litedramcore_bankmachine7_source_payload_addr = litedramcore_bankmachine7_fifo_out_payload_addr;
+assign litedramcore_bankmachine7_syncfifo7_re = litedramcore_bankmachine7_source_ready;
+always @(*) begin
+ litedramcore_bankmachine7_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine7_replace) begin
+ litedramcore_bankmachine7_wrport_adr <= (litedramcore_bankmachine7_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine7_wrport_adr <= litedramcore_bankmachine7_produce;
+ end
+end
+assign litedramcore_bankmachine7_wrport_dat_w = litedramcore_bankmachine7_syncfifo7_din;
+assign litedramcore_bankmachine7_wrport_we = (litedramcore_bankmachine7_syncfifo7_we & (litedramcore_bankmachine7_syncfifo7_writable | litedramcore_bankmachine7_replace));
+assign litedramcore_bankmachine7_do_read = (litedramcore_bankmachine7_syncfifo7_readable & litedramcore_bankmachine7_syncfifo7_re);
+assign litedramcore_bankmachine7_rdport_adr = litedramcore_bankmachine7_consume;
+assign litedramcore_bankmachine7_syncfifo7_dout = litedramcore_bankmachine7_rdport_dat_r;
+assign litedramcore_bankmachine7_syncfifo7_writable = (litedramcore_bankmachine7_level != 5'd16);
+assign litedramcore_bankmachine7_syncfifo7_readable = (litedramcore_bankmachine7_level != 1'd0);
+assign litedramcore_bankmachine7_pipe_valid_sink_ready = ((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready);
+assign litedramcore_bankmachine7_pipe_valid_sink_valid = litedramcore_bankmachine7_sink_sink_valid;
+assign litedramcore_bankmachine7_sink_sink_ready = litedramcore_bankmachine7_pipe_valid_sink_ready;
+assign litedramcore_bankmachine7_pipe_valid_sink_first = litedramcore_bankmachine7_sink_sink_first;
+assign litedramcore_bankmachine7_pipe_valid_sink_last = litedramcore_bankmachine7_sink_sink_last;
+assign litedramcore_bankmachine7_pipe_valid_sink_payload_we = litedramcore_bankmachine7_sink_sink_payload_we;
+assign litedramcore_bankmachine7_pipe_valid_sink_payload_addr = litedramcore_bankmachine7_sink_sink_payload_addr;
+assign litedramcore_bankmachine7_source_source_valid = litedramcore_bankmachine7_pipe_valid_source_valid;
+assign litedramcore_bankmachine7_pipe_valid_source_ready = litedramcore_bankmachine7_source_source_ready;
+assign litedramcore_bankmachine7_source_source_first = litedramcore_bankmachine7_pipe_valid_source_first;
+assign litedramcore_bankmachine7_source_source_last = litedramcore_bankmachine7_pipe_valid_source_last;
+assign litedramcore_bankmachine7_source_source_payload_we = litedramcore_bankmachine7_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine7_source_source_payload_addr = litedramcore_bankmachine7_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine7_next_state <= 4'd0;
+ litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ if (litedramcore_bankmachine7_cmd_ready) begin
+ litedramcore_bankmachine7_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ if (litedramcore_bankmachine7_cmd_ready) begin
+ litedramcore_bankmachine7_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine7_refresh_req)) begin
+ litedramcore_bankmachine7_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine7_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine7_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine7_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine7_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ litedramcore_bankmachine7_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin
+ litedramcore_bankmachine7_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine7_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine7_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_row_open <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ litedramcore_bankmachine7_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_row_close <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ litedramcore_bankmachine7_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine7_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine7_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if (litedramcore_bankmachine7_source_source_payload_we) begin
+ litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if (litedramcore_bankmachine7_source_source_payload_we) begin
+ litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if (litedramcore_bankmachine7_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if (litedramcore_bankmachine7_source_source_payload_we) begin
+ litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if (litedramcore_bankmachine7_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine7_twtpcon_ready) begin
+ litedramcore_bankmachine7_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
end
assign litedramcore_rdcmdphase = (a7ddrphy_rdphase_storage - 1'd1);
assign litedramcore_wrcmdphase = (a7ddrphy_wrphase_storage - 1'd1);
assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
always @(*) begin
- litedramcore_choose_cmd_valids <= 8'd0;
- litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids <= 8'd0;
+ litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
end
assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids;
assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0;
assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4;
assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5;
always @(*) begin
- litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
- if (litedramcore_choose_cmd_cmd_valid) begin
- litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0;
- end
+ litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
+ if (litedramcore_choose_cmd_cmd_valid) begin
+ litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0;
+ end
end
always @(*) begin
- litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
- if (litedramcore_choose_cmd_cmd_valid) begin
- litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1;
- end
+ litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
+ if (litedramcore_choose_cmd_cmd_valid) begin
+ litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1;
+ end
end
always @(*) begin
- litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
- if (litedramcore_choose_cmd_cmd_valid) begin
- litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2;
- end
+ litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
+ if (litedramcore_choose_cmd_cmd_valid) begin
+ litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2;
+ end
end
always @(*) begin
- litedramcore_bankmachine0_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin
- litedramcore_bankmachine0_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin
- litedramcore_bankmachine0_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine0_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin
+ litedramcore_bankmachine0_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin
+ litedramcore_bankmachine0_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_bankmachine1_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin
- litedramcore_bankmachine1_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin
- litedramcore_bankmachine1_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine1_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin
+ litedramcore_bankmachine1_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin
+ litedramcore_bankmachine1_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_bankmachine2_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin
- litedramcore_bankmachine2_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin
- litedramcore_bankmachine2_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine2_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin
+ litedramcore_bankmachine2_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin
+ litedramcore_bankmachine2_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_bankmachine3_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin
- litedramcore_bankmachine3_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin
- litedramcore_bankmachine3_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine3_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin
+ litedramcore_bankmachine3_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin
+ litedramcore_bankmachine3_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_bankmachine4_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin
- litedramcore_bankmachine4_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin
- litedramcore_bankmachine4_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine4_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin
+ litedramcore_bankmachine4_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin
+ litedramcore_bankmachine4_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_bankmachine5_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin
- litedramcore_bankmachine5_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin
- litedramcore_bankmachine5_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine5_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin
+ litedramcore_bankmachine5_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin
+ litedramcore_bankmachine5_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_bankmachine6_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin
- litedramcore_bankmachine6_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin
- litedramcore_bankmachine6_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine6_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin
+ litedramcore_bankmachine6_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin
+ litedramcore_bankmachine6_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_bankmachine7_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin
- litedramcore_bankmachine7_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin
- litedramcore_bankmachine7_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine7_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin
+ litedramcore_bankmachine7_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin
+ litedramcore_bankmachine7_cmd_ready <= 1'd1;
+ end
end
assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid));
always @(*) begin
- litedramcore_choose_req_valids <= 8'd0;
- litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids <= 8'd0;
+ litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
end
assign litedramcore_choose_req_request = litedramcore_choose_req_valids;
assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6;
assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10;
assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11;
always @(*) begin
- litedramcore_choose_req_cmd_payload_cas <= 1'd0;
- if (litedramcore_choose_req_cmd_valid) begin
- litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3;
- end
+ litedramcore_choose_req_cmd_payload_cas <= 1'd0;
+ if (litedramcore_choose_req_cmd_valid) begin
+ litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3;
+ end
end
always @(*) begin
- litedramcore_choose_req_cmd_payload_ras <= 1'd0;
- if (litedramcore_choose_req_cmd_valid) begin
- litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4;
- end
+ litedramcore_choose_req_cmd_payload_ras <= 1'd0;
+ if (litedramcore_choose_req_cmd_valid) begin
+ litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4;
+ end
end
always @(*) begin
- litedramcore_choose_req_cmd_payload_we <= 1'd0;
- if (litedramcore_choose_req_cmd_valid) begin
- litedramcore_choose_req_cmd_payload_we <= t_array_muxed5;
- end
+ litedramcore_choose_req_cmd_payload_we <= 1'd0;
+ if (litedramcore_choose_req_cmd_valid) begin
+ litedramcore_choose_req_cmd_payload_we <= t_array_muxed5;
+ end
end
assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid));
assign litedramcore_dfi_p0_reset_n = 1'd1;
assign litedramcore_dfi_p3_odt = {1{litedramcore_steerer7}};
assign litedramcore_tfawcon_count = ((((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]) + litedramcore_tfawcon_window[3]) + litedramcore_tfawcon_window[4]);
always @(*) begin
- litedramcore_multiplexer_next_state <= 4'd0;
- litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- if (litedramcore_read_available) begin
- if (((~litedramcore_write_available) | litedramcore_max_time1)) begin
- litedramcore_multiplexer_next_state <= 2'd3;
- end
- end
- if (litedramcore_go_to_refresh) begin
- litedramcore_multiplexer_next_state <= 2'd2;
- end
- end
- 2'd2: begin
- if (litedramcore_cmd_last) begin
- litedramcore_multiplexer_next_state <= 1'd0;
- end
- end
- 2'd3: begin
- if (litedramcore_twtrcon_ready) begin
- litedramcore_multiplexer_next_state <= 1'd0;
- end
- end
- 3'd4: begin
- litedramcore_multiplexer_next_state <= 3'd5;
- end
- 3'd5: begin
- litedramcore_multiplexer_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_multiplexer_next_state <= 3'd7;
- end
- 3'd7: begin
- litedramcore_multiplexer_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_multiplexer_next_state <= 4'd9;
- end
- 4'd9: begin
- litedramcore_multiplexer_next_state <= 4'd10;
- end
- 4'd10: begin
- litedramcore_multiplexer_next_state <= 1'd1;
- end
- default: begin
- if (litedramcore_write_available) begin
- if (((~litedramcore_read_available) | litedramcore_max_time0)) begin
- litedramcore_multiplexer_next_state <= 3'd4;
- end
- end
- if (litedramcore_go_to_refresh) begin
- litedramcore_multiplexer_next_state <= 2'd2;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_choose_req_want_writes <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- litedramcore_choose_req_want_writes <= 1'd1;
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_choose_req_cmd_ready <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- if (1'd0) begin
- litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
- end else begin
- litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- if (1'd0) begin
- litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
- end else begin
- litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_en1 <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- litedramcore_en1 <= 1'd1;
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_steerer_sel0 <= 2'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- litedramcore_steerer_sel0 <= 1'd0;
- if ((a7ddrphy_wrphase_storage == 1'd0)) begin
- litedramcore_steerer_sel0 <= 2'd2;
- end
- if ((litedramcore_wrcmdphase == 1'd0)) begin
- litedramcore_steerer_sel0 <= 1'd1;
- end
- end
- 2'd2: begin
- litedramcore_steerer_sel0 <= 2'd3;
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- litedramcore_steerer_sel0 <= 1'd0;
- if ((a7ddrphy_rdphase_storage == 1'd0)) begin
- litedramcore_steerer_sel0 <= 2'd2;
- end
- if ((litedramcore_rdcmdphase == 1'd0)) begin
- litedramcore_steerer_sel0 <= 1'd1;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_cmd_ready <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- end
- 2'd2: begin
- litedramcore_cmd_ready <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_steerer_sel1 <= 2'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- litedramcore_steerer_sel1 <= 1'd0;
- if ((a7ddrphy_wrphase_storage == 1'd1)) begin
- litedramcore_steerer_sel1 <= 2'd2;
- end
- if ((litedramcore_wrcmdphase == 1'd1)) begin
- litedramcore_steerer_sel1 <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- litedramcore_steerer_sel1 <= 1'd0;
- if ((a7ddrphy_rdphase_storage == 1'd1)) begin
- litedramcore_steerer_sel1 <= 2'd2;
- end
- if ((litedramcore_rdcmdphase == 1'd1)) begin
- litedramcore_steerer_sel1 <= 1'd1;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_steerer_sel2 <= 2'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- litedramcore_steerer_sel2 <= 1'd0;
- if ((a7ddrphy_wrphase_storage == 2'd2)) begin
- litedramcore_steerer_sel2 <= 2'd2;
- end
- if ((litedramcore_wrcmdphase == 2'd2)) begin
- litedramcore_steerer_sel2 <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- litedramcore_steerer_sel2 <= 1'd0;
- if ((a7ddrphy_rdphase_storage == 2'd2)) begin
- litedramcore_steerer_sel2 <= 2'd2;
- end
- if ((litedramcore_rdcmdphase == 2'd2)) begin
- litedramcore_steerer_sel2 <= 1'd1;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_choose_cmd_want_activates <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_en0 <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- litedramcore_en0 <= 1'd1;
- end
- endcase
-end
-always @(*) begin
- litedramcore_steerer_sel3 <= 2'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- litedramcore_steerer_sel3 <= 1'd0;
- if ((a7ddrphy_wrphase_storage == 2'd3)) begin
- litedramcore_steerer_sel3 <= 2'd2;
- end
- if ((litedramcore_wrcmdphase == 2'd3)) begin
- litedramcore_steerer_sel3 <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- litedramcore_steerer_sel3 <= 1'd0;
- if ((a7ddrphy_rdphase_storage == 2'd3)) begin
- litedramcore_steerer_sel3 <= 2'd2;
- end
- if ((litedramcore_rdcmdphase == 2'd3)) begin
- litedramcore_steerer_sel3 <= 1'd1;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_choose_cmd_cmd_ready <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_choose_req_want_reads <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- litedramcore_choose_req_want_reads <= 1'd1;
- end
- endcase
+ litedramcore_multiplexer_next_state <= 4'd0;
+ litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ if (litedramcore_read_available) begin
+ if (((~litedramcore_write_available) | litedramcore_max_time1)) begin
+ litedramcore_multiplexer_next_state <= 2'd3;
+ end
+ end
+ if (litedramcore_go_to_refresh) begin
+ litedramcore_multiplexer_next_state <= 2'd2;
+ end
+ end
+ 2'd2: begin
+ if (litedramcore_cmd_last) begin
+ litedramcore_multiplexer_next_state <= 1'd0;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_twtrcon_ready) begin
+ litedramcore_multiplexer_next_state <= 1'd0;
+ end
+ end
+ 3'd4: begin
+ litedramcore_multiplexer_next_state <= 3'd5;
+ end
+ 3'd5: begin
+ litedramcore_multiplexer_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_multiplexer_next_state <= 3'd7;
+ end
+ 3'd7: begin
+ litedramcore_multiplexer_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_multiplexer_next_state <= 4'd9;
+ end
+ 4'd9: begin
+ litedramcore_multiplexer_next_state <= 4'd10;
+ end
+ 4'd10: begin
+ litedramcore_multiplexer_next_state <= 1'd1;
+ end
+ default: begin
+ if (litedramcore_write_available) begin
+ if (((~litedramcore_read_available) | litedramcore_max_time0)) begin
+ litedramcore_multiplexer_next_state <= 3'd4;
+ end
+ end
+ if (litedramcore_go_to_refresh) begin
+ litedramcore_multiplexer_next_state <= 2'd2;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_choose_req_want_writes <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ litedramcore_choose_req_want_writes <= 1'd1;
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_steerer_sel3 <= 2'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ litedramcore_steerer_sel3 <= 1'd0;
+ if ((a7ddrphy_wrphase_storage == 2'd3)) begin
+ litedramcore_steerer_sel3 <= 2'd2;
+ end
+ if ((litedramcore_wrcmdphase == 2'd3)) begin
+ litedramcore_steerer_sel3 <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ litedramcore_steerer_sel3 <= 1'd0;
+ if ((a7ddrphy_rdphase_storage == 2'd3)) begin
+ litedramcore_steerer_sel3 <= 2'd2;
+ end
+ if ((litedramcore_rdcmdphase == 2'd3)) begin
+ litedramcore_steerer_sel3 <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_choose_req_cmd_ready <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ if (1'd0) begin
+ litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+ end else begin
+ litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ if (1'd0) begin
+ litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+ end else begin
+ litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_en1 <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ litedramcore_en1 <= 1'd1;
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_steerer_sel0 <= 2'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ litedramcore_steerer_sel0 <= 1'd0;
+ if ((a7ddrphy_wrphase_storage == 1'd0)) begin
+ litedramcore_steerer_sel0 <= 2'd2;
+ end
+ if ((litedramcore_wrcmdphase == 1'd0)) begin
+ litedramcore_steerer_sel0 <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ litedramcore_steerer_sel0 <= 2'd3;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ litedramcore_steerer_sel0 <= 1'd0;
+ if ((a7ddrphy_rdphase_storage == 1'd0)) begin
+ litedramcore_steerer_sel0 <= 2'd2;
+ end
+ if ((litedramcore_rdcmdphase == 1'd0)) begin
+ litedramcore_steerer_sel0 <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_cmd_ready <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ litedramcore_cmd_ready <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_steerer_sel1 <= 2'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ litedramcore_steerer_sel1 <= 1'd0;
+ if ((a7ddrphy_wrphase_storage == 1'd1)) begin
+ litedramcore_steerer_sel1 <= 2'd2;
+ end
+ if ((litedramcore_wrcmdphase == 1'd1)) begin
+ litedramcore_steerer_sel1 <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ litedramcore_steerer_sel1 <= 1'd0;
+ if ((a7ddrphy_rdphase_storage == 1'd1)) begin
+ litedramcore_steerer_sel1 <= 2'd2;
+ end
+ if ((litedramcore_rdcmdphase == 1'd1)) begin
+ litedramcore_steerer_sel1 <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_steerer_sel2 <= 2'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ litedramcore_steerer_sel2 <= 1'd0;
+ if ((a7ddrphy_wrphase_storage == 2'd2)) begin
+ litedramcore_steerer_sel2 <= 2'd2;
+ end
+ if ((litedramcore_wrcmdphase == 2'd2)) begin
+ litedramcore_steerer_sel2 <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ litedramcore_steerer_sel2 <= 1'd0;
+ if ((a7ddrphy_rdphase_storage == 2'd2)) begin
+ litedramcore_steerer_sel2 <= 2'd2;
+ end
+ if ((litedramcore_rdcmdphase == 2'd2)) begin
+ litedramcore_steerer_sel2 <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_choose_cmd_want_activates <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ if (1'd0) begin
+ end else begin
+ litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ if (1'd0) begin
+ end else begin
+ litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_en0 <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ litedramcore_en0 <= 1'd1;
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_choose_cmd_cmd_ready <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ if (1'd0) begin
+ end else begin
+ litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ if (1'd0) begin
+ end else begin
+ litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_choose_req_want_reads <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ litedramcore_choose_req_want_reads <= 1'd1;
+ end
+ endcase
end
assign litedramcore_roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
assign litedramcore_roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock));
assign user_port_wdata_ready = litedramcore_new_master_wdata_ready1;
assign user_port_rdata_valid = litedramcore_new_master_rdata_valid8;
always @(*) begin
- litedramcore_interface_wdata <= 128'd0;
- case ({litedramcore_new_master_wdata_ready1})
- 1'd1: begin
- litedramcore_interface_wdata <= user_port_wdata_payload_data;
- end
- default: begin
- litedramcore_interface_wdata <= 1'd0;
- end
- endcase
-end
-always @(*) begin
- litedramcore_interface_wdata_we <= 16'd0;
- case ({litedramcore_new_master_wdata_ready1})
- 1'd1: begin
- litedramcore_interface_wdata_we <= user_port_wdata_payload_we;
- end
- default: begin
- litedramcore_interface_wdata_we <= 1'd0;
- end
- endcase
+ litedramcore_interface_wdata <= 128'd0;
+ case ({litedramcore_new_master_wdata_ready1})
+ 1'd1: begin
+ litedramcore_interface_wdata <= user_port_wdata_payload_data;
+ end
+ default: begin
+ litedramcore_interface_wdata <= 1'd0;
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_interface_wdata_we <= 16'd0;
+ case ({litedramcore_new_master_wdata_ready1})
+ 1'd1: begin
+ litedramcore_interface_wdata_we <= user_port_wdata_payload_we;
+ end
+ default: begin
+ litedramcore_interface_wdata_we <= 1'd0;
+ end
+ endcase
end
assign user_port_rdata_payload_data = litedramcore_interface_rdata;
assign litedramcore_roundrobin0_grant = 1'd0;
assign litedramcore_roundrobin6_grant = 1'd0;
assign litedramcore_roundrobin7_grant = 1'd0;
always @(*) begin
- litedramcore_next_state <= 2'd0;
- litedramcore_next_state <= litedramcore_state;
- case (litedramcore_state)
- 1'd1: begin
- litedramcore_next_state <= 2'd2;
- end
- 2'd2: begin
- litedramcore_next_state <= 1'd0;
- end
- default: begin
- if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_next_state <= 1'd1;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_dat_w_next_value0 <= 32'd0;
- case (litedramcore_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- default: begin
- litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w;
- end
- endcase
-end
-always @(*) begin
- litedramcore_dat_w_next_value_ce0 <= 1'd0;
- case (litedramcore_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- default: begin
- litedramcore_dat_w_next_value_ce0 <= 1'd1;
- end
- endcase
-end
-always @(*) begin
- litedramcore_adr_next_value1 <= 14'd0;
- case (litedramcore_state)
- 1'd1: begin
- litedramcore_adr_next_value1 <= 1'd0;
- end
- 2'd2: begin
- end
- default: begin
- if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_adr_next_value1 <= litedramcore_wishbone_adr;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_adr_next_value_ce1 <= 1'd0;
- case (litedramcore_state)
- 1'd1: begin
- litedramcore_adr_next_value_ce1 <= 1'd1;
- end
- 2'd2: begin
- end
- default: begin
- if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_adr_next_value_ce1 <= 1'd1;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_wishbone_dat_r <= 32'd0;
- case (litedramcore_state)
- 1'd1: begin
- end
- 2'd2: begin
- litedramcore_wishbone_dat_r <= litedramcore_dat_r;
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_we_next_value2 <= 1'd0;
- case (litedramcore_state)
- 1'd1: begin
- litedramcore_we_next_value2 <= 1'd0;
- end
- 2'd2: begin
- end
- default: begin
- if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_we_next_value_ce2 <= 1'd0;
- case (litedramcore_state)
- 1'd1: begin
- litedramcore_we_next_value_ce2 <= 1'd1;
- end
- 2'd2: begin
- end
- default: begin
- if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_we_next_value_ce2 <= 1'd1;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_wishbone_ack <= 1'd0;
- case (litedramcore_state)
- 1'd1: begin
- end
- 2'd2: begin
- litedramcore_wishbone_ack <= 1'd1;
- end
- default: begin
- end
- endcase
+ litedramcore_next_state <= 2'd0;
+ litedramcore_next_state <= litedramcore_state;
+ case (litedramcore_state)
+ 1'd1: begin
+ litedramcore_next_state <= 2'd2;
+ end
+ 2'd2: begin
+ litedramcore_next_state <= 1'd0;
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_next_state <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_dat_w_next_value0 <= 32'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ default: begin
+ litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w;
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_dat_w_next_value_ce0 <= 1'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ default: begin
+ litedramcore_dat_w_next_value_ce0 <= 1'd1;
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_adr_next_value1 <= 14'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ litedramcore_adr_next_value1 <= 1'd0;
+ end
+ 2'd2: begin
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_adr_next_value1 <= litedramcore_wishbone_adr;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_adr_next_value_ce1 <= 1'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ litedramcore_adr_next_value_ce1 <= 1'd1;
+ end
+ 2'd2: begin
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_adr_next_value_ce1 <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_wishbone_dat_r <= 32'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ litedramcore_wishbone_dat_r <= litedramcore_dat_r;
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_we_next_value2 <= 1'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ litedramcore_we_next_value2 <= 1'd0;
+ end
+ 2'd2: begin
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_we_next_value_ce2 <= 1'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ litedramcore_we_next_value_ce2 <= 1'd1;
+ end
+ 2'd2: begin
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_we_next_value_ce2 <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_wishbone_ack <= 1'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ litedramcore_wishbone_ack <= 1'd1;
+ end
+ default: begin
+ end
+ endcase
end
assign litedramcore_wishbone_adr = wb_bus_adr;
assign litedramcore_wishbone_dat_w = wb_bus_dat_w;
assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0);
assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
always @(*) begin
- csrbank0_init_done0_re <= 1'd0;
- if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
- csrbank0_init_done0_re <= interface0_bank_bus_we;
- end
+ csrbank0_init_done0_re <= 1'd0;
+ if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank0_init_done0_re <= interface0_bank_bus_we;
+ end
end
always @(*) begin
- csrbank0_init_done0_we <= 1'd0;
- if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
- csrbank0_init_done0_we <= (~interface0_bank_bus_we);
- end
+ csrbank0_init_done0_we <= 1'd0;
+ if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank0_init_done0_we <= (~interface0_bank_bus_we);
+ end
end
assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0];
always @(*) begin
- csrbank0_init_error0_we <= 1'd0;
- if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
- csrbank0_init_error0_we <= (~interface0_bank_bus_we);
- end
+ csrbank0_init_error0_we <= 1'd0;
+ if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
+ csrbank0_init_error0_we <= (~interface0_bank_bus_we);
+ end
end
always @(*) begin
- csrbank0_init_error0_re <= 1'd0;
- if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
- csrbank0_init_error0_re <= interface0_bank_bus_we;
- end
+ csrbank0_init_error0_re <= 1'd0;
+ if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
+ csrbank0_init_error0_re <= interface0_bank_bus_we;
+ end
end
assign csrbank0_init_done0_w = init_done_storage;
assign csrbank0_init_error0_w = init_error_storage;
assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1);
assign csrbank1_rst0_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- csrbank1_rst0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
- csrbank1_rst0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_rst0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank1_rst0_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- csrbank1_rst0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
- csrbank1_rst0_re <= interface1_bank_bus_we;
- end
+ csrbank1_rst0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank1_rst0_re <= interface1_bank_bus_we;
+ end
end
assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0];
always @(*) begin
- csrbank1_dly_sel0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
- csrbank1_dly_sel0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_dly_sel0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
+ csrbank1_dly_sel0_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- csrbank1_dly_sel0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
- csrbank1_dly_sel0_re <= interface1_bank_bus_we;
- end
+ csrbank1_dly_sel0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
+ csrbank1_dly_sel0_re <= interface1_bank_bus_we;
+ end
end
assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0];
always @(*) begin
- csrbank1_half_sys8x_taps0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
- csrbank1_half_sys8x_taps0_re <= interface1_bank_bus_we;
- end
+ csrbank1_half_sys8x_taps0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
+ csrbank1_half_sys8x_taps0_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- csrbank1_half_sys8x_taps0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
- csrbank1_half_sys8x_taps0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_half_sys8x_taps0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
+ csrbank1_half_sys8x_taps0_we <= (~interface1_bank_bus_we);
+ end
end
assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- csrbank1_wlevel_en0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
- csrbank1_wlevel_en0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_wlevel_en0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
+ csrbank1_wlevel_en0_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- csrbank1_wlevel_en0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
- csrbank1_wlevel_en0_re <= interface1_bank_bus_we;
- end
+ csrbank1_wlevel_en0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
+ csrbank1_wlevel_en0_re <= interface1_bank_bus_we;
+ end
end
assign a7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- a7ddrphy_wlevel_strobe_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
- a7ddrphy_wlevel_strobe_re <= interface1_bank_bus_we;
- end
+ a7ddrphy_wlevel_strobe_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
+ a7ddrphy_wlevel_strobe_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- a7ddrphy_wlevel_strobe_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
- a7ddrphy_wlevel_strobe_we <= (~interface1_bank_bus_we);
- end
+ a7ddrphy_wlevel_strobe_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
+ a7ddrphy_wlevel_strobe_we <= (~interface1_bank_bus_we);
+ end
end
assign a7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- a7ddrphy_rdly_dq_rst_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
- a7ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we;
- end
+ a7ddrphy_rdly_dq_rst_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
+ a7ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- a7ddrphy_rdly_dq_rst_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
- a7ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we);
- end
+ a7ddrphy_rdly_dq_rst_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
+ a7ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we);
+ end
end
assign a7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- a7ddrphy_rdly_dq_inc_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
- a7ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we;
- end
+ a7ddrphy_rdly_dq_inc_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
+ a7ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- a7ddrphy_rdly_dq_inc_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
- a7ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we);
- end
+ a7ddrphy_rdly_dq_inc_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
+ a7ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we);
+ end
end
assign a7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
- a7ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
- end
+ a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
+ a7ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
- a7ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
- end
+ a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
+ a7ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
+ end
end
assign a7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- a7ddrphy_rdly_dq_bitslip_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
- a7ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we);
- end
+ a7ddrphy_rdly_dq_bitslip_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
+ a7ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- a7ddrphy_rdly_dq_bitslip_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
- a7ddrphy_rdly_dq_bitslip_re <= interface1_bank_bus_we;
- end
+ a7ddrphy_rdly_dq_bitslip_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
+ a7ddrphy_rdly_dq_bitslip_re <= interface1_bank_bus_we;
+ end
end
assign a7ddrphy_wdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
- a7ddrphy_wdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
- end
+ a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
+ a7ddrphy_wdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
- a7ddrphy_wdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
- end
+ a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
+ a7ddrphy_wdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
+ end
end
assign a7ddrphy_wdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- a7ddrphy_wdly_dq_bitslip_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
- a7ddrphy_wdly_dq_bitslip_we <= (~interface1_bank_bus_we);
- end
+ a7ddrphy_wdly_dq_bitslip_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
+ a7ddrphy_wdly_dq_bitslip_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- a7ddrphy_wdly_dq_bitslip_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
- a7ddrphy_wdly_dq_bitslip_re <= interface1_bank_bus_we;
- end
+ a7ddrphy_wdly_dq_bitslip_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
+ a7ddrphy_wdly_dq_bitslip_re <= interface1_bank_bus_we;
+ end
end
assign csrbank1_rdphase0_r = interface1_bank_bus_dat_w[1:0];
always @(*) begin
- csrbank1_rdphase0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
- csrbank1_rdphase0_re <= interface1_bank_bus_we;
- end
+ csrbank1_rdphase0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
+ csrbank1_rdphase0_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- csrbank1_rdphase0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
- csrbank1_rdphase0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_rdphase0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
+ csrbank1_rdphase0_we <= (~interface1_bank_bus_we);
+ end
end
assign csrbank1_wrphase0_r = interface1_bank_bus_dat_w[1:0];
always @(*) begin
- csrbank1_wrphase0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
- csrbank1_wrphase0_re <= interface1_bank_bus_we;
- end
+ csrbank1_wrphase0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
+ csrbank1_wrphase0_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- csrbank1_wrphase0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
- csrbank1_wrphase0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_wrphase0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
+ csrbank1_wrphase0_we <= (~interface1_bank_bus_we);
+ end
end
assign csrbank1_rst0_w = a7ddrphy_rst_storage;
assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0];
assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2);
assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0];
always @(*) begin
- csrbank2_dfii_control0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
- csrbank2_dfii_control0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_control0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank2_dfii_control0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_control0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
- csrbank2_dfii_control0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_control0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank2_dfii_control0_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0];
always @(*) begin
- csrbank2_dfii_pi0_command0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
- csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi0_command0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
+ csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi0_command0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
- csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi0_command0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
+ csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we);
+ end
end
assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0];
always @(*) begin
- litedramcore_phaseinjector0_command_issue_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
- litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we);
- end
+ litedramcore_phaseinjector0_command_issue_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
+ litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- litedramcore_phaseinjector0_command_issue_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
- litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we;
- end
+ litedramcore_phaseinjector0_command_issue_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
+ litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[14:0];
always @(*) begin
- csrbank2_dfii_pi0_address0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
- csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi0_address0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
+ csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi0_address0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
- csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi0_address0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
+ csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0];
always @(*) begin
- csrbank2_dfii_pi0_baddress0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
- csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi0_baddress0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
+ csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi0_baddress0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
- csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi0_baddress0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
+ csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
- csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
+ csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
- csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
+ csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi0_rddata_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi0_rddata_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
- csrbank2_dfii_pi0_rddata_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi0_rddata_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
+ csrbank2_dfii_pi0_rddata_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi0_rddata_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
- csrbank2_dfii_pi0_rddata_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi0_rddata_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
+ csrbank2_dfii_pi0_rddata_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0];
always @(*) begin
- csrbank2_dfii_pi1_command0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
- csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi1_command0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
+ csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi1_command0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
- csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi1_command0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
+ csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we);
+ end
end
assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0];
always @(*) begin
- litedramcore_phaseinjector1_command_issue_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
- litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we);
- end
+ litedramcore_phaseinjector1_command_issue_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
+ litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- litedramcore_phaseinjector1_command_issue_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
- litedramcore_phaseinjector1_command_issue_re <= interface2_bank_bus_we;
- end
+ litedramcore_phaseinjector1_command_issue_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
+ litedramcore_phaseinjector1_command_issue_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[14:0];
always @(*) begin
- csrbank2_dfii_pi1_address0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
- csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi1_address0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
+ csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi1_address0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
- csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi1_address0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
+ csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0];
always @(*) begin
- csrbank2_dfii_pi1_baddress0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
- csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi1_baddress0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
+ csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi1_baddress0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
- csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi1_baddress0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
+ csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
- csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
+ csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
- csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
+ csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi1_rddata_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi1_rddata_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
- csrbank2_dfii_pi1_rddata_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi1_rddata_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
+ csrbank2_dfii_pi1_rddata_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi1_rddata_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
- csrbank2_dfii_pi1_rddata_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi1_rddata_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
+ csrbank2_dfii_pi1_rddata_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0];
always @(*) begin
- csrbank2_dfii_pi2_command0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
- csrbank2_dfii_pi2_command0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi2_command0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
+ csrbank2_dfii_pi2_command0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi2_command0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
- csrbank2_dfii_pi2_command0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi2_command0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
+ csrbank2_dfii_pi2_command0_re <= interface2_bank_bus_we;
+ end
end
assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0];
always @(*) begin
- litedramcore_phaseinjector2_command_issue_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
- litedramcore_phaseinjector2_command_issue_re <= interface2_bank_bus_we;
- end
+ litedramcore_phaseinjector2_command_issue_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
+ litedramcore_phaseinjector2_command_issue_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- litedramcore_phaseinjector2_command_issue_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
- litedramcore_phaseinjector2_command_issue_we <= (~interface2_bank_bus_we);
- end
+ litedramcore_phaseinjector2_command_issue_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
+ litedramcore_phaseinjector2_command_issue_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[14:0];
always @(*) begin
- csrbank2_dfii_pi2_address0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
- csrbank2_dfii_pi2_address0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi2_address0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
+ csrbank2_dfii_pi2_address0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi2_address0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
- csrbank2_dfii_pi2_address0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi2_address0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
+ csrbank2_dfii_pi2_address0_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0];
always @(*) begin
- csrbank2_dfii_pi2_baddress0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
- csrbank2_dfii_pi2_baddress0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi2_baddress0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
+ csrbank2_dfii_pi2_baddress0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi2_baddress0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
- csrbank2_dfii_pi2_baddress0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi2_baddress0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
+ csrbank2_dfii_pi2_baddress0_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
- csrbank2_dfii_pi2_wrdata0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
+ csrbank2_dfii_pi2_wrdata0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
- csrbank2_dfii_pi2_wrdata0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
+ csrbank2_dfii_pi2_wrdata0_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi2_rddata_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi2_rddata_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
- csrbank2_dfii_pi2_rddata_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi2_rddata_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
+ csrbank2_dfii_pi2_rddata_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi2_rddata_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
- csrbank2_dfii_pi2_rddata_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi2_rddata_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
+ csrbank2_dfii_pi2_rddata_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0];
always @(*) begin
- csrbank2_dfii_pi3_command0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin
- csrbank2_dfii_pi3_command0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi3_command0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin
+ csrbank2_dfii_pi3_command0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi3_command0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin
- csrbank2_dfii_pi3_command0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi3_command0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin
+ csrbank2_dfii_pi3_command0_re <= interface2_bank_bus_we;
+ end
end
assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0];
always @(*) begin
- litedramcore_phaseinjector3_command_issue_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin
- litedramcore_phaseinjector3_command_issue_we <= (~interface2_bank_bus_we);
- end
+ litedramcore_phaseinjector3_command_issue_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin
+ litedramcore_phaseinjector3_command_issue_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- litedramcore_phaseinjector3_command_issue_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin
- litedramcore_phaseinjector3_command_issue_re <= interface2_bank_bus_we;
- end
+ litedramcore_phaseinjector3_command_issue_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin
+ litedramcore_phaseinjector3_command_issue_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[14:0];
always @(*) begin
- csrbank2_dfii_pi3_address0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin
- csrbank2_dfii_pi3_address0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi3_address0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin
+ csrbank2_dfii_pi3_address0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi3_address0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin
- csrbank2_dfii_pi3_address0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi3_address0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin
+ csrbank2_dfii_pi3_address0_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0];
always @(*) begin
- csrbank2_dfii_pi3_baddress0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin
- csrbank2_dfii_pi3_baddress0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi3_baddress0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin
+ csrbank2_dfii_pi3_baddress0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi3_baddress0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin
- csrbank2_dfii_pi3_baddress0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi3_baddress0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin
+ csrbank2_dfii_pi3_baddress0_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin
- csrbank2_dfii_pi3_wrdata0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin
+ csrbank2_dfii_pi3_wrdata0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi3_wrdata0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin
- csrbank2_dfii_pi3_wrdata0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi3_wrdata0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin
+ csrbank2_dfii_pi3_wrdata0_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi3_rddata_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi3_rddata_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin
- csrbank2_dfii_pi3_rddata_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi3_rddata_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin
+ csrbank2_dfii_pi3_rddata_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi3_rddata_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin
- csrbank2_dfii_pi3_rddata_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi3_rddata_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin
+ csrbank2_dfii_pi3_rddata_we <= (~interface2_bank_bus_we);
+ end
end
assign litedramcore_sel = litedramcore_storage[0];
assign litedramcore_cke = litedramcore_storage[1];
assign interface2_bank_bus_dat_w = csr_interconnect_dat_w;
assign csr_interconnect_dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r);
always @(*) begin
- rhs_array_muxed0 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0];
- end
- 1'd1: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1];
- end
- 2'd2: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2];
- end
- 2'd3: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3];
- end
- 3'd4: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4];
- end
- 3'd5: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5];
- end
- 3'd6: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6];
- end
- default: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7];
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed1 <= 15'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a;
- end
- 1'd1: begin
- rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a;
- end
- 2'd2: begin
- rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a;
- end
- 2'd3: begin
- rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a;
- end
- 3'd4: begin
- rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a;
- end
- 3'd5: begin
- rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a;
- end
- 3'd6: begin
- rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a;
- end
- default: begin
- rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed2 <= 3'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba;
- end
- 1'd1: begin
- rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba;
- end
- 2'd2: begin
- rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba;
- end
- 2'd3: begin
- rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba;
- end
- 3'd4: begin
- rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba;
- end
- 3'd5: begin
- rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba;
- end
- 3'd6: begin
- rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba;
- end
- default: begin
- rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed3 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read;
- end
- 1'd1: begin
- rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read;
- end
- 2'd2: begin
- rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read;
- end
- 2'd3: begin
- rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read;
- end
- 3'd4: begin
- rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read;
- end
- 3'd5: begin
- rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read;
- end
- 3'd6: begin
- rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read;
- end
- default: begin
- rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed4 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write;
- end
- 1'd1: begin
- rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write;
- end
- 2'd2: begin
- rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write;
- end
- 2'd3: begin
- rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write;
- end
- 3'd4: begin
- rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write;
- end
- 3'd5: begin
- rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write;
- end
- 3'd6: begin
- rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write;
- end
- default: begin
- rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed5 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
- end
- 1'd1: begin
- rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
- end
- 2'd2: begin
- rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
- end
- 2'd3: begin
- rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
- end
- 3'd4: begin
- rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
- end
- 3'd5: begin
- rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
- end
- 3'd6: begin
- rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
- end
- default: begin
- rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
- end
- endcase
-end
-always @(*) begin
- t_array_muxed0 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas;
- end
- 1'd1: begin
- t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas;
- end
- 2'd2: begin
- t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas;
- end
- 2'd3: begin
- t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas;
- end
- 3'd4: begin
- t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas;
- end
- 3'd5: begin
- t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas;
- end
- 3'd6: begin
- t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas;
- end
- default: begin
- t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas;
- end
- endcase
-end
-always @(*) begin
- t_array_muxed1 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras;
- end
- 1'd1: begin
- t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras;
- end
- 2'd2: begin
- t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras;
- end
- 2'd3: begin
- t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras;
- end
- 3'd4: begin
- t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras;
- end
- 3'd5: begin
- t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras;
- end
- 3'd6: begin
- t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras;
- end
- default: begin
- t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras;
- end
- endcase
-end
-always @(*) begin
- t_array_muxed2 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we;
- end
- 1'd1: begin
- t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we;
- end
- 2'd2: begin
- t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we;
- end
- 2'd3: begin
- t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we;
- end
- 3'd4: begin
- t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we;
- end
- 3'd5: begin
- t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we;
- end
- 3'd6: begin
- t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we;
- end
- default: begin
- t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed6 <= 1'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[0];
- end
- 1'd1: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[1];
- end
- 2'd2: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[2];
- end
- 2'd3: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[3];
- end
- 3'd4: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[4];
- end
- 3'd5: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[5];
- end
- 3'd6: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[6];
- end
- default: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[7];
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed7 <= 15'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a;
- end
- 1'd1: begin
- rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a;
- end
- 2'd2: begin
- rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a;
- end
- 2'd3: begin
- rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a;
- end
- 3'd4: begin
- rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a;
- end
- 3'd5: begin
- rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a;
- end
- 3'd6: begin
- rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a;
- end
- default: begin
- rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed8 <= 3'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba;
- end
- 1'd1: begin
- rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba;
- end
- 2'd2: begin
- rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba;
- end
- 2'd3: begin
- rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba;
- end
- 3'd4: begin
- rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba;
- end
- 3'd5: begin
- rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba;
- end
- 3'd6: begin
- rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba;
- end
- default: begin
- rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed9 <= 1'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read;
- end
- 1'd1: begin
- rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read;
- end
- 2'd2: begin
- rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read;
- end
- 2'd3: begin
- rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read;
- end
- 3'd4: begin
- rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read;
- end
- 3'd5: begin
- rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read;
- end
- 3'd6: begin
- rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read;
- end
- default: begin
- rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed10 <= 1'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write;
- end
- 1'd1: begin
- rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write;
- end
- 2'd2: begin
- rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write;
- end
- 2'd3: begin
- rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write;
- end
- 3'd4: begin
- rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write;
- end
- 3'd5: begin
- rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write;
- end
- 3'd6: begin
- rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write;
- end
- default: begin
- rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed11 <= 1'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
- end
- 1'd1: begin
- rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
- end
- 2'd2: begin
- rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
- end
- 2'd3: begin
- rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
- end
- 3'd4: begin
- rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
- end
- 3'd5: begin
- rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
- end
- 3'd6: begin
- rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
- end
- default: begin
- rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
- end
- endcase
-end
-always @(*) begin
- t_array_muxed3 <= 1'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas;
- end
- 1'd1: begin
- t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas;
- end
- 2'd2: begin
- t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas;
- end
- 2'd3: begin
- t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas;
- end
- 3'd4: begin
- t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas;
- end
- 3'd5: begin
- t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas;
- end
- 3'd6: begin
- t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas;
- end
- default: begin
- t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas;
- end
- endcase
-end
-always @(*) begin
- t_array_muxed4 <= 1'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras;
- end
- 1'd1: begin
- t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras;
- end
- 2'd2: begin
- t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras;
- end
- 2'd3: begin
- t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras;
- end
- 3'd4: begin
- t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras;
- end
- 3'd5: begin
- t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras;
- end
- 3'd6: begin
- t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras;
- end
- default: begin
- t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras;
- end
- endcase
-end
-always @(*) begin
- t_array_muxed5 <= 1'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we;
- end
- 1'd1: begin
- t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we;
- end
- 2'd2: begin
- t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we;
- end
- 2'd3: begin
- t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we;
- end
- 3'd4: begin
- t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we;
- end
- 3'd5: begin
- t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we;
- end
- 3'd6: begin
- t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we;
- end
- default: begin
- t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed12 <= 22'd0;
- case (litedramcore_roundrobin0_grant)
- default: begin
- rhs_array_muxed12 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed13 <= 1'd0;
- case (litedramcore_roundrobin0_grant)
- default: begin
- rhs_array_muxed13 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed14 <= 1'd0;
- case (litedramcore_roundrobin0_grant)
- default: begin
- rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed15 <= 22'd0;
- case (litedramcore_roundrobin1_grant)
- default: begin
- rhs_array_muxed15 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed16 <= 1'd0;
- case (litedramcore_roundrobin1_grant)
- default: begin
- rhs_array_muxed16 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed17 <= 1'd0;
- case (litedramcore_roundrobin1_grant)
- default: begin
- rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed18 <= 22'd0;
- case (litedramcore_roundrobin2_grant)
- default: begin
- rhs_array_muxed18 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed19 <= 1'd0;
- case (litedramcore_roundrobin2_grant)
- default: begin
- rhs_array_muxed19 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed20 <= 1'd0;
- case (litedramcore_roundrobin2_grant)
- default: begin
- rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed21 <= 22'd0;
- case (litedramcore_roundrobin3_grant)
- default: begin
- rhs_array_muxed21 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed22 <= 1'd0;
- case (litedramcore_roundrobin3_grant)
- default: begin
- rhs_array_muxed22 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed23 <= 1'd0;
- case (litedramcore_roundrobin3_grant)
- default: begin
- rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
+ rhs_array_muxed0 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0];
+ end
+ 1'd1: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1];
+ end
+ 2'd2: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2];
+ end
+ 2'd3: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3];
+ end
+ 3'd4: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4];
+ end
+ 3'd5: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5];
+ end
+ 3'd6: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6];
+ end
+ default: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7];
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed1 <= 15'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a;
+ end
+ 1'd1: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a;
+ end
+ 2'd2: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a;
+ end
+ 2'd3: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a;
+ end
+ 3'd4: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a;
+ end
+ 3'd5: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a;
+ end
+ 3'd6: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a;
+ end
+ default: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed2 <= 3'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba;
+ end
+ 1'd1: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba;
+ end
+ 2'd2: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba;
+ end
+ 2'd3: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba;
+ end
+ 3'd4: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba;
+ end
+ 3'd5: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba;
+ end
+ 3'd6: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba;
+ end
+ default: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed3 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read;
+ end
+ 1'd1: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read;
+ end
+ 2'd2: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read;
+ end
+ 2'd3: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read;
+ end
+ 3'd4: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read;
+ end
+ 3'd5: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read;
+ end
+ 3'd6: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read;
+ end
+ default: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed4 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write;
+ end
+ 1'd1: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write;
+ end
+ 2'd2: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write;
+ end
+ 2'd3: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write;
+ end
+ 3'd4: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write;
+ end
+ 3'd5: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write;
+ end
+ 3'd6: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write;
+ end
+ default: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed5 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
+ end
+ 1'd1: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
+ end
+ 2'd2: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
+ end
+ 2'd3: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
+ end
+ 3'd4: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
+ end
+ 3'd5: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
+ end
+ 3'd6: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
+ end
+ default: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed0 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas;
+ end
+ 1'd1: begin
+ t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas;
+ end
+ 2'd2: begin
+ t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas;
+ end
+ 2'd3: begin
+ t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas;
+ end
+ 3'd4: begin
+ t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas;
+ end
+ 3'd5: begin
+ t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas;
+ end
+ 3'd6: begin
+ t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas;
+ end
+ default: begin
+ t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed1 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras;
+ end
+ 1'd1: begin
+ t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras;
+ end
+ 2'd2: begin
+ t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras;
+ end
+ 2'd3: begin
+ t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras;
+ end
+ 3'd4: begin
+ t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras;
+ end
+ 3'd5: begin
+ t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras;
+ end
+ 3'd6: begin
+ t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras;
+ end
+ default: begin
+ t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed2 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we;
+ end
+ 1'd1: begin
+ t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we;
+ end
+ 2'd2: begin
+ t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we;
+ end
+ 2'd3: begin
+ t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we;
+ end
+ 3'd4: begin
+ t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we;
+ end
+ 3'd5: begin
+ t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we;
+ end
+ 3'd6: begin
+ t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we;
+ end
+ default: begin
+ t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed6 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[0];
+ end
+ 1'd1: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[1];
+ end
+ 2'd2: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[2];
+ end
+ 2'd3: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[3];
+ end
+ 3'd4: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[4];
+ end
+ 3'd5: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[5];
+ end
+ 3'd6: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[6];
+ end
+ default: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[7];
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed7 <= 15'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a;
+ end
+ 1'd1: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a;
+ end
+ 2'd2: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a;
+ end
+ 2'd3: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a;
+ end
+ 3'd4: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a;
+ end
+ 3'd5: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a;
+ end
+ 3'd6: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a;
+ end
+ default: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed8 <= 3'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba;
+ end
+ 1'd1: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba;
+ end
+ 2'd2: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba;
+ end
+ 2'd3: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba;
+ end
+ 3'd4: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba;
+ end
+ 3'd5: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba;
+ end
+ 3'd6: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba;
+ end
+ default: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed9 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read;
+ end
+ 1'd1: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read;
+ end
+ 2'd2: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read;
+ end
+ 2'd3: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read;
+ end
+ 3'd4: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read;
+ end
+ 3'd5: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read;
+ end
+ 3'd6: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read;
+ end
+ default: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed10 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write;
+ end
+ 1'd1: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write;
+ end
+ 2'd2: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write;
+ end
+ 2'd3: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write;
+ end
+ 3'd4: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write;
+ end
+ 3'd5: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write;
+ end
+ 3'd6: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write;
+ end
+ default: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed11 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
+ end
+ 1'd1: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
+ end
+ 2'd2: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
+ end
+ 2'd3: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
+ end
+ 3'd4: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
+ end
+ 3'd5: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
+ end
+ 3'd6: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
+ end
+ default: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed3 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas;
+ end
+ 1'd1: begin
+ t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas;
+ end
+ 2'd2: begin
+ t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas;
+ end
+ 2'd3: begin
+ t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas;
+ end
+ 3'd4: begin
+ t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas;
+ end
+ 3'd5: begin
+ t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas;
+ end
+ 3'd6: begin
+ t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas;
+ end
+ default: begin
+ t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed4 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras;
+ end
+ 1'd1: begin
+ t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras;
+ end
+ 2'd2: begin
+ t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras;
+ end
+ 2'd3: begin
+ t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras;
+ end
+ 3'd4: begin
+ t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras;
+ end
+ 3'd5: begin
+ t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras;
+ end
+ 3'd6: begin
+ t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras;
+ end
+ default: begin
+ t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed5 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we;
+ end
+ 1'd1: begin
+ t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we;
+ end
+ 2'd2: begin
+ t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we;
+ end
+ 2'd3: begin
+ t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we;
+ end
+ 3'd4: begin
+ t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we;
+ end
+ 3'd5: begin
+ t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we;
+ end
+ 3'd6: begin
+ t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we;
+ end
+ default: begin
+ t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed12 <= 22'd0;
+ case (litedramcore_roundrobin0_grant)
+ default: begin
+ rhs_array_muxed12 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed13 <= 1'd0;
+ case (litedramcore_roundrobin0_grant)
+ default: begin
+ rhs_array_muxed13 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed14 <= 1'd0;
+ case (litedramcore_roundrobin0_grant)
+ default: begin
+ rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed15 <= 22'd0;
+ case (litedramcore_roundrobin1_grant)
+ default: begin
+ rhs_array_muxed15 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed16 <= 1'd0;
+ case (litedramcore_roundrobin1_grant)
+ default: begin
+ rhs_array_muxed16 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed17 <= 1'd0;
+ case (litedramcore_roundrobin1_grant)
+ default: begin
+ rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed18 <= 22'd0;
+ case (litedramcore_roundrobin2_grant)
+ default: begin
+ rhs_array_muxed18 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed19 <= 1'd0;
+ case (litedramcore_roundrobin2_grant)
+ default: begin
+ rhs_array_muxed19 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed20 <= 1'd0;
+ case (litedramcore_roundrobin2_grant)
+ default: begin
+ rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed21 <= 22'd0;
+ case (litedramcore_roundrobin3_grant)
+ default: begin
+ rhs_array_muxed21 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed22 <= 1'd0;
+ case (litedramcore_roundrobin3_grant)
+ default: begin
+ rhs_array_muxed22 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed23 <= 1'd0;
+ case (litedramcore_roundrobin3_grant)
+ default: begin
+ rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
end
always @(*) begin
- rhs_array_muxed24 <= 22'd0;
- case (litedramcore_roundrobin4_grant)
- default: begin
- rhs_array_muxed24 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed25 <= 1'd0;
- case (litedramcore_roundrobin4_grant)
- default: begin
- rhs_array_muxed25 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed26 <= 1'd0;
- case (litedramcore_roundrobin4_grant)
- default: begin
- rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed27 <= 22'd0;
- case (litedramcore_roundrobin5_grant)
- default: begin
- rhs_array_muxed27 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed28 <= 1'd0;
- case (litedramcore_roundrobin5_grant)
- default: begin
- rhs_array_muxed28 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed29 <= 1'd0;
- case (litedramcore_roundrobin5_grant)
- default: begin
- rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed30 <= 22'd0;
- case (litedramcore_roundrobin6_grant)
- default: begin
- rhs_array_muxed30 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed31 <= 1'd0;
- case (litedramcore_roundrobin6_grant)
- default: begin
- rhs_array_muxed31 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed32 <= 1'd0;
- case (litedramcore_roundrobin6_grant)
- default: begin
- rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed33 <= 22'd0;
- case (litedramcore_roundrobin7_grant)
- default: begin
- rhs_array_muxed33 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed34 <= 1'd0;
- case (litedramcore_roundrobin7_grant)
- default: begin
- rhs_array_muxed34 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed35 <= 1'd0;
- case (litedramcore_roundrobin7_grant)
- default: begin
- rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- array_muxed0 <= 3'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed0 <= litedramcore_nop_ba[2:0];
- end
- 1'd1: begin
- array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
- end
- 2'd2: begin
- array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0];
- end
- default: begin
- array_muxed0 <= litedramcore_cmd_payload_ba[2:0];
- end
- endcase
-end
-always @(*) begin
- array_muxed1 <= 15'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed1 <= litedramcore_nop_a;
- end
- 1'd1: begin
- array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a;
- end
- 2'd2: begin
- array_muxed1 <= litedramcore_choose_req_cmd_payload_a;
- end
- default: begin
- array_muxed1 <= litedramcore_cmd_payload_a;
- end
- endcase
-end
-always @(*) begin
- array_muxed2 <= 1'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed2 <= 1'd0;
- end
- 1'd1: begin
- array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
- end
- 2'd2: begin
- array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
- end
- default: begin
- array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
- end
- endcase
-end
-always @(*) begin
- array_muxed3 <= 1'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed3 <= 1'd0;
- end
- 1'd1: begin
- array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
- end
- 2'd2: begin
- array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
- end
- default: begin
- array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
- end
- endcase
-end
-always @(*) begin
- array_muxed4 <= 1'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed4 <= 1'd0;
- end
- 1'd1: begin
- array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
- end
- 2'd2: begin
- array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
- end
- default: begin
- array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
- end
- endcase
-end
-always @(*) begin
- array_muxed5 <= 1'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed5 <= 1'd0;
- end
- 1'd1: begin
- array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
- end
- 2'd2: begin
- array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
- end
- default: begin
- array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
- end
- endcase
-end
-always @(*) begin
- array_muxed6 <= 1'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed6 <= 1'd0;
- end
- 1'd1: begin
- array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
- end
- 2'd2: begin
- array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
- end
- default: begin
- array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
- end
- endcase
-end
-always @(*) begin
- array_muxed7 <= 3'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed7 <= litedramcore_nop_ba[2:0];
- end
- 1'd1: begin
- array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
- end
- 2'd2: begin
- array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0];
- end
- default: begin
- array_muxed7 <= litedramcore_cmd_payload_ba[2:0];
- end
- endcase
-end
-always @(*) begin
- array_muxed8 <= 15'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed8 <= litedramcore_nop_a;
- end
- 1'd1: begin
- array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a;
- end
- 2'd2: begin
- array_muxed8 <= litedramcore_choose_req_cmd_payload_a;
- end
- default: begin
- array_muxed8 <= litedramcore_cmd_payload_a;
- end
- endcase
-end
-always @(*) begin
- array_muxed9 <= 1'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed9 <= 1'd0;
- end
- 1'd1: begin
- array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
- end
- 2'd2: begin
- array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
- end
- default: begin
- array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
- end
- endcase
-end
-always @(*) begin
- array_muxed10 <= 1'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed10 <= 1'd0;
- end
- 1'd1: begin
- array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
- end
- 2'd2: begin
- array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
- end
- default: begin
- array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
- end
- endcase
-end
-always @(*) begin
- array_muxed11 <= 1'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed11 <= 1'd0;
- end
- 1'd1: begin
- array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
- end
- 2'd2: begin
- array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
- end
- default: begin
- array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
- end
- endcase
-end
-always @(*) begin
- array_muxed12 <= 1'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed12 <= 1'd0;
- end
- 1'd1: begin
- array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
- end
- 2'd2: begin
- array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
- end
- default: begin
- array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
- end
- endcase
-end
-always @(*) begin
- array_muxed13 <= 1'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed13 <= 1'd0;
- end
- 1'd1: begin
- array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
- end
- 2'd2: begin
- array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
- end
- default: begin
- array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
- end
- endcase
-end
-always @(*) begin
- array_muxed14 <= 3'd0;
- case (litedramcore_steerer_sel2)
- 1'd0: begin
- array_muxed14 <= litedramcore_nop_ba[2:0];
- end
- 1'd1: begin
- array_muxed14 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
- end
- 2'd2: begin
- array_muxed14 <= litedramcore_choose_req_cmd_payload_ba[2:0];
- end
- default: begin
- array_muxed14 <= litedramcore_cmd_payload_ba[2:0];
- end
- endcase
-end
-always @(*) begin
- array_muxed15 <= 15'd0;
- case (litedramcore_steerer_sel2)
- 1'd0: begin
- array_muxed15 <= litedramcore_nop_a;
- end
- 1'd1: begin
- array_muxed15 <= litedramcore_choose_cmd_cmd_payload_a;
- end
- 2'd2: begin
- array_muxed15 <= litedramcore_choose_req_cmd_payload_a;
- end
- default: begin
- array_muxed15 <= litedramcore_cmd_payload_a;
- end
- endcase
-end
-always @(*) begin
- array_muxed16 <= 1'd0;
- case (litedramcore_steerer_sel2)
- 1'd0: begin
- array_muxed16 <= 1'd0;
- end
- 1'd1: begin
- array_muxed16 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
- end
- 2'd2: begin
- array_muxed16 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
- end
- default: begin
- array_muxed16 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
- end
- endcase
-end
-always @(*) begin
- array_muxed17 <= 1'd0;
- case (litedramcore_steerer_sel2)
- 1'd0: begin
- array_muxed17 <= 1'd0;
- end
- 1'd1: begin
- array_muxed17 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
- end
- 2'd2: begin
- array_muxed17 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
- end
- default: begin
- array_muxed17 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
- end
- endcase
-end
-always @(*) begin
- array_muxed18 <= 1'd0;
- case (litedramcore_steerer_sel2)
- 1'd0: begin
- array_muxed18 <= 1'd0;
- end
- 1'd1: begin
- array_muxed18 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
- end
- 2'd2: begin
- array_muxed18 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
- end
- default: begin
- array_muxed18 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
- end
- endcase
-end
-always @(*) begin
- array_muxed19 <= 1'd0;
- case (litedramcore_steerer_sel2)
- 1'd0: begin
- array_muxed19 <= 1'd0;
- end
- 1'd1: begin
- array_muxed19 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
- end
- 2'd2: begin
- array_muxed19 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
- end
- default: begin
- array_muxed19 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
- end
- endcase
-end
-always @(*) begin
- array_muxed20 <= 1'd0;
- case (litedramcore_steerer_sel2)
- 1'd0: begin
- array_muxed20 <= 1'd0;
- end
- 1'd1: begin
- array_muxed20 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
- end
- 2'd2: begin
- array_muxed20 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
- end
- default: begin
- array_muxed20 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
- end
- endcase
-end
-always @(*) begin
- array_muxed21 <= 3'd0;
- case (litedramcore_steerer_sel3)
- 1'd0: begin
- array_muxed21 <= litedramcore_nop_ba[2:0];
- end
- 1'd1: begin
- array_muxed21 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
- end
- 2'd2: begin
- array_muxed21 <= litedramcore_choose_req_cmd_payload_ba[2:0];
- end
- default: begin
- array_muxed21 <= litedramcore_cmd_payload_ba[2:0];
- end
- endcase
-end
-always @(*) begin
- array_muxed22 <= 15'd0;
- case (litedramcore_steerer_sel3)
- 1'd0: begin
- array_muxed22 <= litedramcore_nop_a;
- end
- 1'd1: begin
- array_muxed22 <= litedramcore_choose_cmd_cmd_payload_a;
- end
- 2'd2: begin
- array_muxed22 <= litedramcore_choose_req_cmd_payload_a;
- end
- default: begin
- array_muxed22 <= litedramcore_cmd_payload_a;
- end
- endcase
-end
-always @(*) begin
- array_muxed23 <= 1'd0;
- case (litedramcore_steerer_sel3)
- 1'd0: begin
- array_muxed23 <= 1'd0;
- end
- 1'd1: begin
- array_muxed23 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
- end
- 2'd2: begin
- array_muxed23 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
- end
- default: begin
- array_muxed23 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
- end
- endcase
-end
-always @(*) begin
- array_muxed24 <= 1'd0;
- case (litedramcore_steerer_sel3)
- 1'd0: begin
- array_muxed24 <= 1'd0;
- end
- 1'd1: begin
- array_muxed24 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
- end
- 2'd2: begin
- array_muxed24 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
- end
- default: begin
- array_muxed24 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
- end
- endcase
-end
-always @(*) begin
- array_muxed25 <= 1'd0;
- case (litedramcore_steerer_sel3)
- 1'd0: begin
- array_muxed25 <= 1'd0;
- end
- 1'd1: begin
- array_muxed25 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
- end
- 2'd2: begin
- array_muxed25 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
- end
- default: begin
- array_muxed25 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
- end
- endcase
-end
-always @(*) begin
- array_muxed26 <= 1'd0;
- case (litedramcore_steerer_sel3)
- 1'd0: begin
- array_muxed26 <= 1'd0;
- end
- 1'd1: begin
- array_muxed26 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
- end
- 2'd2: begin
- array_muxed26 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
- end
- default: begin
- array_muxed26 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
- end
- endcase
-end
-always @(*) begin
- array_muxed27 <= 1'd0;
- case (litedramcore_steerer_sel3)
- 1'd0: begin
- array_muxed27 <= 1'd0;
- end
- 1'd1: begin
- array_muxed27 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
- end
- 2'd2: begin
- array_muxed27 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
- end
- default: begin
- array_muxed27 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
- end
- endcase
+ rhs_array_muxed24 <= 22'd0;
+ case (litedramcore_roundrobin4_grant)
+ default: begin
+ rhs_array_muxed24 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed25 <= 1'd0;
+ case (litedramcore_roundrobin4_grant)
+ default: begin
+ rhs_array_muxed25 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed26 <= 1'd0;
+ case (litedramcore_roundrobin4_grant)
+ default: begin
+ rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed27 <= 22'd0;
+ case (litedramcore_roundrobin5_grant)
+ default: begin
+ rhs_array_muxed27 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed28 <= 1'd0;
+ case (litedramcore_roundrobin5_grant)
+ default: begin
+ rhs_array_muxed28 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed29 <= 1'd0;
+ case (litedramcore_roundrobin5_grant)
+ default: begin
+ rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed30 <= 22'd0;
+ case (litedramcore_roundrobin6_grant)
+ default: begin
+ rhs_array_muxed30 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed31 <= 1'd0;
+ case (litedramcore_roundrobin6_grant)
+ default: begin
+ rhs_array_muxed31 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed32 <= 1'd0;
+ case (litedramcore_roundrobin6_grant)
+ default: begin
+ rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed33 <= 22'd0;
+ case (litedramcore_roundrobin7_grant)
+ default: begin
+ rhs_array_muxed33 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed34 <= 1'd0;
+ case (litedramcore_roundrobin7_grant)
+ default: begin
+ rhs_array_muxed34 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed35 <= 1'd0;
+ case (litedramcore_roundrobin7_grant)
+ default: begin
+ rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed0 <= 3'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed0 <= litedramcore_nop_ba[2:0];
+ end
+ 1'd1: begin
+ array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+ end
+ 2'd2: begin
+ array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+ end
+ default: begin
+ array_muxed0 <= litedramcore_cmd_payload_ba[2:0];
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed1 <= 15'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed1 <= litedramcore_nop_a;
+ end
+ 1'd1: begin
+ array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a;
+ end
+ 2'd2: begin
+ array_muxed1 <= litedramcore_choose_req_cmd_payload_a;
+ end
+ default: begin
+ array_muxed1 <= litedramcore_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed2 <= 1'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed2 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+ end
+ 2'd2: begin
+ array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+ end
+ default: begin
+ array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed3 <= 1'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed3 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+ end
+ 2'd2: begin
+ array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+ end
+ default: begin
+ array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed4 <= 1'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed4 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+ end
+ 2'd2: begin
+ array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+ end
+ default: begin
+ array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed5 <= 1'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed5 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+ end
+ 2'd2: begin
+ array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+ end
+ default: begin
+ array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed6 <= 1'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed6 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+ end
+ 2'd2: begin
+ array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+ end
+ default: begin
+ array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed7 <= 3'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed7 <= litedramcore_nop_ba[2:0];
+ end
+ 1'd1: begin
+ array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+ end
+ 2'd2: begin
+ array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+ end
+ default: begin
+ array_muxed7 <= litedramcore_cmd_payload_ba[2:0];
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed8 <= 15'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed8 <= litedramcore_nop_a;
+ end
+ 1'd1: begin
+ array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a;
+ end
+ 2'd2: begin
+ array_muxed8 <= litedramcore_choose_req_cmd_payload_a;
+ end
+ default: begin
+ array_muxed8 <= litedramcore_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed9 <= 1'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed9 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+ end
+ 2'd2: begin
+ array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+ end
+ default: begin
+ array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed10 <= 1'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed10 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+ end
+ 2'd2: begin
+ array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+ end
+ default: begin
+ array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed11 <= 1'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed11 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+ end
+ 2'd2: begin
+ array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+ end
+ default: begin
+ array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed12 <= 1'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed12 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+ end
+ 2'd2: begin
+ array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+ end
+ default: begin
+ array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed13 <= 1'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed13 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+ end
+ 2'd2: begin
+ array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+ end
+ default: begin
+ array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed14 <= 3'd0;
+ case (litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed14 <= litedramcore_nop_ba[2:0];
+ end
+ 1'd1: begin
+ array_muxed14 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+ end
+ 2'd2: begin
+ array_muxed14 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+ end
+ default: begin
+ array_muxed14 <= litedramcore_cmd_payload_ba[2:0];
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed15 <= 15'd0;
+ case (litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed15 <= litedramcore_nop_a;
+ end
+ 1'd1: begin
+ array_muxed15 <= litedramcore_choose_cmd_cmd_payload_a;
+ end
+ 2'd2: begin
+ array_muxed15 <= litedramcore_choose_req_cmd_payload_a;
+ end
+ default: begin
+ array_muxed15 <= litedramcore_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed16 <= 1'd0;
+ case (litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed16 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed16 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+ end
+ 2'd2: begin
+ array_muxed16 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+ end
+ default: begin
+ array_muxed16 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed17 <= 1'd0;
+ case (litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed17 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed17 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+ end
+ 2'd2: begin
+ array_muxed17 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+ end
+ default: begin
+ array_muxed17 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed18 <= 1'd0;
+ case (litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed18 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed18 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+ end
+ 2'd2: begin
+ array_muxed18 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+ end
+ default: begin
+ array_muxed18 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed19 <= 1'd0;
+ case (litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed19 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed19 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+ end
+ 2'd2: begin
+ array_muxed19 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+ end
+ default: begin
+ array_muxed19 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed20 <= 1'd0;
+ case (litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed20 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed20 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+ end
+ 2'd2: begin
+ array_muxed20 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+ end
+ default: begin
+ array_muxed20 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed21 <= 3'd0;
+ case (litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed21 <= litedramcore_nop_ba[2:0];
+ end
+ 1'd1: begin
+ array_muxed21 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+ end
+ 2'd2: begin
+ array_muxed21 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+ end
+ default: begin
+ array_muxed21 <= litedramcore_cmd_payload_ba[2:0];
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed22 <= 15'd0;
+ case (litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed22 <= litedramcore_nop_a;
+ end
+ 1'd1: begin
+ array_muxed22 <= litedramcore_choose_cmd_cmd_payload_a;
+ end
+ 2'd2: begin
+ array_muxed22 <= litedramcore_choose_req_cmd_payload_a;
+ end
+ default: begin
+ array_muxed22 <= litedramcore_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed23 <= 1'd0;
+ case (litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed23 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed23 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+ end
+ 2'd2: begin
+ array_muxed23 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+ end
+ default: begin
+ array_muxed23 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed24 <= 1'd0;
+ case (litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed24 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed24 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+ end
+ 2'd2: begin
+ array_muxed24 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+ end
+ default: begin
+ array_muxed24 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed25 <= 1'd0;
+ case (litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed25 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed25 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+ end
+ 2'd2: begin
+ array_muxed25 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+ end
+ default: begin
+ array_muxed25 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed26 <= 1'd0;
+ case (litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed26 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed26 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+ end
+ 2'd2: begin
+ array_muxed26 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+ end
+ default: begin
+ array_muxed26 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed27 <= 1'd0;
+ case (litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed27 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed27 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+ end
+ 2'd2: begin
+ array_muxed27 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+ end
+ default: begin
+ array_muxed27 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+ end
+ endcase
end
assign xilinxasyncresetsynchronizerimpl0 = (~locked);
assign xilinxasyncresetsynchronizerimpl1 = (~locked);
//------------------------------------------------------------------------------
always @(posedge iodelay_clk) begin
- if ((reset_counter != 1'd0)) begin
- reset_counter <= (reset_counter - 1'd1);
- end else begin
- ic_reset <= 1'd0;
- end
- if (iodelay_rst) begin
- reset_counter <= 4'd15;
- ic_reset <= 1'd1;
- end
+ if ((reset_counter != 1'd0)) begin
+ reset_counter <= (reset_counter - 1'd1);
+ end else begin
+ ic_reset <= 1'd0;
+ end
+ if (iodelay_rst) begin
+ reset_counter <= 4'd15;
+ ic_reset <= 1'd1;
+ end
end
always @(posedge sys_clk) begin
- a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dqs_oe_delay_tappeddelayline;
- a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0;
- a7ddrphy_dqspattern_o1 <= a7ddrphy_dqspattern_o0;
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip0_value0 <= (a7ddrphy_bitslip0_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip0_value0 <= 3'd7;
- end
- a7ddrphy_bitslip0_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip0_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip1_value0 <= (a7ddrphy_bitslip1_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip1_value0 <= 3'd7;
- end
- a7ddrphy_bitslip1_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip1_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip0_value1 <= (a7ddrphy_bitslip0_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip0_value1 <= 3'd7;
- end
- a7ddrphy_bitslip0_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[2], a7ddrphy_dfi_p3_wrdata_mask[0], a7ddrphy_dfi_p2_wrdata_mask[2], a7ddrphy_dfi_p2_wrdata_mask[0], a7ddrphy_dfi_p1_wrdata_mask[2], a7ddrphy_dfi_p1_wrdata_mask[0], a7ddrphy_dfi_p0_wrdata_mask[2], a7ddrphy_dfi_p0_wrdata_mask[0]}, a7ddrphy_bitslip0_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip1_value1 <= (a7ddrphy_bitslip1_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip1_value1 <= 3'd7;
- end
- a7ddrphy_bitslip1_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[3], a7ddrphy_dfi_p3_wrdata_mask[1], a7ddrphy_dfi_p2_wrdata_mask[3], a7ddrphy_dfi_p2_wrdata_mask[1], a7ddrphy_dfi_p1_wrdata_mask[3], a7ddrphy_dfi_p1_wrdata_mask[1], a7ddrphy_dfi_p0_wrdata_mask[3], a7ddrphy_dfi_p0_wrdata_mask[1]}, a7ddrphy_bitslip1_r1[15:8]};
- a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dq_oe_delay_tappeddelayline;
- a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0;
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip0_value2 <= (a7ddrphy_bitslip0_value2 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip0_value2 <= 3'd7;
- end
- a7ddrphy_bitslip0_r2 <= {{a7ddrphy_dfi_p3_wrdata[16], a7ddrphy_dfi_p3_wrdata[0], a7ddrphy_dfi_p2_wrdata[16], a7ddrphy_dfi_p2_wrdata[0], a7ddrphy_dfi_p1_wrdata[16], a7ddrphy_dfi_p1_wrdata[0], a7ddrphy_dfi_p0_wrdata[16], a7ddrphy_dfi_p0_wrdata[0]}, a7ddrphy_bitslip0_r2[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip0_value3 <= (a7ddrphy_bitslip0_value3 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip0_value3 <= 3'd7;
- end
- a7ddrphy_bitslip0_r3 <= {a7ddrphy_bitslip03, a7ddrphy_bitslip0_r3[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip1_value2 <= (a7ddrphy_bitslip1_value2 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip1_value2 <= 3'd7;
- end
- a7ddrphy_bitslip1_r2 <= {{a7ddrphy_dfi_p3_wrdata[17], a7ddrphy_dfi_p3_wrdata[1], a7ddrphy_dfi_p2_wrdata[17], a7ddrphy_dfi_p2_wrdata[1], a7ddrphy_dfi_p1_wrdata[17], a7ddrphy_dfi_p1_wrdata[1], a7ddrphy_dfi_p0_wrdata[17], a7ddrphy_dfi_p0_wrdata[1]}, a7ddrphy_bitslip1_r2[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip1_value3 <= (a7ddrphy_bitslip1_value3 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip1_value3 <= 3'd7;
- end
- a7ddrphy_bitslip1_r3 <= {a7ddrphy_bitslip13, a7ddrphy_bitslip1_r3[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip2_value0 <= (a7ddrphy_bitslip2_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip2_value0 <= 3'd7;
- end
- a7ddrphy_bitslip2_r0 <= {{a7ddrphy_dfi_p3_wrdata[18], a7ddrphy_dfi_p3_wrdata[2], a7ddrphy_dfi_p2_wrdata[18], a7ddrphy_dfi_p2_wrdata[2], a7ddrphy_dfi_p1_wrdata[18], a7ddrphy_dfi_p1_wrdata[2], a7ddrphy_dfi_p0_wrdata[18], a7ddrphy_dfi_p0_wrdata[2]}, a7ddrphy_bitslip2_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip2_value1 <= (a7ddrphy_bitslip2_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip2_value1 <= 3'd7;
- end
- a7ddrphy_bitslip2_r1 <= {a7ddrphy_bitslip21, a7ddrphy_bitslip2_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip3_value0 <= (a7ddrphy_bitslip3_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip3_value0 <= 3'd7;
- end
- a7ddrphy_bitslip3_r0 <= {{a7ddrphy_dfi_p3_wrdata[19], a7ddrphy_dfi_p3_wrdata[3], a7ddrphy_dfi_p2_wrdata[19], a7ddrphy_dfi_p2_wrdata[3], a7ddrphy_dfi_p1_wrdata[19], a7ddrphy_dfi_p1_wrdata[3], a7ddrphy_dfi_p0_wrdata[19], a7ddrphy_dfi_p0_wrdata[3]}, a7ddrphy_bitslip3_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip3_value1 <= (a7ddrphy_bitslip3_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip3_value1 <= 3'd7;
- end
- a7ddrphy_bitslip3_r1 <= {a7ddrphy_bitslip31, a7ddrphy_bitslip3_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip4_value0 <= (a7ddrphy_bitslip4_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip4_value0 <= 3'd7;
- end
- a7ddrphy_bitslip4_r0 <= {{a7ddrphy_dfi_p3_wrdata[20], a7ddrphy_dfi_p3_wrdata[4], a7ddrphy_dfi_p2_wrdata[20], a7ddrphy_dfi_p2_wrdata[4], a7ddrphy_dfi_p1_wrdata[20], a7ddrphy_dfi_p1_wrdata[4], a7ddrphy_dfi_p0_wrdata[20], a7ddrphy_dfi_p0_wrdata[4]}, a7ddrphy_bitslip4_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip4_value1 <= (a7ddrphy_bitslip4_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip4_value1 <= 3'd7;
- end
- a7ddrphy_bitslip4_r1 <= {a7ddrphy_bitslip41, a7ddrphy_bitslip4_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip5_value0 <= (a7ddrphy_bitslip5_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip5_value0 <= 3'd7;
- end
- a7ddrphy_bitslip5_r0 <= {{a7ddrphy_dfi_p3_wrdata[21], a7ddrphy_dfi_p3_wrdata[5], a7ddrphy_dfi_p2_wrdata[21], a7ddrphy_dfi_p2_wrdata[5], a7ddrphy_dfi_p1_wrdata[21], a7ddrphy_dfi_p1_wrdata[5], a7ddrphy_dfi_p0_wrdata[21], a7ddrphy_dfi_p0_wrdata[5]}, a7ddrphy_bitslip5_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip5_value1 <= (a7ddrphy_bitslip5_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip5_value1 <= 3'd7;
- end
- a7ddrphy_bitslip5_r1 <= {a7ddrphy_bitslip51, a7ddrphy_bitslip5_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip6_value0 <= (a7ddrphy_bitslip6_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip6_value0 <= 3'd7;
- end
- a7ddrphy_bitslip6_r0 <= {{a7ddrphy_dfi_p3_wrdata[22], a7ddrphy_dfi_p3_wrdata[6], a7ddrphy_dfi_p2_wrdata[22], a7ddrphy_dfi_p2_wrdata[6], a7ddrphy_dfi_p1_wrdata[22], a7ddrphy_dfi_p1_wrdata[6], a7ddrphy_dfi_p0_wrdata[22], a7ddrphy_dfi_p0_wrdata[6]}, a7ddrphy_bitslip6_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip6_value1 <= (a7ddrphy_bitslip6_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip6_value1 <= 3'd7;
- end
- a7ddrphy_bitslip6_r1 <= {a7ddrphy_bitslip61, a7ddrphy_bitslip6_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip7_value0 <= (a7ddrphy_bitslip7_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip7_value0 <= 3'd7;
- end
- a7ddrphy_bitslip7_r0 <= {{a7ddrphy_dfi_p3_wrdata[23], a7ddrphy_dfi_p3_wrdata[7], a7ddrphy_dfi_p2_wrdata[23], a7ddrphy_dfi_p2_wrdata[7], a7ddrphy_dfi_p1_wrdata[23], a7ddrphy_dfi_p1_wrdata[7], a7ddrphy_dfi_p0_wrdata[23], a7ddrphy_dfi_p0_wrdata[7]}, a7ddrphy_bitslip7_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip7_value1 <= (a7ddrphy_bitslip7_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip7_value1 <= 3'd7;
- end
- a7ddrphy_bitslip7_r1 <= {a7ddrphy_bitslip71, a7ddrphy_bitslip7_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip8_value0 <= (a7ddrphy_bitslip8_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip8_value0 <= 3'd7;
- end
- a7ddrphy_bitslip8_r0 <= {{a7ddrphy_dfi_p3_wrdata[24], a7ddrphy_dfi_p3_wrdata[8], a7ddrphy_dfi_p2_wrdata[24], a7ddrphy_dfi_p2_wrdata[8], a7ddrphy_dfi_p1_wrdata[24], a7ddrphy_dfi_p1_wrdata[8], a7ddrphy_dfi_p0_wrdata[24], a7ddrphy_dfi_p0_wrdata[8]}, a7ddrphy_bitslip8_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip8_value1 <= (a7ddrphy_bitslip8_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip8_value1 <= 3'd7;
- end
- a7ddrphy_bitslip8_r1 <= {a7ddrphy_bitslip81, a7ddrphy_bitslip8_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip9_value0 <= (a7ddrphy_bitslip9_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip9_value0 <= 3'd7;
- end
- a7ddrphy_bitslip9_r0 <= {{a7ddrphy_dfi_p3_wrdata[25], a7ddrphy_dfi_p3_wrdata[9], a7ddrphy_dfi_p2_wrdata[25], a7ddrphy_dfi_p2_wrdata[9], a7ddrphy_dfi_p1_wrdata[25], a7ddrphy_dfi_p1_wrdata[9], a7ddrphy_dfi_p0_wrdata[25], a7ddrphy_dfi_p0_wrdata[9]}, a7ddrphy_bitslip9_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip9_value1 <= (a7ddrphy_bitslip9_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip9_value1 <= 3'd7;
- end
- a7ddrphy_bitslip9_r1 <= {a7ddrphy_bitslip91, a7ddrphy_bitslip9_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip10_value0 <= (a7ddrphy_bitslip10_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip10_value0 <= 3'd7;
- end
- a7ddrphy_bitslip10_r0 <= {{a7ddrphy_dfi_p3_wrdata[26], a7ddrphy_dfi_p3_wrdata[10], a7ddrphy_dfi_p2_wrdata[26], a7ddrphy_dfi_p2_wrdata[10], a7ddrphy_dfi_p1_wrdata[26], a7ddrphy_dfi_p1_wrdata[10], a7ddrphy_dfi_p0_wrdata[26], a7ddrphy_dfi_p0_wrdata[10]}, a7ddrphy_bitslip10_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip10_value1 <= (a7ddrphy_bitslip10_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip10_value1 <= 3'd7;
- end
- a7ddrphy_bitslip10_r1 <= {a7ddrphy_bitslip101, a7ddrphy_bitslip10_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip11_value0 <= (a7ddrphy_bitslip11_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip11_value0 <= 3'd7;
- end
- a7ddrphy_bitslip11_r0 <= {{a7ddrphy_dfi_p3_wrdata[27], a7ddrphy_dfi_p3_wrdata[11], a7ddrphy_dfi_p2_wrdata[27], a7ddrphy_dfi_p2_wrdata[11], a7ddrphy_dfi_p1_wrdata[27], a7ddrphy_dfi_p1_wrdata[11], a7ddrphy_dfi_p0_wrdata[27], a7ddrphy_dfi_p0_wrdata[11]}, a7ddrphy_bitslip11_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip11_value1 <= (a7ddrphy_bitslip11_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip11_value1 <= 3'd7;
- end
- a7ddrphy_bitslip11_r1 <= {a7ddrphy_bitslip111, a7ddrphy_bitslip11_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip12_value0 <= (a7ddrphy_bitslip12_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip12_value0 <= 3'd7;
- end
- a7ddrphy_bitslip12_r0 <= {{a7ddrphy_dfi_p3_wrdata[28], a7ddrphy_dfi_p3_wrdata[12], a7ddrphy_dfi_p2_wrdata[28], a7ddrphy_dfi_p2_wrdata[12], a7ddrphy_dfi_p1_wrdata[28], a7ddrphy_dfi_p1_wrdata[12], a7ddrphy_dfi_p0_wrdata[28], a7ddrphy_dfi_p0_wrdata[12]}, a7ddrphy_bitslip12_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip12_value1 <= (a7ddrphy_bitslip12_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip12_value1 <= 3'd7;
- end
- a7ddrphy_bitslip12_r1 <= {a7ddrphy_bitslip121, a7ddrphy_bitslip12_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip13_value0 <= (a7ddrphy_bitslip13_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip13_value0 <= 3'd7;
- end
- a7ddrphy_bitslip13_r0 <= {{a7ddrphy_dfi_p3_wrdata[29], a7ddrphy_dfi_p3_wrdata[13], a7ddrphy_dfi_p2_wrdata[29], a7ddrphy_dfi_p2_wrdata[13], a7ddrphy_dfi_p1_wrdata[29], a7ddrphy_dfi_p1_wrdata[13], a7ddrphy_dfi_p0_wrdata[29], a7ddrphy_dfi_p0_wrdata[13]}, a7ddrphy_bitslip13_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip13_value1 <= (a7ddrphy_bitslip13_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip13_value1 <= 3'd7;
- end
- a7ddrphy_bitslip13_r1 <= {a7ddrphy_bitslip131, a7ddrphy_bitslip13_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip14_value0 <= (a7ddrphy_bitslip14_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip14_value0 <= 3'd7;
- end
- a7ddrphy_bitslip14_r0 <= {{a7ddrphy_dfi_p3_wrdata[30], a7ddrphy_dfi_p3_wrdata[14], a7ddrphy_dfi_p2_wrdata[30], a7ddrphy_dfi_p2_wrdata[14], a7ddrphy_dfi_p1_wrdata[30], a7ddrphy_dfi_p1_wrdata[14], a7ddrphy_dfi_p0_wrdata[30], a7ddrphy_dfi_p0_wrdata[14]}, a7ddrphy_bitslip14_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip14_value1 <= (a7ddrphy_bitslip14_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip14_value1 <= 3'd7;
- end
- a7ddrphy_bitslip14_r1 <= {a7ddrphy_bitslip141, a7ddrphy_bitslip14_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip15_value0 <= (a7ddrphy_bitslip15_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip15_value0 <= 3'd7;
- end
- a7ddrphy_bitslip15_r0 <= {{a7ddrphy_dfi_p3_wrdata[31], a7ddrphy_dfi_p3_wrdata[15], a7ddrphy_dfi_p2_wrdata[31], a7ddrphy_dfi_p2_wrdata[15], a7ddrphy_dfi_p1_wrdata[31], a7ddrphy_dfi_p1_wrdata[15], a7ddrphy_dfi_p0_wrdata[31], a7ddrphy_dfi_p0_wrdata[15]}, a7ddrphy_bitslip15_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip15_value1 <= (a7ddrphy_bitslip15_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip15_value1 <= 3'd7;
- end
- a7ddrphy_bitslip15_r1 <= {a7ddrphy_bitslip151, a7ddrphy_bitslip15_r1[15:8]};
- a7ddrphy_rddata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_rddata_en | a7ddrphy_dfi_p1_rddata_en) | a7ddrphy_dfi_p2_rddata_en) | a7ddrphy_dfi_p3_rddata_en);
- a7ddrphy_rddata_en_tappeddelayline1 <= a7ddrphy_rddata_en_tappeddelayline0;
- a7ddrphy_rddata_en_tappeddelayline2 <= a7ddrphy_rddata_en_tappeddelayline1;
- a7ddrphy_rddata_en_tappeddelayline3 <= a7ddrphy_rddata_en_tappeddelayline2;
- a7ddrphy_rddata_en_tappeddelayline4 <= a7ddrphy_rddata_en_tappeddelayline3;
- a7ddrphy_rddata_en_tappeddelayline5 <= a7ddrphy_rddata_en_tappeddelayline4;
- a7ddrphy_rddata_en_tappeddelayline6 <= a7ddrphy_rddata_en_tappeddelayline5;
- a7ddrphy_rddata_en_tappeddelayline7 <= a7ddrphy_rddata_en_tappeddelayline6;
- a7ddrphy_wrdata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_wrdata_en | a7ddrphy_dfi_p1_wrdata_en) | a7ddrphy_dfi_p2_wrdata_en) | a7ddrphy_dfi_p3_wrdata_en);
- a7ddrphy_wrdata_en_tappeddelayline1 <= a7ddrphy_wrdata_en_tappeddelayline0;
- a7ddrphy_wrdata_en_tappeddelayline2 <= a7ddrphy_wrdata_en_tappeddelayline1;
- if (litedramcore_csr_dfi_p0_rddata_valid) begin
- litedramcore_phaseinjector0_rddata_status <= litedramcore_csr_dfi_p0_rddata;
- end
- if (litedramcore_csr_dfi_p1_rddata_valid) begin
- litedramcore_phaseinjector1_rddata_status <= litedramcore_csr_dfi_p1_rddata;
- end
- if (litedramcore_csr_dfi_p2_rddata_valid) begin
- litedramcore_phaseinjector2_rddata_status <= litedramcore_csr_dfi_p2_rddata;
- end
- if (litedramcore_csr_dfi_p3_rddata_valid) begin
- litedramcore_phaseinjector3_rddata_status <= litedramcore_csr_dfi_p3_rddata;
- end
- if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin
- litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1);
- end else begin
- litedramcore_timer_count1 <= 10'd781;
- end
- litedramcore_postponer_req_o <= 1'd0;
- if (litedramcore_postponer_req_i) begin
- litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1);
- if ((litedramcore_postponer_count == 1'd0)) begin
- litedramcore_postponer_count <= 1'd0;
- litedramcore_postponer_req_o <= 1'd1;
- end
- end
- if (litedramcore_sequencer_start0) begin
- litedramcore_sequencer_count <= 1'd0;
- end else begin
- if (litedramcore_sequencer_done1) begin
- if ((litedramcore_sequencer_count != 1'd0)) begin
- litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1);
- end
- end
- end
- litedramcore_cmd_payload_a <= 1'd0;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd0;
- litedramcore_cmd_payload_we <= 1'd0;
- litedramcore_sequencer_done1 <= 1'd0;
- if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin
- litedramcore_cmd_payload_a <= 11'd1024;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd1;
- litedramcore_cmd_payload_we <= 1'd1;
- end
- if ((litedramcore_sequencer_counter == 2'd3)) begin
- litedramcore_cmd_payload_a <= 11'd1024;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd1;
- litedramcore_cmd_payload_ras <= 1'd1;
- litedramcore_cmd_payload_we <= 1'd0;
- end
- if ((litedramcore_sequencer_counter == 6'd55)) begin
- litedramcore_cmd_payload_a <= 1'd0;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd0;
- litedramcore_cmd_payload_we <= 1'd0;
- litedramcore_sequencer_done1 <= 1'd1;
- end
- if ((litedramcore_sequencer_counter == 6'd55)) begin
- litedramcore_sequencer_counter <= 1'd0;
- end else begin
- if ((litedramcore_sequencer_counter != 1'd0)) begin
- litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1);
- end else begin
- if (litedramcore_sequencer_start1) begin
- litedramcore_sequencer_counter <= 1'd1;
- end
- end
- end
- if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin
- litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1);
- end else begin
- litedramcore_zqcs_timer_count1 <= 27'd99999999;
- end
- litedramcore_zqcs_executer_done <= 1'd0;
- if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin
- litedramcore_cmd_payload_a <= 11'd1024;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd1;
- litedramcore_cmd_payload_we <= 1'd1;
- end
- if ((litedramcore_zqcs_executer_counter == 2'd3)) begin
- litedramcore_cmd_payload_a <= 1'd0;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd0;
- litedramcore_cmd_payload_we <= 1'd1;
- end
- if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
- litedramcore_cmd_payload_a <= 1'd0;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd0;
- litedramcore_cmd_payload_we <= 1'd0;
- litedramcore_zqcs_executer_done <= 1'd1;
- end
- if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
- litedramcore_zqcs_executer_counter <= 1'd0;
- end else begin
- if ((litedramcore_zqcs_executer_counter != 1'd0)) begin
- litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1);
- end else begin
- if (litedramcore_zqcs_executer_start) begin
- litedramcore_zqcs_executer_counter <= 1'd1;
- end
- end
- end
- litedramcore_refresher_state <= litedramcore_refresher_next_state;
- if (litedramcore_bankmachine0_row_close) begin
- litedramcore_bankmachine0_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine0_row_open) begin
- litedramcore_bankmachine0_row_opened <= 1'd1;
- litedramcore_bankmachine0_row <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7];
- end
- end
- if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine0_cmd_buffer_source_valid <= litedramcore_bankmachine0_cmd_buffer_sink_valid;
- litedramcore_bankmachine0_cmd_buffer_source_first <= litedramcore_bankmachine0_cmd_buffer_sink_first;
- litedramcore_bankmachine0_cmd_buffer_source_last <= litedramcore_bankmachine0_cmd_buffer_sink_last;
- litedramcore_bankmachine0_cmd_buffer_source_payload_we <= litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine0_twtpcon_valid) begin
- litedramcore_bankmachine0_twtpcon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine0_twtpcon_ready)) begin
- litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine0_trccon_valid) begin
- litedramcore_bankmachine0_trccon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine0_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine0_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine0_trccon_ready)) begin
- litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1);
- if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin
- litedramcore_bankmachine0_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine0_trascon_valid) begin
- litedramcore_bankmachine0_trascon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_bankmachine0_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine0_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1);
- if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin
- litedramcore_bankmachine0_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state;
- if (litedramcore_bankmachine1_row_close) begin
- litedramcore_bankmachine1_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine1_row_open) begin
- litedramcore_bankmachine1_row_opened <= 1'd1;
- litedramcore_bankmachine1_row <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7];
- end
- end
- if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine1_cmd_buffer_source_valid <= litedramcore_bankmachine1_cmd_buffer_sink_valid;
- litedramcore_bankmachine1_cmd_buffer_source_first <= litedramcore_bankmachine1_cmd_buffer_sink_first;
- litedramcore_bankmachine1_cmd_buffer_source_last <= litedramcore_bankmachine1_cmd_buffer_sink_last;
- litedramcore_bankmachine1_cmd_buffer_source_payload_we <= litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine1_twtpcon_valid) begin
- litedramcore_bankmachine1_twtpcon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine1_twtpcon_ready)) begin
- litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine1_trccon_valid) begin
- litedramcore_bankmachine1_trccon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine1_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine1_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine1_trccon_ready)) begin
- litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1);
- if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin
- litedramcore_bankmachine1_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine1_trascon_valid) begin
- litedramcore_bankmachine1_trascon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_bankmachine1_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine1_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1);
- if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin
- litedramcore_bankmachine1_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state;
- if (litedramcore_bankmachine2_row_close) begin
- litedramcore_bankmachine2_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine2_row_open) begin
- litedramcore_bankmachine2_row_opened <= 1'd1;
- litedramcore_bankmachine2_row <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7];
- end
- end
- if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine2_cmd_buffer_source_valid <= litedramcore_bankmachine2_cmd_buffer_sink_valid;
- litedramcore_bankmachine2_cmd_buffer_source_first <= litedramcore_bankmachine2_cmd_buffer_sink_first;
- litedramcore_bankmachine2_cmd_buffer_source_last <= litedramcore_bankmachine2_cmd_buffer_sink_last;
- litedramcore_bankmachine2_cmd_buffer_source_payload_we <= litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine2_twtpcon_valid) begin
- litedramcore_bankmachine2_twtpcon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine2_twtpcon_ready)) begin
- litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine2_trccon_valid) begin
- litedramcore_bankmachine2_trccon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine2_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine2_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine2_trccon_ready)) begin
- litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1);
- if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin
- litedramcore_bankmachine2_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine2_trascon_valid) begin
- litedramcore_bankmachine2_trascon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_bankmachine2_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine2_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1);
- if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin
- litedramcore_bankmachine2_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state;
- if (litedramcore_bankmachine3_row_close) begin
- litedramcore_bankmachine3_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine3_row_open) begin
- litedramcore_bankmachine3_row_opened <= 1'd1;
- litedramcore_bankmachine3_row <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7];
- end
- end
- if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine3_cmd_buffer_source_valid <= litedramcore_bankmachine3_cmd_buffer_sink_valid;
- litedramcore_bankmachine3_cmd_buffer_source_first <= litedramcore_bankmachine3_cmd_buffer_sink_first;
- litedramcore_bankmachine3_cmd_buffer_source_last <= litedramcore_bankmachine3_cmd_buffer_sink_last;
- litedramcore_bankmachine3_cmd_buffer_source_payload_we <= litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine3_twtpcon_valid) begin
- litedramcore_bankmachine3_twtpcon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine3_twtpcon_ready)) begin
- litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine3_trccon_valid) begin
- litedramcore_bankmachine3_trccon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine3_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine3_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine3_trccon_ready)) begin
- litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1);
- if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin
- litedramcore_bankmachine3_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine3_trascon_valid) begin
- litedramcore_bankmachine3_trascon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_bankmachine3_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine3_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1);
- if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin
- litedramcore_bankmachine3_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state;
- if (litedramcore_bankmachine4_row_close) begin
- litedramcore_bankmachine4_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine4_row_open) begin
- litedramcore_bankmachine4_row_opened <= 1'd1;
- litedramcore_bankmachine4_row <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7];
- end
- end
- if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine4_cmd_buffer_source_valid <= litedramcore_bankmachine4_cmd_buffer_sink_valid;
- litedramcore_bankmachine4_cmd_buffer_source_first <= litedramcore_bankmachine4_cmd_buffer_sink_first;
- litedramcore_bankmachine4_cmd_buffer_source_last <= litedramcore_bankmachine4_cmd_buffer_sink_last;
- litedramcore_bankmachine4_cmd_buffer_source_payload_we <= litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine4_twtpcon_valid) begin
- litedramcore_bankmachine4_twtpcon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine4_twtpcon_ready)) begin
- litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine4_trccon_valid) begin
- litedramcore_bankmachine4_trccon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine4_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine4_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine4_trccon_ready)) begin
- litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1);
- if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin
- litedramcore_bankmachine4_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine4_trascon_valid) begin
- litedramcore_bankmachine4_trascon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_bankmachine4_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine4_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1);
- if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin
- litedramcore_bankmachine4_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state;
- if (litedramcore_bankmachine5_row_close) begin
- litedramcore_bankmachine5_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine5_row_open) begin
- litedramcore_bankmachine5_row_opened <= 1'd1;
- litedramcore_bankmachine5_row <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7];
- end
- end
- if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine5_cmd_buffer_source_valid <= litedramcore_bankmachine5_cmd_buffer_sink_valid;
- litedramcore_bankmachine5_cmd_buffer_source_first <= litedramcore_bankmachine5_cmd_buffer_sink_first;
- litedramcore_bankmachine5_cmd_buffer_source_last <= litedramcore_bankmachine5_cmd_buffer_sink_last;
- litedramcore_bankmachine5_cmd_buffer_source_payload_we <= litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine5_twtpcon_valid) begin
- litedramcore_bankmachine5_twtpcon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine5_twtpcon_ready)) begin
- litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine5_trccon_valid) begin
- litedramcore_bankmachine5_trccon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine5_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine5_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine5_trccon_ready)) begin
- litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1);
- if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin
- litedramcore_bankmachine5_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine5_trascon_valid) begin
- litedramcore_bankmachine5_trascon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_bankmachine5_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine5_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1);
- if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin
- litedramcore_bankmachine5_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state;
- if (litedramcore_bankmachine6_row_close) begin
- litedramcore_bankmachine6_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine6_row_open) begin
- litedramcore_bankmachine6_row_opened <= 1'd1;
- litedramcore_bankmachine6_row <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7];
- end
- end
- if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine6_cmd_buffer_source_valid <= litedramcore_bankmachine6_cmd_buffer_sink_valid;
- litedramcore_bankmachine6_cmd_buffer_source_first <= litedramcore_bankmachine6_cmd_buffer_sink_first;
- litedramcore_bankmachine6_cmd_buffer_source_last <= litedramcore_bankmachine6_cmd_buffer_sink_last;
- litedramcore_bankmachine6_cmd_buffer_source_payload_we <= litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine6_twtpcon_valid) begin
- litedramcore_bankmachine6_twtpcon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine6_twtpcon_ready)) begin
- litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine6_trccon_valid) begin
- litedramcore_bankmachine6_trccon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine6_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine6_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine6_trccon_ready)) begin
- litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1);
- if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin
- litedramcore_bankmachine6_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine6_trascon_valid) begin
- litedramcore_bankmachine6_trascon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_bankmachine6_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine6_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1);
- if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin
- litedramcore_bankmachine6_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state;
- if (litedramcore_bankmachine7_row_close) begin
- litedramcore_bankmachine7_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine7_row_open) begin
- litedramcore_bankmachine7_row_opened <= 1'd1;
- litedramcore_bankmachine7_row <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7];
- end
- end
- if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine7_cmd_buffer_source_valid <= litedramcore_bankmachine7_cmd_buffer_sink_valid;
- litedramcore_bankmachine7_cmd_buffer_source_first <= litedramcore_bankmachine7_cmd_buffer_sink_first;
- litedramcore_bankmachine7_cmd_buffer_source_last <= litedramcore_bankmachine7_cmd_buffer_sink_last;
- litedramcore_bankmachine7_cmd_buffer_source_payload_we <= litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine7_twtpcon_valid) begin
- litedramcore_bankmachine7_twtpcon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine7_twtpcon_ready)) begin
- litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine7_trccon_valid) begin
- litedramcore_bankmachine7_trccon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine7_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine7_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine7_trccon_ready)) begin
- litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1);
- if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin
- litedramcore_bankmachine7_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine7_trascon_valid) begin
- litedramcore_bankmachine7_trascon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_bankmachine7_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine7_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1);
- if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin
- litedramcore_bankmachine7_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state;
- if ((~litedramcore_en0)) begin
- litedramcore_time0 <= 5'd31;
- end else begin
- if ((~litedramcore_max_time0)) begin
- litedramcore_time0 <= (litedramcore_time0 - 1'd1);
- end
- end
- if ((~litedramcore_en1)) begin
- litedramcore_time1 <= 4'd15;
- end else begin
- if ((~litedramcore_max_time1)) begin
- litedramcore_time1 <= (litedramcore_time1 - 1'd1);
- end
- end
- if (litedramcore_choose_cmd_ce) begin
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
- end
- end
- end
- end
- end
- end
- end
- end
- 1'd1: begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
- end
- end
- end
- end
- end
- end
- end
- end
- 2'd2: begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
- end
- end
- end
- end
- end
- end
- end
- end
- 2'd3: begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd4: begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd5: begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd6: begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd7: begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
- end
- end
- end
- end
- end
- end
- end
- end
- endcase
- end
- if (litedramcore_choose_req_ce) begin
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
- end
- end
- end
- end
- end
- end
- end
- end
- 1'd1: begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
- end
- end
- end
- end
- end
- end
- end
- end
- 2'd2: begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
- end
- end
- end
- end
- end
- end
- end
- end
- 2'd3: begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd4: begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd5: begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd6: begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd7: begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
- end
- end
- end
- end
- end
- end
- end
- end
- endcase
- end
- litedramcore_dfi_p0_cs_n <= 1'd0;
- litedramcore_dfi_p0_bank <= array_muxed0;
- litedramcore_dfi_p0_address <= array_muxed1;
- litedramcore_dfi_p0_cas_n <= (~array_muxed2);
- litedramcore_dfi_p0_ras_n <= (~array_muxed3);
- litedramcore_dfi_p0_we_n <= (~array_muxed4);
- litedramcore_dfi_p0_rddata_en <= array_muxed5;
- litedramcore_dfi_p0_wrdata_en <= array_muxed6;
- litedramcore_dfi_p1_cs_n <= 1'd0;
- litedramcore_dfi_p1_bank <= array_muxed7;
- litedramcore_dfi_p1_address <= array_muxed8;
- litedramcore_dfi_p1_cas_n <= (~array_muxed9);
- litedramcore_dfi_p1_ras_n <= (~array_muxed10);
- litedramcore_dfi_p1_we_n <= (~array_muxed11);
- litedramcore_dfi_p1_rddata_en <= array_muxed12;
- litedramcore_dfi_p1_wrdata_en <= array_muxed13;
- litedramcore_dfi_p2_cs_n <= 1'd0;
- litedramcore_dfi_p2_bank <= array_muxed14;
- litedramcore_dfi_p2_address <= array_muxed15;
- litedramcore_dfi_p2_cas_n <= (~array_muxed16);
- litedramcore_dfi_p2_ras_n <= (~array_muxed17);
- litedramcore_dfi_p2_we_n <= (~array_muxed18);
- litedramcore_dfi_p2_rddata_en <= array_muxed19;
- litedramcore_dfi_p2_wrdata_en <= array_muxed20;
- litedramcore_dfi_p3_cs_n <= 1'd0;
- litedramcore_dfi_p3_bank <= array_muxed21;
- litedramcore_dfi_p3_address <= array_muxed22;
- litedramcore_dfi_p3_cas_n <= (~array_muxed23);
- litedramcore_dfi_p3_ras_n <= (~array_muxed24);
- litedramcore_dfi_p3_we_n <= (~array_muxed25);
- litedramcore_dfi_p3_rddata_en <= array_muxed26;
- litedramcore_dfi_p3_wrdata_en <= array_muxed27;
- if (litedramcore_trrdcon_valid) begin
- litedramcore_trrdcon_count <= 1'd1;
- if (1'd0) begin
- litedramcore_trrdcon_ready <= 1'd1;
- end else begin
- litedramcore_trrdcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_trrdcon_ready)) begin
- litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1);
- if ((litedramcore_trrdcon_count == 1'd1)) begin
- litedramcore_trrdcon_ready <= 1'd1;
- end
- end
- end
- litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid};
- if ((litedramcore_tfawcon_count < 3'd4)) begin
- if ((litedramcore_tfawcon_count == 2'd3)) begin
- litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid);
- end else begin
- litedramcore_tfawcon_ready <= 1'd1;
- end
- end
- if (litedramcore_tccdcon_valid) begin
- litedramcore_tccdcon_count <= 1'd0;
- if (1'd1) begin
- litedramcore_tccdcon_ready <= 1'd1;
- end else begin
- litedramcore_tccdcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_tccdcon_ready)) begin
- litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1);
- if ((litedramcore_tccdcon_count == 1'd1)) begin
- litedramcore_tccdcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_twtrcon_valid) begin
- litedramcore_twtrcon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_twtrcon_ready <= 1'd1;
- end else begin
- litedramcore_twtrcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_twtrcon_ready)) begin
- litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1);
- if ((litedramcore_twtrcon_count == 1'd1)) begin
- litedramcore_twtrcon_ready <= 1'd1;
- end
- end
- end
- litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state;
- litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready));
- litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0;
- litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid));
- litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0;
- litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1;
- litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2;
- litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3;
- litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4;
- litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5;
- litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6;
- litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7;
- litedramcore_state <= litedramcore_next_state;
- if (litedramcore_dat_w_next_value_ce0) begin
- litedramcore_dat_w <= litedramcore_dat_w_next_value0;
- end
- if (litedramcore_adr_next_value_ce1) begin
- litedramcore_adr <= litedramcore_adr_next_value1;
- end
- if (litedramcore_we_next_value_ce2) begin
- litedramcore_we <= litedramcore_we_next_value2;
- end
- interface0_bank_bus_dat_r <= 1'd0;
- if (csrbank0_sel) begin
- case (interface0_bank_bus_adr[8:0])
- 1'd0: begin
- interface0_bank_bus_dat_r <= csrbank0_init_done0_w;
- end
- 1'd1: begin
- interface0_bank_bus_dat_r <= csrbank0_init_error0_w;
- end
- endcase
- end
- if (csrbank0_init_done0_re) begin
- init_done_storage <= csrbank0_init_done0_r;
- end
- init_done_re <= csrbank0_init_done0_re;
- if (csrbank0_init_error0_re) begin
- init_error_storage <= csrbank0_init_error0_r;
- end
- init_error_re <= csrbank0_init_error0_re;
- interface1_bank_bus_dat_r <= 1'd0;
- if (csrbank1_sel) begin
- case (interface1_bank_bus_adr[8:0])
- 1'd0: begin
- interface1_bank_bus_dat_r <= csrbank1_rst0_w;
- end
- 1'd1: begin
- interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w;
- end
- 2'd2: begin
- interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w;
- end
- 2'd3: begin
- interface1_bank_bus_dat_r <= csrbank1_wlevel_en0_w;
- end
- 3'd4: begin
- interface1_bank_bus_dat_r <= a7ddrphy_wlevel_strobe_w;
- end
- 3'd5: begin
- interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_rst_w;
- end
- 3'd6: begin
- interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_inc_w;
- end
- 3'd7: begin
- interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_rst_w;
- end
- 4'd8: begin
- interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_w;
- end
- 4'd9: begin
- interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_rst_w;
- end
- 4'd10: begin
- interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_w;
- end
- 4'd11: begin
- interface1_bank_bus_dat_r <= csrbank1_rdphase0_w;
- end
- 4'd12: begin
- interface1_bank_bus_dat_r <= csrbank1_wrphase0_w;
- end
- endcase
- end
- if (csrbank1_rst0_re) begin
- a7ddrphy_rst_storage <= csrbank1_rst0_r;
- end
- a7ddrphy_rst_re <= csrbank1_rst0_re;
- if (csrbank1_dly_sel0_re) begin
- a7ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r;
- end
- a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re;
- if (csrbank1_half_sys8x_taps0_re) begin
- a7ddrphy_half_sys8x_taps_storage[4:0] <= csrbank1_half_sys8x_taps0_r;
- end
- a7ddrphy_half_sys8x_taps_re <= csrbank1_half_sys8x_taps0_re;
- if (csrbank1_wlevel_en0_re) begin
- a7ddrphy_wlevel_en_storage <= csrbank1_wlevel_en0_r;
- end
- a7ddrphy_wlevel_en_re <= csrbank1_wlevel_en0_re;
- if (csrbank1_rdphase0_re) begin
- a7ddrphy_rdphase_storage[1:0] <= csrbank1_rdphase0_r;
- end
- a7ddrphy_rdphase_re <= csrbank1_rdphase0_re;
- if (csrbank1_wrphase0_re) begin
- a7ddrphy_wrphase_storage[1:0] <= csrbank1_wrphase0_r;
- end
- a7ddrphy_wrphase_re <= csrbank1_wrphase0_re;
- interface2_bank_bus_dat_r <= 1'd0;
- if (csrbank2_sel) begin
- case (interface2_bank_bus_adr[8:0])
- 1'd0: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w;
- end
- 1'd1: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w;
- end
- 2'd2: begin
- interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w;
- end
- 2'd3: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w;
- end
- 3'd4: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w;
- end
- 3'd5: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w;
- end
- 3'd6: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata_w;
- end
- 3'd7: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w;
- end
- 4'd8: begin
- interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w;
- end
- 4'd9: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w;
- end
- 4'd10: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w;
- end
- 4'd11: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w;
- end
- 4'd12: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata_w;
- end
- 4'd13: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w;
- end
- 4'd14: begin
- interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w;
- end
- 4'd15: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w;
- end
- 5'd16: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w;
- end
- 5'd17: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w;
- end
- 5'd18: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata_w;
- end
- 5'd19: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w;
- end
- 5'd20: begin
- interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w;
- end
- 5'd21: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w;
- end
- 5'd22: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w;
- end
- 5'd23: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w;
- end
- 5'd24: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata_w;
- end
- endcase
- end
- if (csrbank2_dfii_control0_re) begin
- litedramcore_storage[3:0] <= csrbank2_dfii_control0_r;
- end
- litedramcore_re <= csrbank2_dfii_control0_re;
- if (csrbank2_dfii_pi0_command0_re) begin
- litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r;
- end
- litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re;
- if (csrbank2_dfii_pi0_address0_re) begin
- litedramcore_phaseinjector0_address_storage[14:0] <= csrbank2_dfii_pi0_address0_r;
- end
- litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re;
- if (csrbank2_dfii_pi0_baddress0_re) begin
- litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r;
- end
- litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re;
- if (csrbank2_dfii_pi0_wrdata0_re) begin
- litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r;
- end
- litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re;
- litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata_re;
- if (csrbank2_dfii_pi1_command0_re) begin
- litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r;
- end
- litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re;
- if (csrbank2_dfii_pi1_address0_re) begin
- litedramcore_phaseinjector1_address_storage[14:0] <= csrbank2_dfii_pi1_address0_r;
- end
- litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re;
- if (csrbank2_dfii_pi1_baddress0_re) begin
- litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r;
- end
- litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re;
- if (csrbank2_dfii_pi1_wrdata0_re) begin
- litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r;
- end
- litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re;
- litedramcore_phaseinjector1_rddata_re <= csrbank2_dfii_pi1_rddata_re;
- if (csrbank2_dfii_pi2_command0_re) begin
- litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r;
- end
- litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re;
- if (csrbank2_dfii_pi2_address0_re) begin
- litedramcore_phaseinjector2_address_storage[14:0] <= csrbank2_dfii_pi2_address0_r;
- end
- litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re;
- if (csrbank2_dfii_pi2_baddress0_re) begin
- litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r;
- end
- litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re;
- if (csrbank2_dfii_pi2_wrdata0_re) begin
- litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r;
- end
- litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re;
- litedramcore_phaseinjector2_rddata_re <= csrbank2_dfii_pi2_rddata_re;
- if (csrbank2_dfii_pi3_command0_re) begin
- litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r;
- end
- litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re;
- if (csrbank2_dfii_pi3_address0_re) begin
- litedramcore_phaseinjector3_address_storage[14:0] <= csrbank2_dfii_pi3_address0_r;
- end
- litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re;
- if (csrbank2_dfii_pi3_baddress0_re) begin
- litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r;
- end
- litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re;
- if (csrbank2_dfii_pi3_wrdata0_re) begin
- litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r;
- end
- litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re;
- litedramcore_phaseinjector3_rddata_re <= csrbank2_dfii_pi3_rddata_re;
- if (sys_rst) begin
- a7ddrphy_rst_storage <= 1'd0;
- a7ddrphy_rst_re <= 1'd0;
- a7ddrphy_dly_sel_storage <= 2'd0;
- a7ddrphy_dly_sel_re <= 1'd0;
- a7ddrphy_half_sys8x_taps_storage <= 5'd8;
- a7ddrphy_half_sys8x_taps_re <= 1'd0;
- a7ddrphy_wlevel_en_storage <= 1'd0;
- a7ddrphy_wlevel_en_re <= 1'd0;
- a7ddrphy_rdphase_storage <= 2'd2;
- a7ddrphy_rdphase_re <= 1'd0;
- a7ddrphy_wrphase_storage <= 2'd3;
- a7ddrphy_wrphase_re <= 1'd0;
- a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
- a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
- a7ddrphy_dqspattern_o1 <= 8'd0;
- a7ddrphy_bitslip0_value0 <= 3'd7;
- a7ddrphy_bitslip1_value0 <= 3'd7;
- a7ddrphy_bitslip0_value1 <= 3'd7;
- a7ddrphy_bitslip1_value1 <= 3'd7;
- a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
- a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
- a7ddrphy_bitslip0_value2 <= 3'd7;
- a7ddrphy_bitslip0_value3 <= 3'd7;
- a7ddrphy_bitslip1_value2 <= 3'd7;
- a7ddrphy_bitslip1_value3 <= 3'd7;
- a7ddrphy_bitslip2_value0 <= 3'd7;
- a7ddrphy_bitslip2_value1 <= 3'd7;
- a7ddrphy_bitslip3_value0 <= 3'd7;
- a7ddrphy_bitslip3_value1 <= 3'd7;
- a7ddrphy_bitslip4_value0 <= 3'd7;
- a7ddrphy_bitslip4_value1 <= 3'd7;
- a7ddrphy_bitslip5_value0 <= 3'd7;
- a7ddrphy_bitslip5_value1 <= 3'd7;
- a7ddrphy_bitslip6_value0 <= 3'd7;
- a7ddrphy_bitslip6_value1 <= 3'd7;
- a7ddrphy_bitslip7_value0 <= 3'd7;
- a7ddrphy_bitslip7_value1 <= 3'd7;
- a7ddrphy_bitslip8_value0 <= 3'd7;
- a7ddrphy_bitslip8_value1 <= 3'd7;
- a7ddrphy_bitslip9_value0 <= 3'd7;
- a7ddrphy_bitslip9_value1 <= 3'd7;
- a7ddrphy_bitslip10_value0 <= 3'd7;
- a7ddrphy_bitslip10_value1 <= 3'd7;
- a7ddrphy_bitslip11_value0 <= 3'd7;
- a7ddrphy_bitslip11_value1 <= 3'd7;
- a7ddrphy_bitslip12_value0 <= 3'd7;
- a7ddrphy_bitslip12_value1 <= 3'd7;
- a7ddrphy_bitslip13_value0 <= 3'd7;
- a7ddrphy_bitslip13_value1 <= 3'd7;
- a7ddrphy_bitslip14_value0 <= 3'd7;
- a7ddrphy_bitslip14_value1 <= 3'd7;
- a7ddrphy_bitslip15_value0 <= 3'd7;
- a7ddrphy_bitslip15_value1 <= 3'd7;
- a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0;
- a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0;
- a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0;
- a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0;
- a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0;
- a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0;
- a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0;
- a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0;
- a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0;
- a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0;
- a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0;
- litedramcore_storage <= 4'd1;
- litedramcore_re <= 1'd0;
- litedramcore_phaseinjector0_command_storage <= 6'd0;
- litedramcore_phaseinjector0_command_re <= 1'd0;
- litedramcore_phaseinjector0_address_re <= 1'd0;
- litedramcore_phaseinjector0_baddress_re <= 1'd0;
- litedramcore_phaseinjector0_wrdata_re <= 1'd0;
- litedramcore_phaseinjector0_rddata_status <= 32'd0;
- litedramcore_phaseinjector0_rddata_re <= 1'd0;
- litedramcore_phaseinjector1_command_storage <= 6'd0;
- litedramcore_phaseinjector1_command_re <= 1'd0;
- litedramcore_phaseinjector1_address_re <= 1'd0;
- litedramcore_phaseinjector1_baddress_re <= 1'd0;
- litedramcore_phaseinjector1_wrdata_re <= 1'd0;
- litedramcore_phaseinjector1_rddata_status <= 32'd0;
- litedramcore_phaseinjector1_rddata_re <= 1'd0;
- litedramcore_phaseinjector2_command_storage <= 6'd0;
- litedramcore_phaseinjector2_command_re <= 1'd0;
- litedramcore_phaseinjector2_address_re <= 1'd0;
- litedramcore_phaseinjector2_baddress_re <= 1'd0;
- litedramcore_phaseinjector2_wrdata_re <= 1'd0;
- litedramcore_phaseinjector2_rddata_status <= 32'd0;
- litedramcore_phaseinjector2_rddata_re <= 1'd0;
- litedramcore_phaseinjector3_command_storage <= 6'd0;
- litedramcore_phaseinjector3_command_re <= 1'd0;
- litedramcore_phaseinjector3_address_re <= 1'd0;
- litedramcore_phaseinjector3_baddress_re <= 1'd0;
- litedramcore_phaseinjector3_wrdata_re <= 1'd0;
- litedramcore_phaseinjector3_rddata_status <= 32'd0;
- litedramcore_phaseinjector3_rddata_re <= 1'd0;
- litedramcore_dfi_p0_address <= 15'd0;
- litedramcore_dfi_p0_bank <= 3'd0;
- litedramcore_dfi_p0_cas_n <= 1'd1;
- litedramcore_dfi_p0_cs_n <= 1'd1;
- litedramcore_dfi_p0_ras_n <= 1'd1;
- litedramcore_dfi_p0_we_n <= 1'd1;
- litedramcore_dfi_p0_wrdata_en <= 1'd0;
- litedramcore_dfi_p0_rddata_en <= 1'd0;
- litedramcore_dfi_p1_address <= 15'd0;
- litedramcore_dfi_p1_bank <= 3'd0;
- litedramcore_dfi_p1_cas_n <= 1'd1;
- litedramcore_dfi_p1_cs_n <= 1'd1;
- litedramcore_dfi_p1_ras_n <= 1'd1;
- litedramcore_dfi_p1_we_n <= 1'd1;
- litedramcore_dfi_p1_wrdata_en <= 1'd0;
- litedramcore_dfi_p1_rddata_en <= 1'd0;
- litedramcore_dfi_p2_address <= 15'd0;
- litedramcore_dfi_p2_bank <= 3'd0;
- litedramcore_dfi_p2_cas_n <= 1'd1;
- litedramcore_dfi_p2_cs_n <= 1'd1;
- litedramcore_dfi_p2_ras_n <= 1'd1;
- litedramcore_dfi_p2_we_n <= 1'd1;
- litedramcore_dfi_p2_wrdata_en <= 1'd0;
- litedramcore_dfi_p2_rddata_en <= 1'd0;
- litedramcore_dfi_p3_address <= 15'd0;
- litedramcore_dfi_p3_bank <= 3'd0;
- litedramcore_dfi_p3_cas_n <= 1'd1;
- litedramcore_dfi_p3_cs_n <= 1'd1;
- litedramcore_dfi_p3_ras_n <= 1'd1;
- litedramcore_dfi_p3_we_n <= 1'd1;
- litedramcore_dfi_p3_wrdata_en <= 1'd0;
- litedramcore_dfi_p3_rddata_en <= 1'd0;
- litedramcore_cmd_payload_a <= 15'd0;
- litedramcore_cmd_payload_ba <= 3'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd0;
- litedramcore_cmd_payload_we <= 1'd0;
- litedramcore_timer_count1 <= 10'd781;
- litedramcore_postponer_req_o <= 1'd0;
- litedramcore_postponer_count <= 1'd0;
- litedramcore_sequencer_done1 <= 1'd0;
- litedramcore_sequencer_counter <= 6'd0;
- litedramcore_sequencer_count <= 1'd0;
- litedramcore_zqcs_timer_count1 <= 27'd99999999;
- litedramcore_zqcs_executer_done <= 1'd0;
- litedramcore_zqcs_executer_counter <= 5'd0;
- litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine0_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= 22'd0;
- litedramcore_bankmachine0_row <= 15'd0;
- litedramcore_bankmachine0_row_opened <= 1'd0;
- litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine0_twtpcon_count <= 3'd0;
- litedramcore_bankmachine0_trccon_ready <= 1'd0;
- litedramcore_bankmachine0_trccon_count <= 3'd0;
- litedramcore_bankmachine0_trascon_ready <= 1'd0;
- litedramcore_bankmachine0_trascon_count <= 3'd0;
- litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine1_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= 22'd0;
- litedramcore_bankmachine1_row <= 15'd0;
- litedramcore_bankmachine1_row_opened <= 1'd0;
- litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine1_twtpcon_count <= 3'd0;
- litedramcore_bankmachine1_trccon_ready <= 1'd0;
- litedramcore_bankmachine1_trccon_count <= 3'd0;
- litedramcore_bankmachine1_trascon_ready <= 1'd0;
- litedramcore_bankmachine1_trascon_count <= 3'd0;
- litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine2_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= 22'd0;
- litedramcore_bankmachine2_row <= 15'd0;
- litedramcore_bankmachine2_row_opened <= 1'd0;
- litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine2_twtpcon_count <= 3'd0;
- litedramcore_bankmachine2_trccon_ready <= 1'd0;
- litedramcore_bankmachine2_trccon_count <= 3'd0;
- litedramcore_bankmachine2_trascon_ready <= 1'd0;
- litedramcore_bankmachine2_trascon_count <= 3'd0;
- litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine3_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= 22'd0;
- litedramcore_bankmachine3_row <= 15'd0;
- litedramcore_bankmachine3_row_opened <= 1'd0;
- litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine3_twtpcon_count <= 3'd0;
- litedramcore_bankmachine3_trccon_ready <= 1'd0;
- litedramcore_bankmachine3_trccon_count <= 3'd0;
- litedramcore_bankmachine3_trascon_ready <= 1'd0;
- litedramcore_bankmachine3_trascon_count <= 3'd0;
- litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine4_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= 22'd0;
- litedramcore_bankmachine4_row <= 15'd0;
- litedramcore_bankmachine4_row_opened <= 1'd0;
- litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine4_twtpcon_count <= 3'd0;
- litedramcore_bankmachine4_trccon_ready <= 1'd0;
- litedramcore_bankmachine4_trccon_count <= 3'd0;
- litedramcore_bankmachine4_trascon_ready <= 1'd0;
- litedramcore_bankmachine4_trascon_count <= 3'd0;
- litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine5_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= 22'd0;
- litedramcore_bankmachine5_row <= 15'd0;
- litedramcore_bankmachine5_row_opened <= 1'd0;
- litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine5_twtpcon_count <= 3'd0;
- litedramcore_bankmachine5_trccon_ready <= 1'd0;
- litedramcore_bankmachine5_trccon_count <= 3'd0;
- litedramcore_bankmachine5_trascon_ready <= 1'd0;
- litedramcore_bankmachine5_trascon_count <= 3'd0;
- litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine6_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= 22'd0;
- litedramcore_bankmachine6_row <= 15'd0;
- litedramcore_bankmachine6_row_opened <= 1'd0;
- litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine6_twtpcon_count <= 3'd0;
- litedramcore_bankmachine6_trccon_ready <= 1'd0;
- litedramcore_bankmachine6_trccon_count <= 3'd0;
- litedramcore_bankmachine6_trascon_ready <= 1'd0;
- litedramcore_bankmachine6_trascon_count <= 3'd0;
- litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine7_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= 22'd0;
- litedramcore_bankmachine7_row <= 15'd0;
- litedramcore_bankmachine7_row_opened <= 1'd0;
- litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine7_twtpcon_count <= 3'd0;
- litedramcore_bankmachine7_trccon_ready <= 1'd0;
- litedramcore_bankmachine7_trccon_count <= 3'd0;
- litedramcore_bankmachine7_trascon_ready <= 1'd0;
- litedramcore_bankmachine7_trascon_count <= 3'd0;
- litedramcore_choose_cmd_grant <= 3'd0;
- litedramcore_choose_req_grant <= 3'd0;
- litedramcore_trrdcon_ready <= 1'd0;
- litedramcore_trrdcon_count <= 1'd0;
- litedramcore_tfawcon_ready <= 1'd1;
- litedramcore_tfawcon_window <= 5'd0;
- litedramcore_tccdcon_ready <= 1'd0;
- litedramcore_tccdcon_count <= 1'd0;
- litedramcore_twtrcon_ready <= 1'd0;
- litedramcore_twtrcon_count <= 3'd0;
- litedramcore_time0 <= 5'd0;
- litedramcore_time1 <= 4'd0;
- init_done_storage <= 1'd0;
- init_done_re <= 1'd0;
- init_error_storage <= 1'd0;
- init_error_re <= 1'd0;
- litedramcore_we <= 1'd0;
- litedramcore_refresher_state <= 2'd0;
- litedramcore_bankmachine0_state <= 4'd0;
- litedramcore_bankmachine1_state <= 4'd0;
- litedramcore_bankmachine2_state <= 4'd0;
- litedramcore_bankmachine3_state <= 4'd0;
- litedramcore_bankmachine4_state <= 4'd0;
- litedramcore_bankmachine5_state <= 4'd0;
- litedramcore_bankmachine6_state <= 4'd0;
- litedramcore_bankmachine7_state <= 4'd0;
- litedramcore_multiplexer_state <= 4'd0;
- litedramcore_new_master_wdata_ready0 <= 1'd0;
- litedramcore_new_master_wdata_ready1 <= 1'd0;
- litedramcore_new_master_rdata_valid0 <= 1'd0;
- litedramcore_new_master_rdata_valid1 <= 1'd0;
- litedramcore_new_master_rdata_valid2 <= 1'd0;
- litedramcore_new_master_rdata_valid3 <= 1'd0;
- litedramcore_new_master_rdata_valid4 <= 1'd0;
- litedramcore_new_master_rdata_valid5 <= 1'd0;
- litedramcore_new_master_rdata_valid6 <= 1'd0;
- litedramcore_new_master_rdata_valid7 <= 1'd0;
- litedramcore_new_master_rdata_valid8 <= 1'd0;
- litedramcore_state <= 2'd0;
- end
+ a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dqs_oe_delay_tappeddelayline;
+ a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0;
+ a7ddrphy_dqspattern_o1 <= a7ddrphy_dqspattern_o0;
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip0_value0 <= (a7ddrphy_bitslip0_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip0_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip0_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip0_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip1_value0 <= (a7ddrphy_bitslip1_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip1_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip1_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip1_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip0_value1 <= (a7ddrphy_bitslip0_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip0_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip0_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[2], a7ddrphy_dfi_p3_wrdata_mask[0], a7ddrphy_dfi_p2_wrdata_mask[2], a7ddrphy_dfi_p2_wrdata_mask[0], a7ddrphy_dfi_p1_wrdata_mask[2], a7ddrphy_dfi_p1_wrdata_mask[0], a7ddrphy_dfi_p0_wrdata_mask[2], a7ddrphy_dfi_p0_wrdata_mask[0]}, a7ddrphy_bitslip0_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip1_value1 <= (a7ddrphy_bitslip1_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip1_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip1_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[3], a7ddrphy_dfi_p3_wrdata_mask[1], a7ddrphy_dfi_p2_wrdata_mask[3], a7ddrphy_dfi_p2_wrdata_mask[1], a7ddrphy_dfi_p1_wrdata_mask[3], a7ddrphy_dfi_p1_wrdata_mask[1], a7ddrphy_dfi_p0_wrdata_mask[3], a7ddrphy_dfi_p0_wrdata_mask[1]}, a7ddrphy_bitslip1_r1[15:8]};
+ a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dq_oe_delay_tappeddelayline;
+ a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0;
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip0_value2 <= (a7ddrphy_bitslip0_value2 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip0_value2 <= 3'd7;
+ end
+ a7ddrphy_bitslip0_r2 <= {{a7ddrphy_dfi_p3_wrdata[16], a7ddrphy_dfi_p3_wrdata[0], a7ddrphy_dfi_p2_wrdata[16], a7ddrphy_dfi_p2_wrdata[0], a7ddrphy_dfi_p1_wrdata[16], a7ddrphy_dfi_p1_wrdata[0], a7ddrphy_dfi_p0_wrdata[16], a7ddrphy_dfi_p0_wrdata[0]}, a7ddrphy_bitslip0_r2[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip0_value3 <= (a7ddrphy_bitslip0_value3 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip0_value3 <= 3'd7;
+ end
+ a7ddrphy_bitslip0_r3 <= {a7ddrphy_bitslip03, a7ddrphy_bitslip0_r3[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip1_value2 <= (a7ddrphy_bitslip1_value2 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip1_value2 <= 3'd7;
+ end
+ a7ddrphy_bitslip1_r2 <= {{a7ddrphy_dfi_p3_wrdata[17], a7ddrphy_dfi_p3_wrdata[1], a7ddrphy_dfi_p2_wrdata[17], a7ddrphy_dfi_p2_wrdata[1], a7ddrphy_dfi_p1_wrdata[17], a7ddrphy_dfi_p1_wrdata[1], a7ddrphy_dfi_p0_wrdata[17], a7ddrphy_dfi_p0_wrdata[1]}, a7ddrphy_bitslip1_r2[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip1_value3 <= (a7ddrphy_bitslip1_value3 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip1_value3 <= 3'd7;
+ end
+ a7ddrphy_bitslip1_r3 <= {a7ddrphy_bitslip13, a7ddrphy_bitslip1_r3[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip2_value0 <= (a7ddrphy_bitslip2_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip2_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip2_r0 <= {{a7ddrphy_dfi_p3_wrdata[18], a7ddrphy_dfi_p3_wrdata[2], a7ddrphy_dfi_p2_wrdata[18], a7ddrphy_dfi_p2_wrdata[2], a7ddrphy_dfi_p1_wrdata[18], a7ddrphy_dfi_p1_wrdata[2], a7ddrphy_dfi_p0_wrdata[18], a7ddrphy_dfi_p0_wrdata[2]}, a7ddrphy_bitslip2_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip2_value1 <= (a7ddrphy_bitslip2_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip2_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip2_r1 <= {a7ddrphy_bitslip21, a7ddrphy_bitslip2_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip3_value0 <= (a7ddrphy_bitslip3_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip3_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip3_r0 <= {{a7ddrphy_dfi_p3_wrdata[19], a7ddrphy_dfi_p3_wrdata[3], a7ddrphy_dfi_p2_wrdata[19], a7ddrphy_dfi_p2_wrdata[3], a7ddrphy_dfi_p1_wrdata[19], a7ddrphy_dfi_p1_wrdata[3], a7ddrphy_dfi_p0_wrdata[19], a7ddrphy_dfi_p0_wrdata[3]}, a7ddrphy_bitslip3_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip3_value1 <= (a7ddrphy_bitslip3_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip3_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip3_r1 <= {a7ddrphy_bitslip31, a7ddrphy_bitslip3_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip4_value0 <= (a7ddrphy_bitslip4_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip4_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip4_r0 <= {{a7ddrphy_dfi_p3_wrdata[20], a7ddrphy_dfi_p3_wrdata[4], a7ddrphy_dfi_p2_wrdata[20], a7ddrphy_dfi_p2_wrdata[4], a7ddrphy_dfi_p1_wrdata[20], a7ddrphy_dfi_p1_wrdata[4], a7ddrphy_dfi_p0_wrdata[20], a7ddrphy_dfi_p0_wrdata[4]}, a7ddrphy_bitslip4_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip4_value1 <= (a7ddrphy_bitslip4_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip4_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip4_r1 <= {a7ddrphy_bitslip41, a7ddrphy_bitslip4_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip5_value0 <= (a7ddrphy_bitslip5_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip5_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip5_r0 <= {{a7ddrphy_dfi_p3_wrdata[21], a7ddrphy_dfi_p3_wrdata[5], a7ddrphy_dfi_p2_wrdata[21], a7ddrphy_dfi_p2_wrdata[5], a7ddrphy_dfi_p1_wrdata[21], a7ddrphy_dfi_p1_wrdata[5], a7ddrphy_dfi_p0_wrdata[21], a7ddrphy_dfi_p0_wrdata[5]}, a7ddrphy_bitslip5_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip5_value1 <= (a7ddrphy_bitslip5_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip5_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip5_r1 <= {a7ddrphy_bitslip51, a7ddrphy_bitslip5_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip6_value0 <= (a7ddrphy_bitslip6_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip6_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip6_r0 <= {{a7ddrphy_dfi_p3_wrdata[22], a7ddrphy_dfi_p3_wrdata[6], a7ddrphy_dfi_p2_wrdata[22], a7ddrphy_dfi_p2_wrdata[6], a7ddrphy_dfi_p1_wrdata[22], a7ddrphy_dfi_p1_wrdata[6], a7ddrphy_dfi_p0_wrdata[22], a7ddrphy_dfi_p0_wrdata[6]}, a7ddrphy_bitslip6_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip6_value1 <= (a7ddrphy_bitslip6_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip6_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip6_r1 <= {a7ddrphy_bitslip61, a7ddrphy_bitslip6_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip7_value0 <= (a7ddrphy_bitslip7_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip7_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip7_r0 <= {{a7ddrphy_dfi_p3_wrdata[23], a7ddrphy_dfi_p3_wrdata[7], a7ddrphy_dfi_p2_wrdata[23], a7ddrphy_dfi_p2_wrdata[7], a7ddrphy_dfi_p1_wrdata[23], a7ddrphy_dfi_p1_wrdata[7], a7ddrphy_dfi_p0_wrdata[23], a7ddrphy_dfi_p0_wrdata[7]}, a7ddrphy_bitslip7_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip7_value1 <= (a7ddrphy_bitslip7_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip7_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip7_r1 <= {a7ddrphy_bitslip71, a7ddrphy_bitslip7_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip8_value0 <= (a7ddrphy_bitslip8_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip8_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip8_r0 <= {{a7ddrphy_dfi_p3_wrdata[24], a7ddrphy_dfi_p3_wrdata[8], a7ddrphy_dfi_p2_wrdata[24], a7ddrphy_dfi_p2_wrdata[8], a7ddrphy_dfi_p1_wrdata[24], a7ddrphy_dfi_p1_wrdata[8], a7ddrphy_dfi_p0_wrdata[24], a7ddrphy_dfi_p0_wrdata[8]}, a7ddrphy_bitslip8_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip8_value1 <= (a7ddrphy_bitslip8_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip8_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip8_r1 <= {a7ddrphy_bitslip81, a7ddrphy_bitslip8_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip9_value0 <= (a7ddrphy_bitslip9_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip9_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip9_r0 <= {{a7ddrphy_dfi_p3_wrdata[25], a7ddrphy_dfi_p3_wrdata[9], a7ddrphy_dfi_p2_wrdata[25], a7ddrphy_dfi_p2_wrdata[9], a7ddrphy_dfi_p1_wrdata[25], a7ddrphy_dfi_p1_wrdata[9], a7ddrphy_dfi_p0_wrdata[25], a7ddrphy_dfi_p0_wrdata[9]}, a7ddrphy_bitslip9_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip9_value1 <= (a7ddrphy_bitslip9_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip9_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip9_r1 <= {a7ddrphy_bitslip91, a7ddrphy_bitslip9_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip10_value0 <= (a7ddrphy_bitslip10_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip10_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip10_r0 <= {{a7ddrphy_dfi_p3_wrdata[26], a7ddrphy_dfi_p3_wrdata[10], a7ddrphy_dfi_p2_wrdata[26], a7ddrphy_dfi_p2_wrdata[10], a7ddrphy_dfi_p1_wrdata[26], a7ddrphy_dfi_p1_wrdata[10], a7ddrphy_dfi_p0_wrdata[26], a7ddrphy_dfi_p0_wrdata[10]}, a7ddrphy_bitslip10_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip10_value1 <= (a7ddrphy_bitslip10_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip10_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip10_r1 <= {a7ddrphy_bitslip101, a7ddrphy_bitslip10_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip11_value0 <= (a7ddrphy_bitslip11_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip11_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip11_r0 <= {{a7ddrphy_dfi_p3_wrdata[27], a7ddrphy_dfi_p3_wrdata[11], a7ddrphy_dfi_p2_wrdata[27], a7ddrphy_dfi_p2_wrdata[11], a7ddrphy_dfi_p1_wrdata[27], a7ddrphy_dfi_p1_wrdata[11], a7ddrphy_dfi_p0_wrdata[27], a7ddrphy_dfi_p0_wrdata[11]}, a7ddrphy_bitslip11_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip11_value1 <= (a7ddrphy_bitslip11_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip11_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip11_r1 <= {a7ddrphy_bitslip111, a7ddrphy_bitslip11_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip12_value0 <= (a7ddrphy_bitslip12_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip12_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip12_r0 <= {{a7ddrphy_dfi_p3_wrdata[28], a7ddrphy_dfi_p3_wrdata[12], a7ddrphy_dfi_p2_wrdata[28], a7ddrphy_dfi_p2_wrdata[12], a7ddrphy_dfi_p1_wrdata[28], a7ddrphy_dfi_p1_wrdata[12], a7ddrphy_dfi_p0_wrdata[28], a7ddrphy_dfi_p0_wrdata[12]}, a7ddrphy_bitslip12_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip12_value1 <= (a7ddrphy_bitslip12_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip12_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip12_r1 <= {a7ddrphy_bitslip121, a7ddrphy_bitslip12_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip13_value0 <= (a7ddrphy_bitslip13_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip13_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip13_r0 <= {{a7ddrphy_dfi_p3_wrdata[29], a7ddrphy_dfi_p3_wrdata[13], a7ddrphy_dfi_p2_wrdata[29], a7ddrphy_dfi_p2_wrdata[13], a7ddrphy_dfi_p1_wrdata[29], a7ddrphy_dfi_p1_wrdata[13], a7ddrphy_dfi_p0_wrdata[29], a7ddrphy_dfi_p0_wrdata[13]}, a7ddrphy_bitslip13_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip13_value1 <= (a7ddrphy_bitslip13_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip13_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip13_r1 <= {a7ddrphy_bitslip131, a7ddrphy_bitslip13_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip14_value0 <= (a7ddrphy_bitslip14_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip14_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip14_r0 <= {{a7ddrphy_dfi_p3_wrdata[30], a7ddrphy_dfi_p3_wrdata[14], a7ddrphy_dfi_p2_wrdata[30], a7ddrphy_dfi_p2_wrdata[14], a7ddrphy_dfi_p1_wrdata[30], a7ddrphy_dfi_p1_wrdata[14], a7ddrphy_dfi_p0_wrdata[30], a7ddrphy_dfi_p0_wrdata[14]}, a7ddrphy_bitslip14_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip14_value1 <= (a7ddrphy_bitslip14_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip14_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip14_r1 <= {a7ddrphy_bitslip141, a7ddrphy_bitslip14_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip15_value0 <= (a7ddrphy_bitslip15_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip15_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip15_r0 <= {{a7ddrphy_dfi_p3_wrdata[31], a7ddrphy_dfi_p3_wrdata[15], a7ddrphy_dfi_p2_wrdata[31], a7ddrphy_dfi_p2_wrdata[15], a7ddrphy_dfi_p1_wrdata[31], a7ddrphy_dfi_p1_wrdata[15], a7ddrphy_dfi_p0_wrdata[31], a7ddrphy_dfi_p0_wrdata[15]}, a7ddrphy_bitslip15_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip15_value1 <= (a7ddrphy_bitslip15_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip15_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip15_r1 <= {a7ddrphy_bitslip151, a7ddrphy_bitslip15_r1[15:8]};
+ a7ddrphy_rddata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_rddata_en | a7ddrphy_dfi_p1_rddata_en) | a7ddrphy_dfi_p2_rddata_en) | a7ddrphy_dfi_p3_rddata_en);
+ a7ddrphy_rddata_en_tappeddelayline1 <= a7ddrphy_rddata_en_tappeddelayline0;
+ a7ddrphy_rddata_en_tappeddelayline2 <= a7ddrphy_rddata_en_tappeddelayline1;
+ a7ddrphy_rddata_en_tappeddelayline3 <= a7ddrphy_rddata_en_tappeddelayline2;
+ a7ddrphy_rddata_en_tappeddelayline4 <= a7ddrphy_rddata_en_tappeddelayline3;
+ a7ddrphy_rddata_en_tappeddelayline5 <= a7ddrphy_rddata_en_tappeddelayline4;
+ a7ddrphy_rddata_en_tappeddelayline6 <= a7ddrphy_rddata_en_tappeddelayline5;
+ a7ddrphy_rddata_en_tappeddelayline7 <= a7ddrphy_rddata_en_tappeddelayline6;
+ a7ddrphy_wrdata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_wrdata_en | a7ddrphy_dfi_p1_wrdata_en) | a7ddrphy_dfi_p2_wrdata_en) | a7ddrphy_dfi_p3_wrdata_en);
+ a7ddrphy_wrdata_en_tappeddelayline1 <= a7ddrphy_wrdata_en_tappeddelayline0;
+ a7ddrphy_wrdata_en_tappeddelayline2 <= a7ddrphy_wrdata_en_tappeddelayline1;
+ if (litedramcore_csr_dfi_p0_rddata_valid) begin
+ litedramcore_phaseinjector0_rddata_status <= litedramcore_csr_dfi_p0_rddata;
+ end
+ if (litedramcore_csr_dfi_p1_rddata_valid) begin
+ litedramcore_phaseinjector1_rddata_status <= litedramcore_csr_dfi_p1_rddata;
+ end
+ if (litedramcore_csr_dfi_p2_rddata_valid) begin
+ litedramcore_phaseinjector2_rddata_status <= litedramcore_csr_dfi_p2_rddata;
+ end
+ if (litedramcore_csr_dfi_p3_rddata_valid) begin
+ litedramcore_phaseinjector3_rddata_status <= litedramcore_csr_dfi_p3_rddata;
+ end
+ if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin
+ litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1);
+ end else begin
+ litedramcore_timer_count1 <= 10'd781;
+ end
+ litedramcore_postponer_req_o <= 1'd0;
+ if (litedramcore_postponer_req_i) begin
+ litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1);
+ if ((litedramcore_postponer_count == 1'd0)) begin
+ litedramcore_postponer_count <= 1'd0;
+ litedramcore_postponer_req_o <= 1'd1;
+ end
+ end
+ if (litedramcore_sequencer_start0) begin
+ litedramcore_sequencer_count <= 1'd0;
+ end else begin
+ if (litedramcore_sequencer_done1) begin
+ if ((litedramcore_sequencer_count != 1'd0)) begin
+ litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1);
+ end
+ end
+ end
+ litedramcore_cmd_payload_a <= 1'd0;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd0;
+ litedramcore_cmd_payload_we <= 1'd0;
+ litedramcore_sequencer_done1 <= 1'd0;
+ if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin
+ litedramcore_cmd_payload_a <= 11'd1024;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd1;
+ litedramcore_cmd_payload_we <= 1'd1;
+ end
+ if ((litedramcore_sequencer_counter == 2'd3)) begin
+ litedramcore_cmd_payload_a <= 11'd1024;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd1;
+ litedramcore_cmd_payload_ras <= 1'd1;
+ litedramcore_cmd_payload_we <= 1'd0;
+ end
+ if ((litedramcore_sequencer_counter == 6'd55)) begin
+ litedramcore_cmd_payload_a <= 1'd0;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd0;
+ litedramcore_cmd_payload_we <= 1'd0;
+ litedramcore_sequencer_done1 <= 1'd1;
+ end
+ if ((litedramcore_sequencer_counter == 6'd55)) begin
+ litedramcore_sequencer_counter <= 1'd0;
+ end else begin
+ if ((litedramcore_sequencer_counter != 1'd0)) begin
+ litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1);
+ end else begin
+ if (litedramcore_sequencer_start1) begin
+ litedramcore_sequencer_counter <= 1'd1;
+ end
+ end
+ end
+ if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin
+ litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1);
+ end else begin
+ litedramcore_zqcs_timer_count1 <= 27'd99999999;
+ end
+ litedramcore_zqcs_executer_done <= 1'd0;
+ if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin
+ litedramcore_cmd_payload_a <= 11'd1024;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd1;
+ litedramcore_cmd_payload_we <= 1'd1;
+ end
+ if ((litedramcore_zqcs_executer_counter == 2'd3)) begin
+ litedramcore_cmd_payload_a <= 1'd0;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd0;
+ litedramcore_cmd_payload_we <= 1'd1;
+ end
+ if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
+ litedramcore_cmd_payload_a <= 1'd0;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd0;
+ litedramcore_cmd_payload_we <= 1'd0;
+ litedramcore_zqcs_executer_done <= 1'd1;
+ end
+ if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
+ litedramcore_zqcs_executer_counter <= 1'd0;
+ end else begin
+ if ((litedramcore_zqcs_executer_counter != 1'd0)) begin
+ litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1);
+ end else begin
+ if (litedramcore_zqcs_executer_start) begin
+ litedramcore_zqcs_executer_counter <= 1'd1;
+ end
+ end
+ end
+ litedramcore_refresher_state <= litedramcore_refresher_next_state;
+ if (litedramcore_bankmachine0_row_close) begin
+ litedramcore_bankmachine0_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine0_row_open) begin
+ litedramcore_bankmachine0_row_opened <= 1'd1;
+ litedramcore_bankmachine0_row <= litedramcore_bankmachine0_source_source_payload_addr[21:7];
+ end
+ end
+ if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin
+ litedramcore_bankmachine0_produce <= (litedramcore_bankmachine0_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine0_do_read) begin
+ litedramcore_bankmachine0_consume <= (litedramcore_bankmachine0_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin
+ if ((~litedramcore_bankmachine0_do_read)) begin
+ litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine0_do_read) begin
+ litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine0_pipe_valid_source_valid <= litedramcore_bankmachine0_pipe_valid_sink_valid;
+ litedramcore_bankmachine0_pipe_valid_source_first <= litedramcore_bankmachine0_pipe_valid_sink_first;
+ litedramcore_bankmachine0_pipe_valid_source_last <= litedramcore_bankmachine0_pipe_valid_sink_last;
+ litedramcore_bankmachine0_pipe_valid_source_payload_we <= litedramcore_bankmachine0_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine0_pipe_valid_source_payload_addr <= litedramcore_bankmachine0_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine0_twtpcon_valid) begin
+ litedramcore_bankmachine0_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine0_twtpcon_ready)) begin
+ litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine0_trccon_valid) begin
+ litedramcore_bankmachine0_trccon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine0_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine0_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine0_trccon_ready)) begin
+ litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine0_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine0_trascon_valid) begin
+ litedramcore_bankmachine0_trascon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_bankmachine0_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine0_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine0_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state;
+ if (litedramcore_bankmachine1_row_close) begin
+ litedramcore_bankmachine1_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine1_row_open) begin
+ litedramcore_bankmachine1_row_opened <= 1'd1;
+ litedramcore_bankmachine1_row <= litedramcore_bankmachine1_source_source_payload_addr[21:7];
+ end
+ end
+ if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin
+ litedramcore_bankmachine1_produce <= (litedramcore_bankmachine1_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine1_do_read) begin
+ litedramcore_bankmachine1_consume <= (litedramcore_bankmachine1_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin
+ if ((~litedramcore_bankmachine1_do_read)) begin
+ litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine1_do_read) begin
+ litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine1_pipe_valid_source_valid <= litedramcore_bankmachine1_pipe_valid_sink_valid;
+ litedramcore_bankmachine1_pipe_valid_source_first <= litedramcore_bankmachine1_pipe_valid_sink_first;
+ litedramcore_bankmachine1_pipe_valid_source_last <= litedramcore_bankmachine1_pipe_valid_sink_last;
+ litedramcore_bankmachine1_pipe_valid_source_payload_we <= litedramcore_bankmachine1_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine1_pipe_valid_source_payload_addr <= litedramcore_bankmachine1_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine1_twtpcon_valid) begin
+ litedramcore_bankmachine1_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine1_twtpcon_ready)) begin
+ litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine1_trccon_valid) begin
+ litedramcore_bankmachine1_trccon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine1_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine1_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine1_trccon_ready)) begin
+ litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine1_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine1_trascon_valid) begin
+ litedramcore_bankmachine1_trascon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_bankmachine1_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine1_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine1_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state;
+ if (litedramcore_bankmachine2_row_close) begin
+ litedramcore_bankmachine2_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine2_row_open) begin
+ litedramcore_bankmachine2_row_opened <= 1'd1;
+ litedramcore_bankmachine2_row <= litedramcore_bankmachine2_source_source_payload_addr[21:7];
+ end
+ end
+ if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin
+ litedramcore_bankmachine2_produce <= (litedramcore_bankmachine2_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine2_do_read) begin
+ litedramcore_bankmachine2_consume <= (litedramcore_bankmachine2_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin
+ if ((~litedramcore_bankmachine2_do_read)) begin
+ litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine2_do_read) begin
+ litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine2_pipe_valid_source_valid <= litedramcore_bankmachine2_pipe_valid_sink_valid;
+ litedramcore_bankmachine2_pipe_valid_source_first <= litedramcore_bankmachine2_pipe_valid_sink_first;
+ litedramcore_bankmachine2_pipe_valid_source_last <= litedramcore_bankmachine2_pipe_valid_sink_last;
+ litedramcore_bankmachine2_pipe_valid_source_payload_we <= litedramcore_bankmachine2_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine2_pipe_valid_source_payload_addr <= litedramcore_bankmachine2_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine2_twtpcon_valid) begin
+ litedramcore_bankmachine2_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine2_twtpcon_ready)) begin
+ litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine2_trccon_valid) begin
+ litedramcore_bankmachine2_trccon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine2_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine2_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine2_trccon_ready)) begin
+ litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine2_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine2_trascon_valid) begin
+ litedramcore_bankmachine2_trascon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_bankmachine2_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine2_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine2_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state;
+ if (litedramcore_bankmachine3_row_close) begin
+ litedramcore_bankmachine3_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine3_row_open) begin
+ litedramcore_bankmachine3_row_opened <= 1'd1;
+ litedramcore_bankmachine3_row <= litedramcore_bankmachine3_source_source_payload_addr[21:7];
+ end
+ end
+ if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin
+ litedramcore_bankmachine3_produce <= (litedramcore_bankmachine3_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine3_do_read) begin
+ litedramcore_bankmachine3_consume <= (litedramcore_bankmachine3_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin
+ if ((~litedramcore_bankmachine3_do_read)) begin
+ litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine3_do_read) begin
+ litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine3_pipe_valid_source_valid <= litedramcore_bankmachine3_pipe_valid_sink_valid;
+ litedramcore_bankmachine3_pipe_valid_source_first <= litedramcore_bankmachine3_pipe_valid_sink_first;
+ litedramcore_bankmachine3_pipe_valid_source_last <= litedramcore_bankmachine3_pipe_valid_sink_last;
+ litedramcore_bankmachine3_pipe_valid_source_payload_we <= litedramcore_bankmachine3_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine3_pipe_valid_source_payload_addr <= litedramcore_bankmachine3_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine3_twtpcon_valid) begin
+ litedramcore_bankmachine3_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine3_twtpcon_ready)) begin
+ litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine3_trccon_valid) begin
+ litedramcore_bankmachine3_trccon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine3_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine3_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine3_trccon_ready)) begin
+ litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine3_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine3_trascon_valid) begin
+ litedramcore_bankmachine3_trascon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_bankmachine3_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine3_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine3_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state;
+ if (litedramcore_bankmachine4_row_close) begin
+ litedramcore_bankmachine4_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine4_row_open) begin
+ litedramcore_bankmachine4_row_opened <= 1'd1;
+ litedramcore_bankmachine4_row <= litedramcore_bankmachine4_source_source_payload_addr[21:7];
+ end
+ end
+ if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin
+ litedramcore_bankmachine4_produce <= (litedramcore_bankmachine4_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine4_do_read) begin
+ litedramcore_bankmachine4_consume <= (litedramcore_bankmachine4_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin
+ if ((~litedramcore_bankmachine4_do_read)) begin
+ litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine4_do_read) begin
+ litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine4_pipe_valid_source_valid <= litedramcore_bankmachine4_pipe_valid_sink_valid;
+ litedramcore_bankmachine4_pipe_valid_source_first <= litedramcore_bankmachine4_pipe_valid_sink_first;
+ litedramcore_bankmachine4_pipe_valid_source_last <= litedramcore_bankmachine4_pipe_valid_sink_last;
+ litedramcore_bankmachine4_pipe_valid_source_payload_we <= litedramcore_bankmachine4_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine4_pipe_valid_source_payload_addr <= litedramcore_bankmachine4_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine4_twtpcon_valid) begin
+ litedramcore_bankmachine4_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine4_twtpcon_ready)) begin
+ litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine4_trccon_valid) begin
+ litedramcore_bankmachine4_trccon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine4_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine4_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine4_trccon_ready)) begin
+ litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine4_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine4_trascon_valid) begin
+ litedramcore_bankmachine4_trascon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_bankmachine4_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine4_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine4_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state;
+ if (litedramcore_bankmachine5_row_close) begin
+ litedramcore_bankmachine5_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine5_row_open) begin
+ litedramcore_bankmachine5_row_opened <= 1'd1;
+ litedramcore_bankmachine5_row <= litedramcore_bankmachine5_source_source_payload_addr[21:7];
+ end
+ end
+ if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin
+ litedramcore_bankmachine5_produce <= (litedramcore_bankmachine5_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine5_do_read) begin
+ litedramcore_bankmachine5_consume <= (litedramcore_bankmachine5_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin
+ if ((~litedramcore_bankmachine5_do_read)) begin
+ litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine5_do_read) begin
+ litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine5_pipe_valid_source_valid <= litedramcore_bankmachine5_pipe_valid_sink_valid;
+ litedramcore_bankmachine5_pipe_valid_source_first <= litedramcore_bankmachine5_pipe_valid_sink_first;
+ litedramcore_bankmachine5_pipe_valid_source_last <= litedramcore_bankmachine5_pipe_valid_sink_last;
+ litedramcore_bankmachine5_pipe_valid_source_payload_we <= litedramcore_bankmachine5_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine5_pipe_valid_source_payload_addr <= litedramcore_bankmachine5_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine5_twtpcon_valid) begin
+ litedramcore_bankmachine5_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine5_twtpcon_ready)) begin
+ litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine5_trccon_valid) begin
+ litedramcore_bankmachine5_trccon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine5_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine5_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine5_trccon_ready)) begin
+ litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine5_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine5_trascon_valid) begin
+ litedramcore_bankmachine5_trascon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_bankmachine5_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine5_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine5_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state;
+ if (litedramcore_bankmachine6_row_close) begin
+ litedramcore_bankmachine6_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine6_row_open) begin
+ litedramcore_bankmachine6_row_opened <= 1'd1;
+ litedramcore_bankmachine6_row <= litedramcore_bankmachine6_source_source_payload_addr[21:7];
+ end
+ end
+ if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin
+ litedramcore_bankmachine6_produce <= (litedramcore_bankmachine6_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine6_do_read) begin
+ litedramcore_bankmachine6_consume <= (litedramcore_bankmachine6_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin
+ if ((~litedramcore_bankmachine6_do_read)) begin
+ litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine6_do_read) begin
+ litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine6_pipe_valid_source_valid <= litedramcore_bankmachine6_pipe_valid_sink_valid;
+ litedramcore_bankmachine6_pipe_valid_source_first <= litedramcore_bankmachine6_pipe_valid_sink_first;
+ litedramcore_bankmachine6_pipe_valid_source_last <= litedramcore_bankmachine6_pipe_valid_sink_last;
+ litedramcore_bankmachine6_pipe_valid_source_payload_we <= litedramcore_bankmachine6_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine6_pipe_valid_source_payload_addr <= litedramcore_bankmachine6_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine6_twtpcon_valid) begin
+ litedramcore_bankmachine6_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine6_twtpcon_ready)) begin
+ litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine6_trccon_valid) begin
+ litedramcore_bankmachine6_trccon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine6_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine6_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine6_trccon_ready)) begin
+ litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine6_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine6_trascon_valid) begin
+ litedramcore_bankmachine6_trascon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_bankmachine6_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine6_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine6_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state;
+ if (litedramcore_bankmachine7_row_close) begin
+ litedramcore_bankmachine7_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine7_row_open) begin
+ litedramcore_bankmachine7_row_opened <= 1'd1;
+ litedramcore_bankmachine7_row <= litedramcore_bankmachine7_source_source_payload_addr[21:7];
+ end
+ end
+ if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin
+ litedramcore_bankmachine7_produce <= (litedramcore_bankmachine7_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine7_do_read) begin
+ litedramcore_bankmachine7_consume <= (litedramcore_bankmachine7_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin
+ if ((~litedramcore_bankmachine7_do_read)) begin
+ litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine7_do_read) begin
+ litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine7_pipe_valid_source_valid <= litedramcore_bankmachine7_pipe_valid_sink_valid;
+ litedramcore_bankmachine7_pipe_valid_source_first <= litedramcore_bankmachine7_pipe_valid_sink_first;
+ litedramcore_bankmachine7_pipe_valid_source_last <= litedramcore_bankmachine7_pipe_valid_sink_last;
+ litedramcore_bankmachine7_pipe_valid_source_payload_we <= litedramcore_bankmachine7_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine7_pipe_valid_source_payload_addr <= litedramcore_bankmachine7_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine7_twtpcon_valid) begin
+ litedramcore_bankmachine7_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine7_twtpcon_ready)) begin
+ litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine7_trccon_valid) begin
+ litedramcore_bankmachine7_trccon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine7_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine7_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine7_trccon_ready)) begin
+ litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine7_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine7_trascon_valid) begin
+ litedramcore_bankmachine7_trascon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_bankmachine7_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine7_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine7_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state;
+ if ((~litedramcore_en0)) begin
+ litedramcore_time0 <= 5'd31;
+ end else begin
+ if ((~litedramcore_max_time0)) begin
+ litedramcore_time0 <= (litedramcore_time0 - 1'd1);
+ end
+ end
+ if ((~litedramcore_en1)) begin
+ litedramcore_time1 <= 4'd15;
+ end else begin
+ if ((~litedramcore_max_time1)) begin
+ litedramcore_time1 <= (litedramcore_time1 - 1'd1);
+ end
+ end
+ if (litedramcore_choose_cmd_ce) begin
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 1'd1: begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 2'd2: begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd4: begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd5: begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd6: begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd7: begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ endcase
+ end
+ if (litedramcore_choose_req_ce) begin
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 1'd1: begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 2'd2: begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd4: begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd5: begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd6: begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd7: begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ endcase
+ end
+ litedramcore_dfi_p0_cs_n <= 1'd0;
+ litedramcore_dfi_p0_bank <= array_muxed0;
+ litedramcore_dfi_p0_address <= array_muxed1;
+ litedramcore_dfi_p0_cas_n <= (~array_muxed2);
+ litedramcore_dfi_p0_ras_n <= (~array_muxed3);
+ litedramcore_dfi_p0_we_n <= (~array_muxed4);
+ litedramcore_dfi_p0_rddata_en <= array_muxed5;
+ litedramcore_dfi_p0_wrdata_en <= array_muxed6;
+ litedramcore_dfi_p1_cs_n <= 1'd0;
+ litedramcore_dfi_p1_bank <= array_muxed7;
+ litedramcore_dfi_p1_address <= array_muxed8;
+ litedramcore_dfi_p1_cas_n <= (~array_muxed9);
+ litedramcore_dfi_p1_ras_n <= (~array_muxed10);
+ litedramcore_dfi_p1_we_n <= (~array_muxed11);
+ litedramcore_dfi_p1_rddata_en <= array_muxed12;
+ litedramcore_dfi_p1_wrdata_en <= array_muxed13;
+ litedramcore_dfi_p2_cs_n <= 1'd0;
+ litedramcore_dfi_p2_bank <= array_muxed14;
+ litedramcore_dfi_p2_address <= array_muxed15;
+ litedramcore_dfi_p2_cas_n <= (~array_muxed16);
+ litedramcore_dfi_p2_ras_n <= (~array_muxed17);
+ litedramcore_dfi_p2_we_n <= (~array_muxed18);
+ litedramcore_dfi_p2_rddata_en <= array_muxed19;
+ litedramcore_dfi_p2_wrdata_en <= array_muxed20;
+ litedramcore_dfi_p3_cs_n <= 1'd0;
+ litedramcore_dfi_p3_bank <= array_muxed21;
+ litedramcore_dfi_p3_address <= array_muxed22;
+ litedramcore_dfi_p3_cas_n <= (~array_muxed23);
+ litedramcore_dfi_p3_ras_n <= (~array_muxed24);
+ litedramcore_dfi_p3_we_n <= (~array_muxed25);
+ litedramcore_dfi_p3_rddata_en <= array_muxed26;
+ litedramcore_dfi_p3_wrdata_en <= array_muxed27;
+ if (litedramcore_trrdcon_valid) begin
+ litedramcore_trrdcon_count <= 1'd1;
+ if (1'd0) begin
+ litedramcore_trrdcon_ready <= 1'd1;
+ end else begin
+ litedramcore_trrdcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_trrdcon_ready)) begin
+ litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1);
+ if ((litedramcore_trrdcon_count == 1'd1)) begin
+ litedramcore_trrdcon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid};
+ if ((litedramcore_tfawcon_count < 3'd4)) begin
+ if ((litedramcore_tfawcon_count == 2'd3)) begin
+ litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid);
+ end else begin
+ litedramcore_tfawcon_ready <= 1'd1;
+ end
+ end
+ if (litedramcore_tccdcon_valid) begin
+ litedramcore_tccdcon_count <= 1'd0;
+ if (1'd1) begin
+ litedramcore_tccdcon_ready <= 1'd1;
+ end else begin
+ litedramcore_tccdcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_tccdcon_ready)) begin
+ litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1);
+ if ((litedramcore_tccdcon_count == 1'd1)) begin
+ litedramcore_tccdcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_twtrcon_valid) begin
+ litedramcore_twtrcon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_twtrcon_ready <= 1'd1;
+ end else begin
+ litedramcore_twtrcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_twtrcon_ready)) begin
+ litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1);
+ if ((litedramcore_twtrcon_count == 1'd1)) begin
+ litedramcore_twtrcon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state;
+ litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready));
+ litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0;
+ litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid));
+ litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0;
+ litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1;
+ litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2;
+ litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3;
+ litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4;
+ litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5;
+ litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6;
+ litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7;
+ litedramcore_state <= litedramcore_next_state;
+ if (litedramcore_dat_w_next_value_ce0) begin
+ litedramcore_dat_w <= litedramcore_dat_w_next_value0;
+ end
+ if (litedramcore_adr_next_value_ce1) begin
+ litedramcore_adr <= litedramcore_adr_next_value1;
+ end
+ if (litedramcore_we_next_value_ce2) begin
+ litedramcore_we <= litedramcore_we_next_value2;
+ end
+ interface0_bank_bus_dat_r <= 1'd0;
+ if (csrbank0_sel) begin
+ case (interface0_bank_bus_adr[8:0])
+ 1'd0: begin
+ interface0_bank_bus_dat_r <= csrbank0_init_done0_w;
+ end
+ 1'd1: begin
+ interface0_bank_bus_dat_r <= csrbank0_init_error0_w;
+ end
+ endcase
+ end
+ if (csrbank0_init_done0_re) begin
+ init_done_storage <= csrbank0_init_done0_r;
+ end
+ init_done_re <= csrbank0_init_done0_re;
+ if (csrbank0_init_error0_re) begin
+ init_error_storage <= csrbank0_init_error0_r;
+ end
+ init_error_re <= csrbank0_init_error0_re;
+ interface1_bank_bus_dat_r <= 1'd0;
+ if (csrbank1_sel) begin
+ case (interface1_bank_bus_adr[8:0])
+ 1'd0: begin
+ interface1_bank_bus_dat_r <= csrbank1_rst0_w;
+ end
+ 1'd1: begin
+ interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w;
+ end
+ 2'd2: begin
+ interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w;
+ end
+ 2'd3: begin
+ interface1_bank_bus_dat_r <= csrbank1_wlevel_en0_w;
+ end
+ 3'd4: begin
+ interface1_bank_bus_dat_r <= a7ddrphy_wlevel_strobe_w;
+ end
+ 3'd5: begin
+ interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_rst_w;
+ end
+ 3'd6: begin
+ interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_inc_w;
+ end
+ 3'd7: begin
+ interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_rst_w;
+ end
+ 4'd8: begin
+ interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_w;
+ end
+ 4'd9: begin
+ interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_rst_w;
+ end
+ 4'd10: begin
+ interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_w;
+ end
+ 4'd11: begin
+ interface1_bank_bus_dat_r <= csrbank1_rdphase0_w;
+ end
+ 4'd12: begin
+ interface1_bank_bus_dat_r <= csrbank1_wrphase0_w;
+ end
+ endcase
+ end
+ if (csrbank1_rst0_re) begin
+ a7ddrphy_rst_storage <= csrbank1_rst0_r;
+ end
+ a7ddrphy_rst_re <= csrbank1_rst0_re;
+ if (csrbank1_dly_sel0_re) begin
+ a7ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r;
+ end
+ a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re;
+ if (csrbank1_half_sys8x_taps0_re) begin
+ a7ddrphy_half_sys8x_taps_storage[4:0] <= csrbank1_half_sys8x_taps0_r;
+ end
+ a7ddrphy_half_sys8x_taps_re <= csrbank1_half_sys8x_taps0_re;
+ if (csrbank1_wlevel_en0_re) begin
+ a7ddrphy_wlevel_en_storage <= csrbank1_wlevel_en0_r;
+ end
+ a7ddrphy_wlevel_en_re <= csrbank1_wlevel_en0_re;
+ if (csrbank1_rdphase0_re) begin
+ a7ddrphy_rdphase_storage[1:0] <= csrbank1_rdphase0_r;
+ end
+ a7ddrphy_rdphase_re <= csrbank1_rdphase0_re;
+ if (csrbank1_wrphase0_re) begin
+ a7ddrphy_wrphase_storage[1:0] <= csrbank1_wrphase0_r;
+ end
+ a7ddrphy_wrphase_re <= csrbank1_wrphase0_re;
+ interface2_bank_bus_dat_r <= 1'd0;
+ if (csrbank2_sel) begin
+ case (interface2_bank_bus_adr[8:0])
+ 1'd0: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w;
+ end
+ 1'd1: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w;
+ end
+ 2'd2: begin
+ interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w;
+ end
+ 2'd3: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w;
+ end
+ 3'd4: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w;
+ end
+ 3'd5: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w;
+ end
+ 3'd6: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata_w;
+ end
+ 3'd7: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w;
+ end
+ 4'd8: begin
+ interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w;
+ end
+ 4'd9: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w;
+ end
+ 4'd10: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w;
+ end
+ 4'd11: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w;
+ end
+ 4'd12: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata_w;
+ end
+ 4'd13: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w;
+ end
+ 4'd14: begin
+ interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w;
+ end
+ 4'd15: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w;
+ end
+ 5'd16: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w;
+ end
+ 5'd17: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w;
+ end
+ 5'd18: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata_w;
+ end
+ 5'd19: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w;
+ end
+ 5'd20: begin
+ interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w;
+ end
+ 5'd21: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w;
+ end
+ 5'd22: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w;
+ end
+ 5'd23: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w;
+ end
+ 5'd24: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata_w;
+ end
+ endcase
+ end
+ if (csrbank2_dfii_control0_re) begin
+ litedramcore_storage[3:0] <= csrbank2_dfii_control0_r;
+ end
+ litedramcore_re <= csrbank2_dfii_control0_re;
+ if (csrbank2_dfii_pi0_command0_re) begin
+ litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r;
+ end
+ litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re;
+ if (csrbank2_dfii_pi0_address0_re) begin
+ litedramcore_phaseinjector0_address_storage[14:0] <= csrbank2_dfii_pi0_address0_r;
+ end
+ litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re;
+ if (csrbank2_dfii_pi0_baddress0_re) begin
+ litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r;
+ end
+ litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re;
+ if (csrbank2_dfii_pi0_wrdata0_re) begin
+ litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r;
+ end
+ litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re;
+ litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata_re;
+ if (csrbank2_dfii_pi1_command0_re) begin
+ litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r;
+ end
+ litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re;
+ if (csrbank2_dfii_pi1_address0_re) begin
+ litedramcore_phaseinjector1_address_storage[14:0] <= csrbank2_dfii_pi1_address0_r;
+ end
+ litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re;
+ if (csrbank2_dfii_pi1_baddress0_re) begin
+ litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r;
+ end
+ litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re;
+ if (csrbank2_dfii_pi1_wrdata0_re) begin
+ litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r;
+ end
+ litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re;
+ litedramcore_phaseinjector1_rddata_re <= csrbank2_dfii_pi1_rddata_re;
+ if (csrbank2_dfii_pi2_command0_re) begin
+ litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r;
+ end
+ litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re;
+ if (csrbank2_dfii_pi2_address0_re) begin
+ litedramcore_phaseinjector2_address_storage[14:0] <= csrbank2_dfii_pi2_address0_r;
+ end
+ litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re;
+ if (csrbank2_dfii_pi2_baddress0_re) begin
+ litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r;
+ end
+ litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re;
+ if (csrbank2_dfii_pi2_wrdata0_re) begin
+ litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r;
+ end
+ litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re;
+ litedramcore_phaseinjector2_rddata_re <= csrbank2_dfii_pi2_rddata_re;
+ if (csrbank2_dfii_pi3_command0_re) begin
+ litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r;
+ end
+ litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re;
+ if (csrbank2_dfii_pi3_address0_re) begin
+ litedramcore_phaseinjector3_address_storage[14:0] <= csrbank2_dfii_pi3_address0_r;
+ end
+ litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re;
+ if (csrbank2_dfii_pi3_baddress0_re) begin
+ litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r;
+ end
+ litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re;
+ if (csrbank2_dfii_pi3_wrdata0_re) begin
+ litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r;
+ end
+ litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re;
+ litedramcore_phaseinjector3_rddata_re <= csrbank2_dfii_pi3_rddata_re;
+ if (sys_rst) begin
+ a7ddrphy_rst_storage <= 1'd0;
+ a7ddrphy_rst_re <= 1'd0;
+ a7ddrphy_dly_sel_storage <= 2'd0;
+ a7ddrphy_dly_sel_re <= 1'd0;
+ a7ddrphy_half_sys8x_taps_storage <= 5'd8;
+ a7ddrphy_half_sys8x_taps_re <= 1'd0;
+ a7ddrphy_wlevel_en_storage <= 1'd0;
+ a7ddrphy_wlevel_en_re <= 1'd0;
+ a7ddrphy_rdphase_storage <= 2'd2;
+ a7ddrphy_rdphase_re <= 1'd0;
+ a7ddrphy_wrphase_storage <= 2'd3;
+ a7ddrphy_wrphase_re <= 1'd0;
+ a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
+ a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
+ a7ddrphy_dqspattern_o1 <= 8'd0;
+ a7ddrphy_bitslip0_value0 <= 3'd7;
+ a7ddrphy_bitslip1_value0 <= 3'd7;
+ a7ddrphy_bitslip0_value1 <= 3'd7;
+ a7ddrphy_bitslip1_value1 <= 3'd7;
+ a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
+ a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
+ a7ddrphy_bitslip0_value2 <= 3'd7;
+ a7ddrphy_bitslip0_value3 <= 3'd7;
+ a7ddrphy_bitslip1_value2 <= 3'd7;
+ a7ddrphy_bitslip1_value3 <= 3'd7;
+ a7ddrphy_bitslip2_value0 <= 3'd7;
+ a7ddrphy_bitslip2_value1 <= 3'd7;
+ a7ddrphy_bitslip3_value0 <= 3'd7;
+ a7ddrphy_bitslip3_value1 <= 3'd7;
+ a7ddrphy_bitslip4_value0 <= 3'd7;
+ a7ddrphy_bitslip4_value1 <= 3'd7;
+ a7ddrphy_bitslip5_value0 <= 3'd7;
+ a7ddrphy_bitslip5_value1 <= 3'd7;
+ a7ddrphy_bitslip6_value0 <= 3'd7;
+ a7ddrphy_bitslip6_value1 <= 3'd7;
+ a7ddrphy_bitslip7_value0 <= 3'd7;
+ a7ddrphy_bitslip7_value1 <= 3'd7;
+ a7ddrphy_bitslip8_value0 <= 3'd7;
+ a7ddrphy_bitslip8_value1 <= 3'd7;
+ a7ddrphy_bitslip9_value0 <= 3'd7;
+ a7ddrphy_bitslip9_value1 <= 3'd7;
+ a7ddrphy_bitslip10_value0 <= 3'd7;
+ a7ddrphy_bitslip10_value1 <= 3'd7;
+ a7ddrphy_bitslip11_value0 <= 3'd7;
+ a7ddrphy_bitslip11_value1 <= 3'd7;
+ a7ddrphy_bitslip12_value0 <= 3'd7;
+ a7ddrphy_bitslip12_value1 <= 3'd7;
+ a7ddrphy_bitslip13_value0 <= 3'd7;
+ a7ddrphy_bitslip13_value1 <= 3'd7;
+ a7ddrphy_bitslip14_value0 <= 3'd7;
+ a7ddrphy_bitslip14_value1 <= 3'd7;
+ a7ddrphy_bitslip15_value0 <= 3'd7;
+ a7ddrphy_bitslip15_value1 <= 3'd7;
+ a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0;
+ a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0;
+ a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0;
+ a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0;
+ a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0;
+ a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0;
+ a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0;
+ a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0;
+ a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0;
+ a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0;
+ a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0;
+ litedramcore_storage <= 4'd1;
+ litedramcore_re <= 1'd0;
+ litedramcore_phaseinjector0_command_storage <= 6'd0;
+ litedramcore_phaseinjector0_command_re <= 1'd0;
+ litedramcore_phaseinjector0_address_re <= 1'd0;
+ litedramcore_phaseinjector0_baddress_re <= 1'd0;
+ litedramcore_phaseinjector0_wrdata_re <= 1'd0;
+ litedramcore_phaseinjector0_rddata_status <= 32'd0;
+ litedramcore_phaseinjector0_rddata_re <= 1'd0;
+ litedramcore_phaseinjector1_command_storage <= 6'd0;
+ litedramcore_phaseinjector1_command_re <= 1'd0;
+ litedramcore_phaseinjector1_address_re <= 1'd0;
+ litedramcore_phaseinjector1_baddress_re <= 1'd0;
+ litedramcore_phaseinjector1_wrdata_re <= 1'd0;
+ litedramcore_phaseinjector1_rddata_status <= 32'd0;
+ litedramcore_phaseinjector1_rddata_re <= 1'd0;
+ litedramcore_phaseinjector2_command_storage <= 6'd0;
+ litedramcore_phaseinjector2_command_re <= 1'd0;
+ litedramcore_phaseinjector2_address_re <= 1'd0;
+ litedramcore_phaseinjector2_baddress_re <= 1'd0;
+ litedramcore_phaseinjector2_wrdata_re <= 1'd0;
+ litedramcore_phaseinjector2_rddata_status <= 32'd0;
+ litedramcore_phaseinjector2_rddata_re <= 1'd0;
+ litedramcore_phaseinjector3_command_storage <= 6'd0;
+ litedramcore_phaseinjector3_command_re <= 1'd0;
+ litedramcore_phaseinjector3_address_re <= 1'd0;
+ litedramcore_phaseinjector3_baddress_re <= 1'd0;
+ litedramcore_phaseinjector3_wrdata_re <= 1'd0;
+ litedramcore_phaseinjector3_rddata_status <= 32'd0;
+ litedramcore_phaseinjector3_rddata_re <= 1'd0;
+ litedramcore_dfi_p0_address <= 15'd0;
+ litedramcore_dfi_p0_bank <= 3'd0;
+ litedramcore_dfi_p0_cas_n <= 1'd1;
+ litedramcore_dfi_p0_cs_n <= 1'd1;
+ litedramcore_dfi_p0_ras_n <= 1'd1;
+ litedramcore_dfi_p0_we_n <= 1'd1;
+ litedramcore_dfi_p0_wrdata_en <= 1'd0;
+ litedramcore_dfi_p0_rddata_en <= 1'd0;
+ litedramcore_dfi_p1_address <= 15'd0;
+ litedramcore_dfi_p1_bank <= 3'd0;
+ litedramcore_dfi_p1_cas_n <= 1'd1;
+ litedramcore_dfi_p1_cs_n <= 1'd1;
+ litedramcore_dfi_p1_ras_n <= 1'd1;
+ litedramcore_dfi_p1_we_n <= 1'd1;
+ litedramcore_dfi_p1_wrdata_en <= 1'd0;
+ litedramcore_dfi_p1_rddata_en <= 1'd0;
+ litedramcore_dfi_p2_address <= 15'd0;
+ litedramcore_dfi_p2_bank <= 3'd0;
+ litedramcore_dfi_p2_cas_n <= 1'd1;
+ litedramcore_dfi_p2_cs_n <= 1'd1;
+ litedramcore_dfi_p2_ras_n <= 1'd1;
+ litedramcore_dfi_p2_we_n <= 1'd1;
+ litedramcore_dfi_p2_wrdata_en <= 1'd0;
+ litedramcore_dfi_p2_rddata_en <= 1'd0;
+ litedramcore_dfi_p3_address <= 15'd0;
+ litedramcore_dfi_p3_bank <= 3'd0;
+ litedramcore_dfi_p3_cas_n <= 1'd1;
+ litedramcore_dfi_p3_cs_n <= 1'd1;
+ litedramcore_dfi_p3_ras_n <= 1'd1;
+ litedramcore_dfi_p3_we_n <= 1'd1;
+ litedramcore_dfi_p3_wrdata_en <= 1'd0;
+ litedramcore_dfi_p3_rddata_en <= 1'd0;
+ litedramcore_cmd_payload_a <= 15'd0;
+ litedramcore_cmd_payload_ba <= 3'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd0;
+ litedramcore_cmd_payload_we <= 1'd0;
+ litedramcore_timer_count1 <= 10'd781;
+ litedramcore_postponer_req_o <= 1'd0;
+ litedramcore_postponer_count <= 1'd0;
+ litedramcore_sequencer_done1 <= 1'd0;
+ litedramcore_sequencer_counter <= 6'd0;
+ litedramcore_sequencer_count <= 1'd0;
+ litedramcore_zqcs_timer_count1 <= 27'd99999999;
+ litedramcore_zqcs_executer_done <= 1'd0;
+ litedramcore_zqcs_executer_counter <= 5'd0;
+ litedramcore_bankmachine0_level <= 5'd0;
+ litedramcore_bankmachine0_produce <= 4'd0;
+ litedramcore_bankmachine0_consume <= 4'd0;
+ litedramcore_bankmachine0_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine0_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine0_pipe_valid_source_payload_addr <= 22'd0;
+ litedramcore_bankmachine0_row <= 15'd0;
+ litedramcore_bankmachine0_row_opened <= 1'd0;
+ litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine0_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine0_trccon_ready <= 1'd0;
+ litedramcore_bankmachine0_trccon_count <= 3'd0;
+ litedramcore_bankmachine0_trascon_ready <= 1'd0;
+ litedramcore_bankmachine0_trascon_count <= 3'd0;
+ litedramcore_bankmachine1_level <= 5'd0;
+ litedramcore_bankmachine1_produce <= 4'd0;
+ litedramcore_bankmachine1_consume <= 4'd0;
+ litedramcore_bankmachine1_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine1_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine1_pipe_valid_source_payload_addr <= 22'd0;
+ litedramcore_bankmachine1_row <= 15'd0;
+ litedramcore_bankmachine1_row_opened <= 1'd0;
+ litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine1_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine1_trccon_ready <= 1'd0;
+ litedramcore_bankmachine1_trccon_count <= 3'd0;
+ litedramcore_bankmachine1_trascon_ready <= 1'd0;
+ litedramcore_bankmachine1_trascon_count <= 3'd0;
+ litedramcore_bankmachine2_level <= 5'd0;
+ litedramcore_bankmachine2_produce <= 4'd0;
+ litedramcore_bankmachine2_consume <= 4'd0;
+ litedramcore_bankmachine2_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine2_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine2_pipe_valid_source_payload_addr <= 22'd0;
+ litedramcore_bankmachine2_row <= 15'd0;
+ litedramcore_bankmachine2_row_opened <= 1'd0;
+ litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine2_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine2_trccon_ready <= 1'd0;
+ litedramcore_bankmachine2_trccon_count <= 3'd0;
+ litedramcore_bankmachine2_trascon_ready <= 1'd0;
+ litedramcore_bankmachine2_trascon_count <= 3'd0;
+ litedramcore_bankmachine3_level <= 5'd0;
+ litedramcore_bankmachine3_produce <= 4'd0;
+ litedramcore_bankmachine3_consume <= 4'd0;
+ litedramcore_bankmachine3_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine3_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine3_pipe_valid_source_payload_addr <= 22'd0;
+ litedramcore_bankmachine3_row <= 15'd0;
+ litedramcore_bankmachine3_row_opened <= 1'd0;
+ litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine3_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine3_trccon_ready <= 1'd0;
+ litedramcore_bankmachine3_trccon_count <= 3'd0;
+ litedramcore_bankmachine3_trascon_ready <= 1'd0;
+ litedramcore_bankmachine3_trascon_count <= 3'd0;
+ litedramcore_bankmachine4_level <= 5'd0;
+ litedramcore_bankmachine4_produce <= 4'd0;
+ litedramcore_bankmachine4_consume <= 4'd0;
+ litedramcore_bankmachine4_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine4_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine4_pipe_valid_source_payload_addr <= 22'd0;
+ litedramcore_bankmachine4_row <= 15'd0;
+ litedramcore_bankmachine4_row_opened <= 1'd0;
+ litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine4_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine4_trccon_ready <= 1'd0;
+ litedramcore_bankmachine4_trccon_count <= 3'd0;
+ litedramcore_bankmachine4_trascon_ready <= 1'd0;
+ litedramcore_bankmachine4_trascon_count <= 3'd0;
+ litedramcore_bankmachine5_level <= 5'd0;
+ litedramcore_bankmachine5_produce <= 4'd0;
+ litedramcore_bankmachine5_consume <= 4'd0;
+ litedramcore_bankmachine5_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine5_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine5_pipe_valid_source_payload_addr <= 22'd0;
+ litedramcore_bankmachine5_row <= 15'd0;
+ litedramcore_bankmachine5_row_opened <= 1'd0;
+ litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine5_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine5_trccon_ready <= 1'd0;
+ litedramcore_bankmachine5_trccon_count <= 3'd0;
+ litedramcore_bankmachine5_trascon_ready <= 1'd0;
+ litedramcore_bankmachine5_trascon_count <= 3'd0;
+ litedramcore_bankmachine6_level <= 5'd0;
+ litedramcore_bankmachine6_produce <= 4'd0;
+ litedramcore_bankmachine6_consume <= 4'd0;
+ litedramcore_bankmachine6_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine6_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine6_pipe_valid_source_payload_addr <= 22'd0;
+ litedramcore_bankmachine6_row <= 15'd0;
+ litedramcore_bankmachine6_row_opened <= 1'd0;
+ litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine6_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine6_trccon_ready <= 1'd0;
+ litedramcore_bankmachine6_trccon_count <= 3'd0;
+ litedramcore_bankmachine6_trascon_ready <= 1'd0;
+ litedramcore_bankmachine6_trascon_count <= 3'd0;
+ litedramcore_bankmachine7_level <= 5'd0;
+ litedramcore_bankmachine7_produce <= 4'd0;
+ litedramcore_bankmachine7_consume <= 4'd0;
+ litedramcore_bankmachine7_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine7_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine7_pipe_valid_source_payload_addr <= 22'd0;
+ litedramcore_bankmachine7_row <= 15'd0;
+ litedramcore_bankmachine7_row_opened <= 1'd0;
+ litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine7_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine7_trccon_ready <= 1'd0;
+ litedramcore_bankmachine7_trccon_count <= 3'd0;
+ litedramcore_bankmachine7_trascon_ready <= 1'd0;
+ litedramcore_bankmachine7_trascon_count <= 3'd0;
+ litedramcore_choose_cmd_grant <= 3'd0;
+ litedramcore_choose_req_grant <= 3'd0;
+ litedramcore_trrdcon_ready <= 1'd0;
+ litedramcore_trrdcon_count <= 1'd0;
+ litedramcore_tfawcon_ready <= 1'd1;
+ litedramcore_tfawcon_window <= 5'd0;
+ litedramcore_tccdcon_ready <= 1'd0;
+ litedramcore_tccdcon_count <= 1'd0;
+ litedramcore_twtrcon_ready <= 1'd0;
+ litedramcore_twtrcon_count <= 3'd0;
+ litedramcore_time0 <= 5'd0;
+ litedramcore_time1 <= 4'd0;
+ init_done_storage <= 1'd0;
+ init_done_re <= 1'd0;
+ init_error_storage <= 1'd0;
+ init_error_re <= 1'd0;
+ litedramcore_we <= 1'd0;
+ litedramcore_refresher_state <= 2'd0;
+ litedramcore_bankmachine0_state <= 4'd0;
+ litedramcore_bankmachine1_state <= 4'd0;
+ litedramcore_bankmachine2_state <= 4'd0;
+ litedramcore_bankmachine3_state <= 4'd0;
+ litedramcore_bankmachine4_state <= 4'd0;
+ litedramcore_bankmachine5_state <= 4'd0;
+ litedramcore_bankmachine6_state <= 4'd0;
+ litedramcore_bankmachine7_state <= 4'd0;
+ litedramcore_multiplexer_state <= 4'd0;
+ litedramcore_new_master_wdata_ready0 <= 1'd0;
+ litedramcore_new_master_wdata_ready1 <= 1'd0;
+ litedramcore_new_master_rdata_valid0 <= 1'd0;
+ litedramcore_new_master_rdata_valid1 <= 1'd0;
+ litedramcore_new_master_rdata_valid2 <= 1'd0;
+ litedramcore_new_master_rdata_valid3 <= 1'd0;
+ litedramcore_new_master_rdata_valid4 <= 1'd0;
+ litedramcore_new_master_rdata_valid5 <= 1'd0;
+ litedramcore_new_master_rdata_valid6 <= 1'd0;
+ litedramcore_new_master_rdata_valid7 <= 1'd0;
+ litedramcore_new_master_rdata_valid8 <= 1'd0;
+ litedramcore_state <= 2'd0;
+ end
end
reg [24:0] storage[0:15];
reg [24:0] storage_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we)
- storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
- storage_dat0 <= storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine0_wrport_we)
+ storage[litedramcore_bankmachine0_wrport_adr] <= litedramcore_bankmachine0_wrport_dat_w;
+ storage_dat0 <= storage[litedramcore_bankmachine0_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = storage_dat0;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine0_wrport_dat_r = storage_dat0;
+assign litedramcore_bankmachine0_rdport_dat_r = storage[litedramcore_bankmachine0_rdport_adr];
//------------------------------------------------------------------------------
reg [24:0] storage_1[0:15];
reg [24:0] storage_1_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we)
- storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
- storage_1_dat0 <= storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine1_wrport_we)
+ storage_1[litedramcore_bankmachine1_wrport_adr] <= litedramcore_bankmachine1_wrport_dat_w;
+ storage_1_dat0 <= storage_1[litedramcore_bankmachine1_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = storage_1_dat0;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine1_wrport_dat_r = storage_1_dat0;
+assign litedramcore_bankmachine1_rdport_dat_r = storage_1[litedramcore_bankmachine1_rdport_adr];
//------------------------------------------------------------------------------
reg [24:0] storage_2[0:15];
reg [24:0] storage_2_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we)
- storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
- storage_2_dat0 <= storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine2_wrport_we)
+ storage_2[litedramcore_bankmachine2_wrport_adr] <= litedramcore_bankmachine2_wrport_dat_w;
+ storage_2_dat0 <= storage_2[litedramcore_bankmachine2_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = storage_2_dat0;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine2_wrport_dat_r = storage_2_dat0;
+assign litedramcore_bankmachine2_rdport_dat_r = storage_2[litedramcore_bankmachine2_rdport_adr];
//------------------------------------------------------------------------------
reg [24:0] storage_3[0:15];
reg [24:0] storage_3_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we)
- storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
- storage_3_dat0 <= storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine3_wrport_we)
+ storage_3[litedramcore_bankmachine3_wrport_adr] <= litedramcore_bankmachine3_wrport_dat_w;
+ storage_3_dat0 <= storage_3[litedramcore_bankmachine3_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = storage_3_dat0;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine3_wrport_dat_r = storage_3_dat0;
+assign litedramcore_bankmachine3_rdport_dat_r = storage_3[litedramcore_bankmachine3_rdport_adr];
//------------------------------------------------------------------------------
reg [24:0] storage_4[0:15];
reg [24:0] storage_4_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we)
- storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
- storage_4_dat0 <= storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine4_wrport_we)
+ storage_4[litedramcore_bankmachine4_wrport_adr] <= litedramcore_bankmachine4_wrport_dat_w;
+ storage_4_dat0 <= storage_4[litedramcore_bankmachine4_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = storage_4_dat0;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine4_wrport_dat_r = storage_4_dat0;
+assign litedramcore_bankmachine4_rdport_dat_r = storage_4[litedramcore_bankmachine4_rdport_adr];
//------------------------------------------------------------------------------
reg [24:0] storage_5[0:15];
reg [24:0] storage_5_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we)
- storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
- storage_5_dat0 <= storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine5_wrport_we)
+ storage_5[litedramcore_bankmachine5_wrport_adr] <= litedramcore_bankmachine5_wrport_dat_w;
+ storage_5_dat0 <= storage_5[litedramcore_bankmachine5_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = storage_5_dat0;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine5_wrport_dat_r = storage_5_dat0;
+assign litedramcore_bankmachine5_rdport_dat_r = storage_5[litedramcore_bankmachine5_rdport_adr];
//------------------------------------------------------------------------------
reg [24:0] storage_6[0:15];
reg [24:0] storage_6_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we)
- storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
- storage_6_dat0 <= storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine6_wrport_we)
+ storage_6[litedramcore_bankmachine6_wrport_adr] <= litedramcore_bankmachine6_wrport_dat_w;
+ storage_6_dat0 <= storage_6[litedramcore_bankmachine6_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = storage_6_dat0;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine6_wrport_dat_r = storage_6_dat0;
+assign litedramcore_bankmachine6_rdport_dat_r = storage_6[litedramcore_bankmachine6_rdport_adr];
//------------------------------------------------------------------------------
reg [24:0] storage_7[0:15];
reg [24:0] storage_7_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we)
- storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
- storage_7_dat0 <= storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine7_wrport_we)
+ storage_7[litedramcore_bankmachine7_wrport_adr] <= litedramcore_bankmachine7_wrport_dat_w;
+ storage_7_dat0 <= storage_7[litedramcore_bankmachine7_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = storage_7_dat0;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine7_wrport_dat_r = storage_7_dat0;
+assign litedramcore_bankmachine7_rdport_dat_r = storage_7[litedramcore_bankmachine7_rdport_adr];
FDCE FDCE(
.LOCKED(locked)
);
-(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
+(* ars_ff1 = "true", async_reg = "true" *)
+FDPE #(
.INIT(1'd1)
) FDPE (
.C(iodelay_clk),
.Q(xilinxasyncresetsynchronizerimpl0_rst_meta)
);
-(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
+(* ars_ff2 = "true", async_reg = "true" *)
+FDPE #(
.INIT(1'd1)
) FDPE_1 (
.C(iodelay_clk),
.Q(iodelay_rst)
);
-(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
+(* ars_ff1 = "true", async_reg = "true" *)
+FDPE #(
.INIT(1'd1)
) FDPE_2 (
.C(sys_clk),
.Q(xilinxasyncresetsynchronizerimpl1_rst_meta)
);
-(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
+(* ars_ff2 = "true", async_reg = "true" *)
+FDPE #(
.INIT(1'd1)
) FDPE_3 (
.C(sys_clk),
.Q(sys_rst)
);
-(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
+(* ars_ff1 = "true", async_reg = "true" *)
+FDPE #(
.INIT(1'd1)
) FDPE_4 (
.C(sys4x_clk),
.Q(xilinxasyncresetsynchronizerimpl2_rst_meta)
);
-(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
+(* ars_ff2 = "true", async_reg = "true" *)
+FDPE #(
.INIT(1'd1)
) FDPE_5 (
.C(sys4x_clk),
.Q(xilinxasyncresetsynchronizerimpl2_expr)
);
-(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
+(* ars_ff1 = "true", async_reg = "true" *)
+FDPE #(
.INIT(1'd1)
) FDPE_6 (
.C(sys4x_dqs_clk),
.Q(xilinxasyncresetsynchronizerimpl3_rst_meta)
);
-(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
+(* ars_ff2 = "true", async_reg = "true" *)
+FDPE #(
.INIT(1'd1)
) FDPE_7 (
.C(sys4x_dqs_clk),
endmodule
// -----------------------------------------------------------------------------
-// Auto-Generated by LiteX on 2022-08-04 21:06:57.
+// Auto-Generated by LiteX on 2022-10-28 19:01:20.
//------------------------------------------------------------------------------
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//
// Filename : litedram_core.v
// Device : LFE5U-85F-8MG285C
-// LiteX sha1 : 6932fc51
-// Date : 2022-08-04 21:07:03
+// LiteX sha1 : --------
+// Date : 2022-10-28 19:01:26
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
module litedram_core (
- input wire clk,
- input wire rst,
- output wire pll_locked,
- output wire [14:0] ddram_a,
- output wire [2:0] ddram_ba,
- output wire ddram_ras_n,
- output wire ddram_cas_n,
- output wire ddram_we_n,
- output wire ddram_cs_n,
- output wire [1:0] ddram_dm,
- input wire [15:0] ddram_dq,
- input wire [1:0] ddram_dqs_p,
- input wire [1:0] ddram_dqs_n,
- output wire ddram_clk_p,
- input wire ddram_clk_n,
- output wire ddram_cke,
- output wire ddram_odt,
- output wire ddram_reset_n,
- output wire init_done,
- output wire init_error,
- input wire [29:0] wb_ctrl_adr,
- input wire [31:0] wb_ctrl_dat_w,
- output wire [31:0] wb_ctrl_dat_r,
- input wire [3:0] wb_ctrl_sel,
- input wire wb_ctrl_cyc,
- input wire wb_ctrl_stb,
- output wire wb_ctrl_ack,
- input wire wb_ctrl_we,
- input wire [2:0] wb_ctrl_cti,
- input wire [1:0] wb_ctrl_bte,
- output wire wb_ctrl_err,
- output wire user_clk,
- output wire user_rst,
- input wire user_port_native_0_cmd_valid,
- output wire user_port_native_0_cmd_ready,
- input wire user_port_native_0_cmd_we,
- input wire [24:0] user_port_native_0_cmd_addr,
- input wire user_port_native_0_wdata_valid,
- output wire user_port_native_0_wdata_ready,
- input wire [15:0] user_port_native_0_wdata_we,
- input wire [127:0] user_port_native_0_wdata_data,
- output wire user_port_native_0_rdata_valid,
- input wire user_port_native_0_rdata_ready,
- output wire [127:0] user_port_native_0_rdata_data
+ input wire clk,
+ input wire rst,
+ output wire pll_locked,
+ output wire [14:0] ddram_a,
+ output wire [2:0] ddram_ba,
+ output wire ddram_ras_n,
+ output wire ddram_cas_n,
+ output wire ddram_we_n,
+ output wire ddram_cs_n,
+ output wire [1:0] ddram_dm,
+ input wire [15:0] ddram_dq,
+ input wire [1:0] ddram_dqs_p,
+ input wire [1:0] ddram_dqs_n,
+ output wire ddram_clk_p,
+ input wire ddram_clk_n,
+ output wire ddram_cke,
+ output wire ddram_odt,
+ output wire ddram_reset_n,
+ output wire init_done,
+ output wire init_error,
+ input wire [29:0] wb_ctrl_adr,
+ input wire [31:0] wb_ctrl_dat_w,
+ output wire [31:0] wb_ctrl_dat_r,
+ input wire [3:0] wb_ctrl_sel,
+ input wire wb_ctrl_cyc,
+ input wire wb_ctrl_stb,
+ output wire wb_ctrl_ack,
+ input wire wb_ctrl_we,
+ input wire [2:0] wb_ctrl_cti,
+ input wire [1:0] wb_ctrl_bte,
+ output wire wb_ctrl_err,
+ output wire user_clk,
+ output wire user_rst,
+ input wire user_port_native_0_cmd_valid,
+ output wire user_port_native_0_cmd_ready,
+ input wire user_port_native_0_cmd_we,
+ input wire [24:0] user_port_native_0_cmd_addr,
+ input wire user_port_native_0_wdata_valid,
+ output wire user_port_native_0_wdata_ready,
+ input wire [15:0] user_port_native_0_wdata_we,
+ input wire [127:0] user_port_native_0_wdata_data,
+ output wire user_port_native_0_rdata_valid,
+ input wire user_port_native_0_rdata_ready,
+ output wire [127:0] user_port_native_0_rdata_data
);
// Signals
//------------------------------------------------------------------------------
-reg crg_rst = 1'd0;
-wire init_clk;
-wire init_rst;
-wire por_clk;
-wire sys_clk;
-wire sys_rst;
-wire sys2x_clk;
-wire sys2x_rst;
-wire sys2x_i_clk;
-wire crg_stop;
-wire crg_reset0;
-reg [15:0] crg_por_count = 16'd65535;
-wire crg_por_done;
-wire crg_sys2x_clk_ecsout;
-wire crg_reset1;
-wire crg_locked;
-reg crg_stdby = 1'd0;
-wire crg_clkin;
-wire crg_clkout0;
-wire crg_clkout1;
-wire ddrphy_pause0;
-wire ddrphy_stop0;
-wire ddrphy_delay0;
-wire ddrphy_reset0;
-wire ddrphy_new_lock;
-reg ddrphy_update = 1'd0;
-reg ddrphy_stop1 = 1'd0;
-reg ddrphy_freeze = 1'd0;
-reg ddrphy_pause1 = 1'd0;
-reg ddrphy_reset1 = 1'd0;
-wire ddrphy_lock0;
-wire ddrphy_delay1;
-wire ddrphy_lock1;
-reg ddrphy_lock_d = 1'd0;
-reg [6:0] ddrphy_counter = 7'd0;
-reg [1:0] ddrphy_dly_sel_storage = 2'd0;
-reg ddrphy_dly_sel_re = 1'd0;
-reg ddrphy_rdly_dq_rst_re = 1'd0;
-wire ddrphy_rdly_dq_rst_r;
-reg ddrphy_rdly_dq_rst_we = 1'd0;
-reg ddrphy_rdly_dq_rst_w = 1'd0;
-reg ddrphy_rdly_dq_inc_re = 1'd0;
-wire ddrphy_rdly_dq_inc_r;
-reg ddrphy_rdly_dq_inc_we = 1'd0;
-reg ddrphy_rdly_dq_inc_w = 1'd0;
-reg ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
-wire ddrphy_rdly_dq_bitslip_rst_r;
-reg ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
-reg ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
-reg ddrphy_rdly_dq_bitslip_re = 1'd0;
-wire ddrphy_rdly_dq_bitslip_r;
-reg ddrphy_rdly_dq_bitslip_we = 1'd0;
-reg ddrphy_rdly_dq_bitslip_w = 1'd0;
-reg ddrphy_burstdet_clr_re = 1'd0;
-wire ddrphy_burstdet_clr_r;
-reg ddrphy_burstdet_clr_we = 1'd0;
-reg ddrphy_burstdet_clr_w = 1'd0;
-reg [1:0] ddrphy_burstdet_seen_status = 2'd0;
-wire ddrphy_burstdet_seen_we;
-reg ddrphy_burstdet_seen_re = 1'd0;
-wire [1:0] ddrphy_datavalid;
-wire [14:0] ddrphy_dfi_p0_address;
-wire [2:0] ddrphy_dfi_p0_bank;
-wire ddrphy_dfi_p0_cas_n;
-wire ddrphy_dfi_p0_cs_n;
-wire ddrphy_dfi_p0_ras_n;
-wire ddrphy_dfi_p0_we_n;
-wire ddrphy_dfi_p0_cke;
-wire ddrphy_dfi_p0_odt;
-wire ddrphy_dfi_p0_reset_n;
-wire ddrphy_dfi_p0_act_n;
-wire [63:0] ddrphy_dfi_p0_wrdata;
-wire ddrphy_dfi_p0_wrdata_en;
-wire [7:0] ddrphy_dfi_p0_wrdata_mask;
-wire ddrphy_dfi_p0_rddata_en;
-reg [63:0] ddrphy_dfi_p0_rddata = 64'd0;
-wire ddrphy_dfi_p0_rddata_valid;
-wire [14:0] ddrphy_dfi_p1_address;
-wire [2:0] ddrphy_dfi_p1_bank;
-wire ddrphy_dfi_p1_cas_n;
-wire ddrphy_dfi_p1_cs_n;
-wire ddrphy_dfi_p1_ras_n;
-wire ddrphy_dfi_p1_we_n;
-wire ddrphy_dfi_p1_cke;
-wire ddrphy_dfi_p1_odt;
-wire ddrphy_dfi_p1_reset_n;
-wire ddrphy_dfi_p1_act_n;
-wire [63:0] ddrphy_dfi_p1_wrdata;
-wire ddrphy_dfi_p1_wrdata_en;
-wire [7:0] ddrphy_dfi_p1_wrdata_mask;
-wire ddrphy_dfi_p1_rddata_en;
-reg [63:0] ddrphy_dfi_p1_rddata = 64'd0;
-wire ddrphy_dfi_p1_rddata_valid;
-wire ddrphy_bl8_chunk;
-wire ddrphy_pad_oddrx2f0;
-wire ddrphy_pad_oddrx2f1;
-wire ddrphy_pad_oddrx2f2;
-wire ddrphy_pad_oddrx2f3;
-wire ddrphy_pad_oddrx2f4;
-wire ddrphy_pad_oddrx2f5;
-wire ddrphy_pad_oddrx2f6;
-wire ddrphy_pad_oddrx2f7;
-wire ddrphy_pad_oddrx2f8;
-wire ddrphy_pad_oddrx2f9;
-wire ddrphy_pad_oddrx2f10;
-wire ddrphy_pad_oddrx2f11;
-wire ddrphy_pad_oddrx2f12;
-wire ddrphy_pad_oddrx2f13;
-wire ddrphy_pad_oddrx2f14;
-wire ddrphy_pad_oddrx2f15;
-wire ddrphy_pad_oddrx2f16;
-wire ddrphy_pad_oddrx2f17;
-wire ddrphy_pad_oddrx2f18;
-wire ddrphy_pad_oddrx2f19;
-wire ddrphy_pad_oddrx2f20;
-wire ddrphy_pad_oddrx2f21;
-wire ddrphy_pad_oddrx2f22;
-wire ddrphy_pad_oddrx2f23;
-wire ddrphy_pad_oddrx2f24;
-wire ddrphy_pad_oddrx2f25;
-wire ddrphy_dq_oe;
-wire ddrphy_dqs_re;
-wire ddrphy_dqs_oe;
-wire ddrphy_dqs_postamble;
-wire ddrphy_dqs_preamble;
-wire ddrphy_dqs_i0;
-wire ddrphy_dqsr900;
-wire ddrphy_dqsw2700;
-wire ddrphy_dqsw0;
-wire [2:0] ddrphy_rdpntr0;
-wire [2:0] ddrphy_wrpntr0;
-reg [2:0] ddrphy_rdly0 = 3'd0;
-wire ddrphy_burstdet0;
-reg ddrphy_burstdet_d0 = 1'd0;
-wire ddrphy_dqs0;
-wire ddrphy_dqs_oe_n0;
-reg [7:0] ddrphy_dm_o_data0 = 8'd0;
-reg [7:0] ddrphy_dm_o_data_d0 = 8'd0;
-reg [3:0] ddrphy_dm_o_data_muxed0 = 4'd0;
-wire ddrphy_dq_o0;
-wire ddrphy_dq_i0;
-wire ddrphy_dq_oe_n0;
-wire ddrphy_dq_i_delayed0;
-wire [7:0] ddrphy_dq_i_data0;
-reg [7:0] ddrphy_dq_o_data0 = 8'd0;
-reg [7:0] ddrphy_dq_o_data_d0 = 8'd0;
-reg [3:0] ddrphy_dq_o_data_muxed0 = 4'd0;
-wire [3:0] ddrphy_bitslip0_i;
-reg [3:0] ddrphy_bitslip0_o = 4'd0;
-reg [1:0] ddrphy_bitslip0_value = 2'd0;
-reg [7:0] ddrphy_bitslip0_r = 8'd0;
-reg [3:0] ddrphy_dq_i_bitslip_o_d0 = 4'd0;
-wire ddrphy_dq_o1;
-wire ddrphy_dq_i1;
-wire ddrphy_dq_oe_n1;
-wire ddrphy_dq_i_delayed1;
-wire [7:0] ddrphy_dq_i_data1;
-reg [7:0] ddrphy_dq_o_data1 = 8'd0;
-reg [7:0] ddrphy_dq_o_data_d1 = 8'd0;
-reg [3:0] ddrphy_dq_o_data_muxed1 = 4'd0;
-wire [3:0] ddrphy_bitslip1_i;
-reg [3:0] ddrphy_bitslip1_o = 4'd0;
-reg [1:0] ddrphy_bitslip1_value = 2'd0;
-reg [7:0] ddrphy_bitslip1_r = 8'd0;
-reg [3:0] ddrphy_dq_i_bitslip_o_d1 = 4'd0;
-wire ddrphy_dq_o2;
-wire ddrphy_dq_i2;
-wire ddrphy_dq_oe_n2;
-wire ddrphy_dq_i_delayed2;
-wire [7:0] ddrphy_dq_i_data2;
-reg [7:0] ddrphy_dq_o_data2 = 8'd0;
-reg [7:0] ddrphy_dq_o_data_d2 = 8'd0;
-reg [3:0] ddrphy_dq_o_data_muxed2 = 4'd0;
-wire [3:0] ddrphy_bitslip2_i;
-reg [3:0] ddrphy_bitslip2_o = 4'd0;
-reg [1:0] ddrphy_bitslip2_value = 2'd0;
-reg [7:0] ddrphy_bitslip2_r = 8'd0;
-reg [3:0] ddrphy_dq_i_bitslip_o_d2 = 4'd0;
-wire ddrphy_dq_o3;
-wire ddrphy_dq_i3;
-wire ddrphy_dq_oe_n3;
-wire ddrphy_dq_i_delayed3;
-wire [7:0] ddrphy_dq_i_data3;
-reg [7:0] ddrphy_dq_o_data3 = 8'd0;
-reg [7:0] ddrphy_dq_o_data_d3 = 8'd0;
-reg [3:0] ddrphy_dq_o_data_muxed3 = 4'd0;
-wire [3:0] ddrphy_bitslip3_i;
-reg [3:0] ddrphy_bitslip3_o = 4'd0;
-reg [1:0] ddrphy_bitslip3_value = 2'd0;
-reg [7:0] ddrphy_bitslip3_r = 8'd0;
-reg [3:0] ddrphy_dq_i_bitslip_o_d3 = 4'd0;
-wire ddrphy_dq_o4;
-wire ddrphy_dq_i4;
-wire ddrphy_dq_oe_n4;
-wire ddrphy_dq_i_delayed4;
-wire [7:0] ddrphy_dq_i_data4;
-reg [7:0] ddrphy_dq_o_data4 = 8'd0;
-reg [7:0] ddrphy_dq_o_data_d4 = 8'd0;
-reg [3:0] ddrphy_dq_o_data_muxed4 = 4'd0;
-wire [3:0] ddrphy_bitslip4_i;
-reg [3:0] ddrphy_bitslip4_o = 4'd0;
-reg [1:0] ddrphy_bitslip4_value = 2'd0;
-reg [7:0] ddrphy_bitslip4_r = 8'd0;
-reg [3:0] ddrphy_dq_i_bitslip_o_d4 = 4'd0;
-wire ddrphy_dq_o5;
-wire ddrphy_dq_i5;
-wire ddrphy_dq_oe_n5;
-wire ddrphy_dq_i_delayed5;
-wire [7:0] ddrphy_dq_i_data5;
-reg [7:0] ddrphy_dq_o_data5 = 8'd0;
-reg [7:0] ddrphy_dq_o_data_d5 = 8'd0;
-reg [3:0] ddrphy_dq_o_data_muxed5 = 4'd0;
-wire [3:0] ddrphy_bitslip5_i;
-reg [3:0] ddrphy_bitslip5_o = 4'd0;
-reg [1:0] ddrphy_bitslip5_value = 2'd0;
-reg [7:0] ddrphy_bitslip5_r = 8'd0;
-reg [3:0] ddrphy_dq_i_bitslip_o_d5 = 4'd0;
-wire ddrphy_dq_o6;
-wire ddrphy_dq_i6;
-wire ddrphy_dq_oe_n6;
-wire ddrphy_dq_i_delayed6;
-wire [7:0] ddrphy_dq_i_data6;
-reg [7:0] ddrphy_dq_o_data6 = 8'd0;
-reg [7:0] ddrphy_dq_o_data_d6 = 8'd0;
-reg [3:0] ddrphy_dq_o_data_muxed6 = 4'd0;
-wire [3:0] ddrphy_bitslip6_i;
-reg [3:0] ddrphy_bitslip6_o = 4'd0;
-reg [1:0] ddrphy_bitslip6_value = 2'd0;
-reg [7:0] ddrphy_bitslip6_r = 8'd0;
-reg [3:0] ddrphy_dq_i_bitslip_o_d6 = 4'd0;
-wire ddrphy_dq_o7;
-wire ddrphy_dq_i7;
-wire ddrphy_dq_oe_n7;
-wire ddrphy_dq_i_delayed7;
-wire [7:0] ddrphy_dq_i_data7;
-reg [7:0] ddrphy_dq_o_data7 = 8'd0;
-reg [7:0] ddrphy_dq_o_data_d7 = 8'd0;
-reg [3:0] ddrphy_dq_o_data_muxed7 = 4'd0;
-wire [3:0] ddrphy_bitslip7_i;
-reg [3:0] ddrphy_bitslip7_o = 4'd0;
-reg [1:0] ddrphy_bitslip7_value = 2'd0;
-reg [7:0] ddrphy_bitslip7_r = 8'd0;
-reg [3:0] ddrphy_dq_i_bitslip_o_d7 = 4'd0;
-wire ddrphy_dqs_i1;
-wire ddrphy_dqsr901;
-wire ddrphy_dqsw2701;
-wire ddrphy_dqsw1;
-wire [2:0] ddrphy_rdpntr1;
-wire [2:0] ddrphy_wrpntr1;
-reg [2:0] ddrphy_rdly1 = 3'd0;
-wire ddrphy_burstdet1;
-reg ddrphy_burstdet_d1 = 1'd0;
-wire ddrphy_dqs1;
-wire ddrphy_dqs_oe_n1;
-reg [7:0] ddrphy_dm_o_data1 = 8'd0;
-reg [7:0] ddrphy_dm_o_data_d1 = 8'd0;
-reg [3:0] ddrphy_dm_o_data_muxed1 = 4'd0;
-wire ddrphy_dq_o8;
-wire ddrphy_dq_i8;
-wire ddrphy_dq_oe_n8;
-wire ddrphy_dq_i_delayed8;
-wire [7:0] ddrphy_dq_i_data8;
-reg [7:0] ddrphy_dq_o_data8 = 8'd0;
-reg [7:0] ddrphy_dq_o_data_d8 = 8'd0;
-reg [3:0] ddrphy_dq_o_data_muxed8 = 4'd0;
-wire [3:0] ddrphy_bitslip8_i;
-reg [3:0] ddrphy_bitslip8_o = 4'd0;
-reg [1:0] ddrphy_bitslip8_value = 2'd0;
-reg [7:0] ddrphy_bitslip8_r = 8'd0;
-reg [3:0] ddrphy_dq_i_bitslip_o_d8 = 4'd0;
-wire ddrphy_dq_o9;
-wire ddrphy_dq_i9;
-wire ddrphy_dq_oe_n9;
-wire ddrphy_dq_i_delayed9;
-wire [7:0] ddrphy_dq_i_data9;
-reg [7:0] ddrphy_dq_o_data9 = 8'd0;
-reg [7:0] ddrphy_dq_o_data_d9 = 8'd0;
-reg [3:0] ddrphy_dq_o_data_muxed9 = 4'd0;
-wire [3:0] ddrphy_bitslip9_i;
-reg [3:0] ddrphy_bitslip9_o = 4'd0;
-reg [1:0] ddrphy_bitslip9_value = 2'd0;
-reg [7:0] ddrphy_bitslip9_r = 8'd0;
-reg [3:0] ddrphy_dq_i_bitslip_o_d9 = 4'd0;
-wire ddrphy_dq_o10;
-wire ddrphy_dq_i10;
-wire ddrphy_dq_oe_n10;
-wire ddrphy_dq_i_delayed10;
-wire [7:0] ddrphy_dq_i_data10;
-reg [7:0] ddrphy_dq_o_data10 = 8'd0;
-reg [7:0] ddrphy_dq_o_data_d10 = 8'd0;
-reg [3:0] ddrphy_dq_o_data_muxed10 = 4'd0;
-wire [3:0] ddrphy_bitslip10_i;
-reg [3:0] ddrphy_bitslip10_o = 4'd0;
-reg [1:0] ddrphy_bitslip10_value = 2'd0;
-reg [7:0] ddrphy_bitslip10_r = 8'd0;
-reg [3:0] ddrphy_dq_i_bitslip_o_d10 = 4'd0;
-wire ddrphy_dq_o11;
-wire ddrphy_dq_i11;
-wire ddrphy_dq_oe_n11;
-wire ddrphy_dq_i_delayed11;
-wire [7:0] ddrphy_dq_i_data11;
-reg [7:0] ddrphy_dq_o_data11 = 8'd0;
-reg [7:0] ddrphy_dq_o_data_d11 = 8'd0;
-reg [3:0] ddrphy_dq_o_data_muxed11 = 4'd0;
-wire [3:0] ddrphy_bitslip11_i;
-reg [3:0] ddrphy_bitslip11_o = 4'd0;
-reg [1:0] ddrphy_bitslip11_value = 2'd0;
-reg [7:0] ddrphy_bitslip11_r = 8'd0;
-reg [3:0] ddrphy_dq_i_bitslip_o_d11 = 4'd0;
-wire ddrphy_dq_o12;
-wire ddrphy_dq_i12;
-wire ddrphy_dq_oe_n12;
-wire ddrphy_dq_i_delayed12;
-wire [7:0] ddrphy_dq_i_data12;
-reg [7:0] ddrphy_dq_o_data12 = 8'd0;
-reg [7:0] ddrphy_dq_o_data_d12 = 8'd0;
-reg [3:0] ddrphy_dq_o_data_muxed12 = 4'd0;
-wire [3:0] ddrphy_bitslip12_i;
-reg [3:0] ddrphy_bitslip12_o = 4'd0;
-reg [1:0] ddrphy_bitslip12_value = 2'd0;
-reg [7:0] ddrphy_bitslip12_r = 8'd0;
-reg [3:0] ddrphy_dq_i_bitslip_o_d12 = 4'd0;
-wire ddrphy_dq_o13;
-wire ddrphy_dq_i13;
-wire ddrphy_dq_oe_n13;
-wire ddrphy_dq_i_delayed13;
-wire [7:0] ddrphy_dq_i_data13;
-reg [7:0] ddrphy_dq_o_data13 = 8'd0;
-reg [7:0] ddrphy_dq_o_data_d13 = 8'd0;
-reg [3:0] ddrphy_dq_o_data_muxed13 = 4'd0;
-wire [3:0] ddrphy_bitslip13_i;
-reg [3:0] ddrphy_bitslip13_o = 4'd0;
-reg [1:0] ddrphy_bitslip13_value = 2'd0;
-reg [7:0] ddrphy_bitslip13_r = 8'd0;
-reg [3:0] ddrphy_dq_i_bitslip_o_d13 = 4'd0;
-wire ddrphy_dq_o14;
-wire ddrphy_dq_i14;
-wire ddrphy_dq_oe_n14;
-wire ddrphy_dq_i_delayed14;
-wire [7:0] ddrphy_dq_i_data14;
-reg [7:0] ddrphy_dq_o_data14 = 8'd0;
-reg [7:0] ddrphy_dq_o_data_d14 = 8'd0;
-reg [3:0] ddrphy_dq_o_data_muxed14 = 4'd0;
-wire [3:0] ddrphy_bitslip14_i;
-reg [3:0] ddrphy_bitslip14_o = 4'd0;
-reg [1:0] ddrphy_bitslip14_value = 2'd0;
-reg [7:0] ddrphy_bitslip14_r = 8'd0;
-reg [3:0] ddrphy_dq_i_bitslip_o_d14 = 4'd0;
-wire ddrphy_dq_o15;
-wire ddrphy_dq_i15;
-wire ddrphy_dq_oe_n15;
-wire ddrphy_dq_i_delayed15;
-wire [7:0] ddrphy_dq_i_data15;
-reg [7:0] ddrphy_dq_o_data15 = 8'd0;
-reg [7:0] ddrphy_dq_o_data_d15 = 8'd0;
-reg [3:0] ddrphy_dq_o_data_muxed15 = 4'd0;
-wire [3:0] ddrphy_bitslip15_i;
-reg [3:0] ddrphy_bitslip15_o = 4'd0;
-reg [1:0] ddrphy_bitslip15_value = 2'd0;
-reg [7:0] ddrphy_bitslip15_r = 8'd0;
-reg [3:0] ddrphy_dq_i_bitslip_o_d15 = 4'd0;
-reg ddrphy_rddata_en_tappeddelayline0 = 1'd0;
-reg ddrphy_rddata_en_tappeddelayline1 = 1'd0;
-reg ddrphy_rddata_en_tappeddelayline2 = 1'd0;
-reg ddrphy_rddata_en_tappeddelayline3 = 1'd0;
-reg ddrphy_rddata_en_tappeddelayline4 = 1'd0;
-reg ddrphy_rddata_en_tappeddelayline5 = 1'd0;
-reg ddrphy_rddata_en_tappeddelayline6 = 1'd0;
-reg ddrphy_rddata_en_tappeddelayline7 = 1'd0;
-reg ddrphy_rddata_en_tappeddelayline8 = 1'd0;
-reg ddrphy_rddata_en_tappeddelayline9 = 1'd0;
-reg ddrphy_rddata_en_tappeddelayline10 = 1'd0;
-reg ddrphy_rddata_en_tappeddelayline11 = 1'd0;
-reg ddrphy_rddata_en_tappeddelayline12 = 1'd0;
-reg ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
-reg ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
-reg ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
-reg ddrphy_wrdata_en_tappeddelayline3 = 1'd0;
-reg ddrphy_wrdata_en_tappeddelayline4 = 1'd0;
-reg ddrphy_wrdata_en_tappeddelayline5 = 1'd0;
-reg ddrphy_wrdata_en_tappeddelayline6 = 1'd0;
-wire [14:0] litedramcore_slave_p0_address;
-wire [2:0] litedramcore_slave_p0_bank;
-wire litedramcore_slave_p0_cas_n;
-wire litedramcore_slave_p0_cs_n;
-wire litedramcore_slave_p0_ras_n;
-wire litedramcore_slave_p0_we_n;
-wire litedramcore_slave_p0_cke;
-wire litedramcore_slave_p0_odt;
-wire litedramcore_slave_p0_reset_n;
-wire litedramcore_slave_p0_act_n;
-wire [63:0] litedramcore_slave_p0_wrdata;
-wire litedramcore_slave_p0_wrdata_en;
-wire [7:0] litedramcore_slave_p0_wrdata_mask;
-wire litedramcore_slave_p0_rddata_en;
-reg [63:0] litedramcore_slave_p0_rddata = 64'd0;
-reg litedramcore_slave_p0_rddata_valid = 1'd0;
-wire [14:0] litedramcore_slave_p1_address;
-wire [2:0] litedramcore_slave_p1_bank;
-wire litedramcore_slave_p1_cas_n;
-wire litedramcore_slave_p1_cs_n;
-wire litedramcore_slave_p1_ras_n;
-wire litedramcore_slave_p1_we_n;
-wire litedramcore_slave_p1_cke;
-wire litedramcore_slave_p1_odt;
-wire litedramcore_slave_p1_reset_n;
-wire litedramcore_slave_p1_act_n;
-wire [63:0] litedramcore_slave_p1_wrdata;
-wire litedramcore_slave_p1_wrdata_en;
-wire [7:0] litedramcore_slave_p1_wrdata_mask;
-wire litedramcore_slave_p1_rddata_en;
-reg [63:0] litedramcore_slave_p1_rddata = 64'd0;
-reg litedramcore_slave_p1_rddata_valid = 1'd0;
-reg [14:0] litedramcore_master_p0_address = 15'd0;
-reg [2:0] litedramcore_master_p0_bank = 3'd0;
-reg litedramcore_master_p0_cas_n = 1'd1;
-reg litedramcore_master_p0_cs_n = 1'd1;
-reg litedramcore_master_p0_ras_n = 1'd1;
-reg litedramcore_master_p0_we_n = 1'd1;
-reg litedramcore_master_p0_cke = 1'd0;
-reg litedramcore_master_p0_odt = 1'd0;
-reg litedramcore_master_p0_reset_n = 1'd0;
-reg litedramcore_master_p0_act_n = 1'd1;
-reg [63:0] litedramcore_master_p0_wrdata = 64'd0;
-reg litedramcore_master_p0_wrdata_en = 1'd0;
-reg [7:0] litedramcore_master_p0_wrdata_mask = 8'd0;
-reg litedramcore_master_p0_rddata_en = 1'd0;
-wire [63:0] litedramcore_master_p0_rddata;
-wire litedramcore_master_p0_rddata_valid;
-reg [14:0] litedramcore_master_p1_address = 15'd0;
-reg [2:0] litedramcore_master_p1_bank = 3'd0;
-reg litedramcore_master_p1_cas_n = 1'd1;
-reg litedramcore_master_p1_cs_n = 1'd1;
-reg litedramcore_master_p1_ras_n = 1'd1;
-reg litedramcore_master_p1_we_n = 1'd1;
-reg litedramcore_master_p1_cke = 1'd0;
-reg litedramcore_master_p1_odt = 1'd0;
-reg litedramcore_master_p1_reset_n = 1'd0;
-reg litedramcore_master_p1_act_n = 1'd1;
-reg [63:0] litedramcore_master_p1_wrdata = 64'd0;
-reg litedramcore_master_p1_wrdata_en = 1'd0;
-reg [7:0] litedramcore_master_p1_wrdata_mask = 8'd0;
-reg litedramcore_master_p1_rddata_en = 1'd0;
-wire [63:0] litedramcore_master_p1_rddata;
-wire litedramcore_master_p1_rddata_valid;
-wire [14:0] litedramcore_csr_dfi_p0_address;
-wire [2:0] litedramcore_csr_dfi_p0_bank;
-reg litedramcore_csr_dfi_p0_cas_n = 1'd1;
-reg litedramcore_csr_dfi_p0_cs_n = 1'd1;
-reg litedramcore_csr_dfi_p0_ras_n = 1'd1;
-reg litedramcore_csr_dfi_p0_we_n = 1'd1;
-wire litedramcore_csr_dfi_p0_cke;
-wire litedramcore_csr_dfi_p0_odt;
-wire litedramcore_csr_dfi_p0_reset_n;
-reg litedramcore_csr_dfi_p0_act_n = 1'd1;
-wire [63:0] litedramcore_csr_dfi_p0_wrdata;
-wire litedramcore_csr_dfi_p0_wrdata_en;
-wire [7:0] litedramcore_csr_dfi_p0_wrdata_mask;
-wire litedramcore_csr_dfi_p0_rddata_en;
-reg [63:0] litedramcore_csr_dfi_p0_rddata = 64'd0;
-reg litedramcore_csr_dfi_p0_rddata_valid = 1'd0;
-wire [14:0] litedramcore_csr_dfi_p1_address;
-wire [2:0] litedramcore_csr_dfi_p1_bank;
-reg litedramcore_csr_dfi_p1_cas_n = 1'd1;
-reg litedramcore_csr_dfi_p1_cs_n = 1'd1;
-reg litedramcore_csr_dfi_p1_ras_n = 1'd1;
-reg litedramcore_csr_dfi_p1_we_n = 1'd1;
-wire litedramcore_csr_dfi_p1_cke;
-wire litedramcore_csr_dfi_p1_odt;
-wire litedramcore_csr_dfi_p1_reset_n;
-reg litedramcore_csr_dfi_p1_act_n = 1'd1;
-wire [63:0] litedramcore_csr_dfi_p1_wrdata;
-wire litedramcore_csr_dfi_p1_wrdata_en;
-wire [7:0] litedramcore_csr_dfi_p1_wrdata_mask;
-wire litedramcore_csr_dfi_p1_rddata_en;
-reg [63:0] litedramcore_csr_dfi_p1_rddata = 64'd0;
-reg litedramcore_csr_dfi_p1_rddata_valid = 1'd0;
-reg [14:0] litedramcore_ext_dfi_p0_address = 15'd0;
-reg [2:0] litedramcore_ext_dfi_p0_bank = 3'd0;
-reg litedramcore_ext_dfi_p0_cas_n = 1'd1;
-reg litedramcore_ext_dfi_p0_cs_n = 1'd1;
-reg litedramcore_ext_dfi_p0_ras_n = 1'd1;
-reg litedramcore_ext_dfi_p0_we_n = 1'd1;
-reg litedramcore_ext_dfi_p0_cke = 1'd0;
-reg litedramcore_ext_dfi_p0_odt = 1'd0;
-reg litedramcore_ext_dfi_p0_reset_n = 1'd0;
-reg litedramcore_ext_dfi_p0_act_n = 1'd1;
-reg [63:0] litedramcore_ext_dfi_p0_wrdata = 64'd0;
-reg litedramcore_ext_dfi_p0_wrdata_en = 1'd0;
-reg [7:0] litedramcore_ext_dfi_p0_wrdata_mask = 8'd0;
-reg litedramcore_ext_dfi_p0_rddata_en = 1'd0;
-reg [63:0] litedramcore_ext_dfi_p0_rddata = 64'd0;
-reg litedramcore_ext_dfi_p0_rddata_valid = 1'd0;
-reg [14:0] litedramcore_ext_dfi_p1_address = 15'd0;
-reg [2:0] litedramcore_ext_dfi_p1_bank = 3'd0;
-reg litedramcore_ext_dfi_p1_cas_n = 1'd1;
-reg litedramcore_ext_dfi_p1_cs_n = 1'd1;
-reg litedramcore_ext_dfi_p1_ras_n = 1'd1;
-reg litedramcore_ext_dfi_p1_we_n = 1'd1;
-reg litedramcore_ext_dfi_p1_cke = 1'd0;
-reg litedramcore_ext_dfi_p1_odt = 1'd0;
-reg litedramcore_ext_dfi_p1_reset_n = 1'd0;
-reg litedramcore_ext_dfi_p1_act_n = 1'd1;
-reg [63:0] litedramcore_ext_dfi_p1_wrdata = 64'd0;
-reg litedramcore_ext_dfi_p1_wrdata_en = 1'd0;
-reg [7:0] litedramcore_ext_dfi_p1_wrdata_mask = 8'd0;
-reg litedramcore_ext_dfi_p1_rddata_en = 1'd0;
-reg [63:0] litedramcore_ext_dfi_p1_rddata = 64'd0;
-reg litedramcore_ext_dfi_p1_rddata_valid = 1'd0;
-reg litedramcore_ext_dfi_sel = 1'd0;
-wire litedramcore_sel;
-wire litedramcore_cke;
-wire litedramcore_odt;
-wire litedramcore_reset_n;
-reg [3:0] litedramcore_storage = 4'd1;
-reg litedramcore_re = 1'd0;
-wire litedramcore_phaseinjector0_csrfield_cs;
-wire litedramcore_phaseinjector0_csrfield_we;
-wire litedramcore_phaseinjector0_csrfield_cas;
-wire litedramcore_phaseinjector0_csrfield_ras;
-wire litedramcore_phaseinjector0_csrfield_wren;
-wire litedramcore_phaseinjector0_csrfield_rden;
-reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0;
-reg litedramcore_phaseinjector0_command_re = 1'd0;
-reg litedramcore_phaseinjector0_command_issue_re = 1'd0;
-wire litedramcore_phaseinjector0_command_issue_r;
-reg litedramcore_phaseinjector0_command_issue_we = 1'd0;
-reg litedramcore_phaseinjector0_command_issue_w = 1'd0;
-reg [14:0] litedramcore_phaseinjector0_address_storage = 15'd0;
-reg litedramcore_phaseinjector0_address_re = 1'd0;
-reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0;
-reg litedramcore_phaseinjector0_baddress_re = 1'd0;
-reg [63:0] litedramcore_phaseinjector0_wrdata_storage = 64'd0;
-reg litedramcore_phaseinjector0_wrdata_re = 1'd0;
-reg [63:0] litedramcore_phaseinjector0_rddata_status = 64'd0;
-wire litedramcore_phaseinjector0_rddata_we;
-reg litedramcore_phaseinjector0_rddata_re = 1'd0;
-wire litedramcore_phaseinjector1_csrfield_cs;
-wire litedramcore_phaseinjector1_csrfield_we;
-wire litedramcore_phaseinjector1_csrfield_cas;
-wire litedramcore_phaseinjector1_csrfield_ras;
-wire litedramcore_phaseinjector1_csrfield_wren;
-wire litedramcore_phaseinjector1_csrfield_rden;
-reg [5:0] litedramcore_phaseinjector1_command_storage = 6'd0;
-reg litedramcore_phaseinjector1_command_re = 1'd0;
-reg litedramcore_phaseinjector1_command_issue_re = 1'd0;
-wire litedramcore_phaseinjector1_command_issue_r;
-reg litedramcore_phaseinjector1_command_issue_we = 1'd0;
-reg litedramcore_phaseinjector1_command_issue_w = 1'd0;
-reg [14:0] litedramcore_phaseinjector1_address_storage = 15'd0;
-reg litedramcore_phaseinjector1_address_re = 1'd0;
-reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0;
-reg litedramcore_phaseinjector1_baddress_re = 1'd0;
-reg [63:0] litedramcore_phaseinjector1_wrdata_storage = 64'd0;
-reg litedramcore_phaseinjector1_wrdata_re = 1'd0;
-reg [63:0] litedramcore_phaseinjector1_rddata_status = 64'd0;
-wire litedramcore_phaseinjector1_rddata_we;
-reg litedramcore_phaseinjector1_rddata_re = 1'd0;
-wire litedramcore_interface_bank0_valid;
-wire litedramcore_interface_bank0_ready;
-wire litedramcore_interface_bank0_we;
-wire [21:0] litedramcore_interface_bank0_addr;
-wire litedramcore_interface_bank0_lock;
-wire litedramcore_interface_bank0_wdata_ready;
-wire litedramcore_interface_bank0_rdata_valid;
-wire litedramcore_interface_bank1_valid;
-wire litedramcore_interface_bank1_ready;
-wire litedramcore_interface_bank1_we;
-wire [21:0] litedramcore_interface_bank1_addr;
-wire litedramcore_interface_bank1_lock;
-wire litedramcore_interface_bank1_wdata_ready;
-wire litedramcore_interface_bank1_rdata_valid;
-wire litedramcore_interface_bank2_valid;
-wire litedramcore_interface_bank2_ready;
-wire litedramcore_interface_bank2_we;
-wire [21:0] litedramcore_interface_bank2_addr;
-wire litedramcore_interface_bank2_lock;
-wire litedramcore_interface_bank2_wdata_ready;
-wire litedramcore_interface_bank2_rdata_valid;
-wire litedramcore_interface_bank3_valid;
-wire litedramcore_interface_bank3_ready;
-wire litedramcore_interface_bank3_we;
-wire [21:0] litedramcore_interface_bank3_addr;
-wire litedramcore_interface_bank3_lock;
-wire litedramcore_interface_bank3_wdata_ready;
-wire litedramcore_interface_bank3_rdata_valid;
-wire litedramcore_interface_bank4_valid;
-wire litedramcore_interface_bank4_ready;
-wire litedramcore_interface_bank4_we;
-wire [21:0] litedramcore_interface_bank4_addr;
-wire litedramcore_interface_bank4_lock;
-wire litedramcore_interface_bank4_wdata_ready;
-wire litedramcore_interface_bank4_rdata_valid;
-wire litedramcore_interface_bank5_valid;
-wire litedramcore_interface_bank5_ready;
-wire litedramcore_interface_bank5_we;
-wire [21:0] litedramcore_interface_bank5_addr;
-wire litedramcore_interface_bank5_lock;
-wire litedramcore_interface_bank5_wdata_ready;
-wire litedramcore_interface_bank5_rdata_valid;
-wire litedramcore_interface_bank6_valid;
-wire litedramcore_interface_bank6_ready;
-wire litedramcore_interface_bank6_we;
-wire [21:0] litedramcore_interface_bank6_addr;
-wire litedramcore_interface_bank6_lock;
-wire litedramcore_interface_bank6_wdata_ready;
-wire litedramcore_interface_bank6_rdata_valid;
-wire litedramcore_interface_bank7_valid;
-wire litedramcore_interface_bank7_ready;
-wire litedramcore_interface_bank7_we;
-wire [21:0] litedramcore_interface_bank7_addr;
-wire litedramcore_interface_bank7_lock;
-wire litedramcore_interface_bank7_wdata_ready;
-wire litedramcore_interface_bank7_rdata_valid;
-reg [127:0] litedramcore_interface_wdata = 128'd0;
-reg [15:0] litedramcore_interface_wdata_we = 16'd0;
-wire [127:0] litedramcore_interface_rdata;
-reg [14:0] litedramcore_dfi_p0_address = 15'd0;
-reg [2:0] litedramcore_dfi_p0_bank = 3'd0;
-reg litedramcore_dfi_p0_cas_n = 1'd1;
-reg litedramcore_dfi_p0_cs_n = 1'd1;
-reg litedramcore_dfi_p0_ras_n = 1'd1;
-reg litedramcore_dfi_p0_we_n = 1'd1;
-wire litedramcore_dfi_p0_cke;
-wire litedramcore_dfi_p0_odt;
-wire litedramcore_dfi_p0_reset_n;
-reg litedramcore_dfi_p0_act_n = 1'd1;
-wire [63:0] litedramcore_dfi_p0_wrdata;
-reg litedramcore_dfi_p0_wrdata_en = 1'd0;
-wire [7:0] litedramcore_dfi_p0_wrdata_mask;
-reg litedramcore_dfi_p0_rddata_en = 1'd0;
-wire [63:0] litedramcore_dfi_p0_rddata;
-wire litedramcore_dfi_p0_rddata_valid;
-reg [14:0] litedramcore_dfi_p1_address = 15'd0;
-reg [2:0] litedramcore_dfi_p1_bank = 3'd0;
-reg litedramcore_dfi_p1_cas_n = 1'd1;
-reg litedramcore_dfi_p1_cs_n = 1'd1;
-reg litedramcore_dfi_p1_ras_n = 1'd1;
-reg litedramcore_dfi_p1_we_n = 1'd1;
-wire litedramcore_dfi_p1_cke;
-wire litedramcore_dfi_p1_odt;
-wire litedramcore_dfi_p1_reset_n;
-reg litedramcore_dfi_p1_act_n = 1'd1;
-wire [63:0] litedramcore_dfi_p1_wrdata;
-reg litedramcore_dfi_p1_wrdata_en = 1'd0;
-wire [7:0] litedramcore_dfi_p1_wrdata_mask;
-reg litedramcore_dfi_p1_rddata_en = 1'd0;
-wire [63:0] litedramcore_dfi_p1_rddata;
-wire litedramcore_dfi_p1_rddata_valid;
-reg litedramcore_cmd_valid = 1'd0;
-reg litedramcore_cmd_ready = 1'd0;
-reg litedramcore_cmd_last = 1'd0;
-reg [14:0] litedramcore_cmd_payload_a = 15'd0;
-reg [2:0] litedramcore_cmd_payload_ba = 3'd0;
-reg litedramcore_cmd_payload_cas = 1'd0;
-reg litedramcore_cmd_payload_ras = 1'd0;
-reg litedramcore_cmd_payload_we = 1'd0;
-reg litedramcore_cmd_payload_is_read = 1'd0;
-reg litedramcore_cmd_payload_is_write = 1'd0;
-wire litedramcore_wants_refresh;
-wire litedramcore_wants_zqcs;
-wire litedramcore_timer_wait;
-wire litedramcore_timer_done0;
-wire [8:0] litedramcore_timer_count0;
-wire litedramcore_timer_done1;
-reg [8:0] litedramcore_timer_count1 = 9'd374;
-wire litedramcore_postponer_req_i;
-reg litedramcore_postponer_req_o = 1'd0;
-reg litedramcore_postponer_count = 1'd0;
-reg litedramcore_sequencer_start0 = 1'd0;
-wire litedramcore_sequencer_done0;
-wire litedramcore_sequencer_start1;
-reg litedramcore_sequencer_done1 = 1'd0;
-reg [6:0] litedramcore_sequencer_counter = 7'd0;
-reg litedramcore_sequencer_count = 1'd0;
-wire litedramcore_zqcs_timer_wait;
-wire litedramcore_zqcs_timer_done0;
-wire [25:0] litedramcore_zqcs_timer_count0;
-wire litedramcore_zqcs_timer_done1;
-reg [25:0] litedramcore_zqcs_timer_count1 = 26'd47999999;
-reg litedramcore_zqcs_executer_start = 1'd0;
-reg litedramcore_zqcs_executer_done = 1'd0;
-reg [5:0] litedramcore_zqcs_executer_counter = 6'd0;
-wire litedramcore_bankmachine0_req_valid;
-wire litedramcore_bankmachine0_req_ready;
-wire litedramcore_bankmachine0_req_we;
-wire [21:0] litedramcore_bankmachine0_req_addr;
-wire litedramcore_bankmachine0_req_lock;
-reg litedramcore_bankmachine0_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine0_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine0_refresh_req;
-reg litedramcore_bankmachine0_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine0_cmd_valid = 1'd0;
-reg litedramcore_bankmachine0_cmd_ready = 1'd0;
-reg [14:0] litedramcore_bankmachine0_cmd_payload_a = 15'd0;
-wire [2:0] litedramcore_bankmachine0_cmd_payload_ba;
-reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine0_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine0_auto_precharge = 1'd0;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
-wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
-wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-reg [4:0] litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we;
-wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine0_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine0_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine0_cmd_buffer_sink_first;
-wire litedramcore_bankmachine0_cmd_buffer_sink_last;
-wire litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
-wire [21:0] litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine0_cmd_buffer_source_ready;
-reg litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] litedramcore_bankmachine0_row = 15'd0;
-reg litedramcore_bankmachine0_row_opened = 1'd0;
-wire litedramcore_bankmachine0_row_hit;
-reg litedramcore_bankmachine0_row_open = 1'd0;
-reg litedramcore_bankmachine0_row_close = 1'd0;
-reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine0_twtpcon_valid;
-reg litedramcore_bankmachine0_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine0_trccon_valid;
-reg litedramcore_bankmachine0_trccon_ready = 1'd0;
-reg [1:0] litedramcore_bankmachine0_trccon_count = 2'd0;
-wire litedramcore_bankmachine0_trascon_valid;
-reg litedramcore_bankmachine0_trascon_ready = 1'd0;
-reg [1:0] litedramcore_bankmachine0_trascon_count = 2'd0;
-wire litedramcore_bankmachine1_req_valid;
-wire litedramcore_bankmachine1_req_ready;
-wire litedramcore_bankmachine1_req_we;
-wire [21:0] litedramcore_bankmachine1_req_addr;
-wire litedramcore_bankmachine1_req_lock;
-reg litedramcore_bankmachine1_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine1_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine1_refresh_req;
-reg litedramcore_bankmachine1_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine1_cmd_valid = 1'd0;
-reg litedramcore_bankmachine1_cmd_ready = 1'd0;
-reg [14:0] litedramcore_bankmachine1_cmd_payload_a = 15'd0;
-wire [2:0] litedramcore_bankmachine1_cmd_payload_ba;
-reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine1_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine1_auto_precharge = 1'd0;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
-wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
-wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-reg [4:0] litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we;
-wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine1_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine1_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine1_cmd_buffer_sink_first;
-wire litedramcore_bankmachine1_cmd_buffer_sink_last;
-wire litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
-wire [21:0] litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine1_cmd_buffer_source_ready;
-reg litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] litedramcore_bankmachine1_row = 15'd0;
-reg litedramcore_bankmachine1_row_opened = 1'd0;
-wire litedramcore_bankmachine1_row_hit;
-reg litedramcore_bankmachine1_row_open = 1'd0;
-reg litedramcore_bankmachine1_row_close = 1'd0;
-reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine1_twtpcon_valid;
-reg litedramcore_bankmachine1_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine1_trccon_valid;
-reg litedramcore_bankmachine1_trccon_ready = 1'd0;
-reg [1:0] litedramcore_bankmachine1_trccon_count = 2'd0;
-wire litedramcore_bankmachine1_trascon_valid;
-reg litedramcore_bankmachine1_trascon_ready = 1'd0;
-reg [1:0] litedramcore_bankmachine1_trascon_count = 2'd0;
-wire litedramcore_bankmachine2_req_valid;
-wire litedramcore_bankmachine2_req_ready;
-wire litedramcore_bankmachine2_req_we;
-wire [21:0] litedramcore_bankmachine2_req_addr;
-wire litedramcore_bankmachine2_req_lock;
-reg litedramcore_bankmachine2_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine2_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine2_refresh_req;
-reg litedramcore_bankmachine2_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine2_cmd_valid = 1'd0;
-reg litedramcore_bankmachine2_cmd_ready = 1'd0;
-reg [14:0] litedramcore_bankmachine2_cmd_payload_a = 15'd0;
-wire [2:0] litedramcore_bankmachine2_cmd_payload_ba;
-reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine2_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine2_auto_precharge = 1'd0;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
-wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
-wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-reg [4:0] litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we;
-wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine2_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine2_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine2_cmd_buffer_sink_first;
-wire litedramcore_bankmachine2_cmd_buffer_sink_last;
-wire litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
-wire [21:0] litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine2_cmd_buffer_source_ready;
-reg litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] litedramcore_bankmachine2_row = 15'd0;
-reg litedramcore_bankmachine2_row_opened = 1'd0;
-wire litedramcore_bankmachine2_row_hit;
-reg litedramcore_bankmachine2_row_open = 1'd0;
-reg litedramcore_bankmachine2_row_close = 1'd0;
-reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine2_twtpcon_valid;
-reg litedramcore_bankmachine2_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine2_trccon_valid;
-reg litedramcore_bankmachine2_trccon_ready = 1'd0;
-reg [1:0] litedramcore_bankmachine2_trccon_count = 2'd0;
-wire litedramcore_bankmachine2_trascon_valid;
-reg litedramcore_bankmachine2_trascon_ready = 1'd0;
-reg [1:0] litedramcore_bankmachine2_trascon_count = 2'd0;
-wire litedramcore_bankmachine3_req_valid;
-wire litedramcore_bankmachine3_req_ready;
-wire litedramcore_bankmachine3_req_we;
-wire [21:0] litedramcore_bankmachine3_req_addr;
-wire litedramcore_bankmachine3_req_lock;
-reg litedramcore_bankmachine3_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine3_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine3_refresh_req;
-reg litedramcore_bankmachine3_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine3_cmd_valid = 1'd0;
-reg litedramcore_bankmachine3_cmd_ready = 1'd0;
-reg [14:0] litedramcore_bankmachine3_cmd_payload_a = 15'd0;
-wire [2:0] litedramcore_bankmachine3_cmd_payload_ba;
-reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine3_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine3_auto_precharge = 1'd0;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
-wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
-wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-reg [4:0] litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we;
-wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine3_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine3_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine3_cmd_buffer_sink_first;
-wire litedramcore_bankmachine3_cmd_buffer_sink_last;
-wire litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
-wire [21:0] litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine3_cmd_buffer_source_ready;
-reg litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] litedramcore_bankmachine3_row = 15'd0;
-reg litedramcore_bankmachine3_row_opened = 1'd0;
-wire litedramcore_bankmachine3_row_hit;
-reg litedramcore_bankmachine3_row_open = 1'd0;
-reg litedramcore_bankmachine3_row_close = 1'd0;
-reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine3_twtpcon_valid;
-reg litedramcore_bankmachine3_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine3_trccon_valid;
-reg litedramcore_bankmachine3_trccon_ready = 1'd0;
-reg [1:0] litedramcore_bankmachine3_trccon_count = 2'd0;
-wire litedramcore_bankmachine3_trascon_valid;
-reg litedramcore_bankmachine3_trascon_ready = 1'd0;
-reg [1:0] litedramcore_bankmachine3_trascon_count = 2'd0;
-wire litedramcore_bankmachine4_req_valid;
-wire litedramcore_bankmachine4_req_ready;
-wire litedramcore_bankmachine4_req_we;
-wire [21:0] litedramcore_bankmachine4_req_addr;
-wire litedramcore_bankmachine4_req_lock;
-reg litedramcore_bankmachine4_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine4_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine4_refresh_req;
-reg litedramcore_bankmachine4_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine4_cmd_valid = 1'd0;
-reg litedramcore_bankmachine4_cmd_ready = 1'd0;
-reg [14:0] litedramcore_bankmachine4_cmd_payload_a = 15'd0;
-wire [2:0] litedramcore_bankmachine4_cmd_payload_ba;
-reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine4_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine4_auto_precharge = 1'd0;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
-wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
-wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-reg [4:0] litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we;
-wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine4_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine4_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine4_cmd_buffer_sink_first;
-wire litedramcore_bankmachine4_cmd_buffer_sink_last;
-wire litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
-wire [21:0] litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine4_cmd_buffer_source_ready;
-reg litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] litedramcore_bankmachine4_row = 15'd0;
-reg litedramcore_bankmachine4_row_opened = 1'd0;
-wire litedramcore_bankmachine4_row_hit;
-reg litedramcore_bankmachine4_row_open = 1'd0;
-reg litedramcore_bankmachine4_row_close = 1'd0;
-reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine4_twtpcon_valid;
-reg litedramcore_bankmachine4_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine4_trccon_valid;
-reg litedramcore_bankmachine4_trccon_ready = 1'd0;
-reg [1:0] litedramcore_bankmachine4_trccon_count = 2'd0;
-wire litedramcore_bankmachine4_trascon_valid;
-reg litedramcore_bankmachine4_trascon_ready = 1'd0;
-reg [1:0] litedramcore_bankmachine4_trascon_count = 2'd0;
-wire litedramcore_bankmachine5_req_valid;
-wire litedramcore_bankmachine5_req_ready;
-wire litedramcore_bankmachine5_req_we;
-wire [21:0] litedramcore_bankmachine5_req_addr;
-wire litedramcore_bankmachine5_req_lock;
-reg litedramcore_bankmachine5_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine5_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine5_refresh_req;
-reg litedramcore_bankmachine5_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine5_cmd_valid = 1'd0;
-reg litedramcore_bankmachine5_cmd_ready = 1'd0;
-reg [14:0] litedramcore_bankmachine5_cmd_payload_a = 15'd0;
-wire [2:0] litedramcore_bankmachine5_cmd_payload_ba;
-reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine5_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine5_auto_precharge = 1'd0;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
-wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
-wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-reg [4:0] litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we;
-wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine5_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine5_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine5_cmd_buffer_sink_first;
-wire litedramcore_bankmachine5_cmd_buffer_sink_last;
-wire litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
-wire [21:0] litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine5_cmd_buffer_source_ready;
-reg litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] litedramcore_bankmachine5_row = 15'd0;
-reg litedramcore_bankmachine5_row_opened = 1'd0;
-wire litedramcore_bankmachine5_row_hit;
-reg litedramcore_bankmachine5_row_open = 1'd0;
-reg litedramcore_bankmachine5_row_close = 1'd0;
-reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine5_twtpcon_valid;
-reg litedramcore_bankmachine5_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine5_trccon_valid;
-reg litedramcore_bankmachine5_trccon_ready = 1'd0;
-reg [1:0] litedramcore_bankmachine5_trccon_count = 2'd0;
-wire litedramcore_bankmachine5_trascon_valid;
-reg litedramcore_bankmachine5_trascon_ready = 1'd0;
-reg [1:0] litedramcore_bankmachine5_trascon_count = 2'd0;
-wire litedramcore_bankmachine6_req_valid;
-wire litedramcore_bankmachine6_req_ready;
-wire litedramcore_bankmachine6_req_we;
-wire [21:0] litedramcore_bankmachine6_req_addr;
-wire litedramcore_bankmachine6_req_lock;
-reg litedramcore_bankmachine6_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine6_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine6_refresh_req;
-reg litedramcore_bankmachine6_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine6_cmd_valid = 1'd0;
-reg litedramcore_bankmachine6_cmd_ready = 1'd0;
-reg [14:0] litedramcore_bankmachine6_cmd_payload_a = 15'd0;
-wire [2:0] litedramcore_bankmachine6_cmd_payload_ba;
-reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine6_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine6_auto_precharge = 1'd0;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
-wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
-wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-reg [4:0] litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we;
-wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine6_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine6_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine6_cmd_buffer_sink_first;
-wire litedramcore_bankmachine6_cmd_buffer_sink_last;
-wire litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
-wire [21:0] litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine6_cmd_buffer_source_ready;
-reg litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] litedramcore_bankmachine6_row = 15'd0;
-reg litedramcore_bankmachine6_row_opened = 1'd0;
-wire litedramcore_bankmachine6_row_hit;
-reg litedramcore_bankmachine6_row_open = 1'd0;
-reg litedramcore_bankmachine6_row_close = 1'd0;
-reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine6_twtpcon_valid;
-reg litedramcore_bankmachine6_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine6_trccon_valid;
-reg litedramcore_bankmachine6_trccon_ready = 1'd0;
-reg [1:0] litedramcore_bankmachine6_trccon_count = 2'd0;
-wire litedramcore_bankmachine6_trascon_valid;
-reg litedramcore_bankmachine6_trascon_ready = 1'd0;
-reg [1:0] litedramcore_bankmachine6_trascon_count = 2'd0;
-wire litedramcore_bankmachine7_req_valid;
-wire litedramcore_bankmachine7_req_ready;
-wire litedramcore_bankmachine7_req_we;
-wire [21:0] litedramcore_bankmachine7_req_addr;
-wire litedramcore_bankmachine7_req_lock;
-reg litedramcore_bankmachine7_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine7_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine7_refresh_req;
-reg litedramcore_bankmachine7_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine7_cmd_valid = 1'd0;
-reg litedramcore_bankmachine7_cmd_ready = 1'd0;
-reg [14:0] litedramcore_bankmachine7_cmd_payload_a = 15'd0;
-wire [2:0] litedramcore_bankmachine7_cmd_payload_ba;
-reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine7_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine7_auto_precharge = 1'd0;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
-wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
-wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
-wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
-wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-reg [4:0] litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we;
-wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr;
-wire [24:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [21:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine7_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine7_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine7_cmd_buffer_sink_first;
-wire litedramcore_bankmachine7_cmd_buffer_sink_last;
-wire litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
-wire [21:0] litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine7_cmd_buffer_source_ready;
-reg litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
-reg [21:0] litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 22'd0;
-reg [14:0] litedramcore_bankmachine7_row = 15'd0;
-reg litedramcore_bankmachine7_row_opened = 1'd0;
-wire litedramcore_bankmachine7_row_hit;
-reg litedramcore_bankmachine7_row_open = 1'd0;
-reg litedramcore_bankmachine7_row_close = 1'd0;
-reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine7_twtpcon_valid;
-reg litedramcore_bankmachine7_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine7_trccon_valid;
-reg litedramcore_bankmachine7_trccon_ready = 1'd0;
-reg [1:0] litedramcore_bankmachine7_trccon_count = 2'd0;
-wire litedramcore_bankmachine7_trascon_valid;
-reg litedramcore_bankmachine7_trascon_ready = 1'd0;
-reg [1:0] litedramcore_bankmachine7_trascon_count = 2'd0;
-wire litedramcore_ras_allowed;
-wire litedramcore_cas_allowed;
-reg litedramcore_choose_cmd_want_reads = 1'd0;
-reg litedramcore_choose_cmd_want_writes = 1'd0;
-reg litedramcore_choose_cmd_want_cmds = 1'd0;
-reg litedramcore_choose_cmd_want_activates = 1'd0;
-wire litedramcore_choose_cmd_cmd_valid;
-reg litedramcore_choose_cmd_cmd_ready = 1'd0;
-wire [14:0] litedramcore_choose_cmd_cmd_payload_a;
-wire [2:0] litedramcore_choose_cmd_cmd_payload_ba;
-reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
-reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
-reg litedramcore_choose_cmd_cmd_payload_we = 1'd0;
-wire litedramcore_choose_cmd_cmd_payload_is_cmd;
-wire litedramcore_choose_cmd_cmd_payload_is_read;
-wire litedramcore_choose_cmd_cmd_payload_is_write;
-reg [7:0] litedramcore_choose_cmd_valids = 8'd0;
-wire [7:0] litedramcore_choose_cmd_request;
-reg [2:0] litedramcore_choose_cmd_grant = 3'd0;
-wire litedramcore_choose_cmd_ce;
-reg litedramcore_choose_req_want_reads = 1'd0;
-reg litedramcore_choose_req_want_writes = 1'd0;
-reg litedramcore_choose_req_want_cmds = 1'd0;
-reg litedramcore_choose_req_want_activates = 1'd0;
-wire litedramcore_choose_req_cmd_valid;
-reg litedramcore_choose_req_cmd_ready = 1'd0;
-wire [14:0] litedramcore_choose_req_cmd_payload_a;
-wire [2:0] litedramcore_choose_req_cmd_payload_ba;
-reg litedramcore_choose_req_cmd_payload_cas = 1'd0;
-reg litedramcore_choose_req_cmd_payload_ras = 1'd0;
-reg litedramcore_choose_req_cmd_payload_we = 1'd0;
-wire litedramcore_choose_req_cmd_payload_is_cmd;
-wire litedramcore_choose_req_cmd_payload_is_read;
-wire litedramcore_choose_req_cmd_payload_is_write;
-reg [7:0] litedramcore_choose_req_valids = 8'd0;
-wire [7:0] litedramcore_choose_req_request;
-reg [2:0] litedramcore_choose_req_grant = 3'd0;
-wire litedramcore_choose_req_ce;
-reg [14:0] litedramcore_nop_a = 15'd0;
-reg [2:0] litedramcore_nop_ba = 3'd0;
-reg [1:0] litedramcore_steerer_sel0 = 2'd0;
-reg [1:0] litedramcore_steerer_sel1 = 2'd0;
-reg litedramcore_steerer0 = 1'd1;
-reg litedramcore_steerer1 = 1'd1;
-reg litedramcore_steerer2 = 1'd1;
-reg litedramcore_steerer3 = 1'd1;
-wire litedramcore_trrdcon_valid;
-reg litedramcore_trrdcon_ready = 1'd0;
-reg litedramcore_trrdcon_count = 1'd0;
-wire litedramcore_tfawcon_valid;
-reg litedramcore_tfawcon_ready = 1'd1;
-wire [1:0] litedramcore_tfawcon_count;
-reg [2:0] litedramcore_tfawcon_window = 3'd0;
-wire litedramcore_tccdcon_valid;
-reg litedramcore_tccdcon_ready = 1'd0;
-reg litedramcore_tccdcon_count = 1'd0;
-wire litedramcore_twtrcon_valid;
-reg litedramcore_twtrcon_ready = 1'd0;
-reg [2:0] litedramcore_twtrcon_count = 3'd0;
-wire litedramcore_read_available;
-wire litedramcore_write_available;
-reg litedramcore_en0 = 1'd0;
-wire litedramcore_max_time0;
-reg [4:0] litedramcore_time0 = 5'd0;
-reg litedramcore_en1 = 1'd0;
-wire litedramcore_max_time1;
-reg [3:0] litedramcore_time1 = 4'd0;
-wire litedramcore_go_to_refresh;
-reg init_done_storage = 1'd0;
-reg init_done_re = 1'd0;
-reg init_error_storage = 1'd0;
-reg init_error_re = 1'd0;
-wire [29:0] wb_bus_adr;
-wire [31:0] wb_bus_dat_w;
-wire [31:0] wb_bus_dat_r;
-wire [3:0] wb_bus_sel;
-wire wb_bus_cyc;
-wire wb_bus_stb;
-wire wb_bus_ack;
-wire wb_bus_we;
-wire [2:0] wb_bus_cti;
-wire [1:0] wb_bus_bte;
-wire wb_bus_err;
-wire user_enable;
-wire user_port_cmd_valid;
-wire user_port_cmd_ready;
-wire user_port_cmd_payload_we;
-wire [24:0] user_port_cmd_payload_addr;
-wire user_port_wdata_valid;
-wire user_port_wdata_ready;
-wire [127:0] user_port_wdata_payload_data;
-wire [15:0] user_port_wdata_payload_we;
-wire user_port_rdata_valid;
-wire user_port_rdata_ready;
-wire [127:0] user_port_rdata_payload_data;
-reg [13:0] litedramcore_adr = 14'd0;
-reg litedramcore_we = 1'd0;
-reg [31:0] litedramcore_dat_w = 32'd0;
-wire [31:0] litedramcore_dat_r;
-wire [29:0] litedramcore_wishbone_adr;
-wire [31:0] litedramcore_wishbone_dat_w;
-reg [31:0] litedramcore_wishbone_dat_r = 32'd0;
-wire [3:0] litedramcore_wishbone_sel;
-wire litedramcore_wishbone_cyc;
-wire litedramcore_wishbone_stb;
-reg litedramcore_wishbone_ack = 1'd0;
-wire litedramcore_wishbone_we;
-wire [2:0] litedramcore_wishbone_cti;
-wire [1:0] litedramcore_wishbone_bte;
-reg litedramcore_wishbone_err = 1'd0;
-wire [13:0] interface0_bank_bus_adr;
-wire interface0_bank_bus_we;
-wire [31:0] interface0_bank_bus_dat_w;
-reg [31:0] interface0_bank_bus_dat_r = 32'd0;
-reg csrbank0_init_done0_re = 1'd0;
-wire csrbank0_init_done0_r;
-reg csrbank0_init_done0_we = 1'd0;
-wire csrbank0_init_done0_w;
-reg csrbank0_init_error0_re = 1'd0;
-wire csrbank0_init_error0_r;
-reg csrbank0_init_error0_we = 1'd0;
-wire csrbank0_init_error0_w;
-wire csrbank0_sel;
-wire [13:0] interface1_bank_bus_adr;
-wire interface1_bank_bus_we;
-wire [31:0] interface1_bank_bus_dat_w;
-reg [31:0] interface1_bank_bus_dat_r = 32'd0;
-reg csrbank1_dly_sel0_re = 1'd0;
-wire [1:0] csrbank1_dly_sel0_r;
-reg csrbank1_dly_sel0_we = 1'd0;
-wire [1:0] csrbank1_dly_sel0_w;
-reg csrbank1_burstdet_seen_re = 1'd0;
-wire [1:0] csrbank1_burstdet_seen_r;
-reg csrbank1_burstdet_seen_we = 1'd0;
-wire [1:0] csrbank1_burstdet_seen_w;
-wire csrbank1_sel;
-wire [13:0] interface2_bank_bus_adr;
-wire interface2_bank_bus_we;
-wire [31:0] interface2_bank_bus_dat_w;
-reg [31:0] interface2_bank_bus_dat_r = 32'd0;
-reg csrbank2_dfii_control0_re = 1'd0;
-wire [3:0] csrbank2_dfii_control0_r;
-reg csrbank2_dfii_control0_we = 1'd0;
-wire [3:0] csrbank2_dfii_control0_w;
-reg csrbank2_dfii_pi0_command0_re = 1'd0;
-wire [5:0] csrbank2_dfii_pi0_command0_r;
-reg csrbank2_dfii_pi0_command0_we = 1'd0;
-wire [5:0] csrbank2_dfii_pi0_command0_w;
-reg csrbank2_dfii_pi0_address0_re = 1'd0;
-wire [14:0] csrbank2_dfii_pi0_address0_r;
-reg csrbank2_dfii_pi0_address0_we = 1'd0;
-wire [14:0] csrbank2_dfii_pi0_address0_w;
-reg csrbank2_dfii_pi0_baddress0_re = 1'd0;
-wire [2:0] csrbank2_dfii_pi0_baddress0_r;
-reg csrbank2_dfii_pi0_baddress0_we = 1'd0;
-wire [2:0] csrbank2_dfii_pi0_baddress0_w;
-reg csrbank2_dfii_pi0_wrdata1_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi0_wrdata1_r;
-reg csrbank2_dfii_pi0_wrdata1_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi0_wrdata1_w;
-reg csrbank2_dfii_pi0_wrdata0_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi0_wrdata0_r;
-reg csrbank2_dfii_pi0_wrdata0_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi0_wrdata0_w;
-reg csrbank2_dfii_pi0_rddata1_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi0_rddata1_r;
-reg csrbank2_dfii_pi0_rddata1_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi0_rddata1_w;
-reg csrbank2_dfii_pi0_rddata0_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi0_rddata0_r;
-reg csrbank2_dfii_pi0_rddata0_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi0_rddata0_w;
-reg csrbank2_dfii_pi1_command0_re = 1'd0;
-wire [5:0] csrbank2_dfii_pi1_command0_r;
-reg csrbank2_dfii_pi1_command0_we = 1'd0;
-wire [5:0] csrbank2_dfii_pi1_command0_w;
-reg csrbank2_dfii_pi1_address0_re = 1'd0;
-wire [14:0] csrbank2_dfii_pi1_address0_r;
-reg csrbank2_dfii_pi1_address0_we = 1'd0;
-wire [14:0] csrbank2_dfii_pi1_address0_w;
-reg csrbank2_dfii_pi1_baddress0_re = 1'd0;
-wire [2:0] csrbank2_dfii_pi1_baddress0_r;
-reg csrbank2_dfii_pi1_baddress0_we = 1'd0;
-wire [2:0] csrbank2_dfii_pi1_baddress0_w;
-reg csrbank2_dfii_pi1_wrdata1_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi1_wrdata1_r;
-reg csrbank2_dfii_pi1_wrdata1_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi1_wrdata1_w;
-reg csrbank2_dfii_pi1_wrdata0_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi1_wrdata0_r;
-reg csrbank2_dfii_pi1_wrdata0_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi1_wrdata0_w;
-reg csrbank2_dfii_pi1_rddata1_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi1_rddata1_r;
-reg csrbank2_dfii_pi1_rddata1_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi1_rddata1_w;
-reg csrbank2_dfii_pi1_rddata0_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi1_rddata0_r;
-reg csrbank2_dfii_pi1_rddata0_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi1_rddata0_w;
-wire csrbank2_sel;
-wire [13:0] csr_interconnect_adr;
-wire csr_interconnect_we;
-wire [31:0] csr_interconnect_dat_w;
-wire [31:0] csr_interconnect_dat_r;
-wire litedramcore_litedramecp5ddrphycrg_ecp5pll;
-wire litedramcore_litedramecp5ddrphycrg_locked;
-reg [1:0] litedramcore_litedramcore_refresher_state = 2'd0;
-reg [1:0] litedramcore_litedramcore_refresher_next_state = 2'd0;
-reg [2:0] litedramcore_litedramcore_bankmachine0_state = 3'd0;
-reg [2:0] litedramcore_litedramcore_bankmachine0_next_state = 3'd0;
-reg [2:0] litedramcore_litedramcore_bankmachine1_state = 3'd0;
-reg [2:0] litedramcore_litedramcore_bankmachine1_next_state = 3'd0;
-reg [2:0] litedramcore_litedramcore_bankmachine2_state = 3'd0;
-reg [2:0] litedramcore_litedramcore_bankmachine2_next_state = 3'd0;
-reg [2:0] litedramcore_litedramcore_bankmachine3_state = 3'd0;
-reg [2:0] litedramcore_litedramcore_bankmachine3_next_state = 3'd0;
-reg [2:0] litedramcore_litedramcore_bankmachine4_state = 3'd0;
-reg [2:0] litedramcore_litedramcore_bankmachine4_next_state = 3'd0;
-reg [2:0] litedramcore_litedramcore_bankmachine5_state = 3'd0;
-reg [2:0] litedramcore_litedramcore_bankmachine5_next_state = 3'd0;
-reg [2:0] litedramcore_litedramcore_bankmachine6_state = 3'd0;
-reg [2:0] litedramcore_litedramcore_bankmachine6_next_state = 3'd0;
-reg [2:0] litedramcore_litedramcore_bankmachine7_state = 3'd0;
-reg [2:0] litedramcore_litedramcore_bankmachine7_next_state = 3'd0;
-reg [3:0] litedramcore_litedramcore_multiplexer_state = 4'd0;
-reg [3:0] litedramcore_litedramcore_multiplexer_next_state = 4'd0;
-wire litedramcore_litedramcore_roundrobin0_request;
-wire litedramcore_litedramcore_roundrobin0_grant;
-wire litedramcore_litedramcore_roundrobin0_ce;
-wire litedramcore_litedramcore_roundrobin1_request;
-wire litedramcore_litedramcore_roundrobin1_grant;
-wire litedramcore_litedramcore_roundrobin1_ce;
-wire litedramcore_litedramcore_roundrobin2_request;
-wire litedramcore_litedramcore_roundrobin2_grant;
-wire litedramcore_litedramcore_roundrobin2_ce;
-wire litedramcore_litedramcore_roundrobin3_request;
-wire litedramcore_litedramcore_roundrobin3_grant;
-wire litedramcore_litedramcore_roundrobin3_ce;
-wire litedramcore_litedramcore_roundrobin4_request;
-wire litedramcore_litedramcore_roundrobin4_grant;
-wire litedramcore_litedramcore_roundrobin4_ce;
-wire litedramcore_litedramcore_roundrobin5_request;
-wire litedramcore_litedramcore_roundrobin5_grant;
-wire litedramcore_litedramcore_roundrobin5_ce;
-wire litedramcore_litedramcore_roundrobin6_request;
-wire litedramcore_litedramcore_roundrobin6_grant;
-wire litedramcore_litedramcore_roundrobin6_ce;
-wire litedramcore_litedramcore_roundrobin7_request;
-wire litedramcore_litedramcore_roundrobin7_grant;
-wire litedramcore_litedramcore_roundrobin7_ce;
-reg litedramcore_litedramcore_locked0 = 1'd0;
-reg litedramcore_litedramcore_locked1 = 1'd0;
-reg litedramcore_litedramcore_locked2 = 1'd0;
-reg litedramcore_litedramcore_locked3 = 1'd0;
-reg litedramcore_litedramcore_locked4 = 1'd0;
-reg litedramcore_litedramcore_locked5 = 1'd0;
-reg litedramcore_litedramcore_locked6 = 1'd0;
-reg litedramcore_litedramcore_locked7 = 1'd0;
-reg litedramcore_litedramcore_new_master_wdata_ready0 = 1'd0;
-reg litedramcore_litedramcore_new_master_wdata_ready1 = 1'd0;
-reg litedramcore_litedramcore_new_master_wdata_ready2 = 1'd0;
-reg litedramcore_litedramcore_new_master_wdata_ready3 = 1'd0;
-reg litedramcore_litedramcore_new_master_rdata_valid0 = 1'd0;
-reg litedramcore_litedramcore_new_master_rdata_valid1 = 1'd0;
-reg litedramcore_litedramcore_new_master_rdata_valid2 = 1'd0;
-reg litedramcore_litedramcore_new_master_rdata_valid3 = 1'd0;
-reg litedramcore_litedramcore_new_master_rdata_valid4 = 1'd0;
-reg litedramcore_litedramcore_new_master_rdata_valid5 = 1'd0;
-reg litedramcore_litedramcore_new_master_rdata_valid6 = 1'd0;
-reg litedramcore_litedramcore_new_master_rdata_valid7 = 1'd0;
-reg litedramcore_litedramcore_new_master_rdata_valid8 = 1'd0;
-reg litedramcore_litedramcore_new_master_rdata_valid9 = 1'd0;
-reg litedramcore_litedramcore_new_master_rdata_valid10 = 1'd0;
-reg litedramcore_litedramcore_new_master_rdata_valid11 = 1'd0;
-reg litedramcore_litedramcore_new_master_rdata_valid12 = 1'd0;
-reg litedramcore_litedramcore_new_master_rdata_valid13 = 1'd0;
-reg [1:0] litedramcore_state = 2'd0;
-reg [1:0] litedramcore_next_state = 2'd0;
-reg [31:0] litedramcore_dat_w_next_value0 = 32'd0;
-reg litedramcore_dat_w_next_value_ce0 = 1'd0;
-reg [13:0] litedramcore_adr_next_value1 = 14'd0;
-reg litedramcore_adr_next_value_ce1 = 1'd0;
-reg litedramcore_we_next_value2 = 1'd0;
-reg litedramcore_we_next_value_ce2 = 1'd0;
-reg rhs_array_muxed0 = 1'd0;
-reg [14:0] rhs_array_muxed1 = 15'd0;
-reg [2:0] rhs_array_muxed2 = 3'd0;
-reg rhs_array_muxed3 = 1'd0;
-reg rhs_array_muxed4 = 1'd0;
-reg rhs_array_muxed5 = 1'd0;
-reg t_array_muxed0 = 1'd0;
-reg t_array_muxed1 = 1'd0;
-reg t_array_muxed2 = 1'd0;
-reg rhs_array_muxed6 = 1'd0;
-reg [14:0] rhs_array_muxed7 = 15'd0;
-reg [2:0] rhs_array_muxed8 = 3'd0;
-reg rhs_array_muxed9 = 1'd0;
-reg rhs_array_muxed10 = 1'd0;
-reg rhs_array_muxed11 = 1'd0;
-reg t_array_muxed3 = 1'd0;
-reg t_array_muxed4 = 1'd0;
-reg t_array_muxed5 = 1'd0;
-reg [21:0] rhs_array_muxed12 = 22'd0;
-reg rhs_array_muxed13 = 1'd0;
-reg rhs_array_muxed14 = 1'd0;
-reg [21:0] rhs_array_muxed15 = 22'd0;
-reg rhs_array_muxed16 = 1'd0;
-reg rhs_array_muxed17 = 1'd0;
-reg [21:0] rhs_array_muxed18 = 22'd0;
-reg rhs_array_muxed19 = 1'd0;
-reg rhs_array_muxed20 = 1'd0;
-reg [21:0] rhs_array_muxed21 = 22'd0;
-reg rhs_array_muxed22 = 1'd0;
-reg rhs_array_muxed23 = 1'd0;
-reg [21:0] rhs_array_muxed24 = 22'd0;
-reg rhs_array_muxed25 = 1'd0;
-reg rhs_array_muxed26 = 1'd0;
-reg [21:0] rhs_array_muxed27 = 22'd0;
-reg rhs_array_muxed28 = 1'd0;
-reg rhs_array_muxed29 = 1'd0;
-reg [21:0] rhs_array_muxed30 = 22'd0;
-reg rhs_array_muxed31 = 1'd0;
-reg rhs_array_muxed32 = 1'd0;
-reg [21:0] rhs_array_muxed33 = 22'd0;
-reg rhs_array_muxed34 = 1'd0;
-reg rhs_array_muxed35 = 1'd0;
-reg [2:0] array_muxed0 = 3'd0;
-reg [14:0] array_muxed1 = 15'd0;
-reg array_muxed2 = 1'd0;
-reg array_muxed3 = 1'd0;
-reg array_muxed4 = 1'd0;
-reg array_muxed5 = 1'd0;
-reg array_muxed6 = 1'd0;
-reg [2:0] array_muxed7 = 3'd0;
-reg [14:0] array_muxed8 = 15'd0;
-reg array_muxed9 = 1'd0;
-reg array_muxed10 = 1'd0;
-reg array_muxed11 = 1'd0;
-reg array_muxed12 = 1'd0;
-reg array_muxed13 = 1'd0;
-wire latticeecp5asyncresetsynchronizerimpl0_rst1;
-wire latticeecp5asyncresetsynchronizerimpl0_expr;
-wire latticeecp5asyncresetsynchronizerimpl1_rst1;
-wire latticeecp5asyncresetsynchronizerimpl2_rst1;
-wire latticeecp5asyncresetsynchronizerimpl3_rst1;
-reg regs0 = 1'd0;
-reg regs1 = 1'd0;
+reg crg_rst = 1'd0;
+wire init_clk;
+wire init_rst;
+wire por_clk;
+wire sys_clk;
+wire sys_rst;
+wire sys2x_clk;
+wire sys2x_rst;
+wire sys2x_i_clk;
+wire crg_stop;
+wire crg_reset0;
+reg [15:0] crg_por_count = 16'd65535;
+wire crg_por_done;
+wire crg_sys2x_clk_ecsout;
+wire crg_reset1;
+wire crg_locked;
+reg crg_stdby = 1'd0;
+wire crg_clkin;
+wire crg_clkout0;
+wire crg_clkout1;
+wire ddrphy_pause0;
+wire ddrphy_stop0;
+wire ddrphy_delay0;
+wire ddrphy_reset0;
+wire ddrphy_new_lock;
+reg ddrphy_update = 1'd0;
+reg ddrphy_stop1 = 1'd0;
+reg ddrphy_freeze = 1'd0;
+reg ddrphy_pause1 = 1'd0;
+reg ddrphy_reset1 = 1'd0;
+wire ddrphy_lock0;
+wire ddrphy_delay1;
+wire ddrphy_lock1;
+reg ddrphy_lock_d = 1'd0;
+reg [6:0] ddrphy_counter = 7'd0;
+reg [1:0] ddrphy_dly_sel_storage = 2'd0;
+reg ddrphy_dly_sel_re = 1'd0;
+reg ddrphy_rdly_dq_rst_re = 1'd0;
+wire ddrphy_rdly_dq_rst_r;
+reg ddrphy_rdly_dq_rst_we = 1'd0;
+reg ddrphy_rdly_dq_rst_w = 1'd0;
+reg ddrphy_rdly_dq_inc_re = 1'd0;
+wire ddrphy_rdly_dq_inc_r;
+reg ddrphy_rdly_dq_inc_we = 1'd0;
+reg ddrphy_rdly_dq_inc_w = 1'd0;
+reg ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
+wire ddrphy_rdly_dq_bitslip_rst_r;
+reg ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
+reg ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
+reg ddrphy_rdly_dq_bitslip_re = 1'd0;
+wire ddrphy_rdly_dq_bitslip_r;
+reg ddrphy_rdly_dq_bitslip_we = 1'd0;
+reg ddrphy_rdly_dq_bitslip_w = 1'd0;
+reg ddrphy_burstdet_clr_re = 1'd0;
+wire ddrphy_burstdet_clr_r;
+reg ddrphy_burstdet_clr_we = 1'd0;
+reg ddrphy_burstdet_clr_w = 1'd0;
+reg [1:0] ddrphy_burstdet_seen_status = 2'd0;
+wire ddrphy_burstdet_seen_we;
+reg ddrphy_burstdet_seen_re = 1'd0;
+wire [1:0] ddrphy_datavalid;
+wire [14:0] ddrphy_dfi_p0_address;
+wire [2:0] ddrphy_dfi_p0_bank;
+wire ddrphy_dfi_p0_cas_n;
+wire ddrphy_dfi_p0_cs_n;
+wire ddrphy_dfi_p0_ras_n;
+wire ddrphy_dfi_p0_we_n;
+wire ddrphy_dfi_p0_cke;
+wire ddrphy_dfi_p0_odt;
+wire ddrphy_dfi_p0_reset_n;
+wire ddrphy_dfi_p0_act_n;
+wire [63:0] ddrphy_dfi_p0_wrdata;
+wire ddrphy_dfi_p0_wrdata_en;
+wire [7:0] ddrphy_dfi_p0_wrdata_mask;
+wire ddrphy_dfi_p0_rddata_en;
+reg [63:0] ddrphy_dfi_p0_rddata = 64'd0;
+wire ddrphy_dfi_p0_rddata_valid;
+wire [14:0] ddrphy_dfi_p1_address;
+wire [2:0] ddrphy_dfi_p1_bank;
+wire ddrphy_dfi_p1_cas_n;
+wire ddrphy_dfi_p1_cs_n;
+wire ddrphy_dfi_p1_ras_n;
+wire ddrphy_dfi_p1_we_n;
+wire ddrphy_dfi_p1_cke;
+wire ddrphy_dfi_p1_odt;
+wire ddrphy_dfi_p1_reset_n;
+wire ddrphy_dfi_p1_act_n;
+wire [63:0] ddrphy_dfi_p1_wrdata;
+wire ddrphy_dfi_p1_wrdata_en;
+wire [7:0] ddrphy_dfi_p1_wrdata_mask;
+wire ddrphy_dfi_p1_rddata_en;
+reg [63:0] ddrphy_dfi_p1_rddata = 64'd0;
+wire ddrphy_dfi_p1_rddata_valid;
+wire ddrphy_bl8_chunk;
+wire ddrphy_pad_oddrx2f0;
+wire ddrphy_pad_oddrx2f1;
+wire ddrphy_pad_oddrx2f2;
+wire ddrphy_pad_oddrx2f3;
+wire ddrphy_pad_oddrx2f4;
+wire ddrphy_pad_oddrx2f5;
+wire ddrphy_pad_oddrx2f6;
+wire ddrphy_pad_oddrx2f7;
+wire ddrphy_pad_oddrx2f8;
+wire ddrphy_pad_oddrx2f9;
+wire ddrphy_pad_oddrx2f10;
+wire ddrphy_pad_oddrx2f11;
+wire ddrphy_pad_oddrx2f12;
+wire ddrphy_pad_oddrx2f13;
+wire ddrphy_pad_oddrx2f14;
+wire ddrphy_pad_oddrx2f15;
+wire ddrphy_pad_oddrx2f16;
+wire ddrphy_pad_oddrx2f17;
+wire ddrphy_pad_oddrx2f18;
+wire ddrphy_pad_oddrx2f19;
+wire ddrphy_pad_oddrx2f20;
+wire ddrphy_pad_oddrx2f21;
+wire ddrphy_pad_oddrx2f22;
+wire ddrphy_pad_oddrx2f23;
+wire ddrphy_pad_oddrx2f24;
+wire ddrphy_pad_oddrx2f25;
+wire ddrphy_dq_oe;
+wire ddrphy_dqs_re;
+wire ddrphy_dqs_oe;
+wire ddrphy_dqs_postamble;
+wire ddrphy_dqs_preamble;
+wire ddrphy_dqs_i0;
+wire ddrphy_dqsr900;
+wire ddrphy_dqsw2700;
+wire ddrphy_dqsw0;
+wire [2:0] ddrphy_rdpntr0;
+wire [2:0] ddrphy_wrpntr0;
+reg [2:0] ddrphy_rdly0 = 3'd0;
+wire ddrphy_burstdet0;
+reg ddrphy_burstdet_d0 = 1'd0;
+wire ddrphy_dqs0;
+wire ddrphy_dqs_oe_n0;
+reg [7:0] ddrphy_dm_o_data0 = 8'd0;
+reg [7:0] ddrphy_dm_o_data_d0 = 8'd0;
+reg [3:0] ddrphy_dm_o_data_muxed0 = 4'd0;
+wire ddrphy_dq_o0;
+wire ddrphy_dq_i0;
+wire ddrphy_dq_oe_n0;
+wire ddrphy_dq_i_delayed0;
+wire [7:0] ddrphy_dq_i_data0;
+reg [7:0] ddrphy_dq_o_data0 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d0 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed0 = 4'd0;
+wire [3:0] ddrphy_bitslip0_i;
+reg [3:0] ddrphy_bitslip0_o = 4'd0;
+reg [1:0] ddrphy_bitslip0_value = 2'd0;
+reg [7:0] ddrphy_bitslip0_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d0 = 4'd0;
+wire ddrphy_dq_o1;
+wire ddrphy_dq_i1;
+wire ddrphy_dq_oe_n1;
+wire ddrphy_dq_i_delayed1;
+wire [7:0] ddrphy_dq_i_data1;
+reg [7:0] ddrphy_dq_o_data1 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d1 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed1 = 4'd0;
+wire [3:0] ddrphy_bitslip1_i;
+reg [3:0] ddrphy_bitslip1_o = 4'd0;
+reg [1:0] ddrphy_bitslip1_value = 2'd0;
+reg [7:0] ddrphy_bitslip1_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d1 = 4'd0;
+wire ddrphy_dq_o2;
+wire ddrphy_dq_i2;
+wire ddrphy_dq_oe_n2;
+wire ddrphy_dq_i_delayed2;
+wire [7:0] ddrphy_dq_i_data2;
+reg [7:0] ddrphy_dq_o_data2 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d2 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed2 = 4'd0;
+wire [3:0] ddrphy_bitslip2_i;
+reg [3:0] ddrphy_bitslip2_o = 4'd0;
+reg [1:0] ddrphy_bitslip2_value = 2'd0;
+reg [7:0] ddrphy_bitslip2_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d2 = 4'd0;
+wire ddrphy_dq_o3;
+wire ddrphy_dq_i3;
+wire ddrphy_dq_oe_n3;
+wire ddrphy_dq_i_delayed3;
+wire [7:0] ddrphy_dq_i_data3;
+reg [7:0] ddrphy_dq_o_data3 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d3 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed3 = 4'd0;
+wire [3:0] ddrphy_bitslip3_i;
+reg [3:0] ddrphy_bitslip3_o = 4'd0;
+reg [1:0] ddrphy_bitslip3_value = 2'd0;
+reg [7:0] ddrphy_bitslip3_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d3 = 4'd0;
+wire ddrphy_dq_o4;
+wire ddrphy_dq_i4;
+wire ddrphy_dq_oe_n4;
+wire ddrphy_dq_i_delayed4;
+wire [7:0] ddrphy_dq_i_data4;
+reg [7:0] ddrphy_dq_o_data4 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d4 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed4 = 4'd0;
+wire [3:0] ddrphy_bitslip4_i;
+reg [3:0] ddrphy_bitslip4_o = 4'd0;
+reg [1:0] ddrphy_bitslip4_value = 2'd0;
+reg [7:0] ddrphy_bitslip4_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d4 = 4'd0;
+wire ddrphy_dq_o5;
+wire ddrphy_dq_i5;
+wire ddrphy_dq_oe_n5;
+wire ddrphy_dq_i_delayed5;
+wire [7:0] ddrphy_dq_i_data5;
+reg [7:0] ddrphy_dq_o_data5 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d5 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed5 = 4'd0;
+wire [3:0] ddrphy_bitslip5_i;
+reg [3:0] ddrphy_bitslip5_o = 4'd0;
+reg [1:0] ddrphy_bitslip5_value = 2'd0;
+reg [7:0] ddrphy_bitslip5_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d5 = 4'd0;
+wire ddrphy_dq_o6;
+wire ddrphy_dq_i6;
+wire ddrphy_dq_oe_n6;
+wire ddrphy_dq_i_delayed6;
+wire [7:0] ddrphy_dq_i_data6;
+reg [7:0] ddrphy_dq_o_data6 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d6 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed6 = 4'd0;
+wire [3:0] ddrphy_bitslip6_i;
+reg [3:0] ddrphy_bitslip6_o = 4'd0;
+reg [1:0] ddrphy_bitslip6_value = 2'd0;
+reg [7:0] ddrphy_bitslip6_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d6 = 4'd0;
+wire ddrphy_dq_o7;
+wire ddrphy_dq_i7;
+wire ddrphy_dq_oe_n7;
+wire ddrphy_dq_i_delayed7;
+wire [7:0] ddrphy_dq_i_data7;
+reg [7:0] ddrphy_dq_o_data7 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d7 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed7 = 4'd0;
+wire [3:0] ddrphy_bitslip7_i;
+reg [3:0] ddrphy_bitslip7_o = 4'd0;
+reg [1:0] ddrphy_bitslip7_value = 2'd0;
+reg [7:0] ddrphy_bitslip7_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d7 = 4'd0;
+wire ddrphy_dqs_i1;
+wire ddrphy_dqsr901;
+wire ddrphy_dqsw2701;
+wire ddrphy_dqsw1;
+wire [2:0] ddrphy_rdpntr1;
+wire [2:0] ddrphy_wrpntr1;
+reg [2:0] ddrphy_rdly1 = 3'd0;
+wire ddrphy_burstdet1;
+reg ddrphy_burstdet_d1 = 1'd0;
+wire ddrphy_dqs1;
+wire ddrphy_dqs_oe_n1;
+reg [7:0] ddrphy_dm_o_data1 = 8'd0;
+reg [7:0] ddrphy_dm_o_data_d1 = 8'd0;
+reg [3:0] ddrphy_dm_o_data_muxed1 = 4'd0;
+wire ddrphy_dq_o8;
+wire ddrphy_dq_i8;
+wire ddrphy_dq_oe_n8;
+wire ddrphy_dq_i_delayed8;
+wire [7:0] ddrphy_dq_i_data8;
+reg [7:0] ddrphy_dq_o_data8 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d8 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed8 = 4'd0;
+wire [3:0] ddrphy_bitslip8_i;
+reg [3:0] ddrphy_bitslip8_o = 4'd0;
+reg [1:0] ddrphy_bitslip8_value = 2'd0;
+reg [7:0] ddrphy_bitslip8_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d8 = 4'd0;
+wire ddrphy_dq_o9;
+wire ddrphy_dq_i9;
+wire ddrphy_dq_oe_n9;
+wire ddrphy_dq_i_delayed9;
+wire [7:0] ddrphy_dq_i_data9;
+reg [7:0] ddrphy_dq_o_data9 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d9 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed9 = 4'd0;
+wire [3:0] ddrphy_bitslip9_i;
+reg [3:0] ddrphy_bitslip9_o = 4'd0;
+reg [1:0] ddrphy_bitslip9_value = 2'd0;
+reg [7:0] ddrphy_bitslip9_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d9 = 4'd0;
+wire ddrphy_dq_o10;
+wire ddrphy_dq_i10;
+wire ddrphy_dq_oe_n10;
+wire ddrphy_dq_i_delayed10;
+wire [7:0] ddrphy_dq_i_data10;
+reg [7:0] ddrphy_dq_o_data10 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d10 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed10 = 4'd0;
+wire [3:0] ddrphy_bitslip10_i;
+reg [3:0] ddrphy_bitslip10_o = 4'd0;
+reg [1:0] ddrphy_bitslip10_value = 2'd0;
+reg [7:0] ddrphy_bitslip10_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d10 = 4'd0;
+wire ddrphy_dq_o11;
+wire ddrphy_dq_i11;
+wire ddrphy_dq_oe_n11;
+wire ddrphy_dq_i_delayed11;
+wire [7:0] ddrphy_dq_i_data11;
+reg [7:0] ddrphy_dq_o_data11 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d11 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed11 = 4'd0;
+wire [3:0] ddrphy_bitslip11_i;
+reg [3:0] ddrphy_bitslip11_o = 4'd0;
+reg [1:0] ddrphy_bitslip11_value = 2'd0;
+reg [7:0] ddrphy_bitslip11_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d11 = 4'd0;
+wire ddrphy_dq_o12;
+wire ddrphy_dq_i12;
+wire ddrphy_dq_oe_n12;
+wire ddrphy_dq_i_delayed12;
+wire [7:0] ddrphy_dq_i_data12;
+reg [7:0] ddrphy_dq_o_data12 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d12 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed12 = 4'd0;
+wire [3:0] ddrphy_bitslip12_i;
+reg [3:0] ddrphy_bitslip12_o = 4'd0;
+reg [1:0] ddrphy_bitslip12_value = 2'd0;
+reg [7:0] ddrphy_bitslip12_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d12 = 4'd0;
+wire ddrphy_dq_o13;
+wire ddrphy_dq_i13;
+wire ddrphy_dq_oe_n13;
+wire ddrphy_dq_i_delayed13;
+wire [7:0] ddrphy_dq_i_data13;
+reg [7:0] ddrphy_dq_o_data13 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d13 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed13 = 4'd0;
+wire [3:0] ddrphy_bitslip13_i;
+reg [3:0] ddrphy_bitslip13_o = 4'd0;
+reg [1:0] ddrphy_bitslip13_value = 2'd0;
+reg [7:0] ddrphy_bitslip13_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d13 = 4'd0;
+wire ddrphy_dq_o14;
+wire ddrphy_dq_i14;
+wire ddrphy_dq_oe_n14;
+wire ddrphy_dq_i_delayed14;
+wire [7:0] ddrphy_dq_i_data14;
+reg [7:0] ddrphy_dq_o_data14 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d14 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed14 = 4'd0;
+wire [3:0] ddrphy_bitslip14_i;
+reg [3:0] ddrphy_bitslip14_o = 4'd0;
+reg [1:0] ddrphy_bitslip14_value = 2'd0;
+reg [7:0] ddrphy_bitslip14_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d14 = 4'd0;
+wire ddrphy_dq_o15;
+wire ddrphy_dq_i15;
+wire ddrphy_dq_oe_n15;
+wire ddrphy_dq_i_delayed15;
+wire [7:0] ddrphy_dq_i_data15;
+reg [7:0] ddrphy_dq_o_data15 = 8'd0;
+reg [7:0] ddrphy_dq_o_data_d15 = 8'd0;
+reg [3:0] ddrphy_dq_o_data_muxed15 = 4'd0;
+wire [3:0] ddrphy_bitslip15_i;
+reg [3:0] ddrphy_bitslip15_o = 4'd0;
+reg [1:0] ddrphy_bitslip15_value = 2'd0;
+reg [7:0] ddrphy_bitslip15_r = 8'd0;
+reg [3:0] ddrphy_dq_i_bitslip_o_d15 = 4'd0;
+reg ddrphy_rddata_en_tappeddelayline0 = 1'd0;
+reg ddrphy_rddata_en_tappeddelayline1 = 1'd0;
+reg ddrphy_rddata_en_tappeddelayline2 = 1'd0;
+reg ddrphy_rddata_en_tappeddelayline3 = 1'd0;
+reg ddrphy_rddata_en_tappeddelayline4 = 1'd0;
+reg ddrphy_rddata_en_tappeddelayline5 = 1'd0;
+reg ddrphy_rddata_en_tappeddelayline6 = 1'd0;
+reg ddrphy_rddata_en_tappeddelayline7 = 1'd0;
+reg ddrphy_rddata_en_tappeddelayline8 = 1'd0;
+reg ddrphy_rddata_en_tappeddelayline9 = 1'd0;
+reg ddrphy_rddata_en_tappeddelayline10 = 1'd0;
+reg ddrphy_rddata_en_tappeddelayline11 = 1'd0;
+reg ddrphy_rddata_en_tappeddelayline12 = 1'd0;
+reg ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
+reg ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
+reg ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
+reg ddrphy_wrdata_en_tappeddelayline3 = 1'd0;
+reg ddrphy_wrdata_en_tappeddelayline4 = 1'd0;
+reg ddrphy_wrdata_en_tappeddelayline5 = 1'd0;
+reg ddrphy_wrdata_en_tappeddelayline6 = 1'd0;
+wire [14:0] litedramcore_slave_p0_address;
+wire [2:0] litedramcore_slave_p0_bank;
+wire litedramcore_slave_p0_cas_n;
+wire litedramcore_slave_p0_cs_n;
+wire litedramcore_slave_p0_ras_n;
+wire litedramcore_slave_p0_we_n;
+wire litedramcore_slave_p0_cke;
+wire litedramcore_slave_p0_odt;
+wire litedramcore_slave_p0_reset_n;
+wire litedramcore_slave_p0_act_n;
+wire [63:0] litedramcore_slave_p0_wrdata;
+wire litedramcore_slave_p0_wrdata_en;
+wire [7:0] litedramcore_slave_p0_wrdata_mask;
+wire litedramcore_slave_p0_rddata_en;
+reg [63:0] litedramcore_slave_p0_rddata = 64'd0;
+reg litedramcore_slave_p0_rddata_valid = 1'd0;
+wire [14:0] litedramcore_slave_p1_address;
+wire [2:0] litedramcore_slave_p1_bank;
+wire litedramcore_slave_p1_cas_n;
+wire litedramcore_slave_p1_cs_n;
+wire litedramcore_slave_p1_ras_n;
+wire litedramcore_slave_p1_we_n;
+wire litedramcore_slave_p1_cke;
+wire litedramcore_slave_p1_odt;
+wire litedramcore_slave_p1_reset_n;
+wire litedramcore_slave_p1_act_n;
+wire [63:0] litedramcore_slave_p1_wrdata;
+wire litedramcore_slave_p1_wrdata_en;
+wire [7:0] litedramcore_slave_p1_wrdata_mask;
+wire litedramcore_slave_p1_rddata_en;
+reg [63:0] litedramcore_slave_p1_rddata = 64'd0;
+reg litedramcore_slave_p1_rddata_valid = 1'd0;
+reg [14:0] litedramcore_master_p0_address = 15'd0;
+reg [2:0] litedramcore_master_p0_bank = 3'd0;
+reg litedramcore_master_p0_cas_n = 1'd1;
+reg litedramcore_master_p0_cs_n = 1'd1;
+reg litedramcore_master_p0_ras_n = 1'd1;
+reg litedramcore_master_p0_we_n = 1'd1;
+reg litedramcore_master_p0_cke = 1'd0;
+reg litedramcore_master_p0_odt = 1'd0;
+reg litedramcore_master_p0_reset_n = 1'd0;
+reg litedramcore_master_p0_act_n = 1'd1;
+reg [63:0] litedramcore_master_p0_wrdata = 64'd0;
+reg litedramcore_master_p0_wrdata_en = 1'd0;
+reg [7:0] litedramcore_master_p0_wrdata_mask = 8'd0;
+reg litedramcore_master_p0_rddata_en = 1'd0;
+wire [63:0] litedramcore_master_p0_rddata;
+wire litedramcore_master_p0_rddata_valid;
+reg [14:0] litedramcore_master_p1_address = 15'd0;
+reg [2:0] litedramcore_master_p1_bank = 3'd0;
+reg litedramcore_master_p1_cas_n = 1'd1;
+reg litedramcore_master_p1_cs_n = 1'd1;
+reg litedramcore_master_p1_ras_n = 1'd1;
+reg litedramcore_master_p1_we_n = 1'd1;
+reg litedramcore_master_p1_cke = 1'd0;
+reg litedramcore_master_p1_odt = 1'd0;
+reg litedramcore_master_p1_reset_n = 1'd0;
+reg litedramcore_master_p1_act_n = 1'd1;
+reg [63:0] litedramcore_master_p1_wrdata = 64'd0;
+reg litedramcore_master_p1_wrdata_en = 1'd0;
+reg [7:0] litedramcore_master_p1_wrdata_mask = 8'd0;
+reg litedramcore_master_p1_rddata_en = 1'd0;
+wire [63:0] litedramcore_master_p1_rddata;
+wire litedramcore_master_p1_rddata_valid;
+wire [14:0] litedramcore_csr_dfi_p0_address;
+wire [2:0] litedramcore_csr_dfi_p0_bank;
+reg litedramcore_csr_dfi_p0_cas_n = 1'd1;
+reg litedramcore_csr_dfi_p0_cs_n = 1'd1;
+reg litedramcore_csr_dfi_p0_ras_n = 1'd1;
+reg litedramcore_csr_dfi_p0_we_n = 1'd1;
+wire litedramcore_csr_dfi_p0_cke;
+wire litedramcore_csr_dfi_p0_odt;
+wire litedramcore_csr_dfi_p0_reset_n;
+reg litedramcore_csr_dfi_p0_act_n = 1'd1;
+wire [63:0] litedramcore_csr_dfi_p0_wrdata;
+wire litedramcore_csr_dfi_p0_wrdata_en;
+wire [7:0] litedramcore_csr_dfi_p0_wrdata_mask;
+wire litedramcore_csr_dfi_p0_rddata_en;
+reg [63:0] litedramcore_csr_dfi_p0_rddata = 64'd0;
+reg litedramcore_csr_dfi_p0_rddata_valid = 1'd0;
+wire [14:0] litedramcore_csr_dfi_p1_address;
+wire [2:0] litedramcore_csr_dfi_p1_bank;
+reg litedramcore_csr_dfi_p1_cas_n = 1'd1;
+reg litedramcore_csr_dfi_p1_cs_n = 1'd1;
+reg litedramcore_csr_dfi_p1_ras_n = 1'd1;
+reg litedramcore_csr_dfi_p1_we_n = 1'd1;
+wire litedramcore_csr_dfi_p1_cke;
+wire litedramcore_csr_dfi_p1_odt;
+wire litedramcore_csr_dfi_p1_reset_n;
+reg litedramcore_csr_dfi_p1_act_n = 1'd1;
+wire [63:0] litedramcore_csr_dfi_p1_wrdata;
+wire litedramcore_csr_dfi_p1_wrdata_en;
+wire [7:0] litedramcore_csr_dfi_p1_wrdata_mask;
+wire litedramcore_csr_dfi_p1_rddata_en;
+reg [63:0] litedramcore_csr_dfi_p1_rddata = 64'd0;
+reg litedramcore_csr_dfi_p1_rddata_valid = 1'd0;
+reg [14:0] litedramcore_ext_dfi_p0_address = 15'd0;
+reg [2:0] litedramcore_ext_dfi_p0_bank = 3'd0;
+reg litedramcore_ext_dfi_p0_cas_n = 1'd1;
+reg litedramcore_ext_dfi_p0_cs_n = 1'd1;
+reg litedramcore_ext_dfi_p0_ras_n = 1'd1;
+reg litedramcore_ext_dfi_p0_we_n = 1'd1;
+reg litedramcore_ext_dfi_p0_cke = 1'd0;
+reg litedramcore_ext_dfi_p0_odt = 1'd0;
+reg litedramcore_ext_dfi_p0_reset_n = 1'd0;
+reg litedramcore_ext_dfi_p0_act_n = 1'd1;
+reg [63:0] litedramcore_ext_dfi_p0_wrdata = 64'd0;
+reg litedramcore_ext_dfi_p0_wrdata_en = 1'd0;
+reg [7:0] litedramcore_ext_dfi_p0_wrdata_mask = 8'd0;
+reg litedramcore_ext_dfi_p0_rddata_en = 1'd0;
+reg [63:0] litedramcore_ext_dfi_p0_rddata = 64'd0;
+reg litedramcore_ext_dfi_p0_rddata_valid = 1'd0;
+reg [14:0] litedramcore_ext_dfi_p1_address = 15'd0;
+reg [2:0] litedramcore_ext_dfi_p1_bank = 3'd0;
+reg litedramcore_ext_dfi_p1_cas_n = 1'd1;
+reg litedramcore_ext_dfi_p1_cs_n = 1'd1;
+reg litedramcore_ext_dfi_p1_ras_n = 1'd1;
+reg litedramcore_ext_dfi_p1_we_n = 1'd1;
+reg litedramcore_ext_dfi_p1_cke = 1'd0;
+reg litedramcore_ext_dfi_p1_odt = 1'd0;
+reg litedramcore_ext_dfi_p1_reset_n = 1'd0;
+reg litedramcore_ext_dfi_p1_act_n = 1'd1;
+reg [63:0] litedramcore_ext_dfi_p1_wrdata = 64'd0;
+reg litedramcore_ext_dfi_p1_wrdata_en = 1'd0;
+reg [7:0] litedramcore_ext_dfi_p1_wrdata_mask = 8'd0;
+reg litedramcore_ext_dfi_p1_rddata_en = 1'd0;
+reg [63:0] litedramcore_ext_dfi_p1_rddata = 64'd0;
+reg litedramcore_ext_dfi_p1_rddata_valid = 1'd0;
+reg litedramcore_ext_dfi_sel = 1'd0;
+wire litedramcore_sel;
+wire litedramcore_cke;
+wire litedramcore_odt;
+wire litedramcore_reset_n;
+reg [3:0] litedramcore_storage = 4'd1;
+reg litedramcore_re = 1'd0;
+wire litedramcore_phaseinjector0_csrfield_cs;
+wire litedramcore_phaseinjector0_csrfield_we;
+wire litedramcore_phaseinjector0_csrfield_cas;
+wire litedramcore_phaseinjector0_csrfield_ras;
+wire litedramcore_phaseinjector0_csrfield_wren;
+wire litedramcore_phaseinjector0_csrfield_rden;
+reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0;
+reg litedramcore_phaseinjector0_command_re = 1'd0;
+reg litedramcore_phaseinjector0_command_issue_re = 1'd0;
+wire litedramcore_phaseinjector0_command_issue_r;
+reg litedramcore_phaseinjector0_command_issue_we = 1'd0;
+reg litedramcore_phaseinjector0_command_issue_w = 1'd0;
+reg [14:0] litedramcore_phaseinjector0_address_storage = 15'd0;
+reg litedramcore_phaseinjector0_address_re = 1'd0;
+reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0;
+reg litedramcore_phaseinjector0_baddress_re = 1'd0;
+reg [63:0] litedramcore_phaseinjector0_wrdata_storage = 64'd0;
+reg litedramcore_phaseinjector0_wrdata_re = 1'd0;
+reg [63:0] litedramcore_phaseinjector0_rddata_status = 64'd0;
+wire litedramcore_phaseinjector0_rddata_we;
+reg litedramcore_phaseinjector0_rddata_re = 1'd0;
+wire litedramcore_phaseinjector1_csrfield_cs;
+wire litedramcore_phaseinjector1_csrfield_we;
+wire litedramcore_phaseinjector1_csrfield_cas;
+wire litedramcore_phaseinjector1_csrfield_ras;
+wire litedramcore_phaseinjector1_csrfield_wren;
+wire litedramcore_phaseinjector1_csrfield_rden;
+reg [5:0] litedramcore_phaseinjector1_command_storage = 6'd0;
+reg litedramcore_phaseinjector1_command_re = 1'd0;
+reg litedramcore_phaseinjector1_command_issue_re = 1'd0;
+wire litedramcore_phaseinjector1_command_issue_r;
+reg litedramcore_phaseinjector1_command_issue_we = 1'd0;
+reg litedramcore_phaseinjector1_command_issue_w = 1'd0;
+reg [14:0] litedramcore_phaseinjector1_address_storage = 15'd0;
+reg litedramcore_phaseinjector1_address_re = 1'd0;
+reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0;
+reg litedramcore_phaseinjector1_baddress_re = 1'd0;
+reg [63:0] litedramcore_phaseinjector1_wrdata_storage = 64'd0;
+reg litedramcore_phaseinjector1_wrdata_re = 1'd0;
+reg [63:0] litedramcore_phaseinjector1_rddata_status = 64'd0;
+wire litedramcore_phaseinjector1_rddata_we;
+reg litedramcore_phaseinjector1_rddata_re = 1'd0;
+wire litedramcore_interface_bank0_valid;
+wire litedramcore_interface_bank0_ready;
+wire litedramcore_interface_bank0_we;
+wire [21:0] litedramcore_interface_bank0_addr;
+wire litedramcore_interface_bank0_lock;
+wire litedramcore_interface_bank0_wdata_ready;
+wire litedramcore_interface_bank0_rdata_valid;
+wire litedramcore_interface_bank1_valid;
+wire litedramcore_interface_bank1_ready;
+wire litedramcore_interface_bank1_we;
+wire [21:0] litedramcore_interface_bank1_addr;
+wire litedramcore_interface_bank1_lock;
+wire litedramcore_interface_bank1_wdata_ready;
+wire litedramcore_interface_bank1_rdata_valid;
+wire litedramcore_interface_bank2_valid;
+wire litedramcore_interface_bank2_ready;
+wire litedramcore_interface_bank2_we;
+wire [21:0] litedramcore_interface_bank2_addr;
+wire litedramcore_interface_bank2_lock;
+wire litedramcore_interface_bank2_wdata_ready;
+wire litedramcore_interface_bank2_rdata_valid;
+wire litedramcore_interface_bank3_valid;
+wire litedramcore_interface_bank3_ready;
+wire litedramcore_interface_bank3_we;
+wire [21:0] litedramcore_interface_bank3_addr;
+wire litedramcore_interface_bank3_lock;
+wire litedramcore_interface_bank3_wdata_ready;
+wire litedramcore_interface_bank3_rdata_valid;
+wire litedramcore_interface_bank4_valid;
+wire litedramcore_interface_bank4_ready;
+wire litedramcore_interface_bank4_we;
+wire [21:0] litedramcore_interface_bank4_addr;
+wire litedramcore_interface_bank4_lock;
+wire litedramcore_interface_bank4_wdata_ready;
+wire litedramcore_interface_bank4_rdata_valid;
+wire litedramcore_interface_bank5_valid;
+wire litedramcore_interface_bank5_ready;
+wire litedramcore_interface_bank5_we;
+wire [21:0] litedramcore_interface_bank5_addr;
+wire litedramcore_interface_bank5_lock;
+wire litedramcore_interface_bank5_wdata_ready;
+wire litedramcore_interface_bank5_rdata_valid;
+wire litedramcore_interface_bank6_valid;
+wire litedramcore_interface_bank6_ready;
+wire litedramcore_interface_bank6_we;
+wire [21:0] litedramcore_interface_bank6_addr;
+wire litedramcore_interface_bank6_lock;
+wire litedramcore_interface_bank6_wdata_ready;
+wire litedramcore_interface_bank6_rdata_valid;
+wire litedramcore_interface_bank7_valid;
+wire litedramcore_interface_bank7_ready;
+wire litedramcore_interface_bank7_we;
+wire [21:0] litedramcore_interface_bank7_addr;
+wire litedramcore_interface_bank7_lock;
+wire litedramcore_interface_bank7_wdata_ready;
+wire litedramcore_interface_bank7_rdata_valid;
+reg [127:0] litedramcore_interface_wdata = 128'd0;
+reg [15:0] litedramcore_interface_wdata_we = 16'd0;
+wire [127:0] litedramcore_interface_rdata;
+reg [14:0] litedramcore_dfi_p0_address = 15'd0;
+reg [2:0] litedramcore_dfi_p0_bank = 3'd0;
+reg litedramcore_dfi_p0_cas_n = 1'd1;
+reg litedramcore_dfi_p0_cs_n = 1'd1;
+reg litedramcore_dfi_p0_ras_n = 1'd1;
+reg litedramcore_dfi_p0_we_n = 1'd1;
+wire litedramcore_dfi_p0_cke;
+wire litedramcore_dfi_p0_odt;
+wire litedramcore_dfi_p0_reset_n;
+reg litedramcore_dfi_p0_act_n = 1'd1;
+wire [63:0] litedramcore_dfi_p0_wrdata;
+reg litedramcore_dfi_p0_wrdata_en = 1'd0;
+wire [7:0] litedramcore_dfi_p0_wrdata_mask;
+reg litedramcore_dfi_p0_rddata_en = 1'd0;
+wire [63:0] litedramcore_dfi_p0_rddata;
+wire litedramcore_dfi_p0_rddata_valid;
+reg [14:0] litedramcore_dfi_p1_address = 15'd0;
+reg [2:0] litedramcore_dfi_p1_bank = 3'd0;
+reg litedramcore_dfi_p1_cas_n = 1'd1;
+reg litedramcore_dfi_p1_cs_n = 1'd1;
+reg litedramcore_dfi_p1_ras_n = 1'd1;
+reg litedramcore_dfi_p1_we_n = 1'd1;
+wire litedramcore_dfi_p1_cke;
+wire litedramcore_dfi_p1_odt;
+wire litedramcore_dfi_p1_reset_n;
+reg litedramcore_dfi_p1_act_n = 1'd1;
+wire [63:0] litedramcore_dfi_p1_wrdata;
+reg litedramcore_dfi_p1_wrdata_en = 1'd0;
+wire [7:0] litedramcore_dfi_p1_wrdata_mask;
+reg litedramcore_dfi_p1_rddata_en = 1'd0;
+wire [63:0] litedramcore_dfi_p1_rddata;
+wire litedramcore_dfi_p1_rddata_valid;
+reg litedramcore_cmd_valid = 1'd0;
+reg litedramcore_cmd_ready = 1'd0;
+reg litedramcore_cmd_last = 1'd0;
+reg [14:0] litedramcore_cmd_payload_a = 15'd0;
+reg [2:0] litedramcore_cmd_payload_ba = 3'd0;
+reg litedramcore_cmd_payload_cas = 1'd0;
+reg litedramcore_cmd_payload_ras = 1'd0;
+reg litedramcore_cmd_payload_we = 1'd0;
+reg litedramcore_cmd_payload_is_read = 1'd0;
+reg litedramcore_cmd_payload_is_write = 1'd0;
+wire litedramcore_wants_refresh;
+wire litedramcore_wants_zqcs;
+wire litedramcore_timer_wait;
+wire litedramcore_timer_done0;
+wire [8:0] litedramcore_timer_count0;
+wire litedramcore_timer_done1;
+reg [8:0] litedramcore_timer_count1 = 9'd374;
+wire litedramcore_postponer_req_i;
+reg litedramcore_postponer_req_o = 1'd0;
+reg litedramcore_postponer_count = 1'd0;
+reg litedramcore_sequencer_start0 = 1'd0;
+wire litedramcore_sequencer_done0;
+wire litedramcore_sequencer_start1;
+reg litedramcore_sequencer_done1 = 1'd0;
+reg [6:0] litedramcore_sequencer_counter = 7'd0;
+reg litedramcore_sequencer_count = 1'd0;
+wire litedramcore_zqcs_timer_wait;
+wire litedramcore_zqcs_timer_done0;
+wire [25:0] litedramcore_zqcs_timer_count0;
+wire litedramcore_zqcs_timer_done1;
+reg [25:0] litedramcore_zqcs_timer_count1 = 26'd47999999;
+reg litedramcore_zqcs_executer_start = 1'd0;
+reg litedramcore_zqcs_executer_done = 1'd0;
+reg [5:0] litedramcore_zqcs_executer_counter = 6'd0;
+wire litedramcore_bankmachine0_req_valid;
+wire litedramcore_bankmachine0_req_ready;
+wire litedramcore_bankmachine0_req_we;
+wire [21:0] litedramcore_bankmachine0_req_addr;
+wire litedramcore_bankmachine0_req_lock;
+reg litedramcore_bankmachine0_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine0_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine0_refresh_req;
+reg litedramcore_bankmachine0_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine0_cmd_valid = 1'd0;
+reg litedramcore_bankmachine0_cmd_ready = 1'd0;
+reg [14:0] litedramcore_bankmachine0_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine0_cmd_payload_ba;
+reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine0_auto_precharge = 1'd0;
+wire litedramcore_bankmachine0_sink_valid;
+wire litedramcore_bankmachine0_sink_ready;
+reg litedramcore_bankmachine0_sink_first = 1'd0;
+reg litedramcore_bankmachine0_sink_last = 1'd0;
+wire litedramcore_bankmachine0_sink_payload_we;
+wire [21:0] litedramcore_bankmachine0_sink_payload_addr;
+wire litedramcore_bankmachine0_source_valid;
+wire litedramcore_bankmachine0_source_ready;
+wire litedramcore_bankmachine0_source_first;
+wire litedramcore_bankmachine0_source_last;
+wire litedramcore_bankmachine0_source_payload_we;
+wire [21:0] litedramcore_bankmachine0_source_payload_addr;
+wire litedramcore_bankmachine0_syncfifo0_we;
+wire litedramcore_bankmachine0_syncfifo0_writable;
+wire litedramcore_bankmachine0_syncfifo0_re;
+wire litedramcore_bankmachine0_syncfifo0_readable;
+wire [24:0] litedramcore_bankmachine0_syncfifo0_din;
+wire [24:0] litedramcore_bankmachine0_syncfifo0_dout;
+reg [4:0] litedramcore_bankmachine0_level = 5'd0;
+reg litedramcore_bankmachine0_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine0_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine0_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine0_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine0_wrport_dat_r;
+wire litedramcore_bankmachine0_wrport_we;
+wire [24:0] litedramcore_bankmachine0_wrport_dat_w;
+wire litedramcore_bankmachine0_do_read;
+wire [3:0] litedramcore_bankmachine0_rdport_adr;
+wire [24:0] litedramcore_bankmachine0_rdport_dat_r;
+wire litedramcore_bankmachine0_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine0_fifo_in_payload_addr;
+wire litedramcore_bankmachine0_fifo_in_first;
+wire litedramcore_bankmachine0_fifo_in_last;
+wire litedramcore_bankmachine0_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine0_fifo_out_payload_addr;
+wire litedramcore_bankmachine0_fifo_out_first;
+wire litedramcore_bankmachine0_fifo_out_last;
+wire litedramcore_bankmachine0_sink_sink_valid;
+wire litedramcore_bankmachine0_sink_sink_ready;
+wire litedramcore_bankmachine0_sink_sink_first;
+wire litedramcore_bankmachine0_sink_sink_last;
+wire litedramcore_bankmachine0_sink_sink_payload_we;
+wire [21:0] litedramcore_bankmachine0_sink_sink_payload_addr;
+wire litedramcore_bankmachine0_source_source_valid;
+wire litedramcore_bankmachine0_source_source_ready;
+wire litedramcore_bankmachine0_source_source_first;
+wire litedramcore_bankmachine0_source_source_last;
+wire litedramcore_bankmachine0_source_source_payload_we;
+wire [21:0] litedramcore_bankmachine0_source_source_payload_addr;
+wire litedramcore_bankmachine0_pipe_valid_sink_valid;
+wire litedramcore_bankmachine0_pipe_valid_sink_ready;
+wire litedramcore_bankmachine0_pipe_valid_sink_first;
+wire litedramcore_bankmachine0_pipe_valid_sink_last;
+wire litedramcore_bankmachine0_pipe_valid_sink_payload_we;
+wire [21:0] litedramcore_bankmachine0_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine0_pipe_valid_source_ready;
+reg litedramcore_bankmachine0_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine0_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0;
+reg [21:0] litedramcore_bankmachine0_pipe_valid_source_payload_addr = 22'd0;
+reg [14:0] litedramcore_bankmachine0_row = 15'd0;
+reg litedramcore_bankmachine0_row_opened = 1'd0;
+wire litedramcore_bankmachine0_row_hit;
+reg litedramcore_bankmachine0_row_open = 1'd0;
+reg litedramcore_bankmachine0_row_close = 1'd0;
+reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine0_twtpcon_valid;
+reg litedramcore_bankmachine0_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine0_trccon_valid;
+reg litedramcore_bankmachine0_trccon_ready = 1'd0;
+reg [1:0] litedramcore_bankmachine0_trccon_count = 2'd0;
+wire litedramcore_bankmachine0_trascon_valid;
+reg litedramcore_bankmachine0_trascon_ready = 1'd0;
+reg [1:0] litedramcore_bankmachine0_trascon_count = 2'd0;
+wire litedramcore_bankmachine1_req_valid;
+wire litedramcore_bankmachine1_req_ready;
+wire litedramcore_bankmachine1_req_we;
+wire [21:0] litedramcore_bankmachine1_req_addr;
+wire litedramcore_bankmachine1_req_lock;
+reg litedramcore_bankmachine1_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine1_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine1_refresh_req;
+reg litedramcore_bankmachine1_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine1_cmd_valid = 1'd0;
+reg litedramcore_bankmachine1_cmd_ready = 1'd0;
+reg [14:0] litedramcore_bankmachine1_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine1_cmd_payload_ba;
+reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine1_auto_precharge = 1'd0;
+wire litedramcore_bankmachine1_sink_valid;
+wire litedramcore_bankmachine1_sink_ready;
+reg litedramcore_bankmachine1_sink_first = 1'd0;
+reg litedramcore_bankmachine1_sink_last = 1'd0;
+wire litedramcore_bankmachine1_sink_payload_we;
+wire [21:0] litedramcore_bankmachine1_sink_payload_addr;
+wire litedramcore_bankmachine1_source_valid;
+wire litedramcore_bankmachine1_source_ready;
+wire litedramcore_bankmachine1_source_first;
+wire litedramcore_bankmachine1_source_last;
+wire litedramcore_bankmachine1_source_payload_we;
+wire [21:0] litedramcore_bankmachine1_source_payload_addr;
+wire litedramcore_bankmachine1_syncfifo1_we;
+wire litedramcore_bankmachine1_syncfifo1_writable;
+wire litedramcore_bankmachine1_syncfifo1_re;
+wire litedramcore_bankmachine1_syncfifo1_readable;
+wire [24:0] litedramcore_bankmachine1_syncfifo1_din;
+wire [24:0] litedramcore_bankmachine1_syncfifo1_dout;
+reg [4:0] litedramcore_bankmachine1_level = 5'd0;
+reg litedramcore_bankmachine1_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine1_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine1_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine1_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine1_wrport_dat_r;
+wire litedramcore_bankmachine1_wrport_we;
+wire [24:0] litedramcore_bankmachine1_wrport_dat_w;
+wire litedramcore_bankmachine1_do_read;
+wire [3:0] litedramcore_bankmachine1_rdport_adr;
+wire [24:0] litedramcore_bankmachine1_rdport_dat_r;
+wire litedramcore_bankmachine1_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine1_fifo_in_payload_addr;
+wire litedramcore_bankmachine1_fifo_in_first;
+wire litedramcore_bankmachine1_fifo_in_last;
+wire litedramcore_bankmachine1_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine1_fifo_out_payload_addr;
+wire litedramcore_bankmachine1_fifo_out_first;
+wire litedramcore_bankmachine1_fifo_out_last;
+wire litedramcore_bankmachine1_sink_sink_valid;
+wire litedramcore_bankmachine1_sink_sink_ready;
+wire litedramcore_bankmachine1_sink_sink_first;
+wire litedramcore_bankmachine1_sink_sink_last;
+wire litedramcore_bankmachine1_sink_sink_payload_we;
+wire [21:0] litedramcore_bankmachine1_sink_sink_payload_addr;
+wire litedramcore_bankmachine1_source_source_valid;
+wire litedramcore_bankmachine1_source_source_ready;
+wire litedramcore_bankmachine1_source_source_first;
+wire litedramcore_bankmachine1_source_source_last;
+wire litedramcore_bankmachine1_source_source_payload_we;
+wire [21:0] litedramcore_bankmachine1_source_source_payload_addr;
+wire litedramcore_bankmachine1_pipe_valid_sink_valid;
+wire litedramcore_bankmachine1_pipe_valid_sink_ready;
+wire litedramcore_bankmachine1_pipe_valid_sink_first;
+wire litedramcore_bankmachine1_pipe_valid_sink_last;
+wire litedramcore_bankmachine1_pipe_valid_sink_payload_we;
+wire [21:0] litedramcore_bankmachine1_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine1_pipe_valid_source_ready;
+reg litedramcore_bankmachine1_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine1_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0;
+reg [21:0] litedramcore_bankmachine1_pipe_valid_source_payload_addr = 22'd0;
+reg [14:0] litedramcore_bankmachine1_row = 15'd0;
+reg litedramcore_bankmachine1_row_opened = 1'd0;
+wire litedramcore_bankmachine1_row_hit;
+reg litedramcore_bankmachine1_row_open = 1'd0;
+reg litedramcore_bankmachine1_row_close = 1'd0;
+reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine1_twtpcon_valid;
+reg litedramcore_bankmachine1_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine1_trccon_valid;
+reg litedramcore_bankmachine1_trccon_ready = 1'd0;
+reg [1:0] litedramcore_bankmachine1_trccon_count = 2'd0;
+wire litedramcore_bankmachine1_trascon_valid;
+reg litedramcore_bankmachine1_trascon_ready = 1'd0;
+reg [1:0] litedramcore_bankmachine1_trascon_count = 2'd0;
+wire litedramcore_bankmachine2_req_valid;
+wire litedramcore_bankmachine2_req_ready;
+wire litedramcore_bankmachine2_req_we;
+wire [21:0] litedramcore_bankmachine2_req_addr;
+wire litedramcore_bankmachine2_req_lock;
+reg litedramcore_bankmachine2_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine2_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine2_refresh_req;
+reg litedramcore_bankmachine2_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine2_cmd_valid = 1'd0;
+reg litedramcore_bankmachine2_cmd_ready = 1'd0;
+reg [14:0] litedramcore_bankmachine2_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine2_cmd_payload_ba;
+reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine2_auto_precharge = 1'd0;
+wire litedramcore_bankmachine2_sink_valid;
+wire litedramcore_bankmachine2_sink_ready;
+reg litedramcore_bankmachine2_sink_first = 1'd0;
+reg litedramcore_bankmachine2_sink_last = 1'd0;
+wire litedramcore_bankmachine2_sink_payload_we;
+wire [21:0] litedramcore_bankmachine2_sink_payload_addr;
+wire litedramcore_bankmachine2_source_valid;
+wire litedramcore_bankmachine2_source_ready;
+wire litedramcore_bankmachine2_source_first;
+wire litedramcore_bankmachine2_source_last;
+wire litedramcore_bankmachine2_source_payload_we;
+wire [21:0] litedramcore_bankmachine2_source_payload_addr;
+wire litedramcore_bankmachine2_syncfifo2_we;
+wire litedramcore_bankmachine2_syncfifo2_writable;
+wire litedramcore_bankmachine2_syncfifo2_re;
+wire litedramcore_bankmachine2_syncfifo2_readable;
+wire [24:0] litedramcore_bankmachine2_syncfifo2_din;
+wire [24:0] litedramcore_bankmachine2_syncfifo2_dout;
+reg [4:0] litedramcore_bankmachine2_level = 5'd0;
+reg litedramcore_bankmachine2_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine2_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine2_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine2_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine2_wrport_dat_r;
+wire litedramcore_bankmachine2_wrport_we;
+wire [24:0] litedramcore_bankmachine2_wrport_dat_w;
+wire litedramcore_bankmachine2_do_read;
+wire [3:0] litedramcore_bankmachine2_rdport_adr;
+wire [24:0] litedramcore_bankmachine2_rdport_dat_r;
+wire litedramcore_bankmachine2_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine2_fifo_in_payload_addr;
+wire litedramcore_bankmachine2_fifo_in_first;
+wire litedramcore_bankmachine2_fifo_in_last;
+wire litedramcore_bankmachine2_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine2_fifo_out_payload_addr;
+wire litedramcore_bankmachine2_fifo_out_first;
+wire litedramcore_bankmachine2_fifo_out_last;
+wire litedramcore_bankmachine2_sink_sink_valid;
+wire litedramcore_bankmachine2_sink_sink_ready;
+wire litedramcore_bankmachine2_sink_sink_first;
+wire litedramcore_bankmachine2_sink_sink_last;
+wire litedramcore_bankmachine2_sink_sink_payload_we;
+wire [21:0] litedramcore_bankmachine2_sink_sink_payload_addr;
+wire litedramcore_bankmachine2_source_source_valid;
+wire litedramcore_bankmachine2_source_source_ready;
+wire litedramcore_bankmachine2_source_source_first;
+wire litedramcore_bankmachine2_source_source_last;
+wire litedramcore_bankmachine2_source_source_payload_we;
+wire [21:0] litedramcore_bankmachine2_source_source_payload_addr;
+wire litedramcore_bankmachine2_pipe_valid_sink_valid;
+wire litedramcore_bankmachine2_pipe_valid_sink_ready;
+wire litedramcore_bankmachine2_pipe_valid_sink_first;
+wire litedramcore_bankmachine2_pipe_valid_sink_last;
+wire litedramcore_bankmachine2_pipe_valid_sink_payload_we;
+wire [21:0] litedramcore_bankmachine2_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine2_pipe_valid_source_ready;
+reg litedramcore_bankmachine2_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine2_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0;
+reg [21:0] litedramcore_bankmachine2_pipe_valid_source_payload_addr = 22'd0;
+reg [14:0] litedramcore_bankmachine2_row = 15'd0;
+reg litedramcore_bankmachine2_row_opened = 1'd0;
+wire litedramcore_bankmachine2_row_hit;
+reg litedramcore_bankmachine2_row_open = 1'd0;
+reg litedramcore_bankmachine2_row_close = 1'd0;
+reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine2_twtpcon_valid;
+reg litedramcore_bankmachine2_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine2_trccon_valid;
+reg litedramcore_bankmachine2_trccon_ready = 1'd0;
+reg [1:0] litedramcore_bankmachine2_trccon_count = 2'd0;
+wire litedramcore_bankmachine2_trascon_valid;
+reg litedramcore_bankmachine2_trascon_ready = 1'd0;
+reg [1:0] litedramcore_bankmachine2_trascon_count = 2'd0;
+wire litedramcore_bankmachine3_req_valid;
+wire litedramcore_bankmachine3_req_ready;
+wire litedramcore_bankmachine3_req_we;
+wire [21:0] litedramcore_bankmachine3_req_addr;
+wire litedramcore_bankmachine3_req_lock;
+reg litedramcore_bankmachine3_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine3_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine3_refresh_req;
+reg litedramcore_bankmachine3_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine3_cmd_valid = 1'd0;
+reg litedramcore_bankmachine3_cmd_ready = 1'd0;
+reg [14:0] litedramcore_bankmachine3_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine3_cmd_payload_ba;
+reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine3_auto_precharge = 1'd0;
+wire litedramcore_bankmachine3_sink_valid;
+wire litedramcore_bankmachine3_sink_ready;
+reg litedramcore_bankmachine3_sink_first = 1'd0;
+reg litedramcore_bankmachine3_sink_last = 1'd0;
+wire litedramcore_bankmachine3_sink_payload_we;
+wire [21:0] litedramcore_bankmachine3_sink_payload_addr;
+wire litedramcore_bankmachine3_source_valid;
+wire litedramcore_bankmachine3_source_ready;
+wire litedramcore_bankmachine3_source_first;
+wire litedramcore_bankmachine3_source_last;
+wire litedramcore_bankmachine3_source_payload_we;
+wire [21:0] litedramcore_bankmachine3_source_payload_addr;
+wire litedramcore_bankmachine3_syncfifo3_we;
+wire litedramcore_bankmachine3_syncfifo3_writable;
+wire litedramcore_bankmachine3_syncfifo3_re;
+wire litedramcore_bankmachine3_syncfifo3_readable;
+wire [24:0] litedramcore_bankmachine3_syncfifo3_din;
+wire [24:0] litedramcore_bankmachine3_syncfifo3_dout;
+reg [4:0] litedramcore_bankmachine3_level = 5'd0;
+reg litedramcore_bankmachine3_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine3_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine3_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine3_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine3_wrport_dat_r;
+wire litedramcore_bankmachine3_wrport_we;
+wire [24:0] litedramcore_bankmachine3_wrport_dat_w;
+wire litedramcore_bankmachine3_do_read;
+wire [3:0] litedramcore_bankmachine3_rdport_adr;
+wire [24:0] litedramcore_bankmachine3_rdport_dat_r;
+wire litedramcore_bankmachine3_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine3_fifo_in_payload_addr;
+wire litedramcore_bankmachine3_fifo_in_first;
+wire litedramcore_bankmachine3_fifo_in_last;
+wire litedramcore_bankmachine3_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine3_fifo_out_payload_addr;
+wire litedramcore_bankmachine3_fifo_out_first;
+wire litedramcore_bankmachine3_fifo_out_last;
+wire litedramcore_bankmachine3_sink_sink_valid;
+wire litedramcore_bankmachine3_sink_sink_ready;
+wire litedramcore_bankmachine3_sink_sink_first;
+wire litedramcore_bankmachine3_sink_sink_last;
+wire litedramcore_bankmachine3_sink_sink_payload_we;
+wire [21:0] litedramcore_bankmachine3_sink_sink_payload_addr;
+wire litedramcore_bankmachine3_source_source_valid;
+wire litedramcore_bankmachine3_source_source_ready;
+wire litedramcore_bankmachine3_source_source_first;
+wire litedramcore_bankmachine3_source_source_last;
+wire litedramcore_bankmachine3_source_source_payload_we;
+wire [21:0] litedramcore_bankmachine3_source_source_payload_addr;
+wire litedramcore_bankmachine3_pipe_valid_sink_valid;
+wire litedramcore_bankmachine3_pipe_valid_sink_ready;
+wire litedramcore_bankmachine3_pipe_valid_sink_first;
+wire litedramcore_bankmachine3_pipe_valid_sink_last;
+wire litedramcore_bankmachine3_pipe_valid_sink_payload_we;
+wire [21:0] litedramcore_bankmachine3_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine3_pipe_valid_source_ready;
+reg litedramcore_bankmachine3_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine3_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0;
+reg [21:0] litedramcore_bankmachine3_pipe_valid_source_payload_addr = 22'd0;
+reg [14:0] litedramcore_bankmachine3_row = 15'd0;
+reg litedramcore_bankmachine3_row_opened = 1'd0;
+wire litedramcore_bankmachine3_row_hit;
+reg litedramcore_bankmachine3_row_open = 1'd0;
+reg litedramcore_bankmachine3_row_close = 1'd0;
+reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine3_twtpcon_valid;
+reg litedramcore_bankmachine3_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine3_trccon_valid;
+reg litedramcore_bankmachine3_trccon_ready = 1'd0;
+reg [1:0] litedramcore_bankmachine3_trccon_count = 2'd0;
+wire litedramcore_bankmachine3_trascon_valid;
+reg litedramcore_bankmachine3_trascon_ready = 1'd0;
+reg [1:0] litedramcore_bankmachine3_trascon_count = 2'd0;
+wire litedramcore_bankmachine4_req_valid;
+wire litedramcore_bankmachine4_req_ready;
+wire litedramcore_bankmachine4_req_we;
+wire [21:0] litedramcore_bankmachine4_req_addr;
+wire litedramcore_bankmachine4_req_lock;
+reg litedramcore_bankmachine4_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine4_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine4_refresh_req;
+reg litedramcore_bankmachine4_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine4_cmd_valid = 1'd0;
+reg litedramcore_bankmachine4_cmd_ready = 1'd0;
+reg [14:0] litedramcore_bankmachine4_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine4_cmd_payload_ba;
+reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine4_auto_precharge = 1'd0;
+wire litedramcore_bankmachine4_sink_valid;
+wire litedramcore_bankmachine4_sink_ready;
+reg litedramcore_bankmachine4_sink_first = 1'd0;
+reg litedramcore_bankmachine4_sink_last = 1'd0;
+wire litedramcore_bankmachine4_sink_payload_we;
+wire [21:0] litedramcore_bankmachine4_sink_payload_addr;
+wire litedramcore_bankmachine4_source_valid;
+wire litedramcore_bankmachine4_source_ready;
+wire litedramcore_bankmachine4_source_first;
+wire litedramcore_bankmachine4_source_last;
+wire litedramcore_bankmachine4_source_payload_we;
+wire [21:0] litedramcore_bankmachine4_source_payload_addr;
+wire litedramcore_bankmachine4_syncfifo4_we;
+wire litedramcore_bankmachine4_syncfifo4_writable;
+wire litedramcore_bankmachine4_syncfifo4_re;
+wire litedramcore_bankmachine4_syncfifo4_readable;
+wire [24:0] litedramcore_bankmachine4_syncfifo4_din;
+wire [24:0] litedramcore_bankmachine4_syncfifo4_dout;
+reg [4:0] litedramcore_bankmachine4_level = 5'd0;
+reg litedramcore_bankmachine4_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine4_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine4_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine4_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine4_wrport_dat_r;
+wire litedramcore_bankmachine4_wrport_we;
+wire [24:0] litedramcore_bankmachine4_wrport_dat_w;
+wire litedramcore_bankmachine4_do_read;
+wire [3:0] litedramcore_bankmachine4_rdport_adr;
+wire [24:0] litedramcore_bankmachine4_rdport_dat_r;
+wire litedramcore_bankmachine4_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine4_fifo_in_payload_addr;
+wire litedramcore_bankmachine4_fifo_in_first;
+wire litedramcore_bankmachine4_fifo_in_last;
+wire litedramcore_bankmachine4_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine4_fifo_out_payload_addr;
+wire litedramcore_bankmachine4_fifo_out_first;
+wire litedramcore_bankmachine4_fifo_out_last;
+wire litedramcore_bankmachine4_sink_sink_valid;
+wire litedramcore_bankmachine4_sink_sink_ready;
+wire litedramcore_bankmachine4_sink_sink_first;
+wire litedramcore_bankmachine4_sink_sink_last;
+wire litedramcore_bankmachine4_sink_sink_payload_we;
+wire [21:0] litedramcore_bankmachine4_sink_sink_payload_addr;
+wire litedramcore_bankmachine4_source_source_valid;
+wire litedramcore_bankmachine4_source_source_ready;
+wire litedramcore_bankmachine4_source_source_first;
+wire litedramcore_bankmachine4_source_source_last;
+wire litedramcore_bankmachine4_source_source_payload_we;
+wire [21:0] litedramcore_bankmachine4_source_source_payload_addr;
+wire litedramcore_bankmachine4_pipe_valid_sink_valid;
+wire litedramcore_bankmachine4_pipe_valid_sink_ready;
+wire litedramcore_bankmachine4_pipe_valid_sink_first;
+wire litedramcore_bankmachine4_pipe_valid_sink_last;
+wire litedramcore_bankmachine4_pipe_valid_sink_payload_we;
+wire [21:0] litedramcore_bankmachine4_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine4_pipe_valid_source_ready;
+reg litedramcore_bankmachine4_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine4_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0;
+reg [21:0] litedramcore_bankmachine4_pipe_valid_source_payload_addr = 22'd0;
+reg [14:0] litedramcore_bankmachine4_row = 15'd0;
+reg litedramcore_bankmachine4_row_opened = 1'd0;
+wire litedramcore_bankmachine4_row_hit;
+reg litedramcore_bankmachine4_row_open = 1'd0;
+reg litedramcore_bankmachine4_row_close = 1'd0;
+reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine4_twtpcon_valid;
+reg litedramcore_bankmachine4_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine4_trccon_valid;
+reg litedramcore_bankmachine4_trccon_ready = 1'd0;
+reg [1:0] litedramcore_bankmachine4_trccon_count = 2'd0;
+wire litedramcore_bankmachine4_trascon_valid;
+reg litedramcore_bankmachine4_trascon_ready = 1'd0;
+reg [1:0] litedramcore_bankmachine4_trascon_count = 2'd0;
+wire litedramcore_bankmachine5_req_valid;
+wire litedramcore_bankmachine5_req_ready;
+wire litedramcore_bankmachine5_req_we;
+wire [21:0] litedramcore_bankmachine5_req_addr;
+wire litedramcore_bankmachine5_req_lock;
+reg litedramcore_bankmachine5_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine5_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine5_refresh_req;
+reg litedramcore_bankmachine5_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine5_cmd_valid = 1'd0;
+reg litedramcore_bankmachine5_cmd_ready = 1'd0;
+reg [14:0] litedramcore_bankmachine5_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine5_cmd_payload_ba;
+reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine5_auto_precharge = 1'd0;
+wire litedramcore_bankmachine5_sink_valid;
+wire litedramcore_bankmachine5_sink_ready;
+reg litedramcore_bankmachine5_sink_first = 1'd0;
+reg litedramcore_bankmachine5_sink_last = 1'd0;
+wire litedramcore_bankmachine5_sink_payload_we;
+wire [21:0] litedramcore_bankmachine5_sink_payload_addr;
+wire litedramcore_bankmachine5_source_valid;
+wire litedramcore_bankmachine5_source_ready;
+wire litedramcore_bankmachine5_source_first;
+wire litedramcore_bankmachine5_source_last;
+wire litedramcore_bankmachine5_source_payload_we;
+wire [21:0] litedramcore_bankmachine5_source_payload_addr;
+wire litedramcore_bankmachine5_syncfifo5_we;
+wire litedramcore_bankmachine5_syncfifo5_writable;
+wire litedramcore_bankmachine5_syncfifo5_re;
+wire litedramcore_bankmachine5_syncfifo5_readable;
+wire [24:0] litedramcore_bankmachine5_syncfifo5_din;
+wire [24:0] litedramcore_bankmachine5_syncfifo5_dout;
+reg [4:0] litedramcore_bankmachine5_level = 5'd0;
+reg litedramcore_bankmachine5_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine5_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine5_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine5_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine5_wrport_dat_r;
+wire litedramcore_bankmachine5_wrport_we;
+wire [24:0] litedramcore_bankmachine5_wrport_dat_w;
+wire litedramcore_bankmachine5_do_read;
+wire [3:0] litedramcore_bankmachine5_rdport_adr;
+wire [24:0] litedramcore_bankmachine5_rdport_dat_r;
+wire litedramcore_bankmachine5_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine5_fifo_in_payload_addr;
+wire litedramcore_bankmachine5_fifo_in_first;
+wire litedramcore_bankmachine5_fifo_in_last;
+wire litedramcore_bankmachine5_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine5_fifo_out_payload_addr;
+wire litedramcore_bankmachine5_fifo_out_first;
+wire litedramcore_bankmachine5_fifo_out_last;
+wire litedramcore_bankmachine5_sink_sink_valid;
+wire litedramcore_bankmachine5_sink_sink_ready;
+wire litedramcore_bankmachine5_sink_sink_first;
+wire litedramcore_bankmachine5_sink_sink_last;
+wire litedramcore_bankmachine5_sink_sink_payload_we;
+wire [21:0] litedramcore_bankmachine5_sink_sink_payload_addr;
+wire litedramcore_bankmachine5_source_source_valid;
+wire litedramcore_bankmachine5_source_source_ready;
+wire litedramcore_bankmachine5_source_source_first;
+wire litedramcore_bankmachine5_source_source_last;
+wire litedramcore_bankmachine5_source_source_payload_we;
+wire [21:0] litedramcore_bankmachine5_source_source_payload_addr;
+wire litedramcore_bankmachine5_pipe_valid_sink_valid;
+wire litedramcore_bankmachine5_pipe_valid_sink_ready;
+wire litedramcore_bankmachine5_pipe_valid_sink_first;
+wire litedramcore_bankmachine5_pipe_valid_sink_last;
+wire litedramcore_bankmachine5_pipe_valid_sink_payload_we;
+wire [21:0] litedramcore_bankmachine5_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine5_pipe_valid_source_ready;
+reg litedramcore_bankmachine5_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine5_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0;
+reg [21:0] litedramcore_bankmachine5_pipe_valid_source_payload_addr = 22'd0;
+reg [14:0] litedramcore_bankmachine5_row = 15'd0;
+reg litedramcore_bankmachine5_row_opened = 1'd0;
+wire litedramcore_bankmachine5_row_hit;
+reg litedramcore_bankmachine5_row_open = 1'd0;
+reg litedramcore_bankmachine5_row_close = 1'd0;
+reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine5_twtpcon_valid;
+reg litedramcore_bankmachine5_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine5_trccon_valid;
+reg litedramcore_bankmachine5_trccon_ready = 1'd0;
+reg [1:0] litedramcore_bankmachine5_trccon_count = 2'd0;
+wire litedramcore_bankmachine5_trascon_valid;
+reg litedramcore_bankmachine5_trascon_ready = 1'd0;
+reg [1:0] litedramcore_bankmachine5_trascon_count = 2'd0;
+wire litedramcore_bankmachine6_req_valid;
+wire litedramcore_bankmachine6_req_ready;
+wire litedramcore_bankmachine6_req_we;
+wire [21:0] litedramcore_bankmachine6_req_addr;
+wire litedramcore_bankmachine6_req_lock;
+reg litedramcore_bankmachine6_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine6_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine6_refresh_req;
+reg litedramcore_bankmachine6_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine6_cmd_valid = 1'd0;
+reg litedramcore_bankmachine6_cmd_ready = 1'd0;
+reg [14:0] litedramcore_bankmachine6_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine6_cmd_payload_ba;
+reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine6_auto_precharge = 1'd0;
+wire litedramcore_bankmachine6_sink_valid;
+wire litedramcore_bankmachine6_sink_ready;
+reg litedramcore_bankmachine6_sink_first = 1'd0;
+reg litedramcore_bankmachine6_sink_last = 1'd0;
+wire litedramcore_bankmachine6_sink_payload_we;
+wire [21:0] litedramcore_bankmachine6_sink_payload_addr;
+wire litedramcore_bankmachine6_source_valid;
+wire litedramcore_bankmachine6_source_ready;
+wire litedramcore_bankmachine6_source_first;
+wire litedramcore_bankmachine6_source_last;
+wire litedramcore_bankmachine6_source_payload_we;
+wire [21:0] litedramcore_bankmachine6_source_payload_addr;
+wire litedramcore_bankmachine6_syncfifo6_we;
+wire litedramcore_bankmachine6_syncfifo6_writable;
+wire litedramcore_bankmachine6_syncfifo6_re;
+wire litedramcore_bankmachine6_syncfifo6_readable;
+wire [24:0] litedramcore_bankmachine6_syncfifo6_din;
+wire [24:0] litedramcore_bankmachine6_syncfifo6_dout;
+reg [4:0] litedramcore_bankmachine6_level = 5'd0;
+reg litedramcore_bankmachine6_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine6_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine6_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine6_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine6_wrport_dat_r;
+wire litedramcore_bankmachine6_wrport_we;
+wire [24:0] litedramcore_bankmachine6_wrport_dat_w;
+wire litedramcore_bankmachine6_do_read;
+wire [3:0] litedramcore_bankmachine6_rdport_adr;
+wire [24:0] litedramcore_bankmachine6_rdport_dat_r;
+wire litedramcore_bankmachine6_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine6_fifo_in_payload_addr;
+wire litedramcore_bankmachine6_fifo_in_first;
+wire litedramcore_bankmachine6_fifo_in_last;
+wire litedramcore_bankmachine6_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine6_fifo_out_payload_addr;
+wire litedramcore_bankmachine6_fifo_out_first;
+wire litedramcore_bankmachine6_fifo_out_last;
+wire litedramcore_bankmachine6_sink_sink_valid;
+wire litedramcore_bankmachine6_sink_sink_ready;
+wire litedramcore_bankmachine6_sink_sink_first;
+wire litedramcore_bankmachine6_sink_sink_last;
+wire litedramcore_bankmachine6_sink_sink_payload_we;
+wire [21:0] litedramcore_bankmachine6_sink_sink_payload_addr;
+wire litedramcore_bankmachine6_source_source_valid;
+wire litedramcore_bankmachine6_source_source_ready;
+wire litedramcore_bankmachine6_source_source_first;
+wire litedramcore_bankmachine6_source_source_last;
+wire litedramcore_bankmachine6_source_source_payload_we;
+wire [21:0] litedramcore_bankmachine6_source_source_payload_addr;
+wire litedramcore_bankmachine6_pipe_valid_sink_valid;
+wire litedramcore_bankmachine6_pipe_valid_sink_ready;
+wire litedramcore_bankmachine6_pipe_valid_sink_first;
+wire litedramcore_bankmachine6_pipe_valid_sink_last;
+wire litedramcore_bankmachine6_pipe_valid_sink_payload_we;
+wire [21:0] litedramcore_bankmachine6_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine6_pipe_valid_source_ready;
+reg litedramcore_bankmachine6_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine6_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0;
+reg [21:0] litedramcore_bankmachine6_pipe_valid_source_payload_addr = 22'd0;
+reg [14:0] litedramcore_bankmachine6_row = 15'd0;
+reg litedramcore_bankmachine6_row_opened = 1'd0;
+wire litedramcore_bankmachine6_row_hit;
+reg litedramcore_bankmachine6_row_open = 1'd0;
+reg litedramcore_bankmachine6_row_close = 1'd0;
+reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine6_twtpcon_valid;
+reg litedramcore_bankmachine6_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine6_trccon_valid;
+reg litedramcore_bankmachine6_trccon_ready = 1'd0;
+reg [1:0] litedramcore_bankmachine6_trccon_count = 2'd0;
+wire litedramcore_bankmachine6_trascon_valid;
+reg litedramcore_bankmachine6_trascon_ready = 1'd0;
+reg [1:0] litedramcore_bankmachine6_trascon_count = 2'd0;
+wire litedramcore_bankmachine7_req_valid;
+wire litedramcore_bankmachine7_req_ready;
+wire litedramcore_bankmachine7_req_we;
+wire [21:0] litedramcore_bankmachine7_req_addr;
+wire litedramcore_bankmachine7_req_lock;
+reg litedramcore_bankmachine7_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine7_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine7_refresh_req;
+reg litedramcore_bankmachine7_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine7_cmd_valid = 1'd0;
+reg litedramcore_bankmachine7_cmd_ready = 1'd0;
+reg [14:0] litedramcore_bankmachine7_cmd_payload_a = 15'd0;
+wire [2:0] litedramcore_bankmachine7_cmd_payload_ba;
+reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine7_auto_precharge = 1'd0;
+wire litedramcore_bankmachine7_sink_valid;
+wire litedramcore_bankmachine7_sink_ready;
+reg litedramcore_bankmachine7_sink_first = 1'd0;
+reg litedramcore_bankmachine7_sink_last = 1'd0;
+wire litedramcore_bankmachine7_sink_payload_we;
+wire [21:0] litedramcore_bankmachine7_sink_payload_addr;
+wire litedramcore_bankmachine7_source_valid;
+wire litedramcore_bankmachine7_source_ready;
+wire litedramcore_bankmachine7_source_first;
+wire litedramcore_bankmachine7_source_last;
+wire litedramcore_bankmachine7_source_payload_we;
+wire [21:0] litedramcore_bankmachine7_source_payload_addr;
+wire litedramcore_bankmachine7_syncfifo7_we;
+wire litedramcore_bankmachine7_syncfifo7_writable;
+wire litedramcore_bankmachine7_syncfifo7_re;
+wire litedramcore_bankmachine7_syncfifo7_readable;
+wire [24:0] litedramcore_bankmachine7_syncfifo7_din;
+wire [24:0] litedramcore_bankmachine7_syncfifo7_dout;
+reg [4:0] litedramcore_bankmachine7_level = 5'd0;
+reg litedramcore_bankmachine7_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine7_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine7_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine7_wrport_adr = 4'd0;
+wire [24:0] litedramcore_bankmachine7_wrport_dat_r;
+wire litedramcore_bankmachine7_wrport_we;
+wire [24:0] litedramcore_bankmachine7_wrport_dat_w;
+wire litedramcore_bankmachine7_do_read;
+wire [3:0] litedramcore_bankmachine7_rdport_adr;
+wire [24:0] litedramcore_bankmachine7_rdport_dat_r;
+wire litedramcore_bankmachine7_fifo_in_payload_we;
+wire [21:0] litedramcore_bankmachine7_fifo_in_payload_addr;
+wire litedramcore_bankmachine7_fifo_in_first;
+wire litedramcore_bankmachine7_fifo_in_last;
+wire litedramcore_bankmachine7_fifo_out_payload_we;
+wire [21:0] litedramcore_bankmachine7_fifo_out_payload_addr;
+wire litedramcore_bankmachine7_fifo_out_first;
+wire litedramcore_bankmachine7_fifo_out_last;
+wire litedramcore_bankmachine7_sink_sink_valid;
+wire litedramcore_bankmachine7_sink_sink_ready;
+wire litedramcore_bankmachine7_sink_sink_first;
+wire litedramcore_bankmachine7_sink_sink_last;
+wire litedramcore_bankmachine7_sink_sink_payload_we;
+wire [21:0] litedramcore_bankmachine7_sink_sink_payload_addr;
+wire litedramcore_bankmachine7_source_source_valid;
+wire litedramcore_bankmachine7_source_source_ready;
+wire litedramcore_bankmachine7_source_source_first;
+wire litedramcore_bankmachine7_source_source_last;
+wire litedramcore_bankmachine7_source_source_payload_we;
+wire [21:0] litedramcore_bankmachine7_source_source_payload_addr;
+wire litedramcore_bankmachine7_pipe_valid_sink_valid;
+wire litedramcore_bankmachine7_pipe_valid_sink_ready;
+wire litedramcore_bankmachine7_pipe_valid_sink_first;
+wire litedramcore_bankmachine7_pipe_valid_sink_last;
+wire litedramcore_bankmachine7_pipe_valid_sink_payload_we;
+wire [21:0] litedramcore_bankmachine7_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine7_pipe_valid_source_ready;
+reg litedramcore_bankmachine7_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine7_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0;
+reg [21:0] litedramcore_bankmachine7_pipe_valid_source_payload_addr = 22'd0;
+reg [14:0] litedramcore_bankmachine7_row = 15'd0;
+reg litedramcore_bankmachine7_row_opened = 1'd0;
+wire litedramcore_bankmachine7_row_hit;
+reg litedramcore_bankmachine7_row_open = 1'd0;
+reg litedramcore_bankmachine7_row_close = 1'd0;
+reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine7_twtpcon_valid;
+reg litedramcore_bankmachine7_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine7_trccon_valid;
+reg litedramcore_bankmachine7_trccon_ready = 1'd0;
+reg [1:0] litedramcore_bankmachine7_trccon_count = 2'd0;
+wire litedramcore_bankmachine7_trascon_valid;
+reg litedramcore_bankmachine7_trascon_ready = 1'd0;
+reg [1:0] litedramcore_bankmachine7_trascon_count = 2'd0;
+wire litedramcore_ras_allowed;
+wire litedramcore_cas_allowed;
+reg litedramcore_choose_cmd_want_reads = 1'd0;
+reg litedramcore_choose_cmd_want_writes = 1'd0;
+reg litedramcore_choose_cmd_want_cmds = 1'd0;
+reg litedramcore_choose_cmd_want_activates = 1'd0;
+wire litedramcore_choose_cmd_cmd_valid;
+reg litedramcore_choose_cmd_cmd_ready = 1'd0;
+wire [14:0] litedramcore_choose_cmd_cmd_payload_a;
+wire [2:0] litedramcore_choose_cmd_cmd_payload_ba;
+reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
+reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
+reg litedramcore_choose_cmd_cmd_payload_we = 1'd0;
+wire litedramcore_choose_cmd_cmd_payload_is_cmd;
+wire litedramcore_choose_cmd_cmd_payload_is_read;
+wire litedramcore_choose_cmd_cmd_payload_is_write;
+reg [7:0] litedramcore_choose_cmd_valids = 8'd0;
+wire [7:0] litedramcore_choose_cmd_request;
+reg [2:0] litedramcore_choose_cmd_grant = 3'd0;
+wire litedramcore_choose_cmd_ce;
+reg litedramcore_choose_req_want_reads = 1'd0;
+reg litedramcore_choose_req_want_writes = 1'd0;
+reg litedramcore_choose_req_want_cmds = 1'd0;
+reg litedramcore_choose_req_want_activates = 1'd0;
+wire litedramcore_choose_req_cmd_valid;
+reg litedramcore_choose_req_cmd_ready = 1'd0;
+wire [14:0] litedramcore_choose_req_cmd_payload_a;
+wire [2:0] litedramcore_choose_req_cmd_payload_ba;
+reg litedramcore_choose_req_cmd_payload_cas = 1'd0;
+reg litedramcore_choose_req_cmd_payload_ras = 1'd0;
+reg litedramcore_choose_req_cmd_payload_we = 1'd0;
+wire litedramcore_choose_req_cmd_payload_is_cmd;
+wire litedramcore_choose_req_cmd_payload_is_read;
+wire litedramcore_choose_req_cmd_payload_is_write;
+reg [7:0] litedramcore_choose_req_valids = 8'd0;
+wire [7:0] litedramcore_choose_req_request;
+reg [2:0] litedramcore_choose_req_grant = 3'd0;
+wire litedramcore_choose_req_ce;
+reg [14:0] litedramcore_nop_a = 15'd0;
+reg [2:0] litedramcore_nop_ba = 3'd0;
+reg [1:0] litedramcore_steerer_sel0 = 2'd0;
+reg [1:0] litedramcore_steerer_sel1 = 2'd0;
+reg litedramcore_steerer0 = 1'd1;
+reg litedramcore_steerer1 = 1'd1;
+reg litedramcore_steerer2 = 1'd1;
+reg litedramcore_steerer3 = 1'd1;
+wire litedramcore_trrdcon_valid;
+reg litedramcore_trrdcon_ready = 1'd0;
+reg litedramcore_trrdcon_count = 1'd0;
+wire litedramcore_tfawcon_valid;
+reg litedramcore_tfawcon_ready = 1'd1;
+wire [1:0] litedramcore_tfawcon_count;
+reg [2:0] litedramcore_tfawcon_window = 3'd0;
+wire litedramcore_tccdcon_valid;
+reg litedramcore_tccdcon_ready = 1'd0;
+reg litedramcore_tccdcon_count = 1'd0;
+wire litedramcore_twtrcon_valid;
+reg litedramcore_twtrcon_ready = 1'd0;
+reg [2:0] litedramcore_twtrcon_count = 3'd0;
+wire litedramcore_read_available;
+wire litedramcore_write_available;
+reg litedramcore_en0 = 1'd0;
+wire litedramcore_max_time0;
+reg [4:0] litedramcore_time0 = 5'd0;
+reg litedramcore_en1 = 1'd0;
+wire litedramcore_max_time1;
+reg [3:0] litedramcore_time1 = 4'd0;
+wire litedramcore_go_to_refresh;
+reg init_done_storage = 1'd0;
+reg init_done_re = 1'd0;
+reg init_error_storage = 1'd0;
+reg init_error_re = 1'd0;
+wire [29:0] wb_bus_adr;
+wire [31:0] wb_bus_dat_w;
+wire [31:0] wb_bus_dat_r;
+wire [3:0] wb_bus_sel;
+wire wb_bus_cyc;
+wire wb_bus_stb;
+wire wb_bus_ack;
+wire wb_bus_we;
+wire [2:0] wb_bus_cti;
+wire [1:0] wb_bus_bte;
+wire wb_bus_err;
+wire user_enable;
+wire user_port_cmd_valid;
+wire user_port_cmd_ready;
+wire user_port_cmd_payload_we;
+wire [24:0] user_port_cmd_payload_addr;
+wire user_port_wdata_valid;
+wire user_port_wdata_ready;
+wire [127:0] user_port_wdata_payload_data;
+wire [15:0] user_port_wdata_payload_we;
+wire user_port_rdata_valid;
+wire user_port_rdata_ready;
+wire [127:0] user_port_rdata_payload_data;
+reg [13:0] litedramcore_adr = 14'd0;
+reg litedramcore_we = 1'd0;
+reg [31:0] litedramcore_dat_w = 32'd0;
+wire [31:0] litedramcore_dat_r;
+wire [29:0] litedramcore_wishbone_adr;
+wire [31:0] litedramcore_wishbone_dat_w;
+reg [31:0] litedramcore_wishbone_dat_r = 32'd0;
+wire [3:0] litedramcore_wishbone_sel;
+wire litedramcore_wishbone_cyc;
+wire litedramcore_wishbone_stb;
+reg litedramcore_wishbone_ack = 1'd0;
+wire litedramcore_wishbone_we;
+wire [2:0] litedramcore_wishbone_cti;
+wire [1:0] litedramcore_wishbone_bte;
+reg litedramcore_wishbone_err = 1'd0;
+wire [13:0] interface0_bank_bus_adr;
+wire interface0_bank_bus_we;
+wire [31:0] interface0_bank_bus_dat_w;
+reg [31:0] interface0_bank_bus_dat_r = 32'd0;
+reg csrbank0_init_done0_re = 1'd0;
+wire csrbank0_init_done0_r;
+reg csrbank0_init_done0_we = 1'd0;
+wire csrbank0_init_done0_w;
+reg csrbank0_init_error0_re = 1'd0;
+wire csrbank0_init_error0_r;
+reg csrbank0_init_error0_we = 1'd0;
+wire csrbank0_init_error0_w;
+wire csrbank0_sel;
+wire [13:0] interface1_bank_bus_adr;
+wire interface1_bank_bus_we;
+wire [31:0] interface1_bank_bus_dat_w;
+reg [31:0] interface1_bank_bus_dat_r = 32'd0;
+reg csrbank1_dly_sel0_re = 1'd0;
+wire [1:0] csrbank1_dly_sel0_r;
+reg csrbank1_dly_sel0_we = 1'd0;
+wire [1:0] csrbank1_dly_sel0_w;
+reg csrbank1_burstdet_seen_re = 1'd0;
+wire [1:0] csrbank1_burstdet_seen_r;
+reg csrbank1_burstdet_seen_we = 1'd0;
+wire [1:0] csrbank1_burstdet_seen_w;
+wire csrbank1_sel;
+wire [13:0] interface2_bank_bus_adr;
+wire interface2_bank_bus_we;
+wire [31:0] interface2_bank_bus_dat_w;
+reg [31:0] interface2_bank_bus_dat_r = 32'd0;
+reg csrbank2_dfii_control0_re = 1'd0;
+wire [3:0] csrbank2_dfii_control0_r;
+reg csrbank2_dfii_control0_we = 1'd0;
+wire [3:0] csrbank2_dfii_control0_w;
+reg csrbank2_dfii_pi0_command0_re = 1'd0;
+wire [5:0] csrbank2_dfii_pi0_command0_r;
+reg csrbank2_dfii_pi0_command0_we = 1'd0;
+wire [5:0] csrbank2_dfii_pi0_command0_w;
+reg csrbank2_dfii_pi0_address0_re = 1'd0;
+wire [14:0] csrbank2_dfii_pi0_address0_r;
+reg csrbank2_dfii_pi0_address0_we = 1'd0;
+wire [14:0] csrbank2_dfii_pi0_address0_w;
+reg csrbank2_dfii_pi0_baddress0_re = 1'd0;
+wire [2:0] csrbank2_dfii_pi0_baddress0_r;
+reg csrbank2_dfii_pi0_baddress0_we = 1'd0;
+wire [2:0] csrbank2_dfii_pi0_baddress0_w;
+reg csrbank2_dfii_pi0_wrdata1_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_wrdata1_r;
+reg csrbank2_dfii_pi0_wrdata1_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_wrdata1_w;
+reg csrbank2_dfii_pi0_wrdata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_wrdata0_r;
+reg csrbank2_dfii_pi0_wrdata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_wrdata0_w;
+reg csrbank2_dfii_pi0_rddata1_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_rddata1_r;
+reg csrbank2_dfii_pi0_rddata1_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_rddata1_w;
+reg csrbank2_dfii_pi0_rddata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_rddata0_r;
+reg csrbank2_dfii_pi0_rddata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_rddata0_w;
+reg csrbank2_dfii_pi1_command0_re = 1'd0;
+wire [5:0] csrbank2_dfii_pi1_command0_r;
+reg csrbank2_dfii_pi1_command0_we = 1'd0;
+wire [5:0] csrbank2_dfii_pi1_command0_w;
+reg csrbank2_dfii_pi1_address0_re = 1'd0;
+wire [14:0] csrbank2_dfii_pi1_address0_r;
+reg csrbank2_dfii_pi1_address0_we = 1'd0;
+wire [14:0] csrbank2_dfii_pi1_address0_w;
+reg csrbank2_dfii_pi1_baddress0_re = 1'd0;
+wire [2:0] csrbank2_dfii_pi1_baddress0_r;
+reg csrbank2_dfii_pi1_baddress0_we = 1'd0;
+wire [2:0] csrbank2_dfii_pi1_baddress0_w;
+reg csrbank2_dfii_pi1_wrdata1_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_wrdata1_r;
+reg csrbank2_dfii_pi1_wrdata1_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_wrdata1_w;
+reg csrbank2_dfii_pi1_wrdata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_wrdata0_r;
+reg csrbank2_dfii_pi1_wrdata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_wrdata0_w;
+reg csrbank2_dfii_pi1_rddata1_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_rddata1_r;
+reg csrbank2_dfii_pi1_rddata1_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_rddata1_w;
+reg csrbank2_dfii_pi1_rddata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_rddata0_r;
+reg csrbank2_dfii_pi1_rddata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_rddata0_w;
+wire csrbank2_sel;
+wire [13:0] csr_interconnect_adr;
+wire csr_interconnect_we;
+wire [31:0] csr_interconnect_dat_w;
+wire [31:0] csr_interconnect_dat_r;
+wire litedramcore_litedramecp5ddrphycrg_ecp5pll;
+wire litedramcore_litedramecp5ddrphycrg_locked;
+reg [1:0] litedramcore_litedramcore_refresher_state = 2'd0;
+reg [1:0] litedramcore_litedramcore_refresher_next_state = 2'd0;
+reg [2:0] litedramcore_litedramcore_bankmachine0_state = 3'd0;
+reg [2:0] litedramcore_litedramcore_bankmachine0_next_state = 3'd0;
+reg [2:0] litedramcore_litedramcore_bankmachine1_state = 3'd0;
+reg [2:0] litedramcore_litedramcore_bankmachine1_next_state = 3'd0;
+reg [2:0] litedramcore_litedramcore_bankmachine2_state = 3'd0;
+reg [2:0] litedramcore_litedramcore_bankmachine2_next_state = 3'd0;
+reg [2:0] litedramcore_litedramcore_bankmachine3_state = 3'd0;
+reg [2:0] litedramcore_litedramcore_bankmachine3_next_state = 3'd0;
+reg [2:0] litedramcore_litedramcore_bankmachine4_state = 3'd0;
+reg [2:0] litedramcore_litedramcore_bankmachine4_next_state = 3'd0;
+reg [2:0] litedramcore_litedramcore_bankmachine5_state = 3'd0;
+reg [2:0] litedramcore_litedramcore_bankmachine5_next_state = 3'd0;
+reg [2:0] litedramcore_litedramcore_bankmachine6_state = 3'd0;
+reg [2:0] litedramcore_litedramcore_bankmachine6_next_state = 3'd0;
+reg [2:0] litedramcore_litedramcore_bankmachine7_state = 3'd0;
+reg [2:0] litedramcore_litedramcore_bankmachine7_next_state = 3'd0;
+reg [3:0] litedramcore_litedramcore_multiplexer_state = 4'd0;
+reg [3:0] litedramcore_litedramcore_multiplexer_next_state = 4'd0;
+wire litedramcore_litedramcore_roundrobin0_request;
+wire litedramcore_litedramcore_roundrobin0_grant;
+wire litedramcore_litedramcore_roundrobin0_ce;
+wire litedramcore_litedramcore_roundrobin1_request;
+wire litedramcore_litedramcore_roundrobin1_grant;
+wire litedramcore_litedramcore_roundrobin1_ce;
+wire litedramcore_litedramcore_roundrobin2_request;
+wire litedramcore_litedramcore_roundrobin2_grant;
+wire litedramcore_litedramcore_roundrobin2_ce;
+wire litedramcore_litedramcore_roundrobin3_request;
+wire litedramcore_litedramcore_roundrobin3_grant;
+wire litedramcore_litedramcore_roundrobin3_ce;
+wire litedramcore_litedramcore_roundrobin4_request;
+wire litedramcore_litedramcore_roundrobin4_grant;
+wire litedramcore_litedramcore_roundrobin4_ce;
+wire litedramcore_litedramcore_roundrobin5_request;
+wire litedramcore_litedramcore_roundrobin5_grant;
+wire litedramcore_litedramcore_roundrobin5_ce;
+wire litedramcore_litedramcore_roundrobin6_request;
+wire litedramcore_litedramcore_roundrobin6_grant;
+wire litedramcore_litedramcore_roundrobin6_ce;
+wire litedramcore_litedramcore_roundrobin7_request;
+wire litedramcore_litedramcore_roundrobin7_grant;
+wire litedramcore_litedramcore_roundrobin7_ce;
+reg litedramcore_litedramcore_locked0 = 1'd0;
+reg litedramcore_litedramcore_locked1 = 1'd0;
+reg litedramcore_litedramcore_locked2 = 1'd0;
+reg litedramcore_litedramcore_locked3 = 1'd0;
+reg litedramcore_litedramcore_locked4 = 1'd0;
+reg litedramcore_litedramcore_locked5 = 1'd0;
+reg litedramcore_litedramcore_locked6 = 1'd0;
+reg litedramcore_litedramcore_locked7 = 1'd0;
+reg litedramcore_litedramcore_new_master_wdata_ready0 = 1'd0;
+reg litedramcore_litedramcore_new_master_wdata_ready1 = 1'd0;
+reg litedramcore_litedramcore_new_master_wdata_ready2 = 1'd0;
+reg litedramcore_litedramcore_new_master_wdata_ready3 = 1'd0;
+reg litedramcore_litedramcore_new_master_rdata_valid0 = 1'd0;
+reg litedramcore_litedramcore_new_master_rdata_valid1 = 1'd0;
+reg litedramcore_litedramcore_new_master_rdata_valid2 = 1'd0;
+reg litedramcore_litedramcore_new_master_rdata_valid3 = 1'd0;
+reg litedramcore_litedramcore_new_master_rdata_valid4 = 1'd0;
+reg litedramcore_litedramcore_new_master_rdata_valid5 = 1'd0;
+reg litedramcore_litedramcore_new_master_rdata_valid6 = 1'd0;
+reg litedramcore_litedramcore_new_master_rdata_valid7 = 1'd0;
+reg litedramcore_litedramcore_new_master_rdata_valid8 = 1'd0;
+reg litedramcore_litedramcore_new_master_rdata_valid9 = 1'd0;
+reg litedramcore_litedramcore_new_master_rdata_valid10 = 1'd0;
+reg litedramcore_litedramcore_new_master_rdata_valid11 = 1'd0;
+reg litedramcore_litedramcore_new_master_rdata_valid12 = 1'd0;
+reg litedramcore_litedramcore_new_master_rdata_valid13 = 1'd0;
+reg [1:0] litedramcore_state = 2'd0;
+reg [1:0] litedramcore_next_state = 2'd0;
+reg [31:0] litedramcore_dat_w_next_value0 = 32'd0;
+reg litedramcore_dat_w_next_value_ce0 = 1'd0;
+reg [13:0] litedramcore_adr_next_value1 = 14'd0;
+reg litedramcore_adr_next_value_ce1 = 1'd0;
+reg litedramcore_we_next_value2 = 1'd0;
+reg litedramcore_we_next_value_ce2 = 1'd0;
+reg rhs_array_muxed0 = 1'd0;
+reg [14:0] rhs_array_muxed1 = 15'd0;
+reg [2:0] rhs_array_muxed2 = 3'd0;
+reg rhs_array_muxed3 = 1'd0;
+reg rhs_array_muxed4 = 1'd0;
+reg rhs_array_muxed5 = 1'd0;
+reg t_array_muxed0 = 1'd0;
+reg t_array_muxed1 = 1'd0;
+reg t_array_muxed2 = 1'd0;
+reg rhs_array_muxed6 = 1'd0;
+reg [14:0] rhs_array_muxed7 = 15'd0;
+reg [2:0] rhs_array_muxed8 = 3'd0;
+reg rhs_array_muxed9 = 1'd0;
+reg rhs_array_muxed10 = 1'd0;
+reg rhs_array_muxed11 = 1'd0;
+reg t_array_muxed3 = 1'd0;
+reg t_array_muxed4 = 1'd0;
+reg t_array_muxed5 = 1'd0;
+reg [21:0] rhs_array_muxed12 = 22'd0;
+reg rhs_array_muxed13 = 1'd0;
+reg rhs_array_muxed14 = 1'd0;
+reg [21:0] rhs_array_muxed15 = 22'd0;
+reg rhs_array_muxed16 = 1'd0;
+reg rhs_array_muxed17 = 1'd0;
+reg [21:0] rhs_array_muxed18 = 22'd0;
+reg rhs_array_muxed19 = 1'd0;
+reg rhs_array_muxed20 = 1'd0;
+reg [21:0] rhs_array_muxed21 = 22'd0;
+reg rhs_array_muxed22 = 1'd0;
+reg rhs_array_muxed23 = 1'd0;
+reg [21:0] rhs_array_muxed24 = 22'd0;
+reg rhs_array_muxed25 = 1'd0;
+reg rhs_array_muxed26 = 1'd0;
+reg [21:0] rhs_array_muxed27 = 22'd0;
+reg rhs_array_muxed28 = 1'd0;
+reg rhs_array_muxed29 = 1'd0;
+reg [21:0] rhs_array_muxed30 = 22'd0;
+reg rhs_array_muxed31 = 1'd0;
+reg rhs_array_muxed32 = 1'd0;
+reg [21:0] rhs_array_muxed33 = 22'd0;
+reg rhs_array_muxed34 = 1'd0;
+reg rhs_array_muxed35 = 1'd0;
+reg [2:0] array_muxed0 = 3'd0;
+reg [14:0] array_muxed1 = 15'd0;
+reg array_muxed2 = 1'd0;
+reg array_muxed3 = 1'd0;
+reg array_muxed4 = 1'd0;
+reg array_muxed5 = 1'd0;
+reg array_muxed6 = 1'd0;
+reg [2:0] array_muxed7 = 3'd0;
+reg [14:0] array_muxed8 = 15'd0;
+reg array_muxed9 = 1'd0;
+reg array_muxed10 = 1'd0;
+reg array_muxed11 = 1'd0;
+reg array_muxed12 = 1'd0;
+reg array_muxed13 = 1'd0;
+wire latticeecp5asyncresetsynchronizerimpl0_rst1;
+wire latticeecp5asyncresetsynchronizerimpl0_expr;
+wire latticeecp5asyncresetsynchronizerimpl1_rst1;
+wire latticeecp5asyncresetsynchronizerimpl2_rst1;
+wire latticeecp5asyncresetsynchronizerimpl3_rst1;
+reg regs0 = 1'd0;
+reg regs1 = 1'd0;
//------------------------------------------------------------------------------
// Combinatorial Logic
assign init_clk = crg_clkout1;
assign crg_locked = (litedramcore_litedramecp5ddrphycrg_locked & (~crg_reset1));
always @(*) begin
- ddrphy_dm_o_data0 <= 8'd0;
- ddrphy_dm_o_data0[0] <= ddrphy_dfi_p0_wrdata_mask[1];
- ddrphy_dm_o_data0[1] <= ddrphy_dfi_p0_wrdata_mask[3];
- ddrphy_dm_o_data0[2] <= ddrphy_dfi_p0_wrdata_mask[5];
- ddrphy_dm_o_data0[3] <= ddrphy_dfi_p0_wrdata_mask[7];
- ddrphy_dm_o_data0[4] <= ddrphy_dfi_p1_wrdata_mask[1];
- ddrphy_dm_o_data0[5] <= ddrphy_dfi_p1_wrdata_mask[3];
- ddrphy_dm_o_data0[6] <= ddrphy_dfi_p1_wrdata_mask[5];
- ddrphy_dm_o_data0[7] <= ddrphy_dfi_p1_wrdata_mask[7];
-end
-always @(*) begin
- ddrphy_dq_o_data0 <= 8'd0;
- ddrphy_dq_o_data0[0] <= ddrphy_dfi_p0_wrdata[0];
- ddrphy_dq_o_data0[1] <= ddrphy_dfi_p0_wrdata[16];
- ddrphy_dq_o_data0[2] <= ddrphy_dfi_p0_wrdata[32];
- ddrphy_dq_o_data0[3] <= ddrphy_dfi_p0_wrdata[48];
- ddrphy_dq_o_data0[4] <= ddrphy_dfi_p1_wrdata[0];
- ddrphy_dq_o_data0[5] <= ddrphy_dfi_p1_wrdata[16];
- ddrphy_dq_o_data0[6] <= ddrphy_dfi_p1_wrdata[32];
- ddrphy_dq_o_data0[7] <= ddrphy_dfi_p1_wrdata[48];
+ ddrphy_dm_o_data0 <= 8'd0;
+ ddrphy_dm_o_data0[0] <= ddrphy_dfi_p0_wrdata_mask[1];
+ ddrphy_dm_o_data0[1] <= ddrphy_dfi_p0_wrdata_mask[3];
+ ddrphy_dm_o_data0[2] <= ddrphy_dfi_p0_wrdata_mask[5];
+ ddrphy_dm_o_data0[3] <= ddrphy_dfi_p0_wrdata_mask[7];
+ ddrphy_dm_o_data0[4] <= ddrphy_dfi_p1_wrdata_mask[1];
+ ddrphy_dm_o_data0[5] <= ddrphy_dfi_p1_wrdata_mask[3];
+ ddrphy_dm_o_data0[6] <= ddrphy_dfi_p1_wrdata_mask[5];
+ ddrphy_dm_o_data0[7] <= ddrphy_dfi_p1_wrdata_mask[7];
+end
+always @(*) begin
+ ddrphy_dq_o_data0 <= 8'd0;
+ ddrphy_dq_o_data0[0] <= ddrphy_dfi_p0_wrdata[0];
+ ddrphy_dq_o_data0[1] <= ddrphy_dfi_p0_wrdata[16];
+ ddrphy_dq_o_data0[2] <= ddrphy_dfi_p0_wrdata[32];
+ ddrphy_dq_o_data0[3] <= ddrphy_dfi_p0_wrdata[48];
+ ddrphy_dq_o_data0[4] <= ddrphy_dfi_p1_wrdata[0];
+ ddrphy_dq_o_data0[5] <= ddrphy_dfi_p1_wrdata[16];
+ ddrphy_dq_o_data0[6] <= ddrphy_dfi_p1_wrdata[32];
+ ddrphy_dq_o_data0[7] <= ddrphy_dfi_p1_wrdata[48];
end
assign ddrphy_dq_i_data0 = {ddrphy_bitslip0_o, ddrphy_dq_i_bitslip_o_d0};
always @(*) begin
- ddrphy_dfi_p0_rddata <= 64'd0;
- ddrphy_dfi_p0_rddata[0] <= ddrphy_dq_i_data0[0];
- ddrphy_dfi_p0_rddata[16] <= ddrphy_dq_i_data0[1];
- ddrphy_dfi_p0_rddata[32] <= ddrphy_dq_i_data0[2];
- ddrphy_dfi_p0_rddata[48] <= ddrphy_dq_i_data0[3];
- ddrphy_dfi_p0_rddata[1] <= ddrphy_dq_i_data1[0];
- ddrphy_dfi_p0_rddata[17] <= ddrphy_dq_i_data1[1];
- ddrphy_dfi_p0_rddata[33] <= ddrphy_dq_i_data1[2];
- ddrphy_dfi_p0_rddata[49] <= ddrphy_dq_i_data1[3];
- ddrphy_dfi_p0_rddata[2] <= ddrphy_dq_i_data2[0];
- ddrphy_dfi_p0_rddata[18] <= ddrphy_dq_i_data2[1];
- ddrphy_dfi_p0_rddata[34] <= ddrphy_dq_i_data2[2];
- ddrphy_dfi_p0_rddata[50] <= ddrphy_dq_i_data2[3];
- ddrphy_dfi_p0_rddata[3] <= ddrphy_dq_i_data3[0];
- ddrphy_dfi_p0_rddata[19] <= ddrphy_dq_i_data3[1];
- ddrphy_dfi_p0_rddata[35] <= ddrphy_dq_i_data3[2];
- ddrphy_dfi_p0_rddata[51] <= ddrphy_dq_i_data3[3];
- ddrphy_dfi_p0_rddata[4] <= ddrphy_dq_i_data4[0];
- ddrphy_dfi_p0_rddata[20] <= ddrphy_dq_i_data4[1];
- ddrphy_dfi_p0_rddata[36] <= ddrphy_dq_i_data4[2];
- ddrphy_dfi_p0_rddata[52] <= ddrphy_dq_i_data4[3];
- ddrphy_dfi_p0_rddata[5] <= ddrphy_dq_i_data5[0];
- ddrphy_dfi_p0_rddata[21] <= ddrphy_dq_i_data5[1];
- ddrphy_dfi_p0_rddata[37] <= ddrphy_dq_i_data5[2];
- ddrphy_dfi_p0_rddata[53] <= ddrphy_dq_i_data5[3];
- ddrphy_dfi_p0_rddata[6] <= ddrphy_dq_i_data6[0];
- ddrphy_dfi_p0_rddata[22] <= ddrphy_dq_i_data6[1];
- ddrphy_dfi_p0_rddata[38] <= ddrphy_dq_i_data6[2];
- ddrphy_dfi_p0_rddata[54] <= ddrphy_dq_i_data6[3];
- ddrphy_dfi_p0_rddata[7] <= ddrphy_dq_i_data7[0];
- ddrphy_dfi_p0_rddata[23] <= ddrphy_dq_i_data7[1];
- ddrphy_dfi_p0_rddata[39] <= ddrphy_dq_i_data7[2];
- ddrphy_dfi_p0_rddata[55] <= ddrphy_dq_i_data7[3];
- ddrphy_dfi_p0_rddata[8] <= ddrphy_dq_i_data8[0];
- ddrphy_dfi_p0_rddata[24] <= ddrphy_dq_i_data8[1];
- ddrphy_dfi_p0_rddata[40] <= ddrphy_dq_i_data8[2];
- ddrphy_dfi_p0_rddata[56] <= ddrphy_dq_i_data8[3];
- ddrphy_dfi_p0_rddata[9] <= ddrphy_dq_i_data9[0];
- ddrphy_dfi_p0_rddata[25] <= ddrphy_dq_i_data9[1];
- ddrphy_dfi_p0_rddata[41] <= ddrphy_dq_i_data9[2];
- ddrphy_dfi_p0_rddata[57] <= ddrphy_dq_i_data9[3];
- ddrphy_dfi_p0_rddata[10] <= ddrphy_dq_i_data10[0];
- ddrphy_dfi_p0_rddata[26] <= ddrphy_dq_i_data10[1];
- ddrphy_dfi_p0_rddata[42] <= ddrphy_dq_i_data10[2];
- ddrphy_dfi_p0_rddata[58] <= ddrphy_dq_i_data10[3];
- ddrphy_dfi_p0_rddata[11] <= ddrphy_dq_i_data11[0];
- ddrphy_dfi_p0_rddata[27] <= ddrphy_dq_i_data11[1];
- ddrphy_dfi_p0_rddata[43] <= ddrphy_dq_i_data11[2];
- ddrphy_dfi_p0_rddata[59] <= ddrphy_dq_i_data11[3];
- ddrphy_dfi_p0_rddata[12] <= ddrphy_dq_i_data12[0];
- ddrphy_dfi_p0_rddata[28] <= ddrphy_dq_i_data12[1];
- ddrphy_dfi_p0_rddata[44] <= ddrphy_dq_i_data12[2];
- ddrphy_dfi_p0_rddata[60] <= ddrphy_dq_i_data12[3];
- ddrphy_dfi_p0_rddata[13] <= ddrphy_dq_i_data13[0];
- ddrphy_dfi_p0_rddata[29] <= ddrphy_dq_i_data13[1];
- ddrphy_dfi_p0_rddata[45] <= ddrphy_dq_i_data13[2];
- ddrphy_dfi_p0_rddata[61] <= ddrphy_dq_i_data13[3];
- ddrphy_dfi_p0_rddata[14] <= ddrphy_dq_i_data14[0];
- ddrphy_dfi_p0_rddata[30] <= ddrphy_dq_i_data14[1];
- ddrphy_dfi_p0_rddata[46] <= ddrphy_dq_i_data14[2];
- ddrphy_dfi_p0_rddata[62] <= ddrphy_dq_i_data14[3];
- ddrphy_dfi_p0_rddata[15] <= ddrphy_dq_i_data15[0];
- ddrphy_dfi_p0_rddata[31] <= ddrphy_dq_i_data15[1];
- ddrphy_dfi_p0_rddata[47] <= ddrphy_dq_i_data15[2];
- ddrphy_dfi_p0_rddata[63] <= ddrphy_dq_i_data15[3];
-end
-always @(*) begin
- ddrphy_dfi_p1_rddata <= 64'd0;
- ddrphy_dfi_p1_rddata[0] <= ddrphy_dq_i_data0[4];
- ddrphy_dfi_p1_rddata[16] <= ddrphy_dq_i_data0[5];
- ddrphy_dfi_p1_rddata[32] <= ddrphy_dq_i_data0[6];
- ddrphy_dfi_p1_rddata[48] <= ddrphy_dq_i_data0[7];
- ddrphy_dfi_p1_rddata[1] <= ddrphy_dq_i_data1[4];
- ddrphy_dfi_p1_rddata[17] <= ddrphy_dq_i_data1[5];
- ddrphy_dfi_p1_rddata[33] <= ddrphy_dq_i_data1[6];
- ddrphy_dfi_p1_rddata[49] <= ddrphy_dq_i_data1[7];
- ddrphy_dfi_p1_rddata[2] <= ddrphy_dq_i_data2[4];
- ddrphy_dfi_p1_rddata[18] <= ddrphy_dq_i_data2[5];
- ddrphy_dfi_p1_rddata[34] <= ddrphy_dq_i_data2[6];
- ddrphy_dfi_p1_rddata[50] <= ddrphy_dq_i_data2[7];
- ddrphy_dfi_p1_rddata[3] <= ddrphy_dq_i_data3[4];
- ddrphy_dfi_p1_rddata[19] <= ddrphy_dq_i_data3[5];
- ddrphy_dfi_p1_rddata[35] <= ddrphy_dq_i_data3[6];
- ddrphy_dfi_p1_rddata[51] <= ddrphy_dq_i_data3[7];
- ddrphy_dfi_p1_rddata[4] <= ddrphy_dq_i_data4[4];
- ddrphy_dfi_p1_rddata[20] <= ddrphy_dq_i_data4[5];
- ddrphy_dfi_p1_rddata[36] <= ddrphy_dq_i_data4[6];
- ddrphy_dfi_p1_rddata[52] <= ddrphy_dq_i_data4[7];
- ddrphy_dfi_p1_rddata[5] <= ddrphy_dq_i_data5[4];
- ddrphy_dfi_p1_rddata[21] <= ddrphy_dq_i_data5[5];
- ddrphy_dfi_p1_rddata[37] <= ddrphy_dq_i_data5[6];
- ddrphy_dfi_p1_rddata[53] <= ddrphy_dq_i_data5[7];
- ddrphy_dfi_p1_rddata[6] <= ddrphy_dq_i_data6[4];
- ddrphy_dfi_p1_rddata[22] <= ddrphy_dq_i_data6[5];
- ddrphy_dfi_p1_rddata[38] <= ddrphy_dq_i_data6[6];
- ddrphy_dfi_p1_rddata[54] <= ddrphy_dq_i_data6[7];
- ddrphy_dfi_p1_rddata[7] <= ddrphy_dq_i_data7[4];
- ddrphy_dfi_p1_rddata[23] <= ddrphy_dq_i_data7[5];
- ddrphy_dfi_p1_rddata[39] <= ddrphy_dq_i_data7[6];
- ddrphy_dfi_p1_rddata[55] <= ddrphy_dq_i_data7[7];
- ddrphy_dfi_p1_rddata[8] <= ddrphy_dq_i_data8[4];
- ddrphy_dfi_p1_rddata[24] <= ddrphy_dq_i_data8[5];
- ddrphy_dfi_p1_rddata[40] <= ddrphy_dq_i_data8[6];
- ddrphy_dfi_p1_rddata[56] <= ddrphy_dq_i_data8[7];
- ddrphy_dfi_p1_rddata[9] <= ddrphy_dq_i_data9[4];
- ddrphy_dfi_p1_rddata[25] <= ddrphy_dq_i_data9[5];
- ddrphy_dfi_p1_rddata[41] <= ddrphy_dq_i_data9[6];
- ddrphy_dfi_p1_rddata[57] <= ddrphy_dq_i_data9[7];
- ddrphy_dfi_p1_rddata[10] <= ddrphy_dq_i_data10[4];
- ddrphy_dfi_p1_rddata[26] <= ddrphy_dq_i_data10[5];
- ddrphy_dfi_p1_rddata[42] <= ddrphy_dq_i_data10[6];
- ddrphy_dfi_p1_rddata[58] <= ddrphy_dq_i_data10[7];
- ddrphy_dfi_p1_rddata[11] <= ddrphy_dq_i_data11[4];
- ddrphy_dfi_p1_rddata[27] <= ddrphy_dq_i_data11[5];
- ddrphy_dfi_p1_rddata[43] <= ddrphy_dq_i_data11[6];
- ddrphy_dfi_p1_rddata[59] <= ddrphy_dq_i_data11[7];
- ddrphy_dfi_p1_rddata[12] <= ddrphy_dq_i_data12[4];
- ddrphy_dfi_p1_rddata[28] <= ddrphy_dq_i_data12[5];
- ddrphy_dfi_p1_rddata[44] <= ddrphy_dq_i_data12[6];
- ddrphy_dfi_p1_rddata[60] <= ddrphy_dq_i_data12[7];
- ddrphy_dfi_p1_rddata[13] <= ddrphy_dq_i_data13[4];
- ddrphy_dfi_p1_rddata[29] <= ddrphy_dq_i_data13[5];
- ddrphy_dfi_p1_rddata[45] <= ddrphy_dq_i_data13[6];
- ddrphy_dfi_p1_rddata[61] <= ddrphy_dq_i_data13[7];
- ddrphy_dfi_p1_rddata[14] <= ddrphy_dq_i_data14[4];
- ddrphy_dfi_p1_rddata[30] <= ddrphy_dq_i_data14[5];
- ddrphy_dfi_p1_rddata[46] <= ddrphy_dq_i_data14[6];
- ddrphy_dfi_p1_rddata[62] <= ddrphy_dq_i_data14[7];
- ddrphy_dfi_p1_rddata[15] <= ddrphy_dq_i_data15[4];
- ddrphy_dfi_p1_rddata[31] <= ddrphy_dq_i_data15[5];
- ddrphy_dfi_p1_rddata[47] <= ddrphy_dq_i_data15[6];
- ddrphy_dfi_p1_rddata[63] <= ddrphy_dq_i_data15[7];
-end
-always @(*) begin
- ddrphy_dq_o_data1 <= 8'd0;
- ddrphy_dq_o_data1[0] <= ddrphy_dfi_p0_wrdata[1];
- ddrphy_dq_o_data1[1] <= ddrphy_dfi_p0_wrdata[17];
- ddrphy_dq_o_data1[2] <= ddrphy_dfi_p0_wrdata[33];
- ddrphy_dq_o_data1[3] <= ddrphy_dfi_p0_wrdata[49];
- ddrphy_dq_o_data1[4] <= ddrphy_dfi_p1_wrdata[1];
- ddrphy_dq_o_data1[5] <= ddrphy_dfi_p1_wrdata[17];
- ddrphy_dq_o_data1[6] <= ddrphy_dfi_p1_wrdata[33];
- ddrphy_dq_o_data1[7] <= ddrphy_dfi_p1_wrdata[49];
+ ddrphy_dfi_p0_rddata <= 64'd0;
+ ddrphy_dfi_p0_rddata[0] <= ddrphy_dq_i_data0[0];
+ ddrphy_dfi_p0_rddata[16] <= ddrphy_dq_i_data0[1];
+ ddrphy_dfi_p0_rddata[32] <= ddrphy_dq_i_data0[2];
+ ddrphy_dfi_p0_rddata[48] <= ddrphy_dq_i_data0[3];
+ ddrphy_dfi_p0_rddata[1] <= ddrphy_dq_i_data1[0];
+ ddrphy_dfi_p0_rddata[17] <= ddrphy_dq_i_data1[1];
+ ddrphy_dfi_p0_rddata[33] <= ddrphy_dq_i_data1[2];
+ ddrphy_dfi_p0_rddata[49] <= ddrphy_dq_i_data1[3];
+ ddrphy_dfi_p0_rddata[2] <= ddrphy_dq_i_data2[0];
+ ddrphy_dfi_p0_rddata[18] <= ddrphy_dq_i_data2[1];
+ ddrphy_dfi_p0_rddata[34] <= ddrphy_dq_i_data2[2];
+ ddrphy_dfi_p0_rddata[50] <= ddrphy_dq_i_data2[3];
+ ddrphy_dfi_p0_rddata[3] <= ddrphy_dq_i_data3[0];
+ ddrphy_dfi_p0_rddata[19] <= ddrphy_dq_i_data3[1];
+ ddrphy_dfi_p0_rddata[35] <= ddrphy_dq_i_data3[2];
+ ddrphy_dfi_p0_rddata[51] <= ddrphy_dq_i_data3[3];
+ ddrphy_dfi_p0_rddata[4] <= ddrphy_dq_i_data4[0];
+ ddrphy_dfi_p0_rddata[20] <= ddrphy_dq_i_data4[1];
+ ddrphy_dfi_p0_rddata[36] <= ddrphy_dq_i_data4[2];
+ ddrphy_dfi_p0_rddata[52] <= ddrphy_dq_i_data4[3];
+ ddrphy_dfi_p0_rddata[5] <= ddrphy_dq_i_data5[0];
+ ddrphy_dfi_p0_rddata[21] <= ddrphy_dq_i_data5[1];
+ ddrphy_dfi_p0_rddata[37] <= ddrphy_dq_i_data5[2];
+ ddrphy_dfi_p0_rddata[53] <= ddrphy_dq_i_data5[3];
+ ddrphy_dfi_p0_rddata[6] <= ddrphy_dq_i_data6[0];
+ ddrphy_dfi_p0_rddata[22] <= ddrphy_dq_i_data6[1];
+ ddrphy_dfi_p0_rddata[38] <= ddrphy_dq_i_data6[2];
+ ddrphy_dfi_p0_rddata[54] <= ddrphy_dq_i_data6[3];
+ ddrphy_dfi_p0_rddata[7] <= ddrphy_dq_i_data7[0];
+ ddrphy_dfi_p0_rddata[23] <= ddrphy_dq_i_data7[1];
+ ddrphy_dfi_p0_rddata[39] <= ddrphy_dq_i_data7[2];
+ ddrphy_dfi_p0_rddata[55] <= ddrphy_dq_i_data7[3];
+ ddrphy_dfi_p0_rddata[8] <= ddrphy_dq_i_data8[0];
+ ddrphy_dfi_p0_rddata[24] <= ddrphy_dq_i_data8[1];
+ ddrphy_dfi_p0_rddata[40] <= ddrphy_dq_i_data8[2];
+ ddrphy_dfi_p0_rddata[56] <= ddrphy_dq_i_data8[3];
+ ddrphy_dfi_p0_rddata[9] <= ddrphy_dq_i_data9[0];
+ ddrphy_dfi_p0_rddata[25] <= ddrphy_dq_i_data9[1];
+ ddrphy_dfi_p0_rddata[41] <= ddrphy_dq_i_data9[2];
+ ddrphy_dfi_p0_rddata[57] <= ddrphy_dq_i_data9[3];
+ ddrphy_dfi_p0_rddata[10] <= ddrphy_dq_i_data10[0];
+ ddrphy_dfi_p0_rddata[26] <= ddrphy_dq_i_data10[1];
+ ddrphy_dfi_p0_rddata[42] <= ddrphy_dq_i_data10[2];
+ ddrphy_dfi_p0_rddata[58] <= ddrphy_dq_i_data10[3];
+ ddrphy_dfi_p0_rddata[11] <= ddrphy_dq_i_data11[0];
+ ddrphy_dfi_p0_rddata[27] <= ddrphy_dq_i_data11[1];
+ ddrphy_dfi_p0_rddata[43] <= ddrphy_dq_i_data11[2];
+ ddrphy_dfi_p0_rddata[59] <= ddrphy_dq_i_data11[3];
+ ddrphy_dfi_p0_rddata[12] <= ddrphy_dq_i_data12[0];
+ ddrphy_dfi_p0_rddata[28] <= ddrphy_dq_i_data12[1];
+ ddrphy_dfi_p0_rddata[44] <= ddrphy_dq_i_data12[2];
+ ddrphy_dfi_p0_rddata[60] <= ddrphy_dq_i_data12[3];
+ ddrphy_dfi_p0_rddata[13] <= ddrphy_dq_i_data13[0];
+ ddrphy_dfi_p0_rddata[29] <= ddrphy_dq_i_data13[1];
+ ddrphy_dfi_p0_rddata[45] <= ddrphy_dq_i_data13[2];
+ ddrphy_dfi_p0_rddata[61] <= ddrphy_dq_i_data13[3];
+ ddrphy_dfi_p0_rddata[14] <= ddrphy_dq_i_data14[0];
+ ddrphy_dfi_p0_rddata[30] <= ddrphy_dq_i_data14[1];
+ ddrphy_dfi_p0_rddata[46] <= ddrphy_dq_i_data14[2];
+ ddrphy_dfi_p0_rddata[62] <= ddrphy_dq_i_data14[3];
+ ddrphy_dfi_p0_rddata[15] <= ddrphy_dq_i_data15[0];
+ ddrphy_dfi_p0_rddata[31] <= ddrphy_dq_i_data15[1];
+ ddrphy_dfi_p0_rddata[47] <= ddrphy_dq_i_data15[2];
+ ddrphy_dfi_p0_rddata[63] <= ddrphy_dq_i_data15[3];
+end
+always @(*) begin
+ ddrphy_dfi_p1_rddata <= 64'd0;
+ ddrphy_dfi_p1_rddata[0] <= ddrphy_dq_i_data0[4];
+ ddrphy_dfi_p1_rddata[16] <= ddrphy_dq_i_data0[5];
+ ddrphy_dfi_p1_rddata[32] <= ddrphy_dq_i_data0[6];
+ ddrphy_dfi_p1_rddata[48] <= ddrphy_dq_i_data0[7];
+ ddrphy_dfi_p1_rddata[1] <= ddrphy_dq_i_data1[4];
+ ddrphy_dfi_p1_rddata[17] <= ddrphy_dq_i_data1[5];
+ ddrphy_dfi_p1_rddata[33] <= ddrphy_dq_i_data1[6];
+ ddrphy_dfi_p1_rddata[49] <= ddrphy_dq_i_data1[7];
+ ddrphy_dfi_p1_rddata[2] <= ddrphy_dq_i_data2[4];
+ ddrphy_dfi_p1_rddata[18] <= ddrphy_dq_i_data2[5];
+ ddrphy_dfi_p1_rddata[34] <= ddrphy_dq_i_data2[6];
+ ddrphy_dfi_p1_rddata[50] <= ddrphy_dq_i_data2[7];
+ ddrphy_dfi_p1_rddata[3] <= ddrphy_dq_i_data3[4];
+ ddrphy_dfi_p1_rddata[19] <= ddrphy_dq_i_data3[5];
+ ddrphy_dfi_p1_rddata[35] <= ddrphy_dq_i_data3[6];
+ ddrphy_dfi_p1_rddata[51] <= ddrphy_dq_i_data3[7];
+ ddrphy_dfi_p1_rddata[4] <= ddrphy_dq_i_data4[4];
+ ddrphy_dfi_p1_rddata[20] <= ddrphy_dq_i_data4[5];
+ ddrphy_dfi_p1_rddata[36] <= ddrphy_dq_i_data4[6];
+ ddrphy_dfi_p1_rddata[52] <= ddrphy_dq_i_data4[7];
+ ddrphy_dfi_p1_rddata[5] <= ddrphy_dq_i_data5[4];
+ ddrphy_dfi_p1_rddata[21] <= ddrphy_dq_i_data5[5];
+ ddrphy_dfi_p1_rddata[37] <= ddrphy_dq_i_data5[6];
+ ddrphy_dfi_p1_rddata[53] <= ddrphy_dq_i_data5[7];
+ ddrphy_dfi_p1_rddata[6] <= ddrphy_dq_i_data6[4];
+ ddrphy_dfi_p1_rddata[22] <= ddrphy_dq_i_data6[5];
+ ddrphy_dfi_p1_rddata[38] <= ddrphy_dq_i_data6[6];
+ ddrphy_dfi_p1_rddata[54] <= ddrphy_dq_i_data6[7];
+ ddrphy_dfi_p1_rddata[7] <= ddrphy_dq_i_data7[4];
+ ddrphy_dfi_p1_rddata[23] <= ddrphy_dq_i_data7[5];
+ ddrphy_dfi_p1_rddata[39] <= ddrphy_dq_i_data7[6];
+ ddrphy_dfi_p1_rddata[55] <= ddrphy_dq_i_data7[7];
+ ddrphy_dfi_p1_rddata[8] <= ddrphy_dq_i_data8[4];
+ ddrphy_dfi_p1_rddata[24] <= ddrphy_dq_i_data8[5];
+ ddrphy_dfi_p1_rddata[40] <= ddrphy_dq_i_data8[6];
+ ddrphy_dfi_p1_rddata[56] <= ddrphy_dq_i_data8[7];
+ ddrphy_dfi_p1_rddata[9] <= ddrphy_dq_i_data9[4];
+ ddrphy_dfi_p1_rddata[25] <= ddrphy_dq_i_data9[5];
+ ddrphy_dfi_p1_rddata[41] <= ddrphy_dq_i_data9[6];
+ ddrphy_dfi_p1_rddata[57] <= ddrphy_dq_i_data9[7];
+ ddrphy_dfi_p1_rddata[10] <= ddrphy_dq_i_data10[4];
+ ddrphy_dfi_p1_rddata[26] <= ddrphy_dq_i_data10[5];
+ ddrphy_dfi_p1_rddata[42] <= ddrphy_dq_i_data10[6];
+ ddrphy_dfi_p1_rddata[58] <= ddrphy_dq_i_data10[7];
+ ddrphy_dfi_p1_rddata[11] <= ddrphy_dq_i_data11[4];
+ ddrphy_dfi_p1_rddata[27] <= ddrphy_dq_i_data11[5];
+ ddrphy_dfi_p1_rddata[43] <= ddrphy_dq_i_data11[6];
+ ddrphy_dfi_p1_rddata[59] <= ddrphy_dq_i_data11[7];
+ ddrphy_dfi_p1_rddata[12] <= ddrphy_dq_i_data12[4];
+ ddrphy_dfi_p1_rddata[28] <= ddrphy_dq_i_data12[5];
+ ddrphy_dfi_p1_rddata[44] <= ddrphy_dq_i_data12[6];
+ ddrphy_dfi_p1_rddata[60] <= ddrphy_dq_i_data12[7];
+ ddrphy_dfi_p1_rddata[13] <= ddrphy_dq_i_data13[4];
+ ddrphy_dfi_p1_rddata[29] <= ddrphy_dq_i_data13[5];
+ ddrphy_dfi_p1_rddata[45] <= ddrphy_dq_i_data13[6];
+ ddrphy_dfi_p1_rddata[61] <= ddrphy_dq_i_data13[7];
+ ddrphy_dfi_p1_rddata[14] <= ddrphy_dq_i_data14[4];
+ ddrphy_dfi_p1_rddata[30] <= ddrphy_dq_i_data14[5];
+ ddrphy_dfi_p1_rddata[46] <= ddrphy_dq_i_data14[6];
+ ddrphy_dfi_p1_rddata[62] <= ddrphy_dq_i_data14[7];
+ ddrphy_dfi_p1_rddata[15] <= ddrphy_dq_i_data15[4];
+ ddrphy_dfi_p1_rddata[31] <= ddrphy_dq_i_data15[5];
+ ddrphy_dfi_p1_rddata[47] <= ddrphy_dq_i_data15[6];
+ ddrphy_dfi_p1_rddata[63] <= ddrphy_dq_i_data15[7];
+end
+always @(*) begin
+ ddrphy_dq_o_data1 <= 8'd0;
+ ddrphy_dq_o_data1[0] <= ddrphy_dfi_p0_wrdata[1];
+ ddrphy_dq_o_data1[1] <= ddrphy_dfi_p0_wrdata[17];
+ ddrphy_dq_o_data1[2] <= ddrphy_dfi_p0_wrdata[33];
+ ddrphy_dq_o_data1[3] <= ddrphy_dfi_p0_wrdata[49];
+ ddrphy_dq_o_data1[4] <= ddrphy_dfi_p1_wrdata[1];
+ ddrphy_dq_o_data1[5] <= ddrphy_dfi_p1_wrdata[17];
+ ddrphy_dq_o_data1[6] <= ddrphy_dfi_p1_wrdata[33];
+ ddrphy_dq_o_data1[7] <= ddrphy_dfi_p1_wrdata[49];
end
assign ddrphy_dq_i_data1 = {ddrphy_bitslip1_o, ddrphy_dq_i_bitslip_o_d1};
always @(*) begin
- ddrphy_dq_o_data2 <= 8'd0;
- ddrphy_dq_o_data2[0] <= ddrphy_dfi_p0_wrdata[2];
- ddrphy_dq_o_data2[1] <= ddrphy_dfi_p0_wrdata[18];
- ddrphy_dq_o_data2[2] <= ddrphy_dfi_p0_wrdata[34];
- ddrphy_dq_o_data2[3] <= ddrphy_dfi_p0_wrdata[50];
- ddrphy_dq_o_data2[4] <= ddrphy_dfi_p1_wrdata[2];
- ddrphy_dq_o_data2[5] <= ddrphy_dfi_p1_wrdata[18];
- ddrphy_dq_o_data2[6] <= ddrphy_dfi_p1_wrdata[34];
- ddrphy_dq_o_data2[7] <= ddrphy_dfi_p1_wrdata[50];
+ ddrphy_dq_o_data2 <= 8'd0;
+ ddrphy_dq_o_data2[0] <= ddrphy_dfi_p0_wrdata[2];
+ ddrphy_dq_o_data2[1] <= ddrphy_dfi_p0_wrdata[18];
+ ddrphy_dq_o_data2[2] <= ddrphy_dfi_p0_wrdata[34];
+ ddrphy_dq_o_data2[3] <= ddrphy_dfi_p0_wrdata[50];
+ ddrphy_dq_o_data2[4] <= ddrphy_dfi_p1_wrdata[2];
+ ddrphy_dq_o_data2[5] <= ddrphy_dfi_p1_wrdata[18];
+ ddrphy_dq_o_data2[6] <= ddrphy_dfi_p1_wrdata[34];
+ ddrphy_dq_o_data2[7] <= ddrphy_dfi_p1_wrdata[50];
end
assign ddrphy_dq_i_data2 = {ddrphy_bitslip2_o, ddrphy_dq_i_bitslip_o_d2};
always @(*) begin
- ddrphy_dq_o_data3 <= 8'd0;
- ddrphy_dq_o_data3[0] <= ddrphy_dfi_p0_wrdata[3];
- ddrphy_dq_o_data3[1] <= ddrphy_dfi_p0_wrdata[19];
- ddrphy_dq_o_data3[2] <= ddrphy_dfi_p0_wrdata[35];
- ddrphy_dq_o_data3[3] <= ddrphy_dfi_p0_wrdata[51];
- ddrphy_dq_o_data3[4] <= ddrphy_dfi_p1_wrdata[3];
- ddrphy_dq_o_data3[5] <= ddrphy_dfi_p1_wrdata[19];
- ddrphy_dq_o_data3[6] <= ddrphy_dfi_p1_wrdata[35];
- ddrphy_dq_o_data3[7] <= ddrphy_dfi_p1_wrdata[51];
+ ddrphy_dq_o_data3 <= 8'd0;
+ ddrphy_dq_o_data3[0] <= ddrphy_dfi_p0_wrdata[3];
+ ddrphy_dq_o_data3[1] <= ddrphy_dfi_p0_wrdata[19];
+ ddrphy_dq_o_data3[2] <= ddrphy_dfi_p0_wrdata[35];
+ ddrphy_dq_o_data3[3] <= ddrphy_dfi_p0_wrdata[51];
+ ddrphy_dq_o_data3[4] <= ddrphy_dfi_p1_wrdata[3];
+ ddrphy_dq_o_data3[5] <= ddrphy_dfi_p1_wrdata[19];
+ ddrphy_dq_o_data3[6] <= ddrphy_dfi_p1_wrdata[35];
+ ddrphy_dq_o_data3[7] <= ddrphy_dfi_p1_wrdata[51];
end
assign ddrphy_dq_i_data3 = {ddrphy_bitslip3_o, ddrphy_dq_i_bitslip_o_d3};
always @(*) begin
- ddrphy_dq_o_data4 <= 8'd0;
- ddrphy_dq_o_data4[0] <= ddrphy_dfi_p0_wrdata[4];
- ddrphy_dq_o_data4[1] <= ddrphy_dfi_p0_wrdata[20];
- ddrphy_dq_o_data4[2] <= ddrphy_dfi_p0_wrdata[36];
- ddrphy_dq_o_data4[3] <= ddrphy_dfi_p0_wrdata[52];
- ddrphy_dq_o_data4[4] <= ddrphy_dfi_p1_wrdata[4];
- ddrphy_dq_o_data4[5] <= ddrphy_dfi_p1_wrdata[20];
- ddrphy_dq_o_data4[6] <= ddrphy_dfi_p1_wrdata[36];
- ddrphy_dq_o_data4[7] <= ddrphy_dfi_p1_wrdata[52];
+ ddrphy_dq_o_data4 <= 8'd0;
+ ddrphy_dq_o_data4[0] <= ddrphy_dfi_p0_wrdata[4];
+ ddrphy_dq_o_data4[1] <= ddrphy_dfi_p0_wrdata[20];
+ ddrphy_dq_o_data4[2] <= ddrphy_dfi_p0_wrdata[36];
+ ddrphy_dq_o_data4[3] <= ddrphy_dfi_p0_wrdata[52];
+ ddrphy_dq_o_data4[4] <= ddrphy_dfi_p1_wrdata[4];
+ ddrphy_dq_o_data4[5] <= ddrphy_dfi_p1_wrdata[20];
+ ddrphy_dq_o_data4[6] <= ddrphy_dfi_p1_wrdata[36];
+ ddrphy_dq_o_data4[7] <= ddrphy_dfi_p1_wrdata[52];
end
assign ddrphy_dq_i_data4 = {ddrphy_bitslip4_o, ddrphy_dq_i_bitslip_o_d4};
always @(*) begin
- ddrphy_dq_o_data5 <= 8'd0;
- ddrphy_dq_o_data5[0] <= ddrphy_dfi_p0_wrdata[5];
- ddrphy_dq_o_data5[1] <= ddrphy_dfi_p0_wrdata[21];
- ddrphy_dq_o_data5[2] <= ddrphy_dfi_p0_wrdata[37];
- ddrphy_dq_o_data5[3] <= ddrphy_dfi_p0_wrdata[53];
- ddrphy_dq_o_data5[4] <= ddrphy_dfi_p1_wrdata[5];
- ddrphy_dq_o_data5[5] <= ddrphy_dfi_p1_wrdata[21];
- ddrphy_dq_o_data5[6] <= ddrphy_dfi_p1_wrdata[37];
- ddrphy_dq_o_data5[7] <= ddrphy_dfi_p1_wrdata[53];
+ ddrphy_dq_o_data5 <= 8'd0;
+ ddrphy_dq_o_data5[0] <= ddrphy_dfi_p0_wrdata[5];
+ ddrphy_dq_o_data5[1] <= ddrphy_dfi_p0_wrdata[21];
+ ddrphy_dq_o_data5[2] <= ddrphy_dfi_p0_wrdata[37];
+ ddrphy_dq_o_data5[3] <= ddrphy_dfi_p0_wrdata[53];
+ ddrphy_dq_o_data5[4] <= ddrphy_dfi_p1_wrdata[5];
+ ddrphy_dq_o_data5[5] <= ddrphy_dfi_p1_wrdata[21];
+ ddrphy_dq_o_data5[6] <= ddrphy_dfi_p1_wrdata[37];
+ ddrphy_dq_o_data5[7] <= ddrphy_dfi_p1_wrdata[53];
end
assign ddrphy_dq_i_data5 = {ddrphy_bitslip5_o, ddrphy_dq_i_bitslip_o_d5};
always @(*) begin
- ddrphy_dq_o_data6 <= 8'd0;
- ddrphy_dq_o_data6[0] <= ddrphy_dfi_p0_wrdata[6];
- ddrphy_dq_o_data6[1] <= ddrphy_dfi_p0_wrdata[22];
- ddrphy_dq_o_data6[2] <= ddrphy_dfi_p0_wrdata[38];
- ddrphy_dq_o_data6[3] <= ddrphy_dfi_p0_wrdata[54];
- ddrphy_dq_o_data6[4] <= ddrphy_dfi_p1_wrdata[6];
- ddrphy_dq_o_data6[5] <= ddrphy_dfi_p1_wrdata[22];
- ddrphy_dq_o_data6[6] <= ddrphy_dfi_p1_wrdata[38];
- ddrphy_dq_o_data6[7] <= ddrphy_dfi_p1_wrdata[54];
+ ddrphy_dq_o_data6 <= 8'd0;
+ ddrphy_dq_o_data6[0] <= ddrphy_dfi_p0_wrdata[6];
+ ddrphy_dq_o_data6[1] <= ddrphy_dfi_p0_wrdata[22];
+ ddrphy_dq_o_data6[2] <= ddrphy_dfi_p0_wrdata[38];
+ ddrphy_dq_o_data6[3] <= ddrphy_dfi_p0_wrdata[54];
+ ddrphy_dq_o_data6[4] <= ddrphy_dfi_p1_wrdata[6];
+ ddrphy_dq_o_data6[5] <= ddrphy_dfi_p1_wrdata[22];
+ ddrphy_dq_o_data6[6] <= ddrphy_dfi_p1_wrdata[38];
+ ddrphy_dq_o_data6[7] <= ddrphy_dfi_p1_wrdata[54];
end
assign ddrphy_dq_i_data6 = {ddrphy_bitslip6_o, ddrphy_dq_i_bitslip_o_d6};
always @(*) begin
- ddrphy_dq_o_data7 <= 8'd0;
- ddrphy_dq_o_data7[0] <= ddrphy_dfi_p0_wrdata[7];
- ddrphy_dq_o_data7[1] <= ddrphy_dfi_p0_wrdata[23];
- ddrphy_dq_o_data7[2] <= ddrphy_dfi_p0_wrdata[39];
- ddrphy_dq_o_data7[3] <= ddrphy_dfi_p0_wrdata[55];
- ddrphy_dq_o_data7[4] <= ddrphy_dfi_p1_wrdata[7];
- ddrphy_dq_o_data7[5] <= ddrphy_dfi_p1_wrdata[23];
- ddrphy_dq_o_data7[6] <= ddrphy_dfi_p1_wrdata[39];
- ddrphy_dq_o_data7[7] <= ddrphy_dfi_p1_wrdata[55];
+ ddrphy_dq_o_data7 <= 8'd0;
+ ddrphy_dq_o_data7[0] <= ddrphy_dfi_p0_wrdata[7];
+ ddrphy_dq_o_data7[1] <= ddrphy_dfi_p0_wrdata[23];
+ ddrphy_dq_o_data7[2] <= ddrphy_dfi_p0_wrdata[39];
+ ddrphy_dq_o_data7[3] <= ddrphy_dfi_p0_wrdata[55];
+ ddrphy_dq_o_data7[4] <= ddrphy_dfi_p1_wrdata[7];
+ ddrphy_dq_o_data7[5] <= ddrphy_dfi_p1_wrdata[23];
+ ddrphy_dq_o_data7[6] <= ddrphy_dfi_p1_wrdata[39];
+ ddrphy_dq_o_data7[7] <= ddrphy_dfi_p1_wrdata[55];
end
assign ddrphy_dq_i_data7 = {ddrphy_bitslip7_o, ddrphy_dq_i_bitslip_o_d7};
always @(*) begin
- ddrphy_dm_o_data1 <= 8'd0;
- ddrphy_dm_o_data1[0] <= ddrphy_dfi_p0_wrdata_mask[0];
- ddrphy_dm_o_data1[1] <= ddrphy_dfi_p0_wrdata_mask[2];
- ddrphy_dm_o_data1[2] <= ddrphy_dfi_p0_wrdata_mask[4];
- ddrphy_dm_o_data1[3] <= ddrphy_dfi_p0_wrdata_mask[6];
- ddrphy_dm_o_data1[4] <= ddrphy_dfi_p1_wrdata_mask[0];
- ddrphy_dm_o_data1[5] <= ddrphy_dfi_p1_wrdata_mask[2];
- ddrphy_dm_o_data1[6] <= ddrphy_dfi_p1_wrdata_mask[4];
- ddrphy_dm_o_data1[7] <= ddrphy_dfi_p1_wrdata_mask[6];
-end
-always @(*) begin
- ddrphy_dq_o_data8 <= 8'd0;
- ddrphy_dq_o_data8[0] <= ddrphy_dfi_p0_wrdata[8];
- ddrphy_dq_o_data8[1] <= ddrphy_dfi_p0_wrdata[24];
- ddrphy_dq_o_data8[2] <= ddrphy_dfi_p0_wrdata[40];
- ddrphy_dq_o_data8[3] <= ddrphy_dfi_p0_wrdata[56];
- ddrphy_dq_o_data8[4] <= ddrphy_dfi_p1_wrdata[8];
- ddrphy_dq_o_data8[5] <= ddrphy_dfi_p1_wrdata[24];
- ddrphy_dq_o_data8[6] <= ddrphy_dfi_p1_wrdata[40];
- ddrphy_dq_o_data8[7] <= ddrphy_dfi_p1_wrdata[56];
+ ddrphy_dm_o_data1 <= 8'd0;
+ ddrphy_dm_o_data1[0] <= ddrphy_dfi_p0_wrdata_mask[0];
+ ddrphy_dm_o_data1[1] <= ddrphy_dfi_p0_wrdata_mask[2];
+ ddrphy_dm_o_data1[2] <= ddrphy_dfi_p0_wrdata_mask[4];
+ ddrphy_dm_o_data1[3] <= ddrphy_dfi_p0_wrdata_mask[6];
+ ddrphy_dm_o_data1[4] <= ddrphy_dfi_p1_wrdata_mask[0];
+ ddrphy_dm_o_data1[5] <= ddrphy_dfi_p1_wrdata_mask[2];
+ ddrphy_dm_o_data1[6] <= ddrphy_dfi_p1_wrdata_mask[4];
+ ddrphy_dm_o_data1[7] <= ddrphy_dfi_p1_wrdata_mask[6];
+end
+always @(*) begin
+ ddrphy_dq_o_data8 <= 8'd0;
+ ddrphy_dq_o_data8[0] <= ddrphy_dfi_p0_wrdata[8];
+ ddrphy_dq_o_data8[1] <= ddrphy_dfi_p0_wrdata[24];
+ ddrphy_dq_o_data8[2] <= ddrphy_dfi_p0_wrdata[40];
+ ddrphy_dq_o_data8[3] <= ddrphy_dfi_p0_wrdata[56];
+ ddrphy_dq_o_data8[4] <= ddrphy_dfi_p1_wrdata[8];
+ ddrphy_dq_o_data8[5] <= ddrphy_dfi_p1_wrdata[24];
+ ddrphy_dq_o_data8[6] <= ddrphy_dfi_p1_wrdata[40];
+ ddrphy_dq_o_data8[7] <= ddrphy_dfi_p1_wrdata[56];
end
assign ddrphy_dq_i_data8 = {ddrphy_bitslip8_o, ddrphy_dq_i_bitslip_o_d8};
always @(*) begin
- ddrphy_dq_o_data9 <= 8'd0;
- ddrphy_dq_o_data9[0] <= ddrphy_dfi_p0_wrdata[9];
- ddrphy_dq_o_data9[1] <= ddrphy_dfi_p0_wrdata[25];
- ddrphy_dq_o_data9[2] <= ddrphy_dfi_p0_wrdata[41];
- ddrphy_dq_o_data9[3] <= ddrphy_dfi_p0_wrdata[57];
- ddrphy_dq_o_data9[4] <= ddrphy_dfi_p1_wrdata[9];
- ddrphy_dq_o_data9[5] <= ddrphy_dfi_p1_wrdata[25];
- ddrphy_dq_o_data9[6] <= ddrphy_dfi_p1_wrdata[41];
- ddrphy_dq_o_data9[7] <= ddrphy_dfi_p1_wrdata[57];
+ ddrphy_dq_o_data9 <= 8'd0;
+ ddrphy_dq_o_data9[0] <= ddrphy_dfi_p0_wrdata[9];
+ ddrphy_dq_o_data9[1] <= ddrphy_dfi_p0_wrdata[25];
+ ddrphy_dq_o_data9[2] <= ddrphy_dfi_p0_wrdata[41];
+ ddrphy_dq_o_data9[3] <= ddrphy_dfi_p0_wrdata[57];
+ ddrphy_dq_o_data9[4] <= ddrphy_dfi_p1_wrdata[9];
+ ddrphy_dq_o_data9[5] <= ddrphy_dfi_p1_wrdata[25];
+ ddrphy_dq_o_data9[6] <= ddrphy_dfi_p1_wrdata[41];
+ ddrphy_dq_o_data9[7] <= ddrphy_dfi_p1_wrdata[57];
end
assign ddrphy_dq_i_data9 = {ddrphy_bitslip9_o, ddrphy_dq_i_bitslip_o_d9};
always @(*) begin
- ddrphy_dq_o_data10 <= 8'd0;
- ddrphy_dq_o_data10[0] <= ddrphy_dfi_p0_wrdata[10];
- ddrphy_dq_o_data10[1] <= ddrphy_dfi_p0_wrdata[26];
- ddrphy_dq_o_data10[2] <= ddrphy_dfi_p0_wrdata[42];
- ddrphy_dq_o_data10[3] <= ddrphy_dfi_p0_wrdata[58];
- ddrphy_dq_o_data10[4] <= ddrphy_dfi_p1_wrdata[10];
- ddrphy_dq_o_data10[5] <= ddrphy_dfi_p1_wrdata[26];
- ddrphy_dq_o_data10[6] <= ddrphy_dfi_p1_wrdata[42];
- ddrphy_dq_o_data10[7] <= ddrphy_dfi_p1_wrdata[58];
+ ddrphy_dq_o_data10 <= 8'd0;
+ ddrphy_dq_o_data10[0] <= ddrphy_dfi_p0_wrdata[10];
+ ddrphy_dq_o_data10[1] <= ddrphy_dfi_p0_wrdata[26];
+ ddrphy_dq_o_data10[2] <= ddrphy_dfi_p0_wrdata[42];
+ ddrphy_dq_o_data10[3] <= ddrphy_dfi_p0_wrdata[58];
+ ddrphy_dq_o_data10[4] <= ddrphy_dfi_p1_wrdata[10];
+ ddrphy_dq_o_data10[5] <= ddrphy_dfi_p1_wrdata[26];
+ ddrphy_dq_o_data10[6] <= ddrphy_dfi_p1_wrdata[42];
+ ddrphy_dq_o_data10[7] <= ddrphy_dfi_p1_wrdata[58];
end
assign ddrphy_dq_i_data10 = {ddrphy_bitslip10_o, ddrphy_dq_i_bitslip_o_d10};
always @(*) begin
- ddrphy_dq_o_data11 <= 8'd0;
- ddrphy_dq_o_data11[0] <= ddrphy_dfi_p0_wrdata[11];
- ddrphy_dq_o_data11[1] <= ddrphy_dfi_p0_wrdata[27];
- ddrphy_dq_o_data11[2] <= ddrphy_dfi_p0_wrdata[43];
- ddrphy_dq_o_data11[3] <= ddrphy_dfi_p0_wrdata[59];
- ddrphy_dq_o_data11[4] <= ddrphy_dfi_p1_wrdata[11];
- ddrphy_dq_o_data11[5] <= ddrphy_dfi_p1_wrdata[27];
- ddrphy_dq_o_data11[6] <= ddrphy_dfi_p1_wrdata[43];
- ddrphy_dq_o_data11[7] <= ddrphy_dfi_p1_wrdata[59];
+ ddrphy_dq_o_data11 <= 8'd0;
+ ddrphy_dq_o_data11[0] <= ddrphy_dfi_p0_wrdata[11];
+ ddrphy_dq_o_data11[1] <= ddrphy_dfi_p0_wrdata[27];
+ ddrphy_dq_o_data11[2] <= ddrphy_dfi_p0_wrdata[43];
+ ddrphy_dq_o_data11[3] <= ddrphy_dfi_p0_wrdata[59];
+ ddrphy_dq_o_data11[4] <= ddrphy_dfi_p1_wrdata[11];
+ ddrphy_dq_o_data11[5] <= ddrphy_dfi_p1_wrdata[27];
+ ddrphy_dq_o_data11[6] <= ddrphy_dfi_p1_wrdata[43];
+ ddrphy_dq_o_data11[7] <= ddrphy_dfi_p1_wrdata[59];
end
assign ddrphy_dq_i_data11 = {ddrphy_bitslip11_o, ddrphy_dq_i_bitslip_o_d11};
always @(*) begin
- ddrphy_dq_o_data12 <= 8'd0;
- ddrphy_dq_o_data12[0] <= ddrphy_dfi_p0_wrdata[12];
- ddrphy_dq_o_data12[1] <= ddrphy_dfi_p0_wrdata[28];
- ddrphy_dq_o_data12[2] <= ddrphy_dfi_p0_wrdata[44];
- ddrphy_dq_o_data12[3] <= ddrphy_dfi_p0_wrdata[60];
- ddrphy_dq_o_data12[4] <= ddrphy_dfi_p1_wrdata[12];
- ddrphy_dq_o_data12[5] <= ddrphy_dfi_p1_wrdata[28];
- ddrphy_dq_o_data12[6] <= ddrphy_dfi_p1_wrdata[44];
- ddrphy_dq_o_data12[7] <= ddrphy_dfi_p1_wrdata[60];
+ ddrphy_dq_o_data12 <= 8'd0;
+ ddrphy_dq_o_data12[0] <= ddrphy_dfi_p0_wrdata[12];
+ ddrphy_dq_o_data12[1] <= ddrphy_dfi_p0_wrdata[28];
+ ddrphy_dq_o_data12[2] <= ddrphy_dfi_p0_wrdata[44];
+ ddrphy_dq_o_data12[3] <= ddrphy_dfi_p0_wrdata[60];
+ ddrphy_dq_o_data12[4] <= ddrphy_dfi_p1_wrdata[12];
+ ddrphy_dq_o_data12[5] <= ddrphy_dfi_p1_wrdata[28];
+ ddrphy_dq_o_data12[6] <= ddrphy_dfi_p1_wrdata[44];
+ ddrphy_dq_o_data12[7] <= ddrphy_dfi_p1_wrdata[60];
end
assign ddrphy_dq_i_data12 = {ddrphy_bitslip12_o, ddrphy_dq_i_bitslip_o_d12};
always @(*) begin
- ddrphy_dq_o_data13 <= 8'd0;
- ddrphy_dq_o_data13[0] <= ddrphy_dfi_p0_wrdata[13];
- ddrphy_dq_o_data13[1] <= ddrphy_dfi_p0_wrdata[29];
- ddrphy_dq_o_data13[2] <= ddrphy_dfi_p0_wrdata[45];
- ddrphy_dq_o_data13[3] <= ddrphy_dfi_p0_wrdata[61];
- ddrphy_dq_o_data13[4] <= ddrphy_dfi_p1_wrdata[13];
- ddrphy_dq_o_data13[5] <= ddrphy_dfi_p1_wrdata[29];
- ddrphy_dq_o_data13[6] <= ddrphy_dfi_p1_wrdata[45];
- ddrphy_dq_o_data13[7] <= ddrphy_dfi_p1_wrdata[61];
+ ddrphy_dq_o_data13 <= 8'd0;
+ ddrphy_dq_o_data13[0] <= ddrphy_dfi_p0_wrdata[13];
+ ddrphy_dq_o_data13[1] <= ddrphy_dfi_p0_wrdata[29];
+ ddrphy_dq_o_data13[2] <= ddrphy_dfi_p0_wrdata[45];
+ ddrphy_dq_o_data13[3] <= ddrphy_dfi_p0_wrdata[61];
+ ddrphy_dq_o_data13[4] <= ddrphy_dfi_p1_wrdata[13];
+ ddrphy_dq_o_data13[5] <= ddrphy_dfi_p1_wrdata[29];
+ ddrphy_dq_o_data13[6] <= ddrphy_dfi_p1_wrdata[45];
+ ddrphy_dq_o_data13[7] <= ddrphy_dfi_p1_wrdata[61];
end
assign ddrphy_dq_i_data13 = {ddrphy_bitslip13_o, ddrphy_dq_i_bitslip_o_d13};
always @(*) begin
- ddrphy_dq_o_data14 <= 8'd0;
- ddrphy_dq_o_data14[0] <= ddrphy_dfi_p0_wrdata[14];
- ddrphy_dq_o_data14[1] <= ddrphy_dfi_p0_wrdata[30];
- ddrphy_dq_o_data14[2] <= ddrphy_dfi_p0_wrdata[46];
- ddrphy_dq_o_data14[3] <= ddrphy_dfi_p0_wrdata[62];
- ddrphy_dq_o_data14[4] <= ddrphy_dfi_p1_wrdata[14];
- ddrphy_dq_o_data14[5] <= ddrphy_dfi_p1_wrdata[30];
- ddrphy_dq_o_data14[6] <= ddrphy_dfi_p1_wrdata[46];
- ddrphy_dq_o_data14[7] <= ddrphy_dfi_p1_wrdata[62];
+ ddrphy_dq_o_data14 <= 8'd0;
+ ddrphy_dq_o_data14[0] <= ddrphy_dfi_p0_wrdata[14];
+ ddrphy_dq_o_data14[1] <= ddrphy_dfi_p0_wrdata[30];
+ ddrphy_dq_o_data14[2] <= ddrphy_dfi_p0_wrdata[46];
+ ddrphy_dq_o_data14[3] <= ddrphy_dfi_p0_wrdata[62];
+ ddrphy_dq_o_data14[4] <= ddrphy_dfi_p1_wrdata[14];
+ ddrphy_dq_o_data14[5] <= ddrphy_dfi_p1_wrdata[30];
+ ddrphy_dq_o_data14[6] <= ddrphy_dfi_p1_wrdata[46];
+ ddrphy_dq_o_data14[7] <= ddrphy_dfi_p1_wrdata[62];
end
assign ddrphy_dq_i_data14 = {ddrphy_bitslip14_o, ddrphy_dq_i_bitslip_o_d14};
always @(*) begin
- ddrphy_dq_o_data15 <= 8'd0;
- ddrphy_dq_o_data15[0] <= ddrphy_dfi_p0_wrdata[15];
- ddrphy_dq_o_data15[1] <= ddrphy_dfi_p0_wrdata[31];
- ddrphy_dq_o_data15[2] <= ddrphy_dfi_p0_wrdata[47];
- ddrphy_dq_o_data15[3] <= ddrphy_dfi_p0_wrdata[63];
- ddrphy_dq_o_data15[4] <= ddrphy_dfi_p1_wrdata[15];
- ddrphy_dq_o_data15[5] <= ddrphy_dfi_p1_wrdata[31];
- ddrphy_dq_o_data15[6] <= ddrphy_dfi_p1_wrdata[47];
- ddrphy_dq_o_data15[7] <= ddrphy_dfi_p1_wrdata[63];
+ ddrphy_dq_o_data15 <= 8'd0;
+ ddrphy_dq_o_data15[0] <= ddrphy_dfi_p0_wrdata[15];
+ ddrphy_dq_o_data15[1] <= ddrphy_dfi_p0_wrdata[31];
+ ddrphy_dq_o_data15[2] <= ddrphy_dfi_p0_wrdata[47];
+ ddrphy_dq_o_data15[3] <= ddrphy_dfi_p0_wrdata[63];
+ ddrphy_dq_o_data15[4] <= ddrphy_dfi_p1_wrdata[15];
+ ddrphy_dq_o_data15[5] <= ddrphy_dfi_p1_wrdata[31];
+ ddrphy_dq_o_data15[6] <= ddrphy_dfi_p1_wrdata[47];
+ ddrphy_dq_o_data15[7] <= ddrphy_dfi_p1_wrdata[63];
end
assign ddrphy_dq_i_data15 = {ddrphy_bitslip15_o, ddrphy_dq_i_bitslip_o_d15};
assign ddrphy_dfi_p0_rddata_valid = ddrphy_rddata_en_tappeddelayline12;
assign ddrphy_delay0 = ddrphy_delay1;
assign ddrphy_reset0 = ddrphy_reset1;
always @(*) begin
- ddrphy_bitslip0_o <= 4'd0;
- case (ddrphy_bitslip0_value)
- 1'd0: begin
- ddrphy_bitslip0_o <= ddrphy_bitslip0_r[3:0];
- end
- 1'd1: begin
- ddrphy_bitslip0_o <= ddrphy_bitslip0_r[4:1];
- end
- 2'd2: begin
- ddrphy_bitslip0_o <= ddrphy_bitslip0_r[5:2];
- end
- 2'd3: begin
- ddrphy_bitslip0_o <= ddrphy_bitslip0_r[6:3];
- end
- endcase
-end
-always @(*) begin
- ddrphy_bitslip1_o <= 4'd0;
- case (ddrphy_bitslip1_value)
- 1'd0: begin
- ddrphy_bitslip1_o <= ddrphy_bitslip1_r[3:0];
- end
- 1'd1: begin
- ddrphy_bitslip1_o <= ddrphy_bitslip1_r[4:1];
- end
- 2'd2: begin
- ddrphy_bitslip1_o <= ddrphy_bitslip1_r[5:2];
- end
- 2'd3: begin
- ddrphy_bitslip1_o <= ddrphy_bitslip1_r[6:3];
- end
- endcase
-end
-always @(*) begin
- ddrphy_bitslip2_o <= 4'd0;
- case (ddrphy_bitslip2_value)
- 1'd0: begin
- ddrphy_bitslip2_o <= ddrphy_bitslip2_r[3:0];
- end
- 1'd1: begin
- ddrphy_bitslip2_o <= ddrphy_bitslip2_r[4:1];
- end
- 2'd2: begin
- ddrphy_bitslip2_o <= ddrphy_bitslip2_r[5:2];
- end
- 2'd3: begin
- ddrphy_bitslip2_o <= ddrphy_bitslip2_r[6:3];
- end
- endcase
-end
-always @(*) begin
- ddrphy_bitslip3_o <= 4'd0;
- case (ddrphy_bitslip3_value)
- 1'd0: begin
- ddrphy_bitslip3_o <= ddrphy_bitslip3_r[3:0];
- end
- 1'd1: begin
- ddrphy_bitslip3_o <= ddrphy_bitslip3_r[4:1];
- end
- 2'd2: begin
- ddrphy_bitslip3_o <= ddrphy_bitslip3_r[5:2];
- end
- 2'd3: begin
- ddrphy_bitslip3_o <= ddrphy_bitslip3_r[6:3];
- end
- endcase
-end
-always @(*) begin
- ddrphy_bitslip4_o <= 4'd0;
- case (ddrphy_bitslip4_value)
- 1'd0: begin
- ddrphy_bitslip4_o <= ddrphy_bitslip4_r[3:0];
- end
- 1'd1: begin
- ddrphy_bitslip4_o <= ddrphy_bitslip4_r[4:1];
- end
- 2'd2: begin
- ddrphy_bitslip4_o <= ddrphy_bitslip4_r[5:2];
- end
- 2'd3: begin
- ddrphy_bitslip4_o <= ddrphy_bitslip4_r[6:3];
- end
- endcase
-end
-always @(*) begin
- ddrphy_bitslip5_o <= 4'd0;
- case (ddrphy_bitslip5_value)
- 1'd0: begin
- ddrphy_bitslip5_o <= ddrphy_bitslip5_r[3:0];
- end
- 1'd1: begin
- ddrphy_bitslip5_o <= ddrphy_bitslip5_r[4:1];
- end
- 2'd2: begin
- ddrphy_bitslip5_o <= ddrphy_bitslip5_r[5:2];
- end
- 2'd3: begin
- ddrphy_bitslip5_o <= ddrphy_bitslip5_r[6:3];
- end
- endcase
-end
-always @(*) begin
- ddrphy_bitslip6_o <= 4'd0;
- case (ddrphy_bitslip6_value)
- 1'd0: begin
- ddrphy_bitslip6_o <= ddrphy_bitslip6_r[3:0];
- end
- 1'd1: begin
- ddrphy_bitslip6_o <= ddrphy_bitslip6_r[4:1];
- end
- 2'd2: begin
- ddrphy_bitslip6_o <= ddrphy_bitslip6_r[5:2];
- end
- 2'd3: begin
- ddrphy_bitslip6_o <= ddrphy_bitslip6_r[6:3];
- end
- endcase
-end
-always @(*) begin
- ddrphy_bitslip7_o <= 4'd0;
- case (ddrphy_bitslip7_value)
- 1'd0: begin
- ddrphy_bitslip7_o <= ddrphy_bitslip7_r[3:0];
- end
- 1'd1: begin
- ddrphy_bitslip7_o <= ddrphy_bitslip7_r[4:1];
- end
- 2'd2: begin
- ddrphy_bitslip7_o <= ddrphy_bitslip7_r[5:2];
- end
- 2'd3: begin
- ddrphy_bitslip7_o <= ddrphy_bitslip7_r[6:3];
- end
- endcase
-end
-always @(*) begin
- ddrphy_bitslip8_o <= 4'd0;
- case (ddrphy_bitslip8_value)
- 1'd0: begin
- ddrphy_bitslip8_o <= ddrphy_bitslip8_r[3:0];
- end
- 1'd1: begin
- ddrphy_bitslip8_o <= ddrphy_bitslip8_r[4:1];
- end
- 2'd2: begin
- ddrphy_bitslip8_o <= ddrphy_bitslip8_r[5:2];
- end
- 2'd3: begin
- ddrphy_bitslip8_o <= ddrphy_bitslip8_r[6:3];
- end
- endcase
-end
-always @(*) begin
- ddrphy_bitslip9_o <= 4'd0;
- case (ddrphy_bitslip9_value)
- 1'd0: begin
- ddrphy_bitslip9_o <= ddrphy_bitslip9_r[3:0];
- end
- 1'd1: begin
- ddrphy_bitslip9_o <= ddrphy_bitslip9_r[4:1];
- end
- 2'd2: begin
- ddrphy_bitslip9_o <= ddrphy_bitslip9_r[5:2];
- end
- 2'd3: begin
- ddrphy_bitslip9_o <= ddrphy_bitslip9_r[6:3];
- end
- endcase
-end
-always @(*) begin
- ddrphy_bitslip10_o <= 4'd0;
- case (ddrphy_bitslip10_value)
- 1'd0: begin
- ddrphy_bitslip10_o <= ddrphy_bitslip10_r[3:0];
- end
- 1'd1: begin
- ddrphy_bitslip10_o <= ddrphy_bitslip10_r[4:1];
- end
- 2'd2: begin
- ddrphy_bitslip10_o <= ddrphy_bitslip10_r[5:2];
- end
- 2'd3: begin
- ddrphy_bitslip10_o <= ddrphy_bitslip10_r[6:3];
- end
- endcase
-end
-always @(*) begin
- ddrphy_bitslip11_o <= 4'd0;
- case (ddrphy_bitslip11_value)
- 1'd0: begin
- ddrphy_bitslip11_o <= ddrphy_bitslip11_r[3:0];
- end
- 1'd1: begin
- ddrphy_bitslip11_o <= ddrphy_bitslip11_r[4:1];
- end
- 2'd2: begin
- ddrphy_bitslip11_o <= ddrphy_bitslip11_r[5:2];
- end
- 2'd3: begin
- ddrphy_bitslip11_o <= ddrphy_bitslip11_r[6:3];
- end
- endcase
-end
-always @(*) begin
- ddrphy_bitslip12_o <= 4'd0;
- case (ddrphy_bitslip12_value)
- 1'd0: begin
- ddrphy_bitslip12_o <= ddrphy_bitslip12_r[3:0];
- end
- 1'd1: begin
- ddrphy_bitslip12_o <= ddrphy_bitslip12_r[4:1];
- end
- 2'd2: begin
- ddrphy_bitslip12_o <= ddrphy_bitslip12_r[5:2];
- end
- 2'd3: begin
- ddrphy_bitslip12_o <= ddrphy_bitslip12_r[6:3];
- end
- endcase
-end
-always @(*) begin
- ddrphy_bitslip13_o <= 4'd0;
- case (ddrphy_bitslip13_value)
- 1'd0: begin
- ddrphy_bitslip13_o <= ddrphy_bitslip13_r[3:0];
- end
- 1'd1: begin
- ddrphy_bitslip13_o <= ddrphy_bitslip13_r[4:1];
- end
- 2'd2: begin
- ddrphy_bitslip13_o <= ddrphy_bitslip13_r[5:2];
- end
- 2'd3: begin
- ddrphy_bitslip13_o <= ddrphy_bitslip13_r[6:3];
- end
- endcase
-end
-always @(*) begin
- ddrphy_bitslip14_o <= 4'd0;
- case (ddrphy_bitslip14_value)
- 1'd0: begin
- ddrphy_bitslip14_o <= ddrphy_bitslip14_r[3:0];
- end
- 1'd1: begin
- ddrphy_bitslip14_o <= ddrphy_bitslip14_r[4:1];
- end
- 2'd2: begin
- ddrphy_bitslip14_o <= ddrphy_bitslip14_r[5:2];
- end
- 2'd3: begin
- ddrphy_bitslip14_o <= ddrphy_bitslip14_r[6:3];
- end
- endcase
-end
-always @(*) begin
- ddrphy_bitslip15_o <= 4'd0;
- case (ddrphy_bitslip15_value)
- 1'd0: begin
- ddrphy_bitslip15_o <= ddrphy_bitslip15_r[3:0];
- end
- 1'd1: begin
- ddrphy_bitslip15_o <= ddrphy_bitslip15_r[4:1];
- end
- 2'd2: begin
- ddrphy_bitslip15_o <= ddrphy_bitslip15_r[5:2];
- end
- 2'd3: begin
- ddrphy_bitslip15_o <= ddrphy_bitslip15_r[6:3];
- end
- endcase
+ ddrphy_bitslip0_o <= 4'd0;
+ case (ddrphy_bitslip0_value)
+ 1'd0: begin
+ ddrphy_bitslip0_o <= ddrphy_bitslip0_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip0_o <= ddrphy_bitslip0_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip0_o <= ddrphy_bitslip0_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip0_o <= ddrphy_bitslip0_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip1_o <= 4'd0;
+ case (ddrphy_bitslip1_value)
+ 1'd0: begin
+ ddrphy_bitslip1_o <= ddrphy_bitslip1_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip1_o <= ddrphy_bitslip1_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip1_o <= ddrphy_bitslip1_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip1_o <= ddrphy_bitslip1_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip2_o <= 4'd0;
+ case (ddrphy_bitslip2_value)
+ 1'd0: begin
+ ddrphy_bitslip2_o <= ddrphy_bitslip2_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip2_o <= ddrphy_bitslip2_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip2_o <= ddrphy_bitslip2_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip2_o <= ddrphy_bitslip2_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip3_o <= 4'd0;
+ case (ddrphy_bitslip3_value)
+ 1'd0: begin
+ ddrphy_bitslip3_o <= ddrphy_bitslip3_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip3_o <= ddrphy_bitslip3_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip3_o <= ddrphy_bitslip3_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip3_o <= ddrphy_bitslip3_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip4_o <= 4'd0;
+ case (ddrphy_bitslip4_value)
+ 1'd0: begin
+ ddrphy_bitslip4_o <= ddrphy_bitslip4_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip4_o <= ddrphy_bitslip4_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip4_o <= ddrphy_bitslip4_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip4_o <= ddrphy_bitslip4_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip5_o <= 4'd0;
+ case (ddrphy_bitslip5_value)
+ 1'd0: begin
+ ddrphy_bitslip5_o <= ddrphy_bitslip5_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip5_o <= ddrphy_bitslip5_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip5_o <= ddrphy_bitslip5_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip5_o <= ddrphy_bitslip5_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip6_o <= 4'd0;
+ case (ddrphy_bitslip6_value)
+ 1'd0: begin
+ ddrphy_bitslip6_o <= ddrphy_bitslip6_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip6_o <= ddrphy_bitslip6_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip6_o <= ddrphy_bitslip6_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip6_o <= ddrphy_bitslip6_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip7_o <= 4'd0;
+ case (ddrphy_bitslip7_value)
+ 1'd0: begin
+ ddrphy_bitslip7_o <= ddrphy_bitslip7_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip7_o <= ddrphy_bitslip7_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip7_o <= ddrphy_bitslip7_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip7_o <= ddrphy_bitslip7_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip8_o <= 4'd0;
+ case (ddrphy_bitslip8_value)
+ 1'd0: begin
+ ddrphy_bitslip8_o <= ddrphy_bitslip8_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip8_o <= ddrphy_bitslip8_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip8_o <= ddrphy_bitslip8_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip8_o <= ddrphy_bitslip8_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip9_o <= 4'd0;
+ case (ddrphy_bitslip9_value)
+ 1'd0: begin
+ ddrphy_bitslip9_o <= ddrphy_bitslip9_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip9_o <= ddrphy_bitslip9_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip9_o <= ddrphy_bitslip9_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip9_o <= ddrphy_bitslip9_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip10_o <= 4'd0;
+ case (ddrphy_bitslip10_value)
+ 1'd0: begin
+ ddrphy_bitslip10_o <= ddrphy_bitslip10_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip10_o <= ddrphy_bitslip10_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip10_o <= ddrphy_bitslip10_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip10_o <= ddrphy_bitslip10_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip11_o <= 4'd0;
+ case (ddrphy_bitslip11_value)
+ 1'd0: begin
+ ddrphy_bitslip11_o <= ddrphy_bitslip11_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip11_o <= ddrphy_bitslip11_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip11_o <= ddrphy_bitslip11_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip11_o <= ddrphy_bitslip11_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip12_o <= 4'd0;
+ case (ddrphy_bitslip12_value)
+ 1'd0: begin
+ ddrphy_bitslip12_o <= ddrphy_bitslip12_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip12_o <= ddrphy_bitslip12_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip12_o <= ddrphy_bitslip12_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip12_o <= ddrphy_bitslip12_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip13_o <= 4'd0;
+ case (ddrphy_bitslip13_value)
+ 1'd0: begin
+ ddrphy_bitslip13_o <= ddrphy_bitslip13_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip13_o <= ddrphy_bitslip13_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip13_o <= ddrphy_bitslip13_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip13_o <= ddrphy_bitslip13_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip14_o <= 4'd0;
+ case (ddrphy_bitslip14_value)
+ 1'd0: begin
+ ddrphy_bitslip14_o <= ddrphy_bitslip14_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip14_o <= ddrphy_bitslip14_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip14_o <= ddrphy_bitslip14_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip14_o <= ddrphy_bitslip14_r[6:3];
+ end
+ endcase
+end
+always @(*) begin
+ ddrphy_bitslip15_o <= 4'd0;
+ case (ddrphy_bitslip15_value)
+ 1'd0: begin
+ ddrphy_bitslip15_o <= ddrphy_bitslip15_r[3:0];
+ end
+ 1'd1: begin
+ ddrphy_bitslip15_o <= ddrphy_bitslip15_r[4:1];
+ end
+ 2'd2: begin
+ ddrphy_bitslip15_o <= ddrphy_bitslip15_r[5:2];
+ end
+ 2'd3: begin
+ ddrphy_bitslip15_o <= ddrphy_bitslip15_r[6:3];
+ end
+ endcase
end
assign ddrphy_dfi_p0_address = litedramcore_master_p0_address;
assign ddrphy_dfi_p0_bank = litedramcore_master_p0_bank;
assign litedramcore_dfi_p1_rddata = litedramcore_slave_p1_rddata;
assign litedramcore_dfi_p1_rddata_valid = litedramcore_slave_p1_rddata_valid;
always @(*) begin
- litedramcore_master_p0_cs_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n;
- end else begin
- litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n;
- end
- end else begin
- litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n;
- end
-end
-always @(*) begin
- litedramcore_csr_dfi_p1_rddata <= 64'd0;
- if (litedramcore_sel) begin
- end else begin
- litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata;
- end
-end
-always @(*) begin
- litedramcore_master_p0_ras_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n;
- end else begin
- litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n;
- end
- end else begin
- litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n;
- end
-end
-always @(*) begin
- litedramcore_csr_dfi_p1_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- end else begin
- litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
- end
-end
-always @(*) begin
- litedramcore_master_p0_we_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n;
- end else begin
- litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n;
- end
- end else begin
- litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n;
- end
-end
-always @(*) begin
- litedramcore_master_p0_cke <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_cke <= litedramcore_ext_dfi_p0_cke;
- end else begin
- litedramcore_master_p0_cke <= litedramcore_slave_p0_cke;
- end
- end else begin
- litedramcore_master_p0_cke <= litedramcore_csr_dfi_p0_cke;
- end
-end
-always @(*) begin
- litedramcore_master_p0_odt <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_odt <= litedramcore_ext_dfi_p0_odt;
- end else begin
- litedramcore_master_p0_odt <= litedramcore_slave_p0_odt;
- end
- end else begin
- litedramcore_master_p0_odt <= litedramcore_csr_dfi_p0_odt;
- end
-end
-always @(*) begin
- litedramcore_master_p0_reset_n <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_reset_n <= litedramcore_ext_dfi_p0_reset_n;
- end else begin
- litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n;
- end
- end else begin
- litedramcore_master_p0_reset_n <= litedramcore_csr_dfi_p0_reset_n;
- end
-end
-always @(*) begin
- litedramcore_master_p0_act_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_act_n <= litedramcore_ext_dfi_p0_act_n;
- end else begin
- litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n;
- end
- end else begin
- litedramcore_master_p0_act_n <= litedramcore_csr_dfi_p0_act_n;
- end
-end
-always @(*) begin
- litedramcore_master_p0_wrdata <= 64'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_wrdata <= litedramcore_ext_dfi_p0_wrdata;
- end else begin
- litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata;
- end
- end else begin
- litedramcore_master_p0_wrdata <= litedramcore_csr_dfi_p0_wrdata;
- end
-end
-always @(*) begin
- litedramcore_master_p0_wrdata_en <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_wrdata_en <= litedramcore_ext_dfi_p0_wrdata_en;
- end else begin
- litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en;
- end
- end else begin
- litedramcore_master_p0_wrdata_en <= litedramcore_csr_dfi_p0_wrdata_en;
- end
-end
-always @(*) begin
- litedramcore_master_p0_wrdata_mask <= 8'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_wrdata_mask <= litedramcore_ext_dfi_p0_wrdata_mask;
- end else begin
- litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask;
- end
- end else begin
- litedramcore_master_p0_wrdata_mask <= litedramcore_csr_dfi_p0_wrdata_mask;
- end
-end
-always @(*) begin
- litedramcore_master_p0_rddata_en <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_rddata_en <= litedramcore_ext_dfi_p0_rddata_en;
- end else begin
- litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en;
- end
- end else begin
- litedramcore_master_p0_rddata_en <= litedramcore_csr_dfi_p0_rddata_en;
- end
-end
-always @(*) begin
- litedramcore_master_p1_address <= 15'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_address <= litedramcore_ext_dfi_p1_address;
- end else begin
- litedramcore_master_p1_address <= litedramcore_slave_p1_address;
- end
- end else begin
- litedramcore_master_p1_address <= litedramcore_csr_dfi_p1_address;
- end
-end
-always @(*) begin
- litedramcore_master_p1_bank <= 3'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_bank <= litedramcore_ext_dfi_p1_bank;
- end else begin
- litedramcore_master_p1_bank <= litedramcore_slave_p1_bank;
- end
- end else begin
- litedramcore_master_p1_bank <= litedramcore_csr_dfi_p1_bank;
- end
-end
-always @(*) begin
- litedramcore_master_p1_cas_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_cas_n <= litedramcore_ext_dfi_p1_cas_n;
- end else begin
- litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n;
- end
- end else begin
- litedramcore_master_p1_cas_n <= litedramcore_csr_dfi_p1_cas_n;
- end
-end
-always @(*) begin
- litedramcore_master_p1_cs_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_cs_n <= litedramcore_ext_dfi_p1_cs_n;
- end else begin
- litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n;
- end
- end else begin
- litedramcore_master_p1_cs_n <= litedramcore_csr_dfi_p1_cs_n;
- end
-end
-always @(*) begin
- litedramcore_master_p1_ras_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_ras_n <= litedramcore_ext_dfi_p1_ras_n;
- end else begin
- litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n;
- end
- end else begin
- litedramcore_master_p1_ras_n <= litedramcore_csr_dfi_p1_ras_n;
- end
-end
-always @(*) begin
- litedramcore_master_p1_we_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_we_n <= litedramcore_ext_dfi_p1_we_n;
- end else begin
- litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n;
- end
- end else begin
- litedramcore_master_p1_we_n <= litedramcore_csr_dfi_p1_we_n;
- end
-end
-always @(*) begin
- litedramcore_master_p1_cke <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_cke <= litedramcore_ext_dfi_p1_cke;
- end else begin
- litedramcore_master_p1_cke <= litedramcore_slave_p1_cke;
- end
- end else begin
- litedramcore_master_p1_cke <= litedramcore_csr_dfi_p1_cke;
- end
-end
-always @(*) begin
- litedramcore_master_p1_odt <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_odt <= litedramcore_ext_dfi_p1_odt;
- end else begin
- litedramcore_master_p1_odt <= litedramcore_slave_p1_odt;
- end
- end else begin
- litedramcore_master_p1_odt <= litedramcore_csr_dfi_p1_odt;
- end
-end
-always @(*) begin
- litedramcore_ext_dfi_p0_rddata <= 64'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_ext_dfi_p0_rddata <= litedramcore_master_p0_rddata;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_master_p1_reset_n <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_reset_n <= litedramcore_ext_dfi_p1_reset_n;
- end else begin
- litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n;
- end
- end else begin
- litedramcore_master_p1_reset_n <= litedramcore_csr_dfi_p1_reset_n;
- end
-end
-always @(*) begin
- litedramcore_ext_dfi_p0_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_ext_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_master_p1_act_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_act_n <= litedramcore_ext_dfi_p1_act_n;
- end else begin
- litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n;
- end
- end else begin
- litedramcore_master_p1_act_n <= litedramcore_csr_dfi_p1_act_n;
- end
-end
-always @(*) begin
- litedramcore_master_p1_wrdata <= 64'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_wrdata <= litedramcore_ext_dfi_p1_wrdata;
- end else begin
- litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata;
- end
- end else begin
- litedramcore_master_p1_wrdata <= litedramcore_csr_dfi_p1_wrdata;
- end
-end
-always @(*) begin
- litedramcore_master_p1_wrdata_en <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_wrdata_en <= litedramcore_ext_dfi_p1_wrdata_en;
- end else begin
- litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en;
- end
- end else begin
- litedramcore_master_p1_wrdata_en <= litedramcore_csr_dfi_p1_wrdata_en;
- end
-end
-always @(*) begin
- litedramcore_master_p1_wrdata_mask <= 8'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_wrdata_mask <= litedramcore_ext_dfi_p1_wrdata_mask;
- end else begin
- litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask;
- end
- end else begin
- litedramcore_master_p1_wrdata_mask <= litedramcore_csr_dfi_p1_wrdata_mask;
- end
-end
-always @(*) begin
- litedramcore_master_p1_rddata_en <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_rddata_en <= litedramcore_ext_dfi_p1_rddata_en;
- end else begin
- litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en;
- end
- end else begin
- litedramcore_master_p1_rddata_en <= litedramcore_csr_dfi_p1_rddata_en;
- end
-end
-always @(*) begin
- litedramcore_ext_dfi_p1_rddata <= 64'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_ext_dfi_p1_rddata <= litedramcore_master_p1_rddata;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_ext_dfi_p1_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_ext_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_slave_p0_rddata <= 64'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- end else begin
- litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata;
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_slave_p0_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- end else begin
- litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_csr_dfi_p0_rddata <= 64'd0;
- if (litedramcore_sel) begin
- end else begin
- litedramcore_csr_dfi_p0_rddata <= litedramcore_master_p0_rddata;
- end
-end
-always @(*) begin
- litedramcore_csr_dfi_p0_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- end else begin
- litedramcore_csr_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
- end
-end
-always @(*) begin
- litedramcore_slave_p1_rddata <= 64'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- end else begin
- litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata;
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_slave_p1_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- end else begin
- litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_master_p0_address <= 15'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_address <= litedramcore_ext_dfi_p0_address;
- end else begin
- litedramcore_master_p0_address <= litedramcore_slave_p0_address;
- end
- end else begin
- litedramcore_master_p0_address <= litedramcore_csr_dfi_p0_address;
- end
-end
-always @(*) begin
- litedramcore_master_p0_bank <= 3'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_bank <= litedramcore_ext_dfi_p0_bank;
- end else begin
- litedramcore_master_p0_bank <= litedramcore_slave_p0_bank;
- end
- end else begin
- litedramcore_master_p0_bank <= litedramcore_csr_dfi_p0_bank;
- end
-end
-always @(*) begin
- litedramcore_master_p0_cas_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_cas_n <= litedramcore_ext_dfi_p0_cas_n;
- end else begin
- litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n;
- end
- end else begin
- litedramcore_master_p0_cas_n <= litedramcore_csr_dfi_p0_cas_n;
- end
+ litedramcore_master_p0_cs_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n;
+ end else begin
+ litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n;
+ end
+ end else begin
+ litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n;
+ end
+end
+always @(*) begin
+ litedramcore_csr_dfi_p1_rddata <= 64'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_ras_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n;
+ end else begin
+ litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n;
+ end
+ end else begin
+ litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n;
+ end
+end
+always @(*) begin
+ litedramcore_csr_dfi_p1_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_we_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n;
+ end else begin
+ litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n;
+ end
+ end else begin
+ litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_cke <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_cke <= litedramcore_ext_dfi_p0_cke;
+ end else begin
+ litedramcore_master_p0_cke <= litedramcore_slave_p0_cke;
+ end
+ end else begin
+ litedramcore_master_p0_cke <= litedramcore_csr_dfi_p0_cke;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_odt <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_odt <= litedramcore_ext_dfi_p0_odt;
+ end else begin
+ litedramcore_master_p0_odt <= litedramcore_slave_p0_odt;
+ end
+ end else begin
+ litedramcore_master_p0_odt <= litedramcore_csr_dfi_p0_odt;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_reset_n <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_reset_n <= litedramcore_ext_dfi_p0_reset_n;
+ end else begin
+ litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n;
+ end
+ end else begin
+ litedramcore_master_p0_reset_n <= litedramcore_csr_dfi_p0_reset_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_act_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_act_n <= litedramcore_ext_dfi_p0_act_n;
+ end else begin
+ litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n;
+ end
+ end else begin
+ litedramcore_master_p0_act_n <= litedramcore_csr_dfi_p0_act_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_wrdata <= 64'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_wrdata <= litedramcore_ext_dfi_p0_wrdata;
+ end else begin
+ litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata;
+ end
+ end else begin
+ litedramcore_master_p0_wrdata <= litedramcore_csr_dfi_p0_wrdata;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_wrdata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_wrdata_en <= litedramcore_ext_dfi_p0_wrdata_en;
+ end else begin
+ litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en;
+ end
+ end else begin
+ litedramcore_master_p0_wrdata_en <= litedramcore_csr_dfi_p0_wrdata_en;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_wrdata_mask <= 8'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_wrdata_mask <= litedramcore_ext_dfi_p0_wrdata_mask;
+ end else begin
+ litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask;
+ end
+ end else begin
+ litedramcore_master_p0_wrdata_mask <= litedramcore_csr_dfi_p0_wrdata_mask;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_rddata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_rddata_en <= litedramcore_ext_dfi_p0_rddata_en;
+ end else begin
+ litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en;
+ end
+ end else begin
+ litedramcore_master_p0_rddata_en <= litedramcore_csr_dfi_p0_rddata_en;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_address <= 15'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_address <= litedramcore_ext_dfi_p1_address;
+ end else begin
+ litedramcore_master_p1_address <= litedramcore_slave_p1_address;
+ end
+ end else begin
+ litedramcore_master_p1_address <= litedramcore_csr_dfi_p1_address;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_bank <= 3'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_bank <= litedramcore_ext_dfi_p1_bank;
+ end else begin
+ litedramcore_master_p1_bank <= litedramcore_slave_p1_bank;
+ end
+ end else begin
+ litedramcore_master_p1_bank <= litedramcore_csr_dfi_p1_bank;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_cas_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_cas_n <= litedramcore_ext_dfi_p1_cas_n;
+ end else begin
+ litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n;
+ end
+ end else begin
+ litedramcore_master_p1_cas_n <= litedramcore_csr_dfi_p1_cas_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_cs_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_cs_n <= litedramcore_ext_dfi_p1_cs_n;
+ end else begin
+ litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n;
+ end
+ end else begin
+ litedramcore_master_p1_cs_n <= litedramcore_csr_dfi_p1_cs_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_ras_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_ras_n <= litedramcore_ext_dfi_p1_ras_n;
+ end else begin
+ litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n;
+ end
+ end else begin
+ litedramcore_master_p1_ras_n <= litedramcore_csr_dfi_p1_ras_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_we_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_we_n <= litedramcore_ext_dfi_p1_we_n;
+ end else begin
+ litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n;
+ end
+ end else begin
+ litedramcore_master_p1_we_n <= litedramcore_csr_dfi_p1_we_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_cke <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_cke <= litedramcore_ext_dfi_p1_cke;
+ end else begin
+ litedramcore_master_p1_cke <= litedramcore_slave_p1_cke;
+ end
+ end else begin
+ litedramcore_master_p1_cke <= litedramcore_csr_dfi_p1_cke;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_odt <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_odt <= litedramcore_ext_dfi_p1_odt;
+ end else begin
+ litedramcore_master_p1_odt <= litedramcore_slave_p1_odt;
+ end
+ end else begin
+ litedramcore_master_p1_odt <= litedramcore_csr_dfi_p1_odt;
+ end
+end
+always @(*) begin
+ litedramcore_ext_dfi_p0_rddata <= 64'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_ext_dfi_p0_rddata <= litedramcore_master_p0_rddata;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_reset_n <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_reset_n <= litedramcore_ext_dfi_p1_reset_n;
+ end else begin
+ litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n;
+ end
+ end else begin
+ litedramcore_master_p1_reset_n <= litedramcore_csr_dfi_p1_reset_n;
+ end
+end
+always @(*) begin
+ litedramcore_ext_dfi_p0_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_ext_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_act_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_act_n <= litedramcore_ext_dfi_p1_act_n;
+ end else begin
+ litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n;
+ end
+ end else begin
+ litedramcore_master_p1_act_n <= litedramcore_csr_dfi_p1_act_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_wrdata <= 64'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_wrdata <= litedramcore_ext_dfi_p1_wrdata;
+ end else begin
+ litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata;
+ end
+ end else begin
+ litedramcore_master_p1_wrdata <= litedramcore_csr_dfi_p1_wrdata;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_wrdata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_wrdata_en <= litedramcore_ext_dfi_p1_wrdata_en;
+ end else begin
+ litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en;
+ end
+ end else begin
+ litedramcore_master_p1_wrdata_en <= litedramcore_csr_dfi_p1_wrdata_en;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_wrdata_mask <= 8'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_wrdata_mask <= litedramcore_ext_dfi_p1_wrdata_mask;
+ end else begin
+ litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask;
+ end
+ end else begin
+ litedramcore_master_p1_wrdata_mask <= litedramcore_csr_dfi_p1_wrdata_mask;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_rddata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_rddata_en <= litedramcore_ext_dfi_p1_rddata_en;
+ end else begin
+ litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en;
+ end
+ end else begin
+ litedramcore_master_p1_rddata_en <= litedramcore_csr_dfi_p1_rddata_en;
+ end
+end
+always @(*) begin
+ litedramcore_ext_dfi_p1_rddata <= 64'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_ext_dfi_p1_rddata <= litedramcore_master_p1_rddata;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_ext_dfi_p1_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_ext_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p0_rddata <= 64'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ end else begin
+ litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p0_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ end else begin
+ litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_csr_dfi_p0_rddata <= 64'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_csr_dfi_p0_rddata <= litedramcore_master_p0_rddata;
+ end
+end
+always @(*) begin
+ litedramcore_csr_dfi_p0_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_csr_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+ end
+end
+always @(*) begin
+ litedramcore_slave_p1_rddata <= 64'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ end else begin
+ litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p1_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ end else begin
+ litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_address <= 15'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_address <= litedramcore_ext_dfi_p0_address;
+ end else begin
+ litedramcore_master_p0_address <= litedramcore_slave_p0_address;
+ end
+ end else begin
+ litedramcore_master_p0_address <= litedramcore_csr_dfi_p0_address;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_bank <= 3'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_bank <= litedramcore_ext_dfi_p0_bank;
+ end else begin
+ litedramcore_master_p0_bank <= litedramcore_slave_p0_bank;
+ end
+ end else begin
+ litedramcore_master_p0_bank <= litedramcore_csr_dfi_p0_bank;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_cas_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_cas_n <= litedramcore_ext_dfi_p0_cas_n;
+ end else begin
+ litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n;
+ end
+ end else begin
+ litedramcore_master_p0_cas_n <= litedramcore_csr_dfi_p0_cas_n;
+ end
end
assign litedramcore_csr_dfi_p0_cke = litedramcore_cke;
assign litedramcore_csr_dfi_p1_cke = litedramcore_cke;
assign litedramcore_csr_dfi_p0_reset_n = litedramcore_reset_n;
assign litedramcore_csr_dfi_p1_reset_n = litedramcore_reset_n;
always @(*) begin
- litedramcore_csr_dfi_p0_cas_n <= 1'd1;
- if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_csr_dfi_p0_cas_n <= (~litedramcore_phaseinjector0_csrfield_cas);
- end else begin
- litedramcore_csr_dfi_p0_cas_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p0_cas_n <= 1'd1;
+ if (litedramcore_phaseinjector0_command_issue_re) begin
+ litedramcore_csr_dfi_p0_cas_n <= (~litedramcore_phaseinjector0_csrfield_cas);
+ end else begin
+ litedramcore_csr_dfi_p0_cas_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p0_cs_n <= 1'd1;
- if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}};
- end else begin
- litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}};
- end
+ litedramcore_csr_dfi_p0_cs_n <= 1'd1;
+ if (litedramcore_phaseinjector0_command_issue_re) begin
+ litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}};
+ end else begin
+ litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}};
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p0_ras_n <= 1'd1;
- if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_csr_dfi_p0_ras_n <= (~litedramcore_phaseinjector0_csrfield_ras);
- end else begin
- litedramcore_csr_dfi_p0_ras_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p0_ras_n <= 1'd1;
+ if (litedramcore_phaseinjector0_command_issue_re) begin
+ litedramcore_csr_dfi_p0_ras_n <= (~litedramcore_phaseinjector0_csrfield_ras);
+ end else begin
+ litedramcore_csr_dfi_p0_ras_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p0_we_n <= 1'd1;
- if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we);
- end else begin
- litedramcore_csr_dfi_p0_we_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p0_we_n <= 1'd1;
+ if (litedramcore_phaseinjector0_command_issue_re) begin
+ litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we);
+ end else begin
+ litedramcore_csr_dfi_p0_we_n <= 1'd1;
+ end
end
assign litedramcore_csr_dfi_p0_address = litedramcore_phaseinjector0_address_storage;
assign litedramcore_csr_dfi_p0_bank = litedramcore_phaseinjector0_baddress_storage;
assign litedramcore_csr_dfi_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage;
assign litedramcore_csr_dfi_p0_wrdata_mask = 1'd0;
always @(*) begin
- litedramcore_csr_dfi_p1_cas_n <= 1'd1;
- if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_csr_dfi_p1_cas_n <= (~litedramcore_phaseinjector1_csrfield_cas);
- end else begin
- litedramcore_csr_dfi_p1_cas_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p1_cas_n <= 1'd1;
+ if (litedramcore_phaseinjector1_command_issue_re) begin
+ litedramcore_csr_dfi_p1_cas_n <= (~litedramcore_phaseinjector1_csrfield_cas);
+ end else begin
+ litedramcore_csr_dfi_p1_cas_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p1_cs_n <= 1'd1;
- if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}};
- end else begin
- litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}};
- end
+ litedramcore_csr_dfi_p1_cs_n <= 1'd1;
+ if (litedramcore_phaseinjector1_command_issue_re) begin
+ litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}};
+ end else begin
+ litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}};
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p1_ras_n <= 1'd1;
- if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_csr_dfi_p1_ras_n <= (~litedramcore_phaseinjector1_csrfield_ras);
- end else begin
- litedramcore_csr_dfi_p1_ras_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p1_ras_n <= 1'd1;
+ if (litedramcore_phaseinjector1_command_issue_re) begin
+ litedramcore_csr_dfi_p1_ras_n <= (~litedramcore_phaseinjector1_csrfield_ras);
+ end else begin
+ litedramcore_csr_dfi_p1_ras_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p1_we_n <= 1'd1;
- if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we);
- end else begin
- litedramcore_csr_dfi_p1_we_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p1_we_n <= 1'd1;
+ if (litedramcore_phaseinjector1_command_issue_re) begin
+ litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we);
+ end else begin
+ litedramcore_csr_dfi_p1_we_n <= 1'd1;
+ end
end
assign litedramcore_csr_dfi_p1_address = litedramcore_phaseinjector1_address_storage;
assign litedramcore_csr_dfi_p1_bank = litedramcore_phaseinjector1_baddress_storage;
assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1;
assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1;
always @(*) begin
- litedramcore_litedramcore_refresher_next_state <= 2'd0;
- litedramcore_litedramcore_refresher_next_state <= litedramcore_litedramcore_refresher_state;
- case (litedramcore_litedramcore_refresher_state)
- 1'd1: begin
- if (litedramcore_cmd_ready) begin
- litedramcore_litedramcore_refresher_next_state <= 2'd2;
- end
- end
- 2'd2: begin
- if (litedramcore_sequencer_done0) begin
- if (litedramcore_wants_zqcs) begin
- litedramcore_litedramcore_refresher_next_state <= 2'd3;
- end else begin
- litedramcore_litedramcore_refresher_next_state <= 1'd0;
- end
- end
- end
- 2'd3: begin
- if (litedramcore_zqcs_executer_done) begin
- litedramcore_litedramcore_refresher_next_state <= 1'd0;
- end
- end
- default: begin
- if (1'd1) begin
- if (litedramcore_wants_refresh) begin
- litedramcore_litedramcore_refresher_next_state <= 1'd1;
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_sequencer_start0 <= 1'd0;
- case (litedramcore_litedramcore_refresher_state)
- 1'd1: begin
- if (litedramcore_cmd_ready) begin
- litedramcore_sequencer_start0 <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_cmd_valid <= 1'd0;
- case (litedramcore_litedramcore_refresher_state)
- 1'd1: begin
- litedramcore_cmd_valid <= 1'd1;
- end
- 2'd2: begin
- litedramcore_cmd_valid <= 1'd1;
- if (litedramcore_sequencer_done0) begin
- if (litedramcore_wants_zqcs) begin
- end else begin
- litedramcore_cmd_valid <= 1'd0;
- end
- end
- end
- 2'd3: begin
- litedramcore_cmd_valid <= 1'd1;
- if (litedramcore_zqcs_executer_done) begin
- litedramcore_cmd_valid <= 1'd0;
- end
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_zqcs_executer_start <= 1'd0;
- case (litedramcore_litedramcore_refresher_state)
- 1'd1: begin
- end
- 2'd2: begin
- if (litedramcore_sequencer_done0) begin
- if (litedramcore_wants_zqcs) begin
- litedramcore_zqcs_executer_start <= 1'd1;
- end else begin
- end
- end
- end
- 2'd3: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_cmd_last <= 1'd0;
- case (litedramcore_litedramcore_refresher_state)
- 1'd1: begin
- end
- 2'd2: begin
- if (litedramcore_sequencer_done0) begin
- if (litedramcore_wants_zqcs) begin
- end else begin
- litedramcore_cmd_last <= 1'd1;
- end
- end
- end
- 2'd3: begin
- if (litedramcore_zqcs_executer_done) begin
- litedramcore_cmd_last <= 1'd1;
- end
- end
- default: begin
- end
- endcase
-end
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine0_req_valid;
-assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine0_req_we;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine0_req_addr;
-assign litedramcore_bankmachine0_cmd_buffer_sink_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine0_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine0_cmd_buffer_sink_first = litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine0_cmd_buffer_sink_last = litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine0_cmd_buffer_sink_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine0_cmd_buffer_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid);
-assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine0_cmd_buffer_source_valid);
-assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7]);
+ litedramcore_litedramcore_refresher_next_state <= 2'd0;
+ litedramcore_litedramcore_refresher_next_state <= litedramcore_litedramcore_refresher_state;
+ case (litedramcore_litedramcore_refresher_state)
+ 1'd1: begin
+ if (litedramcore_cmd_ready) begin
+ litedramcore_litedramcore_refresher_next_state <= 2'd2;
+ end
+ end
+ 2'd2: begin
+ if (litedramcore_sequencer_done0) begin
+ if (litedramcore_wants_zqcs) begin
+ litedramcore_litedramcore_refresher_next_state <= 2'd3;
+ end else begin
+ litedramcore_litedramcore_refresher_next_state <= 1'd0;
+ end
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_zqcs_executer_done) begin
+ litedramcore_litedramcore_refresher_next_state <= 1'd0;
+ end
+ end
+ default: begin
+ if (1'd1) begin
+ if (litedramcore_wants_refresh) begin
+ litedramcore_litedramcore_refresher_next_state <= 1'd1;
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_sequencer_start0 <= 1'd0;
+ case (litedramcore_litedramcore_refresher_state)
+ 1'd1: begin
+ if (litedramcore_cmd_ready) begin
+ litedramcore_sequencer_start0 <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_cmd_valid <= 1'd0;
+ case (litedramcore_litedramcore_refresher_state)
+ 1'd1: begin
+ litedramcore_cmd_valid <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_cmd_valid <= 1'd1;
+ if (litedramcore_sequencer_done0) begin
+ if (litedramcore_wants_zqcs) begin
+ end else begin
+ litedramcore_cmd_valid <= 1'd0;
+ end
+ end
+ end
+ 2'd3: begin
+ litedramcore_cmd_valid <= 1'd1;
+ if (litedramcore_zqcs_executer_done) begin
+ litedramcore_cmd_valid <= 1'd0;
+ end
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_zqcs_executer_start <= 1'd0;
+ case (litedramcore_litedramcore_refresher_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ if (litedramcore_sequencer_done0) begin
+ if (litedramcore_wants_zqcs) begin
+ litedramcore_zqcs_executer_start <= 1'd1;
+ end else begin
+ end
+ end
+ end
+ 2'd3: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_cmd_last <= 1'd0;
+ case (litedramcore_litedramcore_refresher_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ if (litedramcore_sequencer_done0) begin
+ if (litedramcore_wants_zqcs) begin
+ end else begin
+ litedramcore_cmd_last <= 1'd1;
+ end
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_zqcs_executer_done) begin
+ litedramcore_cmd_last <= 1'd1;
+ end
+ end
+ default: begin
+ end
+ endcase
+end
+assign litedramcore_bankmachine0_sink_valid = litedramcore_bankmachine0_req_valid;
+assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_sink_ready;
+assign litedramcore_bankmachine0_sink_payload_we = litedramcore_bankmachine0_req_we;
+assign litedramcore_bankmachine0_sink_payload_addr = litedramcore_bankmachine0_req_addr;
+assign litedramcore_bankmachine0_sink_sink_valid = litedramcore_bankmachine0_source_valid;
+assign litedramcore_bankmachine0_source_ready = litedramcore_bankmachine0_sink_sink_ready;
+assign litedramcore_bankmachine0_sink_sink_first = litedramcore_bankmachine0_source_first;
+assign litedramcore_bankmachine0_sink_sink_last = litedramcore_bankmachine0_source_last;
+assign litedramcore_bankmachine0_sink_sink_payload_we = litedramcore_bankmachine0_source_payload_we;
+assign litedramcore_bankmachine0_sink_sink_payload_addr = litedramcore_bankmachine0_source_payload_addr;
+assign litedramcore_bankmachine0_source_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid);
+assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_source_valid | litedramcore_bankmachine0_source_source_valid);
+assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_source_source_payload_addr[21:7]);
assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
always @(*) begin
- litedramcore_bankmachine0_cmd_payload_a <= 15'd0;
- if (litedramcore_bankmachine0_row_col_n_addr_sel) begin
- litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7];
- end else begin
- litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine0_cmd_payload_a <= 15'd0;
+ if (litedramcore_bankmachine0_row_col_n_addr_sel) begin
+ litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_source_source_payload_addr[21:7];
+ end else begin
+ litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write);
assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
always @(*) begin
- litedramcore_bankmachine0_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine0_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7])) begin
- litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine0_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | litedramcore_bankmachine0_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re);
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine0_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_litedramcore_bankmachine0_next_state <= 3'd0;
- litedramcore_litedramcore_bankmachine0_next_state <= litedramcore_litedramcore_bankmachine0_state;
- case (litedramcore_litedramcore_bankmachine0_state)
- 1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- if (litedramcore_bankmachine0_cmd_ready) begin
- litedramcore_litedramcore_bankmachine0_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_litedramcore_bankmachine0_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- if (litedramcore_bankmachine0_cmd_ready) begin
- litedramcore_litedramcore_bankmachine0_next_state <= 3'd6;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine0_refresh_req)) begin
- litedramcore_litedramcore_bankmachine0_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_litedramcore_bankmachine0_next_state <= 2'd3;
- end
- 3'd6: begin
- litedramcore_litedramcore_bankmachine0_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- litedramcore_litedramcore_bankmachine0_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin
- litedramcore_litedramcore_bankmachine0_next_state <= 2'd2;
- end
- end else begin
- litedramcore_litedramcore_bankmachine0_next_state <= 1'd1;
- end
- end else begin
- litedramcore_litedramcore_bankmachine0_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_row_open <= 1'd0;
- case (litedramcore_litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_row_close <= 1'd0;
- case (litedramcore_litedramcore_bankmachine0_state)
- 1'd1: begin
- litedramcore_bankmachine0_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine0_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine0_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
- case (litedramcore_litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
- case (litedramcore_litedramcore_bankmachine0_state)
- 1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
- case (litedramcore_litedramcore_bankmachine0_state)
- 1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_litedramcore_bankmachine0_state)
- 1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
- case (litedramcore_litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
- case (litedramcore_litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
- case (litedramcore_litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
- case (litedramcore_litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_refresh_gnt <= 1'd0;
- case (litedramcore_litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine0_twtpcon_ready) begin
- litedramcore_bankmachine0_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_cmd_valid <= 1'd0;
- case (litedramcore_litedramcore_bankmachine0_state)
- 1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- litedramcore_bankmachine0_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine1_req_valid;
-assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine1_req_we;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine1_req_addr;
-assign litedramcore_bankmachine1_cmd_buffer_sink_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine1_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine1_cmd_buffer_sink_first = litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine1_cmd_buffer_sink_last = litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine1_cmd_buffer_sink_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine1_cmd_buffer_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid);
-assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine1_cmd_buffer_source_valid);
-assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7]);
+ litedramcore_bankmachine0_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine0_source_valid & litedramcore_bankmachine0_source_source_valid)) begin
+ if ((litedramcore_bankmachine0_source_payload_addr[21:7] != litedramcore_bankmachine0_source_source_payload_addr[21:7])) begin
+ litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine0_syncfifo0_din = {litedramcore_bankmachine0_fifo_in_last, litedramcore_bankmachine0_fifo_in_first, litedramcore_bankmachine0_fifo_in_payload_addr, litedramcore_bankmachine0_fifo_in_payload_we};
+assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout;
+assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout;
+assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout;
+assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout;
+assign litedramcore_bankmachine0_sink_ready = litedramcore_bankmachine0_syncfifo0_writable;
+assign litedramcore_bankmachine0_syncfifo0_we = litedramcore_bankmachine0_sink_valid;
+assign litedramcore_bankmachine0_fifo_in_first = litedramcore_bankmachine0_sink_first;
+assign litedramcore_bankmachine0_fifo_in_last = litedramcore_bankmachine0_sink_last;
+assign litedramcore_bankmachine0_fifo_in_payload_we = litedramcore_bankmachine0_sink_payload_we;
+assign litedramcore_bankmachine0_fifo_in_payload_addr = litedramcore_bankmachine0_sink_payload_addr;
+assign litedramcore_bankmachine0_source_valid = litedramcore_bankmachine0_syncfifo0_readable;
+assign litedramcore_bankmachine0_source_first = litedramcore_bankmachine0_fifo_out_first;
+assign litedramcore_bankmachine0_source_last = litedramcore_bankmachine0_fifo_out_last;
+assign litedramcore_bankmachine0_source_payload_we = litedramcore_bankmachine0_fifo_out_payload_we;
+assign litedramcore_bankmachine0_source_payload_addr = litedramcore_bankmachine0_fifo_out_payload_addr;
+assign litedramcore_bankmachine0_syncfifo0_re = litedramcore_bankmachine0_source_ready;
+always @(*) begin
+ litedramcore_bankmachine0_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine0_replace) begin
+ litedramcore_bankmachine0_wrport_adr <= (litedramcore_bankmachine0_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine0_wrport_adr <= litedramcore_bankmachine0_produce;
+ end
+end
+assign litedramcore_bankmachine0_wrport_dat_w = litedramcore_bankmachine0_syncfifo0_din;
+assign litedramcore_bankmachine0_wrport_we = (litedramcore_bankmachine0_syncfifo0_we & (litedramcore_bankmachine0_syncfifo0_writable | litedramcore_bankmachine0_replace));
+assign litedramcore_bankmachine0_do_read = (litedramcore_bankmachine0_syncfifo0_readable & litedramcore_bankmachine0_syncfifo0_re);
+assign litedramcore_bankmachine0_rdport_adr = litedramcore_bankmachine0_consume;
+assign litedramcore_bankmachine0_syncfifo0_dout = litedramcore_bankmachine0_rdport_dat_r;
+assign litedramcore_bankmachine0_syncfifo0_writable = (litedramcore_bankmachine0_level != 5'd16);
+assign litedramcore_bankmachine0_syncfifo0_readable = (litedramcore_bankmachine0_level != 1'd0);
+assign litedramcore_bankmachine0_pipe_valid_sink_ready = ((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready);
+assign litedramcore_bankmachine0_pipe_valid_sink_valid = litedramcore_bankmachine0_sink_sink_valid;
+assign litedramcore_bankmachine0_sink_sink_ready = litedramcore_bankmachine0_pipe_valid_sink_ready;
+assign litedramcore_bankmachine0_pipe_valid_sink_first = litedramcore_bankmachine0_sink_sink_first;
+assign litedramcore_bankmachine0_pipe_valid_sink_last = litedramcore_bankmachine0_sink_sink_last;
+assign litedramcore_bankmachine0_pipe_valid_sink_payload_we = litedramcore_bankmachine0_sink_sink_payload_we;
+assign litedramcore_bankmachine0_pipe_valid_sink_payload_addr = litedramcore_bankmachine0_sink_sink_payload_addr;
+assign litedramcore_bankmachine0_source_source_valid = litedramcore_bankmachine0_pipe_valid_source_valid;
+assign litedramcore_bankmachine0_pipe_valid_source_ready = litedramcore_bankmachine0_source_source_ready;
+assign litedramcore_bankmachine0_source_source_first = litedramcore_bankmachine0_pipe_valid_source_first;
+assign litedramcore_bankmachine0_source_source_last = litedramcore_bankmachine0_pipe_valid_source_last;
+assign litedramcore_bankmachine0_source_source_payload_we = litedramcore_bankmachine0_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine0_source_source_payload_addr = litedramcore_bankmachine0_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_litedramcore_bankmachine0_next_state <= 3'd0;
+ litedramcore_litedramcore_bankmachine0_next_state <= litedramcore_litedramcore_bankmachine0_state;
+ case (litedramcore_litedramcore_bankmachine0_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ if (litedramcore_bankmachine0_cmd_ready) begin
+ litedramcore_litedramcore_bankmachine0_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_litedramcore_bankmachine0_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ if (litedramcore_bankmachine0_cmd_ready) begin
+ litedramcore_litedramcore_bankmachine0_next_state <= 3'd6;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine0_refresh_req)) begin
+ litedramcore_litedramcore_bankmachine0_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_litedramcore_bankmachine0_next_state <= 2'd3;
+ end
+ 3'd6: begin
+ litedramcore_litedramcore_bankmachine0_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ litedramcore_litedramcore_bankmachine0_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin
+ litedramcore_litedramcore_bankmachine0_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_litedramcore_bankmachine0_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_litedramcore_bankmachine0_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine0_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine0_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if (litedramcore_bankmachine0_source_source_payload_we) begin
+ litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine0_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if (litedramcore_bankmachine0_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if (litedramcore_bankmachine0_source_source_payload_we) begin
+ litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if (litedramcore_bankmachine0_source_source_payload_we) begin
+ litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if (litedramcore_bankmachine0_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_refresh_gnt <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine0_twtpcon_ready) begin
+ litedramcore_bankmachine0_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_row_open <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_valid <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine0_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ litedramcore_bankmachine0_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_row_close <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine0_state)
+ 1'd1: begin
+ litedramcore_bankmachine0_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine0_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine0_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+assign litedramcore_bankmachine1_sink_valid = litedramcore_bankmachine1_req_valid;
+assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_sink_ready;
+assign litedramcore_bankmachine1_sink_payload_we = litedramcore_bankmachine1_req_we;
+assign litedramcore_bankmachine1_sink_payload_addr = litedramcore_bankmachine1_req_addr;
+assign litedramcore_bankmachine1_sink_sink_valid = litedramcore_bankmachine1_source_valid;
+assign litedramcore_bankmachine1_source_ready = litedramcore_bankmachine1_sink_sink_ready;
+assign litedramcore_bankmachine1_sink_sink_first = litedramcore_bankmachine1_source_first;
+assign litedramcore_bankmachine1_sink_sink_last = litedramcore_bankmachine1_source_last;
+assign litedramcore_bankmachine1_sink_sink_payload_we = litedramcore_bankmachine1_source_payload_we;
+assign litedramcore_bankmachine1_sink_sink_payload_addr = litedramcore_bankmachine1_source_payload_addr;
+assign litedramcore_bankmachine1_source_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid);
+assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_source_valid | litedramcore_bankmachine1_source_source_valid);
+assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_source_source_payload_addr[21:7]);
assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
always @(*) begin
- litedramcore_bankmachine1_cmd_payload_a <= 15'd0;
- if (litedramcore_bankmachine1_row_col_n_addr_sel) begin
- litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7];
- end else begin
- litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine1_cmd_payload_a <= 15'd0;
+ if (litedramcore_bankmachine1_row_col_n_addr_sel) begin
+ litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_source_source_payload_addr[21:7];
+ end else begin
+ litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write);
assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
always @(*) begin
- litedramcore_bankmachine1_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine1_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7])) begin
- litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine1_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | litedramcore_bankmachine1_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re);
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine1_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_litedramcore_bankmachine1_next_state <= 3'd0;
- litedramcore_litedramcore_bankmachine1_next_state <= litedramcore_litedramcore_bankmachine1_state;
- case (litedramcore_litedramcore_bankmachine1_state)
- 1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- if (litedramcore_bankmachine1_cmd_ready) begin
- litedramcore_litedramcore_bankmachine1_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_litedramcore_bankmachine1_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- if (litedramcore_bankmachine1_cmd_ready) begin
- litedramcore_litedramcore_bankmachine1_next_state <= 3'd6;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine1_refresh_req)) begin
- litedramcore_litedramcore_bankmachine1_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_litedramcore_bankmachine1_next_state <= 2'd3;
- end
- 3'd6: begin
- litedramcore_litedramcore_bankmachine1_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- litedramcore_litedramcore_bankmachine1_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin
- litedramcore_litedramcore_bankmachine1_next_state <= 2'd2;
- end
- end else begin
- litedramcore_litedramcore_bankmachine1_next_state <= 1'd1;
- end
- end else begin
- litedramcore_litedramcore_bankmachine1_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_row_open <= 1'd0;
- case (litedramcore_litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_row_close <= 1'd0;
- case (litedramcore_litedramcore_bankmachine1_state)
- 1'd1: begin
- litedramcore_bankmachine1_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine1_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine1_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
- case (litedramcore_litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
- case (litedramcore_litedramcore_bankmachine1_state)
- 1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
- case (litedramcore_litedramcore_bankmachine1_state)
- 1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_litedramcore_bankmachine1_state)
- 1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
- case (litedramcore_litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
- case (litedramcore_litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
- case (litedramcore_litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
- case (litedramcore_litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_refresh_gnt <= 1'd0;
- case (litedramcore_litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine1_twtpcon_ready) begin
- litedramcore_bankmachine1_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd0;
- case (litedramcore_litedramcore_bankmachine1_state)
- 1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine2_req_valid;
-assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine2_req_we;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine2_req_addr;
-assign litedramcore_bankmachine2_cmd_buffer_sink_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine2_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine2_cmd_buffer_sink_first = litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine2_cmd_buffer_sink_last = litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine2_cmd_buffer_sink_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine2_cmd_buffer_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid);
-assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine2_cmd_buffer_source_valid);
-assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7]);
+ litedramcore_bankmachine1_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine1_source_valid & litedramcore_bankmachine1_source_source_valid)) begin
+ if ((litedramcore_bankmachine1_source_payload_addr[21:7] != litedramcore_bankmachine1_source_source_payload_addr[21:7])) begin
+ litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine1_syncfifo1_din = {litedramcore_bankmachine1_fifo_in_last, litedramcore_bankmachine1_fifo_in_first, litedramcore_bankmachine1_fifo_in_payload_addr, litedramcore_bankmachine1_fifo_in_payload_we};
+assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout;
+assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout;
+assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout;
+assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout;
+assign litedramcore_bankmachine1_sink_ready = litedramcore_bankmachine1_syncfifo1_writable;
+assign litedramcore_bankmachine1_syncfifo1_we = litedramcore_bankmachine1_sink_valid;
+assign litedramcore_bankmachine1_fifo_in_first = litedramcore_bankmachine1_sink_first;
+assign litedramcore_bankmachine1_fifo_in_last = litedramcore_bankmachine1_sink_last;
+assign litedramcore_bankmachine1_fifo_in_payload_we = litedramcore_bankmachine1_sink_payload_we;
+assign litedramcore_bankmachine1_fifo_in_payload_addr = litedramcore_bankmachine1_sink_payload_addr;
+assign litedramcore_bankmachine1_source_valid = litedramcore_bankmachine1_syncfifo1_readable;
+assign litedramcore_bankmachine1_source_first = litedramcore_bankmachine1_fifo_out_first;
+assign litedramcore_bankmachine1_source_last = litedramcore_bankmachine1_fifo_out_last;
+assign litedramcore_bankmachine1_source_payload_we = litedramcore_bankmachine1_fifo_out_payload_we;
+assign litedramcore_bankmachine1_source_payload_addr = litedramcore_bankmachine1_fifo_out_payload_addr;
+assign litedramcore_bankmachine1_syncfifo1_re = litedramcore_bankmachine1_source_ready;
+always @(*) begin
+ litedramcore_bankmachine1_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine1_replace) begin
+ litedramcore_bankmachine1_wrport_adr <= (litedramcore_bankmachine1_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine1_wrport_adr <= litedramcore_bankmachine1_produce;
+ end
+end
+assign litedramcore_bankmachine1_wrport_dat_w = litedramcore_bankmachine1_syncfifo1_din;
+assign litedramcore_bankmachine1_wrport_we = (litedramcore_bankmachine1_syncfifo1_we & (litedramcore_bankmachine1_syncfifo1_writable | litedramcore_bankmachine1_replace));
+assign litedramcore_bankmachine1_do_read = (litedramcore_bankmachine1_syncfifo1_readable & litedramcore_bankmachine1_syncfifo1_re);
+assign litedramcore_bankmachine1_rdport_adr = litedramcore_bankmachine1_consume;
+assign litedramcore_bankmachine1_syncfifo1_dout = litedramcore_bankmachine1_rdport_dat_r;
+assign litedramcore_bankmachine1_syncfifo1_writable = (litedramcore_bankmachine1_level != 5'd16);
+assign litedramcore_bankmachine1_syncfifo1_readable = (litedramcore_bankmachine1_level != 1'd0);
+assign litedramcore_bankmachine1_pipe_valid_sink_ready = ((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready);
+assign litedramcore_bankmachine1_pipe_valid_sink_valid = litedramcore_bankmachine1_sink_sink_valid;
+assign litedramcore_bankmachine1_sink_sink_ready = litedramcore_bankmachine1_pipe_valid_sink_ready;
+assign litedramcore_bankmachine1_pipe_valid_sink_first = litedramcore_bankmachine1_sink_sink_first;
+assign litedramcore_bankmachine1_pipe_valid_sink_last = litedramcore_bankmachine1_sink_sink_last;
+assign litedramcore_bankmachine1_pipe_valid_sink_payload_we = litedramcore_bankmachine1_sink_sink_payload_we;
+assign litedramcore_bankmachine1_pipe_valid_sink_payload_addr = litedramcore_bankmachine1_sink_sink_payload_addr;
+assign litedramcore_bankmachine1_source_source_valid = litedramcore_bankmachine1_pipe_valid_source_valid;
+assign litedramcore_bankmachine1_pipe_valid_source_ready = litedramcore_bankmachine1_source_source_ready;
+assign litedramcore_bankmachine1_source_source_first = litedramcore_bankmachine1_pipe_valid_source_first;
+assign litedramcore_bankmachine1_source_source_last = litedramcore_bankmachine1_pipe_valid_source_last;
+assign litedramcore_bankmachine1_source_source_payload_we = litedramcore_bankmachine1_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine1_source_source_payload_addr = litedramcore_bankmachine1_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_litedramcore_bankmachine1_next_state <= 3'd0;
+ litedramcore_litedramcore_bankmachine1_next_state <= litedramcore_litedramcore_bankmachine1_state;
+ case (litedramcore_litedramcore_bankmachine1_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ if (litedramcore_bankmachine1_cmd_ready) begin
+ litedramcore_litedramcore_bankmachine1_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_litedramcore_bankmachine1_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ if (litedramcore_bankmachine1_cmd_ready) begin
+ litedramcore_litedramcore_bankmachine1_next_state <= 3'd6;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine1_refresh_req)) begin
+ litedramcore_litedramcore_bankmachine1_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_litedramcore_bankmachine1_next_state <= 2'd3;
+ end
+ 3'd6: begin
+ litedramcore_litedramcore_bankmachine1_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ litedramcore_litedramcore_bankmachine1_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin
+ litedramcore_litedramcore_bankmachine1_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_litedramcore_bankmachine1_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_litedramcore_bankmachine1_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine1_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine1_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if (litedramcore_bankmachine1_source_source_payload_we) begin
+ litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine1_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if (litedramcore_bankmachine1_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if (litedramcore_bankmachine1_source_source_payload_we) begin
+ litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if (litedramcore_bankmachine1_source_source_payload_we) begin
+ litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if (litedramcore_bankmachine1_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_refresh_gnt <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine1_twtpcon_ready) begin
+ litedramcore_bankmachine1_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_row_open <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_valid <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine1_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ litedramcore_bankmachine1_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_row_close <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine1_state)
+ 1'd1: begin
+ litedramcore_bankmachine1_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine1_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine1_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+assign litedramcore_bankmachine2_sink_valid = litedramcore_bankmachine2_req_valid;
+assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_sink_ready;
+assign litedramcore_bankmachine2_sink_payload_we = litedramcore_bankmachine2_req_we;
+assign litedramcore_bankmachine2_sink_payload_addr = litedramcore_bankmachine2_req_addr;
+assign litedramcore_bankmachine2_sink_sink_valid = litedramcore_bankmachine2_source_valid;
+assign litedramcore_bankmachine2_source_ready = litedramcore_bankmachine2_sink_sink_ready;
+assign litedramcore_bankmachine2_sink_sink_first = litedramcore_bankmachine2_source_first;
+assign litedramcore_bankmachine2_sink_sink_last = litedramcore_bankmachine2_source_last;
+assign litedramcore_bankmachine2_sink_sink_payload_we = litedramcore_bankmachine2_source_payload_we;
+assign litedramcore_bankmachine2_sink_sink_payload_addr = litedramcore_bankmachine2_source_payload_addr;
+assign litedramcore_bankmachine2_source_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid);
+assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_source_valid | litedramcore_bankmachine2_source_source_valid);
+assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_source_source_payload_addr[21:7]);
assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
always @(*) begin
- litedramcore_bankmachine2_cmd_payload_a <= 15'd0;
- if (litedramcore_bankmachine2_row_col_n_addr_sel) begin
- litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7];
- end else begin
- litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine2_cmd_payload_a <= 15'd0;
+ if (litedramcore_bankmachine2_row_col_n_addr_sel) begin
+ litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_source_source_payload_addr[21:7];
+ end else begin
+ litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write);
assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
always @(*) begin
- litedramcore_bankmachine2_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine2_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7])) begin
- litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine2_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | litedramcore_bankmachine2_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re);
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine2_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_litedramcore_bankmachine2_next_state <= 3'd0;
- litedramcore_litedramcore_bankmachine2_next_state <= litedramcore_litedramcore_bankmachine2_state;
- case (litedramcore_litedramcore_bankmachine2_state)
- 1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- if (litedramcore_bankmachine2_cmd_ready) begin
- litedramcore_litedramcore_bankmachine2_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_litedramcore_bankmachine2_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- if (litedramcore_bankmachine2_cmd_ready) begin
- litedramcore_litedramcore_bankmachine2_next_state <= 3'd6;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine2_refresh_req)) begin
- litedramcore_litedramcore_bankmachine2_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_litedramcore_bankmachine2_next_state <= 2'd3;
- end
- 3'd6: begin
- litedramcore_litedramcore_bankmachine2_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- litedramcore_litedramcore_bankmachine2_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin
- litedramcore_litedramcore_bankmachine2_next_state <= 2'd2;
- end
- end else begin
- litedramcore_litedramcore_bankmachine2_next_state <= 1'd1;
- end
- end else begin
- litedramcore_litedramcore_bankmachine2_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_row_open <= 1'd0;
- case (litedramcore_litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_row_close <= 1'd0;
- case (litedramcore_litedramcore_bankmachine2_state)
- 1'd1: begin
- litedramcore_bankmachine2_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine2_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine2_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
- case (litedramcore_litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
- case (litedramcore_litedramcore_bankmachine2_state)
- 1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
- case (litedramcore_litedramcore_bankmachine2_state)
- 1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_litedramcore_bankmachine2_state)
- 1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_refresh_gnt <= 1'd0;
- case (litedramcore_litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine2_twtpcon_ready) begin
- litedramcore_bankmachine2_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
- case (litedramcore_litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
- case (litedramcore_litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
- case (litedramcore_litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
- case (litedramcore_litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_cmd_valid <= 1'd0;
- case (litedramcore_litedramcore_bankmachine2_state)
- 1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- litedramcore_bankmachine2_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine3_req_valid;
-assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine3_req_we;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine3_req_addr;
-assign litedramcore_bankmachine3_cmd_buffer_sink_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine3_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine3_cmd_buffer_sink_first = litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine3_cmd_buffer_sink_last = litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine3_cmd_buffer_sink_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine3_cmd_buffer_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid);
-assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine3_cmd_buffer_source_valid);
-assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7]);
+ litedramcore_bankmachine2_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine2_source_valid & litedramcore_bankmachine2_source_source_valid)) begin
+ if ((litedramcore_bankmachine2_source_payload_addr[21:7] != litedramcore_bankmachine2_source_source_payload_addr[21:7])) begin
+ litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine2_syncfifo2_din = {litedramcore_bankmachine2_fifo_in_last, litedramcore_bankmachine2_fifo_in_first, litedramcore_bankmachine2_fifo_in_payload_addr, litedramcore_bankmachine2_fifo_in_payload_we};
+assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout;
+assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout;
+assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout;
+assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout;
+assign litedramcore_bankmachine2_sink_ready = litedramcore_bankmachine2_syncfifo2_writable;
+assign litedramcore_bankmachine2_syncfifo2_we = litedramcore_bankmachine2_sink_valid;
+assign litedramcore_bankmachine2_fifo_in_first = litedramcore_bankmachine2_sink_first;
+assign litedramcore_bankmachine2_fifo_in_last = litedramcore_bankmachine2_sink_last;
+assign litedramcore_bankmachine2_fifo_in_payload_we = litedramcore_bankmachine2_sink_payload_we;
+assign litedramcore_bankmachine2_fifo_in_payload_addr = litedramcore_bankmachine2_sink_payload_addr;
+assign litedramcore_bankmachine2_source_valid = litedramcore_bankmachine2_syncfifo2_readable;
+assign litedramcore_bankmachine2_source_first = litedramcore_bankmachine2_fifo_out_first;
+assign litedramcore_bankmachine2_source_last = litedramcore_bankmachine2_fifo_out_last;
+assign litedramcore_bankmachine2_source_payload_we = litedramcore_bankmachine2_fifo_out_payload_we;
+assign litedramcore_bankmachine2_source_payload_addr = litedramcore_bankmachine2_fifo_out_payload_addr;
+assign litedramcore_bankmachine2_syncfifo2_re = litedramcore_bankmachine2_source_ready;
+always @(*) begin
+ litedramcore_bankmachine2_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine2_replace) begin
+ litedramcore_bankmachine2_wrport_adr <= (litedramcore_bankmachine2_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine2_wrport_adr <= litedramcore_bankmachine2_produce;
+ end
+end
+assign litedramcore_bankmachine2_wrport_dat_w = litedramcore_bankmachine2_syncfifo2_din;
+assign litedramcore_bankmachine2_wrport_we = (litedramcore_bankmachine2_syncfifo2_we & (litedramcore_bankmachine2_syncfifo2_writable | litedramcore_bankmachine2_replace));
+assign litedramcore_bankmachine2_do_read = (litedramcore_bankmachine2_syncfifo2_readable & litedramcore_bankmachine2_syncfifo2_re);
+assign litedramcore_bankmachine2_rdport_adr = litedramcore_bankmachine2_consume;
+assign litedramcore_bankmachine2_syncfifo2_dout = litedramcore_bankmachine2_rdport_dat_r;
+assign litedramcore_bankmachine2_syncfifo2_writable = (litedramcore_bankmachine2_level != 5'd16);
+assign litedramcore_bankmachine2_syncfifo2_readable = (litedramcore_bankmachine2_level != 1'd0);
+assign litedramcore_bankmachine2_pipe_valid_sink_ready = ((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready);
+assign litedramcore_bankmachine2_pipe_valid_sink_valid = litedramcore_bankmachine2_sink_sink_valid;
+assign litedramcore_bankmachine2_sink_sink_ready = litedramcore_bankmachine2_pipe_valid_sink_ready;
+assign litedramcore_bankmachine2_pipe_valid_sink_first = litedramcore_bankmachine2_sink_sink_first;
+assign litedramcore_bankmachine2_pipe_valid_sink_last = litedramcore_bankmachine2_sink_sink_last;
+assign litedramcore_bankmachine2_pipe_valid_sink_payload_we = litedramcore_bankmachine2_sink_sink_payload_we;
+assign litedramcore_bankmachine2_pipe_valid_sink_payload_addr = litedramcore_bankmachine2_sink_sink_payload_addr;
+assign litedramcore_bankmachine2_source_source_valid = litedramcore_bankmachine2_pipe_valid_source_valid;
+assign litedramcore_bankmachine2_pipe_valid_source_ready = litedramcore_bankmachine2_source_source_ready;
+assign litedramcore_bankmachine2_source_source_first = litedramcore_bankmachine2_pipe_valid_source_first;
+assign litedramcore_bankmachine2_source_source_last = litedramcore_bankmachine2_pipe_valid_source_last;
+assign litedramcore_bankmachine2_source_source_payload_we = litedramcore_bankmachine2_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine2_source_source_payload_addr = litedramcore_bankmachine2_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_litedramcore_bankmachine2_next_state <= 3'd0;
+ litedramcore_litedramcore_bankmachine2_next_state <= litedramcore_litedramcore_bankmachine2_state;
+ case (litedramcore_litedramcore_bankmachine2_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ if (litedramcore_bankmachine2_cmd_ready) begin
+ litedramcore_litedramcore_bankmachine2_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_litedramcore_bankmachine2_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ if (litedramcore_bankmachine2_cmd_ready) begin
+ litedramcore_litedramcore_bankmachine2_next_state <= 3'd6;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine2_refresh_req)) begin
+ litedramcore_litedramcore_bankmachine2_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_litedramcore_bankmachine2_next_state <= 2'd3;
+ end
+ 3'd6: begin
+ litedramcore_litedramcore_bankmachine2_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ litedramcore_litedramcore_bankmachine2_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin
+ litedramcore_litedramcore_bankmachine2_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_litedramcore_bankmachine2_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_litedramcore_bankmachine2_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if (litedramcore_bankmachine2_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if (litedramcore_bankmachine2_source_source_payload_we) begin
+ litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if (litedramcore_bankmachine2_source_source_payload_we) begin
+ litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if (litedramcore_bankmachine2_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_refresh_gnt <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine2_twtpcon_ready) begin
+ litedramcore_bankmachine2_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_row_open <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_valid <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine2_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ litedramcore_bankmachine2_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_row_close <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine2_state)
+ 1'd1: begin
+ litedramcore_bankmachine2_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine2_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine2_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine2_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine2_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if (litedramcore_bankmachine2_source_source_payload_we) begin
+ litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine2_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+assign litedramcore_bankmachine3_sink_valid = litedramcore_bankmachine3_req_valid;
+assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_sink_ready;
+assign litedramcore_bankmachine3_sink_payload_we = litedramcore_bankmachine3_req_we;
+assign litedramcore_bankmachine3_sink_payload_addr = litedramcore_bankmachine3_req_addr;
+assign litedramcore_bankmachine3_sink_sink_valid = litedramcore_bankmachine3_source_valid;
+assign litedramcore_bankmachine3_source_ready = litedramcore_bankmachine3_sink_sink_ready;
+assign litedramcore_bankmachine3_sink_sink_first = litedramcore_bankmachine3_source_first;
+assign litedramcore_bankmachine3_sink_sink_last = litedramcore_bankmachine3_source_last;
+assign litedramcore_bankmachine3_sink_sink_payload_we = litedramcore_bankmachine3_source_payload_we;
+assign litedramcore_bankmachine3_sink_sink_payload_addr = litedramcore_bankmachine3_source_payload_addr;
+assign litedramcore_bankmachine3_source_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid);
+assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_source_valid | litedramcore_bankmachine3_source_source_valid);
+assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_source_source_payload_addr[21:7]);
assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
always @(*) begin
- litedramcore_bankmachine3_cmd_payload_a <= 15'd0;
- if (litedramcore_bankmachine3_row_col_n_addr_sel) begin
- litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7];
- end else begin
- litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine3_cmd_payload_a <= 15'd0;
+ if (litedramcore_bankmachine3_row_col_n_addr_sel) begin
+ litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_source_source_payload_addr[21:7];
+ end else begin
+ litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write);
assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
always @(*) begin
- litedramcore_bankmachine3_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine3_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7])) begin
- litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine3_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | litedramcore_bankmachine3_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re);
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine3_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_litedramcore_bankmachine3_next_state <= 3'd0;
- litedramcore_litedramcore_bankmachine3_next_state <= litedramcore_litedramcore_bankmachine3_state;
- case (litedramcore_litedramcore_bankmachine3_state)
- 1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- if (litedramcore_bankmachine3_cmd_ready) begin
- litedramcore_litedramcore_bankmachine3_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_litedramcore_bankmachine3_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- if (litedramcore_bankmachine3_cmd_ready) begin
- litedramcore_litedramcore_bankmachine3_next_state <= 3'd6;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine3_refresh_req)) begin
- litedramcore_litedramcore_bankmachine3_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_litedramcore_bankmachine3_next_state <= 2'd3;
- end
- 3'd6: begin
- litedramcore_litedramcore_bankmachine3_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- litedramcore_litedramcore_bankmachine3_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin
- litedramcore_litedramcore_bankmachine3_next_state <= 2'd2;
- end
- end else begin
- litedramcore_litedramcore_bankmachine3_next_state <= 1'd1;
- end
- end else begin
- litedramcore_litedramcore_bankmachine3_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_row_open <= 1'd0;
- case (litedramcore_litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_row_close <= 1'd0;
- case (litedramcore_litedramcore_bankmachine3_state)
- 1'd1: begin
- litedramcore_bankmachine3_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine3_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine3_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
- case (litedramcore_litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
- case (litedramcore_litedramcore_bankmachine3_state)
- 1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
- case (litedramcore_litedramcore_bankmachine3_state)
- 1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_litedramcore_bankmachine3_state)
- 1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
- case (litedramcore_litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
- case (litedramcore_litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
- case (litedramcore_litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
- case (litedramcore_litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_refresh_gnt <= 1'd0;
- case (litedramcore_litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine3_twtpcon_ready) begin
- litedramcore_bankmachine3_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_cmd_valid <= 1'd0;
- case (litedramcore_litedramcore_bankmachine3_state)
- 1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- litedramcore_bankmachine3_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine4_req_valid;
-assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine4_req_we;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine4_req_addr;
-assign litedramcore_bankmachine4_cmd_buffer_sink_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine4_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine4_cmd_buffer_sink_first = litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine4_cmd_buffer_sink_last = litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine4_cmd_buffer_sink_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine4_cmd_buffer_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid);
-assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine4_cmd_buffer_source_valid);
-assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7]);
+ litedramcore_bankmachine3_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine3_source_valid & litedramcore_bankmachine3_source_source_valid)) begin
+ if ((litedramcore_bankmachine3_source_payload_addr[21:7] != litedramcore_bankmachine3_source_source_payload_addr[21:7])) begin
+ litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine3_syncfifo3_din = {litedramcore_bankmachine3_fifo_in_last, litedramcore_bankmachine3_fifo_in_first, litedramcore_bankmachine3_fifo_in_payload_addr, litedramcore_bankmachine3_fifo_in_payload_we};
+assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout;
+assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout;
+assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout;
+assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout;
+assign litedramcore_bankmachine3_sink_ready = litedramcore_bankmachine3_syncfifo3_writable;
+assign litedramcore_bankmachine3_syncfifo3_we = litedramcore_bankmachine3_sink_valid;
+assign litedramcore_bankmachine3_fifo_in_first = litedramcore_bankmachine3_sink_first;
+assign litedramcore_bankmachine3_fifo_in_last = litedramcore_bankmachine3_sink_last;
+assign litedramcore_bankmachine3_fifo_in_payload_we = litedramcore_bankmachine3_sink_payload_we;
+assign litedramcore_bankmachine3_fifo_in_payload_addr = litedramcore_bankmachine3_sink_payload_addr;
+assign litedramcore_bankmachine3_source_valid = litedramcore_bankmachine3_syncfifo3_readable;
+assign litedramcore_bankmachine3_source_first = litedramcore_bankmachine3_fifo_out_first;
+assign litedramcore_bankmachine3_source_last = litedramcore_bankmachine3_fifo_out_last;
+assign litedramcore_bankmachine3_source_payload_we = litedramcore_bankmachine3_fifo_out_payload_we;
+assign litedramcore_bankmachine3_source_payload_addr = litedramcore_bankmachine3_fifo_out_payload_addr;
+assign litedramcore_bankmachine3_syncfifo3_re = litedramcore_bankmachine3_source_ready;
+always @(*) begin
+ litedramcore_bankmachine3_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine3_replace) begin
+ litedramcore_bankmachine3_wrport_adr <= (litedramcore_bankmachine3_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine3_wrport_adr <= litedramcore_bankmachine3_produce;
+ end
+end
+assign litedramcore_bankmachine3_wrport_dat_w = litedramcore_bankmachine3_syncfifo3_din;
+assign litedramcore_bankmachine3_wrport_we = (litedramcore_bankmachine3_syncfifo3_we & (litedramcore_bankmachine3_syncfifo3_writable | litedramcore_bankmachine3_replace));
+assign litedramcore_bankmachine3_do_read = (litedramcore_bankmachine3_syncfifo3_readable & litedramcore_bankmachine3_syncfifo3_re);
+assign litedramcore_bankmachine3_rdport_adr = litedramcore_bankmachine3_consume;
+assign litedramcore_bankmachine3_syncfifo3_dout = litedramcore_bankmachine3_rdport_dat_r;
+assign litedramcore_bankmachine3_syncfifo3_writable = (litedramcore_bankmachine3_level != 5'd16);
+assign litedramcore_bankmachine3_syncfifo3_readable = (litedramcore_bankmachine3_level != 1'd0);
+assign litedramcore_bankmachine3_pipe_valid_sink_ready = ((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready);
+assign litedramcore_bankmachine3_pipe_valid_sink_valid = litedramcore_bankmachine3_sink_sink_valid;
+assign litedramcore_bankmachine3_sink_sink_ready = litedramcore_bankmachine3_pipe_valid_sink_ready;
+assign litedramcore_bankmachine3_pipe_valid_sink_first = litedramcore_bankmachine3_sink_sink_first;
+assign litedramcore_bankmachine3_pipe_valid_sink_last = litedramcore_bankmachine3_sink_sink_last;
+assign litedramcore_bankmachine3_pipe_valid_sink_payload_we = litedramcore_bankmachine3_sink_sink_payload_we;
+assign litedramcore_bankmachine3_pipe_valid_sink_payload_addr = litedramcore_bankmachine3_sink_sink_payload_addr;
+assign litedramcore_bankmachine3_source_source_valid = litedramcore_bankmachine3_pipe_valid_source_valid;
+assign litedramcore_bankmachine3_pipe_valid_source_ready = litedramcore_bankmachine3_source_source_ready;
+assign litedramcore_bankmachine3_source_source_first = litedramcore_bankmachine3_pipe_valid_source_first;
+assign litedramcore_bankmachine3_source_source_last = litedramcore_bankmachine3_pipe_valid_source_last;
+assign litedramcore_bankmachine3_source_source_payload_we = litedramcore_bankmachine3_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine3_source_source_payload_addr = litedramcore_bankmachine3_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_litedramcore_bankmachine3_next_state <= 3'd0;
+ litedramcore_litedramcore_bankmachine3_next_state <= litedramcore_litedramcore_bankmachine3_state;
+ case (litedramcore_litedramcore_bankmachine3_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ if (litedramcore_bankmachine3_cmd_ready) begin
+ litedramcore_litedramcore_bankmachine3_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_litedramcore_bankmachine3_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ if (litedramcore_bankmachine3_cmd_ready) begin
+ litedramcore_litedramcore_bankmachine3_next_state <= 3'd6;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine3_refresh_req)) begin
+ litedramcore_litedramcore_bankmachine3_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_litedramcore_bankmachine3_next_state <= 2'd3;
+ end
+ 3'd6: begin
+ litedramcore_litedramcore_bankmachine3_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ litedramcore_litedramcore_bankmachine3_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin
+ litedramcore_litedramcore_bankmachine3_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_litedramcore_bankmachine3_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_litedramcore_bankmachine3_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_refresh_gnt <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine3_twtpcon_ready) begin
+ litedramcore_bankmachine3_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_row_open <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_valid <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine3_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ litedramcore_bankmachine3_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_row_close <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine3_state)
+ 1'd1: begin
+ litedramcore_bankmachine3_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine3_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine3_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine3_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine3_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if (litedramcore_bankmachine3_source_source_payload_we) begin
+ litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine3_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if (litedramcore_bankmachine3_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if (litedramcore_bankmachine3_source_source_payload_we) begin
+ litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if (litedramcore_bankmachine3_source_source_payload_we) begin
+ litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if (litedramcore_bankmachine3_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+assign litedramcore_bankmachine4_sink_valid = litedramcore_bankmachine4_req_valid;
+assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_sink_ready;
+assign litedramcore_bankmachine4_sink_payload_we = litedramcore_bankmachine4_req_we;
+assign litedramcore_bankmachine4_sink_payload_addr = litedramcore_bankmachine4_req_addr;
+assign litedramcore_bankmachine4_sink_sink_valid = litedramcore_bankmachine4_source_valid;
+assign litedramcore_bankmachine4_source_ready = litedramcore_bankmachine4_sink_sink_ready;
+assign litedramcore_bankmachine4_sink_sink_first = litedramcore_bankmachine4_source_first;
+assign litedramcore_bankmachine4_sink_sink_last = litedramcore_bankmachine4_source_last;
+assign litedramcore_bankmachine4_sink_sink_payload_we = litedramcore_bankmachine4_source_payload_we;
+assign litedramcore_bankmachine4_sink_sink_payload_addr = litedramcore_bankmachine4_source_payload_addr;
+assign litedramcore_bankmachine4_source_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid);
+assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_source_valid | litedramcore_bankmachine4_source_source_valid);
+assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_source_source_payload_addr[21:7]);
assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
always @(*) begin
- litedramcore_bankmachine4_cmd_payload_a <= 15'd0;
- if (litedramcore_bankmachine4_row_col_n_addr_sel) begin
- litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7];
- end else begin
- litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine4_cmd_payload_a <= 15'd0;
+ if (litedramcore_bankmachine4_row_col_n_addr_sel) begin
+ litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_source_source_payload_addr[21:7];
+ end else begin
+ litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write);
assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
always @(*) begin
- litedramcore_bankmachine4_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine4_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7])) begin
- litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine4_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | litedramcore_bankmachine4_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re);
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine4_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_litedramcore_bankmachine4_next_state <= 3'd0;
- litedramcore_litedramcore_bankmachine4_next_state <= litedramcore_litedramcore_bankmachine4_state;
- case (litedramcore_litedramcore_bankmachine4_state)
- 1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- if (litedramcore_bankmachine4_cmd_ready) begin
- litedramcore_litedramcore_bankmachine4_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_litedramcore_bankmachine4_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- if (litedramcore_bankmachine4_cmd_ready) begin
- litedramcore_litedramcore_bankmachine4_next_state <= 3'd6;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine4_refresh_req)) begin
- litedramcore_litedramcore_bankmachine4_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_litedramcore_bankmachine4_next_state <= 2'd3;
- end
- 3'd6: begin
- litedramcore_litedramcore_bankmachine4_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- litedramcore_litedramcore_bankmachine4_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin
- litedramcore_litedramcore_bankmachine4_next_state <= 2'd2;
- end
- end else begin
- litedramcore_litedramcore_bankmachine4_next_state <= 1'd1;
- end
- end else begin
- litedramcore_litedramcore_bankmachine4_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_row_open <= 1'd0;
- case (litedramcore_litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_row_close <= 1'd0;
- case (litedramcore_litedramcore_bankmachine4_state)
- 1'd1: begin
- litedramcore_bankmachine4_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine4_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine4_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
- case (litedramcore_litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
- case (litedramcore_litedramcore_bankmachine4_state)
- 1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
- case (litedramcore_litedramcore_bankmachine4_state)
- 1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_litedramcore_bankmachine4_state)
- 1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
- case (litedramcore_litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
- case (litedramcore_litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
- case (litedramcore_litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
- case (litedramcore_litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_refresh_gnt <= 1'd0;
- case (litedramcore_litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine4_twtpcon_ready) begin
- litedramcore_bankmachine4_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_cmd_valid <= 1'd0;
- case (litedramcore_litedramcore_bankmachine4_state)
- 1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- litedramcore_bankmachine4_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine5_req_valid;
-assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine5_req_we;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine5_req_addr;
-assign litedramcore_bankmachine5_cmd_buffer_sink_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine5_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine5_cmd_buffer_sink_first = litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine5_cmd_buffer_sink_last = litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine5_cmd_buffer_sink_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine5_cmd_buffer_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid);
-assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine5_cmd_buffer_source_valid);
-assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7]);
+ litedramcore_bankmachine4_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine4_source_valid & litedramcore_bankmachine4_source_source_valid)) begin
+ if ((litedramcore_bankmachine4_source_payload_addr[21:7] != litedramcore_bankmachine4_source_source_payload_addr[21:7])) begin
+ litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine4_syncfifo4_din = {litedramcore_bankmachine4_fifo_in_last, litedramcore_bankmachine4_fifo_in_first, litedramcore_bankmachine4_fifo_in_payload_addr, litedramcore_bankmachine4_fifo_in_payload_we};
+assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout;
+assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout;
+assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout;
+assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout;
+assign litedramcore_bankmachine4_sink_ready = litedramcore_bankmachine4_syncfifo4_writable;
+assign litedramcore_bankmachine4_syncfifo4_we = litedramcore_bankmachine4_sink_valid;
+assign litedramcore_bankmachine4_fifo_in_first = litedramcore_bankmachine4_sink_first;
+assign litedramcore_bankmachine4_fifo_in_last = litedramcore_bankmachine4_sink_last;
+assign litedramcore_bankmachine4_fifo_in_payload_we = litedramcore_bankmachine4_sink_payload_we;
+assign litedramcore_bankmachine4_fifo_in_payload_addr = litedramcore_bankmachine4_sink_payload_addr;
+assign litedramcore_bankmachine4_source_valid = litedramcore_bankmachine4_syncfifo4_readable;
+assign litedramcore_bankmachine4_source_first = litedramcore_bankmachine4_fifo_out_first;
+assign litedramcore_bankmachine4_source_last = litedramcore_bankmachine4_fifo_out_last;
+assign litedramcore_bankmachine4_source_payload_we = litedramcore_bankmachine4_fifo_out_payload_we;
+assign litedramcore_bankmachine4_source_payload_addr = litedramcore_bankmachine4_fifo_out_payload_addr;
+assign litedramcore_bankmachine4_syncfifo4_re = litedramcore_bankmachine4_source_ready;
+always @(*) begin
+ litedramcore_bankmachine4_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine4_replace) begin
+ litedramcore_bankmachine4_wrport_adr <= (litedramcore_bankmachine4_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine4_wrport_adr <= litedramcore_bankmachine4_produce;
+ end
+end
+assign litedramcore_bankmachine4_wrport_dat_w = litedramcore_bankmachine4_syncfifo4_din;
+assign litedramcore_bankmachine4_wrport_we = (litedramcore_bankmachine4_syncfifo4_we & (litedramcore_bankmachine4_syncfifo4_writable | litedramcore_bankmachine4_replace));
+assign litedramcore_bankmachine4_do_read = (litedramcore_bankmachine4_syncfifo4_readable & litedramcore_bankmachine4_syncfifo4_re);
+assign litedramcore_bankmachine4_rdport_adr = litedramcore_bankmachine4_consume;
+assign litedramcore_bankmachine4_syncfifo4_dout = litedramcore_bankmachine4_rdport_dat_r;
+assign litedramcore_bankmachine4_syncfifo4_writable = (litedramcore_bankmachine4_level != 5'd16);
+assign litedramcore_bankmachine4_syncfifo4_readable = (litedramcore_bankmachine4_level != 1'd0);
+assign litedramcore_bankmachine4_pipe_valid_sink_ready = ((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready);
+assign litedramcore_bankmachine4_pipe_valid_sink_valid = litedramcore_bankmachine4_sink_sink_valid;
+assign litedramcore_bankmachine4_sink_sink_ready = litedramcore_bankmachine4_pipe_valid_sink_ready;
+assign litedramcore_bankmachine4_pipe_valid_sink_first = litedramcore_bankmachine4_sink_sink_first;
+assign litedramcore_bankmachine4_pipe_valid_sink_last = litedramcore_bankmachine4_sink_sink_last;
+assign litedramcore_bankmachine4_pipe_valid_sink_payload_we = litedramcore_bankmachine4_sink_sink_payload_we;
+assign litedramcore_bankmachine4_pipe_valid_sink_payload_addr = litedramcore_bankmachine4_sink_sink_payload_addr;
+assign litedramcore_bankmachine4_source_source_valid = litedramcore_bankmachine4_pipe_valid_source_valid;
+assign litedramcore_bankmachine4_pipe_valid_source_ready = litedramcore_bankmachine4_source_source_ready;
+assign litedramcore_bankmachine4_source_source_first = litedramcore_bankmachine4_pipe_valid_source_first;
+assign litedramcore_bankmachine4_source_source_last = litedramcore_bankmachine4_pipe_valid_source_last;
+assign litedramcore_bankmachine4_source_source_payload_we = litedramcore_bankmachine4_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine4_source_source_payload_addr = litedramcore_bankmachine4_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_litedramcore_bankmachine4_next_state <= 3'd0;
+ litedramcore_litedramcore_bankmachine4_next_state <= litedramcore_litedramcore_bankmachine4_state;
+ case (litedramcore_litedramcore_bankmachine4_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ if (litedramcore_bankmachine4_cmd_ready) begin
+ litedramcore_litedramcore_bankmachine4_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_litedramcore_bankmachine4_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ if (litedramcore_bankmachine4_cmd_ready) begin
+ litedramcore_litedramcore_bankmachine4_next_state <= 3'd6;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine4_refresh_req)) begin
+ litedramcore_litedramcore_bankmachine4_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_litedramcore_bankmachine4_next_state <= 2'd3;
+ end
+ 3'd6: begin
+ litedramcore_litedramcore_bankmachine4_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ litedramcore_litedramcore_bankmachine4_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin
+ litedramcore_litedramcore_bankmachine4_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_litedramcore_bankmachine4_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_litedramcore_bankmachine4_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine4_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine4_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if (litedramcore_bankmachine4_source_source_payload_we) begin
+ litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine4_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if (litedramcore_bankmachine4_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if (litedramcore_bankmachine4_source_source_payload_we) begin
+ litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if (litedramcore_bankmachine4_source_source_payload_we) begin
+ litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if (litedramcore_bankmachine4_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_refresh_gnt <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine4_twtpcon_ready) begin
+ litedramcore_bankmachine4_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_row_open <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ litedramcore_bankmachine4_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_valid <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine4_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ litedramcore_bankmachine4_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ litedramcore_bankmachine4_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_row_close <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine4_state)
+ 1'd1: begin
+ litedramcore_bankmachine4_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine4_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine4_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+assign litedramcore_bankmachine5_sink_valid = litedramcore_bankmachine5_req_valid;
+assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_sink_ready;
+assign litedramcore_bankmachine5_sink_payload_we = litedramcore_bankmachine5_req_we;
+assign litedramcore_bankmachine5_sink_payload_addr = litedramcore_bankmachine5_req_addr;
+assign litedramcore_bankmachine5_sink_sink_valid = litedramcore_bankmachine5_source_valid;
+assign litedramcore_bankmachine5_source_ready = litedramcore_bankmachine5_sink_sink_ready;
+assign litedramcore_bankmachine5_sink_sink_first = litedramcore_bankmachine5_source_first;
+assign litedramcore_bankmachine5_sink_sink_last = litedramcore_bankmachine5_source_last;
+assign litedramcore_bankmachine5_sink_sink_payload_we = litedramcore_bankmachine5_source_payload_we;
+assign litedramcore_bankmachine5_sink_sink_payload_addr = litedramcore_bankmachine5_source_payload_addr;
+assign litedramcore_bankmachine5_source_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid);
+assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_source_valid | litedramcore_bankmachine5_source_source_valid);
+assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_source_source_payload_addr[21:7]);
assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
always @(*) begin
- litedramcore_bankmachine5_cmd_payload_a <= 15'd0;
- if (litedramcore_bankmachine5_row_col_n_addr_sel) begin
- litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7];
- end else begin
- litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine5_cmd_payload_a <= 15'd0;
+ if (litedramcore_bankmachine5_row_col_n_addr_sel) begin
+ litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_source_source_payload_addr[21:7];
+ end else begin
+ litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write);
assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
always @(*) begin
- litedramcore_bankmachine5_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine5_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7])) begin
- litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine5_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | litedramcore_bankmachine5_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re);
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine5_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_litedramcore_bankmachine5_next_state <= 3'd0;
- litedramcore_litedramcore_bankmachine5_next_state <= litedramcore_litedramcore_bankmachine5_state;
- case (litedramcore_litedramcore_bankmachine5_state)
- 1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- if (litedramcore_bankmachine5_cmd_ready) begin
- litedramcore_litedramcore_bankmachine5_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_litedramcore_bankmachine5_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- if (litedramcore_bankmachine5_cmd_ready) begin
- litedramcore_litedramcore_bankmachine5_next_state <= 3'd6;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine5_refresh_req)) begin
- litedramcore_litedramcore_bankmachine5_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_litedramcore_bankmachine5_next_state <= 2'd3;
- end
- 3'd6: begin
- litedramcore_litedramcore_bankmachine5_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- litedramcore_litedramcore_bankmachine5_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin
- litedramcore_litedramcore_bankmachine5_next_state <= 2'd2;
- end
- end else begin
- litedramcore_litedramcore_bankmachine5_next_state <= 1'd1;
- end
- end else begin
- litedramcore_litedramcore_bankmachine5_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_row_open <= 1'd0;
- case (litedramcore_litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_row_close <= 1'd0;
- case (litedramcore_litedramcore_bankmachine5_state)
- 1'd1: begin
- litedramcore_bankmachine5_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine5_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine5_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
- case (litedramcore_litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
- case (litedramcore_litedramcore_bankmachine5_state)
- 1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
- case (litedramcore_litedramcore_bankmachine5_state)
- 1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_litedramcore_bankmachine5_state)
- 1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
- case (litedramcore_litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
- case (litedramcore_litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
- case (litedramcore_litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
- case (litedramcore_litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_refresh_gnt <= 1'd0;
- case (litedramcore_litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine5_twtpcon_ready) begin
- litedramcore_bankmachine5_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd0;
- case (litedramcore_litedramcore_bankmachine5_state)
- 1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine6_req_valid;
-assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine6_req_we;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine6_req_addr;
-assign litedramcore_bankmachine6_cmd_buffer_sink_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine6_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine6_cmd_buffer_sink_first = litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine6_cmd_buffer_sink_last = litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine6_cmd_buffer_sink_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine6_cmd_buffer_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid);
-assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine6_cmd_buffer_source_valid);
-assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7]);
+ litedramcore_bankmachine5_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine5_source_valid & litedramcore_bankmachine5_source_source_valid)) begin
+ if ((litedramcore_bankmachine5_source_payload_addr[21:7] != litedramcore_bankmachine5_source_source_payload_addr[21:7])) begin
+ litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine5_syncfifo5_din = {litedramcore_bankmachine5_fifo_in_last, litedramcore_bankmachine5_fifo_in_first, litedramcore_bankmachine5_fifo_in_payload_addr, litedramcore_bankmachine5_fifo_in_payload_we};
+assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout;
+assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout;
+assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout;
+assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout;
+assign litedramcore_bankmachine5_sink_ready = litedramcore_bankmachine5_syncfifo5_writable;
+assign litedramcore_bankmachine5_syncfifo5_we = litedramcore_bankmachine5_sink_valid;
+assign litedramcore_bankmachine5_fifo_in_first = litedramcore_bankmachine5_sink_first;
+assign litedramcore_bankmachine5_fifo_in_last = litedramcore_bankmachine5_sink_last;
+assign litedramcore_bankmachine5_fifo_in_payload_we = litedramcore_bankmachine5_sink_payload_we;
+assign litedramcore_bankmachine5_fifo_in_payload_addr = litedramcore_bankmachine5_sink_payload_addr;
+assign litedramcore_bankmachine5_source_valid = litedramcore_bankmachine5_syncfifo5_readable;
+assign litedramcore_bankmachine5_source_first = litedramcore_bankmachine5_fifo_out_first;
+assign litedramcore_bankmachine5_source_last = litedramcore_bankmachine5_fifo_out_last;
+assign litedramcore_bankmachine5_source_payload_we = litedramcore_bankmachine5_fifo_out_payload_we;
+assign litedramcore_bankmachine5_source_payload_addr = litedramcore_bankmachine5_fifo_out_payload_addr;
+assign litedramcore_bankmachine5_syncfifo5_re = litedramcore_bankmachine5_source_ready;
+always @(*) begin
+ litedramcore_bankmachine5_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine5_replace) begin
+ litedramcore_bankmachine5_wrport_adr <= (litedramcore_bankmachine5_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine5_wrport_adr <= litedramcore_bankmachine5_produce;
+ end
+end
+assign litedramcore_bankmachine5_wrport_dat_w = litedramcore_bankmachine5_syncfifo5_din;
+assign litedramcore_bankmachine5_wrport_we = (litedramcore_bankmachine5_syncfifo5_we & (litedramcore_bankmachine5_syncfifo5_writable | litedramcore_bankmachine5_replace));
+assign litedramcore_bankmachine5_do_read = (litedramcore_bankmachine5_syncfifo5_readable & litedramcore_bankmachine5_syncfifo5_re);
+assign litedramcore_bankmachine5_rdport_adr = litedramcore_bankmachine5_consume;
+assign litedramcore_bankmachine5_syncfifo5_dout = litedramcore_bankmachine5_rdport_dat_r;
+assign litedramcore_bankmachine5_syncfifo5_writable = (litedramcore_bankmachine5_level != 5'd16);
+assign litedramcore_bankmachine5_syncfifo5_readable = (litedramcore_bankmachine5_level != 1'd0);
+assign litedramcore_bankmachine5_pipe_valid_sink_ready = ((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready);
+assign litedramcore_bankmachine5_pipe_valid_sink_valid = litedramcore_bankmachine5_sink_sink_valid;
+assign litedramcore_bankmachine5_sink_sink_ready = litedramcore_bankmachine5_pipe_valid_sink_ready;
+assign litedramcore_bankmachine5_pipe_valid_sink_first = litedramcore_bankmachine5_sink_sink_first;
+assign litedramcore_bankmachine5_pipe_valid_sink_last = litedramcore_bankmachine5_sink_sink_last;
+assign litedramcore_bankmachine5_pipe_valid_sink_payload_we = litedramcore_bankmachine5_sink_sink_payload_we;
+assign litedramcore_bankmachine5_pipe_valid_sink_payload_addr = litedramcore_bankmachine5_sink_sink_payload_addr;
+assign litedramcore_bankmachine5_source_source_valid = litedramcore_bankmachine5_pipe_valid_source_valid;
+assign litedramcore_bankmachine5_pipe_valid_source_ready = litedramcore_bankmachine5_source_source_ready;
+assign litedramcore_bankmachine5_source_source_first = litedramcore_bankmachine5_pipe_valid_source_first;
+assign litedramcore_bankmachine5_source_source_last = litedramcore_bankmachine5_pipe_valid_source_last;
+assign litedramcore_bankmachine5_source_source_payload_we = litedramcore_bankmachine5_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine5_source_source_payload_addr = litedramcore_bankmachine5_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_litedramcore_bankmachine5_next_state <= 3'd0;
+ litedramcore_litedramcore_bankmachine5_next_state <= litedramcore_litedramcore_bankmachine5_state;
+ case (litedramcore_litedramcore_bankmachine5_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ if (litedramcore_bankmachine5_cmd_ready) begin
+ litedramcore_litedramcore_bankmachine5_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_litedramcore_bankmachine5_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ if (litedramcore_bankmachine5_cmd_ready) begin
+ litedramcore_litedramcore_bankmachine5_next_state <= 3'd6;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine5_refresh_req)) begin
+ litedramcore_litedramcore_bankmachine5_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_litedramcore_bankmachine5_next_state <= 2'd3;
+ end
+ 3'd6: begin
+ litedramcore_litedramcore_bankmachine5_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ litedramcore_litedramcore_bankmachine5_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin
+ litedramcore_litedramcore_bankmachine5_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_litedramcore_bankmachine5_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_litedramcore_bankmachine5_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine5_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine5_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if (litedramcore_bankmachine5_source_source_payload_we) begin
+ litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine5_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if (litedramcore_bankmachine5_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if (litedramcore_bankmachine5_source_source_payload_we) begin
+ litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if (litedramcore_bankmachine5_source_source_payload_we) begin
+ litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if (litedramcore_bankmachine5_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_refresh_gnt <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine5_twtpcon_ready) begin
+ litedramcore_bankmachine5_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_row_open <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_valid <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine5_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_row_close <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine5_state)
+ 1'd1: begin
+ litedramcore_bankmachine5_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine5_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine5_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+assign litedramcore_bankmachine6_sink_valid = litedramcore_bankmachine6_req_valid;
+assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_sink_ready;
+assign litedramcore_bankmachine6_sink_payload_we = litedramcore_bankmachine6_req_we;
+assign litedramcore_bankmachine6_sink_payload_addr = litedramcore_bankmachine6_req_addr;
+assign litedramcore_bankmachine6_sink_sink_valid = litedramcore_bankmachine6_source_valid;
+assign litedramcore_bankmachine6_source_ready = litedramcore_bankmachine6_sink_sink_ready;
+assign litedramcore_bankmachine6_sink_sink_first = litedramcore_bankmachine6_source_first;
+assign litedramcore_bankmachine6_sink_sink_last = litedramcore_bankmachine6_source_last;
+assign litedramcore_bankmachine6_sink_sink_payload_we = litedramcore_bankmachine6_source_payload_we;
+assign litedramcore_bankmachine6_sink_sink_payload_addr = litedramcore_bankmachine6_source_payload_addr;
+assign litedramcore_bankmachine6_source_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid);
+assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_source_valid | litedramcore_bankmachine6_source_source_valid);
+assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_source_source_payload_addr[21:7]);
assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
always @(*) begin
- litedramcore_bankmachine6_cmd_payload_a <= 15'd0;
- if (litedramcore_bankmachine6_row_col_n_addr_sel) begin
- litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7];
- end else begin
- litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine6_cmd_payload_a <= 15'd0;
+ if (litedramcore_bankmachine6_row_col_n_addr_sel) begin
+ litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_source_source_payload_addr[21:7];
+ end else begin
+ litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write);
assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
always @(*) begin
- litedramcore_bankmachine6_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine6_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7])) begin
- litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine6_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | litedramcore_bankmachine6_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re);
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine6_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_litedramcore_bankmachine6_next_state <= 3'd0;
- litedramcore_litedramcore_bankmachine6_next_state <= litedramcore_litedramcore_bankmachine6_state;
- case (litedramcore_litedramcore_bankmachine6_state)
- 1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- if (litedramcore_bankmachine6_cmd_ready) begin
- litedramcore_litedramcore_bankmachine6_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_litedramcore_bankmachine6_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- if (litedramcore_bankmachine6_cmd_ready) begin
- litedramcore_litedramcore_bankmachine6_next_state <= 3'd6;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine6_refresh_req)) begin
- litedramcore_litedramcore_bankmachine6_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_litedramcore_bankmachine6_next_state <= 2'd3;
- end
- 3'd6: begin
- litedramcore_litedramcore_bankmachine6_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- litedramcore_litedramcore_bankmachine6_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin
- litedramcore_litedramcore_bankmachine6_next_state <= 2'd2;
- end
- end else begin
- litedramcore_litedramcore_bankmachine6_next_state <= 1'd1;
- end
- end else begin
- litedramcore_litedramcore_bankmachine6_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_row_open <= 1'd0;
- case (litedramcore_litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_row_close <= 1'd0;
- case (litedramcore_litedramcore_bankmachine6_state)
- 1'd1: begin
- litedramcore_bankmachine6_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine6_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine6_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
- case (litedramcore_litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
- case (litedramcore_litedramcore_bankmachine6_state)
- 1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
- case (litedramcore_litedramcore_bankmachine6_state)
- 1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_litedramcore_bankmachine6_state)
- 1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
- case (litedramcore_litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
- case (litedramcore_litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
- case (litedramcore_litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
- case (litedramcore_litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_refresh_gnt <= 1'd0;
- case (litedramcore_litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine6_twtpcon_ready) begin
- litedramcore_bankmachine6_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_cmd_valid <= 1'd0;
- case (litedramcore_litedramcore_bankmachine6_state)
- 1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- litedramcore_bankmachine6_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine7_req_valid;
-assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine7_req_we;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine7_req_addr;
-assign litedramcore_bankmachine7_cmd_buffer_sink_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine7_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine7_cmd_buffer_sink_first = litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine7_cmd_buffer_sink_last = litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine7_cmd_buffer_sink_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine7_cmd_buffer_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid);
-assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine7_cmd_buffer_source_valid);
-assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7]);
+ litedramcore_bankmachine6_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine6_source_valid & litedramcore_bankmachine6_source_source_valid)) begin
+ if ((litedramcore_bankmachine6_source_payload_addr[21:7] != litedramcore_bankmachine6_source_source_payload_addr[21:7])) begin
+ litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine6_syncfifo6_din = {litedramcore_bankmachine6_fifo_in_last, litedramcore_bankmachine6_fifo_in_first, litedramcore_bankmachine6_fifo_in_payload_addr, litedramcore_bankmachine6_fifo_in_payload_we};
+assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout;
+assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout;
+assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout;
+assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout;
+assign litedramcore_bankmachine6_sink_ready = litedramcore_bankmachine6_syncfifo6_writable;
+assign litedramcore_bankmachine6_syncfifo6_we = litedramcore_bankmachine6_sink_valid;
+assign litedramcore_bankmachine6_fifo_in_first = litedramcore_bankmachine6_sink_first;
+assign litedramcore_bankmachine6_fifo_in_last = litedramcore_bankmachine6_sink_last;
+assign litedramcore_bankmachine6_fifo_in_payload_we = litedramcore_bankmachine6_sink_payload_we;
+assign litedramcore_bankmachine6_fifo_in_payload_addr = litedramcore_bankmachine6_sink_payload_addr;
+assign litedramcore_bankmachine6_source_valid = litedramcore_bankmachine6_syncfifo6_readable;
+assign litedramcore_bankmachine6_source_first = litedramcore_bankmachine6_fifo_out_first;
+assign litedramcore_bankmachine6_source_last = litedramcore_bankmachine6_fifo_out_last;
+assign litedramcore_bankmachine6_source_payload_we = litedramcore_bankmachine6_fifo_out_payload_we;
+assign litedramcore_bankmachine6_source_payload_addr = litedramcore_bankmachine6_fifo_out_payload_addr;
+assign litedramcore_bankmachine6_syncfifo6_re = litedramcore_bankmachine6_source_ready;
+always @(*) begin
+ litedramcore_bankmachine6_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine6_replace) begin
+ litedramcore_bankmachine6_wrport_adr <= (litedramcore_bankmachine6_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine6_wrport_adr <= litedramcore_bankmachine6_produce;
+ end
+end
+assign litedramcore_bankmachine6_wrport_dat_w = litedramcore_bankmachine6_syncfifo6_din;
+assign litedramcore_bankmachine6_wrport_we = (litedramcore_bankmachine6_syncfifo6_we & (litedramcore_bankmachine6_syncfifo6_writable | litedramcore_bankmachine6_replace));
+assign litedramcore_bankmachine6_do_read = (litedramcore_bankmachine6_syncfifo6_readable & litedramcore_bankmachine6_syncfifo6_re);
+assign litedramcore_bankmachine6_rdport_adr = litedramcore_bankmachine6_consume;
+assign litedramcore_bankmachine6_syncfifo6_dout = litedramcore_bankmachine6_rdport_dat_r;
+assign litedramcore_bankmachine6_syncfifo6_writable = (litedramcore_bankmachine6_level != 5'd16);
+assign litedramcore_bankmachine6_syncfifo6_readable = (litedramcore_bankmachine6_level != 1'd0);
+assign litedramcore_bankmachine6_pipe_valid_sink_ready = ((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready);
+assign litedramcore_bankmachine6_pipe_valid_sink_valid = litedramcore_bankmachine6_sink_sink_valid;
+assign litedramcore_bankmachine6_sink_sink_ready = litedramcore_bankmachine6_pipe_valid_sink_ready;
+assign litedramcore_bankmachine6_pipe_valid_sink_first = litedramcore_bankmachine6_sink_sink_first;
+assign litedramcore_bankmachine6_pipe_valid_sink_last = litedramcore_bankmachine6_sink_sink_last;
+assign litedramcore_bankmachine6_pipe_valid_sink_payload_we = litedramcore_bankmachine6_sink_sink_payload_we;
+assign litedramcore_bankmachine6_pipe_valid_sink_payload_addr = litedramcore_bankmachine6_sink_sink_payload_addr;
+assign litedramcore_bankmachine6_source_source_valid = litedramcore_bankmachine6_pipe_valid_source_valid;
+assign litedramcore_bankmachine6_pipe_valid_source_ready = litedramcore_bankmachine6_source_source_ready;
+assign litedramcore_bankmachine6_source_source_first = litedramcore_bankmachine6_pipe_valid_source_first;
+assign litedramcore_bankmachine6_source_source_last = litedramcore_bankmachine6_pipe_valid_source_last;
+assign litedramcore_bankmachine6_source_source_payload_we = litedramcore_bankmachine6_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine6_source_source_payload_addr = litedramcore_bankmachine6_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_litedramcore_bankmachine6_next_state <= 3'd0;
+ litedramcore_litedramcore_bankmachine6_next_state <= litedramcore_litedramcore_bankmachine6_state;
+ case (litedramcore_litedramcore_bankmachine6_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ if (litedramcore_bankmachine6_cmd_ready) begin
+ litedramcore_litedramcore_bankmachine6_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_litedramcore_bankmachine6_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ if (litedramcore_bankmachine6_cmd_ready) begin
+ litedramcore_litedramcore_bankmachine6_next_state <= 3'd6;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine6_refresh_req)) begin
+ litedramcore_litedramcore_bankmachine6_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_litedramcore_bankmachine6_next_state <= 2'd3;
+ end
+ 3'd6: begin
+ litedramcore_litedramcore_bankmachine6_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ litedramcore_litedramcore_bankmachine6_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin
+ litedramcore_litedramcore_bankmachine6_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_litedramcore_bankmachine6_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_litedramcore_bankmachine6_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if (litedramcore_bankmachine6_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if (litedramcore_bankmachine6_source_source_payload_we) begin
+ litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if (litedramcore_bankmachine6_source_source_payload_we) begin
+ litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if (litedramcore_bankmachine6_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_row_open <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_valid <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine6_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ litedramcore_bankmachine6_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_row_close <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine6_state)
+ 1'd1: begin
+ litedramcore_bankmachine6_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine6_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine6_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_refresh_gnt <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine6_twtpcon_ready) begin
+ litedramcore_bankmachine6_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine6_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine6_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if (litedramcore_bankmachine6_source_source_payload_we) begin
+ litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine6_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+assign litedramcore_bankmachine7_sink_valid = litedramcore_bankmachine7_req_valid;
+assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_sink_ready;
+assign litedramcore_bankmachine7_sink_payload_we = litedramcore_bankmachine7_req_we;
+assign litedramcore_bankmachine7_sink_payload_addr = litedramcore_bankmachine7_req_addr;
+assign litedramcore_bankmachine7_sink_sink_valid = litedramcore_bankmachine7_source_valid;
+assign litedramcore_bankmachine7_source_ready = litedramcore_bankmachine7_sink_sink_ready;
+assign litedramcore_bankmachine7_sink_sink_first = litedramcore_bankmachine7_source_first;
+assign litedramcore_bankmachine7_sink_sink_last = litedramcore_bankmachine7_source_last;
+assign litedramcore_bankmachine7_sink_sink_payload_we = litedramcore_bankmachine7_source_payload_we;
+assign litedramcore_bankmachine7_sink_sink_payload_addr = litedramcore_bankmachine7_source_payload_addr;
+assign litedramcore_bankmachine7_source_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid);
+assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_source_valid | litedramcore_bankmachine7_source_source_valid);
+assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_source_source_payload_addr[21:7]);
assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
always @(*) begin
- litedramcore_bankmachine7_cmd_payload_a <= 15'd0;
- if (litedramcore_bankmachine7_row_col_n_addr_sel) begin
- litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7];
- end else begin
- litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine7_cmd_payload_a <= 15'd0;
+ if (litedramcore_bankmachine7_row_col_n_addr_sel) begin
+ litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_source_source_payload_addr[21:7];
+ end else begin
+ litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write);
assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
always @(*) begin
- litedramcore_bankmachine7_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine7_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[21:7] != litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7])) begin
- litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine7_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | litedramcore_bankmachine7_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re);
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine7_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_litedramcore_bankmachine7_next_state <= 3'd0;
- litedramcore_litedramcore_bankmachine7_next_state <= litedramcore_litedramcore_bankmachine7_state;
- case (litedramcore_litedramcore_bankmachine7_state)
- 1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- if (litedramcore_bankmachine7_cmd_ready) begin
- litedramcore_litedramcore_bankmachine7_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_litedramcore_bankmachine7_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- if (litedramcore_bankmachine7_cmd_ready) begin
- litedramcore_litedramcore_bankmachine7_next_state <= 3'd6;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine7_refresh_req)) begin
- litedramcore_litedramcore_bankmachine7_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_litedramcore_bankmachine7_next_state <= 2'd3;
- end
- 3'd6: begin
- litedramcore_litedramcore_bankmachine7_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- litedramcore_litedramcore_bankmachine7_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin
- litedramcore_litedramcore_bankmachine7_next_state <= 2'd2;
- end
- end else begin
- litedramcore_litedramcore_bankmachine7_next_state <= 1'd1;
- end
- end else begin
- litedramcore_litedramcore_bankmachine7_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_row_open <= 1'd0;
- case (litedramcore_litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_row_close <= 1'd0;
- case (litedramcore_litedramcore_bankmachine7_state)
- 1'd1: begin
- litedramcore_bankmachine7_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine7_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine7_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
- case (litedramcore_litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
- case (litedramcore_litedramcore_bankmachine7_state)
- 1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
- case (litedramcore_litedramcore_bankmachine7_state)
- 1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_litedramcore_bankmachine7_state)
- 1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
- case (litedramcore_litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
- case (litedramcore_litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
- case (litedramcore_litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
- case (litedramcore_litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_refresh_gnt <= 1'd0;
- case (litedramcore_litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine7_twtpcon_ready) begin
- litedramcore_bankmachine7_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_cmd_valid <= 1'd0;
- case (litedramcore_litedramcore_bankmachine7_state)
- 1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- litedramcore_bankmachine7_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
+ litedramcore_bankmachine7_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine7_source_valid & litedramcore_bankmachine7_source_source_valid)) begin
+ if ((litedramcore_bankmachine7_source_payload_addr[21:7] != litedramcore_bankmachine7_source_source_payload_addr[21:7])) begin
+ litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine7_syncfifo7_din = {litedramcore_bankmachine7_fifo_in_last, litedramcore_bankmachine7_fifo_in_first, litedramcore_bankmachine7_fifo_in_payload_addr, litedramcore_bankmachine7_fifo_in_payload_we};
+assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout;
+assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout;
+assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout;
+assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout;
+assign litedramcore_bankmachine7_sink_ready = litedramcore_bankmachine7_syncfifo7_writable;
+assign litedramcore_bankmachine7_syncfifo7_we = litedramcore_bankmachine7_sink_valid;
+assign litedramcore_bankmachine7_fifo_in_first = litedramcore_bankmachine7_sink_first;
+assign litedramcore_bankmachine7_fifo_in_last = litedramcore_bankmachine7_sink_last;
+assign litedramcore_bankmachine7_fifo_in_payload_we = litedramcore_bankmachine7_sink_payload_we;
+assign litedramcore_bankmachine7_fifo_in_payload_addr = litedramcore_bankmachine7_sink_payload_addr;
+assign litedramcore_bankmachine7_source_valid = litedramcore_bankmachine7_syncfifo7_readable;
+assign litedramcore_bankmachine7_source_first = litedramcore_bankmachine7_fifo_out_first;
+assign litedramcore_bankmachine7_source_last = litedramcore_bankmachine7_fifo_out_last;
+assign litedramcore_bankmachine7_source_payload_we = litedramcore_bankmachine7_fifo_out_payload_we;
+assign litedramcore_bankmachine7_source_payload_addr = litedramcore_bankmachine7_fifo_out_payload_addr;
+assign litedramcore_bankmachine7_syncfifo7_re = litedramcore_bankmachine7_source_ready;
+always @(*) begin
+ litedramcore_bankmachine7_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine7_replace) begin
+ litedramcore_bankmachine7_wrport_adr <= (litedramcore_bankmachine7_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine7_wrport_adr <= litedramcore_bankmachine7_produce;
+ end
+end
+assign litedramcore_bankmachine7_wrport_dat_w = litedramcore_bankmachine7_syncfifo7_din;
+assign litedramcore_bankmachine7_wrport_we = (litedramcore_bankmachine7_syncfifo7_we & (litedramcore_bankmachine7_syncfifo7_writable | litedramcore_bankmachine7_replace));
+assign litedramcore_bankmachine7_do_read = (litedramcore_bankmachine7_syncfifo7_readable & litedramcore_bankmachine7_syncfifo7_re);
+assign litedramcore_bankmachine7_rdport_adr = litedramcore_bankmachine7_consume;
+assign litedramcore_bankmachine7_syncfifo7_dout = litedramcore_bankmachine7_rdport_dat_r;
+assign litedramcore_bankmachine7_syncfifo7_writable = (litedramcore_bankmachine7_level != 5'd16);
+assign litedramcore_bankmachine7_syncfifo7_readable = (litedramcore_bankmachine7_level != 1'd0);
+assign litedramcore_bankmachine7_pipe_valid_sink_ready = ((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready);
+assign litedramcore_bankmachine7_pipe_valid_sink_valid = litedramcore_bankmachine7_sink_sink_valid;
+assign litedramcore_bankmachine7_sink_sink_ready = litedramcore_bankmachine7_pipe_valid_sink_ready;
+assign litedramcore_bankmachine7_pipe_valid_sink_first = litedramcore_bankmachine7_sink_sink_first;
+assign litedramcore_bankmachine7_pipe_valid_sink_last = litedramcore_bankmachine7_sink_sink_last;
+assign litedramcore_bankmachine7_pipe_valid_sink_payload_we = litedramcore_bankmachine7_sink_sink_payload_we;
+assign litedramcore_bankmachine7_pipe_valid_sink_payload_addr = litedramcore_bankmachine7_sink_sink_payload_addr;
+assign litedramcore_bankmachine7_source_source_valid = litedramcore_bankmachine7_pipe_valid_source_valid;
+assign litedramcore_bankmachine7_pipe_valid_source_ready = litedramcore_bankmachine7_source_source_ready;
+assign litedramcore_bankmachine7_source_source_first = litedramcore_bankmachine7_pipe_valid_source_first;
+assign litedramcore_bankmachine7_source_source_last = litedramcore_bankmachine7_pipe_valid_source_last;
+assign litedramcore_bankmachine7_source_source_payload_we = litedramcore_bankmachine7_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine7_source_source_payload_addr = litedramcore_bankmachine7_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_litedramcore_bankmachine7_next_state <= 3'd0;
+ litedramcore_litedramcore_bankmachine7_next_state <= litedramcore_litedramcore_bankmachine7_state;
+ case (litedramcore_litedramcore_bankmachine7_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ if (litedramcore_bankmachine7_cmd_ready) begin
+ litedramcore_litedramcore_bankmachine7_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_litedramcore_bankmachine7_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ if (litedramcore_bankmachine7_cmd_ready) begin
+ litedramcore_litedramcore_bankmachine7_next_state <= 3'd6;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine7_refresh_req)) begin
+ litedramcore_litedramcore_bankmachine7_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_litedramcore_bankmachine7_next_state <= 2'd3;
+ end
+ 3'd6: begin
+ litedramcore_litedramcore_bankmachine7_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ litedramcore_litedramcore_bankmachine7_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin
+ litedramcore_litedramcore_bankmachine7_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_litedramcore_bankmachine7_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_litedramcore_bankmachine7_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_refresh_gnt <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine7_twtpcon_ready) begin
+ litedramcore_bankmachine7_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_row_open <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_valid <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine7_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ litedramcore_bankmachine7_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_row_close <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine7_state)
+ 1'd1: begin
+ litedramcore_bankmachine7_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine7_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine7_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine7_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine7_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if (litedramcore_bankmachine7_source_source_payload_we) begin
+ litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine7_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if (litedramcore_bankmachine7_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if (litedramcore_bankmachine7_source_source_payload_we) begin
+ litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if (litedramcore_bankmachine7_source_source_payload_we) begin
+ litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
+ case (litedramcore_litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if (litedramcore_bankmachine7_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
end
assign litedramcore_trrdcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
assign litedramcore_tfawcon_valid = ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & ((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we)));
assign {litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
assign {litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
always @(*) begin
- litedramcore_choose_cmd_valids <= 8'd0;
- litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids <= 8'd0;
+ litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
end
assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids;
assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0;
assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4;
assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5;
always @(*) begin
- litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
- if (litedramcore_choose_cmd_cmd_valid) begin
- litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0;
- end
+ litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
+ if (litedramcore_choose_cmd_cmd_valid) begin
+ litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0;
+ end
end
always @(*) begin
- litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
- if (litedramcore_choose_cmd_cmd_valid) begin
- litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1;
- end
+ litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
+ if (litedramcore_choose_cmd_cmd_valid) begin
+ litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1;
+ end
end
always @(*) begin
- litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
- if (litedramcore_choose_cmd_cmd_valid) begin
- litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2;
- end
+ litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
+ if (litedramcore_choose_cmd_cmd_valid) begin
+ litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2;
+ end
end
always @(*) begin
- litedramcore_bankmachine0_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin
- litedramcore_bankmachine0_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin
- litedramcore_bankmachine0_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine0_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin
+ litedramcore_bankmachine0_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin
+ litedramcore_bankmachine0_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_bankmachine1_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin
- litedramcore_bankmachine1_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin
- litedramcore_bankmachine1_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine1_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin
+ litedramcore_bankmachine1_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin
+ litedramcore_bankmachine1_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_bankmachine2_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin
- litedramcore_bankmachine2_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin
- litedramcore_bankmachine2_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine2_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin
+ litedramcore_bankmachine2_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin
+ litedramcore_bankmachine2_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_bankmachine3_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin
- litedramcore_bankmachine3_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin
- litedramcore_bankmachine3_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine3_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin
+ litedramcore_bankmachine3_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin
+ litedramcore_bankmachine3_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_bankmachine4_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin
- litedramcore_bankmachine4_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin
- litedramcore_bankmachine4_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine4_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin
+ litedramcore_bankmachine4_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin
+ litedramcore_bankmachine4_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_bankmachine5_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin
- litedramcore_bankmachine5_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin
- litedramcore_bankmachine5_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine5_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin
+ litedramcore_bankmachine5_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin
+ litedramcore_bankmachine5_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_bankmachine6_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin
- litedramcore_bankmachine6_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin
- litedramcore_bankmachine6_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine6_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin
+ litedramcore_bankmachine6_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin
+ litedramcore_bankmachine6_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_bankmachine7_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin
- litedramcore_bankmachine7_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin
- litedramcore_bankmachine7_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine7_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin
+ litedramcore_bankmachine7_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin
+ litedramcore_bankmachine7_cmd_ready <= 1'd1;
+ end
end
assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid));
always @(*) begin
- litedramcore_choose_req_valids <= 8'd0;
- litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids <= 8'd0;
+ litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
end
assign litedramcore_choose_req_request = litedramcore_choose_req_valids;
assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6;
assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10;
assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11;
always @(*) begin
- litedramcore_choose_req_cmd_payload_cas <= 1'd0;
- if (litedramcore_choose_req_cmd_valid) begin
- litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3;
- end
+ litedramcore_choose_req_cmd_payload_cas <= 1'd0;
+ if (litedramcore_choose_req_cmd_valid) begin
+ litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3;
+ end
end
always @(*) begin
- litedramcore_choose_req_cmd_payload_ras <= 1'd0;
- if (litedramcore_choose_req_cmd_valid) begin
- litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4;
- end
+ litedramcore_choose_req_cmd_payload_ras <= 1'd0;
+ if (litedramcore_choose_req_cmd_valid) begin
+ litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4;
+ end
end
always @(*) begin
- litedramcore_choose_req_cmd_payload_we <= 1'd0;
- if (litedramcore_choose_req_cmd_valid) begin
- litedramcore_choose_req_cmd_payload_we <= t_array_muxed5;
- end
+ litedramcore_choose_req_cmd_payload_we <= 1'd0;
+ if (litedramcore_choose_req_cmd_valid) begin
+ litedramcore_choose_req_cmd_payload_we <= t_array_muxed5;
+ end
end
assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid));
assign litedramcore_dfi_p0_reset_n = 1'd1;
assign litedramcore_dfi_p1_odt = {1{litedramcore_steerer3}};
assign litedramcore_tfawcon_count = ((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]);
always @(*) begin
- litedramcore_litedramcore_multiplexer_next_state <= 4'd0;
- litedramcore_litedramcore_multiplexer_next_state <= litedramcore_litedramcore_multiplexer_state;
- case (litedramcore_litedramcore_multiplexer_state)
- 1'd1: begin
- if (litedramcore_read_available) begin
- if (((~litedramcore_write_available) | litedramcore_max_time1)) begin
- litedramcore_litedramcore_multiplexer_next_state <= 2'd3;
- end
- end
- if (litedramcore_go_to_refresh) begin
- litedramcore_litedramcore_multiplexer_next_state <= 2'd2;
- end
- end
- 2'd2: begin
- if (litedramcore_cmd_last) begin
- litedramcore_litedramcore_multiplexer_next_state <= 1'd0;
- end
- end
- 2'd3: begin
- if (litedramcore_twtrcon_ready) begin
- litedramcore_litedramcore_multiplexer_next_state <= 1'd0;
- end
- end
- 3'd4: begin
- litedramcore_litedramcore_multiplexer_next_state <= 3'd5;
- end
- 3'd5: begin
- litedramcore_litedramcore_multiplexer_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_litedramcore_multiplexer_next_state <= 3'd7;
- end
- 3'd7: begin
- litedramcore_litedramcore_multiplexer_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_litedramcore_multiplexer_next_state <= 4'd9;
- end
- 4'd9: begin
- litedramcore_litedramcore_multiplexer_next_state <= 4'd10;
- end
- 4'd10: begin
- litedramcore_litedramcore_multiplexer_next_state <= 4'd11;
- end
- 4'd11: begin
- litedramcore_litedramcore_multiplexer_next_state <= 4'd12;
- end
- 4'd12: begin
- litedramcore_litedramcore_multiplexer_next_state <= 4'd13;
- end
- 4'd13: begin
- litedramcore_litedramcore_multiplexer_next_state <= 4'd14;
- end
- 4'd14: begin
- litedramcore_litedramcore_multiplexer_next_state <= 4'd15;
- end
- 4'd15: begin
- litedramcore_litedramcore_multiplexer_next_state <= 1'd1;
- end
- default: begin
- if (litedramcore_write_available) begin
- if (((~litedramcore_read_available) | litedramcore_max_time0)) begin
- litedramcore_litedramcore_multiplexer_next_state <= 3'd4;
- end
- end
- if (litedramcore_go_to_refresh) begin
- litedramcore_litedramcore_multiplexer_next_state <= 2'd2;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_choose_req_cmd_ready <= 1'd0;
- case (litedramcore_litedramcore_multiplexer_state)
- 1'd1: begin
- if (1'd0) begin
- litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
- end else begin
- litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- 4'd11: begin
- end
- 4'd12: begin
- end
- 4'd13: begin
- end
- 4'd14: begin
- end
- 4'd15: begin
- end
- default: begin
- if (1'd0) begin
- litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
- end else begin
- litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_en1 <= 1'd0;
- case (litedramcore_litedramcore_multiplexer_state)
- 1'd1: begin
- litedramcore_en1 <= 1'd1;
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- 4'd11: begin
- end
- 4'd12: begin
- end
- 4'd13: begin
- end
- 4'd14: begin
- end
- 4'd15: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_steerer_sel0 <= 2'd0;
- case (litedramcore_litedramcore_multiplexer_state)
- 1'd1: begin
- litedramcore_steerer_sel0 <= 1'd0;
- if (1'd0) begin
- litedramcore_steerer_sel0 <= 2'd2;
- end
- if (1'd1) begin
- litedramcore_steerer_sel0 <= 1'd1;
- end
- end
- 2'd2: begin
- litedramcore_steerer_sel0 <= 2'd3;
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- 4'd11: begin
- end
- 4'd12: begin
- end
- 4'd13: begin
- end
- 4'd14: begin
- end
- 4'd15: begin
- end
- default: begin
- litedramcore_steerer_sel0 <= 1'd0;
- if (1'd1) begin
- litedramcore_steerer_sel0 <= 2'd2;
- end
- if (1'd0) begin
- litedramcore_steerer_sel0 <= 1'd1;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_steerer_sel1 <= 2'd0;
- case (litedramcore_litedramcore_multiplexer_state)
- 1'd1: begin
- litedramcore_steerer_sel1 <= 1'd0;
- if (1'd1) begin
- litedramcore_steerer_sel1 <= 2'd2;
- end
- if (1'd0) begin
- litedramcore_steerer_sel1 <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- 4'd11: begin
- end
- 4'd12: begin
- end
- 4'd13: begin
- end
- 4'd14: begin
- end
- 4'd15: begin
- end
- default: begin
- litedramcore_steerer_sel1 <= 1'd0;
- if (1'd0) begin
- litedramcore_steerer_sel1 <= 2'd2;
- end
- if (1'd1) begin
- litedramcore_steerer_sel1 <= 1'd1;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_choose_cmd_want_activates <= 1'd0;
- case (litedramcore_litedramcore_multiplexer_state)
- 1'd1: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- 4'd11: begin
- end
- 4'd12: begin
- end
- 4'd13: begin
- end
- 4'd14: begin
- end
- 4'd15: begin
- end
- default: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_cmd_ready <= 1'd0;
- case (litedramcore_litedramcore_multiplexer_state)
- 1'd1: begin
- end
- 2'd2: begin
- litedramcore_cmd_ready <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- 4'd11: begin
- end
- 4'd12: begin
- end
- 4'd13: begin
- end
- 4'd14: begin
- end
- 4'd15: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_choose_cmd_cmd_ready <= 1'd0;
- case (litedramcore_litedramcore_multiplexer_state)
- 1'd1: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- 4'd11: begin
- end
- 4'd12: begin
- end
- 4'd13: begin
- end
- 4'd14: begin
- end
- 4'd15: begin
- end
- default: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_choose_req_want_reads <= 1'd0;
- case (litedramcore_litedramcore_multiplexer_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- 4'd11: begin
- end
- 4'd12: begin
- end
- 4'd13: begin
- end
- 4'd14: begin
- end
- 4'd15: begin
- end
- default: begin
- litedramcore_choose_req_want_reads <= 1'd1;
- end
- endcase
-end
-always @(*) begin
- litedramcore_choose_req_want_writes <= 1'd0;
- case (litedramcore_litedramcore_multiplexer_state)
- 1'd1: begin
- litedramcore_choose_req_want_writes <= 1'd1;
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- 4'd11: begin
- end
- 4'd12: begin
- end
- 4'd13: begin
- end
- 4'd14: begin
- end
- 4'd15: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_en0 <= 1'd0;
- case (litedramcore_litedramcore_multiplexer_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- 4'd11: begin
- end
- 4'd12: begin
- end
- 4'd13: begin
- end
- 4'd14: begin
- end
- 4'd15: begin
- end
- default: begin
- litedramcore_en0 <= 1'd1;
- end
- endcase
+ litedramcore_litedramcore_multiplexer_next_state <= 4'd0;
+ litedramcore_litedramcore_multiplexer_next_state <= litedramcore_litedramcore_multiplexer_state;
+ case (litedramcore_litedramcore_multiplexer_state)
+ 1'd1: begin
+ if (litedramcore_read_available) begin
+ if (((~litedramcore_write_available) | litedramcore_max_time1)) begin
+ litedramcore_litedramcore_multiplexer_next_state <= 2'd3;
+ end
+ end
+ if (litedramcore_go_to_refresh) begin
+ litedramcore_litedramcore_multiplexer_next_state <= 2'd2;
+ end
+ end
+ 2'd2: begin
+ if (litedramcore_cmd_last) begin
+ litedramcore_litedramcore_multiplexer_next_state <= 1'd0;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_twtrcon_ready) begin
+ litedramcore_litedramcore_multiplexer_next_state <= 1'd0;
+ end
+ end
+ 3'd4: begin
+ litedramcore_litedramcore_multiplexer_next_state <= 3'd5;
+ end
+ 3'd5: begin
+ litedramcore_litedramcore_multiplexer_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_litedramcore_multiplexer_next_state <= 3'd7;
+ end
+ 3'd7: begin
+ litedramcore_litedramcore_multiplexer_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_litedramcore_multiplexer_next_state <= 4'd9;
+ end
+ 4'd9: begin
+ litedramcore_litedramcore_multiplexer_next_state <= 4'd10;
+ end
+ 4'd10: begin
+ litedramcore_litedramcore_multiplexer_next_state <= 4'd11;
+ end
+ 4'd11: begin
+ litedramcore_litedramcore_multiplexer_next_state <= 4'd12;
+ end
+ 4'd12: begin
+ litedramcore_litedramcore_multiplexer_next_state <= 4'd13;
+ end
+ 4'd13: begin
+ litedramcore_litedramcore_multiplexer_next_state <= 4'd14;
+ end
+ 4'd14: begin
+ litedramcore_litedramcore_multiplexer_next_state <= 4'd15;
+ end
+ 4'd15: begin
+ litedramcore_litedramcore_multiplexer_next_state <= 1'd1;
+ end
+ default: begin
+ if (litedramcore_write_available) begin
+ if (((~litedramcore_read_available) | litedramcore_max_time0)) begin
+ litedramcore_litedramcore_multiplexer_next_state <= 3'd4;
+ end
+ end
+ if (litedramcore_go_to_refresh) begin
+ litedramcore_litedramcore_multiplexer_next_state <= 2'd2;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_choose_req_cmd_ready <= 1'd0;
+ case (litedramcore_litedramcore_multiplexer_state)
+ 1'd1: begin
+ if (1'd0) begin
+ litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+ end else begin
+ litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ 4'd11: begin
+ end
+ 4'd12: begin
+ end
+ 4'd13: begin
+ end
+ 4'd14: begin
+ end
+ 4'd15: begin
+ end
+ default: begin
+ if (1'd0) begin
+ litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+ end else begin
+ litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_en1 <= 1'd0;
+ case (litedramcore_litedramcore_multiplexer_state)
+ 1'd1: begin
+ litedramcore_en1 <= 1'd1;
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ 4'd11: begin
+ end
+ 4'd12: begin
+ end
+ 4'd13: begin
+ end
+ 4'd14: begin
+ end
+ 4'd15: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_steerer_sel0 <= 2'd0;
+ case (litedramcore_litedramcore_multiplexer_state)
+ 1'd1: begin
+ litedramcore_steerer_sel0 <= 1'd0;
+ if (1'd0) begin
+ litedramcore_steerer_sel0 <= 2'd2;
+ end
+ if (1'd1) begin
+ litedramcore_steerer_sel0 <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ litedramcore_steerer_sel0 <= 2'd3;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ 4'd11: begin
+ end
+ 4'd12: begin
+ end
+ 4'd13: begin
+ end
+ 4'd14: begin
+ end
+ 4'd15: begin
+ end
+ default: begin
+ litedramcore_steerer_sel0 <= 1'd0;
+ if (1'd1) begin
+ litedramcore_steerer_sel0 <= 2'd2;
+ end
+ if (1'd0) begin
+ litedramcore_steerer_sel0 <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_steerer_sel1 <= 2'd0;
+ case (litedramcore_litedramcore_multiplexer_state)
+ 1'd1: begin
+ litedramcore_steerer_sel1 <= 1'd0;
+ if (1'd1) begin
+ litedramcore_steerer_sel1 <= 2'd2;
+ end
+ if (1'd0) begin
+ litedramcore_steerer_sel1 <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ 4'd11: begin
+ end
+ 4'd12: begin
+ end
+ 4'd13: begin
+ end
+ 4'd14: begin
+ end
+ 4'd15: begin
+ end
+ default: begin
+ litedramcore_steerer_sel1 <= 1'd0;
+ if (1'd0) begin
+ litedramcore_steerer_sel1 <= 2'd2;
+ end
+ if (1'd1) begin
+ litedramcore_steerer_sel1 <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_choose_cmd_want_activates <= 1'd0;
+ case (litedramcore_litedramcore_multiplexer_state)
+ 1'd1: begin
+ if (1'd0) begin
+ end else begin
+ litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ 4'd11: begin
+ end
+ 4'd12: begin
+ end
+ 4'd13: begin
+ end
+ 4'd14: begin
+ end
+ 4'd15: begin
+ end
+ default: begin
+ if (1'd0) begin
+ end else begin
+ litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_cmd_ready <= 1'd0;
+ case (litedramcore_litedramcore_multiplexer_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ litedramcore_cmd_ready <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ 4'd11: begin
+ end
+ 4'd12: begin
+ end
+ 4'd13: begin
+ end
+ 4'd14: begin
+ end
+ 4'd15: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_choose_cmd_cmd_ready <= 1'd0;
+ case (litedramcore_litedramcore_multiplexer_state)
+ 1'd1: begin
+ if (1'd0) begin
+ end else begin
+ litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ 4'd11: begin
+ end
+ 4'd12: begin
+ end
+ 4'd13: begin
+ end
+ 4'd14: begin
+ end
+ 4'd15: begin
+ end
+ default: begin
+ if (1'd0) begin
+ end else begin
+ litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_choose_req_want_reads <= 1'd0;
+ case (litedramcore_litedramcore_multiplexer_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ 4'd11: begin
+ end
+ 4'd12: begin
+ end
+ 4'd13: begin
+ end
+ 4'd14: begin
+ end
+ 4'd15: begin
+ end
+ default: begin
+ litedramcore_choose_req_want_reads <= 1'd1;
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_choose_req_want_writes <= 1'd0;
+ case (litedramcore_litedramcore_multiplexer_state)
+ 1'd1: begin
+ litedramcore_choose_req_want_writes <= 1'd1;
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ 4'd11: begin
+ end
+ 4'd12: begin
+ end
+ 4'd13: begin
+ end
+ 4'd14: begin
+ end
+ 4'd15: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_en0 <= 1'd0;
+ case (litedramcore_litedramcore_multiplexer_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ 4'd11: begin
+ end
+ 4'd12: begin
+ end
+ 4'd13: begin
+ end
+ 4'd14: begin
+ end
+ 4'd15: begin
+ end
+ default: begin
+ litedramcore_en0 <= 1'd1;
+ end
+ endcase
end
assign litedramcore_litedramcore_roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
assign litedramcore_litedramcore_roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock));
assign user_port_wdata_ready = litedramcore_litedramcore_new_master_wdata_ready3;
assign user_port_rdata_valid = litedramcore_litedramcore_new_master_rdata_valid13;
always @(*) begin
- litedramcore_interface_wdata <= 128'd0;
- case ({litedramcore_litedramcore_new_master_wdata_ready3})
- 1'd1: begin
- litedramcore_interface_wdata <= user_port_wdata_payload_data;
- end
- default: begin
- litedramcore_interface_wdata <= 1'd0;
- end
- endcase
-end
-always @(*) begin
- litedramcore_interface_wdata_we <= 16'd0;
- case ({litedramcore_litedramcore_new_master_wdata_ready3})
- 1'd1: begin
- litedramcore_interface_wdata_we <= user_port_wdata_payload_we;
- end
- default: begin
- litedramcore_interface_wdata_we <= 1'd0;
- end
- endcase
+ litedramcore_interface_wdata <= 128'd0;
+ case ({litedramcore_litedramcore_new_master_wdata_ready3})
+ 1'd1: begin
+ litedramcore_interface_wdata <= user_port_wdata_payload_data;
+ end
+ default: begin
+ litedramcore_interface_wdata <= 1'd0;
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_interface_wdata_we <= 16'd0;
+ case ({litedramcore_litedramcore_new_master_wdata_ready3})
+ 1'd1: begin
+ litedramcore_interface_wdata_we <= user_port_wdata_payload_we;
+ end
+ default: begin
+ litedramcore_interface_wdata_we <= 1'd0;
+ end
+ endcase
end
assign user_port_rdata_payload_data = litedramcore_interface_rdata;
assign litedramcore_litedramcore_roundrobin0_grant = 1'd0;
assign litedramcore_litedramcore_roundrobin6_grant = 1'd0;
assign litedramcore_litedramcore_roundrobin7_grant = 1'd0;
always @(*) begin
- litedramcore_next_state <= 2'd0;
- litedramcore_next_state <= litedramcore_state;
- case (litedramcore_state)
- 1'd1: begin
- litedramcore_next_state <= 2'd2;
- end
- 2'd2: begin
- litedramcore_next_state <= 1'd0;
- end
- default: begin
- if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_next_state <= 1'd1;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_adr_next_value1 <= 14'd0;
- case (litedramcore_state)
- 1'd1: begin
- litedramcore_adr_next_value1 <= 1'd0;
- end
- 2'd2: begin
- end
- default: begin
- if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_adr_next_value1 <= litedramcore_wishbone_adr;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_adr_next_value_ce1 <= 1'd0;
- case (litedramcore_state)
- 1'd1: begin
- litedramcore_adr_next_value_ce1 <= 1'd1;
- end
- 2'd2: begin
- end
- default: begin
- if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_adr_next_value_ce1 <= 1'd1;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_we_next_value2 <= 1'd0;
- case (litedramcore_state)
- 1'd1: begin
- litedramcore_we_next_value2 <= 1'd0;
- end
- 2'd2: begin
- end
- default: begin
- if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_we_next_value_ce2 <= 1'd0;
- case (litedramcore_state)
- 1'd1: begin
- litedramcore_we_next_value_ce2 <= 1'd1;
- end
- 2'd2: begin
- end
- default: begin
- if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_we_next_value_ce2 <= 1'd1;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_wishbone_dat_r <= 32'd0;
- case (litedramcore_state)
- 1'd1: begin
- end
- 2'd2: begin
- litedramcore_wishbone_dat_r <= litedramcore_dat_r;
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_wishbone_ack <= 1'd0;
- case (litedramcore_state)
- 1'd1: begin
- end
- 2'd2: begin
- litedramcore_wishbone_ack <= 1'd1;
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_dat_w_next_value0 <= 32'd0;
- case (litedramcore_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- default: begin
- litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w;
- end
- endcase
-end
-always @(*) begin
- litedramcore_dat_w_next_value_ce0 <= 1'd0;
- case (litedramcore_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- default: begin
- litedramcore_dat_w_next_value_ce0 <= 1'd1;
- end
- endcase
+ litedramcore_next_state <= 2'd0;
+ litedramcore_next_state <= litedramcore_state;
+ case (litedramcore_state)
+ 1'd1: begin
+ litedramcore_next_state <= 2'd2;
+ end
+ 2'd2: begin
+ litedramcore_next_state <= 1'd0;
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_next_state <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_adr_next_value1 <= 14'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ litedramcore_adr_next_value1 <= 1'd0;
+ end
+ 2'd2: begin
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_adr_next_value1 <= litedramcore_wishbone_adr;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_adr_next_value_ce1 <= 1'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ litedramcore_adr_next_value_ce1 <= 1'd1;
+ end
+ 2'd2: begin
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_adr_next_value_ce1 <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_we_next_value2 <= 1'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ litedramcore_we_next_value2 <= 1'd0;
+ end
+ 2'd2: begin
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_we_next_value_ce2 <= 1'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ litedramcore_we_next_value_ce2 <= 1'd1;
+ end
+ 2'd2: begin
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_we_next_value_ce2 <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_wishbone_dat_r <= 32'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ litedramcore_wishbone_dat_r <= litedramcore_dat_r;
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_wishbone_ack <= 1'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ litedramcore_wishbone_ack <= 1'd1;
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_dat_w_next_value0 <= 32'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ default: begin
+ litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w;
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_dat_w_next_value_ce0 <= 1'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ default: begin
+ litedramcore_dat_w_next_value_ce0 <= 1'd1;
+ end
+ endcase
end
assign litedramcore_wishbone_adr = wb_bus_adr;
assign litedramcore_wishbone_dat_w = wb_bus_dat_w;
assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0);
assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
always @(*) begin
- csrbank0_init_done0_we <= 1'd0;
- if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
- csrbank0_init_done0_we <= (~interface0_bank_bus_we);
- end
+ csrbank0_init_done0_we <= 1'd0;
+ if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank0_init_done0_we <= (~interface0_bank_bus_we);
+ end
end
always @(*) begin
- csrbank0_init_done0_re <= 1'd0;
- if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
- csrbank0_init_done0_re <= interface0_bank_bus_we;
- end
+ csrbank0_init_done0_re <= 1'd0;
+ if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank0_init_done0_re <= interface0_bank_bus_we;
+ end
end
assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0];
always @(*) begin
- csrbank0_init_error0_re <= 1'd0;
- if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
- csrbank0_init_error0_re <= interface0_bank_bus_we;
- end
+ csrbank0_init_error0_re <= 1'd0;
+ if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
+ csrbank0_init_error0_re <= interface0_bank_bus_we;
+ end
end
always @(*) begin
- csrbank0_init_error0_we <= 1'd0;
- if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
- csrbank0_init_error0_we <= (~interface0_bank_bus_we);
- end
+ csrbank0_init_error0_we <= 1'd0;
+ if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
+ csrbank0_init_error0_we <= (~interface0_bank_bus_we);
+ end
end
assign csrbank0_init_done0_w = init_done_storage;
assign csrbank0_init_error0_w = init_error_storage;
assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1);
assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0];
always @(*) begin
- csrbank1_dly_sel0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
- csrbank1_dly_sel0_re <= interface1_bank_bus_we;
- end
+ csrbank1_dly_sel0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank1_dly_sel0_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- csrbank1_dly_sel0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
- csrbank1_dly_sel0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_dly_sel0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank1_dly_sel0_we <= (~interface1_bank_bus_we);
+ end
end
assign ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- ddrphy_rdly_dq_rst_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
- ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we);
- end
+ ddrphy_rdly_dq_rst_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
+ ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- ddrphy_rdly_dq_rst_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
- ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we;
- end
+ ddrphy_rdly_dq_rst_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
+ ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we;
+ end
end
assign ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- ddrphy_rdly_dq_inc_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
- ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we);
- end
+ ddrphy_rdly_dq_inc_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
+ ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- ddrphy_rdly_dq_inc_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
- ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we;
- end
+ ddrphy_rdly_dq_inc_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
+ ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we;
+ end
end
assign ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
- ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
- end
+ ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
+ ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
- ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
- end
+ ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
+ ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
+ end
end
assign ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- ddrphy_rdly_dq_bitslip_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
- ddrphy_rdly_dq_bitslip_re <= interface1_bank_bus_we;
- end
+ ddrphy_rdly_dq_bitslip_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
+ ddrphy_rdly_dq_bitslip_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- ddrphy_rdly_dq_bitslip_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
- ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we);
- end
+ ddrphy_rdly_dq_bitslip_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
+ ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we);
+ end
end
assign ddrphy_burstdet_clr_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- ddrphy_burstdet_clr_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
- ddrphy_burstdet_clr_re <= interface1_bank_bus_we;
- end
+ ddrphy_burstdet_clr_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
+ ddrphy_burstdet_clr_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- ddrphy_burstdet_clr_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
- ddrphy_burstdet_clr_we <= (~interface1_bank_bus_we);
- end
+ ddrphy_burstdet_clr_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
+ ddrphy_burstdet_clr_we <= (~interface1_bank_bus_we);
+ end
end
assign csrbank1_burstdet_seen_r = interface1_bank_bus_dat_w[1:0];
always @(*) begin
- csrbank1_burstdet_seen_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
- csrbank1_burstdet_seen_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_burstdet_seen_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
+ csrbank1_burstdet_seen_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- csrbank1_burstdet_seen_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
- csrbank1_burstdet_seen_re <= interface1_bank_bus_we;
- end
+ csrbank1_burstdet_seen_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
+ csrbank1_burstdet_seen_re <= interface1_bank_bus_we;
+ end
end
assign csrbank1_dly_sel0_w = ddrphy_dly_sel_storage[1:0];
assign csrbank1_burstdet_seen_w = ddrphy_burstdet_seen_status[1:0];
assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2);
assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0];
always @(*) begin
- csrbank2_dfii_control0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
- csrbank2_dfii_control0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_control0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank2_dfii_control0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_control0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
- csrbank2_dfii_control0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_control0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank2_dfii_control0_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0];
always @(*) begin
- csrbank2_dfii_pi0_command0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
- csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi0_command0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
+ csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi0_command0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
- csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi0_command0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
+ csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we);
+ end
end
assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0];
always @(*) begin
- litedramcore_phaseinjector0_command_issue_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
- litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we;
- end
+ litedramcore_phaseinjector0_command_issue_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
+ litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- litedramcore_phaseinjector0_command_issue_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
- litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we);
- end
+ litedramcore_phaseinjector0_command_issue_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
+ litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[14:0];
always @(*) begin
- csrbank2_dfii_pi0_address0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
- csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi0_address0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
+ csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi0_address0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
- csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi0_address0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
+ csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0];
always @(*) begin
- csrbank2_dfii_pi0_baddress0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
- csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi0_baddress0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
+ csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi0_baddress0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
- csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi0_baddress0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
+ csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi0_wrdata1_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi0_wrdata1_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
- csrbank2_dfii_pi0_wrdata1_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi0_wrdata1_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
+ csrbank2_dfii_pi0_wrdata1_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi0_wrdata1_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
- csrbank2_dfii_pi0_wrdata1_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi0_wrdata1_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
+ csrbank2_dfii_pi0_wrdata1_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
- csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
+ csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
- csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
+ csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi0_rddata1_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi0_rddata1_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
- csrbank2_dfii_pi0_rddata1_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi0_rddata1_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
+ csrbank2_dfii_pi0_rddata1_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi0_rddata1_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
- csrbank2_dfii_pi0_rddata1_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi0_rddata1_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
+ csrbank2_dfii_pi0_rddata1_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi0_rddata0_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi0_rddata0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
- csrbank2_dfii_pi0_rddata0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi0_rddata0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
+ csrbank2_dfii_pi0_rddata0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi0_rddata0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
- csrbank2_dfii_pi0_rddata0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi0_rddata0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
+ csrbank2_dfii_pi0_rddata0_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0];
always @(*) begin
- csrbank2_dfii_pi1_command0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
- csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi1_command0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
+ csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi1_command0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
- csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi1_command0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
+ csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we;
+ end
end
assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0];
always @(*) begin
- litedramcore_phaseinjector1_command_issue_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
- litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we);
- end
+ litedramcore_phaseinjector1_command_issue_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
+ litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- litedramcore_phaseinjector1_command_issue_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
- litedramcore_phaseinjector1_command_issue_re <= interface2_bank_bus_we;
- end
+ litedramcore_phaseinjector1_command_issue_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
+ litedramcore_phaseinjector1_command_issue_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[14:0];
always @(*) begin
- csrbank2_dfii_pi1_address0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
- csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi1_address0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
+ csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi1_address0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
- csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi1_address0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
+ csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0];
always @(*) begin
- csrbank2_dfii_pi1_baddress0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
- csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi1_baddress0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
+ csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi1_baddress0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
- csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi1_baddress0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
+ csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi1_wrdata1_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi1_wrdata1_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
- csrbank2_dfii_pi1_wrdata1_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi1_wrdata1_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
+ csrbank2_dfii_pi1_wrdata1_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi1_wrdata1_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
- csrbank2_dfii_pi1_wrdata1_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi1_wrdata1_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
+ csrbank2_dfii_pi1_wrdata1_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
- csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
+ csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
- csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
+ csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi1_rddata1_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi1_rddata1_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
- csrbank2_dfii_pi1_rddata1_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi1_rddata1_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
+ csrbank2_dfii_pi1_rddata1_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi1_rddata1_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
- csrbank2_dfii_pi1_rddata1_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi1_rddata1_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
+ csrbank2_dfii_pi1_rddata1_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi1_rddata0_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi1_rddata0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
- csrbank2_dfii_pi1_rddata0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi1_rddata0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
+ csrbank2_dfii_pi1_rddata0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi1_rddata0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
- csrbank2_dfii_pi1_rddata0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi1_rddata0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
+ csrbank2_dfii_pi1_rddata0_re <= interface2_bank_bus_we;
+ end
end
assign litedramcore_sel = litedramcore_storage[0];
assign litedramcore_cke = litedramcore_storage[1];
assign interface2_bank_bus_dat_w = csr_interconnect_dat_w;
assign csr_interconnect_dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r);
always @(*) begin
- rhs_array_muxed0 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0];
- end
- 1'd1: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1];
- end
- 2'd2: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2];
- end
- 2'd3: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3];
- end
- 3'd4: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4];
- end
- 3'd5: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5];
- end
- 3'd6: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6];
- end
- default: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7];
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed1 <= 15'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a;
- end
- 1'd1: begin
- rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a;
- end
- 2'd2: begin
- rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a;
- end
- 2'd3: begin
- rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a;
- end
- 3'd4: begin
- rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a;
- end
- 3'd5: begin
- rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a;
- end
- 3'd6: begin
- rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a;
- end
- default: begin
- rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed2 <= 3'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba;
- end
- 1'd1: begin
- rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba;
- end
- 2'd2: begin
- rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba;
- end
- 2'd3: begin
- rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba;
- end
- 3'd4: begin
- rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba;
- end
- 3'd5: begin
- rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba;
- end
- 3'd6: begin
- rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba;
- end
- default: begin
- rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed3 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read;
- end
- 1'd1: begin
- rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read;
- end
- 2'd2: begin
- rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read;
- end
- 2'd3: begin
- rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read;
- end
- 3'd4: begin
- rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read;
- end
- 3'd5: begin
- rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read;
- end
- 3'd6: begin
- rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read;
- end
- default: begin
- rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed4 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write;
- end
- 1'd1: begin
- rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write;
- end
- 2'd2: begin
- rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write;
- end
- 2'd3: begin
- rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write;
- end
- 3'd4: begin
- rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write;
- end
- 3'd5: begin
- rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write;
- end
- 3'd6: begin
- rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write;
- end
- default: begin
- rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed5 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
- end
- 1'd1: begin
- rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
- end
- 2'd2: begin
- rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
- end
- 2'd3: begin
- rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
- end
- 3'd4: begin
- rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
- end
- 3'd5: begin
- rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
- end
- 3'd6: begin
- rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
- end
- default: begin
- rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
- end
- endcase
-end
-always @(*) begin
- t_array_muxed0 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas;
- end
- 1'd1: begin
- t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas;
- end
- 2'd2: begin
- t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas;
- end
- 2'd3: begin
- t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas;
- end
- 3'd4: begin
- t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas;
- end
- 3'd5: begin
- t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas;
- end
- 3'd6: begin
- t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas;
- end
- default: begin
- t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas;
- end
- endcase
-end
-always @(*) begin
- t_array_muxed1 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras;
- end
- 1'd1: begin
- t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras;
- end
- 2'd2: begin
- t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras;
- end
- 2'd3: begin
- t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras;
- end
- 3'd4: begin
- t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras;
- end
- 3'd5: begin
- t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras;
- end
- 3'd6: begin
- t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras;
- end
- default: begin
- t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras;
- end
- endcase
-end
-always @(*) begin
- t_array_muxed2 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we;
- end
- 1'd1: begin
- t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we;
- end
- 2'd2: begin
- t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we;
- end
- 2'd3: begin
- t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we;
- end
- 3'd4: begin
- t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we;
- end
- 3'd5: begin
- t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we;
- end
- 3'd6: begin
- t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we;
- end
- default: begin
- t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed6 <= 1'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[0];
- end
- 1'd1: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[1];
- end
- 2'd2: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[2];
- end
- 2'd3: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[3];
- end
- 3'd4: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[4];
- end
- 3'd5: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[5];
- end
- 3'd6: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[6];
- end
- default: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[7];
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed7 <= 15'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a;
- end
- 1'd1: begin
- rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a;
- end
- 2'd2: begin
- rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a;
- end
- 2'd3: begin
- rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a;
- end
- 3'd4: begin
- rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a;
- end
- 3'd5: begin
- rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a;
- end
- 3'd6: begin
- rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a;
- end
- default: begin
- rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed8 <= 3'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba;
- end
- 1'd1: begin
- rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba;
- end
- 2'd2: begin
- rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba;
- end
- 2'd3: begin
- rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba;
- end
- 3'd4: begin
- rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba;
- end
- 3'd5: begin
- rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba;
- end
- 3'd6: begin
- rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba;
- end
- default: begin
- rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed9 <= 1'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read;
- end
- 1'd1: begin
- rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read;
- end
- 2'd2: begin
- rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read;
- end
- 2'd3: begin
- rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read;
- end
- 3'd4: begin
- rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read;
- end
- 3'd5: begin
- rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read;
- end
- 3'd6: begin
- rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read;
- end
- default: begin
- rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed10 <= 1'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write;
- end
- 1'd1: begin
- rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write;
- end
- 2'd2: begin
- rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write;
- end
- 2'd3: begin
- rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write;
- end
- 3'd4: begin
- rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write;
- end
- 3'd5: begin
- rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write;
- end
- 3'd6: begin
- rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write;
- end
- default: begin
- rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed11 <= 1'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
- end
- 1'd1: begin
- rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
- end
- 2'd2: begin
- rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
- end
- 2'd3: begin
- rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
- end
- 3'd4: begin
- rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
- end
- 3'd5: begin
- rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
- end
- 3'd6: begin
- rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
- end
- default: begin
- rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
- end
- endcase
-end
-always @(*) begin
- t_array_muxed3 <= 1'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas;
- end
- 1'd1: begin
- t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas;
- end
- 2'd2: begin
- t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas;
- end
- 2'd3: begin
- t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas;
- end
- 3'd4: begin
- t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas;
- end
- 3'd5: begin
- t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas;
- end
- 3'd6: begin
- t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas;
- end
- default: begin
- t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas;
- end
- endcase
-end
-always @(*) begin
- t_array_muxed4 <= 1'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras;
- end
- 1'd1: begin
- t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras;
- end
- 2'd2: begin
- t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras;
- end
- 2'd3: begin
- t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras;
- end
- 3'd4: begin
- t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras;
- end
- 3'd5: begin
- t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras;
- end
- 3'd6: begin
- t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras;
- end
- default: begin
- t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras;
- end
- endcase
-end
-always @(*) begin
- t_array_muxed5 <= 1'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we;
- end
- 1'd1: begin
- t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we;
- end
- 2'd2: begin
- t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we;
- end
- 2'd3: begin
- t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we;
- end
- 3'd4: begin
- t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we;
- end
- 3'd5: begin
- t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we;
- end
- 3'd6: begin
- t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we;
- end
- default: begin
- t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed12 <= 22'd0;
- case (litedramcore_litedramcore_roundrobin0_grant)
- default: begin
- rhs_array_muxed12 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed13 <= 1'd0;
- case (litedramcore_litedramcore_roundrobin0_grant)
- default: begin
- rhs_array_muxed13 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed14 <= 1'd0;
- case (litedramcore_litedramcore_roundrobin0_grant)
- default: begin
- rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed15 <= 22'd0;
- case (litedramcore_litedramcore_roundrobin1_grant)
- default: begin
- rhs_array_muxed15 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed16 <= 1'd0;
- case (litedramcore_litedramcore_roundrobin1_grant)
- default: begin
- rhs_array_muxed16 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed17 <= 1'd0;
- case (litedramcore_litedramcore_roundrobin1_grant)
- default: begin
- rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed18 <= 22'd0;
- case (litedramcore_litedramcore_roundrobin2_grant)
- default: begin
- rhs_array_muxed18 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed19 <= 1'd0;
- case (litedramcore_litedramcore_roundrobin2_grant)
- default: begin
- rhs_array_muxed19 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed20 <= 1'd0;
- case (litedramcore_litedramcore_roundrobin2_grant)
- default: begin
- rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed21 <= 22'd0;
- case (litedramcore_litedramcore_roundrobin3_grant)
- default: begin
- rhs_array_muxed21 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed22 <= 1'd0;
- case (litedramcore_litedramcore_roundrobin3_grant)
- default: begin
- rhs_array_muxed22 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed23 <= 1'd0;
- case (litedramcore_litedramcore_roundrobin3_grant)
- default: begin
- rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
+ rhs_array_muxed0 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0];
+ end
+ 1'd1: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1];
+ end
+ 2'd2: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2];
+ end
+ 2'd3: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3];
+ end
+ 3'd4: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4];
+ end
+ 3'd5: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5];
+ end
+ 3'd6: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6];
+ end
+ default: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7];
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed1 <= 15'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a;
+ end
+ 1'd1: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a;
+ end
+ 2'd2: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a;
+ end
+ 2'd3: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a;
+ end
+ 3'd4: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a;
+ end
+ 3'd5: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a;
+ end
+ 3'd6: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a;
+ end
+ default: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed2 <= 3'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba;
+ end
+ 1'd1: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba;
+ end
+ 2'd2: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba;
+ end
+ 2'd3: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba;
+ end
+ 3'd4: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba;
+ end
+ 3'd5: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba;
+ end
+ 3'd6: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba;
+ end
+ default: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed3 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read;
+ end
+ 1'd1: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read;
+ end
+ 2'd2: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read;
+ end
+ 2'd3: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read;
+ end
+ 3'd4: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read;
+ end
+ 3'd5: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read;
+ end
+ 3'd6: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read;
+ end
+ default: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed4 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write;
+ end
+ 1'd1: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write;
+ end
+ 2'd2: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write;
+ end
+ 2'd3: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write;
+ end
+ 3'd4: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write;
+ end
+ 3'd5: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write;
+ end
+ 3'd6: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write;
+ end
+ default: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed5 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
+ end
+ 1'd1: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
+ end
+ 2'd2: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
+ end
+ 2'd3: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
+ end
+ 3'd4: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
+ end
+ 3'd5: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
+ end
+ 3'd6: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
+ end
+ default: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed0 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas;
+ end
+ 1'd1: begin
+ t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas;
+ end
+ 2'd2: begin
+ t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas;
+ end
+ 2'd3: begin
+ t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas;
+ end
+ 3'd4: begin
+ t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas;
+ end
+ 3'd5: begin
+ t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas;
+ end
+ 3'd6: begin
+ t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas;
+ end
+ default: begin
+ t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed1 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras;
+ end
+ 1'd1: begin
+ t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras;
+ end
+ 2'd2: begin
+ t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras;
+ end
+ 2'd3: begin
+ t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras;
+ end
+ 3'd4: begin
+ t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras;
+ end
+ 3'd5: begin
+ t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras;
+ end
+ 3'd6: begin
+ t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras;
+ end
+ default: begin
+ t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed2 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we;
+ end
+ 1'd1: begin
+ t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we;
+ end
+ 2'd2: begin
+ t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we;
+ end
+ 2'd3: begin
+ t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we;
+ end
+ 3'd4: begin
+ t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we;
+ end
+ 3'd5: begin
+ t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we;
+ end
+ 3'd6: begin
+ t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we;
+ end
+ default: begin
+ t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed6 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[0];
+ end
+ 1'd1: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[1];
+ end
+ 2'd2: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[2];
+ end
+ 2'd3: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[3];
+ end
+ 3'd4: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[4];
+ end
+ 3'd5: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[5];
+ end
+ 3'd6: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[6];
+ end
+ default: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[7];
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed7 <= 15'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a;
+ end
+ 1'd1: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a;
+ end
+ 2'd2: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a;
+ end
+ 2'd3: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a;
+ end
+ 3'd4: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a;
+ end
+ 3'd5: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a;
+ end
+ 3'd6: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a;
+ end
+ default: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed8 <= 3'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba;
+ end
+ 1'd1: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba;
+ end
+ 2'd2: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba;
+ end
+ 2'd3: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba;
+ end
+ 3'd4: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba;
+ end
+ 3'd5: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba;
+ end
+ 3'd6: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba;
+ end
+ default: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed9 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read;
+ end
+ 1'd1: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read;
+ end
+ 2'd2: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read;
+ end
+ 2'd3: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read;
+ end
+ 3'd4: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read;
+ end
+ 3'd5: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read;
+ end
+ 3'd6: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read;
+ end
+ default: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed10 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write;
+ end
+ 1'd1: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write;
+ end
+ 2'd2: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write;
+ end
+ 2'd3: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write;
+ end
+ 3'd4: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write;
+ end
+ 3'd5: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write;
+ end
+ 3'd6: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write;
+ end
+ default: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed11 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
+ end
+ 1'd1: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
+ end
+ 2'd2: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
+ end
+ 2'd3: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
+ end
+ 3'd4: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
+ end
+ 3'd5: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
+ end
+ 3'd6: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
+ end
+ default: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed3 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas;
+ end
+ 1'd1: begin
+ t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas;
+ end
+ 2'd2: begin
+ t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas;
+ end
+ 2'd3: begin
+ t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas;
+ end
+ 3'd4: begin
+ t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas;
+ end
+ 3'd5: begin
+ t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas;
+ end
+ 3'd6: begin
+ t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas;
+ end
+ default: begin
+ t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed4 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras;
+ end
+ 1'd1: begin
+ t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras;
+ end
+ 2'd2: begin
+ t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras;
+ end
+ 2'd3: begin
+ t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras;
+ end
+ 3'd4: begin
+ t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras;
+ end
+ 3'd5: begin
+ t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras;
+ end
+ 3'd6: begin
+ t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras;
+ end
+ default: begin
+ t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed5 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we;
+ end
+ 1'd1: begin
+ t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we;
+ end
+ 2'd2: begin
+ t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we;
+ end
+ 2'd3: begin
+ t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we;
+ end
+ 3'd4: begin
+ t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we;
+ end
+ 3'd5: begin
+ t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we;
+ end
+ 3'd6: begin
+ t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we;
+ end
+ default: begin
+ t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed12 <= 22'd0;
+ case (litedramcore_litedramcore_roundrobin0_grant)
+ default: begin
+ rhs_array_muxed12 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed13 <= 1'd0;
+ case (litedramcore_litedramcore_roundrobin0_grant)
+ default: begin
+ rhs_array_muxed13 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed14 <= 1'd0;
+ case (litedramcore_litedramcore_roundrobin0_grant)
+ default: begin
+ rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed15 <= 22'd0;
+ case (litedramcore_litedramcore_roundrobin1_grant)
+ default: begin
+ rhs_array_muxed15 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed16 <= 1'd0;
+ case (litedramcore_litedramcore_roundrobin1_grant)
+ default: begin
+ rhs_array_muxed16 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed17 <= 1'd0;
+ case (litedramcore_litedramcore_roundrobin1_grant)
+ default: begin
+ rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed18 <= 22'd0;
+ case (litedramcore_litedramcore_roundrobin2_grant)
+ default: begin
+ rhs_array_muxed18 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed19 <= 1'd0;
+ case (litedramcore_litedramcore_roundrobin2_grant)
+ default: begin
+ rhs_array_muxed19 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed20 <= 1'd0;
+ case (litedramcore_litedramcore_roundrobin2_grant)
+ default: begin
+ rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed21 <= 22'd0;
+ case (litedramcore_litedramcore_roundrobin3_grant)
+ default: begin
+ rhs_array_muxed21 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed22 <= 1'd0;
+ case (litedramcore_litedramcore_roundrobin3_grant)
+ default: begin
+ rhs_array_muxed22 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed23 <= 1'd0;
+ case (litedramcore_litedramcore_roundrobin3_grant)
+ default: begin
+ rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
end
always @(*) begin
- rhs_array_muxed24 <= 22'd0;
- case (litedramcore_litedramcore_roundrobin4_grant)
- default: begin
- rhs_array_muxed24 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed25 <= 1'd0;
- case (litedramcore_litedramcore_roundrobin4_grant)
- default: begin
- rhs_array_muxed25 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed26 <= 1'd0;
- case (litedramcore_litedramcore_roundrobin4_grant)
- default: begin
- rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed27 <= 22'd0;
- case (litedramcore_litedramcore_roundrobin5_grant)
- default: begin
- rhs_array_muxed27 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed28 <= 1'd0;
- case (litedramcore_litedramcore_roundrobin5_grant)
- default: begin
- rhs_array_muxed28 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed29 <= 1'd0;
- case (litedramcore_litedramcore_roundrobin5_grant)
- default: begin
- rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed30 <= 22'd0;
- case (litedramcore_litedramcore_roundrobin6_grant)
- default: begin
- rhs_array_muxed30 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed31 <= 1'd0;
- case (litedramcore_litedramcore_roundrobin6_grant)
- default: begin
- rhs_array_muxed31 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed32 <= 1'd0;
- case (litedramcore_litedramcore_roundrobin6_grant)
- default: begin
- rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed33 <= 22'd0;
- case (litedramcore_litedramcore_roundrobin7_grant)
- default: begin
- rhs_array_muxed33 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed34 <= 1'd0;
- case (litedramcore_litedramcore_roundrobin7_grant)
- default: begin
- rhs_array_muxed34 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed35 <= 1'd0;
- case (litedramcore_litedramcore_roundrobin7_grant)
- default: begin
- rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- array_muxed0 <= 3'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed0 <= litedramcore_nop_ba[2:0];
- end
- 1'd1: begin
- array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
- end
- 2'd2: begin
- array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0];
- end
- default: begin
- array_muxed0 <= litedramcore_cmd_payload_ba[2:0];
- end
- endcase
-end
-always @(*) begin
- array_muxed1 <= 15'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed1 <= litedramcore_nop_a;
- end
- 1'd1: begin
- array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a;
- end
- 2'd2: begin
- array_muxed1 <= litedramcore_choose_req_cmd_payload_a;
- end
- default: begin
- array_muxed1 <= litedramcore_cmd_payload_a;
- end
- endcase
-end
-always @(*) begin
- array_muxed2 <= 1'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed2 <= 1'd0;
- end
- 1'd1: begin
- array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
- end
- 2'd2: begin
- array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
- end
- default: begin
- array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
- end
- endcase
-end
-always @(*) begin
- array_muxed3 <= 1'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed3 <= 1'd0;
- end
- 1'd1: begin
- array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
- end
- 2'd2: begin
- array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
- end
- default: begin
- array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
- end
- endcase
-end
-always @(*) begin
- array_muxed4 <= 1'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed4 <= 1'd0;
- end
- 1'd1: begin
- array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
- end
- 2'd2: begin
- array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
- end
- default: begin
- array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
- end
- endcase
-end
-always @(*) begin
- array_muxed5 <= 1'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed5 <= 1'd0;
- end
- 1'd1: begin
- array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
- end
- 2'd2: begin
- array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
- end
- default: begin
- array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
- end
- endcase
-end
-always @(*) begin
- array_muxed6 <= 1'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed6 <= 1'd0;
- end
- 1'd1: begin
- array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
- end
- 2'd2: begin
- array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
- end
- default: begin
- array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
- end
- endcase
-end
-always @(*) begin
- array_muxed7 <= 3'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed7 <= litedramcore_nop_ba[2:0];
- end
- 1'd1: begin
- array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
- end
- 2'd2: begin
- array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0];
- end
- default: begin
- array_muxed7 <= litedramcore_cmd_payload_ba[2:0];
- end
- endcase
-end
-always @(*) begin
- array_muxed8 <= 15'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed8 <= litedramcore_nop_a;
- end
- 1'd1: begin
- array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a;
- end
- 2'd2: begin
- array_muxed8 <= litedramcore_choose_req_cmd_payload_a;
- end
- default: begin
- array_muxed8 <= litedramcore_cmd_payload_a;
- end
- endcase
-end
-always @(*) begin
- array_muxed9 <= 1'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed9 <= 1'd0;
- end
- 1'd1: begin
- array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
- end
- 2'd2: begin
- array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
- end
- default: begin
- array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
- end
- endcase
-end
-always @(*) begin
- array_muxed10 <= 1'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed10 <= 1'd0;
- end
- 1'd1: begin
- array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
- end
- 2'd2: begin
- array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
- end
- default: begin
- array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
- end
- endcase
-end
-always @(*) begin
- array_muxed11 <= 1'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed11 <= 1'd0;
- end
- 1'd1: begin
- array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
- end
- 2'd2: begin
- array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
- end
- default: begin
- array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
- end
- endcase
-end
-always @(*) begin
- array_muxed12 <= 1'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed12 <= 1'd0;
- end
- 1'd1: begin
- array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
- end
- 2'd2: begin
- array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
- end
- default: begin
- array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
- end
- endcase
-end
-always @(*) begin
- array_muxed13 <= 1'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed13 <= 1'd0;
- end
- 1'd1: begin
- array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
- end
- 2'd2: begin
- array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
- end
- default: begin
- array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
- end
- endcase
+ rhs_array_muxed24 <= 22'd0;
+ case (litedramcore_litedramcore_roundrobin4_grant)
+ default: begin
+ rhs_array_muxed24 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed25 <= 1'd0;
+ case (litedramcore_litedramcore_roundrobin4_grant)
+ default: begin
+ rhs_array_muxed25 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed26 <= 1'd0;
+ case (litedramcore_litedramcore_roundrobin4_grant)
+ default: begin
+ rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed27 <= 22'd0;
+ case (litedramcore_litedramcore_roundrobin5_grant)
+ default: begin
+ rhs_array_muxed27 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed28 <= 1'd0;
+ case (litedramcore_litedramcore_roundrobin5_grant)
+ default: begin
+ rhs_array_muxed28 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed29 <= 1'd0;
+ case (litedramcore_litedramcore_roundrobin5_grant)
+ default: begin
+ rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed30 <= 22'd0;
+ case (litedramcore_litedramcore_roundrobin6_grant)
+ default: begin
+ rhs_array_muxed30 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed31 <= 1'd0;
+ case (litedramcore_litedramcore_roundrobin6_grant)
+ default: begin
+ rhs_array_muxed31 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed32 <= 1'd0;
+ case (litedramcore_litedramcore_roundrobin6_grant)
+ default: begin
+ rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed33 <= 22'd0;
+ case (litedramcore_litedramcore_roundrobin7_grant)
+ default: begin
+ rhs_array_muxed33 <= {user_port_cmd_payload_addr[24:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed34 <= 1'd0;
+ case (litedramcore_litedramcore_roundrobin7_grant)
+ default: begin
+ rhs_array_muxed34 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed35 <= 1'd0;
+ case (litedramcore_litedramcore_roundrobin7_grant)
+ default: begin
+ rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed0 <= 3'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed0 <= litedramcore_nop_ba[2:0];
+ end
+ 1'd1: begin
+ array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+ end
+ 2'd2: begin
+ array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+ end
+ default: begin
+ array_muxed0 <= litedramcore_cmd_payload_ba[2:0];
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed1 <= 15'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed1 <= litedramcore_nop_a;
+ end
+ 1'd1: begin
+ array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a;
+ end
+ 2'd2: begin
+ array_muxed1 <= litedramcore_choose_req_cmd_payload_a;
+ end
+ default: begin
+ array_muxed1 <= litedramcore_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed2 <= 1'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed2 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+ end
+ 2'd2: begin
+ array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+ end
+ default: begin
+ array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed3 <= 1'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed3 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+ end
+ 2'd2: begin
+ array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+ end
+ default: begin
+ array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed4 <= 1'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed4 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+ end
+ 2'd2: begin
+ array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+ end
+ default: begin
+ array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed5 <= 1'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed5 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+ end
+ 2'd2: begin
+ array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+ end
+ default: begin
+ array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed6 <= 1'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed6 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+ end
+ 2'd2: begin
+ array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+ end
+ default: begin
+ array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed7 <= 3'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed7 <= litedramcore_nop_ba[2:0];
+ end
+ 1'd1: begin
+ array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+ end
+ 2'd2: begin
+ array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+ end
+ default: begin
+ array_muxed7 <= litedramcore_cmd_payload_ba[2:0];
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed8 <= 15'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed8 <= litedramcore_nop_a;
+ end
+ 1'd1: begin
+ array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a;
+ end
+ 2'd2: begin
+ array_muxed8 <= litedramcore_choose_req_cmd_payload_a;
+ end
+ default: begin
+ array_muxed8 <= litedramcore_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed9 <= 1'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed9 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+ end
+ 2'd2: begin
+ array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+ end
+ default: begin
+ array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed10 <= 1'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed10 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+ end
+ 2'd2: begin
+ array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+ end
+ default: begin
+ array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed11 <= 1'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed11 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+ end
+ 2'd2: begin
+ array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+ end
+ default: begin
+ array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed12 <= 1'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed12 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+ end
+ 2'd2: begin
+ array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+ end
+ default: begin
+ array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed13 <= 1'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed13 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+ end
+ 2'd2: begin
+ array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+ end
+ default: begin
+ array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+ end
+ endcase
end
assign ddrphy_lock1 = regs1;
//------------------------------------------------------------------------------
always @(posedge init_clk) begin
- ddrphy_lock_d <= ddrphy_lock1;
- if ((ddrphy_counter == 4'd8)) begin
- ddrphy_freeze <= 1'd1;
- end
- if ((ddrphy_counter == 5'd16)) begin
- ddrphy_stop1 <= 1'd1;
- end
- if ((ddrphy_counter == 5'd24)) begin
- ddrphy_reset1 <= 1'd1;
- end
- if ((ddrphy_counter == 6'd32)) begin
- ddrphy_reset1 <= 1'd0;
- end
- if ((ddrphy_counter == 6'd40)) begin
- ddrphy_stop1 <= 1'd0;
- end
- if ((ddrphy_counter == 6'd48)) begin
- ddrphy_freeze <= 1'd0;
- end
- if ((ddrphy_counter == 6'd56)) begin
- ddrphy_pause1 <= 1'd1;
- end
- if ((ddrphy_counter == 7'd64)) begin
- ddrphy_update <= 1'd1;
- end
- if ((ddrphy_counter == 7'd72)) begin
- ddrphy_update <= 1'd0;
- end
- if ((ddrphy_counter == 7'd80)) begin
- ddrphy_pause1 <= 1'd0;
- end
- if ((ddrphy_counter == 7'd80)) begin
- ddrphy_counter <= 1'd0;
- end else begin
- if ((ddrphy_counter != 1'd0)) begin
- ddrphy_counter <= (ddrphy_counter + 1'd1);
- end else begin
- if (ddrphy_new_lock) begin
- ddrphy_counter <= 1'd1;
- end
- end
- end
- if (init_rst) begin
- ddrphy_update <= 1'd0;
- ddrphy_stop1 <= 1'd0;
- ddrphy_freeze <= 1'd0;
- ddrphy_pause1 <= 1'd0;
- ddrphy_reset1 <= 1'd0;
- ddrphy_lock_d <= 1'd0;
- ddrphy_counter <= 7'd0;
- end
- regs0 <= ddrphy_lock0;
- regs1 <= regs0;
+ ddrphy_lock_d <= ddrphy_lock1;
+ if ((ddrphy_counter == 4'd8)) begin
+ ddrphy_freeze <= 1'd1;
+ end
+ if ((ddrphy_counter == 5'd16)) begin
+ ddrphy_stop1 <= 1'd1;
+ end
+ if ((ddrphy_counter == 5'd24)) begin
+ ddrphy_reset1 <= 1'd1;
+ end
+ if ((ddrphy_counter == 6'd32)) begin
+ ddrphy_reset1 <= 1'd0;
+ end
+ if ((ddrphy_counter == 6'd40)) begin
+ ddrphy_stop1 <= 1'd0;
+ end
+ if ((ddrphy_counter == 6'd48)) begin
+ ddrphy_freeze <= 1'd0;
+ end
+ if ((ddrphy_counter == 6'd56)) begin
+ ddrphy_pause1 <= 1'd1;
+ end
+ if ((ddrphy_counter == 7'd64)) begin
+ ddrphy_update <= 1'd1;
+ end
+ if ((ddrphy_counter == 7'd72)) begin
+ ddrphy_update <= 1'd0;
+ end
+ if ((ddrphy_counter == 7'd80)) begin
+ ddrphy_pause1 <= 1'd0;
+ end
+ if ((ddrphy_counter == 7'd80)) begin
+ ddrphy_counter <= 1'd0;
+ end else begin
+ if ((ddrphy_counter != 1'd0)) begin
+ ddrphy_counter <= (ddrphy_counter + 1'd1);
+ end else begin
+ if (ddrphy_new_lock) begin
+ ddrphy_counter <= 1'd1;
+ end
+ end
+ end
+ if (init_rst) begin
+ ddrphy_update <= 1'd0;
+ ddrphy_stop1 <= 1'd0;
+ ddrphy_freeze <= 1'd0;
+ ddrphy_pause1 <= 1'd0;
+ ddrphy_reset1 <= 1'd0;
+ ddrphy_lock_d <= 1'd0;
+ ddrphy_counter <= 7'd0;
+ end
+ regs0 <= ddrphy_lock0;
+ regs1 <= regs0;
end
always @(posedge por_clk) begin
- if ((~crg_por_done)) begin
- crg_por_count <= (crg_por_count - 1'd1);
- end
+ if ((~crg_por_done)) begin
+ crg_por_count <= (crg_por_count - 1'd1);
+ end
end
always @(posedge sys_clk) begin
- if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_rst_re)) begin
- ddrphy_rdly0 <= 1'd0;
- end
- if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_inc_re)) begin
- ddrphy_rdly0 <= (ddrphy_rdly0 + 1'd1);
- end
- ddrphy_burstdet_d0 <= ddrphy_burstdet0;
- if (ddrphy_burstdet_clr_re) begin
- ddrphy_burstdet_seen_status[0] <= 1'd0;
- end
- if ((ddrphy_burstdet0 & (~ddrphy_burstdet_d0))) begin
- ddrphy_burstdet_seen_status[0] <= 1'd1;
- end
- ddrphy_dm_o_data_d0 <= ddrphy_dm_o_data0;
- case (ddrphy_bl8_chunk)
- 1'd0: begin
- ddrphy_dm_o_data_muxed0 <= ddrphy_dm_o_data0[3:0];
- end
- 1'd1: begin
- ddrphy_dm_o_data_muxed0 <= ddrphy_dm_o_data_d0[7:4];
- end
- endcase
- ddrphy_dq_o_data_d0 <= ddrphy_dq_o_data0;
- case (ddrphy_bl8_chunk)
- 1'd0: begin
- ddrphy_dq_o_data_muxed0 <= ddrphy_dq_o_data0[3:0];
- end
- 1'd1: begin
- ddrphy_dq_o_data_muxed0 <= ddrphy_dq_o_data_d0[7:4];
- end
- endcase
- ddrphy_dq_i_bitslip_o_d0 <= ddrphy_bitslip0_o;
- ddrphy_dq_o_data_d1 <= ddrphy_dq_o_data1;
- case (ddrphy_bl8_chunk)
- 1'd0: begin
- ddrphy_dq_o_data_muxed1 <= ddrphy_dq_o_data1[3:0];
- end
- 1'd1: begin
- ddrphy_dq_o_data_muxed1 <= ddrphy_dq_o_data_d1[7:4];
- end
- endcase
- ddrphy_dq_i_bitslip_o_d1 <= ddrphy_bitslip1_o;
- ddrphy_dq_o_data_d2 <= ddrphy_dq_o_data2;
- case (ddrphy_bl8_chunk)
- 1'd0: begin
- ddrphy_dq_o_data_muxed2 <= ddrphy_dq_o_data2[3:0];
- end
- 1'd1: begin
- ddrphy_dq_o_data_muxed2 <= ddrphy_dq_o_data_d2[7:4];
- end
- endcase
- ddrphy_dq_i_bitslip_o_d2 <= ddrphy_bitslip2_o;
- ddrphy_dq_o_data_d3 <= ddrphy_dq_o_data3;
- case (ddrphy_bl8_chunk)
- 1'd0: begin
- ddrphy_dq_o_data_muxed3 <= ddrphy_dq_o_data3[3:0];
- end
- 1'd1: begin
- ddrphy_dq_o_data_muxed3 <= ddrphy_dq_o_data_d3[7:4];
- end
- endcase
- ddrphy_dq_i_bitslip_o_d3 <= ddrphy_bitslip3_o;
- ddrphy_dq_o_data_d4 <= ddrphy_dq_o_data4;
- case (ddrphy_bl8_chunk)
- 1'd0: begin
- ddrphy_dq_o_data_muxed4 <= ddrphy_dq_o_data4[3:0];
- end
- 1'd1: begin
- ddrphy_dq_o_data_muxed4 <= ddrphy_dq_o_data_d4[7:4];
- end
- endcase
- ddrphy_dq_i_bitslip_o_d4 <= ddrphy_bitslip4_o;
- ddrphy_dq_o_data_d5 <= ddrphy_dq_o_data5;
- case (ddrphy_bl8_chunk)
- 1'd0: begin
- ddrphy_dq_o_data_muxed5 <= ddrphy_dq_o_data5[3:0];
- end
- 1'd1: begin
- ddrphy_dq_o_data_muxed5 <= ddrphy_dq_o_data_d5[7:4];
- end
- endcase
- ddrphy_dq_i_bitslip_o_d5 <= ddrphy_bitslip5_o;
- ddrphy_dq_o_data_d6 <= ddrphy_dq_o_data6;
- case (ddrphy_bl8_chunk)
- 1'd0: begin
- ddrphy_dq_o_data_muxed6 <= ddrphy_dq_o_data6[3:0];
- end
- 1'd1: begin
- ddrphy_dq_o_data_muxed6 <= ddrphy_dq_o_data_d6[7:4];
- end
- endcase
- ddrphy_dq_i_bitslip_o_d6 <= ddrphy_bitslip6_o;
- ddrphy_dq_o_data_d7 <= ddrphy_dq_o_data7;
- case (ddrphy_bl8_chunk)
- 1'd0: begin
- ddrphy_dq_o_data_muxed7 <= ddrphy_dq_o_data7[3:0];
- end
- 1'd1: begin
- ddrphy_dq_o_data_muxed7 <= ddrphy_dq_o_data_d7[7:4];
- end
- endcase
- ddrphy_dq_i_bitslip_o_d7 <= ddrphy_bitslip7_o;
- if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_rst_re)) begin
- ddrphy_rdly1 <= 1'd0;
- end
- if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_inc_re)) begin
- ddrphy_rdly1 <= (ddrphy_rdly1 + 1'd1);
- end
- ddrphy_burstdet_d1 <= ddrphy_burstdet1;
- if (ddrphy_burstdet_clr_re) begin
- ddrphy_burstdet_seen_status[1] <= 1'd0;
- end
- if ((ddrphy_burstdet1 & (~ddrphy_burstdet_d1))) begin
- ddrphy_burstdet_seen_status[1] <= 1'd1;
- end
- ddrphy_dm_o_data_d1 <= ddrphy_dm_o_data1;
- case (ddrphy_bl8_chunk)
- 1'd0: begin
- ddrphy_dm_o_data_muxed1 <= ddrphy_dm_o_data1[3:0];
- end
- 1'd1: begin
- ddrphy_dm_o_data_muxed1 <= ddrphy_dm_o_data_d1[7:4];
- end
- endcase
- ddrphy_dq_o_data_d8 <= ddrphy_dq_o_data8;
- case (ddrphy_bl8_chunk)
- 1'd0: begin
- ddrphy_dq_o_data_muxed8 <= ddrphy_dq_o_data8[3:0];
- end
- 1'd1: begin
- ddrphy_dq_o_data_muxed8 <= ddrphy_dq_o_data_d8[7:4];
- end
- endcase
- ddrphy_dq_i_bitslip_o_d8 <= ddrphy_bitslip8_o;
- ddrphy_dq_o_data_d9 <= ddrphy_dq_o_data9;
- case (ddrphy_bl8_chunk)
- 1'd0: begin
- ddrphy_dq_o_data_muxed9 <= ddrphy_dq_o_data9[3:0];
- end
- 1'd1: begin
- ddrphy_dq_o_data_muxed9 <= ddrphy_dq_o_data_d9[7:4];
- end
- endcase
- ddrphy_dq_i_bitslip_o_d9 <= ddrphy_bitslip9_o;
- ddrphy_dq_o_data_d10 <= ddrphy_dq_o_data10;
- case (ddrphy_bl8_chunk)
- 1'd0: begin
- ddrphy_dq_o_data_muxed10 <= ddrphy_dq_o_data10[3:0];
- end
- 1'd1: begin
- ddrphy_dq_o_data_muxed10 <= ddrphy_dq_o_data_d10[7:4];
- end
- endcase
- ddrphy_dq_i_bitslip_o_d10 <= ddrphy_bitslip10_o;
- ddrphy_dq_o_data_d11 <= ddrphy_dq_o_data11;
- case (ddrphy_bl8_chunk)
- 1'd0: begin
- ddrphy_dq_o_data_muxed11 <= ddrphy_dq_o_data11[3:0];
- end
- 1'd1: begin
- ddrphy_dq_o_data_muxed11 <= ddrphy_dq_o_data_d11[7:4];
- end
- endcase
- ddrphy_dq_i_bitslip_o_d11 <= ddrphy_bitslip11_o;
- ddrphy_dq_o_data_d12 <= ddrphy_dq_o_data12;
- case (ddrphy_bl8_chunk)
- 1'd0: begin
- ddrphy_dq_o_data_muxed12 <= ddrphy_dq_o_data12[3:0];
- end
- 1'd1: begin
- ddrphy_dq_o_data_muxed12 <= ddrphy_dq_o_data_d12[7:4];
- end
- endcase
- ddrphy_dq_i_bitslip_o_d12 <= ddrphy_bitslip12_o;
- ddrphy_dq_o_data_d13 <= ddrphy_dq_o_data13;
- case (ddrphy_bl8_chunk)
- 1'd0: begin
- ddrphy_dq_o_data_muxed13 <= ddrphy_dq_o_data13[3:0];
- end
- 1'd1: begin
- ddrphy_dq_o_data_muxed13 <= ddrphy_dq_o_data_d13[7:4];
- end
- endcase
- ddrphy_dq_i_bitslip_o_d13 <= ddrphy_bitslip13_o;
- ddrphy_dq_o_data_d14 <= ddrphy_dq_o_data14;
- case (ddrphy_bl8_chunk)
- 1'd0: begin
- ddrphy_dq_o_data_muxed14 <= ddrphy_dq_o_data14[3:0];
- end
- 1'd1: begin
- ddrphy_dq_o_data_muxed14 <= ddrphy_dq_o_data_d14[7:4];
- end
- endcase
- ddrphy_dq_i_bitslip_o_d14 <= ddrphy_bitslip14_o;
- ddrphy_dq_o_data_d15 <= ddrphy_dq_o_data15;
- case (ddrphy_bl8_chunk)
- 1'd0: begin
- ddrphy_dq_o_data_muxed15 <= ddrphy_dq_o_data15[3:0];
- end
- 1'd1: begin
- ddrphy_dq_o_data_muxed15 <= ddrphy_dq_o_data_d15[7:4];
- end
- endcase
- ddrphy_dq_i_bitslip_o_d15 <= ddrphy_bitslip15_o;
- if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin
- ddrphy_bitslip0_value <= (ddrphy_bitslip0_value + 1'd1);
- end
- if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin
- ddrphy_bitslip0_value <= 1'd0;
- end
- ddrphy_bitslip0_r <= {ddrphy_bitslip0_i, ddrphy_bitslip0_r[7:4]};
- if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin
- ddrphy_bitslip1_value <= (ddrphy_bitslip1_value + 1'd1);
- end
- if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin
- ddrphy_bitslip1_value <= 1'd0;
- end
- ddrphy_bitslip1_r <= {ddrphy_bitslip1_i, ddrphy_bitslip1_r[7:4]};
- if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin
- ddrphy_bitslip2_value <= (ddrphy_bitslip2_value + 1'd1);
- end
- if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin
- ddrphy_bitslip2_value <= 1'd0;
- end
- ddrphy_bitslip2_r <= {ddrphy_bitslip2_i, ddrphy_bitslip2_r[7:4]};
- if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin
- ddrphy_bitslip3_value <= (ddrphy_bitslip3_value + 1'd1);
- end
- if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin
- ddrphy_bitslip3_value <= 1'd0;
- end
- ddrphy_bitslip3_r <= {ddrphy_bitslip3_i, ddrphy_bitslip3_r[7:4]};
- if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin
- ddrphy_bitslip4_value <= (ddrphy_bitslip4_value + 1'd1);
- end
- if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin
- ddrphy_bitslip4_value <= 1'd0;
- end
- ddrphy_bitslip4_r <= {ddrphy_bitslip4_i, ddrphy_bitslip4_r[7:4]};
- if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin
- ddrphy_bitslip5_value <= (ddrphy_bitslip5_value + 1'd1);
- end
- if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin
- ddrphy_bitslip5_value <= 1'd0;
- end
- ddrphy_bitslip5_r <= {ddrphy_bitslip5_i, ddrphy_bitslip5_r[7:4]};
- if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin
- ddrphy_bitslip6_value <= (ddrphy_bitslip6_value + 1'd1);
- end
- if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin
- ddrphy_bitslip6_value <= 1'd0;
- end
- ddrphy_bitslip6_r <= {ddrphy_bitslip6_i, ddrphy_bitslip6_r[7:4]};
- if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin
- ddrphy_bitslip7_value <= (ddrphy_bitslip7_value + 1'd1);
- end
- if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin
- ddrphy_bitslip7_value <= 1'd0;
- end
- ddrphy_bitslip7_r <= {ddrphy_bitslip7_i, ddrphy_bitslip7_r[7:4]};
- if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin
- ddrphy_bitslip8_value <= (ddrphy_bitslip8_value + 1'd1);
- end
- if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin
- ddrphy_bitslip8_value <= 1'd0;
- end
- ddrphy_bitslip8_r <= {ddrphy_bitslip8_i, ddrphy_bitslip8_r[7:4]};
- if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin
- ddrphy_bitslip9_value <= (ddrphy_bitslip9_value + 1'd1);
- end
- if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin
- ddrphy_bitslip9_value <= 1'd0;
- end
- ddrphy_bitslip9_r <= {ddrphy_bitslip9_i, ddrphy_bitslip9_r[7:4]};
- if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin
- ddrphy_bitslip10_value <= (ddrphy_bitslip10_value + 1'd1);
- end
- if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin
- ddrphy_bitslip10_value <= 1'd0;
- end
- ddrphy_bitslip10_r <= {ddrphy_bitslip10_i, ddrphy_bitslip10_r[7:4]};
- if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin
- ddrphy_bitslip11_value <= (ddrphy_bitslip11_value + 1'd1);
- end
- if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin
- ddrphy_bitslip11_value <= 1'd0;
- end
- ddrphy_bitslip11_r <= {ddrphy_bitslip11_i, ddrphy_bitslip11_r[7:4]};
- if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin
- ddrphy_bitslip12_value <= (ddrphy_bitslip12_value + 1'd1);
- end
- if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin
- ddrphy_bitslip12_value <= 1'd0;
- end
- ddrphy_bitslip12_r <= {ddrphy_bitslip12_i, ddrphy_bitslip12_r[7:4]};
- if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin
- ddrphy_bitslip13_value <= (ddrphy_bitslip13_value + 1'd1);
- end
- if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin
- ddrphy_bitslip13_value <= 1'd0;
- end
- ddrphy_bitslip13_r <= {ddrphy_bitslip13_i, ddrphy_bitslip13_r[7:4]};
- if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin
- ddrphy_bitslip14_value <= (ddrphy_bitslip14_value + 1'd1);
- end
- if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin
- ddrphy_bitslip14_value <= 1'd0;
- end
- ddrphy_bitslip14_r <= {ddrphy_bitslip14_i, ddrphy_bitslip14_r[7:4]};
- if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin
- ddrphy_bitslip15_value <= (ddrphy_bitslip15_value + 1'd1);
- end
- if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin
- ddrphy_bitslip15_value <= 1'd0;
- end
- ddrphy_bitslip15_r <= {ddrphy_bitslip15_i, ddrphy_bitslip15_r[7:4]};
- ddrphy_rddata_en_tappeddelayline0 <= (ddrphy_dfi_p0_rddata_en | ddrphy_dfi_p1_rddata_en);
- ddrphy_rddata_en_tappeddelayline1 <= ddrphy_rddata_en_tappeddelayline0;
- ddrphy_rddata_en_tappeddelayline2 <= ddrphy_rddata_en_tappeddelayline1;
- ddrphy_rddata_en_tappeddelayline3 <= ddrphy_rddata_en_tappeddelayline2;
- ddrphy_rddata_en_tappeddelayline4 <= ddrphy_rddata_en_tappeddelayline3;
- ddrphy_rddata_en_tappeddelayline5 <= ddrphy_rddata_en_tappeddelayline4;
- ddrphy_rddata_en_tappeddelayline6 <= ddrphy_rddata_en_tappeddelayline5;
- ddrphy_rddata_en_tappeddelayline7 <= ddrphy_rddata_en_tappeddelayline6;
- ddrphy_rddata_en_tappeddelayline8 <= ddrphy_rddata_en_tappeddelayline7;
- ddrphy_rddata_en_tappeddelayline9 <= ddrphy_rddata_en_tappeddelayline8;
- ddrphy_rddata_en_tappeddelayline10 <= ddrphy_rddata_en_tappeddelayline9;
- ddrphy_rddata_en_tappeddelayline11 <= ddrphy_rddata_en_tappeddelayline10;
- ddrphy_rddata_en_tappeddelayline12 <= ddrphy_rddata_en_tappeddelayline11;
- ddrphy_wrdata_en_tappeddelayline0 <= (ddrphy_dfi_p0_wrdata_en | ddrphy_dfi_p1_wrdata_en);
- ddrphy_wrdata_en_tappeddelayline1 <= ddrphy_wrdata_en_tappeddelayline0;
- ddrphy_wrdata_en_tappeddelayline2 <= ddrphy_wrdata_en_tappeddelayline1;
- ddrphy_wrdata_en_tappeddelayline3 <= ddrphy_wrdata_en_tappeddelayline2;
- ddrphy_wrdata_en_tappeddelayline4 <= ddrphy_wrdata_en_tappeddelayline3;
- ddrphy_wrdata_en_tappeddelayline5 <= ddrphy_wrdata_en_tappeddelayline4;
- ddrphy_wrdata_en_tappeddelayline6 <= ddrphy_wrdata_en_tappeddelayline5;
- if (litedramcore_csr_dfi_p0_rddata_valid) begin
- litedramcore_phaseinjector0_rddata_status <= litedramcore_csr_dfi_p0_rddata;
- end
- if (litedramcore_csr_dfi_p1_rddata_valid) begin
- litedramcore_phaseinjector1_rddata_status <= litedramcore_csr_dfi_p1_rddata;
- end
- if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin
- litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1);
- end else begin
- litedramcore_timer_count1 <= 9'd374;
- end
- litedramcore_postponer_req_o <= 1'd0;
- if (litedramcore_postponer_req_i) begin
- litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1);
- if ((litedramcore_postponer_count == 1'd0)) begin
- litedramcore_postponer_count <= 1'd0;
- litedramcore_postponer_req_o <= 1'd1;
- end
- end
- if (litedramcore_sequencer_start0) begin
- litedramcore_sequencer_count <= 1'd0;
- end else begin
- if (litedramcore_sequencer_done1) begin
- if ((litedramcore_sequencer_count != 1'd0)) begin
- litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1);
- end
- end
- end
- litedramcore_cmd_payload_a <= 1'd0;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd0;
- litedramcore_cmd_payload_we <= 1'd0;
- litedramcore_sequencer_done1 <= 1'd0;
- if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin
- litedramcore_cmd_payload_a <= 11'd1024;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd1;
- litedramcore_cmd_payload_we <= 1'd1;
- end
- if ((litedramcore_sequencer_counter == 2'd2)) begin
- litedramcore_cmd_payload_a <= 11'd1024;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd1;
- litedramcore_cmd_payload_ras <= 1'd1;
- litedramcore_cmd_payload_we <= 1'd0;
- end
- if ((litedramcore_sequencer_counter == 7'd106)) begin
- litedramcore_cmd_payload_a <= 1'd0;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd0;
- litedramcore_cmd_payload_we <= 1'd0;
- litedramcore_sequencer_done1 <= 1'd1;
- end
- if ((litedramcore_sequencer_counter == 7'd106)) begin
- litedramcore_sequencer_counter <= 1'd0;
- end else begin
- if ((litedramcore_sequencer_counter != 1'd0)) begin
- litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1);
- end else begin
- if (litedramcore_sequencer_start1) begin
- litedramcore_sequencer_counter <= 1'd1;
- end
- end
- end
- if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin
- litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1);
- end else begin
- litedramcore_zqcs_timer_count1 <= 26'd47999999;
- end
- litedramcore_zqcs_executer_done <= 1'd0;
- if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin
- litedramcore_cmd_payload_a <= 11'd1024;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd1;
- litedramcore_cmd_payload_we <= 1'd1;
- end
- if ((litedramcore_zqcs_executer_counter == 2'd2)) begin
- litedramcore_cmd_payload_a <= 1'd0;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd0;
- litedramcore_cmd_payload_we <= 1'd1;
- end
- if ((litedramcore_zqcs_executer_counter == 6'd34)) begin
- litedramcore_cmd_payload_a <= 1'd0;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd0;
- litedramcore_cmd_payload_we <= 1'd0;
- litedramcore_zqcs_executer_done <= 1'd1;
- end
- if ((litedramcore_zqcs_executer_counter == 6'd34)) begin
- litedramcore_zqcs_executer_counter <= 1'd0;
- end else begin
- if ((litedramcore_zqcs_executer_counter != 1'd0)) begin
- litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1);
- end else begin
- if (litedramcore_zqcs_executer_start) begin
- litedramcore_zqcs_executer_counter <= 1'd1;
- end
- end
- end
- litedramcore_litedramcore_refresher_state <= litedramcore_litedramcore_refresher_next_state;
- if (litedramcore_bankmachine0_row_close) begin
- litedramcore_bankmachine0_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine0_row_open) begin
- litedramcore_bankmachine0_row_opened <= 1'd1;
- litedramcore_bankmachine0_row <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[21:7];
- end
- end
- if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine0_cmd_buffer_source_valid <= litedramcore_bankmachine0_cmd_buffer_sink_valid;
- litedramcore_bankmachine0_cmd_buffer_source_first <= litedramcore_bankmachine0_cmd_buffer_sink_first;
- litedramcore_bankmachine0_cmd_buffer_source_last <= litedramcore_bankmachine0_cmd_buffer_sink_last;
- litedramcore_bankmachine0_cmd_buffer_source_payload_we <= litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine0_twtpcon_valid) begin
- litedramcore_bankmachine0_twtpcon_count <= 3'd6;
- if (1'd0) begin
- litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine0_twtpcon_ready)) begin
- litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine0_trccon_valid) begin
- litedramcore_bankmachine0_trccon_count <= 2'd2;
- if (1'd0) begin
- litedramcore_bankmachine0_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine0_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine0_trccon_ready)) begin
- litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1);
- if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin
- litedramcore_bankmachine0_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine0_trascon_valid) begin
- litedramcore_bankmachine0_trascon_count <= 2'd2;
- if (1'd0) begin
- litedramcore_bankmachine0_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine0_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1);
- if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin
- litedramcore_bankmachine0_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_litedramcore_bankmachine0_state <= litedramcore_litedramcore_bankmachine0_next_state;
- if (litedramcore_bankmachine1_row_close) begin
- litedramcore_bankmachine1_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine1_row_open) begin
- litedramcore_bankmachine1_row_opened <= 1'd1;
- litedramcore_bankmachine1_row <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[21:7];
- end
- end
- if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine1_cmd_buffer_source_valid <= litedramcore_bankmachine1_cmd_buffer_sink_valid;
- litedramcore_bankmachine1_cmd_buffer_source_first <= litedramcore_bankmachine1_cmd_buffer_sink_first;
- litedramcore_bankmachine1_cmd_buffer_source_last <= litedramcore_bankmachine1_cmd_buffer_sink_last;
- litedramcore_bankmachine1_cmd_buffer_source_payload_we <= litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine1_twtpcon_valid) begin
- litedramcore_bankmachine1_twtpcon_count <= 3'd6;
- if (1'd0) begin
- litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine1_twtpcon_ready)) begin
- litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine1_trccon_valid) begin
- litedramcore_bankmachine1_trccon_count <= 2'd2;
- if (1'd0) begin
- litedramcore_bankmachine1_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine1_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine1_trccon_ready)) begin
- litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1);
- if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin
- litedramcore_bankmachine1_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine1_trascon_valid) begin
- litedramcore_bankmachine1_trascon_count <= 2'd2;
- if (1'd0) begin
- litedramcore_bankmachine1_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine1_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1);
- if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin
- litedramcore_bankmachine1_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_litedramcore_bankmachine1_state <= litedramcore_litedramcore_bankmachine1_next_state;
- if (litedramcore_bankmachine2_row_close) begin
- litedramcore_bankmachine2_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine2_row_open) begin
- litedramcore_bankmachine2_row_opened <= 1'd1;
- litedramcore_bankmachine2_row <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[21:7];
- end
- end
- if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine2_cmd_buffer_source_valid <= litedramcore_bankmachine2_cmd_buffer_sink_valid;
- litedramcore_bankmachine2_cmd_buffer_source_first <= litedramcore_bankmachine2_cmd_buffer_sink_first;
- litedramcore_bankmachine2_cmd_buffer_source_last <= litedramcore_bankmachine2_cmd_buffer_sink_last;
- litedramcore_bankmachine2_cmd_buffer_source_payload_we <= litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine2_twtpcon_valid) begin
- litedramcore_bankmachine2_twtpcon_count <= 3'd6;
- if (1'd0) begin
- litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine2_twtpcon_ready)) begin
- litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine2_trccon_valid) begin
- litedramcore_bankmachine2_trccon_count <= 2'd2;
- if (1'd0) begin
- litedramcore_bankmachine2_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine2_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine2_trccon_ready)) begin
- litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1);
- if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin
- litedramcore_bankmachine2_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine2_trascon_valid) begin
- litedramcore_bankmachine2_trascon_count <= 2'd2;
- if (1'd0) begin
- litedramcore_bankmachine2_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine2_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1);
- if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin
- litedramcore_bankmachine2_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_litedramcore_bankmachine2_state <= litedramcore_litedramcore_bankmachine2_next_state;
- if (litedramcore_bankmachine3_row_close) begin
- litedramcore_bankmachine3_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine3_row_open) begin
- litedramcore_bankmachine3_row_opened <= 1'd1;
- litedramcore_bankmachine3_row <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[21:7];
- end
- end
- if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine3_cmd_buffer_source_valid <= litedramcore_bankmachine3_cmd_buffer_sink_valid;
- litedramcore_bankmachine3_cmd_buffer_source_first <= litedramcore_bankmachine3_cmd_buffer_sink_first;
- litedramcore_bankmachine3_cmd_buffer_source_last <= litedramcore_bankmachine3_cmd_buffer_sink_last;
- litedramcore_bankmachine3_cmd_buffer_source_payload_we <= litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine3_twtpcon_valid) begin
- litedramcore_bankmachine3_twtpcon_count <= 3'd6;
- if (1'd0) begin
- litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine3_twtpcon_ready)) begin
- litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine3_trccon_valid) begin
- litedramcore_bankmachine3_trccon_count <= 2'd2;
- if (1'd0) begin
- litedramcore_bankmachine3_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine3_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine3_trccon_ready)) begin
- litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1);
- if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin
- litedramcore_bankmachine3_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine3_trascon_valid) begin
- litedramcore_bankmachine3_trascon_count <= 2'd2;
- if (1'd0) begin
- litedramcore_bankmachine3_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine3_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1);
- if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin
- litedramcore_bankmachine3_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_litedramcore_bankmachine3_state <= litedramcore_litedramcore_bankmachine3_next_state;
- if (litedramcore_bankmachine4_row_close) begin
- litedramcore_bankmachine4_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine4_row_open) begin
- litedramcore_bankmachine4_row_opened <= 1'd1;
- litedramcore_bankmachine4_row <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[21:7];
- end
- end
- if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine4_cmd_buffer_source_valid <= litedramcore_bankmachine4_cmd_buffer_sink_valid;
- litedramcore_bankmachine4_cmd_buffer_source_first <= litedramcore_bankmachine4_cmd_buffer_sink_first;
- litedramcore_bankmachine4_cmd_buffer_source_last <= litedramcore_bankmachine4_cmd_buffer_sink_last;
- litedramcore_bankmachine4_cmd_buffer_source_payload_we <= litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine4_twtpcon_valid) begin
- litedramcore_bankmachine4_twtpcon_count <= 3'd6;
- if (1'd0) begin
- litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine4_twtpcon_ready)) begin
- litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine4_trccon_valid) begin
- litedramcore_bankmachine4_trccon_count <= 2'd2;
- if (1'd0) begin
- litedramcore_bankmachine4_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine4_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine4_trccon_ready)) begin
- litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1);
- if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin
- litedramcore_bankmachine4_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine4_trascon_valid) begin
- litedramcore_bankmachine4_trascon_count <= 2'd2;
- if (1'd0) begin
- litedramcore_bankmachine4_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine4_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1);
- if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin
- litedramcore_bankmachine4_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_litedramcore_bankmachine4_state <= litedramcore_litedramcore_bankmachine4_next_state;
- if (litedramcore_bankmachine5_row_close) begin
- litedramcore_bankmachine5_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine5_row_open) begin
- litedramcore_bankmachine5_row_opened <= 1'd1;
- litedramcore_bankmachine5_row <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[21:7];
- end
- end
- if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine5_cmd_buffer_source_valid <= litedramcore_bankmachine5_cmd_buffer_sink_valid;
- litedramcore_bankmachine5_cmd_buffer_source_first <= litedramcore_bankmachine5_cmd_buffer_sink_first;
- litedramcore_bankmachine5_cmd_buffer_source_last <= litedramcore_bankmachine5_cmd_buffer_sink_last;
- litedramcore_bankmachine5_cmd_buffer_source_payload_we <= litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine5_twtpcon_valid) begin
- litedramcore_bankmachine5_twtpcon_count <= 3'd6;
- if (1'd0) begin
- litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine5_twtpcon_ready)) begin
- litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine5_trccon_valid) begin
- litedramcore_bankmachine5_trccon_count <= 2'd2;
- if (1'd0) begin
- litedramcore_bankmachine5_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine5_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine5_trccon_ready)) begin
- litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1);
- if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin
- litedramcore_bankmachine5_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine5_trascon_valid) begin
- litedramcore_bankmachine5_trascon_count <= 2'd2;
- if (1'd0) begin
- litedramcore_bankmachine5_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine5_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1);
- if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin
- litedramcore_bankmachine5_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_litedramcore_bankmachine5_state <= litedramcore_litedramcore_bankmachine5_next_state;
- if (litedramcore_bankmachine6_row_close) begin
- litedramcore_bankmachine6_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine6_row_open) begin
- litedramcore_bankmachine6_row_opened <= 1'd1;
- litedramcore_bankmachine6_row <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[21:7];
- end
- end
- if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine6_cmd_buffer_source_valid <= litedramcore_bankmachine6_cmd_buffer_sink_valid;
- litedramcore_bankmachine6_cmd_buffer_source_first <= litedramcore_bankmachine6_cmd_buffer_sink_first;
- litedramcore_bankmachine6_cmd_buffer_source_last <= litedramcore_bankmachine6_cmd_buffer_sink_last;
- litedramcore_bankmachine6_cmd_buffer_source_payload_we <= litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine6_twtpcon_valid) begin
- litedramcore_bankmachine6_twtpcon_count <= 3'd6;
- if (1'd0) begin
- litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine6_twtpcon_ready)) begin
- litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine6_trccon_valid) begin
- litedramcore_bankmachine6_trccon_count <= 2'd2;
- if (1'd0) begin
- litedramcore_bankmachine6_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine6_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine6_trccon_ready)) begin
- litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1);
- if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin
- litedramcore_bankmachine6_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine6_trascon_valid) begin
- litedramcore_bankmachine6_trascon_count <= 2'd2;
- if (1'd0) begin
- litedramcore_bankmachine6_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine6_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1);
- if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin
- litedramcore_bankmachine6_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_litedramcore_bankmachine6_state <= litedramcore_litedramcore_bankmachine6_next_state;
- if (litedramcore_bankmachine7_row_close) begin
- litedramcore_bankmachine7_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine7_row_open) begin
- litedramcore_bankmachine7_row_opened <= 1'd1;
- litedramcore_bankmachine7_row <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[21:7];
- end
- end
- if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine7_cmd_buffer_source_valid <= litedramcore_bankmachine7_cmd_buffer_sink_valid;
- litedramcore_bankmachine7_cmd_buffer_source_first <= litedramcore_bankmachine7_cmd_buffer_sink_first;
- litedramcore_bankmachine7_cmd_buffer_source_last <= litedramcore_bankmachine7_cmd_buffer_sink_last;
- litedramcore_bankmachine7_cmd_buffer_source_payload_we <= litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine7_twtpcon_valid) begin
- litedramcore_bankmachine7_twtpcon_count <= 3'd6;
- if (1'd0) begin
- litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine7_twtpcon_ready)) begin
- litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine7_trccon_valid) begin
- litedramcore_bankmachine7_trccon_count <= 2'd2;
- if (1'd0) begin
- litedramcore_bankmachine7_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine7_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine7_trccon_ready)) begin
- litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1);
- if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin
- litedramcore_bankmachine7_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine7_trascon_valid) begin
- litedramcore_bankmachine7_trascon_count <= 2'd2;
- if (1'd0) begin
- litedramcore_bankmachine7_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine7_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1);
- if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin
- litedramcore_bankmachine7_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_litedramcore_bankmachine7_state <= litedramcore_litedramcore_bankmachine7_next_state;
- if ((~litedramcore_en0)) begin
- litedramcore_time0 <= 5'd31;
- end else begin
- if ((~litedramcore_max_time0)) begin
- litedramcore_time0 <= (litedramcore_time0 - 1'd1);
- end
- end
- if ((~litedramcore_en1)) begin
- litedramcore_time1 <= 4'd15;
- end else begin
- if ((~litedramcore_max_time1)) begin
- litedramcore_time1 <= (litedramcore_time1 - 1'd1);
- end
- end
- if (litedramcore_choose_cmd_ce) begin
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
- end
- end
- end
- end
- end
- end
- end
- end
- 1'd1: begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
- end
- end
- end
- end
- end
- end
- end
- end
- 2'd2: begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
- end
- end
- end
- end
- end
- end
- end
- end
- 2'd3: begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd4: begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd5: begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd6: begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd7: begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
- end
- end
- end
- end
- end
- end
- end
- end
- endcase
- end
- if (litedramcore_choose_req_ce) begin
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
- end
- end
- end
- end
- end
- end
- end
- end
- 1'd1: begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
- end
- end
- end
- end
- end
- end
- end
- end
- 2'd2: begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
- end
- end
- end
- end
- end
- end
- end
- end
- 2'd3: begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd4: begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd5: begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd6: begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd7: begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
- end
- end
- end
- end
- end
- end
- end
- end
- endcase
- end
- litedramcore_dfi_p0_cs_n <= 1'd0;
- litedramcore_dfi_p0_bank <= array_muxed0;
- litedramcore_dfi_p0_address <= array_muxed1;
- litedramcore_dfi_p0_cas_n <= (~array_muxed2);
- litedramcore_dfi_p0_ras_n <= (~array_muxed3);
- litedramcore_dfi_p0_we_n <= (~array_muxed4);
- litedramcore_dfi_p0_rddata_en <= array_muxed5;
- litedramcore_dfi_p0_wrdata_en <= array_muxed6;
- litedramcore_dfi_p1_cs_n <= 1'd0;
- litedramcore_dfi_p1_bank <= array_muxed7;
- litedramcore_dfi_p1_address <= array_muxed8;
- litedramcore_dfi_p1_cas_n <= (~array_muxed9);
- litedramcore_dfi_p1_ras_n <= (~array_muxed10);
- litedramcore_dfi_p1_we_n <= (~array_muxed11);
- litedramcore_dfi_p1_rddata_en <= array_muxed12;
- litedramcore_dfi_p1_wrdata_en <= array_muxed13;
- if (litedramcore_trrdcon_valid) begin
- litedramcore_trrdcon_count <= 1'd1;
- if (1'd0) begin
- litedramcore_trrdcon_ready <= 1'd1;
- end else begin
- litedramcore_trrdcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_trrdcon_ready)) begin
- litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1);
- if ((litedramcore_trrdcon_count == 1'd1)) begin
- litedramcore_trrdcon_ready <= 1'd1;
- end
- end
- end
- litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid};
- if ((litedramcore_tfawcon_count < 3'd4)) begin
- if ((litedramcore_tfawcon_count == 2'd3)) begin
- litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid);
- end else begin
- litedramcore_tfawcon_ready <= 1'd1;
- end
- end
- if (litedramcore_tccdcon_valid) begin
- litedramcore_tccdcon_count <= 1'd1;
- if (1'd0) begin
- litedramcore_tccdcon_ready <= 1'd1;
- end else begin
- litedramcore_tccdcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_tccdcon_ready)) begin
- litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1);
- if ((litedramcore_tccdcon_count == 1'd1)) begin
- litedramcore_tccdcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_twtrcon_valid) begin
- litedramcore_twtrcon_count <= 3'd6;
- if (1'd0) begin
- litedramcore_twtrcon_ready <= 1'd1;
- end else begin
- litedramcore_twtrcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_twtrcon_ready)) begin
- litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1);
- if ((litedramcore_twtrcon_count == 1'd1)) begin
- litedramcore_twtrcon_ready <= 1'd1;
- end
- end
- end
- litedramcore_litedramcore_multiplexer_state <= litedramcore_litedramcore_multiplexer_next_state;
- litedramcore_litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready));
- litedramcore_litedramcore_new_master_wdata_ready1 <= litedramcore_litedramcore_new_master_wdata_ready0;
- litedramcore_litedramcore_new_master_wdata_ready2 <= litedramcore_litedramcore_new_master_wdata_ready1;
- litedramcore_litedramcore_new_master_wdata_ready3 <= litedramcore_litedramcore_new_master_wdata_ready2;
- litedramcore_litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid));
- litedramcore_litedramcore_new_master_rdata_valid1 <= litedramcore_litedramcore_new_master_rdata_valid0;
- litedramcore_litedramcore_new_master_rdata_valid2 <= litedramcore_litedramcore_new_master_rdata_valid1;
- litedramcore_litedramcore_new_master_rdata_valid3 <= litedramcore_litedramcore_new_master_rdata_valid2;
- litedramcore_litedramcore_new_master_rdata_valid4 <= litedramcore_litedramcore_new_master_rdata_valid3;
- litedramcore_litedramcore_new_master_rdata_valid5 <= litedramcore_litedramcore_new_master_rdata_valid4;
- litedramcore_litedramcore_new_master_rdata_valid6 <= litedramcore_litedramcore_new_master_rdata_valid5;
- litedramcore_litedramcore_new_master_rdata_valid7 <= litedramcore_litedramcore_new_master_rdata_valid6;
- litedramcore_litedramcore_new_master_rdata_valid8 <= litedramcore_litedramcore_new_master_rdata_valid7;
- litedramcore_litedramcore_new_master_rdata_valid9 <= litedramcore_litedramcore_new_master_rdata_valid8;
- litedramcore_litedramcore_new_master_rdata_valid10 <= litedramcore_litedramcore_new_master_rdata_valid9;
- litedramcore_litedramcore_new_master_rdata_valid11 <= litedramcore_litedramcore_new_master_rdata_valid10;
- litedramcore_litedramcore_new_master_rdata_valid12 <= litedramcore_litedramcore_new_master_rdata_valid11;
- litedramcore_litedramcore_new_master_rdata_valid13 <= litedramcore_litedramcore_new_master_rdata_valid12;
- litedramcore_state <= litedramcore_next_state;
- if (litedramcore_dat_w_next_value_ce0) begin
- litedramcore_dat_w <= litedramcore_dat_w_next_value0;
- end
- if (litedramcore_adr_next_value_ce1) begin
- litedramcore_adr <= litedramcore_adr_next_value1;
- end
- if (litedramcore_we_next_value_ce2) begin
- litedramcore_we <= litedramcore_we_next_value2;
- end
- interface0_bank_bus_dat_r <= 1'd0;
- if (csrbank0_sel) begin
- case (interface0_bank_bus_adr[8:0])
- 1'd0: begin
- interface0_bank_bus_dat_r <= csrbank0_init_done0_w;
- end
- 1'd1: begin
- interface0_bank_bus_dat_r <= csrbank0_init_error0_w;
- end
- endcase
- end
- if (csrbank0_init_done0_re) begin
- init_done_storage <= csrbank0_init_done0_r;
- end
- init_done_re <= csrbank0_init_done0_re;
- if (csrbank0_init_error0_re) begin
- init_error_storage <= csrbank0_init_error0_r;
- end
- init_error_re <= csrbank0_init_error0_re;
- interface1_bank_bus_dat_r <= 1'd0;
- if (csrbank1_sel) begin
- case (interface1_bank_bus_adr[8:0])
- 1'd0: begin
- interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w;
- end
- 1'd1: begin
- interface1_bank_bus_dat_r <= ddrphy_rdly_dq_rst_w;
- end
- 2'd2: begin
- interface1_bank_bus_dat_r <= ddrphy_rdly_dq_inc_w;
- end
- 2'd3: begin
- interface1_bank_bus_dat_r <= ddrphy_rdly_dq_bitslip_rst_w;
- end
- 3'd4: begin
- interface1_bank_bus_dat_r <= ddrphy_rdly_dq_bitslip_w;
- end
- 3'd5: begin
- interface1_bank_bus_dat_r <= ddrphy_burstdet_clr_w;
- end
- 3'd6: begin
- interface1_bank_bus_dat_r <= csrbank1_burstdet_seen_w;
- end
- endcase
- end
- if (csrbank1_dly_sel0_re) begin
- ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r;
- end
- ddrphy_dly_sel_re <= csrbank1_dly_sel0_re;
- ddrphy_burstdet_seen_re <= csrbank1_burstdet_seen_re;
- interface2_bank_bus_dat_r <= 1'd0;
- if (csrbank2_sel) begin
- case (interface2_bank_bus_adr[8:0])
- 1'd0: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w;
- end
- 1'd1: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w;
- end
- 2'd2: begin
- interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w;
- end
- 2'd3: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w;
- end
- 3'd4: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w;
- end
- 3'd5: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata1_w;
- end
- 3'd6: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w;
- end
- 3'd7: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata1_w;
- end
- 4'd8: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata0_w;
- end
- 4'd9: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w;
- end
- 4'd10: begin
- interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w;
- end
- 4'd11: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w;
- end
- 4'd12: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w;
- end
- 4'd13: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata1_w;
- end
- 4'd14: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w;
- end
- 4'd15: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata1_w;
- end
- 5'd16: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata0_w;
- end
- endcase
- end
- if (csrbank2_dfii_control0_re) begin
- litedramcore_storage[3:0] <= csrbank2_dfii_control0_r;
- end
- litedramcore_re <= csrbank2_dfii_control0_re;
- if (csrbank2_dfii_pi0_command0_re) begin
- litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r;
- end
- litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re;
- if (csrbank2_dfii_pi0_address0_re) begin
- litedramcore_phaseinjector0_address_storage[14:0] <= csrbank2_dfii_pi0_address0_r;
- end
- litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re;
- if (csrbank2_dfii_pi0_baddress0_re) begin
- litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r;
- end
- litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re;
- if (csrbank2_dfii_pi0_wrdata1_re) begin
- litedramcore_phaseinjector0_wrdata_storage[63:32] <= csrbank2_dfii_pi0_wrdata1_r;
- end
- if (csrbank2_dfii_pi0_wrdata0_re) begin
- litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r;
- end
- litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re;
- litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata0_re;
- if (csrbank2_dfii_pi1_command0_re) begin
- litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r;
- end
- litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re;
- if (csrbank2_dfii_pi1_address0_re) begin
- litedramcore_phaseinjector1_address_storage[14:0] <= csrbank2_dfii_pi1_address0_r;
- end
- litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re;
- if (csrbank2_dfii_pi1_baddress0_re) begin
- litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r;
- end
- litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re;
- if (csrbank2_dfii_pi1_wrdata1_re) begin
- litedramcore_phaseinjector1_wrdata_storage[63:32] <= csrbank2_dfii_pi1_wrdata1_r;
- end
- if (csrbank2_dfii_pi1_wrdata0_re) begin
- litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r;
- end
- litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re;
- litedramcore_phaseinjector1_rddata_re <= csrbank2_dfii_pi1_rddata0_re;
- if (sys_rst) begin
- ddrphy_dly_sel_storage <= 2'd0;
- ddrphy_dly_sel_re <= 1'd0;
- ddrphy_burstdet_seen_status <= 2'd0;
- ddrphy_burstdet_seen_re <= 1'd0;
- ddrphy_rdly0 <= 3'd0;
- ddrphy_burstdet_d0 <= 1'd0;
- ddrphy_dm_o_data_d0 <= 8'd0;
- ddrphy_dm_o_data_muxed0 <= 4'd0;
- ddrphy_dq_o_data_d0 <= 8'd0;
- ddrphy_dq_o_data_muxed0 <= 4'd0;
- ddrphy_bitslip0_value <= 2'd0;
- ddrphy_dq_i_bitslip_o_d0 <= 4'd0;
- ddrphy_dq_o_data_d1 <= 8'd0;
- ddrphy_dq_o_data_muxed1 <= 4'd0;
- ddrphy_bitslip1_value <= 2'd0;
- ddrphy_dq_i_bitslip_o_d1 <= 4'd0;
- ddrphy_dq_o_data_d2 <= 8'd0;
- ddrphy_dq_o_data_muxed2 <= 4'd0;
- ddrphy_bitslip2_value <= 2'd0;
- ddrphy_dq_i_bitslip_o_d2 <= 4'd0;
- ddrphy_dq_o_data_d3 <= 8'd0;
- ddrphy_dq_o_data_muxed3 <= 4'd0;
- ddrphy_bitslip3_value <= 2'd0;
- ddrphy_dq_i_bitslip_o_d3 <= 4'd0;
- ddrphy_dq_o_data_d4 <= 8'd0;
- ddrphy_dq_o_data_muxed4 <= 4'd0;
- ddrphy_bitslip4_value <= 2'd0;
- ddrphy_dq_i_bitslip_o_d4 <= 4'd0;
- ddrphy_dq_o_data_d5 <= 8'd0;
- ddrphy_dq_o_data_muxed5 <= 4'd0;
- ddrphy_bitslip5_value <= 2'd0;
- ddrphy_dq_i_bitslip_o_d5 <= 4'd0;
- ddrphy_dq_o_data_d6 <= 8'd0;
- ddrphy_dq_o_data_muxed6 <= 4'd0;
- ddrphy_bitslip6_value <= 2'd0;
- ddrphy_dq_i_bitslip_o_d6 <= 4'd0;
- ddrphy_dq_o_data_d7 <= 8'd0;
- ddrphy_dq_o_data_muxed7 <= 4'd0;
- ddrphy_bitslip7_value <= 2'd0;
- ddrphy_dq_i_bitslip_o_d7 <= 4'd0;
- ddrphy_rdly1 <= 3'd0;
- ddrphy_burstdet_d1 <= 1'd0;
- ddrphy_dm_o_data_d1 <= 8'd0;
- ddrphy_dm_o_data_muxed1 <= 4'd0;
- ddrphy_dq_o_data_d8 <= 8'd0;
- ddrphy_dq_o_data_muxed8 <= 4'd0;
- ddrphy_bitslip8_value <= 2'd0;
- ddrphy_dq_i_bitslip_o_d8 <= 4'd0;
- ddrphy_dq_o_data_d9 <= 8'd0;
- ddrphy_dq_o_data_muxed9 <= 4'd0;
- ddrphy_bitslip9_value <= 2'd0;
- ddrphy_dq_i_bitslip_o_d9 <= 4'd0;
- ddrphy_dq_o_data_d10 <= 8'd0;
- ddrphy_dq_o_data_muxed10 <= 4'd0;
- ddrphy_bitslip10_value <= 2'd0;
- ddrphy_dq_i_bitslip_o_d10 <= 4'd0;
- ddrphy_dq_o_data_d11 <= 8'd0;
- ddrphy_dq_o_data_muxed11 <= 4'd0;
- ddrphy_bitslip11_value <= 2'd0;
- ddrphy_dq_i_bitslip_o_d11 <= 4'd0;
- ddrphy_dq_o_data_d12 <= 8'd0;
- ddrphy_dq_o_data_muxed12 <= 4'd0;
- ddrphy_bitslip12_value <= 2'd0;
- ddrphy_dq_i_bitslip_o_d12 <= 4'd0;
- ddrphy_dq_o_data_d13 <= 8'd0;
- ddrphy_dq_o_data_muxed13 <= 4'd0;
- ddrphy_bitslip13_value <= 2'd0;
- ddrphy_dq_i_bitslip_o_d13 <= 4'd0;
- ddrphy_dq_o_data_d14 <= 8'd0;
- ddrphy_dq_o_data_muxed14 <= 4'd0;
- ddrphy_bitslip14_value <= 2'd0;
- ddrphy_dq_i_bitslip_o_d14 <= 4'd0;
- ddrphy_dq_o_data_d15 <= 8'd0;
- ddrphy_dq_o_data_muxed15 <= 4'd0;
- ddrphy_bitslip15_value <= 2'd0;
- ddrphy_dq_i_bitslip_o_d15 <= 4'd0;
- ddrphy_rddata_en_tappeddelayline0 <= 1'd0;
- ddrphy_rddata_en_tappeddelayline1 <= 1'd0;
- ddrphy_rddata_en_tappeddelayline2 <= 1'd0;
- ddrphy_rddata_en_tappeddelayline3 <= 1'd0;
- ddrphy_rddata_en_tappeddelayline4 <= 1'd0;
- ddrphy_rddata_en_tappeddelayline5 <= 1'd0;
- ddrphy_rddata_en_tappeddelayline6 <= 1'd0;
- ddrphy_rddata_en_tappeddelayline7 <= 1'd0;
- ddrphy_rddata_en_tappeddelayline8 <= 1'd0;
- ddrphy_rddata_en_tappeddelayline9 <= 1'd0;
- ddrphy_rddata_en_tappeddelayline10 <= 1'd0;
- ddrphy_rddata_en_tappeddelayline11 <= 1'd0;
- ddrphy_rddata_en_tappeddelayline12 <= 1'd0;
- ddrphy_wrdata_en_tappeddelayline0 <= 1'd0;
- ddrphy_wrdata_en_tappeddelayline1 <= 1'd0;
- ddrphy_wrdata_en_tappeddelayline2 <= 1'd0;
- ddrphy_wrdata_en_tappeddelayline3 <= 1'd0;
- ddrphy_wrdata_en_tappeddelayline4 <= 1'd0;
- ddrphy_wrdata_en_tappeddelayline5 <= 1'd0;
- ddrphy_wrdata_en_tappeddelayline6 <= 1'd0;
- litedramcore_storage <= 4'd1;
- litedramcore_re <= 1'd0;
- litedramcore_phaseinjector0_command_storage <= 6'd0;
- litedramcore_phaseinjector0_command_re <= 1'd0;
- litedramcore_phaseinjector0_address_re <= 1'd0;
- litedramcore_phaseinjector0_baddress_re <= 1'd0;
- litedramcore_phaseinjector0_wrdata_re <= 1'd0;
- litedramcore_phaseinjector0_rddata_status <= 64'd0;
- litedramcore_phaseinjector0_rddata_re <= 1'd0;
- litedramcore_phaseinjector1_command_storage <= 6'd0;
- litedramcore_phaseinjector1_command_re <= 1'd0;
- litedramcore_phaseinjector1_address_re <= 1'd0;
- litedramcore_phaseinjector1_baddress_re <= 1'd0;
- litedramcore_phaseinjector1_wrdata_re <= 1'd0;
- litedramcore_phaseinjector1_rddata_status <= 64'd0;
- litedramcore_phaseinjector1_rddata_re <= 1'd0;
- litedramcore_dfi_p0_address <= 15'd0;
- litedramcore_dfi_p0_bank <= 3'd0;
- litedramcore_dfi_p0_cas_n <= 1'd1;
- litedramcore_dfi_p0_cs_n <= 1'd1;
- litedramcore_dfi_p0_ras_n <= 1'd1;
- litedramcore_dfi_p0_we_n <= 1'd1;
- litedramcore_dfi_p0_wrdata_en <= 1'd0;
- litedramcore_dfi_p0_rddata_en <= 1'd0;
- litedramcore_dfi_p1_address <= 15'd0;
- litedramcore_dfi_p1_bank <= 3'd0;
- litedramcore_dfi_p1_cas_n <= 1'd1;
- litedramcore_dfi_p1_cs_n <= 1'd1;
- litedramcore_dfi_p1_ras_n <= 1'd1;
- litedramcore_dfi_p1_we_n <= 1'd1;
- litedramcore_dfi_p1_wrdata_en <= 1'd0;
- litedramcore_dfi_p1_rddata_en <= 1'd0;
- litedramcore_cmd_payload_a <= 15'd0;
- litedramcore_cmd_payload_ba <= 3'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd0;
- litedramcore_cmd_payload_we <= 1'd0;
- litedramcore_timer_count1 <= 9'd374;
- litedramcore_postponer_req_o <= 1'd0;
- litedramcore_postponer_count <= 1'd0;
- litedramcore_sequencer_done1 <= 1'd0;
- litedramcore_sequencer_counter <= 7'd0;
- litedramcore_sequencer_count <= 1'd0;
- litedramcore_zqcs_timer_count1 <= 26'd47999999;
- litedramcore_zqcs_executer_done <= 1'd0;
- litedramcore_zqcs_executer_counter <= 6'd0;
- litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine0_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= 22'd0;
- litedramcore_bankmachine0_row <= 15'd0;
- litedramcore_bankmachine0_row_opened <= 1'd0;
- litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine0_twtpcon_count <= 3'd0;
- litedramcore_bankmachine0_trccon_ready <= 1'd0;
- litedramcore_bankmachine0_trccon_count <= 2'd0;
- litedramcore_bankmachine0_trascon_ready <= 1'd0;
- litedramcore_bankmachine0_trascon_count <= 2'd0;
- litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine1_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= 22'd0;
- litedramcore_bankmachine1_row <= 15'd0;
- litedramcore_bankmachine1_row_opened <= 1'd0;
- litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine1_twtpcon_count <= 3'd0;
- litedramcore_bankmachine1_trccon_ready <= 1'd0;
- litedramcore_bankmachine1_trccon_count <= 2'd0;
- litedramcore_bankmachine1_trascon_ready <= 1'd0;
- litedramcore_bankmachine1_trascon_count <= 2'd0;
- litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine2_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= 22'd0;
- litedramcore_bankmachine2_row <= 15'd0;
- litedramcore_bankmachine2_row_opened <= 1'd0;
- litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine2_twtpcon_count <= 3'd0;
- litedramcore_bankmachine2_trccon_ready <= 1'd0;
- litedramcore_bankmachine2_trccon_count <= 2'd0;
- litedramcore_bankmachine2_trascon_ready <= 1'd0;
- litedramcore_bankmachine2_trascon_count <= 2'd0;
- litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine3_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= 22'd0;
- litedramcore_bankmachine3_row <= 15'd0;
- litedramcore_bankmachine3_row_opened <= 1'd0;
- litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine3_twtpcon_count <= 3'd0;
- litedramcore_bankmachine3_trccon_ready <= 1'd0;
- litedramcore_bankmachine3_trccon_count <= 2'd0;
- litedramcore_bankmachine3_trascon_ready <= 1'd0;
- litedramcore_bankmachine3_trascon_count <= 2'd0;
- litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine4_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= 22'd0;
- litedramcore_bankmachine4_row <= 15'd0;
- litedramcore_bankmachine4_row_opened <= 1'd0;
- litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine4_twtpcon_count <= 3'd0;
- litedramcore_bankmachine4_trccon_ready <= 1'd0;
- litedramcore_bankmachine4_trccon_count <= 2'd0;
- litedramcore_bankmachine4_trascon_ready <= 1'd0;
- litedramcore_bankmachine4_trascon_count <= 2'd0;
- litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine5_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= 22'd0;
- litedramcore_bankmachine5_row <= 15'd0;
- litedramcore_bankmachine5_row_opened <= 1'd0;
- litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine5_twtpcon_count <= 3'd0;
- litedramcore_bankmachine5_trccon_ready <= 1'd0;
- litedramcore_bankmachine5_trccon_count <= 2'd0;
- litedramcore_bankmachine5_trascon_ready <= 1'd0;
- litedramcore_bankmachine5_trascon_count <= 2'd0;
- litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine6_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= 22'd0;
- litedramcore_bankmachine6_row <= 15'd0;
- litedramcore_bankmachine6_row_opened <= 1'd0;
- litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine6_twtpcon_count <= 3'd0;
- litedramcore_bankmachine6_trccon_ready <= 1'd0;
- litedramcore_bankmachine6_trccon_count <= 2'd0;
- litedramcore_bankmachine6_trascon_ready <= 1'd0;
- litedramcore_bankmachine6_trascon_count <= 2'd0;
- litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine7_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= 22'd0;
- litedramcore_bankmachine7_row <= 15'd0;
- litedramcore_bankmachine7_row_opened <= 1'd0;
- litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine7_twtpcon_count <= 3'd0;
- litedramcore_bankmachine7_trccon_ready <= 1'd0;
- litedramcore_bankmachine7_trccon_count <= 2'd0;
- litedramcore_bankmachine7_trascon_ready <= 1'd0;
- litedramcore_bankmachine7_trascon_count <= 2'd0;
- litedramcore_choose_cmd_grant <= 3'd0;
- litedramcore_choose_req_grant <= 3'd0;
- litedramcore_trrdcon_ready <= 1'd0;
- litedramcore_trrdcon_count <= 1'd0;
- litedramcore_tfawcon_ready <= 1'd1;
- litedramcore_tfawcon_window <= 3'd0;
- litedramcore_tccdcon_ready <= 1'd0;
- litedramcore_tccdcon_count <= 1'd0;
- litedramcore_twtrcon_ready <= 1'd0;
- litedramcore_twtrcon_count <= 3'd0;
- litedramcore_time0 <= 5'd0;
- litedramcore_time1 <= 4'd0;
- init_done_storage <= 1'd0;
- init_done_re <= 1'd0;
- init_error_storage <= 1'd0;
- init_error_re <= 1'd0;
- litedramcore_we <= 1'd0;
- litedramcore_litedramcore_refresher_state <= 2'd0;
- litedramcore_litedramcore_bankmachine0_state <= 3'd0;
- litedramcore_litedramcore_bankmachine1_state <= 3'd0;
- litedramcore_litedramcore_bankmachine2_state <= 3'd0;
- litedramcore_litedramcore_bankmachine3_state <= 3'd0;
- litedramcore_litedramcore_bankmachine4_state <= 3'd0;
- litedramcore_litedramcore_bankmachine5_state <= 3'd0;
- litedramcore_litedramcore_bankmachine6_state <= 3'd0;
- litedramcore_litedramcore_bankmachine7_state <= 3'd0;
- litedramcore_litedramcore_multiplexer_state <= 4'd0;
- litedramcore_litedramcore_new_master_wdata_ready0 <= 1'd0;
- litedramcore_litedramcore_new_master_wdata_ready1 <= 1'd0;
- litedramcore_litedramcore_new_master_wdata_ready2 <= 1'd0;
- litedramcore_litedramcore_new_master_wdata_ready3 <= 1'd0;
- litedramcore_litedramcore_new_master_rdata_valid0 <= 1'd0;
- litedramcore_litedramcore_new_master_rdata_valid1 <= 1'd0;
- litedramcore_litedramcore_new_master_rdata_valid2 <= 1'd0;
- litedramcore_litedramcore_new_master_rdata_valid3 <= 1'd0;
- litedramcore_litedramcore_new_master_rdata_valid4 <= 1'd0;
- litedramcore_litedramcore_new_master_rdata_valid5 <= 1'd0;
- litedramcore_litedramcore_new_master_rdata_valid6 <= 1'd0;
- litedramcore_litedramcore_new_master_rdata_valid7 <= 1'd0;
- litedramcore_litedramcore_new_master_rdata_valid8 <= 1'd0;
- litedramcore_litedramcore_new_master_rdata_valid9 <= 1'd0;
- litedramcore_litedramcore_new_master_rdata_valid10 <= 1'd0;
- litedramcore_litedramcore_new_master_rdata_valid11 <= 1'd0;
- litedramcore_litedramcore_new_master_rdata_valid12 <= 1'd0;
- litedramcore_litedramcore_new_master_rdata_valid13 <= 1'd0;
- litedramcore_state <= 2'd0;
- end
+ if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_rst_re)) begin
+ ddrphy_rdly0 <= 1'd0;
+ end
+ if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_inc_re)) begin
+ ddrphy_rdly0 <= (ddrphy_rdly0 + 1'd1);
+ end
+ ddrphy_burstdet_d0 <= ddrphy_burstdet0;
+ if (ddrphy_burstdet_clr_re) begin
+ ddrphy_burstdet_seen_status[0] <= 1'd0;
+ end
+ if ((ddrphy_burstdet0 & (~ddrphy_burstdet_d0))) begin
+ ddrphy_burstdet_seen_status[0] <= 1'd1;
+ end
+ ddrphy_dm_o_data_d0 <= ddrphy_dm_o_data0;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dm_o_data_muxed0 <= ddrphy_dm_o_data0[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dm_o_data_muxed0 <= ddrphy_dm_o_data_d0[7:4];
+ end
+ endcase
+ ddrphy_dq_o_data_d0 <= ddrphy_dq_o_data0;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed0 <= ddrphy_dq_o_data0[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed0 <= ddrphy_dq_o_data_d0[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d0 <= ddrphy_bitslip0_o;
+ ddrphy_dq_o_data_d1 <= ddrphy_dq_o_data1;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed1 <= ddrphy_dq_o_data1[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed1 <= ddrphy_dq_o_data_d1[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d1 <= ddrphy_bitslip1_o;
+ ddrphy_dq_o_data_d2 <= ddrphy_dq_o_data2;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed2 <= ddrphy_dq_o_data2[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed2 <= ddrphy_dq_o_data_d2[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d2 <= ddrphy_bitslip2_o;
+ ddrphy_dq_o_data_d3 <= ddrphy_dq_o_data3;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed3 <= ddrphy_dq_o_data3[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed3 <= ddrphy_dq_o_data_d3[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d3 <= ddrphy_bitslip3_o;
+ ddrphy_dq_o_data_d4 <= ddrphy_dq_o_data4;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed4 <= ddrphy_dq_o_data4[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed4 <= ddrphy_dq_o_data_d4[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d4 <= ddrphy_bitslip4_o;
+ ddrphy_dq_o_data_d5 <= ddrphy_dq_o_data5;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed5 <= ddrphy_dq_o_data5[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed5 <= ddrphy_dq_o_data_d5[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d5 <= ddrphy_bitslip5_o;
+ ddrphy_dq_o_data_d6 <= ddrphy_dq_o_data6;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed6 <= ddrphy_dq_o_data6[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed6 <= ddrphy_dq_o_data_d6[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d6 <= ddrphy_bitslip6_o;
+ ddrphy_dq_o_data_d7 <= ddrphy_dq_o_data7;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed7 <= ddrphy_dq_o_data7[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed7 <= ddrphy_dq_o_data_d7[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d7 <= ddrphy_bitslip7_o;
+ if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_rst_re)) begin
+ ddrphy_rdly1 <= 1'd0;
+ end
+ if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_inc_re)) begin
+ ddrphy_rdly1 <= (ddrphy_rdly1 + 1'd1);
+ end
+ ddrphy_burstdet_d1 <= ddrphy_burstdet1;
+ if (ddrphy_burstdet_clr_re) begin
+ ddrphy_burstdet_seen_status[1] <= 1'd0;
+ end
+ if ((ddrphy_burstdet1 & (~ddrphy_burstdet_d1))) begin
+ ddrphy_burstdet_seen_status[1] <= 1'd1;
+ end
+ ddrphy_dm_o_data_d1 <= ddrphy_dm_o_data1;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dm_o_data_muxed1 <= ddrphy_dm_o_data1[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dm_o_data_muxed1 <= ddrphy_dm_o_data_d1[7:4];
+ end
+ endcase
+ ddrphy_dq_o_data_d8 <= ddrphy_dq_o_data8;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed8 <= ddrphy_dq_o_data8[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed8 <= ddrphy_dq_o_data_d8[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d8 <= ddrphy_bitslip8_o;
+ ddrphy_dq_o_data_d9 <= ddrphy_dq_o_data9;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed9 <= ddrphy_dq_o_data9[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed9 <= ddrphy_dq_o_data_d9[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d9 <= ddrphy_bitslip9_o;
+ ddrphy_dq_o_data_d10 <= ddrphy_dq_o_data10;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed10 <= ddrphy_dq_o_data10[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed10 <= ddrphy_dq_o_data_d10[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d10 <= ddrphy_bitslip10_o;
+ ddrphy_dq_o_data_d11 <= ddrphy_dq_o_data11;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed11 <= ddrphy_dq_o_data11[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed11 <= ddrphy_dq_o_data_d11[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d11 <= ddrphy_bitslip11_o;
+ ddrphy_dq_o_data_d12 <= ddrphy_dq_o_data12;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed12 <= ddrphy_dq_o_data12[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed12 <= ddrphy_dq_o_data_d12[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d12 <= ddrphy_bitslip12_o;
+ ddrphy_dq_o_data_d13 <= ddrphy_dq_o_data13;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed13 <= ddrphy_dq_o_data13[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed13 <= ddrphy_dq_o_data_d13[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d13 <= ddrphy_bitslip13_o;
+ ddrphy_dq_o_data_d14 <= ddrphy_dq_o_data14;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed14 <= ddrphy_dq_o_data14[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed14 <= ddrphy_dq_o_data_d14[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d14 <= ddrphy_bitslip14_o;
+ ddrphy_dq_o_data_d15 <= ddrphy_dq_o_data15;
+ case (ddrphy_bl8_chunk)
+ 1'd0: begin
+ ddrphy_dq_o_data_muxed15 <= ddrphy_dq_o_data15[3:0];
+ end
+ 1'd1: begin
+ ddrphy_dq_o_data_muxed15 <= ddrphy_dq_o_data_d15[7:4];
+ end
+ endcase
+ ddrphy_dq_i_bitslip_o_d15 <= ddrphy_bitslip15_o;
+ if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip0_value <= (ddrphy_bitslip0_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip0_value <= 1'd0;
+ end
+ ddrphy_bitslip0_r <= {ddrphy_bitslip0_i, ddrphy_bitslip0_r[7:4]};
+ if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip1_value <= (ddrphy_bitslip1_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip1_value <= 1'd0;
+ end
+ ddrphy_bitslip1_r <= {ddrphy_bitslip1_i, ddrphy_bitslip1_r[7:4]};
+ if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip2_value <= (ddrphy_bitslip2_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip2_value <= 1'd0;
+ end
+ ddrphy_bitslip2_r <= {ddrphy_bitslip2_i, ddrphy_bitslip2_r[7:4]};
+ if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip3_value <= (ddrphy_bitslip3_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip3_value <= 1'd0;
+ end
+ ddrphy_bitslip3_r <= {ddrphy_bitslip3_i, ddrphy_bitslip3_r[7:4]};
+ if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip4_value <= (ddrphy_bitslip4_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip4_value <= 1'd0;
+ end
+ ddrphy_bitslip4_r <= {ddrphy_bitslip4_i, ddrphy_bitslip4_r[7:4]};
+ if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip5_value <= (ddrphy_bitslip5_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip5_value <= 1'd0;
+ end
+ ddrphy_bitslip5_r <= {ddrphy_bitslip5_i, ddrphy_bitslip5_r[7:4]};
+ if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip6_value <= (ddrphy_bitslip6_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip6_value <= 1'd0;
+ end
+ ddrphy_bitslip6_r <= {ddrphy_bitslip6_i, ddrphy_bitslip6_r[7:4]};
+ if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip7_value <= (ddrphy_bitslip7_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[0] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip7_value <= 1'd0;
+ end
+ ddrphy_bitslip7_r <= {ddrphy_bitslip7_i, ddrphy_bitslip7_r[7:4]};
+ if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip8_value <= (ddrphy_bitslip8_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip8_value <= 1'd0;
+ end
+ ddrphy_bitslip8_r <= {ddrphy_bitslip8_i, ddrphy_bitslip8_r[7:4]};
+ if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip9_value <= (ddrphy_bitslip9_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip9_value <= 1'd0;
+ end
+ ddrphy_bitslip9_r <= {ddrphy_bitslip9_i, ddrphy_bitslip9_r[7:4]};
+ if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip10_value <= (ddrphy_bitslip10_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip10_value <= 1'd0;
+ end
+ ddrphy_bitslip10_r <= {ddrphy_bitslip10_i, ddrphy_bitslip10_r[7:4]};
+ if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip11_value <= (ddrphy_bitslip11_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip11_value <= 1'd0;
+ end
+ ddrphy_bitslip11_r <= {ddrphy_bitslip11_i, ddrphy_bitslip11_r[7:4]};
+ if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip12_value <= (ddrphy_bitslip12_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip12_value <= 1'd0;
+ end
+ ddrphy_bitslip12_r <= {ddrphy_bitslip12_i, ddrphy_bitslip12_r[7:4]};
+ if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip13_value <= (ddrphy_bitslip13_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip13_value <= 1'd0;
+ end
+ ddrphy_bitslip13_r <= {ddrphy_bitslip13_i, ddrphy_bitslip13_r[7:4]};
+ if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip14_value <= (ddrphy_bitslip14_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip14_value <= 1'd0;
+ end
+ ddrphy_bitslip14_r <= {ddrphy_bitslip14_i, ddrphy_bitslip14_r[7:4]};
+ if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_re)) begin
+ ddrphy_bitslip15_value <= (ddrphy_bitslip15_value + 1'd1);
+ end
+ if ((ddrphy_dly_sel_storage[1] & ddrphy_rdly_dq_bitslip_rst_re)) begin
+ ddrphy_bitslip15_value <= 1'd0;
+ end
+ ddrphy_bitslip15_r <= {ddrphy_bitslip15_i, ddrphy_bitslip15_r[7:4]};
+ ddrphy_rddata_en_tappeddelayline0 <= (ddrphy_dfi_p0_rddata_en | ddrphy_dfi_p1_rddata_en);
+ ddrphy_rddata_en_tappeddelayline1 <= ddrphy_rddata_en_tappeddelayline0;
+ ddrphy_rddata_en_tappeddelayline2 <= ddrphy_rddata_en_tappeddelayline1;
+ ddrphy_rddata_en_tappeddelayline3 <= ddrphy_rddata_en_tappeddelayline2;
+ ddrphy_rddata_en_tappeddelayline4 <= ddrphy_rddata_en_tappeddelayline3;
+ ddrphy_rddata_en_tappeddelayline5 <= ddrphy_rddata_en_tappeddelayline4;
+ ddrphy_rddata_en_tappeddelayline6 <= ddrphy_rddata_en_tappeddelayline5;
+ ddrphy_rddata_en_tappeddelayline7 <= ddrphy_rddata_en_tappeddelayline6;
+ ddrphy_rddata_en_tappeddelayline8 <= ddrphy_rddata_en_tappeddelayline7;
+ ddrphy_rddata_en_tappeddelayline9 <= ddrphy_rddata_en_tappeddelayline8;
+ ddrphy_rddata_en_tappeddelayline10 <= ddrphy_rddata_en_tappeddelayline9;
+ ddrphy_rddata_en_tappeddelayline11 <= ddrphy_rddata_en_tappeddelayline10;
+ ddrphy_rddata_en_tappeddelayline12 <= ddrphy_rddata_en_tappeddelayline11;
+ ddrphy_wrdata_en_tappeddelayline0 <= (ddrphy_dfi_p0_wrdata_en | ddrphy_dfi_p1_wrdata_en);
+ ddrphy_wrdata_en_tappeddelayline1 <= ddrphy_wrdata_en_tappeddelayline0;
+ ddrphy_wrdata_en_tappeddelayline2 <= ddrphy_wrdata_en_tappeddelayline1;
+ ddrphy_wrdata_en_tappeddelayline3 <= ddrphy_wrdata_en_tappeddelayline2;
+ ddrphy_wrdata_en_tappeddelayline4 <= ddrphy_wrdata_en_tappeddelayline3;
+ ddrphy_wrdata_en_tappeddelayline5 <= ddrphy_wrdata_en_tappeddelayline4;
+ ddrphy_wrdata_en_tappeddelayline6 <= ddrphy_wrdata_en_tappeddelayline5;
+ if (litedramcore_csr_dfi_p0_rddata_valid) begin
+ litedramcore_phaseinjector0_rddata_status <= litedramcore_csr_dfi_p0_rddata;
+ end
+ if (litedramcore_csr_dfi_p1_rddata_valid) begin
+ litedramcore_phaseinjector1_rddata_status <= litedramcore_csr_dfi_p1_rddata;
+ end
+ if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin
+ litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1);
+ end else begin
+ litedramcore_timer_count1 <= 9'd374;
+ end
+ litedramcore_postponer_req_o <= 1'd0;
+ if (litedramcore_postponer_req_i) begin
+ litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1);
+ if ((litedramcore_postponer_count == 1'd0)) begin
+ litedramcore_postponer_count <= 1'd0;
+ litedramcore_postponer_req_o <= 1'd1;
+ end
+ end
+ if (litedramcore_sequencer_start0) begin
+ litedramcore_sequencer_count <= 1'd0;
+ end else begin
+ if (litedramcore_sequencer_done1) begin
+ if ((litedramcore_sequencer_count != 1'd0)) begin
+ litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1);
+ end
+ end
+ end
+ litedramcore_cmd_payload_a <= 1'd0;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd0;
+ litedramcore_cmd_payload_we <= 1'd0;
+ litedramcore_sequencer_done1 <= 1'd0;
+ if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin
+ litedramcore_cmd_payload_a <= 11'd1024;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd1;
+ litedramcore_cmd_payload_we <= 1'd1;
+ end
+ if ((litedramcore_sequencer_counter == 2'd2)) begin
+ litedramcore_cmd_payload_a <= 11'd1024;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd1;
+ litedramcore_cmd_payload_ras <= 1'd1;
+ litedramcore_cmd_payload_we <= 1'd0;
+ end
+ if ((litedramcore_sequencer_counter == 7'd106)) begin
+ litedramcore_cmd_payload_a <= 1'd0;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd0;
+ litedramcore_cmd_payload_we <= 1'd0;
+ litedramcore_sequencer_done1 <= 1'd1;
+ end
+ if ((litedramcore_sequencer_counter == 7'd106)) begin
+ litedramcore_sequencer_counter <= 1'd0;
+ end else begin
+ if ((litedramcore_sequencer_counter != 1'd0)) begin
+ litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1);
+ end else begin
+ if (litedramcore_sequencer_start1) begin
+ litedramcore_sequencer_counter <= 1'd1;
+ end
+ end
+ end
+ if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin
+ litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1);
+ end else begin
+ litedramcore_zqcs_timer_count1 <= 26'd47999999;
+ end
+ litedramcore_zqcs_executer_done <= 1'd0;
+ if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin
+ litedramcore_cmd_payload_a <= 11'd1024;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd1;
+ litedramcore_cmd_payload_we <= 1'd1;
+ end
+ if ((litedramcore_zqcs_executer_counter == 2'd2)) begin
+ litedramcore_cmd_payload_a <= 1'd0;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd0;
+ litedramcore_cmd_payload_we <= 1'd1;
+ end
+ if ((litedramcore_zqcs_executer_counter == 6'd34)) begin
+ litedramcore_cmd_payload_a <= 1'd0;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd0;
+ litedramcore_cmd_payload_we <= 1'd0;
+ litedramcore_zqcs_executer_done <= 1'd1;
+ end
+ if ((litedramcore_zqcs_executer_counter == 6'd34)) begin
+ litedramcore_zqcs_executer_counter <= 1'd0;
+ end else begin
+ if ((litedramcore_zqcs_executer_counter != 1'd0)) begin
+ litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1);
+ end else begin
+ if (litedramcore_zqcs_executer_start) begin
+ litedramcore_zqcs_executer_counter <= 1'd1;
+ end
+ end
+ end
+ litedramcore_litedramcore_refresher_state <= litedramcore_litedramcore_refresher_next_state;
+ if (litedramcore_bankmachine0_row_close) begin
+ litedramcore_bankmachine0_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine0_row_open) begin
+ litedramcore_bankmachine0_row_opened <= 1'd1;
+ litedramcore_bankmachine0_row <= litedramcore_bankmachine0_source_source_payload_addr[21:7];
+ end
+ end
+ if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin
+ litedramcore_bankmachine0_produce <= (litedramcore_bankmachine0_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine0_do_read) begin
+ litedramcore_bankmachine0_consume <= (litedramcore_bankmachine0_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin
+ if ((~litedramcore_bankmachine0_do_read)) begin
+ litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine0_do_read) begin
+ litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine0_pipe_valid_source_valid <= litedramcore_bankmachine0_pipe_valid_sink_valid;
+ litedramcore_bankmachine0_pipe_valid_source_first <= litedramcore_bankmachine0_pipe_valid_sink_first;
+ litedramcore_bankmachine0_pipe_valid_source_last <= litedramcore_bankmachine0_pipe_valid_sink_last;
+ litedramcore_bankmachine0_pipe_valid_source_payload_we <= litedramcore_bankmachine0_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine0_pipe_valid_source_payload_addr <= litedramcore_bankmachine0_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine0_twtpcon_valid) begin
+ litedramcore_bankmachine0_twtpcon_count <= 3'd6;
+ if (1'd0) begin
+ litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine0_twtpcon_ready)) begin
+ litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine0_trccon_valid) begin
+ litedramcore_bankmachine0_trccon_count <= 2'd2;
+ if (1'd0) begin
+ litedramcore_bankmachine0_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine0_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine0_trccon_ready)) begin
+ litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine0_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine0_trascon_valid) begin
+ litedramcore_bankmachine0_trascon_count <= 2'd2;
+ if (1'd0) begin
+ litedramcore_bankmachine0_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine0_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine0_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_litedramcore_bankmachine0_state <= litedramcore_litedramcore_bankmachine0_next_state;
+ if (litedramcore_bankmachine1_row_close) begin
+ litedramcore_bankmachine1_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine1_row_open) begin
+ litedramcore_bankmachine1_row_opened <= 1'd1;
+ litedramcore_bankmachine1_row <= litedramcore_bankmachine1_source_source_payload_addr[21:7];
+ end
+ end
+ if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin
+ litedramcore_bankmachine1_produce <= (litedramcore_bankmachine1_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine1_do_read) begin
+ litedramcore_bankmachine1_consume <= (litedramcore_bankmachine1_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin
+ if ((~litedramcore_bankmachine1_do_read)) begin
+ litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine1_do_read) begin
+ litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine1_pipe_valid_source_valid <= litedramcore_bankmachine1_pipe_valid_sink_valid;
+ litedramcore_bankmachine1_pipe_valid_source_first <= litedramcore_bankmachine1_pipe_valid_sink_first;
+ litedramcore_bankmachine1_pipe_valid_source_last <= litedramcore_bankmachine1_pipe_valid_sink_last;
+ litedramcore_bankmachine1_pipe_valid_source_payload_we <= litedramcore_bankmachine1_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine1_pipe_valid_source_payload_addr <= litedramcore_bankmachine1_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine1_twtpcon_valid) begin
+ litedramcore_bankmachine1_twtpcon_count <= 3'd6;
+ if (1'd0) begin
+ litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine1_twtpcon_ready)) begin
+ litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine1_trccon_valid) begin
+ litedramcore_bankmachine1_trccon_count <= 2'd2;
+ if (1'd0) begin
+ litedramcore_bankmachine1_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine1_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine1_trccon_ready)) begin
+ litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine1_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine1_trascon_valid) begin
+ litedramcore_bankmachine1_trascon_count <= 2'd2;
+ if (1'd0) begin
+ litedramcore_bankmachine1_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine1_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine1_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_litedramcore_bankmachine1_state <= litedramcore_litedramcore_bankmachine1_next_state;
+ if (litedramcore_bankmachine2_row_close) begin
+ litedramcore_bankmachine2_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine2_row_open) begin
+ litedramcore_bankmachine2_row_opened <= 1'd1;
+ litedramcore_bankmachine2_row <= litedramcore_bankmachine2_source_source_payload_addr[21:7];
+ end
+ end
+ if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin
+ litedramcore_bankmachine2_produce <= (litedramcore_bankmachine2_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine2_do_read) begin
+ litedramcore_bankmachine2_consume <= (litedramcore_bankmachine2_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin
+ if ((~litedramcore_bankmachine2_do_read)) begin
+ litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine2_do_read) begin
+ litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine2_pipe_valid_source_valid <= litedramcore_bankmachine2_pipe_valid_sink_valid;
+ litedramcore_bankmachine2_pipe_valid_source_first <= litedramcore_bankmachine2_pipe_valid_sink_first;
+ litedramcore_bankmachine2_pipe_valid_source_last <= litedramcore_bankmachine2_pipe_valid_sink_last;
+ litedramcore_bankmachine2_pipe_valid_source_payload_we <= litedramcore_bankmachine2_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine2_pipe_valid_source_payload_addr <= litedramcore_bankmachine2_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine2_twtpcon_valid) begin
+ litedramcore_bankmachine2_twtpcon_count <= 3'd6;
+ if (1'd0) begin
+ litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine2_twtpcon_ready)) begin
+ litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine2_trccon_valid) begin
+ litedramcore_bankmachine2_trccon_count <= 2'd2;
+ if (1'd0) begin
+ litedramcore_bankmachine2_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine2_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine2_trccon_ready)) begin
+ litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine2_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine2_trascon_valid) begin
+ litedramcore_bankmachine2_trascon_count <= 2'd2;
+ if (1'd0) begin
+ litedramcore_bankmachine2_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine2_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine2_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_litedramcore_bankmachine2_state <= litedramcore_litedramcore_bankmachine2_next_state;
+ if (litedramcore_bankmachine3_row_close) begin
+ litedramcore_bankmachine3_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine3_row_open) begin
+ litedramcore_bankmachine3_row_opened <= 1'd1;
+ litedramcore_bankmachine3_row <= litedramcore_bankmachine3_source_source_payload_addr[21:7];
+ end
+ end
+ if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin
+ litedramcore_bankmachine3_produce <= (litedramcore_bankmachine3_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine3_do_read) begin
+ litedramcore_bankmachine3_consume <= (litedramcore_bankmachine3_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin
+ if ((~litedramcore_bankmachine3_do_read)) begin
+ litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine3_do_read) begin
+ litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine3_pipe_valid_source_valid <= litedramcore_bankmachine3_pipe_valid_sink_valid;
+ litedramcore_bankmachine3_pipe_valid_source_first <= litedramcore_bankmachine3_pipe_valid_sink_first;
+ litedramcore_bankmachine3_pipe_valid_source_last <= litedramcore_bankmachine3_pipe_valid_sink_last;
+ litedramcore_bankmachine3_pipe_valid_source_payload_we <= litedramcore_bankmachine3_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine3_pipe_valid_source_payload_addr <= litedramcore_bankmachine3_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine3_twtpcon_valid) begin
+ litedramcore_bankmachine3_twtpcon_count <= 3'd6;
+ if (1'd0) begin
+ litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine3_twtpcon_ready)) begin
+ litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine3_trccon_valid) begin
+ litedramcore_bankmachine3_trccon_count <= 2'd2;
+ if (1'd0) begin
+ litedramcore_bankmachine3_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine3_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine3_trccon_ready)) begin
+ litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine3_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine3_trascon_valid) begin
+ litedramcore_bankmachine3_trascon_count <= 2'd2;
+ if (1'd0) begin
+ litedramcore_bankmachine3_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine3_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine3_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_litedramcore_bankmachine3_state <= litedramcore_litedramcore_bankmachine3_next_state;
+ if (litedramcore_bankmachine4_row_close) begin
+ litedramcore_bankmachine4_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine4_row_open) begin
+ litedramcore_bankmachine4_row_opened <= 1'd1;
+ litedramcore_bankmachine4_row <= litedramcore_bankmachine4_source_source_payload_addr[21:7];
+ end
+ end
+ if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin
+ litedramcore_bankmachine4_produce <= (litedramcore_bankmachine4_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine4_do_read) begin
+ litedramcore_bankmachine4_consume <= (litedramcore_bankmachine4_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin
+ if ((~litedramcore_bankmachine4_do_read)) begin
+ litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine4_do_read) begin
+ litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine4_pipe_valid_source_valid <= litedramcore_bankmachine4_pipe_valid_sink_valid;
+ litedramcore_bankmachine4_pipe_valid_source_first <= litedramcore_bankmachine4_pipe_valid_sink_first;
+ litedramcore_bankmachine4_pipe_valid_source_last <= litedramcore_bankmachine4_pipe_valid_sink_last;
+ litedramcore_bankmachine4_pipe_valid_source_payload_we <= litedramcore_bankmachine4_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine4_pipe_valid_source_payload_addr <= litedramcore_bankmachine4_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine4_twtpcon_valid) begin
+ litedramcore_bankmachine4_twtpcon_count <= 3'd6;
+ if (1'd0) begin
+ litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine4_twtpcon_ready)) begin
+ litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine4_trccon_valid) begin
+ litedramcore_bankmachine4_trccon_count <= 2'd2;
+ if (1'd0) begin
+ litedramcore_bankmachine4_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine4_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine4_trccon_ready)) begin
+ litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine4_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine4_trascon_valid) begin
+ litedramcore_bankmachine4_trascon_count <= 2'd2;
+ if (1'd0) begin
+ litedramcore_bankmachine4_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine4_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine4_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_litedramcore_bankmachine4_state <= litedramcore_litedramcore_bankmachine4_next_state;
+ if (litedramcore_bankmachine5_row_close) begin
+ litedramcore_bankmachine5_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine5_row_open) begin
+ litedramcore_bankmachine5_row_opened <= 1'd1;
+ litedramcore_bankmachine5_row <= litedramcore_bankmachine5_source_source_payload_addr[21:7];
+ end
+ end
+ if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin
+ litedramcore_bankmachine5_produce <= (litedramcore_bankmachine5_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine5_do_read) begin
+ litedramcore_bankmachine5_consume <= (litedramcore_bankmachine5_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin
+ if ((~litedramcore_bankmachine5_do_read)) begin
+ litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine5_do_read) begin
+ litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine5_pipe_valid_source_valid <= litedramcore_bankmachine5_pipe_valid_sink_valid;
+ litedramcore_bankmachine5_pipe_valid_source_first <= litedramcore_bankmachine5_pipe_valid_sink_first;
+ litedramcore_bankmachine5_pipe_valid_source_last <= litedramcore_bankmachine5_pipe_valid_sink_last;
+ litedramcore_bankmachine5_pipe_valid_source_payload_we <= litedramcore_bankmachine5_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine5_pipe_valid_source_payload_addr <= litedramcore_bankmachine5_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine5_twtpcon_valid) begin
+ litedramcore_bankmachine5_twtpcon_count <= 3'd6;
+ if (1'd0) begin
+ litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine5_twtpcon_ready)) begin
+ litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine5_trccon_valid) begin
+ litedramcore_bankmachine5_trccon_count <= 2'd2;
+ if (1'd0) begin
+ litedramcore_bankmachine5_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine5_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine5_trccon_ready)) begin
+ litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine5_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine5_trascon_valid) begin
+ litedramcore_bankmachine5_trascon_count <= 2'd2;
+ if (1'd0) begin
+ litedramcore_bankmachine5_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine5_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine5_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_litedramcore_bankmachine5_state <= litedramcore_litedramcore_bankmachine5_next_state;
+ if (litedramcore_bankmachine6_row_close) begin
+ litedramcore_bankmachine6_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine6_row_open) begin
+ litedramcore_bankmachine6_row_opened <= 1'd1;
+ litedramcore_bankmachine6_row <= litedramcore_bankmachine6_source_source_payload_addr[21:7];
+ end
+ end
+ if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin
+ litedramcore_bankmachine6_produce <= (litedramcore_bankmachine6_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine6_do_read) begin
+ litedramcore_bankmachine6_consume <= (litedramcore_bankmachine6_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin
+ if ((~litedramcore_bankmachine6_do_read)) begin
+ litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine6_do_read) begin
+ litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine6_pipe_valid_source_valid <= litedramcore_bankmachine6_pipe_valid_sink_valid;
+ litedramcore_bankmachine6_pipe_valid_source_first <= litedramcore_bankmachine6_pipe_valid_sink_first;
+ litedramcore_bankmachine6_pipe_valid_source_last <= litedramcore_bankmachine6_pipe_valid_sink_last;
+ litedramcore_bankmachine6_pipe_valid_source_payload_we <= litedramcore_bankmachine6_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine6_pipe_valid_source_payload_addr <= litedramcore_bankmachine6_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine6_twtpcon_valid) begin
+ litedramcore_bankmachine6_twtpcon_count <= 3'd6;
+ if (1'd0) begin
+ litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine6_twtpcon_ready)) begin
+ litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine6_trccon_valid) begin
+ litedramcore_bankmachine6_trccon_count <= 2'd2;
+ if (1'd0) begin
+ litedramcore_bankmachine6_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine6_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine6_trccon_ready)) begin
+ litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine6_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine6_trascon_valid) begin
+ litedramcore_bankmachine6_trascon_count <= 2'd2;
+ if (1'd0) begin
+ litedramcore_bankmachine6_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine6_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine6_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_litedramcore_bankmachine6_state <= litedramcore_litedramcore_bankmachine6_next_state;
+ if (litedramcore_bankmachine7_row_close) begin
+ litedramcore_bankmachine7_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine7_row_open) begin
+ litedramcore_bankmachine7_row_opened <= 1'd1;
+ litedramcore_bankmachine7_row <= litedramcore_bankmachine7_source_source_payload_addr[21:7];
+ end
+ end
+ if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin
+ litedramcore_bankmachine7_produce <= (litedramcore_bankmachine7_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine7_do_read) begin
+ litedramcore_bankmachine7_consume <= (litedramcore_bankmachine7_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin
+ if ((~litedramcore_bankmachine7_do_read)) begin
+ litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine7_do_read) begin
+ litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine7_pipe_valid_source_valid <= litedramcore_bankmachine7_pipe_valid_sink_valid;
+ litedramcore_bankmachine7_pipe_valid_source_first <= litedramcore_bankmachine7_pipe_valid_sink_first;
+ litedramcore_bankmachine7_pipe_valid_source_last <= litedramcore_bankmachine7_pipe_valid_sink_last;
+ litedramcore_bankmachine7_pipe_valid_source_payload_we <= litedramcore_bankmachine7_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine7_pipe_valid_source_payload_addr <= litedramcore_bankmachine7_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine7_twtpcon_valid) begin
+ litedramcore_bankmachine7_twtpcon_count <= 3'd6;
+ if (1'd0) begin
+ litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine7_twtpcon_ready)) begin
+ litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine7_trccon_valid) begin
+ litedramcore_bankmachine7_trccon_count <= 2'd2;
+ if (1'd0) begin
+ litedramcore_bankmachine7_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine7_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine7_trccon_ready)) begin
+ litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine7_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine7_trascon_valid) begin
+ litedramcore_bankmachine7_trascon_count <= 2'd2;
+ if (1'd0) begin
+ litedramcore_bankmachine7_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine7_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine7_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_litedramcore_bankmachine7_state <= litedramcore_litedramcore_bankmachine7_next_state;
+ if ((~litedramcore_en0)) begin
+ litedramcore_time0 <= 5'd31;
+ end else begin
+ if ((~litedramcore_max_time0)) begin
+ litedramcore_time0 <= (litedramcore_time0 - 1'd1);
+ end
+ end
+ if ((~litedramcore_en1)) begin
+ litedramcore_time1 <= 4'd15;
+ end else begin
+ if ((~litedramcore_max_time1)) begin
+ litedramcore_time1 <= (litedramcore_time1 - 1'd1);
+ end
+ end
+ if (litedramcore_choose_cmd_ce) begin
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 1'd1: begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 2'd2: begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd4: begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd5: begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd6: begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd7: begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ endcase
+ end
+ if (litedramcore_choose_req_ce) begin
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 1'd1: begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 2'd2: begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd4: begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd5: begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd6: begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd7: begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ endcase
+ end
+ litedramcore_dfi_p0_cs_n <= 1'd0;
+ litedramcore_dfi_p0_bank <= array_muxed0;
+ litedramcore_dfi_p0_address <= array_muxed1;
+ litedramcore_dfi_p0_cas_n <= (~array_muxed2);
+ litedramcore_dfi_p0_ras_n <= (~array_muxed3);
+ litedramcore_dfi_p0_we_n <= (~array_muxed4);
+ litedramcore_dfi_p0_rddata_en <= array_muxed5;
+ litedramcore_dfi_p0_wrdata_en <= array_muxed6;
+ litedramcore_dfi_p1_cs_n <= 1'd0;
+ litedramcore_dfi_p1_bank <= array_muxed7;
+ litedramcore_dfi_p1_address <= array_muxed8;
+ litedramcore_dfi_p1_cas_n <= (~array_muxed9);
+ litedramcore_dfi_p1_ras_n <= (~array_muxed10);
+ litedramcore_dfi_p1_we_n <= (~array_muxed11);
+ litedramcore_dfi_p1_rddata_en <= array_muxed12;
+ litedramcore_dfi_p1_wrdata_en <= array_muxed13;
+ if (litedramcore_trrdcon_valid) begin
+ litedramcore_trrdcon_count <= 1'd1;
+ if (1'd0) begin
+ litedramcore_trrdcon_ready <= 1'd1;
+ end else begin
+ litedramcore_trrdcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_trrdcon_ready)) begin
+ litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1);
+ if ((litedramcore_trrdcon_count == 1'd1)) begin
+ litedramcore_trrdcon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid};
+ if ((litedramcore_tfawcon_count < 3'd4)) begin
+ if ((litedramcore_tfawcon_count == 2'd3)) begin
+ litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid);
+ end else begin
+ litedramcore_tfawcon_ready <= 1'd1;
+ end
+ end
+ if (litedramcore_tccdcon_valid) begin
+ litedramcore_tccdcon_count <= 1'd1;
+ if (1'd0) begin
+ litedramcore_tccdcon_ready <= 1'd1;
+ end else begin
+ litedramcore_tccdcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_tccdcon_ready)) begin
+ litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1);
+ if ((litedramcore_tccdcon_count == 1'd1)) begin
+ litedramcore_tccdcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_twtrcon_valid) begin
+ litedramcore_twtrcon_count <= 3'd6;
+ if (1'd0) begin
+ litedramcore_twtrcon_ready <= 1'd1;
+ end else begin
+ litedramcore_twtrcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_twtrcon_ready)) begin
+ litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1);
+ if ((litedramcore_twtrcon_count == 1'd1)) begin
+ litedramcore_twtrcon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_litedramcore_multiplexer_state <= litedramcore_litedramcore_multiplexer_next_state;
+ litedramcore_litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready));
+ litedramcore_litedramcore_new_master_wdata_ready1 <= litedramcore_litedramcore_new_master_wdata_ready0;
+ litedramcore_litedramcore_new_master_wdata_ready2 <= litedramcore_litedramcore_new_master_wdata_ready1;
+ litedramcore_litedramcore_new_master_wdata_ready3 <= litedramcore_litedramcore_new_master_wdata_ready2;
+ litedramcore_litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid));
+ litedramcore_litedramcore_new_master_rdata_valid1 <= litedramcore_litedramcore_new_master_rdata_valid0;
+ litedramcore_litedramcore_new_master_rdata_valid2 <= litedramcore_litedramcore_new_master_rdata_valid1;
+ litedramcore_litedramcore_new_master_rdata_valid3 <= litedramcore_litedramcore_new_master_rdata_valid2;
+ litedramcore_litedramcore_new_master_rdata_valid4 <= litedramcore_litedramcore_new_master_rdata_valid3;
+ litedramcore_litedramcore_new_master_rdata_valid5 <= litedramcore_litedramcore_new_master_rdata_valid4;
+ litedramcore_litedramcore_new_master_rdata_valid6 <= litedramcore_litedramcore_new_master_rdata_valid5;
+ litedramcore_litedramcore_new_master_rdata_valid7 <= litedramcore_litedramcore_new_master_rdata_valid6;
+ litedramcore_litedramcore_new_master_rdata_valid8 <= litedramcore_litedramcore_new_master_rdata_valid7;
+ litedramcore_litedramcore_new_master_rdata_valid9 <= litedramcore_litedramcore_new_master_rdata_valid8;
+ litedramcore_litedramcore_new_master_rdata_valid10 <= litedramcore_litedramcore_new_master_rdata_valid9;
+ litedramcore_litedramcore_new_master_rdata_valid11 <= litedramcore_litedramcore_new_master_rdata_valid10;
+ litedramcore_litedramcore_new_master_rdata_valid12 <= litedramcore_litedramcore_new_master_rdata_valid11;
+ litedramcore_litedramcore_new_master_rdata_valid13 <= litedramcore_litedramcore_new_master_rdata_valid12;
+ litedramcore_state <= litedramcore_next_state;
+ if (litedramcore_dat_w_next_value_ce0) begin
+ litedramcore_dat_w <= litedramcore_dat_w_next_value0;
+ end
+ if (litedramcore_adr_next_value_ce1) begin
+ litedramcore_adr <= litedramcore_adr_next_value1;
+ end
+ if (litedramcore_we_next_value_ce2) begin
+ litedramcore_we <= litedramcore_we_next_value2;
+ end
+ interface0_bank_bus_dat_r <= 1'd0;
+ if (csrbank0_sel) begin
+ case (interface0_bank_bus_adr[8:0])
+ 1'd0: begin
+ interface0_bank_bus_dat_r <= csrbank0_init_done0_w;
+ end
+ 1'd1: begin
+ interface0_bank_bus_dat_r <= csrbank0_init_error0_w;
+ end
+ endcase
+ end
+ if (csrbank0_init_done0_re) begin
+ init_done_storage <= csrbank0_init_done0_r;
+ end
+ init_done_re <= csrbank0_init_done0_re;
+ if (csrbank0_init_error0_re) begin
+ init_error_storage <= csrbank0_init_error0_r;
+ end
+ init_error_re <= csrbank0_init_error0_re;
+ interface1_bank_bus_dat_r <= 1'd0;
+ if (csrbank1_sel) begin
+ case (interface1_bank_bus_adr[8:0])
+ 1'd0: begin
+ interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w;
+ end
+ 1'd1: begin
+ interface1_bank_bus_dat_r <= ddrphy_rdly_dq_rst_w;
+ end
+ 2'd2: begin
+ interface1_bank_bus_dat_r <= ddrphy_rdly_dq_inc_w;
+ end
+ 2'd3: begin
+ interface1_bank_bus_dat_r <= ddrphy_rdly_dq_bitslip_rst_w;
+ end
+ 3'd4: begin
+ interface1_bank_bus_dat_r <= ddrphy_rdly_dq_bitslip_w;
+ end
+ 3'd5: begin
+ interface1_bank_bus_dat_r <= ddrphy_burstdet_clr_w;
+ end
+ 3'd6: begin
+ interface1_bank_bus_dat_r <= csrbank1_burstdet_seen_w;
+ end
+ endcase
+ end
+ if (csrbank1_dly_sel0_re) begin
+ ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r;
+ end
+ ddrphy_dly_sel_re <= csrbank1_dly_sel0_re;
+ ddrphy_burstdet_seen_re <= csrbank1_burstdet_seen_re;
+ interface2_bank_bus_dat_r <= 1'd0;
+ if (csrbank2_sel) begin
+ case (interface2_bank_bus_adr[8:0])
+ 1'd0: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w;
+ end
+ 1'd1: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w;
+ end
+ 2'd2: begin
+ interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w;
+ end
+ 2'd3: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w;
+ end
+ 3'd4: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w;
+ end
+ 3'd5: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata1_w;
+ end
+ 3'd6: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w;
+ end
+ 3'd7: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata1_w;
+ end
+ 4'd8: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata0_w;
+ end
+ 4'd9: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w;
+ end
+ 4'd10: begin
+ interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w;
+ end
+ 4'd11: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w;
+ end
+ 4'd12: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w;
+ end
+ 4'd13: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata1_w;
+ end
+ 4'd14: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w;
+ end
+ 4'd15: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata1_w;
+ end
+ 5'd16: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata0_w;
+ end
+ endcase
+ end
+ if (csrbank2_dfii_control0_re) begin
+ litedramcore_storage[3:0] <= csrbank2_dfii_control0_r;
+ end
+ litedramcore_re <= csrbank2_dfii_control0_re;
+ if (csrbank2_dfii_pi0_command0_re) begin
+ litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r;
+ end
+ litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re;
+ if (csrbank2_dfii_pi0_address0_re) begin
+ litedramcore_phaseinjector0_address_storage[14:0] <= csrbank2_dfii_pi0_address0_r;
+ end
+ litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re;
+ if (csrbank2_dfii_pi0_baddress0_re) begin
+ litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r;
+ end
+ litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re;
+ if (csrbank2_dfii_pi0_wrdata1_re) begin
+ litedramcore_phaseinjector0_wrdata_storage[63:32] <= csrbank2_dfii_pi0_wrdata1_r;
+ end
+ if (csrbank2_dfii_pi0_wrdata0_re) begin
+ litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r;
+ end
+ litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re;
+ litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata0_re;
+ if (csrbank2_dfii_pi1_command0_re) begin
+ litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r;
+ end
+ litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re;
+ if (csrbank2_dfii_pi1_address0_re) begin
+ litedramcore_phaseinjector1_address_storage[14:0] <= csrbank2_dfii_pi1_address0_r;
+ end
+ litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re;
+ if (csrbank2_dfii_pi1_baddress0_re) begin
+ litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r;
+ end
+ litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re;
+ if (csrbank2_dfii_pi1_wrdata1_re) begin
+ litedramcore_phaseinjector1_wrdata_storage[63:32] <= csrbank2_dfii_pi1_wrdata1_r;
+ end
+ if (csrbank2_dfii_pi1_wrdata0_re) begin
+ litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r;
+ end
+ litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re;
+ litedramcore_phaseinjector1_rddata_re <= csrbank2_dfii_pi1_rddata0_re;
+ if (sys_rst) begin
+ ddrphy_dly_sel_storage <= 2'd0;
+ ddrphy_dly_sel_re <= 1'd0;
+ ddrphy_burstdet_seen_status <= 2'd0;
+ ddrphy_burstdet_seen_re <= 1'd0;
+ ddrphy_rdly0 <= 3'd0;
+ ddrphy_burstdet_d0 <= 1'd0;
+ ddrphy_dm_o_data_d0 <= 8'd0;
+ ddrphy_dm_o_data_muxed0 <= 4'd0;
+ ddrphy_dq_o_data_d0 <= 8'd0;
+ ddrphy_dq_o_data_muxed0 <= 4'd0;
+ ddrphy_bitslip0_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d0 <= 4'd0;
+ ddrphy_dq_o_data_d1 <= 8'd0;
+ ddrphy_dq_o_data_muxed1 <= 4'd0;
+ ddrphy_bitslip1_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d1 <= 4'd0;
+ ddrphy_dq_o_data_d2 <= 8'd0;
+ ddrphy_dq_o_data_muxed2 <= 4'd0;
+ ddrphy_bitslip2_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d2 <= 4'd0;
+ ddrphy_dq_o_data_d3 <= 8'd0;
+ ddrphy_dq_o_data_muxed3 <= 4'd0;
+ ddrphy_bitslip3_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d3 <= 4'd0;
+ ddrphy_dq_o_data_d4 <= 8'd0;
+ ddrphy_dq_o_data_muxed4 <= 4'd0;
+ ddrphy_bitslip4_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d4 <= 4'd0;
+ ddrphy_dq_o_data_d5 <= 8'd0;
+ ddrphy_dq_o_data_muxed5 <= 4'd0;
+ ddrphy_bitslip5_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d5 <= 4'd0;
+ ddrphy_dq_o_data_d6 <= 8'd0;
+ ddrphy_dq_o_data_muxed6 <= 4'd0;
+ ddrphy_bitslip6_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d6 <= 4'd0;
+ ddrphy_dq_o_data_d7 <= 8'd0;
+ ddrphy_dq_o_data_muxed7 <= 4'd0;
+ ddrphy_bitslip7_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d7 <= 4'd0;
+ ddrphy_rdly1 <= 3'd0;
+ ddrphy_burstdet_d1 <= 1'd0;
+ ddrphy_dm_o_data_d1 <= 8'd0;
+ ddrphy_dm_o_data_muxed1 <= 4'd0;
+ ddrphy_dq_o_data_d8 <= 8'd0;
+ ddrphy_dq_o_data_muxed8 <= 4'd0;
+ ddrphy_bitslip8_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d8 <= 4'd0;
+ ddrphy_dq_o_data_d9 <= 8'd0;
+ ddrphy_dq_o_data_muxed9 <= 4'd0;
+ ddrphy_bitslip9_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d9 <= 4'd0;
+ ddrphy_dq_o_data_d10 <= 8'd0;
+ ddrphy_dq_o_data_muxed10 <= 4'd0;
+ ddrphy_bitslip10_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d10 <= 4'd0;
+ ddrphy_dq_o_data_d11 <= 8'd0;
+ ddrphy_dq_o_data_muxed11 <= 4'd0;
+ ddrphy_bitslip11_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d11 <= 4'd0;
+ ddrphy_dq_o_data_d12 <= 8'd0;
+ ddrphy_dq_o_data_muxed12 <= 4'd0;
+ ddrphy_bitslip12_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d12 <= 4'd0;
+ ddrphy_dq_o_data_d13 <= 8'd0;
+ ddrphy_dq_o_data_muxed13 <= 4'd0;
+ ddrphy_bitslip13_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d13 <= 4'd0;
+ ddrphy_dq_o_data_d14 <= 8'd0;
+ ddrphy_dq_o_data_muxed14 <= 4'd0;
+ ddrphy_bitslip14_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d14 <= 4'd0;
+ ddrphy_dq_o_data_d15 <= 8'd0;
+ ddrphy_dq_o_data_muxed15 <= 4'd0;
+ ddrphy_bitslip15_value <= 2'd0;
+ ddrphy_dq_i_bitslip_o_d15 <= 4'd0;
+ ddrphy_rddata_en_tappeddelayline0 <= 1'd0;
+ ddrphy_rddata_en_tappeddelayline1 <= 1'd0;
+ ddrphy_rddata_en_tappeddelayline2 <= 1'd0;
+ ddrphy_rddata_en_tappeddelayline3 <= 1'd0;
+ ddrphy_rddata_en_tappeddelayline4 <= 1'd0;
+ ddrphy_rddata_en_tappeddelayline5 <= 1'd0;
+ ddrphy_rddata_en_tappeddelayline6 <= 1'd0;
+ ddrphy_rddata_en_tappeddelayline7 <= 1'd0;
+ ddrphy_rddata_en_tappeddelayline8 <= 1'd0;
+ ddrphy_rddata_en_tappeddelayline9 <= 1'd0;
+ ddrphy_rddata_en_tappeddelayline10 <= 1'd0;
+ ddrphy_rddata_en_tappeddelayline11 <= 1'd0;
+ ddrphy_rddata_en_tappeddelayline12 <= 1'd0;
+ ddrphy_wrdata_en_tappeddelayline0 <= 1'd0;
+ ddrphy_wrdata_en_tappeddelayline1 <= 1'd0;
+ ddrphy_wrdata_en_tappeddelayline2 <= 1'd0;
+ ddrphy_wrdata_en_tappeddelayline3 <= 1'd0;
+ ddrphy_wrdata_en_tappeddelayline4 <= 1'd0;
+ ddrphy_wrdata_en_tappeddelayline5 <= 1'd0;
+ ddrphy_wrdata_en_tappeddelayline6 <= 1'd0;
+ litedramcore_storage <= 4'd1;
+ litedramcore_re <= 1'd0;
+ litedramcore_phaseinjector0_command_storage <= 6'd0;
+ litedramcore_phaseinjector0_command_re <= 1'd0;
+ litedramcore_phaseinjector0_address_re <= 1'd0;
+ litedramcore_phaseinjector0_baddress_re <= 1'd0;
+ litedramcore_phaseinjector0_wrdata_re <= 1'd0;
+ litedramcore_phaseinjector0_rddata_status <= 64'd0;
+ litedramcore_phaseinjector0_rddata_re <= 1'd0;
+ litedramcore_phaseinjector1_command_storage <= 6'd0;
+ litedramcore_phaseinjector1_command_re <= 1'd0;
+ litedramcore_phaseinjector1_address_re <= 1'd0;
+ litedramcore_phaseinjector1_baddress_re <= 1'd0;
+ litedramcore_phaseinjector1_wrdata_re <= 1'd0;
+ litedramcore_phaseinjector1_rddata_status <= 64'd0;
+ litedramcore_phaseinjector1_rddata_re <= 1'd0;
+ litedramcore_dfi_p0_address <= 15'd0;
+ litedramcore_dfi_p0_bank <= 3'd0;
+ litedramcore_dfi_p0_cas_n <= 1'd1;
+ litedramcore_dfi_p0_cs_n <= 1'd1;
+ litedramcore_dfi_p0_ras_n <= 1'd1;
+ litedramcore_dfi_p0_we_n <= 1'd1;
+ litedramcore_dfi_p0_wrdata_en <= 1'd0;
+ litedramcore_dfi_p0_rddata_en <= 1'd0;
+ litedramcore_dfi_p1_address <= 15'd0;
+ litedramcore_dfi_p1_bank <= 3'd0;
+ litedramcore_dfi_p1_cas_n <= 1'd1;
+ litedramcore_dfi_p1_cs_n <= 1'd1;
+ litedramcore_dfi_p1_ras_n <= 1'd1;
+ litedramcore_dfi_p1_we_n <= 1'd1;
+ litedramcore_dfi_p1_wrdata_en <= 1'd0;
+ litedramcore_dfi_p1_rddata_en <= 1'd0;
+ litedramcore_cmd_payload_a <= 15'd0;
+ litedramcore_cmd_payload_ba <= 3'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd0;
+ litedramcore_cmd_payload_we <= 1'd0;
+ litedramcore_timer_count1 <= 9'd374;
+ litedramcore_postponer_req_o <= 1'd0;
+ litedramcore_postponer_count <= 1'd0;
+ litedramcore_sequencer_done1 <= 1'd0;
+ litedramcore_sequencer_counter <= 7'd0;
+ litedramcore_sequencer_count <= 1'd0;
+ litedramcore_zqcs_timer_count1 <= 26'd47999999;
+ litedramcore_zqcs_executer_done <= 1'd0;
+ litedramcore_zqcs_executer_counter <= 6'd0;
+ litedramcore_bankmachine0_level <= 5'd0;
+ litedramcore_bankmachine0_produce <= 4'd0;
+ litedramcore_bankmachine0_consume <= 4'd0;
+ litedramcore_bankmachine0_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine0_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine0_pipe_valid_source_payload_addr <= 22'd0;
+ litedramcore_bankmachine0_row <= 15'd0;
+ litedramcore_bankmachine0_row_opened <= 1'd0;
+ litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine0_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine0_trccon_ready <= 1'd0;
+ litedramcore_bankmachine0_trccon_count <= 2'd0;
+ litedramcore_bankmachine0_trascon_ready <= 1'd0;
+ litedramcore_bankmachine0_trascon_count <= 2'd0;
+ litedramcore_bankmachine1_level <= 5'd0;
+ litedramcore_bankmachine1_produce <= 4'd0;
+ litedramcore_bankmachine1_consume <= 4'd0;
+ litedramcore_bankmachine1_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine1_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine1_pipe_valid_source_payload_addr <= 22'd0;
+ litedramcore_bankmachine1_row <= 15'd0;
+ litedramcore_bankmachine1_row_opened <= 1'd0;
+ litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine1_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine1_trccon_ready <= 1'd0;
+ litedramcore_bankmachine1_trccon_count <= 2'd0;
+ litedramcore_bankmachine1_trascon_ready <= 1'd0;
+ litedramcore_bankmachine1_trascon_count <= 2'd0;
+ litedramcore_bankmachine2_level <= 5'd0;
+ litedramcore_bankmachine2_produce <= 4'd0;
+ litedramcore_bankmachine2_consume <= 4'd0;
+ litedramcore_bankmachine2_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine2_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine2_pipe_valid_source_payload_addr <= 22'd0;
+ litedramcore_bankmachine2_row <= 15'd0;
+ litedramcore_bankmachine2_row_opened <= 1'd0;
+ litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine2_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine2_trccon_ready <= 1'd0;
+ litedramcore_bankmachine2_trccon_count <= 2'd0;
+ litedramcore_bankmachine2_trascon_ready <= 1'd0;
+ litedramcore_bankmachine2_trascon_count <= 2'd0;
+ litedramcore_bankmachine3_level <= 5'd0;
+ litedramcore_bankmachine3_produce <= 4'd0;
+ litedramcore_bankmachine3_consume <= 4'd0;
+ litedramcore_bankmachine3_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine3_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine3_pipe_valid_source_payload_addr <= 22'd0;
+ litedramcore_bankmachine3_row <= 15'd0;
+ litedramcore_bankmachine3_row_opened <= 1'd0;
+ litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine3_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine3_trccon_ready <= 1'd0;
+ litedramcore_bankmachine3_trccon_count <= 2'd0;
+ litedramcore_bankmachine3_trascon_ready <= 1'd0;
+ litedramcore_bankmachine3_trascon_count <= 2'd0;
+ litedramcore_bankmachine4_level <= 5'd0;
+ litedramcore_bankmachine4_produce <= 4'd0;
+ litedramcore_bankmachine4_consume <= 4'd0;
+ litedramcore_bankmachine4_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine4_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine4_pipe_valid_source_payload_addr <= 22'd0;
+ litedramcore_bankmachine4_row <= 15'd0;
+ litedramcore_bankmachine4_row_opened <= 1'd0;
+ litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine4_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine4_trccon_ready <= 1'd0;
+ litedramcore_bankmachine4_trccon_count <= 2'd0;
+ litedramcore_bankmachine4_trascon_ready <= 1'd0;
+ litedramcore_bankmachine4_trascon_count <= 2'd0;
+ litedramcore_bankmachine5_level <= 5'd0;
+ litedramcore_bankmachine5_produce <= 4'd0;
+ litedramcore_bankmachine5_consume <= 4'd0;
+ litedramcore_bankmachine5_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine5_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine5_pipe_valid_source_payload_addr <= 22'd0;
+ litedramcore_bankmachine5_row <= 15'd0;
+ litedramcore_bankmachine5_row_opened <= 1'd0;
+ litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine5_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine5_trccon_ready <= 1'd0;
+ litedramcore_bankmachine5_trccon_count <= 2'd0;
+ litedramcore_bankmachine5_trascon_ready <= 1'd0;
+ litedramcore_bankmachine5_trascon_count <= 2'd0;
+ litedramcore_bankmachine6_level <= 5'd0;
+ litedramcore_bankmachine6_produce <= 4'd0;
+ litedramcore_bankmachine6_consume <= 4'd0;
+ litedramcore_bankmachine6_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine6_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine6_pipe_valid_source_payload_addr <= 22'd0;
+ litedramcore_bankmachine6_row <= 15'd0;
+ litedramcore_bankmachine6_row_opened <= 1'd0;
+ litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine6_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine6_trccon_ready <= 1'd0;
+ litedramcore_bankmachine6_trccon_count <= 2'd0;
+ litedramcore_bankmachine6_trascon_ready <= 1'd0;
+ litedramcore_bankmachine6_trascon_count <= 2'd0;
+ litedramcore_bankmachine7_level <= 5'd0;
+ litedramcore_bankmachine7_produce <= 4'd0;
+ litedramcore_bankmachine7_consume <= 4'd0;
+ litedramcore_bankmachine7_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine7_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine7_pipe_valid_source_payload_addr <= 22'd0;
+ litedramcore_bankmachine7_row <= 15'd0;
+ litedramcore_bankmachine7_row_opened <= 1'd0;
+ litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine7_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine7_trccon_ready <= 1'd0;
+ litedramcore_bankmachine7_trccon_count <= 2'd0;
+ litedramcore_bankmachine7_trascon_ready <= 1'd0;
+ litedramcore_bankmachine7_trascon_count <= 2'd0;
+ litedramcore_choose_cmd_grant <= 3'd0;
+ litedramcore_choose_req_grant <= 3'd0;
+ litedramcore_trrdcon_ready <= 1'd0;
+ litedramcore_trrdcon_count <= 1'd0;
+ litedramcore_tfawcon_ready <= 1'd1;
+ litedramcore_tfawcon_window <= 3'd0;
+ litedramcore_tccdcon_ready <= 1'd0;
+ litedramcore_tccdcon_count <= 1'd0;
+ litedramcore_twtrcon_ready <= 1'd0;
+ litedramcore_twtrcon_count <= 3'd0;
+ litedramcore_time0 <= 5'd0;
+ litedramcore_time1 <= 4'd0;
+ init_done_storage <= 1'd0;
+ init_done_re <= 1'd0;
+ init_error_storage <= 1'd0;
+ init_error_re <= 1'd0;
+ litedramcore_we <= 1'd0;
+ litedramcore_litedramcore_refresher_state <= 2'd0;
+ litedramcore_litedramcore_bankmachine0_state <= 3'd0;
+ litedramcore_litedramcore_bankmachine1_state <= 3'd0;
+ litedramcore_litedramcore_bankmachine2_state <= 3'd0;
+ litedramcore_litedramcore_bankmachine3_state <= 3'd0;
+ litedramcore_litedramcore_bankmachine4_state <= 3'd0;
+ litedramcore_litedramcore_bankmachine5_state <= 3'd0;
+ litedramcore_litedramcore_bankmachine6_state <= 3'd0;
+ litedramcore_litedramcore_bankmachine7_state <= 3'd0;
+ litedramcore_litedramcore_multiplexer_state <= 4'd0;
+ litedramcore_litedramcore_new_master_wdata_ready0 <= 1'd0;
+ litedramcore_litedramcore_new_master_wdata_ready1 <= 1'd0;
+ litedramcore_litedramcore_new_master_wdata_ready2 <= 1'd0;
+ litedramcore_litedramcore_new_master_wdata_ready3 <= 1'd0;
+ litedramcore_litedramcore_new_master_rdata_valid0 <= 1'd0;
+ litedramcore_litedramcore_new_master_rdata_valid1 <= 1'd0;
+ litedramcore_litedramcore_new_master_rdata_valid2 <= 1'd0;
+ litedramcore_litedramcore_new_master_rdata_valid3 <= 1'd0;
+ litedramcore_litedramcore_new_master_rdata_valid4 <= 1'd0;
+ litedramcore_litedramcore_new_master_rdata_valid5 <= 1'd0;
+ litedramcore_litedramcore_new_master_rdata_valid6 <= 1'd0;
+ litedramcore_litedramcore_new_master_rdata_valid7 <= 1'd0;
+ litedramcore_litedramcore_new_master_rdata_valid8 <= 1'd0;
+ litedramcore_litedramcore_new_master_rdata_valid9 <= 1'd0;
+ litedramcore_litedramcore_new_master_rdata_valid10 <= 1'd0;
+ litedramcore_litedramcore_new_master_rdata_valid11 <= 1'd0;
+ litedramcore_litedramcore_new_master_rdata_valid12 <= 1'd0;
+ litedramcore_litedramcore_new_master_rdata_valid13 <= 1'd0;
+ litedramcore_state <= 2'd0;
+ end
end
reg [24:0] storage[0:15];
reg [24:0] storage_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we)
- storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
- storage_dat0 <= storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine0_wrport_we)
+ storage[litedramcore_bankmachine0_wrport_adr] <= litedramcore_bankmachine0_wrport_dat_w;
+ storage_dat0 <= storage[litedramcore_bankmachine0_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = storage_dat0;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine0_wrport_dat_r = storage_dat0;
+assign litedramcore_bankmachine0_rdport_dat_r = storage[litedramcore_bankmachine0_rdport_adr];
//------------------------------------------------------------------------------
reg [24:0] storage_1[0:15];
reg [24:0] storage_1_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we)
- storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
- storage_1_dat0 <= storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine1_wrport_we)
+ storage_1[litedramcore_bankmachine1_wrport_adr] <= litedramcore_bankmachine1_wrport_dat_w;
+ storage_1_dat0 <= storage_1[litedramcore_bankmachine1_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = storage_1_dat0;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine1_wrport_dat_r = storage_1_dat0;
+assign litedramcore_bankmachine1_rdport_dat_r = storage_1[litedramcore_bankmachine1_rdport_adr];
//------------------------------------------------------------------------------
reg [24:0] storage_2[0:15];
reg [24:0] storage_2_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we)
- storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
- storage_2_dat0 <= storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine2_wrport_we)
+ storage_2[litedramcore_bankmachine2_wrport_adr] <= litedramcore_bankmachine2_wrport_dat_w;
+ storage_2_dat0 <= storage_2[litedramcore_bankmachine2_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = storage_2_dat0;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine2_wrport_dat_r = storage_2_dat0;
+assign litedramcore_bankmachine2_rdport_dat_r = storage_2[litedramcore_bankmachine2_rdport_adr];
//------------------------------------------------------------------------------
reg [24:0] storage_3[0:15];
reg [24:0] storage_3_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we)
- storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
- storage_3_dat0 <= storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine3_wrport_we)
+ storage_3[litedramcore_bankmachine3_wrport_adr] <= litedramcore_bankmachine3_wrport_dat_w;
+ storage_3_dat0 <= storage_3[litedramcore_bankmachine3_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = storage_3_dat0;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine3_wrport_dat_r = storage_3_dat0;
+assign litedramcore_bankmachine3_rdport_dat_r = storage_3[litedramcore_bankmachine3_rdport_adr];
//------------------------------------------------------------------------------
reg [24:0] storage_4[0:15];
reg [24:0] storage_4_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we)
- storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
- storage_4_dat0 <= storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine4_wrport_we)
+ storage_4[litedramcore_bankmachine4_wrport_adr] <= litedramcore_bankmachine4_wrport_dat_w;
+ storage_4_dat0 <= storage_4[litedramcore_bankmachine4_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = storage_4_dat0;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine4_wrport_dat_r = storage_4_dat0;
+assign litedramcore_bankmachine4_rdport_dat_r = storage_4[litedramcore_bankmachine4_rdport_adr];
//------------------------------------------------------------------------------
reg [24:0] storage_5[0:15];
reg [24:0] storage_5_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we)
- storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
- storage_5_dat0 <= storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine5_wrport_we)
+ storage_5[litedramcore_bankmachine5_wrport_adr] <= litedramcore_bankmachine5_wrport_dat_w;
+ storage_5_dat0 <= storage_5[litedramcore_bankmachine5_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = storage_5_dat0;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine5_wrport_dat_r = storage_5_dat0;
+assign litedramcore_bankmachine5_rdport_dat_r = storage_5[litedramcore_bankmachine5_rdport_adr];
//------------------------------------------------------------------------------
reg [24:0] storage_6[0:15];
reg [24:0] storage_6_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we)
- storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
- storage_6_dat0 <= storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine6_wrport_we)
+ storage_6[litedramcore_bankmachine6_wrport_adr] <= litedramcore_bankmachine6_wrport_dat_w;
+ storage_6_dat0 <= storage_6[litedramcore_bankmachine6_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = storage_6_dat0;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine6_wrport_dat_r = storage_6_dat0;
+assign litedramcore_bankmachine6_rdport_dat_r = storage_6[litedramcore_bankmachine6_rdport_adr];
//------------------------------------------------------------------------------
reg [24:0] storage_7[0:15];
reg [24:0] storage_7_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we)
- storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
- storage_7_dat0 <= storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine7_wrport_we)
+ storage_7[litedramcore_bankmachine7_wrport_adr] <= litedramcore_bankmachine7_wrport_dat_w;
+ storage_7_dat0 <= storage_7[litedramcore_bankmachine7_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = storage_7_dat0;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine7_wrport_dat_r = storage_7_dat0;
+assign litedramcore_bankmachine7_rdport_dat_r = storage_7[litedramcore_bankmachine7_rdport_adr];
-(* FREQUENCY_PIN_CLKI = "48.0", FREQUENCY_PIN_CLKOP = "96.0", FREQUENCY_PIN_CLKOS = "24.0", ICP_CURRENT = "6", LPF_RESISTOR = "16", MFG_ENABLE_FILTEROPAMP = "1", MFG_GMCREF_SEL = "2" *) EHXPLLL #(
+(* FREQUENCY_PIN_CLKI = "48.0", FREQUENCY_PIN_CLKOP = "96.0", FREQUENCY_PIN_CLKOS = "24.0", ICP_CURRENT = "6", LPF_RESISTOR = "16", MFG_ENABLE_FILTEROPAMP = "1", MFG_GMCREF_SEL = "2" *)
+EHXPLLL #(
.CLKFB_DIV(4'd10),
.CLKI_DIV(1'd1),
.CLKOP_CPHASE(3'd4),
endmodule
// -----------------------------------------------------------------------------
-// Auto-Generated by LiteX on 2022-08-04 21:07:03.
+// Auto-Generated by LiteX on 2022-10-28 19:01:26.
//------------------------------------------------------------------------------
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//
// Filename : litedram_core.v
// Device :
-// LiteX sha1 : 6932fc51
-// Date : 2022-08-04 21:07:04
+// LiteX sha1 : --------
+// Date : 2022-10-28 19:01:27
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
module litedram_core (
- input wire sim_trace,
- input wire clk,
- output wire init_done,
- output wire init_error,
- input wire [29:0] wb_ctrl_adr,
- input wire [31:0] wb_ctrl_dat_w,
- output wire [31:0] wb_ctrl_dat_r,
- input wire [3:0] wb_ctrl_sel,
- input wire wb_ctrl_cyc,
- input wire wb_ctrl_stb,
- output wire wb_ctrl_ack,
- input wire wb_ctrl_we,
- input wire [2:0] wb_ctrl_cti,
- input wire [1:0] wb_ctrl_bte,
- output wire wb_ctrl_err,
- output wire user_clk,
- output wire user_rst,
- input wire user_port_native_0_cmd_valid,
- output wire user_port_native_0_cmd_ready,
- input wire user_port_native_0_cmd_we,
- input wire [23:0] user_port_native_0_cmd_addr,
- input wire user_port_native_0_wdata_valid,
- output wire user_port_native_0_wdata_ready,
- input wire [15:0] user_port_native_0_wdata_we,
- input wire [127:0] user_port_native_0_wdata_data,
- output wire user_port_native_0_rdata_valid,
- input wire user_port_native_0_rdata_ready,
- output wire [127:0] user_port_native_0_rdata_data
+ input wire sim_trace,
+ input wire clk,
+ output wire init_done,
+ output wire init_error,
+ input wire [29:0] wb_ctrl_adr,
+ input wire [31:0] wb_ctrl_dat_w,
+ output wire [31:0] wb_ctrl_dat_r,
+ input wire [3:0] wb_ctrl_sel,
+ input wire wb_ctrl_cyc,
+ input wire wb_ctrl_stb,
+ output wire wb_ctrl_ack,
+ input wire wb_ctrl_we,
+ input wire [2:0] wb_ctrl_cti,
+ input wire [1:0] wb_ctrl_bte,
+ output wire wb_ctrl_err,
+ output wire user_clk,
+ output wire user_rst,
+ input wire user_port_native_0_cmd_valid,
+ output wire user_port_native_0_cmd_ready,
+ input wire user_port_native_0_cmd_we,
+ input wire [23:0] user_port_native_0_cmd_addr,
+ input wire user_port_native_0_wdata_valid,
+ output wire user_port_native_0_wdata_ready,
+ input wire [15:0] user_port_native_0_wdata_we,
+ input wire [127:0] user_port_native_0_wdata_data,
+ output wire user_port_native_0_rdata_valid,
+ input wire user_port_native_0_rdata_ready,
+ output wire [127:0] user_port_native_0_rdata_data
);
// Signals
//------------------------------------------------------------------------------
-wire sys_clk;
-wire sys_rst;
-wire por_clk;
-reg soc_int_rst = 1'd1;
-wire [13:0] soc_ddrphy_dfi_p0_address;
-wire [2:0] soc_ddrphy_dfi_p0_bank;
-wire soc_ddrphy_dfi_p0_cas_n;
-wire soc_ddrphy_dfi_p0_cs_n;
-wire soc_ddrphy_dfi_p0_ras_n;
-wire soc_ddrphy_dfi_p0_we_n;
-wire soc_ddrphy_dfi_p0_cke;
-wire soc_ddrphy_dfi_p0_odt;
-wire soc_ddrphy_dfi_p0_reset_n;
-wire soc_ddrphy_dfi_p0_act_n;
-wire [31:0] soc_ddrphy_dfi_p0_wrdata;
-wire soc_ddrphy_dfi_p0_wrdata_en;
-wire [3:0] soc_ddrphy_dfi_p0_wrdata_mask;
-wire soc_ddrphy_dfi_p0_rddata_en;
-wire [31:0] soc_ddrphy_dfi_p0_rddata;
-wire soc_ddrphy_dfi_p0_rddata_valid;
-wire [13:0] soc_ddrphy_dfi_p1_address;
-wire [2:0] soc_ddrphy_dfi_p1_bank;
-wire soc_ddrphy_dfi_p1_cas_n;
-wire soc_ddrphy_dfi_p1_cs_n;
-wire soc_ddrphy_dfi_p1_ras_n;
-wire soc_ddrphy_dfi_p1_we_n;
-wire soc_ddrphy_dfi_p1_cke;
-wire soc_ddrphy_dfi_p1_odt;
-wire soc_ddrphy_dfi_p1_reset_n;
-wire soc_ddrphy_dfi_p1_act_n;
-wire [31:0] soc_ddrphy_dfi_p1_wrdata;
-wire soc_ddrphy_dfi_p1_wrdata_en;
-wire [3:0] soc_ddrphy_dfi_p1_wrdata_mask;
-wire soc_ddrphy_dfi_p1_rddata_en;
-wire [31:0] soc_ddrphy_dfi_p1_rddata;
-wire soc_ddrphy_dfi_p1_rddata_valid;
-wire [13:0] soc_ddrphy_dfi_p2_address;
-wire [2:0] soc_ddrphy_dfi_p2_bank;
-wire soc_ddrphy_dfi_p2_cas_n;
-wire soc_ddrphy_dfi_p2_cs_n;
-wire soc_ddrphy_dfi_p2_ras_n;
-wire soc_ddrphy_dfi_p2_we_n;
-wire soc_ddrphy_dfi_p2_cke;
-wire soc_ddrphy_dfi_p2_odt;
-wire soc_ddrphy_dfi_p2_reset_n;
-wire soc_ddrphy_dfi_p2_act_n;
-wire [31:0] soc_ddrphy_dfi_p2_wrdata;
-wire soc_ddrphy_dfi_p2_wrdata_en;
-wire [3:0] soc_ddrphy_dfi_p2_wrdata_mask;
-wire soc_ddrphy_dfi_p2_rddata_en;
-wire [31:0] soc_ddrphy_dfi_p2_rddata;
-wire soc_ddrphy_dfi_p2_rddata_valid;
-wire [13:0] soc_ddrphy_dfi_p3_address;
-wire [2:0] soc_ddrphy_dfi_p3_bank;
-wire soc_ddrphy_dfi_p3_cas_n;
-wire soc_ddrphy_dfi_p3_cs_n;
-wire soc_ddrphy_dfi_p3_ras_n;
-wire soc_ddrphy_dfi_p3_we_n;
-wire soc_ddrphy_dfi_p3_cke;
-wire soc_ddrphy_dfi_p3_odt;
-wire soc_ddrphy_dfi_p3_reset_n;
-wire soc_ddrphy_dfi_p3_act_n;
-wire [31:0] soc_ddrphy_dfi_p3_wrdata;
-wire soc_ddrphy_dfi_p3_wrdata_en;
-wire [3:0] soc_ddrphy_dfi_p3_wrdata_mask;
-wire soc_ddrphy_dfi_p3_rddata_en;
-wire [31:0] soc_ddrphy_dfi_p3_rddata;
-wire soc_ddrphy_dfi_p3_rddata_valid;
-reg soc_ddrphy_dfiphasemodel0_activate = 1'd0;
-reg soc_ddrphy_dfiphasemodel0_precharge = 1'd0;
-reg soc_ddrphy_dfiphasemodel0_write = 1'd0;
-reg soc_ddrphy_dfiphasemodel0_read = 1'd0;
-reg soc_ddrphy_dfiphasemodel1_activate = 1'd0;
-reg soc_ddrphy_dfiphasemodel1_precharge = 1'd0;
-reg soc_ddrphy_dfiphasemodel1_write = 1'd0;
-reg soc_ddrphy_dfiphasemodel1_read = 1'd0;
-reg soc_ddrphy_dfiphasemodel2_activate = 1'd0;
-reg soc_ddrphy_dfiphasemodel2_precharge = 1'd0;
-reg soc_ddrphy_dfiphasemodel2_write = 1'd0;
-reg soc_ddrphy_dfiphasemodel2_read = 1'd0;
-reg soc_ddrphy_dfiphasemodel3_activate = 1'd0;
-reg soc_ddrphy_dfiphasemodel3_precharge = 1'd0;
-reg soc_ddrphy_dfiphasemodel3_write = 1'd0;
-reg soc_ddrphy_dfiphasemodel3_read = 1'd0;
-reg soc_ddrphy_bankmodel0_activate = 1'd0;
-reg [13:0] soc_ddrphy_bankmodel0_activate_row = 14'd0;
-reg soc_ddrphy_bankmodel0_precharge = 1'd0;
-wire soc_ddrphy_bankmodel0_write;
-wire [9:0] soc_ddrphy_bankmodel0_write_col;
-wire [127:0] soc_ddrphy_bankmodel0_write_data;
-wire [15:0] soc_ddrphy_bankmodel0_write_mask;
-reg soc_ddrphy_bankmodel0_read = 1'd0;
-reg [9:0] soc_ddrphy_bankmodel0_read_col = 10'd0;
-reg [127:0] soc_ddrphy_bankmodel0_read_data = 128'd0;
-reg soc_ddrphy_bankmodel0_active = 1'd0;
-reg [13:0] soc_ddrphy_bankmodel0_row = 14'd0;
-reg [20:0] soc_ddrphy_bankmodel0_write_port_adr = 21'd0;
-wire [127:0] soc_ddrphy_bankmodel0_write_port_dat_r;
-reg [15:0] soc_ddrphy_bankmodel0_write_port_we = 16'd0;
-reg [127:0] soc_ddrphy_bankmodel0_write_port_dat_w = 128'd0;
-reg [20:0] soc_ddrphy_bankmodel0_read_port_adr = 21'd0;
-wire [127:0] soc_ddrphy_bankmodel0_read_port_dat_r;
-wire [20:0] soc_ddrphy_bankmodel0_wraddr;
-wire [20:0] soc_ddrphy_bankmodel0_rdaddr;
-reg soc_ddrphy_bankmodel1_activate = 1'd0;
-reg [13:0] soc_ddrphy_bankmodel1_activate_row = 14'd0;
-reg soc_ddrphy_bankmodel1_precharge = 1'd0;
-wire soc_ddrphy_bankmodel1_write;
-wire [9:0] soc_ddrphy_bankmodel1_write_col;
-wire [127:0] soc_ddrphy_bankmodel1_write_data;
-wire [15:0] soc_ddrphy_bankmodel1_write_mask;
-reg soc_ddrphy_bankmodel1_read = 1'd0;
-reg [9:0] soc_ddrphy_bankmodel1_read_col = 10'd0;
-reg [127:0] soc_ddrphy_bankmodel1_read_data = 128'd0;
-reg soc_ddrphy_bankmodel1_active = 1'd0;
-reg [13:0] soc_ddrphy_bankmodel1_row = 14'd0;
-reg [20:0] soc_ddrphy_bankmodel1_write_port_adr = 21'd0;
-wire [127:0] soc_ddrphy_bankmodel1_write_port_dat_r;
-reg [15:0] soc_ddrphy_bankmodel1_write_port_we = 16'd0;
-reg [127:0] soc_ddrphy_bankmodel1_write_port_dat_w = 128'd0;
-reg [20:0] soc_ddrphy_bankmodel1_read_port_adr = 21'd0;
-wire [127:0] soc_ddrphy_bankmodel1_read_port_dat_r;
-wire [20:0] soc_ddrphy_bankmodel1_wraddr;
-wire [20:0] soc_ddrphy_bankmodel1_rdaddr;
-reg soc_ddrphy_bankmodel2_activate = 1'd0;
-reg [13:0] soc_ddrphy_bankmodel2_activate_row = 14'd0;
-reg soc_ddrphy_bankmodel2_precharge = 1'd0;
-wire soc_ddrphy_bankmodel2_write;
-wire [9:0] soc_ddrphy_bankmodel2_write_col;
-wire [127:0] soc_ddrphy_bankmodel2_write_data;
-wire [15:0] soc_ddrphy_bankmodel2_write_mask;
-reg soc_ddrphy_bankmodel2_read = 1'd0;
-reg [9:0] soc_ddrphy_bankmodel2_read_col = 10'd0;
-reg [127:0] soc_ddrphy_bankmodel2_read_data = 128'd0;
-reg soc_ddrphy_bankmodel2_active = 1'd0;
-reg [13:0] soc_ddrphy_bankmodel2_row = 14'd0;
-reg [20:0] soc_ddrphy_bankmodel2_write_port_adr = 21'd0;
-wire [127:0] soc_ddrphy_bankmodel2_write_port_dat_r;
-reg [15:0] soc_ddrphy_bankmodel2_write_port_we = 16'd0;
-reg [127:0] soc_ddrphy_bankmodel2_write_port_dat_w = 128'd0;
-reg [20:0] soc_ddrphy_bankmodel2_read_port_adr = 21'd0;
-wire [127:0] soc_ddrphy_bankmodel2_read_port_dat_r;
-wire [20:0] soc_ddrphy_bankmodel2_wraddr;
-wire [20:0] soc_ddrphy_bankmodel2_rdaddr;
-reg soc_ddrphy_bankmodel3_activate = 1'd0;
-reg [13:0] soc_ddrphy_bankmodel3_activate_row = 14'd0;
-reg soc_ddrphy_bankmodel3_precharge = 1'd0;
-wire soc_ddrphy_bankmodel3_write;
-wire [9:0] soc_ddrphy_bankmodel3_write_col;
-wire [127:0] soc_ddrphy_bankmodel3_write_data;
-wire [15:0] soc_ddrphy_bankmodel3_write_mask;
-reg soc_ddrphy_bankmodel3_read = 1'd0;
-reg [9:0] soc_ddrphy_bankmodel3_read_col = 10'd0;
-reg [127:0] soc_ddrphy_bankmodel3_read_data = 128'd0;
-reg soc_ddrphy_bankmodel3_active = 1'd0;
-reg [13:0] soc_ddrphy_bankmodel3_row = 14'd0;
-reg [20:0] soc_ddrphy_bankmodel3_write_port_adr = 21'd0;
-wire [127:0] soc_ddrphy_bankmodel3_write_port_dat_r;
-reg [15:0] soc_ddrphy_bankmodel3_write_port_we = 16'd0;
-reg [127:0] soc_ddrphy_bankmodel3_write_port_dat_w = 128'd0;
-reg [20:0] soc_ddrphy_bankmodel3_read_port_adr = 21'd0;
-wire [127:0] soc_ddrphy_bankmodel3_read_port_dat_r;
-wire [20:0] soc_ddrphy_bankmodel3_wraddr;
-wire [20:0] soc_ddrphy_bankmodel3_rdaddr;
-reg soc_ddrphy_bankmodel4_activate = 1'd0;
-reg [13:0] soc_ddrphy_bankmodel4_activate_row = 14'd0;
-reg soc_ddrphy_bankmodel4_precharge = 1'd0;
-wire soc_ddrphy_bankmodel4_write;
-wire [9:0] soc_ddrphy_bankmodel4_write_col;
-wire [127:0] soc_ddrphy_bankmodel4_write_data;
-wire [15:0] soc_ddrphy_bankmodel4_write_mask;
-reg soc_ddrphy_bankmodel4_read = 1'd0;
-reg [9:0] soc_ddrphy_bankmodel4_read_col = 10'd0;
-reg [127:0] soc_ddrphy_bankmodel4_read_data = 128'd0;
-reg soc_ddrphy_bankmodel4_active = 1'd0;
-reg [13:0] soc_ddrphy_bankmodel4_row = 14'd0;
-reg [20:0] soc_ddrphy_bankmodel4_write_port_adr = 21'd0;
-wire [127:0] soc_ddrphy_bankmodel4_write_port_dat_r;
-reg [15:0] soc_ddrphy_bankmodel4_write_port_we = 16'd0;
-reg [127:0] soc_ddrphy_bankmodel4_write_port_dat_w = 128'd0;
-reg [20:0] soc_ddrphy_bankmodel4_read_port_adr = 21'd0;
-wire [127:0] soc_ddrphy_bankmodel4_read_port_dat_r;
-wire [20:0] soc_ddrphy_bankmodel4_wraddr;
-wire [20:0] soc_ddrphy_bankmodel4_rdaddr;
-reg soc_ddrphy_bankmodel5_activate = 1'd0;
-reg [13:0] soc_ddrphy_bankmodel5_activate_row = 14'd0;
-reg soc_ddrphy_bankmodel5_precharge = 1'd0;
-wire soc_ddrphy_bankmodel5_write;
-wire [9:0] soc_ddrphy_bankmodel5_write_col;
-wire [127:0] soc_ddrphy_bankmodel5_write_data;
-wire [15:0] soc_ddrphy_bankmodel5_write_mask;
-reg soc_ddrphy_bankmodel5_read = 1'd0;
-reg [9:0] soc_ddrphy_bankmodel5_read_col = 10'd0;
-reg [127:0] soc_ddrphy_bankmodel5_read_data = 128'd0;
-reg soc_ddrphy_bankmodel5_active = 1'd0;
-reg [13:0] soc_ddrphy_bankmodel5_row = 14'd0;
-reg [20:0] soc_ddrphy_bankmodel5_write_port_adr = 21'd0;
-wire [127:0] soc_ddrphy_bankmodel5_write_port_dat_r;
-reg [15:0] soc_ddrphy_bankmodel5_write_port_we = 16'd0;
-reg [127:0] soc_ddrphy_bankmodel5_write_port_dat_w = 128'd0;
-reg [20:0] soc_ddrphy_bankmodel5_read_port_adr = 21'd0;
-wire [127:0] soc_ddrphy_bankmodel5_read_port_dat_r;
-wire [20:0] soc_ddrphy_bankmodel5_wraddr;
-wire [20:0] soc_ddrphy_bankmodel5_rdaddr;
-reg soc_ddrphy_bankmodel6_activate = 1'd0;
-reg [13:0] soc_ddrphy_bankmodel6_activate_row = 14'd0;
-reg soc_ddrphy_bankmodel6_precharge = 1'd0;
-wire soc_ddrphy_bankmodel6_write;
-wire [9:0] soc_ddrphy_bankmodel6_write_col;
-wire [127:0] soc_ddrphy_bankmodel6_write_data;
-wire [15:0] soc_ddrphy_bankmodel6_write_mask;
-reg soc_ddrphy_bankmodel6_read = 1'd0;
-reg [9:0] soc_ddrphy_bankmodel6_read_col = 10'd0;
-reg [127:0] soc_ddrphy_bankmodel6_read_data = 128'd0;
-reg soc_ddrphy_bankmodel6_active = 1'd0;
-reg [13:0] soc_ddrphy_bankmodel6_row = 14'd0;
-reg [20:0] soc_ddrphy_bankmodel6_write_port_adr = 21'd0;
-wire [127:0] soc_ddrphy_bankmodel6_write_port_dat_r;
-reg [15:0] soc_ddrphy_bankmodel6_write_port_we = 16'd0;
-reg [127:0] soc_ddrphy_bankmodel6_write_port_dat_w = 128'd0;
-reg [20:0] soc_ddrphy_bankmodel6_read_port_adr = 21'd0;
-wire [127:0] soc_ddrphy_bankmodel6_read_port_dat_r;
-wire [20:0] soc_ddrphy_bankmodel6_wraddr;
-wire [20:0] soc_ddrphy_bankmodel6_rdaddr;
-reg soc_ddrphy_bankmodel7_activate = 1'd0;
-reg [13:0] soc_ddrphy_bankmodel7_activate_row = 14'd0;
-reg soc_ddrphy_bankmodel7_precharge = 1'd0;
-wire soc_ddrphy_bankmodel7_write;
-wire [9:0] soc_ddrphy_bankmodel7_write_col;
-wire [127:0] soc_ddrphy_bankmodel7_write_data;
-wire [15:0] soc_ddrphy_bankmodel7_write_mask;
-reg soc_ddrphy_bankmodel7_read = 1'd0;
-reg [9:0] soc_ddrphy_bankmodel7_read_col = 10'd0;
-reg [127:0] soc_ddrphy_bankmodel7_read_data = 128'd0;
-reg soc_ddrphy_bankmodel7_active = 1'd0;
-reg [13:0] soc_ddrphy_bankmodel7_row = 14'd0;
-reg [20:0] soc_ddrphy_bankmodel7_write_port_adr = 21'd0;
-wire [127:0] soc_ddrphy_bankmodel7_write_port_dat_r;
-reg [15:0] soc_ddrphy_bankmodel7_write_port_we = 16'd0;
-reg [127:0] soc_ddrphy_bankmodel7_write_port_dat_w = 128'd0;
-reg [20:0] soc_ddrphy_bankmodel7_read_port_adr = 21'd0;
-wire [127:0] soc_ddrphy_bankmodel7_read_port_dat_r;
-wire [20:0] soc_ddrphy_bankmodel7_wraddr;
-wire [20:0] soc_ddrphy_bankmodel7_rdaddr;
-reg [3:0] soc_ddrphy_activates0 = 4'd0;
-reg [3:0] soc_ddrphy_precharges0 = 4'd0;
-reg soc_ddrphy_bank_write0 = 1'd0;
-reg [9:0] soc_ddrphy_bank_write_col0 = 10'd0;
-reg [3:0] soc_ddrphy_writes0 = 4'd0;
-reg soc_ddrphy_new_bank_write0 = 1'd0;
-reg [9:0] soc_ddrphy_new_bank_write_col0 = 10'd0;
-reg [3:0] soc_ddrphy_reads0 = 4'd0;
-reg [3:0] soc_ddrphy_activates1 = 4'd0;
-reg [3:0] soc_ddrphy_precharges1 = 4'd0;
-reg soc_ddrphy_bank_write1 = 1'd0;
-reg [9:0] soc_ddrphy_bank_write_col1 = 10'd0;
-reg [3:0] soc_ddrphy_writes1 = 4'd0;
-reg soc_ddrphy_new_bank_write1 = 1'd0;
-reg [9:0] soc_ddrphy_new_bank_write_col1 = 10'd0;
-reg [3:0] soc_ddrphy_reads1 = 4'd0;
-reg [3:0] soc_ddrphy_activates2 = 4'd0;
-reg [3:0] soc_ddrphy_precharges2 = 4'd0;
-reg soc_ddrphy_bank_write2 = 1'd0;
-reg [9:0] soc_ddrphy_bank_write_col2 = 10'd0;
-reg [3:0] soc_ddrphy_writes2 = 4'd0;
-reg soc_ddrphy_new_bank_write2 = 1'd0;
-reg [9:0] soc_ddrphy_new_bank_write_col2 = 10'd0;
-reg [3:0] soc_ddrphy_reads2 = 4'd0;
-reg [3:0] soc_ddrphy_activates3 = 4'd0;
-reg [3:0] soc_ddrphy_precharges3 = 4'd0;
-reg soc_ddrphy_bank_write3 = 1'd0;
-reg [9:0] soc_ddrphy_bank_write_col3 = 10'd0;
-reg [3:0] soc_ddrphy_writes3 = 4'd0;
-reg soc_ddrphy_new_bank_write3 = 1'd0;
-reg [9:0] soc_ddrphy_new_bank_write_col3 = 10'd0;
-reg [3:0] soc_ddrphy_reads3 = 4'd0;
-reg [3:0] soc_ddrphy_activates4 = 4'd0;
-reg [3:0] soc_ddrphy_precharges4 = 4'd0;
-reg soc_ddrphy_bank_write4 = 1'd0;
-reg [9:0] soc_ddrphy_bank_write_col4 = 10'd0;
-reg [3:0] soc_ddrphy_writes4 = 4'd0;
-reg soc_ddrphy_new_bank_write4 = 1'd0;
-reg [9:0] soc_ddrphy_new_bank_write_col4 = 10'd0;
-reg [3:0] soc_ddrphy_reads4 = 4'd0;
-reg [3:0] soc_ddrphy_activates5 = 4'd0;
-reg [3:0] soc_ddrphy_precharges5 = 4'd0;
-reg soc_ddrphy_bank_write5 = 1'd0;
-reg [9:0] soc_ddrphy_bank_write_col5 = 10'd0;
-reg [3:0] soc_ddrphy_writes5 = 4'd0;
-reg soc_ddrphy_new_bank_write5 = 1'd0;
-reg [9:0] soc_ddrphy_new_bank_write_col5 = 10'd0;
-reg [3:0] soc_ddrphy_reads5 = 4'd0;
-reg [3:0] soc_ddrphy_activates6 = 4'd0;
-reg [3:0] soc_ddrphy_precharges6 = 4'd0;
-reg soc_ddrphy_bank_write6 = 1'd0;
-reg [9:0] soc_ddrphy_bank_write_col6 = 10'd0;
-reg [3:0] soc_ddrphy_writes6 = 4'd0;
-reg soc_ddrphy_new_bank_write6 = 1'd0;
-reg [9:0] soc_ddrphy_new_bank_write_col6 = 10'd0;
-reg [3:0] soc_ddrphy_reads6 = 4'd0;
-reg [3:0] soc_ddrphy_activates7 = 4'd0;
-reg [3:0] soc_ddrphy_precharges7 = 4'd0;
-reg soc_ddrphy_bank_write7 = 1'd0;
-reg [9:0] soc_ddrphy_bank_write_col7 = 10'd0;
-reg [3:0] soc_ddrphy_writes7 = 4'd0;
-reg soc_ddrphy_new_bank_write7 = 1'd0;
-reg [9:0] soc_ddrphy_new_bank_write_col7 = 10'd0;
-reg [3:0] soc_ddrphy_reads7 = 4'd0;
-wire soc_ddrphy_banks_read;
-wire [127:0] soc_ddrphy_banks_read_data;
-reg soc_ddrphy_new_banks_read0 = 1'd0;
-reg [127:0] soc_ddrphy_new_banks_read_data0 = 128'd0;
-reg soc_ddrphy_new_banks_read1 = 1'd0;
-reg [127:0] soc_ddrphy_new_banks_read_data1 = 128'd0;
-reg soc_ddrphy_new_banks_read2 = 1'd0;
-reg [127:0] soc_ddrphy_new_banks_read_data2 = 128'd0;
-reg soc_ddrphy_new_banks_read3 = 1'd0;
-reg [127:0] soc_ddrphy_new_banks_read_data3 = 128'd0;
-reg soc_ddrphy_new_banks_read4 = 1'd0;
-reg [127:0] soc_ddrphy_new_banks_read_data4 = 128'd0;
-reg soc_ddrphy_new_banks_read5 = 1'd0;
-reg [127:0] soc_ddrphy_new_banks_read_data5 = 128'd0;
-reg soc_ddrphy_new_banks_read6 = 1'd0;
-reg [127:0] soc_ddrphy_new_banks_read_data6 = 128'd0;
-reg soc_ddrphy_new_banks_read7 = 1'd0;
-reg [127:0] soc_ddrphy_new_banks_read_data7 = 128'd0;
-wire [13:0] soc_litedramcore_slave_p0_address;
-wire [2:0] soc_litedramcore_slave_p0_bank;
-wire soc_litedramcore_slave_p0_cas_n;
-wire soc_litedramcore_slave_p0_cs_n;
-wire soc_litedramcore_slave_p0_ras_n;
-wire soc_litedramcore_slave_p0_we_n;
-wire soc_litedramcore_slave_p0_cke;
-wire soc_litedramcore_slave_p0_odt;
-wire soc_litedramcore_slave_p0_reset_n;
-wire soc_litedramcore_slave_p0_act_n;
-wire [31:0] soc_litedramcore_slave_p0_wrdata;
-wire soc_litedramcore_slave_p0_wrdata_en;
-wire [3:0] soc_litedramcore_slave_p0_wrdata_mask;
-wire soc_litedramcore_slave_p0_rddata_en;
-reg [31:0] soc_litedramcore_slave_p0_rddata = 32'd0;
-reg soc_litedramcore_slave_p0_rddata_valid = 1'd0;
-wire [13:0] soc_litedramcore_slave_p1_address;
-wire [2:0] soc_litedramcore_slave_p1_bank;
-wire soc_litedramcore_slave_p1_cas_n;
-wire soc_litedramcore_slave_p1_cs_n;
-wire soc_litedramcore_slave_p1_ras_n;
-wire soc_litedramcore_slave_p1_we_n;
-wire soc_litedramcore_slave_p1_cke;
-wire soc_litedramcore_slave_p1_odt;
-wire soc_litedramcore_slave_p1_reset_n;
-wire soc_litedramcore_slave_p1_act_n;
-wire [31:0] soc_litedramcore_slave_p1_wrdata;
-wire soc_litedramcore_slave_p1_wrdata_en;
-wire [3:0] soc_litedramcore_slave_p1_wrdata_mask;
-wire soc_litedramcore_slave_p1_rddata_en;
-reg [31:0] soc_litedramcore_slave_p1_rddata = 32'd0;
-reg soc_litedramcore_slave_p1_rddata_valid = 1'd0;
-wire [13:0] soc_litedramcore_slave_p2_address;
-wire [2:0] soc_litedramcore_slave_p2_bank;
-wire soc_litedramcore_slave_p2_cas_n;
-wire soc_litedramcore_slave_p2_cs_n;
-wire soc_litedramcore_slave_p2_ras_n;
-wire soc_litedramcore_slave_p2_we_n;
-wire soc_litedramcore_slave_p2_cke;
-wire soc_litedramcore_slave_p2_odt;
-wire soc_litedramcore_slave_p2_reset_n;
-wire soc_litedramcore_slave_p2_act_n;
-wire [31:0] soc_litedramcore_slave_p2_wrdata;
-wire soc_litedramcore_slave_p2_wrdata_en;
-wire [3:0] soc_litedramcore_slave_p2_wrdata_mask;
-wire soc_litedramcore_slave_p2_rddata_en;
-reg [31:0] soc_litedramcore_slave_p2_rddata = 32'd0;
-reg soc_litedramcore_slave_p2_rddata_valid = 1'd0;
-wire [13:0] soc_litedramcore_slave_p3_address;
-wire [2:0] soc_litedramcore_slave_p3_bank;
-wire soc_litedramcore_slave_p3_cas_n;
-wire soc_litedramcore_slave_p3_cs_n;
-wire soc_litedramcore_slave_p3_ras_n;
-wire soc_litedramcore_slave_p3_we_n;
-wire soc_litedramcore_slave_p3_cke;
-wire soc_litedramcore_slave_p3_odt;
-wire soc_litedramcore_slave_p3_reset_n;
-wire soc_litedramcore_slave_p3_act_n;
-wire [31:0] soc_litedramcore_slave_p3_wrdata;
-wire soc_litedramcore_slave_p3_wrdata_en;
-wire [3:0] soc_litedramcore_slave_p3_wrdata_mask;
-wire soc_litedramcore_slave_p3_rddata_en;
-reg [31:0] soc_litedramcore_slave_p3_rddata = 32'd0;
-reg soc_litedramcore_slave_p3_rddata_valid = 1'd0;
-reg [13:0] soc_litedramcore_master_p0_address = 14'd0;
-reg [2:0] soc_litedramcore_master_p0_bank = 3'd0;
-reg soc_litedramcore_master_p0_cas_n = 1'd1;
-reg soc_litedramcore_master_p0_cs_n = 1'd1;
-reg soc_litedramcore_master_p0_ras_n = 1'd1;
-reg soc_litedramcore_master_p0_we_n = 1'd1;
-reg soc_litedramcore_master_p0_cke = 1'd0;
-reg soc_litedramcore_master_p0_odt = 1'd0;
-reg soc_litedramcore_master_p0_reset_n = 1'd0;
-reg soc_litedramcore_master_p0_act_n = 1'd1;
-reg [31:0] soc_litedramcore_master_p0_wrdata = 32'd0;
-reg soc_litedramcore_master_p0_wrdata_en = 1'd0;
-reg [3:0] soc_litedramcore_master_p0_wrdata_mask = 4'd0;
-reg soc_litedramcore_master_p0_rddata_en = 1'd0;
-wire [31:0] soc_litedramcore_master_p0_rddata;
-wire soc_litedramcore_master_p0_rddata_valid;
-reg [13:0] soc_litedramcore_master_p1_address = 14'd0;
-reg [2:0] soc_litedramcore_master_p1_bank = 3'd0;
-reg soc_litedramcore_master_p1_cas_n = 1'd1;
-reg soc_litedramcore_master_p1_cs_n = 1'd1;
-reg soc_litedramcore_master_p1_ras_n = 1'd1;
-reg soc_litedramcore_master_p1_we_n = 1'd1;
-reg soc_litedramcore_master_p1_cke = 1'd0;
-reg soc_litedramcore_master_p1_odt = 1'd0;
-reg soc_litedramcore_master_p1_reset_n = 1'd0;
-reg soc_litedramcore_master_p1_act_n = 1'd1;
-reg [31:0] soc_litedramcore_master_p1_wrdata = 32'd0;
-reg soc_litedramcore_master_p1_wrdata_en = 1'd0;
-reg [3:0] soc_litedramcore_master_p1_wrdata_mask = 4'd0;
-reg soc_litedramcore_master_p1_rddata_en = 1'd0;
-wire [31:0] soc_litedramcore_master_p1_rddata;
-wire soc_litedramcore_master_p1_rddata_valid;
-reg [13:0] soc_litedramcore_master_p2_address = 14'd0;
-reg [2:0] soc_litedramcore_master_p2_bank = 3'd0;
-reg soc_litedramcore_master_p2_cas_n = 1'd1;
-reg soc_litedramcore_master_p2_cs_n = 1'd1;
-reg soc_litedramcore_master_p2_ras_n = 1'd1;
-reg soc_litedramcore_master_p2_we_n = 1'd1;
-reg soc_litedramcore_master_p2_cke = 1'd0;
-reg soc_litedramcore_master_p2_odt = 1'd0;
-reg soc_litedramcore_master_p2_reset_n = 1'd0;
-reg soc_litedramcore_master_p2_act_n = 1'd1;
-reg [31:0] soc_litedramcore_master_p2_wrdata = 32'd0;
-reg soc_litedramcore_master_p2_wrdata_en = 1'd0;
-reg [3:0] soc_litedramcore_master_p2_wrdata_mask = 4'd0;
-reg soc_litedramcore_master_p2_rddata_en = 1'd0;
-wire [31:0] soc_litedramcore_master_p2_rddata;
-wire soc_litedramcore_master_p2_rddata_valid;
-reg [13:0] soc_litedramcore_master_p3_address = 14'd0;
-reg [2:0] soc_litedramcore_master_p3_bank = 3'd0;
-reg soc_litedramcore_master_p3_cas_n = 1'd1;
-reg soc_litedramcore_master_p3_cs_n = 1'd1;
-reg soc_litedramcore_master_p3_ras_n = 1'd1;
-reg soc_litedramcore_master_p3_we_n = 1'd1;
-reg soc_litedramcore_master_p3_cke = 1'd0;
-reg soc_litedramcore_master_p3_odt = 1'd0;
-reg soc_litedramcore_master_p3_reset_n = 1'd0;
-reg soc_litedramcore_master_p3_act_n = 1'd1;
-reg [31:0] soc_litedramcore_master_p3_wrdata = 32'd0;
-reg soc_litedramcore_master_p3_wrdata_en = 1'd0;
-reg [3:0] soc_litedramcore_master_p3_wrdata_mask = 4'd0;
-reg soc_litedramcore_master_p3_rddata_en = 1'd0;
-wire [31:0] soc_litedramcore_master_p3_rddata;
-wire soc_litedramcore_master_p3_rddata_valid;
-wire [13:0] soc_litedramcore_csr_dfi_p0_address;
-wire [2:0] soc_litedramcore_csr_dfi_p0_bank;
-reg soc_litedramcore_csr_dfi_p0_cas_n = 1'd1;
-reg soc_litedramcore_csr_dfi_p0_cs_n = 1'd1;
-reg soc_litedramcore_csr_dfi_p0_ras_n = 1'd1;
-reg soc_litedramcore_csr_dfi_p0_we_n = 1'd1;
-wire soc_litedramcore_csr_dfi_p0_cke;
-wire soc_litedramcore_csr_dfi_p0_odt;
-wire soc_litedramcore_csr_dfi_p0_reset_n;
-reg soc_litedramcore_csr_dfi_p0_act_n = 1'd1;
-wire [31:0] soc_litedramcore_csr_dfi_p0_wrdata;
-wire soc_litedramcore_csr_dfi_p0_wrdata_en;
-wire [3:0] soc_litedramcore_csr_dfi_p0_wrdata_mask;
-wire soc_litedramcore_csr_dfi_p0_rddata_en;
-reg [31:0] soc_litedramcore_csr_dfi_p0_rddata = 32'd0;
-reg soc_litedramcore_csr_dfi_p0_rddata_valid = 1'd0;
-wire [13:0] soc_litedramcore_csr_dfi_p1_address;
-wire [2:0] soc_litedramcore_csr_dfi_p1_bank;
-reg soc_litedramcore_csr_dfi_p1_cas_n = 1'd1;
-reg soc_litedramcore_csr_dfi_p1_cs_n = 1'd1;
-reg soc_litedramcore_csr_dfi_p1_ras_n = 1'd1;
-reg soc_litedramcore_csr_dfi_p1_we_n = 1'd1;
-wire soc_litedramcore_csr_dfi_p1_cke;
-wire soc_litedramcore_csr_dfi_p1_odt;
-wire soc_litedramcore_csr_dfi_p1_reset_n;
-reg soc_litedramcore_csr_dfi_p1_act_n = 1'd1;
-wire [31:0] soc_litedramcore_csr_dfi_p1_wrdata;
-wire soc_litedramcore_csr_dfi_p1_wrdata_en;
-wire [3:0] soc_litedramcore_csr_dfi_p1_wrdata_mask;
-wire soc_litedramcore_csr_dfi_p1_rddata_en;
-reg [31:0] soc_litedramcore_csr_dfi_p1_rddata = 32'd0;
-reg soc_litedramcore_csr_dfi_p1_rddata_valid = 1'd0;
-wire [13:0] soc_litedramcore_csr_dfi_p2_address;
-wire [2:0] soc_litedramcore_csr_dfi_p2_bank;
-reg soc_litedramcore_csr_dfi_p2_cas_n = 1'd1;
-reg soc_litedramcore_csr_dfi_p2_cs_n = 1'd1;
-reg soc_litedramcore_csr_dfi_p2_ras_n = 1'd1;
-reg soc_litedramcore_csr_dfi_p2_we_n = 1'd1;
-wire soc_litedramcore_csr_dfi_p2_cke;
-wire soc_litedramcore_csr_dfi_p2_odt;
-wire soc_litedramcore_csr_dfi_p2_reset_n;
-reg soc_litedramcore_csr_dfi_p2_act_n = 1'd1;
-wire [31:0] soc_litedramcore_csr_dfi_p2_wrdata;
-wire soc_litedramcore_csr_dfi_p2_wrdata_en;
-wire [3:0] soc_litedramcore_csr_dfi_p2_wrdata_mask;
-wire soc_litedramcore_csr_dfi_p2_rddata_en;
-reg [31:0] soc_litedramcore_csr_dfi_p2_rddata = 32'd0;
-reg soc_litedramcore_csr_dfi_p2_rddata_valid = 1'd0;
-wire [13:0] soc_litedramcore_csr_dfi_p3_address;
-wire [2:0] soc_litedramcore_csr_dfi_p3_bank;
-reg soc_litedramcore_csr_dfi_p3_cas_n = 1'd1;
-reg soc_litedramcore_csr_dfi_p3_cs_n = 1'd1;
-reg soc_litedramcore_csr_dfi_p3_ras_n = 1'd1;
-reg soc_litedramcore_csr_dfi_p3_we_n = 1'd1;
-wire soc_litedramcore_csr_dfi_p3_cke;
-wire soc_litedramcore_csr_dfi_p3_odt;
-wire soc_litedramcore_csr_dfi_p3_reset_n;
-reg soc_litedramcore_csr_dfi_p3_act_n = 1'd1;
-wire [31:0] soc_litedramcore_csr_dfi_p3_wrdata;
-wire soc_litedramcore_csr_dfi_p3_wrdata_en;
-wire [3:0] soc_litedramcore_csr_dfi_p3_wrdata_mask;
-wire soc_litedramcore_csr_dfi_p3_rddata_en;
-reg [31:0] soc_litedramcore_csr_dfi_p3_rddata = 32'd0;
-reg soc_litedramcore_csr_dfi_p3_rddata_valid = 1'd0;
-reg [13:0] soc_litedramcore_ext_dfi_p0_address = 14'd0;
-reg [2:0] soc_litedramcore_ext_dfi_p0_bank = 3'd0;
-reg soc_litedramcore_ext_dfi_p0_cas_n = 1'd1;
-reg soc_litedramcore_ext_dfi_p0_cs_n = 1'd1;
-reg soc_litedramcore_ext_dfi_p0_ras_n = 1'd1;
-reg soc_litedramcore_ext_dfi_p0_we_n = 1'd1;
-reg soc_litedramcore_ext_dfi_p0_cke = 1'd0;
-reg soc_litedramcore_ext_dfi_p0_odt = 1'd0;
-reg soc_litedramcore_ext_dfi_p0_reset_n = 1'd0;
-reg soc_litedramcore_ext_dfi_p0_act_n = 1'd1;
-reg [31:0] soc_litedramcore_ext_dfi_p0_wrdata = 32'd0;
-reg soc_litedramcore_ext_dfi_p0_wrdata_en = 1'd0;
-reg [3:0] soc_litedramcore_ext_dfi_p0_wrdata_mask = 4'd0;
-reg soc_litedramcore_ext_dfi_p0_rddata_en = 1'd0;
-reg [31:0] soc_litedramcore_ext_dfi_p0_rddata = 32'd0;
-reg soc_litedramcore_ext_dfi_p0_rddata_valid = 1'd0;
-reg [13:0] soc_litedramcore_ext_dfi_p1_address = 14'd0;
-reg [2:0] soc_litedramcore_ext_dfi_p1_bank = 3'd0;
-reg soc_litedramcore_ext_dfi_p1_cas_n = 1'd1;
-reg soc_litedramcore_ext_dfi_p1_cs_n = 1'd1;
-reg soc_litedramcore_ext_dfi_p1_ras_n = 1'd1;
-reg soc_litedramcore_ext_dfi_p1_we_n = 1'd1;
-reg soc_litedramcore_ext_dfi_p1_cke = 1'd0;
-reg soc_litedramcore_ext_dfi_p1_odt = 1'd0;
-reg soc_litedramcore_ext_dfi_p1_reset_n = 1'd0;
-reg soc_litedramcore_ext_dfi_p1_act_n = 1'd1;
-reg [31:0] soc_litedramcore_ext_dfi_p1_wrdata = 32'd0;
-reg soc_litedramcore_ext_dfi_p1_wrdata_en = 1'd0;
-reg [3:0] soc_litedramcore_ext_dfi_p1_wrdata_mask = 4'd0;
-reg soc_litedramcore_ext_dfi_p1_rddata_en = 1'd0;
-reg [31:0] soc_litedramcore_ext_dfi_p1_rddata = 32'd0;
-reg soc_litedramcore_ext_dfi_p1_rddata_valid = 1'd0;
-reg [13:0] soc_litedramcore_ext_dfi_p2_address = 14'd0;
-reg [2:0] soc_litedramcore_ext_dfi_p2_bank = 3'd0;
-reg soc_litedramcore_ext_dfi_p2_cas_n = 1'd1;
-reg soc_litedramcore_ext_dfi_p2_cs_n = 1'd1;
-reg soc_litedramcore_ext_dfi_p2_ras_n = 1'd1;
-reg soc_litedramcore_ext_dfi_p2_we_n = 1'd1;
-reg soc_litedramcore_ext_dfi_p2_cke = 1'd0;
-reg soc_litedramcore_ext_dfi_p2_odt = 1'd0;
-reg soc_litedramcore_ext_dfi_p2_reset_n = 1'd0;
-reg soc_litedramcore_ext_dfi_p2_act_n = 1'd1;
-reg [31:0] soc_litedramcore_ext_dfi_p2_wrdata = 32'd0;
-reg soc_litedramcore_ext_dfi_p2_wrdata_en = 1'd0;
-reg [3:0] soc_litedramcore_ext_dfi_p2_wrdata_mask = 4'd0;
-reg soc_litedramcore_ext_dfi_p2_rddata_en = 1'd0;
-reg [31:0] soc_litedramcore_ext_dfi_p2_rddata = 32'd0;
-reg soc_litedramcore_ext_dfi_p2_rddata_valid = 1'd0;
-reg [13:0] soc_litedramcore_ext_dfi_p3_address = 14'd0;
-reg [2:0] soc_litedramcore_ext_dfi_p3_bank = 3'd0;
-reg soc_litedramcore_ext_dfi_p3_cas_n = 1'd1;
-reg soc_litedramcore_ext_dfi_p3_cs_n = 1'd1;
-reg soc_litedramcore_ext_dfi_p3_ras_n = 1'd1;
-reg soc_litedramcore_ext_dfi_p3_we_n = 1'd1;
-reg soc_litedramcore_ext_dfi_p3_cke = 1'd0;
-reg soc_litedramcore_ext_dfi_p3_odt = 1'd0;
-reg soc_litedramcore_ext_dfi_p3_reset_n = 1'd0;
-reg soc_litedramcore_ext_dfi_p3_act_n = 1'd1;
-reg [31:0] soc_litedramcore_ext_dfi_p3_wrdata = 32'd0;
-reg soc_litedramcore_ext_dfi_p3_wrdata_en = 1'd0;
-reg [3:0] soc_litedramcore_ext_dfi_p3_wrdata_mask = 4'd0;
-reg soc_litedramcore_ext_dfi_p3_rddata_en = 1'd0;
-reg [31:0] soc_litedramcore_ext_dfi_p3_rddata = 32'd0;
-reg soc_litedramcore_ext_dfi_p3_rddata_valid = 1'd0;
-reg soc_litedramcore_ext_dfi_sel = 1'd0;
-wire soc_litedramcore_sel;
-wire soc_litedramcore_cke;
-wire soc_litedramcore_odt;
-wire soc_litedramcore_reset_n;
-reg [3:0] soc_litedramcore_storage = 4'd1;
-reg soc_litedramcore_re = 1'd0;
-wire soc_litedramcore_phaseinjector0_csrfield_cs;
-wire soc_litedramcore_phaseinjector0_csrfield_we;
-wire soc_litedramcore_phaseinjector0_csrfield_cas;
-wire soc_litedramcore_phaseinjector0_csrfield_ras;
-wire soc_litedramcore_phaseinjector0_csrfield_wren;
-wire soc_litedramcore_phaseinjector0_csrfield_rden;
-reg [5:0] soc_litedramcore_phaseinjector0_command_storage = 6'd0;
-reg soc_litedramcore_phaseinjector0_command_re = 1'd0;
-reg soc_litedramcore_phaseinjector0_command_issue_re = 1'd0;
-wire soc_litedramcore_phaseinjector0_command_issue_r;
-reg soc_litedramcore_phaseinjector0_command_issue_we = 1'd0;
-reg soc_litedramcore_phaseinjector0_command_issue_w = 1'd0;
-reg [13:0] soc_litedramcore_phaseinjector0_address_storage = 14'd0;
-reg soc_litedramcore_phaseinjector0_address_re = 1'd0;
-reg [2:0] soc_litedramcore_phaseinjector0_baddress_storage = 3'd0;
-reg soc_litedramcore_phaseinjector0_baddress_re = 1'd0;
-reg [31:0] soc_litedramcore_phaseinjector0_wrdata_storage = 32'd0;
-reg soc_litedramcore_phaseinjector0_wrdata_re = 1'd0;
-reg [31:0] soc_litedramcore_phaseinjector0_rddata_status = 32'd0;
-wire soc_litedramcore_phaseinjector0_rddata_we;
-reg soc_litedramcore_phaseinjector0_rddata_re = 1'd0;
-wire soc_litedramcore_phaseinjector1_csrfield_cs;
-wire soc_litedramcore_phaseinjector1_csrfield_we;
-wire soc_litedramcore_phaseinjector1_csrfield_cas;
-wire soc_litedramcore_phaseinjector1_csrfield_ras;
-wire soc_litedramcore_phaseinjector1_csrfield_wren;
-wire soc_litedramcore_phaseinjector1_csrfield_rden;
-reg [5:0] soc_litedramcore_phaseinjector1_command_storage = 6'd0;
-reg soc_litedramcore_phaseinjector1_command_re = 1'd0;
-reg soc_litedramcore_phaseinjector1_command_issue_re = 1'd0;
-wire soc_litedramcore_phaseinjector1_command_issue_r;
-reg soc_litedramcore_phaseinjector1_command_issue_we = 1'd0;
-reg soc_litedramcore_phaseinjector1_command_issue_w = 1'd0;
-reg [13:0] soc_litedramcore_phaseinjector1_address_storage = 14'd0;
-reg soc_litedramcore_phaseinjector1_address_re = 1'd0;
-reg [2:0] soc_litedramcore_phaseinjector1_baddress_storage = 3'd0;
-reg soc_litedramcore_phaseinjector1_baddress_re = 1'd0;
-reg [31:0] soc_litedramcore_phaseinjector1_wrdata_storage = 32'd0;
-reg soc_litedramcore_phaseinjector1_wrdata_re = 1'd0;
-reg [31:0] soc_litedramcore_phaseinjector1_rddata_status = 32'd0;
-wire soc_litedramcore_phaseinjector1_rddata_we;
-reg soc_litedramcore_phaseinjector1_rddata_re = 1'd0;
-wire soc_litedramcore_phaseinjector2_csrfield_cs;
-wire soc_litedramcore_phaseinjector2_csrfield_we;
-wire soc_litedramcore_phaseinjector2_csrfield_cas;
-wire soc_litedramcore_phaseinjector2_csrfield_ras;
-wire soc_litedramcore_phaseinjector2_csrfield_wren;
-wire soc_litedramcore_phaseinjector2_csrfield_rden;
-reg [5:0] soc_litedramcore_phaseinjector2_command_storage = 6'd0;
-reg soc_litedramcore_phaseinjector2_command_re = 1'd0;
-reg soc_litedramcore_phaseinjector2_command_issue_re = 1'd0;
-wire soc_litedramcore_phaseinjector2_command_issue_r;
-reg soc_litedramcore_phaseinjector2_command_issue_we = 1'd0;
-reg soc_litedramcore_phaseinjector2_command_issue_w = 1'd0;
-reg [13:0] soc_litedramcore_phaseinjector2_address_storage = 14'd0;
-reg soc_litedramcore_phaseinjector2_address_re = 1'd0;
-reg [2:0] soc_litedramcore_phaseinjector2_baddress_storage = 3'd0;
-reg soc_litedramcore_phaseinjector2_baddress_re = 1'd0;
-reg [31:0] soc_litedramcore_phaseinjector2_wrdata_storage = 32'd0;
-reg soc_litedramcore_phaseinjector2_wrdata_re = 1'd0;
-reg [31:0] soc_litedramcore_phaseinjector2_rddata_status = 32'd0;
-wire soc_litedramcore_phaseinjector2_rddata_we;
-reg soc_litedramcore_phaseinjector2_rddata_re = 1'd0;
-wire soc_litedramcore_phaseinjector3_csrfield_cs;
-wire soc_litedramcore_phaseinjector3_csrfield_we;
-wire soc_litedramcore_phaseinjector3_csrfield_cas;
-wire soc_litedramcore_phaseinjector3_csrfield_ras;
-wire soc_litedramcore_phaseinjector3_csrfield_wren;
-wire soc_litedramcore_phaseinjector3_csrfield_rden;
-reg [5:0] soc_litedramcore_phaseinjector3_command_storage = 6'd0;
-reg soc_litedramcore_phaseinjector3_command_re = 1'd0;
-reg soc_litedramcore_phaseinjector3_command_issue_re = 1'd0;
-wire soc_litedramcore_phaseinjector3_command_issue_r;
-reg soc_litedramcore_phaseinjector3_command_issue_we = 1'd0;
-reg soc_litedramcore_phaseinjector3_command_issue_w = 1'd0;
-reg [13:0] soc_litedramcore_phaseinjector3_address_storage = 14'd0;
-reg soc_litedramcore_phaseinjector3_address_re = 1'd0;
-reg [2:0] soc_litedramcore_phaseinjector3_baddress_storage = 3'd0;
-reg soc_litedramcore_phaseinjector3_baddress_re = 1'd0;
-reg [31:0] soc_litedramcore_phaseinjector3_wrdata_storage = 32'd0;
-reg soc_litedramcore_phaseinjector3_wrdata_re = 1'd0;
-reg [31:0] soc_litedramcore_phaseinjector3_rddata_status = 32'd0;
-wire soc_litedramcore_phaseinjector3_rddata_we;
-reg soc_litedramcore_phaseinjector3_rddata_re = 1'd0;
-wire soc_litedramcore_interface_bank0_valid;
-wire soc_litedramcore_interface_bank0_ready;
-wire soc_litedramcore_interface_bank0_we;
-wire [20:0] soc_litedramcore_interface_bank0_addr;
-wire soc_litedramcore_interface_bank0_lock;
-wire soc_litedramcore_interface_bank0_wdata_ready;
-wire soc_litedramcore_interface_bank0_rdata_valid;
-wire soc_litedramcore_interface_bank1_valid;
-wire soc_litedramcore_interface_bank1_ready;
-wire soc_litedramcore_interface_bank1_we;
-wire [20:0] soc_litedramcore_interface_bank1_addr;
-wire soc_litedramcore_interface_bank1_lock;
-wire soc_litedramcore_interface_bank1_wdata_ready;
-wire soc_litedramcore_interface_bank1_rdata_valid;
-wire soc_litedramcore_interface_bank2_valid;
-wire soc_litedramcore_interface_bank2_ready;
-wire soc_litedramcore_interface_bank2_we;
-wire [20:0] soc_litedramcore_interface_bank2_addr;
-wire soc_litedramcore_interface_bank2_lock;
-wire soc_litedramcore_interface_bank2_wdata_ready;
-wire soc_litedramcore_interface_bank2_rdata_valid;
-wire soc_litedramcore_interface_bank3_valid;
-wire soc_litedramcore_interface_bank3_ready;
-wire soc_litedramcore_interface_bank3_we;
-wire [20:0] soc_litedramcore_interface_bank3_addr;
-wire soc_litedramcore_interface_bank3_lock;
-wire soc_litedramcore_interface_bank3_wdata_ready;
-wire soc_litedramcore_interface_bank3_rdata_valid;
-wire soc_litedramcore_interface_bank4_valid;
-wire soc_litedramcore_interface_bank4_ready;
-wire soc_litedramcore_interface_bank4_we;
-wire [20:0] soc_litedramcore_interface_bank4_addr;
-wire soc_litedramcore_interface_bank4_lock;
-wire soc_litedramcore_interface_bank4_wdata_ready;
-wire soc_litedramcore_interface_bank4_rdata_valid;
-wire soc_litedramcore_interface_bank5_valid;
-wire soc_litedramcore_interface_bank5_ready;
-wire soc_litedramcore_interface_bank5_we;
-wire [20:0] soc_litedramcore_interface_bank5_addr;
-wire soc_litedramcore_interface_bank5_lock;
-wire soc_litedramcore_interface_bank5_wdata_ready;
-wire soc_litedramcore_interface_bank5_rdata_valid;
-wire soc_litedramcore_interface_bank6_valid;
-wire soc_litedramcore_interface_bank6_ready;
-wire soc_litedramcore_interface_bank6_we;
-wire [20:0] soc_litedramcore_interface_bank6_addr;
-wire soc_litedramcore_interface_bank6_lock;
-wire soc_litedramcore_interface_bank6_wdata_ready;
-wire soc_litedramcore_interface_bank6_rdata_valid;
-wire soc_litedramcore_interface_bank7_valid;
-wire soc_litedramcore_interface_bank7_ready;
-wire soc_litedramcore_interface_bank7_we;
-wire [20:0] soc_litedramcore_interface_bank7_addr;
-wire soc_litedramcore_interface_bank7_lock;
-wire soc_litedramcore_interface_bank7_wdata_ready;
-wire soc_litedramcore_interface_bank7_rdata_valid;
-reg [127:0] soc_litedramcore_interface_wdata = 128'd0;
-reg [15:0] soc_litedramcore_interface_wdata_we = 16'd0;
-wire [127:0] soc_litedramcore_interface_rdata;
-reg [13:0] soc_litedramcore_dfi_p0_address = 14'd0;
-reg [2:0] soc_litedramcore_dfi_p0_bank = 3'd0;
-reg soc_litedramcore_dfi_p0_cas_n = 1'd1;
-reg soc_litedramcore_dfi_p0_cs_n = 1'd1;
-reg soc_litedramcore_dfi_p0_ras_n = 1'd1;
-reg soc_litedramcore_dfi_p0_we_n = 1'd1;
-wire soc_litedramcore_dfi_p0_cke;
-wire soc_litedramcore_dfi_p0_odt;
-wire soc_litedramcore_dfi_p0_reset_n;
-reg soc_litedramcore_dfi_p0_act_n = 1'd1;
-wire [31:0] soc_litedramcore_dfi_p0_wrdata;
-reg soc_litedramcore_dfi_p0_wrdata_en = 1'd0;
-wire [3:0] soc_litedramcore_dfi_p0_wrdata_mask;
-reg soc_litedramcore_dfi_p0_rddata_en = 1'd0;
-wire [31:0] soc_litedramcore_dfi_p0_rddata;
-wire soc_litedramcore_dfi_p0_rddata_valid;
-reg [13:0] soc_litedramcore_dfi_p1_address = 14'd0;
-reg [2:0] soc_litedramcore_dfi_p1_bank = 3'd0;
-reg soc_litedramcore_dfi_p1_cas_n = 1'd1;
-reg soc_litedramcore_dfi_p1_cs_n = 1'd1;
-reg soc_litedramcore_dfi_p1_ras_n = 1'd1;
-reg soc_litedramcore_dfi_p1_we_n = 1'd1;
-wire soc_litedramcore_dfi_p1_cke;
-wire soc_litedramcore_dfi_p1_odt;
-wire soc_litedramcore_dfi_p1_reset_n;
-reg soc_litedramcore_dfi_p1_act_n = 1'd1;
-wire [31:0] soc_litedramcore_dfi_p1_wrdata;
-reg soc_litedramcore_dfi_p1_wrdata_en = 1'd0;
-wire [3:0] soc_litedramcore_dfi_p1_wrdata_mask;
-reg soc_litedramcore_dfi_p1_rddata_en = 1'd0;
-wire [31:0] soc_litedramcore_dfi_p1_rddata;
-wire soc_litedramcore_dfi_p1_rddata_valid;
-reg [13:0] soc_litedramcore_dfi_p2_address = 14'd0;
-reg [2:0] soc_litedramcore_dfi_p2_bank = 3'd0;
-reg soc_litedramcore_dfi_p2_cas_n = 1'd1;
-reg soc_litedramcore_dfi_p2_cs_n = 1'd1;
-reg soc_litedramcore_dfi_p2_ras_n = 1'd1;
-reg soc_litedramcore_dfi_p2_we_n = 1'd1;
-wire soc_litedramcore_dfi_p2_cke;
-wire soc_litedramcore_dfi_p2_odt;
-wire soc_litedramcore_dfi_p2_reset_n;
-reg soc_litedramcore_dfi_p2_act_n = 1'd1;
-wire [31:0] soc_litedramcore_dfi_p2_wrdata;
-reg soc_litedramcore_dfi_p2_wrdata_en = 1'd0;
-wire [3:0] soc_litedramcore_dfi_p2_wrdata_mask;
-reg soc_litedramcore_dfi_p2_rddata_en = 1'd0;
-wire [31:0] soc_litedramcore_dfi_p2_rddata;
-wire soc_litedramcore_dfi_p2_rddata_valid;
-reg [13:0] soc_litedramcore_dfi_p3_address = 14'd0;
-reg [2:0] soc_litedramcore_dfi_p3_bank = 3'd0;
-reg soc_litedramcore_dfi_p3_cas_n = 1'd1;
-reg soc_litedramcore_dfi_p3_cs_n = 1'd1;
-reg soc_litedramcore_dfi_p3_ras_n = 1'd1;
-reg soc_litedramcore_dfi_p3_we_n = 1'd1;
-wire soc_litedramcore_dfi_p3_cke;
-wire soc_litedramcore_dfi_p3_odt;
-wire soc_litedramcore_dfi_p3_reset_n;
-reg soc_litedramcore_dfi_p3_act_n = 1'd1;
-wire [31:0] soc_litedramcore_dfi_p3_wrdata;
-reg soc_litedramcore_dfi_p3_wrdata_en = 1'd0;
-wire [3:0] soc_litedramcore_dfi_p3_wrdata_mask;
-reg soc_litedramcore_dfi_p3_rddata_en = 1'd0;
-wire [31:0] soc_litedramcore_dfi_p3_rddata;
-wire soc_litedramcore_dfi_p3_rddata_valid;
-reg soc_litedramcore_cmd_valid = 1'd0;
-reg soc_litedramcore_cmd_ready = 1'd0;
-reg soc_litedramcore_cmd_last = 1'd0;
-reg [13:0] soc_litedramcore_cmd_payload_a = 14'd0;
-reg [2:0] soc_litedramcore_cmd_payload_ba = 3'd0;
-reg soc_litedramcore_cmd_payload_cas = 1'd0;
-reg soc_litedramcore_cmd_payload_ras = 1'd0;
-reg soc_litedramcore_cmd_payload_we = 1'd0;
-reg soc_litedramcore_cmd_payload_is_read = 1'd0;
-reg soc_litedramcore_cmd_payload_is_write = 1'd0;
-wire soc_litedramcore_wants_refresh;
-wire soc_litedramcore_wants_zqcs;
-wire soc_litedramcore_timer_wait;
-wire soc_litedramcore_timer_done0;
-wire [9:0] soc_litedramcore_timer_count0;
-wire soc_litedramcore_timer_done1;
-reg [9:0] soc_litedramcore_timer_count1 = 10'd781;
-wire soc_litedramcore_postponer_req_i;
-reg soc_litedramcore_postponer_req_o = 1'd0;
-reg soc_litedramcore_postponer_count = 1'd0;
-reg soc_litedramcore_sequencer_start0 = 1'd0;
-wire soc_litedramcore_sequencer_done0;
-wire soc_litedramcore_sequencer_start1;
-reg soc_litedramcore_sequencer_done1 = 1'd0;
-reg [5:0] soc_litedramcore_sequencer_counter = 6'd0;
-reg soc_litedramcore_sequencer_count = 1'd0;
-wire soc_litedramcore_zqcs_timer_wait;
-wire soc_litedramcore_zqcs_timer_done0;
-wire [26:0] soc_litedramcore_zqcs_timer_count0;
-wire soc_litedramcore_zqcs_timer_done1;
-reg [26:0] soc_litedramcore_zqcs_timer_count1 = 27'd99999999;
-reg soc_litedramcore_zqcs_executer_start = 1'd0;
-reg soc_litedramcore_zqcs_executer_done = 1'd0;
-reg [4:0] soc_litedramcore_zqcs_executer_counter = 5'd0;
-wire soc_litedramcore_bankmachine0_req_valid;
-wire soc_litedramcore_bankmachine0_req_ready;
-wire soc_litedramcore_bankmachine0_req_we;
-wire [20:0] soc_litedramcore_bankmachine0_req_addr;
-wire soc_litedramcore_bankmachine0_req_lock;
-reg soc_litedramcore_bankmachine0_req_wdata_ready = 1'd0;
-reg soc_litedramcore_bankmachine0_req_rdata_valid = 1'd0;
-wire soc_litedramcore_bankmachine0_refresh_req;
-reg soc_litedramcore_bankmachine0_refresh_gnt = 1'd0;
-reg soc_litedramcore_bankmachine0_cmd_valid = 1'd0;
-reg soc_litedramcore_bankmachine0_cmd_ready = 1'd0;
-reg [13:0] soc_litedramcore_bankmachine0_cmd_payload_a = 14'd0;
-wire [2:0] soc_litedramcore_bankmachine0_cmd_payload_ba;
-reg soc_litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
-reg soc_litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
-reg soc_litedramcore_bankmachine0_cmd_payload_we = 1'd0;
-reg soc_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
-reg soc_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
-reg soc_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
-reg soc_litedramcore_bankmachine0_auto_precharge = 1'd0;
-wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
-wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
-reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
-reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
-wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
-wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
-wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
-wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
-wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
-wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
-wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we;
-wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
-wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
-wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
-wire [23:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
-wire [23:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-reg [4:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
-reg soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
-wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we;
-wire [23:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
-wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read;
-wire [3:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
-wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first;
-wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last;
-wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
-wire soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
-wire soc_litedramcore_bankmachine0_cmd_buffer_sink_valid;
-wire soc_litedramcore_bankmachine0_cmd_buffer_sink_ready;
-wire soc_litedramcore_bankmachine0_cmd_buffer_sink_first;
-wire soc_litedramcore_bankmachine0_cmd_buffer_sink_last;
-wire soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
-wire [20:0] soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
-reg soc_litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0;
-wire soc_litedramcore_bankmachine0_cmd_buffer_source_ready;
-reg soc_litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0;
-reg soc_litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0;
-reg soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] soc_litedramcore_bankmachine0_row = 14'd0;
-reg soc_litedramcore_bankmachine0_row_opened = 1'd0;
-wire soc_litedramcore_bankmachine0_row_hit;
-reg soc_litedramcore_bankmachine0_row_open = 1'd0;
-reg soc_litedramcore_bankmachine0_row_close = 1'd0;
-reg soc_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
-wire soc_litedramcore_bankmachine0_twtpcon_valid;
-reg soc_litedramcore_bankmachine0_twtpcon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine0_twtpcon_count = 3'd0;
-wire soc_litedramcore_bankmachine0_trccon_valid;
-reg soc_litedramcore_bankmachine0_trccon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine0_trccon_count = 3'd0;
-wire soc_litedramcore_bankmachine0_trascon_valid;
-reg soc_litedramcore_bankmachine0_trascon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine0_trascon_count = 3'd0;
-wire soc_litedramcore_bankmachine1_req_valid;
-wire soc_litedramcore_bankmachine1_req_ready;
-wire soc_litedramcore_bankmachine1_req_we;
-wire [20:0] soc_litedramcore_bankmachine1_req_addr;
-wire soc_litedramcore_bankmachine1_req_lock;
-reg soc_litedramcore_bankmachine1_req_wdata_ready = 1'd0;
-reg soc_litedramcore_bankmachine1_req_rdata_valid = 1'd0;
-wire soc_litedramcore_bankmachine1_refresh_req;
-reg soc_litedramcore_bankmachine1_refresh_gnt = 1'd0;
-reg soc_litedramcore_bankmachine1_cmd_valid = 1'd0;
-reg soc_litedramcore_bankmachine1_cmd_ready = 1'd0;
-reg [13:0] soc_litedramcore_bankmachine1_cmd_payload_a = 14'd0;
-wire [2:0] soc_litedramcore_bankmachine1_cmd_payload_ba;
-reg soc_litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
-reg soc_litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
-reg soc_litedramcore_bankmachine1_cmd_payload_we = 1'd0;
-reg soc_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
-reg soc_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
-reg soc_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
-reg soc_litedramcore_bankmachine1_auto_precharge = 1'd0;
-wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
-wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
-reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
-reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
-wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
-wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
-wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
-wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
-wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
-wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
-wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we;
-wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
-wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
-wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
-wire [23:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
-wire [23:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-reg [4:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
-reg soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
-wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we;
-wire [23:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
-wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read;
-wire [3:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
-wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first;
-wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last;
-wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
-wire soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
-wire soc_litedramcore_bankmachine1_cmd_buffer_sink_valid;
-wire soc_litedramcore_bankmachine1_cmd_buffer_sink_ready;
-wire soc_litedramcore_bankmachine1_cmd_buffer_sink_first;
-wire soc_litedramcore_bankmachine1_cmd_buffer_sink_last;
-wire soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
-wire [20:0] soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
-reg soc_litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0;
-wire soc_litedramcore_bankmachine1_cmd_buffer_source_ready;
-reg soc_litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0;
-reg soc_litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0;
-reg soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] soc_litedramcore_bankmachine1_row = 14'd0;
-reg soc_litedramcore_bankmachine1_row_opened = 1'd0;
-wire soc_litedramcore_bankmachine1_row_hit;
-reg soc_litedramcore_bankmachine1_row_open = 1'd0;
-reg soc_litedramcore_bankmachine1_row_close = 1'd0;
-reg soc_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
-wire soc_litedramcore_bankmachine1_twtpcon_valid;
-reg soc_litedramcore_bankmachine1_twtpcon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine1_twtpcon_count = 3'd0;
-wire soc_litedramcore_bankmachine1_trccon_valid;
-reg soc_litedramcore_bankmachine1_trccon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine1_trccon_count = 3'd0;
-wire soc_litedramcore_bankmachine1_trascon_valid;
-reg soc_litedramcore_bankmachine1_trascon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine1_trascon_count = 3'd0;
-wire soc_litedramcore_bankmachine2_req_valid;
-wire soc_litedramcore_bankmachine2_req_ready;
-wire soc_litedramcore_bankmachine2_req_we;
-wire [20:0] soc_litedramcore_bankmachine2_req_addr;
-wire soc_litedramcore_bankmachine2_req_lock;
-reg soc_litedramcore_bankmachine2_req_wdata_ready = 1'd0;
-reg soc_litedramcore_bankmachine2_req_rdata_valid = 1'd0;
-wire soc_litedramcore_bankmachine2_refresh_req;
-reg soc_litedramcore_bankmachine2_refresh_gnt = 1'd0;
-reg soc_litedramcore_bankmachine2_cmd_valid = 1'd0;
-reg soc_litedramcore_bankmachine2_cmd_ready = 1'd0;
-reg [13:0] soc_litedramcore_bankmachine2_cmd_payload_a = 14'd0;
-wire [2:0] soc_litedramcore_bankmachine2_cmd_payload_ba;
-reg soc_litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
-reg soc_litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
-reg soc_litedramcore_bankmachine2_cmd_payload_we = 1'd0;
-reg soc_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
-reg soc_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
-reg soc_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
-reg soc_litedramcore_bankmachine2_auto_precharge = 1'd0;
-wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
-wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
-reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
-reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
-wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
-wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
-wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
-wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
-wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
-wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
-wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we;
-wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
-wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
-wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
-wire [23:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
-wire [23:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-reg [4:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
-reg soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
-wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we;
-wire [23:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
-wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read;
-wire [3:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
-wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first;
-wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last;
-wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
-wire soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
-wire soc_litedramcore_bankmachine2_cmd_buffer_sink_valid;
-wire soc_litedramcore_bankmachine2_cmd_buffer_sink_ready;
-wire soc_litedramcore_bankmachine2_cmd_buffer_sink_first;
-wire soc_litedramcore_bankmachine2_cmd_buffer_sink_last;
-wire soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
-wire [20:0] soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
-reg soc_litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0;
-wire soc_litedramcore_bankmachine2_cmd_buffer_source_ready;
-reg soc_litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0;
-reg soc_litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0;
-reg soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] soc_litedramcore_bankmachine2_row = 14'd0;
-reg soc_litedramcore_bankmachine2_row_opened = 1'd0;
-wire soc_litedramcore_bankmachine2_row_hit;
-reg soc_litedramcore_bankmachine2_row_open = 1'd0;
-reg soc_litedramcore_bankmachine2_row_close = 1'd0;
-reg soc_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
-wire soc_litedramcore_bankmachine2_twtpcon_valid;
-reg soc_litedramcore_bankmachine2_twtpcon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine2_twtpcon_count = 3'd0;
-wire soc_litedramcore_bankmachine2_trccon_valid;
-reg soc_litedramcore_bankmachine2_trccon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine2_trccon_count = 3'd0;
-wire soc_litedramcore_bankmachine2_trascon_valid;
-reg soc_litedramcore_bankmachine2_trascon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine2_trascon_count = 3'd0;
-wire soc_litedramcore_bankmachine3_req_valid;
-wire soc_litedramcore_bankmachine3_req_ready;
-wire soc_litedramcore_bankmachine3_req_we;
-wire [20:0] soc_litedramcore_bankmachine3_req_addr;
-wire soc_litedramcore_bankmachine3_req_lock;
-reg soc_litedramcore_bankmachine3_req_wdata_ready = 1'd0;
-reg soc_litedramcore_bankmachine3_req_rdata_valid = 1'd0;
-wire soc_litedramcore_bankmachine3_refresh_req;
-reg soc_litedramcore_bankmachine3_refresh_gnt = 1'd0;
-reg soc_litedramcore_bankmachine3_cmd_valid = 1'd0;
-reg soc_litedramcore_bankmachine3_cmd_ready = 1'd0;
-reg [13:0] soc_litedramcore_bankmachine3_cmd_payload_a = 14'd0;
-wire [2:0] soc_litedramcore_bankmachine3_cmd_payload_ba;
-reg soc_litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
-reg soc_litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
-reg soc_litedramcore_bankmachine3_cmd_payload_we = 1'd0;
-reg soc_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
-reg soc_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
-reg soc_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
-reg soc_litedramcore_bankmachine3_auto_precharge = 1'd0;
-wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
-wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
-reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
-reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
-wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
-wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
-wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
-wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
-wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
-wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
-wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we;
-wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
-wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
-wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
-wire [23:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
-wire [23:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-reg [4:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
-reg soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
-wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we;
-wire [23:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
-wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read;
-wire [3:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
-wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first;
-wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last;
-wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
-wire soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
-wire soc_litedramcore_bankmachine3_cmd_buffer_sink_valid;
-wire soc_litedramcore_bankmachine3_cmd_buffer_sink_ready;
-wire soc_litedramcore_bankmachine3_cmd_buffer_sink_first;
-wire soc_litedramcore_bankmachine3_cmd_buffer_sink_last;
-wire soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
-wire [20:0] soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
-reg soc_litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0;
-wire soc_litedramcore_bankmachine3_cmd_buffer_source_ready;
-reg soc_litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0;
-reg soc_litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0;
-reg soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] soc_litedramcore_bankmachine3_row = 14'd0;
-reg soc_litedramcore_bankmachine3_row_opened = 1'd0;
-wire soc_litedramcore_bankmachine3_row_hit;
-reg soc_litedramcore_bankmachine3_row_open = 1'd0;
-reg soc_litedramcore_bankmachine3_row_close = 1'd0;
-reg soc_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
-wire soc_litedramcore_bankmachine3_twtpcon_valid;
-reg soc_litedramcore_bankmachine3_twtpcon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine3_twtpcon_count = 3'd0;
-wire soc_litedramcore_bankmachine3_trccon_valid;
-reg soc_litedramcore_bankmachine3_trccon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine3_trccon_count = 3'd0;
-wire soc_litedramcore_bankmachine3_trascon_valid;
-reg soc_litedramcore_bankmachine3_trascon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine3_trascon_count = 3'd0;
-wire soc_litedramcore_bankmachine4_req_valid;
-wire soc_litedramcore_bankmachine4_req_ready;
-wire soc_litedramcore_bankmachine4_req_we;
-wire [20:0] soc_litedramcore_bankmachine4_req_addr;
-wire soc_litedramcore_bankmachine4_req_lock;
-reg soc_litedramcore_bankmachine4_req_wdata_ready = 1'd0;
-reg soc_litedramcore_bankmachine4_req_rdata_valid = 1'd0;
-wire soc_litedramcore_bankmachine4_refresh_req;
-reg soc_litedramcore_bankmachine4_refresh_gnt = 1'd0;
-reg soc_litedramcore_bankmachine4_cmd_valid = 1'd0;
-reg soc_litedramcore_bankmachine4_cmd_ready = 1'd0;
-reg [13:0] soc_litedramcore_bankmachine4_cmd_payload_a = 14'd0;
-wire [2:0] soc_litedramcore_bankmachine4_cmd_payload_ba;
-reg soc_litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
-reg soc_litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
-reg soc_litedramcore_bankmachine4_cmd_payload_we = 1'd0;
-reg soc_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
-reg soc_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
-reg soc_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
-reg soc_litedramcore_bankmachine4_auto_precharge = 1'd0;
-wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
-wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
-reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
-reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
-wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
-wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
-wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
-wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
-wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
-wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
-wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we;
-wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
-wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re;
-wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
-wire [23:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
-wire [23:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-reg [4:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
-reg soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r;
-wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we;
-wire [23:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
-wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read;
-wire [3:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
-wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first;
-wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last;
-wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
-wire soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
-wire soc_litedramcore_bankmachine4_cmd_buffer_sink_valid;
-wire soc_litedramcore_bankmachine4_cmd_buffer_sink_ready;
-wire soc_litedramcore_bankmachine4_cmd_buffer_sink_first;
-wire soc_litedramcore_bankmachine4_cmd_buffer_sink_last;
-wire soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
-wire [20:0] soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
-reg soc_litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0;
-wire soc_litedramcore_bankmachine4_cmd_buffer_source_ready;
-reg soc_litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0;
-reg soc_litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0;
-reg soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] soc_litedramcore_bankmachine4_row = 14'd0;
-reg soc_litedramcore_bankmachine4_row_opened = 1'd0;
-wire soc_litedramcore_bankmachine4_row_hit;
-reg soc_litedramcore_bankmachine4_row_open = 1'd0;
-reg soc_litedramcore_bankmachine4_row_close = 1'd0;
-reg soc_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
-wire soc_litedramcore_bankmachine4_twtpcon_valid;
-reg soc_litedramcore_bankmachine4_twtpcon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine4_twtpcon_count = 3'd0;
-wire soc_litedramcore_bankmachine4_trccon_valid;
-reg soc_litedramcore_bankmachine4_trccon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine4_trccon_count = 3'd0;
-wire soc_litedramcore_bankmachine4_trascon_valid;
-reg soc_litedramcore_bankmachine4_trascon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine4_trascon_count = 3'd0;
-wire soc_litedramcore_bankmachine5_req_valid;
-wire soc_litedramcore_bankmachine5_req_ready;
-wire soc_litedramcore_bankmachine5_req_we;
-wire [20:0] soc_litedramcore_bankmachine5_req_addr;
-wire soc_litedramcore_bankmachine5_req_lock;
-reg soc_litedramcore_bankmachine5_req_wdata_ready = 1'd0;
-reg soc_litedramcore_bankmachine5_req_rdata_valid = 1'd0;
-wire soc_litedramcore_bankmachine5_refresh_req;
-reg soc_litedramcore_bankmachine5_refresh_gnt = 1'd0;
-reg soc_litedramcore_bankmachine5_cmd_valid = 1'd0;
-reg soc_litedramcore_bankmachine5_cmd_ready = 1'd0;
-reg [13:0] soc_litedramcore_bankmachine5_cmd_payload_a = 14'd0;
-wire [2:0] soc_litedramcore_bankmachine5_cmd_payload_ba;
-reg soc_litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
-reg soc_litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
-reg soc_litedramcore_bankmachine5_cmd_payload_we = 1'd0;
-reg soc_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
-reg soc_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
-reg soc_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
-reg soc_litedramcore_bankmachine5_auto_precharge = 1'd0;
-wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
-wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
-reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
-reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
-wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
-wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
-wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
-wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
-wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
-wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
-wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we;
-wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
-wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re;
-wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
-wire [23:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
-wire [23:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-reg [4:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
-reg soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r;
-wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we;
-wire [23:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
-wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read;
-wire [3:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
-wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first;
-wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last;
-wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
-wire soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
-wire soc_litedramcore_bankmachine5_cmd_buffer_sink_valid;
-wire soc_litedramcore_bankmachine5_cmd_buffer_sink_ready;
-wire soc_litedramcore_bankmachine5_cmd_buffer_sink_first;
-wire soc_litedramcore_bankmachine5_cmd_buffer_sink_last;
-wire soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
-wire [20:0] soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
-reg soc_litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0;
-wire soc_litedramcore_bankmachine5_cmd_buffer_source_ready;
-reg soc_litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0;
-reg soc_litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0;
-reg soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] soc_litedramcore_bankmachine5_row = 14'd0;
-reg soc_litedramcore_bankmachine5_row_opened = 1'd0;
-wire soc_litedramcore_bankmachine5_row_hit;
-reg soc_litedramcore_bankmachine5_row_open = 1'd0;
-reg soc_litedramcore_bankmachine5_row_close = 1'd0;
-reg soc_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
-wire soc_litedramcore_bankmachine5_twtpcon_valid;
-reg soc_litedramcore_bankmachine5_twtpcon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine5_twtpcon_count = 3'd0;
-wire soc_litedramcore_bankmachine5_trccon_valid;
-reg soc_litedramcore_bankmachine5_trccon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine5_trccon_count = 3'd0;
-wire soc_litedramcore_bankmachine5_trascon_valid;
-reg soc_litedramcore_bankmachine5_trascon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine5_trascon_count = 3'd0;
-wire soc_litedramcore_bankmachine6_req_valid;
-wire soc_litedramcore_bankmachine6_req_ready;
-wire soc_litedramcore_bankmachine6_req_we;
-wire [20:0] soc_litedramcore_bankmachine6_req_addr;
-wire soc_litedramcore_bankmachine6_req_lock;
-reg soc_litedramcore_bankmachine6_req_wdata_ready = 1'd0;
-reg soc_litedramcore_bankmachine6_req_rdata_valid = 1'd0;
-wire soc_litedramcore_bankmachine6_refresh_req;
-reg soc_litedramcore_bankmachine6_refresh_gnt = 1'd0;
-reg soc_litedramcore_bankmachine6_cmd_valid = 1'd0;
-reg soc_litedramcore_bankmachine6_cmd_ready = 1'd0;
-reg [13:0] soc_litedramcore_bankmachine6_cmd_payload_a = 14'd0;
-wire [2:0] soc_litedramcore_bankmachine6_cmd_payload_ba;
-reg soc_litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
-reg soc_litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
-reg soc_litedramcore_bankmachine6_cmd_payload_we = 1'd0;
-reg soc_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
-reg soc_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
-reg soc_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
-reg soc_litedramcore_bankmachine6_auto_precharge = 1'd0;
-wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
-wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
-reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
-reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
-wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
-wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
-wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
-wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
-wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
-wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
-wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we;
-wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
-wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re;
-wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
-wire [23:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
-wire [23:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-reg [4:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
-reg soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r;
-wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we;
-wire [23:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
-wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read;
-wire [3:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
-wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first;
-wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last;
-wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
-wire soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
-wire soc_litedramcore_bankmachine6_cmd_buffer_sink_valid;
-wire soc_litedramcore_bankmachine6_cmd_buffer_sink_ready;
-wire soc_litedramcore_bankmachine6_cmd_buffer_sink_first;
-wire soc_litedramcore_bankmachine6_cmd_buffer_sink_last;
-wire soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
-wire [20:0] soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
-reg soc_litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0;
-wire soc_litedramcore_bankmachine6_cmd_buffer_source_ready;
-reg soc_litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0;
-reg soc_litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0;
-reg soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] soc_litedramcore_bankmachine6_row = 14'd0;
-reg soc_litedramcore_bankmachine6_row_opened = 1'd0;
-wire soc_litedramcore_bankmachine6_row_hit;
-reg soc_litedramcore_bankmachine6_row_open = 1'd0;
-reg soc_litedramcore_bankmachine6_row_close = 1'd0;
-reg soc_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
-wire soc_litedramcore_bankmachine6_twtpcon_valid;
-reg soc_litedramcore_bankmachine6_twtpcon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine6_twtpcon_count = 3'd0;
-wire soc_litedramcore_bankmachine6_trccon_valid;
-reg soc_litedramcore_bankmachine6_trccon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine6_trccon_count = 3'd0;
-wire soc_litedramcore_bankmachine6_trascon_valid;
-reg soc_litedramcore_bankmachine6_trascon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine6_trascon_count = 3'd0;
-wire soc_litedramcore_bankmachine7_req_valid;
-wire soc_litedramcore_bankmachine7_req_ready;
-wire soc_litedramcore_bankmachine7_req_we;
-wire [20:0] soc_litedramcore_bankmachine7_req_addr;
-wire soc_litedramcore_bankmachine7_req_lock;
-reg soc_litedramcore_bankmachine7_req_wdata_ready = 1'd0;
-reg soc_litedramcore_bankmachine7_req_rdata_valid = 1'd0;
-wire soc_litedramcore_bankmachine7_refresh_req;
-reg soc_litedramcore_bankmachine7_refresh_gnt = 1'd0;
-reg soc_litedramcore_bankmachine7_cmd_valid = 1'd0;
-reg soc_litedramcore_bankmachine7_cmd_ready = 1'd0;
-reg [13:0] soc_litedramcore_bankmachine7_cmd_payload_a = 14'd0;
-wire [2:0] soc_litedramcore_bankmachine7_cmd_payload_ba;
-reg soc_litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
-reg soc_litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
-reg soc_litedramcore_bankmachine7_cmd_payload_we = 1'd0;
-reg soc_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
-reg soc_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
-reg soc_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
-reg soc_litedramcore_bankmachine7_auto_precharge = 1'd0;
-wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
-wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
-reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
-reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
-wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
-wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
-wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
-wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
-wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
-wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
-wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we;
-wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
-wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re;
-wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
-wire [23:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
-wire [23:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-reg [4:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
-reg soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r;
-wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we;
-wire [23:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
-wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read;
-wire [3:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
-wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first;
-wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last;
-wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
-wire soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
-wire soc_litedramcore_bankmachine7_cmd_buffer_sink_valid;
-wire soc_litedramcore_bankmachine7_cmd_buffer_sink_ready;
-wire soc_litedramcore_bankmachine7_cmd_buffer_sink_first;
-wire soc_litedramcore_bankmachine7_cmd_buffer_sink_last;
-wire soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
-wire [20:0] soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
-reg soc_litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0;
-wire soc_litedramcore_bankmachine7_cmd_buffer_source_ready;
-reg soc_litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0;
-reg soc_litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0;
-reg soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] soc_litedramcore_bankmachine7_row = 14'd0;
-reg soc_litedramcore_bankmachine7_row_opened = 1'd0;
-wire soc_litedramcore_bankmachine7_row_hit;
-reg soc_litedramcore_bankmachine7_row_open = 1'd0;
-reg soc_litedramcore_bankmachine7_row_close = 1'd0;
-reg soc_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
-wire soc_litedramcore_bankmachine7_twtpcon_valid;
-reg soc_litedramcore_bankmachine7_twtpcon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine7_twtpcon_count = 3'd0;
-wire soc_litedramcore_bankmachine7_trccon_valid;
-reg soc_litedramcore_bankmachine7_trccon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine7_trccon_count = 3'd0;
-wire soc_litedramcore_bankmachine7_trascon_valid;
-reg soc_litedramcore_bankmachine7_trascon_ready = 1'd0;
-reg [2:0] soc_litedramcore_bankmachine7_trascon_count = 3'd0;
-wire soc_litedramcore_ras_allowed;
-wire soc_litedramcore_cas_allowed;
-reg soc_litedramcore_choose_cmd_want_reads = 1'd0;
-reg soc_litedramcore_choose_cmd_want_writes = 1'd0;
-reg soc_litedramcore_choose_cmd_want_cmds = 1'd0;
-reg soc_litedramcore_choose_cmd_want_activates = 1'd0;
-wire soc_litedramcore_choose_cmd_cmd_valid;
-reg soc_litedramcore_choose_cmd_cmd_ready = 1'd0;
-wire [13:0] soc_litedramcore_choose_cmd_cmd_payload_a;
-wire [2:0] soc_litedramcore_choose_cmd_cmd_payload_ba;
-reg soc_litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
-reg soc_litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
-reg soc_litedramcore_choose_cmd_cmd_payload_we = 1'd0;
-wire soc_litedramcore_choose_cmd_cmd_payload_is_cmd;
-wire soc_litedramcore_choose_cmd_cmd_payload_is_read;
-wire soc_litedramcore_choose_cmd_cmd_payload_is_write;
-reg [7:0] soc_litedramcore_choose_cmd_valids = 8'd0;
-wire [7:0] soc_litedramcore_choose_cmd_request;
-reg [2:0] soc_litedramcore_choose_cmd_grant = 3'd0;
-wire soc_litedramcore_choose_cmd_ce;
-reg soc_litedramcore_choose_req_want_reads = 1'd0;
-reg soc_litedramcore_choose_req_want_writes = 1'd0;
-reg soc_litedramcore_choose_req_want_cmds = 1'd0;
-reg soc_litedramcore_choose_req_want_activates = 1'd0;
-wire soc_litedramcore_choose_req_cmd_valid;
-reg soc_litedramcore_choose_req_cmd_ready = 1'd0;
-wire [13:0] soc_litedramcore_choose_req_cmd_payload_a;
-wire [2:0] soc_litedramcore_choose_req_cmd_payload_ba;
-reg soc_litedramcore_choose_req_cmd_payload_cas = 1'd0;
-reg soc_litedramcore_choose_req_cmd_payload_ras = 1'd0;
-reg soc_litedramcore_choose_req_cmd_payload_we = 1'd0;
-wire soc_litedramcore_choose_req_cmd_payload_is_cmd;
-wire soc_litedramcore_choose_req_cmd_payload_is_read;
-wire soc_litedramcore_choose_req_cmd_payload_is_write;
-reg [7:0] soc_litedramcore_choose_req_valids = 8'd0;
-wire [7:0] soc_litedramcore_choose_req_request;
-reg [2:0] soc_litedramcore_choose_req_grant = 3'd0;
-wire soc_litedramcore_choose_req_ce;
-reg [13:0] soc_litedramcore_nop_a = 14'd0;
-reg [2:0] soc_litedramcore_nop_ba = 3'd0;
-reg [1:0] soc_litedramcore_steerer_sel0 = 2'd0;
-reg [1:0] soc_litedramcore_steerer_sel1 = 2'd0;
-reg [1:0] soc_litedramcore_steerer_sel2 = 2'd0;
-reg [1:0] soc_litedramcore_steerer_sel3 = 2'd0;
-reg soc_litedramcore_steerer0 = 1'd1;
-reg soc_litedramcore_steerer1 = 1'd1;
-reg soc_litedramcore_steerer2 = 1'd1;
-reg soc_litedramcore_steerer3 = 1'd1;
-reg soc_litedramcore_steerer4 = 1'd1;
-reg soc_litedramcore_steerer5 = 1'd1;
-reg soc_litedramcore_steerer6 = 1'd1;
-reg soc_litedramcore_steerer7 = 1'd1;
-wire soc_litedramcore_trrdcon_valid;
-reg soc_litedramcore_trrdcon_ready = 1'd0;
-reg soc_litedramcore_trrdcon_count = 1'd0;
-wire soc_litedramcore_tfawcon_valid;
-reg soc_litedramcore_tfawcon_ready = 1'd1;
-wire [2:0] soc_litedramcore_tfawcon_count;
-reg [4:0] soc_litedramcore_tfawcon_window = 5'd0;
-wire soc_litedramcore_tccdcon_valid;
-reg soc_litedramcore_tccdcon_ready = 1'd0;
-reg soc_litedramcore_tccdcon_count = 1'd0;
-wire soc_litedramcore_twtrcon_valid;
-reg soc_litedramcore_twtrcon_ready = 1'd0;
-reg [2:0] soc_litedramcore_twtrcon_count = 3'd0;
-wire soc_litedramcore_read_available;
-wire soc_litedramcore_write_available;
-reg soc_litedramcore_en0 = 1'd0;
-wire soc_litedramcore_max_time0;
-reg [4:0] soc_litedramcore_time0 = 5'd0;
-reg soc_litedramcore_en1 = 1'd0;
-wire soc_litedramcore_max_time1;
-reg [3:0] soc_litedramcore_time1 = 4'd0;
-wire soc_litedramcore_go_to_refresh;
-reg soc_init_done_storage = 1'd0;
-reg soc_init_done_re = 1'd0;
-reg soc_init_error_storage = 1'd0;
-reg soc_init_error_re = 1'd0;
-wire [29:0] soc_wb_bus_adr;
-wire [31:0] soc_wb_bus_dat_w;
-wire [31:0] soc_wb_bus_dat_r;
-wire [3:0] soc_wb_bus_sel;
-wire soc_wb_bus_cyc;
-wire soc_wb_bus_stb;
-wire soc_wb_bus_ack;
-wire soc_wb_bus_we;
-wire [2:0] soc_wb_bus_cti;
-wire [1:0] soc_wb_bus_bte;
-wire soc_wb_bus_err;
-wire soc_user_enable;
-wire soc_user_port_cmd_valid;
-wire soc_user_port_cmd_ready;
-wire soc_user_port_cmd_payload_we;
-wire [23:0] soc_user_port_cmd_payload_addr;
-wire soc_user_port_wdata_valid;
-wire soc_user_port_wdata_ready;
-wire [127:0] soc_user_port_wdata_payload_data;
-wire [15:0] soc_user_port_wdata_payload_we;
-wire soc_user_port_rdata_valid;
-wire soc_user_port_rdata_ready;
-wire [127:0] soc_user_port_rdata_payload_data;
-reg [13:0] litedramcore_adr = 14'd0;
-reg litedramcore_we = 1'd0;
-reg [31:0] litedramcore_dat_w = 32'd0;
-wire [31:0] litedramcore_dat_r;
-wire [29:0] litedramcore_wishbone_adr;
-wire [31:0] litedramcore_wishbone_dat_w;
-reg [31:0] litedramcore_wishbone_dat_r = 32'd0;
-wire [3:0] litedramcore_wishbone_sel;
-wire litedramcore_wishbone_cyc;
-wire litedramcore_wishbone_stb;
-reg litedramcore_wishbone_ack = 1'd0;
-wire litedramcore_wishbone_we;
-wire [2:0] litedramcore_wishbone_cti;
-wire [1:0] litedramcore_wishbone_bte;
-reg litedramcore_wishbone_err = 1'd0;
-wire [13:0] interface0_bank_bus_adr;
-wire interface0_bank_bus_we;
-wire [31:0] interface0_bank_bus_dat_w;
-reg [31:0] interface0_bank_bus_dat_r = 32'd0;
-reg csrbank0_init_done0_re = 1'd0;
-wire csrbank0_init_done0_r;
-reg csrbank0_init_done0_we = 1'd0;
-wire csrbank0_init_done0_w;
-reg csrbank0_init_error0_re = 1'd0;
-wire csrbank0_init_error0_r;
-reg csrbank0_init_error0_we = 1'd0;
-wire csrbank0_init_error0_w;
-wire csrbank0_sel;
-wire [13:0] interface1_bank_bus_adr;
-wire interface1_bank_bus_we;
-wire [31:0] interface1_bank_bus_dat_w;
-reg [31:0] interface1_bank_bus_dat_r = 32'd0;
-reg csrbank1_dfii_control0_re = 1'd0;
-wire [3:0] csrbank1_dfii_control0_r;
-reg csrbank1_dfii_control0_we = 1'd0;
-wire [3:0] csrbank1_dfii_control0_w;
-reg csrbank1_dfii_pi0_command0_re = 1'd0;
-wire [5:0] csrbank1_dfii_pi0_command0_r;
-reg csrbank1_dfii_pi0_command0_we = 1'd0;
-wire [5:0] csrbank1_dfii_pi0_command0_w;
-reg csrbank1_dfii_pi0_address0_re = 1'd0;
-wire [13:0] csrbank1_dfii_pi0_address0_r;
-reg csrbank1_dfii_pi0_address0_we = 1'd0;
-wire [13:0] csrbank1_dfii_pi0_address0_w;
-reg csrbank1_dfii_pi0_baddress0_re = 1'd0;
-wire [2:0] csrbank1_dfii_pi0_baddress0_r;
-reg csrbank1_dfii_pi0_baddress0_we = 1'd0;
-wire [2:0] csrbank1_dfii_pi0_baddress0_w;
-reg csrbank1_dfii_pi0_wrdata0_re = 1'd0;
-wire [31:0] csrbank1_dfii_pi0_wrdata0_r;
-reg csrbank1_dfii_pi0_wrdata0_we = 1'd0;
-wire [31:0] csrbank1_dfii_pi0_wrdata0_w;
-reg csrbank1_dfii_pi0_rddata_re = 1'd0;
-wire [31:0] csrbank1_dfii_pi0_rddata_r;
-reg csrbank1_dfii_pi0_rddata_we = 1'd0;
-wire [31:0] csrbank1_dfii_pi0_rddata_w;
-reg csrbank1_dfii_pi1_command0_re = 1'd0;
-wire [5:0] csrbank1_dfii_pi1_command0_r;
-reg csrbank1_dfii_pi1_command0_we = 1'd0;
-wire [5:0] csrbank1_dfii_pi1_command0_w;
-reg csrbank1_dfii_pi1_address0_re = 1'd0;
-wire [13:0] csrbank1_dfii_pi1_address0_r;
-reg csrbank1_dfii_pi1_address0_we = 1'd0;
-wire [13:0] csrbank1_dfii_pi1_address0_w;
-reg csrbank1_dfii_pi1_baddress0_re = 1'd0;
-wire [2:0] csrbank1_dfii_pi1_baddress0_r;
-reg csrbank1_dfii_pi1_baddress0_we = 1'd0;
-wire [2:0] csrbank1_dfii_pi1_baddress0_w;
-reg csrbank1_dfii_pi1_wrdata0_re = 1'd0;
-wire [31:0] csrbank1_dfii_pi1_wrdata0_r;
-reg csrbank1_dfii_pi1_wrdata0_we = 1'd0;
-wire [31:0] csrbank1_dfii_pi1_wrdata0_w;
-reg csrbank1_dfii_pi1_rddata_re = 1'd0;
-wire [31:0] csrbank1_dfii_pi1_rddata_r;
-reg csrbank1_dfii_pi1_rddata_we = 1'd0;
-wire [31:0] csrbank1_dfii_pi1_rddata_w;
-reg csrbank1_dfii_pi2_command0_re = 1'd0;
-wire [5:0] csrbank1_dfii_pi2_command0_r;
-reg csrbank1_dfii_pi2_command0_we = 1'd0;
-wire [5:0] csrbank1_dfii_pi2_command0_w;
-reg csrbank1_dfii_pi2_address0_re = 1'd0;
-wire [13:0] csrbank1_dfii_pi2_address0_r;
-reg csrbank1_dfii_pi2_address0_we = 1'd0;
-wire [13:0] csrbank1_dfii_pi2_address0_w;
-reg csrbank1_dfii_pi2_baddress0_re = 1'd0;
-wire [2:0] csrbank1_dfii_pi2_baddress0_r;
-reg csrbank1_dfii_pi2_baddress0_we = 1'd0;
-wire [2:0] csrbank1_dfii_pi2_baddress0_w;
-reg csrbank1_dfii_pi2_wrdata0_re = 1'd0;
-wire [31:0] csrbank1_dfii_pi2_wrdata0_r;
-reg csrbank1_dfii_pi2_wrdata0_we = 1'd0;
-wire [31:0] csrbank1_dfii_pi2_wrdata0_w;
-reg csrbank1_dfii_pi2_rddata_re = 1'd0;
-wire [31:0] csrbank1_dfii_pi2_rddata_r;
-reg csrbank1_dfii_pi2_rddata_we = 1'd0;
-wire [31:0] csrbank1_dfii_pi2_rddata_w;
-reg csrbank1_dfii_pi3_command0_re = 1'd0;
-wire [5:0] csrbank1_dfii_pi3_command0_r;
-reg csrbank1_dfii_pi3_command0_we = 1'd0;
-wire [5:0] csrbank1_dfii_pi3_command0_w;
-reg csrbank1_dfii_pi3_address0_re = 1'd0;
-wire [13:0] csrbank1_dfii_pi3_address0_r;
-reg csrbank1_dfii_pi3_address0_we = 1'd0;
-wire [13:0] csrbank1_dfii_pi3_address0_w;
-reg csrbank1_dfii_pi3_baddress0_re = 1'd0;
-wire [2:0] csrbank1_dfii_pi3_baddress0_r;
-reg csrbank1_dfii_pi3_baddress0_we = 1'd0;
-wire [2:0] csrbank1_dfii_pi3_baddress0_w;
-reg csrbank1_dfii_pi3_wrdata0_re = 1'd0;
-wire [31:0] csrbank1_dfii_pi3_wrdata0_r;
-reg csrbank1_dfii_pi3_wrdata0_we = 1'd0;
-wire [31:0] csrbank1_dfii_pi3_wrdata0_w;
-reg csrbank1_dfii_pi3_rddata_re = 1'd0;
-wire [31:0] csrbank1_dfii_pi3_rddata_r;
-reg csrbank1_dfii_pi3_rddata_we = 1'd0;
-wire [31:0] csrbank1_dfii_pi3_rddata_w;
-wire csrbank1_sel;
-wire [13:0] csr_interconnect_adr;
-wire csr_interconnect_we;
-wire [31:0] csr_interconnect_dat_w;
-wire [31:0] csr_interconnect_dat_r;
-reg [1:0] litedramcore_refresher_state = 2'd0;
-reg [1:0] litedramcore_refresher_next_state = 2'd0;
-reg [3:0] litedramcore_bankmachine0_state = 4'd0;
-reg [3:0] litedramcore_bankmachine0_next_state = 4'd0;
-reg [3:0] litedramcore_bankmachine1_state = 4'd0;
-reg [3:0] litedramcore_bankmachine1_next_state = 4'd0;
-reg [3:0] litedramcore_bankmachine2_state = 4'd0;
-reg [3:0] litedramcore_bankmachine2_next_state = 4'd0;
-reg [3:0] litedramcore_bankmachine3_state = 4'd0;
-reg [3:0] litedramcore_bankmachine3_next_state = 4'd0;
-reg [3:0] litedramcore_bankmachine4_state = 4'd0;
-reg [3:0] litedramcore_bankmachine4_next_state = 4'd0;
-reg [3:0] litedramcore_bankmachine5_state = 4'd0;
-reg [3:0] litedramcore_bankmachine5_next_state = 4'd0;
-reg [3:0] litedramcore_bankmachine6_state = 4'd0;
-reg [3:0] litedramcore_bankmachine6_next_state = 4'd0;
-reg [3:0] litedramcore_bankmachine7_state = 4'd0;
-reg [3:0] litedramcore_bankmachine7_next_state = 4'd0;
-reg [3:0] litedramcore_multiplexer_state = 4'd0;
-reg [3:0] litedramcore_multiplexer_next_state = 4'd0;
-wire litedramcore_roundrobin0_request;
-wire litedramcore_roundrobin0_grant;
-wire litedramcore_roundrobin0_ce;
-wire litedramcore_roundrobin1_request;
-wire litedramcore_roundrobin1_grant;
-wire litedramcore_roundrobin1_ce;
-wire litedramcore_roundrobin2_request;
-wire litedramcore_roundrobin2_grant;
-wire litedramcore_roundrobin2_ce;
-wire litedramcore_roundrobin3_request;
-wire litedramcore_roundrobin3_grant;
-wire litedramcore_roundrobin3_ce;
-wire litedramcore_roundrobin4_request;
-wire litedramcore_roundrobin4_grant;
-wire litedramcore_roundrobin4_ce;
-wire litedramcore_roundrobin5_request;
-wire litedramcore_roundrobin5_grant;
-wire litedramcore_roundrobin5_ce;
-wire litedramcore_roundrobin6_request;
-wire litedramcore_roundrobin6_grant;
-wire litedramcore_roundrobin6_ce;
-wire litedramcore_roundrobin7_request;
-wire litedramcore_roundrobin7_grant;
-wire litedramcore_roundrobin7_ce;
-reg litedramcore_locked0 = 1'd0;
-reg litedramcore_locked1 = 1'd0;
-reg litedramcore_locked2 = 1'd0;
-reg litedramcore_locked3 = 1'd0;
-reg litedramcore_locked4 = 1'd0;
-reg litedramcore_locked5 = 1'd0;
-reg litedramcore_locked6 = 1'd0;
-reg litedramcore_locked7 = 1'd0;
-reg litedramcore_new_master_wdata_ready0 = 1'd0;
-reg litedramcore_new_master_wdata_ready1 = 1'd0;
-reg litedramcore_new_master_rdata_valid0 = 1'd0;
-reg litedramcore_new_master_rdata_valid1 = 1'd0;
-reg litedramcore_new_master_rdata_valid2 = 1'd0;
-reg litedramcore_new_master_rdata_valid3 = 1'd0;
-reg litedramcore_new_master_rdata_valid4 = 1'd0;
-reg litedramcore_new_master_rdata_valid5 = 1'd0;
-reg litedramcore_new_master_rdata_valid6 = 1'd0;
-reg litedramcore_new_master_rdata_valid7 = 1'd0;
-reg litedramcore_new_master_rdata_valid8 = 1'd0;
-reg [1:0] litedramcore_state = 2'd0;
-reg [1:0] litedramcore_next_state = 2'd0;
-reg [31:0] litedramcore_dat_w_next_value0 = 32'd0;
-reg litedramcore_dat_w_next_value_ce0 = 1'd0;
-reg [13:0] litedramcore_adr_next_value1 = 14'd0;
-reg litedramcore_adr_next_value_ce1 = 1'd0;
-reg litedramcore_we_next_value2 = 1'd0;
-reg litedramcore_we_next_value_ce2 = 1'd0;
-wire [24:0] slice_proxy0;
-wire [24:0] slice_proxy1;
-wire [24:0] slice_proxy2;
-wire [24:0] slice_proxy3;
-wire [24:0] slice_proxy4;
-wire [24:0] slice_proxy5;
-wire [24:0] slice_proxy6;
-wire [24:0] slice_proxy7;
-wire [24:0] slice_proxy8;
-wire [24:0] slice_proxy9;
-wire [24:0] slice_proxy10;
-wire [24:0] slice_proxy11;
-wire [24:0] slice_proxy12;
-wire [24:0] slice_proxy13;
-wire [24:0] slice_proxy14;
-wire [24:0] slice_proxy15;
-reg rhs_array_muxed0 = 1'd0;
-reg [13:0] rhs_array_muxed1 = 14'd0;
-reg [2:0] rhs_array_muxed2 = 3'd0;
-reg rhs_array_muxed3 = 1'd0;
-reg rhs_array_muxed4 = 1'd0;
-reg rhs_array_muxed5 = 1'd0;
-reg t_array_muxed0 = 1'd0;
-reg t_array_muxed1 = 1'd0;
-reg t_array_muxed2 = 1'd0;
-reg rhs_array_muxed6 = 1'd0;
-reg [13:0] rhs_array_muxed7 = 14'd0;
-reg [2:0] rhs_array_muxed8 = 3'd0;
-reg rhs_array_muxed9 = 1'd0;
-reg rhs_array_muxed10 = 1'd0;
-reg rhs_array_muxed11 = 1'd0;
-reg t_array_muxed3 = 1'd0;
-reg t_array_muxed4 = 1'd0;
-reg t_array_muxed5 = 1'd0;
-reg [20:0] rhs_array_muxed12 = 21'd0;
-reg rhs_array_muxed13 = 1'd0;
-reg rhs_array_muxed14 = 1'd0;
-reg [20:0] rhs_array_muxed15 = 21'd0;
-reg rhs_array_muxed16 = 1'd0;
-reg rhs_array_muxed17 = 1'd0;
-reg [20:0] rhs_array_muxed18 = 21'd0;
-reg rhs_array_muxed19 = 1'd0;
-reg rhs_array_muxed20 = 1'd0;
-reg [20:0] rhs_array_muxed21 = 21'd0;
-reg rhs_array_muxed22 = 1'd0;
-reg rhs_array_muxed23 = 1'd0;
-reg [20:0] rhs_array_muxed24 = 21'd0;
-reg rhs_array_muxed25 = 1'd0;
-reg rhs_array_muxed26 = 1'd0;
-reg [20:0] rhs_array_muxed27 = 21'd0;
-reg rhs_array_muxed28 = 1'd0;
-reg rhs_array_muxed29 = 1'd0;
-reg [20:0] rhs_array_muxed30 = 21'd0;
-reg rhs_array_muxed31 = 1'd0;
-reg rhs_array_muxed32 = 1'd0;
-reg [20:0] rhs_array_muxed33 = 21'd0;
-reg rhs_array_muxed34 = 1'd0;
-reg rhs_array_muxed35 = 1'd0;
-reg [2:0] array_muxed0 = 3'd0;
-reg [13:0] array_muxed1 = 14'd0;
-reg array_muxed2 = 1'd0;
-reg array_muxed3 = 1'd0;
-reg array_muxed4 = 1'd0;
-reg array_muxed5 = 1'd0;
-reg array_muxed6 = 1'd0;
-reg [2:0] array_muxed7 = 3'd0;
-reg [13:0] array_muxed8 = 14'd0;
-reg array_muxed9 = 1'd0;
-reg array_muxed10 = 1'd0;
-reg array_muxed11 = 1'd0;
-reg array_muxed12 = 1'd0;
-reg array_muxed13 = 1'd0;
-reg [2:0] array_muxed14 = 3'd0;
-reg [13:0] array_muxed15 = 14'd0;
-reg array_muxed16 = 1'd0;
-reg array_muxed17 = 1'd0;
-reg array_muxed18 = 1'd0;
-reg array_muxed19 = 1'd0;
-reg array_muxed20 = 1'd0;
-reg [2:0] array_muxed21 = 3'd0;
-reg [13:0] array_muxed22 = 14'd0;
-reg array_muxed23 = 1'd0;
-reg array_muxed24 = 1'd0;
-reg array_muxed25 = 1'd0;
-reg array_muxed26 = 1'd0;
-reg array_muxed27 = 1'd0;
+wire sys_clk;
+wire sys_rst;
+wire por_clk;
+reg soc_int_rst = 1'd1;
+wire [13:0] soc_ddrphy_dfi_p0_address;
+wire [2:0] soc_ddrphy_dfi_p0_bank;
+wire soc_ddrphy_dfi_p0_cas_n;
+wire soc_ddrphy_dfi_p0_cs_n;
+wire soc_ddrphy_dfi_p0_ras_n;
+wire soc_ddrphy_dfi_p0_we_n;
+wire soc_ddrphy_dfi_p0_cke;
+wire soc_ddrphy_dfi_p0_odt;
+wire soc_ddrphy_dfi_p0_reset_n;
+wire soc_ddrphy_dfi_p0_act_n;
+wire [31:0] soc_ddrphy_dfi_p0_wrdata;
+wire soc_ddrphy_dfi_p0_wrdata_en;
+wire [3:0] soc_ddrphy_dfi_p0_wrdata_mask;
+wire soc_ddrphy_dfi_p0_rddata_en;
+wire [31:0] soc_ddrphy_dfi_p0_rddata;
+wire soc_ddrphy_dfi_p0_rddata_valid;
+wire [13:0] soc_ddrphy_dfi_p1_address;
+wire [2:0] soc_ddrphy_dfi_p1_bank;
+wire soc_ddrphy_dfi_p1_cas_n;
+wire soc_ddrphy_dfi_p1_cs_n;
+wire soc_ddrphy_dfi_p1_ras_n;
+wire soc_ddrphy_dfi_p1_we_n;
+wire soc_ddrphy_dfi_p1_cke;
+wire soc_ddrphy_dfi_p1_odt;
+wire soc_ddrphy_dfi_p1_reset_n;
+wire soc_ddrphy_dfi_p1_act_n;
+wire [31:0] soc_ddrphy_dfi_p1_wrdata;
+wire soc_ddrphy_dfi_p1_wrdata_en;
+wire [3:0] soc_ddrphy_dfi_p1_wrdata_mask;
+wire soc_ddrphy_dfi_p1_rddata_en;
+wire [31:0] soc_ddrphy_dfi_p1_rddata;
+wire soc_ddrphy_dfi_p1_rddata_valid;
+wire [13:0] soc_ddrphy_dfi_p2_address;
+wire [2:0] soc_ddrphy_dfi_p2_bank;
+wire soc_ddrphy_dfi_p2_cas_n;
+wire soc_ddrphy_dfi_p2_cs_n;
+wire soc_ddrphy_dfi_p2_ras_n;
+wire soc_ddrphy_dfi_p2_we_n;
+wire soc_ddrphy_dfi_p2_cke;
+wire soc_ddrphy_dfi_p2_odt;
+wire soc_ddrphy_dfi_p2_reset_n;
+wire soc_ddrphy_dfi_p2_act_n;
+wire [31:0] soc_ddrphy_dfi_p2_wrdata;
+wire soc_ddrphy_dfi_p2_wrdata_en;
+wire [3:0] soc_ddrphy_dfi_p2_wrdata_mask;
+wire soc_ddrphy_dfi_p2_rddata_en;
+wire [31:0] soc_ddrphy_dfi_p2_rddata;
+wire soc_ddrphy_dfi_p2_rddata_valid;
+wire [13:0] soc_ddrphy_dfi_p3_address;
+wire [2:0] soc_ddrphy_dfi_p3_bank;
+wire soc_ddrphy_dfi_p3_cas_n;
+wire soc_ddrphy_dfi_p3_cs_n;
+wire soc_ddrphy_dfi_p3_ras_n;
+wire soc_ddrphy_dfi_p3_we_n;
+wire soc_ddrphy_dfi_p3_cke;
+wire soc_ddrphy_dfi_p3_odt;
+wire soc_ddrphy_dfi_p3_reset_n;
+wire soc_ddrphy_dfi_p3_act_n;
+wire [31:0] soc_ddrphy_dfi_p3_wrdata;
+wire soc_ddrphy_dfi_p3_wrdata_en;
+wire [3:0] soc_ddrphy_dfi_p3_wrdata_mask;
+wire soc_ddrphy_dfi_p3_rddata_en;
+wire [31:0] soc_ddrphy_dfi_p3_rddata;
+wire soc_ddrphy_dfi_p3_rddata_valid;
+reg soc_ddrphy_dfiphasemodel0_activate = 1'd0;
+reg soc_ddrphy_dfiphasemodel0_precharge = 1'd0;
+reg soc_ddrphy_dfiphasemodel0_write = 1'd0;
+reg soc_ddrphy_dfiphasemodel0_read = 1'd0;
+reg soc_ddrphy_dfiphasemodel1_activate = 1'd0;
+reg soc_ddrphy_dfiphasemodel1_precharge = 1'd0;
+reg soc_ddrphy_dfiphasemodel1_write = 1'd0;
+reg soc_ddrphy_dfiphasemodel1_read = 1'd0;
+reg soc_ddrphy_dfiphasemodel2_activate = 1'd0;
+reg soc_ddrphy_dfiphasemodel2_precharge = 1'd0;
+reg soc_ddrphy_dfiphasemodel2_write = 1'd0;
+reg soc_ddrphy_dfiphasemodel2_read = 1'd0;
+reg soc_ddrphy_dfiphasemodel3_activate = 1'd0;
+reg soc_ddrphy_dfiphasemodel3_precharge = 1'd0;
+reg soc_ddrphy_dfiphasemodel3_write = 1'd0;
+reg soc_ddrphy_dfiphasemodel3_read = 1'd0;
+reg soc_ddrphy_bankmodel0_activate = 1'd0;
+reg [13:0] soc_ddrphy_bankmodel0_activate_row = 14'd0;
+reg soc_ddrphy_bankmodel0_precharge = 1'd0;
+wire soc_ddrphy_bankmodel0_write;
+wire [9:0] soc_ddrphy_bankmodel0_write_col;
+wire [127:0] soc_ddrphy_bankmodel0_write_data;
+wire [15:0] soc_ddrphy_bankmodel0_write_mask;
+reg soc_ddrphy_bankmodel0_read = 1'd0;
+reg [9:0] soc_ddrphy_bankmodel0_read_col = 10'd0;
+reg [127:0] soc_ddrphy_bankmodel0_read_data = 128'd0;
+reg soc_ddrphy_bankmodel0_active = 1'd0;
+reg [13:0] soc_ddrphy_bankmodel0_row = 14'd0;
+reg [20:0] soc_ddrphy_bankmodel0_write_port_adr = 21'd0;
+wire [127:0] soc_ddrphy_bankmodel0_write_port_dat_r;
+reg [15:0] soc_ddrphy_bankmodel0_write_port_we = 16'd0;
+reg [127:0] soc_ddrphy_bankmodel0_write_port_dat_w = 128'd0;
+reg [20:0] soc_ddrphy_bankmodel0_read_port_adr = 21'd0;
+wire [127:0] soc_ddrphy_bankmodel0_read_port_dat_r;
+wire [20:0] soc_ddrphy_bankmodel0_wraddr;
+wire [20:0] soc_ddrphy_bankmodel0_rdaddr;
+reg soc_ddrphy_bankmodel1_activate = 1'd0;
+reg [13:0] soc_ddrphy_bankmodel1_activate_row = 14'd0;
+reg soc_ddrphy_bankmodel1_precharge = 1'd0;
+wire soc_ddrphy_bankmodel1_write;
+wire [9:0] soc_ddrphy_bankmodel1_write_col;
+wire [127:0] soc_ddrphy_bankmodel1_write_data;
+wire [15:0] soc_ddrphy_bankmodel1_write_mask;
+reg soc_ddrphy_bankmodel1_read = 1'd0;
+reg [9:0] soc_ddrphy_bankmodel1_read_col = 10'd0;
+reg [127:0] soc_ddrphy_bankmodel1_read_data = 128'd0;
+reg soc_ddrphy_bankmodel1_active = 1'd0;
+reg [13:0] soc_ddrphy_bankmodel1_row = 14'd0;
+reg [20:0] soc_ddrphy_bankmodel1_write_port_adr = 21'd0;
+wire [127:0] soc_ddrphy_bankmodel1_write_port_dat_r;
+reg [15:0] soc_ddrphy_bankmodel1_write_port_we = 16'd0;
+reg [127:0] soc_ddrphy_bankmodel1_write_port_dat_w = 128'd0;
+reg [20:0] soc_ddrphy_bankmodel1_read_port_adr = 21'd0;
+wire [127:0] soc_ddrphy_bankmodel1_read_port_dat_r;
+wire [20:0] soc_ddrphy_bankmodel1_wraddr;
+wire [20:0] soc_ddrphy_bankmodel1_rdaddr;
+reg soc_ddrphy_bankmodel2_activate = 1'd0;
+reg [13:0] soc_ddrphy_bankmodel2_activate_row = 14'd0;
+reg soc_ddrphy_bankmodel2_precharge = 1'd0;
+wire soc_ddrphy_bankmodel2_write;
+wire [9:0] soc_ddrphy_bankmodel2_write_col;
+wire [127:0] soc_ddrphy_bankmodel2_write_data;
+wire [15:0] soc_ddrphy_bankmodel2_write_mask;
+reg soc_ddrphy_bankmodel2_read = 1'd0;
+reg [9:0] soc_ddrphy_bankmodel2_read_col = 10'd0;
+reg [127:0] soc_ddrphy_bankmodel2_read_data = 128'd0;
+reg soc_ddrphy_bankmodel2_active = 1'd0;
+reg [13:0] soc_ddrphy_bankmodel2_row = 14'd0;
+reg [20:0] soc_ddrphy_bankmodel2_write_port_adr = 21'd0;
+wire [127:0] soc_ddrphy_bankmodel2_write_port_dat_r;
+reg [15:0] soc_ddrphy_bankmodel2_write_port_we = 16'd0;
+reg [127:0] soc_ddrphy_bankmodel2_write_port_dat_w = 128'd0;
+reg [20:0] soc_ddrphy_bankmodel2_read_port_adr = 21'd0;
+wire [127:0] soc_ddrphy_bankmodel2_read_port_dat_r;
+wire [20:0] soc_ddrphy_bankmodel2_wraddr;
+wire [20:0] soc_ddrphy_bankmodel2_rdaddr;
+reg soc_ddrphy_bankmodel3_activate = 1'd0;
+reg [13:0] soc_ddrphy_bankmodel3_activate_row = 14'd0;
+reg soc_ddrphy_bankmodel3_precharge = 1'd0;
+wire soc_ddrphy_bankmodel3_write;
+wire [9:0] soc_ddrphy_bankmodel3_write_col;
+wire [127:0] soc_ddrphy_bankmodel3_write_data;
+wire [15:0] soc_ddrphy_bankmodel3_write_mask;
+reg soc_ddrphy_bankmodel3_read = 1'd0;
+reg [9:0] soc_ddrphy_bankmodel3_read_col = 10'd0;
+reg [127:0] soc_ddrphy_bankmodel3_read_data = 128'd0;
+reg soc_ddrphy_bankmodel3_active = 1'd0;
+reg [13:0] soc_ddrphy_bankmodel3_row = 14'd0;
+reg [20:0] soc_ddrphy_bankmodel3_write_port_adr = 21'd0;
+wire [127:0] soc_ddrphy_bankmodel3_write_port_dat_r;
+reg [15:0] soc_ddrphy_bankmodel3_write_port_we = 16'd0;
+reg [127:0] soc_ddrphy_bankmodel3_write_port_dat_w = 128'd0;
+reg [20:0] soc_ddrphy_bankmodel3_read_port_adr = 21'd0;
+wire [127:0] soc_ddrphy_bankmodel3_read_port_dat_r;
+wire [20:0] soc_ddrphy_bankmodel3_wraddr;
+wire [20:0] soc_ddrphy_bankmodel3_rdaddr;
+reg soc_ddrphy_bankmodel4_activate = 1'd0;
+reg [13:0] soc_ddrphy_bankmodel4_activate_row = 14'd0;
+reg soc_ddrphy_bankmodel4_precharge = 1'd0;
+wire soc_ddrphy_bankmodel4_write;
+wire [9:0] soc_ddrphy_bankmodel4_write_col;
+wire [127:0] soc_ddrphy_bankmodel4_write_data;
+wire [15:0] soc_ddrphy_bankmodel4_write_mask;
+reg soc_ddrphy_bankmodel4_read = 1'd0;
+reg [9:0] soc_ddrphy_bankmodel4_read_col = 10'd0;
+reg [127:0] soc_ddrphy_bankmodel4_read_data = 128'd0;
+reg soc_ddrphy_bankmodel4_active = 1'd0;
+reg [13:0] soc_ddrphy_bankmodel4_row = 14'd0;
+reg [20:0] soc_ddrphy_bankmodel4_write_port_adr = 21'd0;
+wire [127:0] soc_ddrphy_bankmodel4_write_port_dat_r;
+reg [15:0] soc_ddrphy_bankmodel4_write_port_we = 16'd0;
+reg [127:0] soc_ddrphy_bankmodel4_write_port_dat_w = 128'd0;
+reg [20:0] soc_ddrphy_bankmodel4_read_port_adr = 21'd0;
+wire [127:0] soc_ddrphy_bankmodel4_read_port_dat_r;
+wire [20:0] soc_ddrphy_bankmodel4_wraddr;
+wire [20:0] soc_ddrphy_bankmodel4_rdaddr;
+reg soc_ddrphy_bankmodel5_activate = 1'd0;
+reg [13:0] soc_ddrphy_bankmodel5_activate_row = 14'd0;
+reg soc_ddrphy_bankmodel5_precharge = 1'd0;
+wire soc_ddrphy_bankmodel5_write;
+wire [9:0] soc_ddrphy_bankmodel5_write_col;
+wire [127:0] soc_ddrphy_bankmodel5_write_data;
+wire [15:0] soc_ddrphy_bankmodel5_write_mask;
+reg soc_ddrphy_bankmodel5_read = 1'd0;
+reg [9:0] soc_ddrphy_bankmodel5_read_col = 10'd0;
+reg [127:0] soc_ddrphy_bankmodel5_read_data = 128'd0;
+reg soc_ddrphy_bankmodel5_active = 1'd0;
+reg [13:0] soc_ddrphy_bankmodel5_row = 14'd0;
+reg [20:0] soc_ddrphy_bankmodel5_write_port_adr = 21'd0;
+wire [127:0] soc_ddrphy_bankmodel5_write_port_dat_r;
+reg [15:0] soc_ddrphy_bankmodel5_write_port_we = 16'd0;
+reg [127:0] soc_ddrphy_bankmodel5_write_port_dat_w = 128'd0;
+reg [20:0] soc_ddrphy_bankmodel5_read_port_adr = 21'd0;
+wire [127:0] soc_ddrphy_bankmodel5_read_port_dat_r;
+wire [20:0] soc_ddrphy_bankmodel5_wraddr;
+wire [20:0] soc_ddrphy_bankmodel5_rdaddr;
+reg soc_ddrphy_bankmodel6_activate = 1'd0;
+reg [13:0] soc_ddrphy_bankmodel6_activate_row = 14'd0;
+reg soc_ddrphy_bankmodel6_precharge = 1'd0;
+wire soc_ddrphy_bankmodel6_write;
+wire [9:0] soc_ddrphy_bankmodel6_write_col;
+wire [127:0] soc_ddrphy_bankmodel6_write_data;
+wire [15:0] soc_ddrphy_bankmodel6_write_mask;
+reg soc_ddrphy_bankmodel6_read = 1'd0;
+reg [9:0] soc_ddrphy_bankmodel6_read_col = 10'd0;
+reg [127:0] soc_ddrphy_bankmodel6_read_data = 128'd0;
+reg soc_ddrphy_bankmodel6_active = 1'd0;
+reg [13:0] soc_ddrphy_bankmodel6_row = 14'd0;
+reg [20:0] soc_ddrphy_bankmodel6_write_port_adr = 21'd0;
+wire [127:0] soc_ddrphy_bankmodel6_write_port_dat_r;
+reg [15:0] soc_ddrphy_bankmodel6_write_port_we = 16'd0;
+reg [127:0] soc_ddrphy_bankmodel6_write_port_dat_w = 128'd0;
+reg [20:0] soc_ddrphy_bankmodel6_read_port_adr = 21'd0;
+wire [127:0] soc_ddrphy_bankmodel6_read_port_dat_r;
+wire [20:0] soc_ddrphy_bankmodel6_wraddr;
+wire [20:0] soc_ddrphy_bankmodel6_rdaddr;
+reg soc_ddrphy_bankmodel7_activate = 1'd0;
+reg [13:0] soc_ddrphy_bankmodel7_activate_row = 14'd0;
+reg soc_ddrphy_bankmodel7_precharge = 1'd0;
+wire soc_ddrphy_bankmodel7_write;
+wire [9:0] soc_ddrphy_bankmodel7_write_col;
+wire [127:0] soc_ddrphy_bankmodel7_write_data;
+wire [15:0] soc_ddrphy_bankmodel7_write_mask;
+reg soc_ddrphy_bankmodel7_read = 1'd0;
+reg [9:0] soc_ddrphy_bankmodel7_read_col = 10'd0;
+reg [127:0] soc_ddrphy_bankmodel7_read_data = 128'd0;
+reg soc_ddrphy_bankmodel7_active = 1'd0;
+reg [13:0] soc_ddrphy_bankmodel7_row = 14'd0;
+reg [20:0] soc_ddrphy_bankmodel7_write_port_adr = 21'd0;
+wire [127:0] soc_ddrphy_bankmodel7_write_port_dat_r;
+reg [15:0] soc_ddrphy_bankmodel7_write_port_we = 16'd0;
+reg [127:0] soc_ddrphy_bankmodel7_write_port_dat_w = 128'd0;
+reg [20:0] soc_ddrphy_bankmodel7_read_port_adr = 21'd0;
+wire [127:0] soc_ddrphy_bankmodel7_read_port_dat_r;
+wire [20:0] soc_ddrphy_bankmodel7_wraddr;
+wire [20:0] soc_ddrphy_bankmodel7_rdaddr;
+reg [3:0] soc_ddrphy_activates0 = 4'd0;
+reg [3:0] soc_ddrphy_precharges0 = 4'd0;
+reg soc_ddrphy_bank_write0 = 1'd0;
+reg [9:0] soc_ddrphy_bank_write_col0 = 10'd0;
+reg [3:0] soc_ddrphy_writes0 = 4'd0;
+reg soc_ddrphy_new_bank_write0 = 1'd0;
+reg [9:0] soc_ddrphy_new_bank_write_col0 = 10'd0;
+reg [3:0] soc_ddrphy_reads0 = 4'd0;
+reg [3:0] soc_ddrphy_activates1 = 4'd0;
+reg [3:0] soc_ddrphy_precharges1 = 4'd0;
+reg soc_ddrphy_bank_write1 = 1'd0;
+reg [9:0] soc_ddrphy_bank_write_col1 = 10'd0;
+reg [3:0] soc_ddrphy_writes1 = 4'd0;
+reg soc_ddrphy_new_bank_write1 = 1'd0;
+reg [9:0] soc_ddrphy_new_bank_write_col1 = 10'd0;
+reg [3:0] soc_ddrphy_reads1 = 4'd0;
+reg [3:0] soc_ddrphy_activates2 = 4'd0;
+reg [3:0] soc_ddrphy_precharges2 = 4'd0;
+reg soc_ddrphy_bank_write2 = 1'd0;
+reg [9:0] soc_ddrphy_bank_write_col2 = 10'd0;
+reg [3:0] soc_ddrphy_writes2 = 4'd0;
+reg soc_ddrphy_new_bank_write2 = 1'd0;
+reg [9:0] soc_ddrphy_new_bank_write_col2 = 10'd0;
+reg [3:0] soc_ddrphy_reads2 = 4'd0;
+reg [3:0] soc_ddrphy_activates3 = 4'd0;
+reg [3:0] soc_ddrphy_precharges3 = 4'd0;
+reg soc_ddrphy_bank_write3 = 1'd0;
+reg [9:0] soc_ddrphy_bank_write_col3 = 10'd0;
+reg [3:0] soc_ddrphy_writes3 = 4'd0;
+reg soc_ddrphy_new_bank_write3 = 1'd0;
+reg [9:0] soc_ddrphy_new_bank_write_col3 = 10'd0;
+reg [3:0] soc_ddrphy_reads3 = 4'd0;
+reg [3:0] soc_ddrphy_activates4 = 4'd0;
+reg [3:0] soc_ddrphy_precharges4 = 4'd0;
+reg soc_ddrphy_bank_write4 = 1'd0;
+reg [9:0] soc_ddrphy_bank_write_col4 = 10'd0;
+reg [3:0] soc_ddrphy_writes4 = 4'd0;
+reg soc_ddrphy_new_bank_write4 = 1'd0;
+reg [9:0] soc_ddrphy_new_bank_write_col4 = 10'd0;
+reg [3:0] soc_ddrphy_reads4 = 4'd0;
+reg [3:0] soc_ddrphy_activates5 = 4'd0;
+reg [3:0] soc_ddrphy_precharges5 = 4'd0;
+reg soc_ddrphy_bank_write5 = 1'd0;
+reg [9:0] soc_ddrphy_bank_write_col5 = 10'd0;
+reg [3:0] soc_ddrphy_writes5 = 4'd0;
+reg soc_ddrphy_new_bank_write5 = 1'd0;
+reg [9:0] soc_ddrphy_new_bank_write_col5 = 10'd0;
+reg [3:0] soc_ddrphy_reads5 = 4'd0;
+reg [3:0] soc_ddrphy_activates6 = 4'd0;
+reg [3:0] soc_ddrphy_precharges6 = 4'd0;
+reg soc_ddrphy_bank_write6 = 1'd0;
+reg [9:0] soc_ddrphy_bank_write_col6 = 10'd0;
+reg [3:0] soc_ddrphy_writes6 = 4'd0;
+reg soc_ddrphy_new_bank_write6 = 1'd0;
+reg [9:0] soc_ddrphy_new_bank_write_col6 = 10'd0;
+reg [3:0] soc_ddrphy_reads6 = 4'd0;
+reg [3:0] soc_ddrphy_activates7 = 4'd0;
+reg [3:0] soc_ddrphy_precharges7 = 4'd0;
+reg soc_ddrphy_bank_write7 = 1'd0;
+reg [9:0] soc_ddrphy_bank_write_col7 = 10'd0;
+reg [3:0] soc_ddrphy_writes7 = 4'd0;
+reg soc_ddrphy_new_bank_write7 = 1'd0;
+reg [9:0] soc_ddrphy_new_bank_write_col7 = 10'd0;
+reg [3:0] soc_ddrphy_reads7 = 4'd0;
+wire soc_ddrphy_banks_read;
+wire [127:0] soc_ddrphy_banks_read_data;
+reg soc_ddrphy_new_banks_read0 = 1'd0;
+reg [127:0] soc_ddrphy_new_banks_read_data0 = 128'd0;
+reg soc_ddrphy_new_banks_read1 = 1'd0;
+reg [127:0] soc_ddrphy_new_banks_read_data1 = 128'd0;
+reg soc_ddrphy_new_banks_read2 = 1'd0;
+reg [127:0] soc_ddrphy_new_banks_read_data2 = 128'd0;
+reg soc_ddrphy_new_banks_read3 = 1'd0;
+reg [127:0] soc_ddrphy_new_banks_read_data3 = 128'd0;
+reg soc_ddrphy_new_banks_read4 = 1'd0;
+reg [127:0] soc_ddrphy_new_banks_read_data4 = 128'd0;
+reg soc_ddrphy_new_banks_read5 = 1'd0;
+reg [127:0] soc_ddrphy_new_banks_read_data5 = 128'd0;
+reg soc_ddrphy_new_banks_read6 = 1'd0;
+reg [127:0] soc_ddrphy_new_banks_read_data6 = 128'd0;
+reg soc_ddrphy_new_banks_read7 = 1'd0;
+reg [127:0] soc_ddrphy_new_banks_read_data7 = 128'd0;
+wire [13:0] soc_litedramcore_slave_p0_address;
+wire [2:0] soc_litedramcore_slave_p0_bank;
+wire soc_litedramcore_slave_p0_cas_n;
+wire soc_litedramcore_slave_p0_cs_n;
+wire soc_litedramcore_slave_p0_ras_n;
+wire soc_litedramcore_slave_p0_we_n;
+wire soc_litedramcore_slave_p0_cke;
+wire soc_litedramcore_slave_p0_odt;
+wire soc_litedramcore_slave_p0_reset_n;
+wire soc_litedramcore_slave_p0_act_n;
+wire [31:0] soc_litedramcore_slave_p0_wrdata;
+wire soc_litedramcore_slave_p0_wrdata_en;
+wire [3:0] soc_litedramcore_slave_p0_wrdata_mask;
+wire soc_litedramcore_slave_p0_rddata_en;
+reg [31:0] soc_litedramcore_slave_p0_rddata = 32'd0;
+reg soc_litedramcore_slave_p0_rddata_valid = 1'd0;
+wire [13:0] soc_litedramcore_slave_p1_address;
+wire [2:0] soc_litedramcore_slave_p1_bank;
+wire soc_litedramcore_slave_p1_cas_n;
+wire soc_litedramcore_slave_p1_cs_n;
+wire soc_litedramcore_slave_p1_ras_n;
+wire soc_litedramcore_slave_p1_we_n;
+wire soc_litedramcore_slave_p1_cke;
+wire soc_litedramcore_slave_p1_odt;
+wire soc_litedramcore_slave_p1_reset_n;
+wire soc_litedramcore_slave_p1_act_n;
+wire [31:0] soc_litedramcore_slave_p1_wrdata;
+wire soc_litedramcore_slave_p1_wrdata_en;
+wire [3:0] soc_litedramcore_slave_p1_wrdata_mask;
+wire soc_litedramcore_slave_p1_rddata_en;
+reg [31:0] soc_litedramcore_slave_p1_rddata = 32'd0;
+reg soc_litedramcore_slave_p1_rddata_valid = 1'd0;
+wire [13:0] soc_litedramcore_slave_p2_address;
+wire [2:0] soc_litedramcore_slave_p2_bank;
+wire soc_litedramcore_slave_p2_cas_n;
+wire soc_litedramcore_slave_p2_cs_n;
+wire soc_litedramcore_slave_p2_ras_n;
+wire soc_litedramcore_slave_p2_we_n;
+wire soc_litedramcore_slave_p2_cke;
+wire soc_litedramcore_slave_p2_odt;
+wire soc_litedramcore_slave_p2_reset_n;
+wire soc_litedramcore_slave_p2_act_n;
+wire [31:0] soc_litedramcore_slave_p2_wrdata;
+wire soc_litedramcore_slave_p2_wrdata_en;
+wire [3:0] soc_litedramcore_slave_p2_wrdata_mask;
+wire soc_litedramcore_slave_p2_rddata_en;
+reg [31:0] soc_litedramcore_slave_p2_rddata = 32'd0;
+reg soc_litedramcore_slave_p2_rddata_valid = 1'd0;
+wire [13:0] soc_litedramcore_slave_p3_address;
+wire [2:0] soc_litedramcore_slave_p3_bank;
+wire soc_litedramcore_slave_p3_cas_n;
+wire soc_litedramcore_slave_p3_cs_n;
+wire soc_litedramcore_slave_p3_ras_n;
+wire soc_litedramcore_slave_p3_we_n;
+wire soc_litedramcore_slave_p3_cke;
+wire soc_litedramcore_slave_p3_odt;
+wire soc_litedramcore_slave_p3_reset_n;
+wire soc_litedramcore_slave_p3_act_n;
+wire [31:0] soc_litedramcore_slave_p3_wrdata;
+wire soc_litedramcore_slave_p3_wrdata_en;
+wire [3:0] soc_litedramcore_slave_p3_wrdata_mask;
+wire soc_litedramcore_slave_p3_rddata_en;
+reg [31:0] soc_litedramcore_slave_p3_rddata = 32'd0;
+reg soc_litedramcore_slave_p3_rddata_valid = 1'd0;
+reg [13:0] soc_litedramcore_master_p0_address = 14'd0;
+reg [2:0] soc_litedramcore_master_p0_bank = 3'd0;
+reg soc_litedramcore_master_p0_cas_n = 1'd1;
+reg soc_litedramcore_master_p0_cs_n = 1'd1;
+reg soc_litedramcore_master_p0_ras_n = 1'd1;
+reg soc_litedramcore_master_p0_we_n = 1'd1;
+reg soc_litedramcore_master_p0_cke = 1'd0;
+reg soc_litedramcore_master_p0_odt = 1'd0;
+reg soc_litedramcore_master_p0_reset_n = 1'd0;
+reg soc_litedramcore_master_p0_act_n = 1'd1;
+reg [31:0] soc_litedramcore_master_p0_wrdata = 32'd0;
+reg soc_litedramcore_master_p0_wrdata_en = 1'd0;
+reg [3:0] soc_litedramcore_master_p0_wrdata_mask = 4'd0;
+reg soc_litedramcore_master_p0_rddata_en = 1'd0;
+wire [31:0] soc_litedramcore_master_p0_rddata;
+wire soc_litedramcore_master_p0_rddata_valid;
+reg [13:0] soc_litedramcore_master_p1_address = 14'd0;
+reg [2:0] soc_litedramcore_master_p1_bank = 3'd0;
+reg soc_litedramcore_master_p1_cas_n = 1'd1;
+reg soc_litedramcore_master_p1_cs_n = 1'd1;
+reg soc_litedramcore_master_p1_ras_n = 1'd1;
+reg soc_litedramcore_master_p1_we_n = 1'd1;
+reg soc_litedramcore_master_p1_cke = 1'd0;
+reg soc_litedramcore_master_p1_odt = 1'd0;
+reg soc_litedramcore_master_p1_reset_n = 1'd0;
+reg soc_litedramcore_master_p1_act_n = 1'd1;
+reg [31:0] soc_litedramcore_master_p1_wrdata = 32'd0;
+reg soc_litedramcore_master_p1_wrdata_en = 1'd0;
+reg [3:0] soc_litedramcore_master_p1_wrdata_mask = 4'd0;
+reg soc_litedramcore_master_p1_rddata_en = 1'd0;
+wire [31:0] soc_litedramcore_master_p1_rddata;
+wire soc_litedramcore_master_p1_rddata_valid;
+reg [13:0] soc_litedramcore_master_p2_address = 14'd0;
+reg [2:0] soc_litedramcore_master_p2_bank = 3'd0;
+reg soc_litedramcore_master_p2_cas_n = 1'd1;
+reg soc_litedramcore_master_p2_cs_n = 1'd1;
+reg soc_litedramcore_master_p2_ras_n = 1'd1;
+reg soc_litedramcore_master_p2_we_n = 1'd1;
+reg soc_litedramcore_master_p2_cke = 1'd0;
+reg soc_litedramcore_master_p2_odt = 1'd0;
+reg soc_litedramcore_master_p2_reset_n = 1'd0;
+reg soc_litedramcore_master_p2_act_n = 1'd1;
+reg [31:0] soc_litedramcore_master_p2_wrdata = 32'd0;
+reg soc_litedramcore_master_p2_wrdata_en = 1'd0;
+reg [3:0] soc_litedramcore_master_p2_wrdata_mask = 4'd0;
+reg soc_litedramcore_master_p2_rddata_en = 1'd0;
+wire [31:0] soc_litedramcore_master_p2_rddata;
+wire soc_litedramcore_master_p2_rddata_valid;
+reg [13:0] soc_litedramcore_master_p3_address = 14'd0;
+reg [2:0] soc_litedramcore_master_p3_bank = 3'd0;
+reg soc_litedramcore_master_p3_cas_n = 1'd1;
+reg soc_litedramcore_master_p3_cs_n = 1'd1;
+reg soc_litedramcore_master_p3_ras_n = 1'd1;
+reg soc_litedramcore_master_p3_we_n = 1'd1;
+reg soc_litedramcore_master_p3_cke = 1'd0;
+reg soc_litedramcore_master_p3_odt = 1'd0;
+reg soc_litedramcore_master_p3_reset_n = 1'd0;
+reg soc_litedramcore_master_p3_act_n = 1'd1;
+reg [31:0] soc_litedramcore_master_p3_wrdata = 32'd0;
+reg soc_litedramcore_master_p3_wrdata_en = 1'd0;
+reg [3:0] soc_litedramcore_master_p3_wrdata_mask = 4'd0;
+reg soc_litedramcore_master_p3_rddata_en = 1'd0;
+wire [31:0] soc_litedramcore_master_p3_rddata;
+wire soc_litedramcore_master_p3_rddata_valid;
+wire [13:0] soc_litedramcore_csr_dfi_p0_address;
+wire [2:0] soc_litedramcore_csr_dfi_p0_bank;
+reg soc_litedramcore_csr_dfi_p0_cas_n = 1'd1;
+reg soc_litedramcore_csr_dfi_p0_cs_n = 1'd1;
+reg soc_litedramcore_csr_dfi_p0_ras_n = 1'd1;
+reg soc_litedramcore_csr_dfi_p0_we_n = 1'd1;
+wire soc_litedramcore_csr_dfi_p0_cke;
+wire soc_litedramcore_csr_dfi_p0_odt;
+wire soc_litedramcore_csr_dfi_p0_reset_n;
+reg soc_litedramcore_csr_dfi_p0_act_n = 1'd1;
+wire [31:0] soc_litedramcore_csr_dfi_p0_wrdata;
+wire soc_litedramcore_csr_dfi_p0_wrdata_en;
+wire [3:0] soc_litedramcore_csr_dfi_p0_wrdata_mask;
+wire soc_litedramcore_csr_dfi_p0_rddata_en;
+reg [31:0] soc_litedramcore_csr_dfi_p0_rddata = 32'd0;
+reg soc_litedramcore_csr_dfi_p0_rddata_valid = 1'd0;
+wire [13:0] soc_litedramcore_csr_dfi_p1_address;
+wire [2:0] soc_litedramcore_csr_dfi_p1_bank;
+reg soc_litedramcore_csr_dfi_p1_cas_n = 1'd1;
+reg soc_litedramcore_csr_dfi_p1_cs_n = 1'd1;
+reg soc_litedramcore_csr_dfi_p1_ras_n = 1'd1;
+reg soc_litedramcore_csr_dfi_p1_we_n = 1'd1;
+wire soc_litedramcore_csr_dfi_p1_cke;
+wire soc_litedramcore_csr_dfi_p1_odt;
+wire soc_litedramcore_csr_dfi_p1_reset_n;
+reg soc_litedramcore_csr_dfi_p1_act_n = 1'd1;
+wire [31:0] soc_litedramcore_csr_dfi_p1_wrdata;
+wire soc_litedramcore_csr_dfi_p1_wrdata_en;
+wire [3:0] soc_litedramcore_csr_dfi_p1_wrdata_mask;
+wire soc_litedramcore_csr_dfi_p1_rddata_en;
+reg [31:0] soc_litedramcore_csr_dfi_p1_rddata = 32'd0;
+reg soc_litedramcore_csr_dfi_p1_rddata_valid = 1'd0;
+wire [13:0] soc_litedramcore_csr_dfi_p2_address;
+wire [2:0] soc_litedramcore_csr_dfi_p2_bank;
+reg soc_litedramcore_csr_dfi_p2_cas_n = 1'd1;
+reg soc_litedramcore_csr_dfi_p2_cs_n = 1'd1;
+reg soc_litedramcore_csr_dfi_p2_ras_n = 1'd1;
+reg soc_litedramcore_csr_dfi_p2_we_n = 1'd1;
+wire soc_litedramcore_csr_dfi_p2_cke;
+wire soc_litedramcore_csr_dfi_p2_odt;
+wire soc_litedramcore_csr_dfi_p2_reset_n;
+reg soc_litedramcore_csr_dfi_p2_act_n = 1'd1;
+wire [31:0] soc_litedramcore_csr_dfi_p2_wrdata;
+wire soc_litedramcore_csr_dfi_p2_wrdata_en;
+wire [3:0] soc_litedramcore_csr_dfi_p2_wrdata_mask;
+wire soc_litedramcore_csr_dfi_p2_rddata_en;
+reg [31:0] soc_litedramcore_csr_dfi_p2_rddata = 32'd0;
+reg soc_litedramcore_csr_dfi_p2_rddata_valid = 1'd0;
+wire [13:0] soc_litedramcore_csr_dfi_p3_address;
+wire [2:0] soc_litedramcore_csr_dfi_p3_bank;
+reg soc_litedramcore_csr_dfi_p3_cas_n = 1'd1;
+reg soc_litedramcore_csr_dfi_p3_cs_n = 1'd1;
+reg soc_litedramcore_csr_dfi_p3_ras_n = 1'd1;
+reg soc_litedramcore_csr_dfi_p3_we_n = 1'd1;
+wire soc_litedramcore_csr_dfi_p3_cke;
+wire soc_litedramcore_csr_dfi_p3_odt;
+wire soc_litedramcore_csr_dfi_p3_reset_n;
+reg soc_litedramcore_csr_dfi_p3_act_n = 1'd1;
+wire [31:0] soc_litedramcore_csr_dfi_p3_wrdata;
+wire soc_litedramcore_csr_dfi_p3_wrdata_en;
+wire [3:0] soc_litedramcore_csr_dfi_p3_wrdata_mask;
+wire soc_litedramcore_csr_dfi_p3_rddata_en;
+reg [31:0] soc_litedramcore_csr_dfi_p3_rddata = 32'd0;
+reg soc_litedramcore_csr_dfi_p3_rddata_valid = 1'd0;
+reg [13:0] soc_litedramcore_ext_dfi_p0_address = 14'd0;
+reg [2:0] soc_litedramcore_ext_dfi_p0_bank = 3'd0;
+reg soc_litedramcore_ext_dfi_p0_cas_n = 1'd1;
+reg soc_litedramcore_ext_dfi_p0_cs_n = 1'd1;
+reg soc_litedramcore_ext_dfi_p0_ras_n = 1'd1;
+reg soc_litedramcore_ext_dfi_p0_we_n = 1'd1;
+reg soc_litedramcore_ext_dfi_p0_cke = 1'd0;
+reg soc_litedramcore_ext_dfi_p0_odt = 1'd0;
+reg soc_litedramcore_ext_dfi_p0_reset_n = 1'd0;
+reg soc_litedramcore_ext_dfi_p0_act_n = 1'd1;
+reg [31:0] soc_litedramcore_ext_dfi_p0_wrdata = 32'd0;
+reg soc_litedramcore_ext_dfi_p0_wrdata_en = 1'd0;
+reg [3:0] soc_litedramcore_ext_dfi_p0_wrdata_mask = 4'd0;
+reg soc_litedramcore_ext_dfi_p0_rddata_en = 1'd0;
+reg [31:0] soc_litedramcore_ext_dfi_p0_rddata = 32'd0;
+reg soc_litedramcore_ext_dfi_p0_rddata_valid = 1'd0;
+reg [13:0] soc_litedramcore_ext_dfi_p1_address = 14'd0;
+reg [2:0] soc_litedramcore_ext_dfi_p1_bank = 3'd0;
+reg soc_litedramcore_ext_dfi_p1_cas_n = 1'd1;
+reg soc_litedramcore_ext_dfi_p1_cs_n = 1'd1;
+reg soc_litedramcore_ext_dfi_p1_ras_n = 1'd1;
+reg soc_litedramcore_ext_dfi_p1_we_n = 1'd1;
+reg soc_litedramcore_ext_dfi_p1_cke = 1'd0;
+reg soc_litedramcore_ext_dfi_p1_odt = 1'd0;
+reg soc_litedramcore_ext_dfi_p1_reset_n = 1'd0;
+reg soc_litedramcore_ext_dfi_p1_act_n = 1'd1;
+reg [31:0] soc_litedramcore_ext_dfi_p1_wrdata = 32'd0;
+reg soc_litedramcore_ext_dfi_p1_wrdata_en = 1'd0;
+reg [3:0] soc_litedramcore_ext_dfi_p1_wrdata_mask = 4'd0;
+reg soc_litedramcore_ext_dfi_p1_rddata_en = 1'd0;
+reg [31:0] soc_litedramcore_ext_dfi_p1_rddata = 32'd0;
+reg soc_litedramcore_ext_dfi_p1_rddata_valid = 1'd0;
+reg [13:0] soc_litedramcore_ext_dfi_p2_address = 14'd0;
+reg [2:0] soc_litedramcore_ext_dfi_p2_bank = 3'd0;
+reg soc_litedramcore_ext_dfi_p2_cas_n = 1'd1;
+reg soc_litedramcore_ext_dfi_p2_cs_n = 1'd1;
+reg soc_litedramcore_ext_dfi_p2_ras_n = 1'd1;
+reg soc_litedramcore_ext_dfi_p2_we_n = 1'd1;
+reg soc_litedramcore_ext_dfi_p2_cke = 1'd0;
+reg soc_litedramcore_ext_dfi_p2_odt = 1'd0;
+reg soc_litedramcore_ext_dfi_p2_reset_n = 1'd0;
+reg soc_litedramcore_ext_dfi_p2_act_n = 1'd1;
+reg [31:0] soc_litedramcore_ext_dfi_p2_wrdata = 32'd0;
+reg soc_litedramcore_ext_dfi_p2_wrdata_en = 1'd0;
+reg [3:0] soc_litedramcore_ext_dfi_p2_wrdata_mask = 4'd0;
+reg soc_litedramcore_ext_dfi_p2_rddata_en = 1'd0;
+reg [31:0] soc_litedramcore_ext_dfi_p2_rddata = 32'd0;
+reg soc_litedramcore_ext_dfi_p2_rddata_valid = 1'd0;
+reg [13:0] soc_litedramcore_ext_dfi_p3_address = 14'd0;
+reg [2:0] soc_litedramcore_ext_dfi_p3_bank = 3'd0;
+reg soc_litedramcore_ext_dfi_p3_cas_n = 1'd1;
+reg soc_litedramcore_ext_dfi_p3_cs_n = 1'd1;
+reg soc_litedramcore_ext_dfi_p3_ras_n = 1'd1;
+reg soc_litedramcore_ext_dfi_p3_we_n = 1'd1;
+reg soc_litedramcore_ext_dfi_p3_cke = 1'd0;
+reg soc_litedramcore_ext_dfi_p3_odt = 1'd0;
+reg soc_litedramcore_ext_dfi_p3_reset_n = 1'd0;
+reg soc_litedramcore_ext_dfi_p3_act_n = 1'd1;
+reg [31:0] soc_litedramcore_ext_dfi_p3_wrdata = 32'd0;
+reg soc_litedramcore_ext_dfi_p3_wrdata_en = 1'd0;
+reg [3:0] soc_litedramcore_ext_dfi_p3_wrdata_mask = 4'd0;
+reg soc_litedramcore_ext_dfi_p3_rddata_en = 1'd0;
+reg [31:0] soc_litedramcore_ext_dfi_p3_rddata = 32'd0;
+reg soc_litedramcore_ext_dfi_p3_rddata_valid = 1'd0;
+reg soc_litedramcore_ext_dfi_sel = 1'd0;
+wire soc_litedramcore_sel;
+wire soc_litedramcore_cke;
+wire soc_litedramcore_odt;
+wire soc_litedramcore_reset_n;
+reg [3:0] soc_litedramcore_storage = 4'd1;
+reg soc_litedramcore_re = 1'd0;
+wire soc_litedramcore_phaseinjector0_csrfield_cs;
+wire soc_litedramcore_phaseinjector0_csrfield_we;
+wire soc_litedramcore_phaseinjector0_csrfield_cas;
+wire soc_litedramcore_phaseinjector0_csrfield_ras;
+wire soc_litedramcore_phaseinjector0_csrfield_wren;
+wire soc_litedramcore_phaseinjector0_csrfield_rden;
+reg [5:0] soc_litedramcore_phaseinjector0_command_storage = 6'd0;
+reg soc_litedramcore_phaseinjector0_command_re = 1'd0;
+reg soc_litedramcore_phaseinjector0_command_issue_re = 1'd0;
+wire soc_litedramcore_phaseinjector0_command_issue_r;
+reg soc_litedramcore_phaseinjector0_command_issue_we = 1'd0;
+reg soc_litedramcore_phaseinjector0_command_issue_w = 1'd0;
+reg [13:0] soc_litedramcore_phaseinjector0_address_storage = 14'd0;
+reg soc_litedramcore_phaseinjector0_address_re = 1'd0;
+reg [2:0] soc_litedramcore_phaseinjector0_baddress_storage = 3'd0;
+reg soc_litedramcore_phaseinjector0_baddress_re = 1'd0;
+reg [31:0] soc_litedramcore_phaseinjector0_wrdata_storage = 32'd0;
+reg soc_litedramcore_phaseinjector0_wrdata_re = 1'd0;
+reg [31:0] soc_litedramcore_phaseinjector0_rddata_status = 32'd0;
+wire soc_litedramcore_phaseinjector0_rddata_we;
+reg soc_litedramcore_phaseinjector0_rddata_re = 1'd0;
+wire soc_litedramcore_phaseinjector1_csrfield_cs;
+wire soc_litedramcore_phaseinjector1_csrfield_we;
+wire soc_litedramcore_phaseinjector1_csrfield_cas;
+wire soc_litedramcore_phaseinjector1_csrfield_ras;
+wire soc_litedramcore_phaseinjector1_csrfield_wren;
+wire soc_litedramcore_phaseinjector1_csrfield_rden;
+reg [5:0] soc_litedramcore_phaseinjector1_command_storage = 6'd0;
+reg soc_litedramcore_phaseinjector1_command_re = 1'd0;
+reg soc_litedramcore_phaseinjector1_command_issue_re = 1'd0;
+wire soc_litedramcore_phaseinjector1_command_issue_r;
+reg soc_litedramcore_phaseinjector1_command_issue_we = 1'd0;
+reg soc_litedramcore_phaseinjector1_command_issue_w = 1'd0;
+reg [13:0] soc_litedramcore_phaseinjector1_address_storage = 14'd0;
+reg soc_litedramcore_phaseinjector1_address_re = 1'd0;
+reg [2:0] soc_litedramcore_phaseinjector1_baddress_storage = 3'd0;
+reg soc_litedramcore_phaseinjector1_baddress_re = 1'd0;
+reg [31:0] soc_litedramcore_phaseinjector1_wrdata_storage = 32'd0;
+reg soc_litedramcore_phaseinjector1_wrdata_re = 1'd0;
+reg [31:0] soc_litedramcore_phaseinjector1_rddata_status = 32'd0;
+wire soc_litedramcore_phaseinjector1_rddata_we;
+reg soc_litedramcore_phaseinjector1_rddata_re = 1'd0;
+wire soc_litedramcore_phaseinjector2_csrfield_cs;
+wire soc_litedramcore_phaseinjector2_csrfield_we;
+wire soc_litedramcore_phaseinjector2_csrfield_cas;
+wire soc_litedramcore_phaseinjector2_csrfield_ras;
+wire soc_litedramcore_phaseinjector2_csrfield_wren;
+wire soc_litedramcore_phaseinjector2_csrfield_rden;
+reg [5:0] soc_litedramcore_phaseinjector2_command_storage = 6'd0;
+reg soc_litedramcore_phaseinjector2_command_re = 1'd0;
+reg soc_litedramcore_phaseinjector2_command_issue_re = 1'd0;
+wire soc_litedramcore_phaseinjector2_command_issue_r;
+reg soc_litedramcore_phaseinjector2_command_issue_we = 1'd0;
+reg soc_litedramcore_phaseinjector2_command_issue_w = 1'd0;
+reg [13:0] soc_litedramcore_phaseinjector2_address_storage = 14'd0;
+reg soc_litedramcore_phaseinjector2_address_re = 1'd0;
+reg [2:0] soc_litedramcore_phaseinjector2_baddress_storage = 3'd0;
+reg soc_litedramcore_phaseinjector2_baddress_re = 1'd0;
+reg [31:0] soc_litedramcore_phaseinjector2_wrdata_storage = 32'd0;
+reg soc_litedramcore_phaseinjector2_wrdata_re = 1'd0;
+reg [31:0] soc_litedramcore_phaseinjector2_rddata_status = 32'd0;
+wire soc_litedramcore_phaseinjector2_rddata_we;
+reg soc_litedramcore_phaseinjector2_rddata_re = 1'd0;
+wire soc_litedramcore_phaseinjector3_csrfield_cs;
+wire soc_litedramcore_phaseinjector3_csrfield_we;
+wire soc_litedramcore_phaseinjector3_csrfield_cas;
+wire soc_litedramcore_phaseinjector3_csrfield_ras;
+wire soc_litedramcore_phaseinjector3_csrfield_wren;
+wire soc_litedramcore_phaseinjector3_csrfield_rden;
+reg [5:0] soc_litedramcore_phaseinjector3_command_storage = 6'd0;
+reg soc_litedramcore_phaseinjector3_command_re = 1'd0;
+reg soc_litedramcore_phaseinjector3_command_issue_re = 1'd0;
+wire soc_litedramcore_phaseinjector3_command_issue_r;
+reg soc_litedramcore_phaseinjector3_command_issue_we = 1'd0;
+reg soc_litedramcore_phaseinjector3_command_issue_w = 1'd0;
+reg [13:0] soc_litedramcore_phaseinjector3_address_storage = 14'd0;
+reg soc_litedramcore_phaseinjector3_address_re = 1'd0;
+reg [2:0] soc_litedramcore_phaseinjector3_baddress_storage = 3'd0;
+reg soc_litedramcore_phaseinjector3_baddress_re = 1'd0;
+reg [31:0] soc_litedramcore_phaseinjector3_wrdata_storage = 32'd0;
+reg soc_litedramcore_phaseinjector3_wrdata_re = 1'd0;
+reg [31:0] soc_litedramcore_phaseinjector3_rddata_status = 32'd0;
+wire soc_litedramcore_phaseinjector3_rddata_we;
+reg soc_litedramcore_phaseinjector3_rddata_re = 1'd0;
+wire soc_litedramcore_interface_bank0_valid;
+wire soc_litedramcore_interface_bank0_ready;
+wire soc_litedramcore_interface_bank0_we;
+wire [20:0] soc_litedramcore_interface_bank0_addr;
+wire soc_litedramcore_interface_bank0_lock;
+wire soc_litedramcore_interface_bank0_wdata_ready;
+wire soc_litedramcore_interface_bank0_rdata_valid;
+wire soc_litedramcore_interface_bank1_valid;
+wire soc_litedramcore_interface_bank1_ready;
+wire soc_litedramcore_interface_bank1_we;
+wire [20:0] soc_litedramcore_interface_bank1_addr;
+wire soc_litedramcore_interface_bank1_lock;
+wire soc_litedramcore_interface_bank1_wdata_ready;
+wire soc_litedramcore_interface_bank1_rdata_valid;
+wire soc_litedramcore_interface_bank2_valid;
+wire soc_litedramcore_interface_bank2_ready;
+wire soc_litedramcore_interface_bank2_we;
+wire [20:0] soc_litedramcore_interface_bank2_addr;
+wire soc_litedramcore_interface_bank2_lock;
+wire soc_litedramcore_interface_bank2_wdata_ready;
+wire soc_litedramcore_interface_bank2_rdata_valid;
+wire soc_litedramcore_interface_bank3_valid;
+wire soc_litedramcore_interface_bank3_ready;
+wire soc_litedramcore_interface_bank3_we;
+wire [20:0] soc_litedramcore_interface_bank3_addr;
+wire soc_litedramcore_interface_bank3_lock;
+wire soc_litedramcore_interface_bank3_wdata_ready;
+wire soc_litedramcore_interface_bank3_rdata_valid;
+wire soc_litedramcore_interface_bank4_valid;
+wire soc_litedramcore_interface_bank4_ready;
+wire soc_litedramcore_interface_bank4_we;
+wire [20:0] soc_litedramcore_interface_bank4_addr;
+wire soc_litedramcore_interface_bank4_lock;
+wire soc_litedramcore_interface_bank4_wdata_ready;
+wire soc_litedramcore_interface_bank4_rdata_valid;
+wire soc_litedramcore_interface_bank5_valid;
+wire soc_litedramcore_interface_bank5_ready;
+wire soc_litedramcore_interface_bank5_we;
+wire [20:0] soc_litedramcore_interface_bank5_addr;
+wire soc_litedramcore_interface_bank5_lock;
+wire soc_litedramcore_interface_bank5_wdata_ready;
+wire soc_litedramcore_interface_bank5_rdata_valid;
+wire soc_litedramcore_interface_bank6_valid;
+wire soc_litedramcore_interface_bank6_ready;
+wire soc_litedramcore_interface_bank6_we;
+wire [20:0] soc_litedramcore_interface_bank6_addr;
+wire soc_litedramcore_interface_bank6_lock;
+wire soc_litedramcore_interface_bank6_wdata_ready;
+wire soc_litedramcore_interface_bank6_rdata_valid;
+wire soc_litedramcore_interface_bank7_valid;
+wire soc_litedramcore_interface_bank7_ready;
+wire soc_litedramcore_interface_bank7_we;
+wire [20:0] soc_litedramcore_interface_bank7_addr;
+wire soc_litedramcore_interface_bank7_lock;
+wire soc_litedramcore_interface_bank7_wdata_ready;
+wire soc_litedramcore_interface_bank7_rdata_valid;
+reg [127:0] soc_litedramcore_interface_wdata = 128'd0;
+reg [15:0] soc_litedramcore_interface_wdata_we = 16'd0;
+wire [127:0] soc_litedramcore_interface_rdata;
+reg [13:0] soc_litedramcore_dfi_p0_address = 14'd0;
+reg [2:0] soc_litedramcore_dfi_p0_bank = 3'd0;
+reg soc_litedramcore_dfi_p0_cas_n = 1'd1;
+reg soc_litedramcore_dfi_p0_cs_n = 1'd1;
+reg soc_litedramcore_dfi_p0_ras_n = 1'd1;
+reg soc_litedramcore_dfi_p0_we_n = 1'd1;
+wire soc_litedramcore_dfi_p0_cke;
+wire soc_litedramcore_dfi_p0_odt;
+wire soc_litedramcore_dfi_p0_reset_n;
+reg soc_litedramcore_dfi_p0_act_n = 1'd1;
+wire [31:0] soc_litedramcore_dfi_p0_wrdata;
+reg soc_litedramcore_dfi_p0_wrdata_en = 1'd0;
+wire [3:0] soc_litedramcore_dfi_p0_wrdata_mask;
+reg soc_litedramcore_dfi_p0_rddata_en = 1'd0;
+wire [31:0] soc_litedramcore_dfi_p0_rddata;
+wire soc_litedramcore_dfi_p0_rddata_valid;
+reg [13:0] soc_litedramcore_dfi_p1_address = 14'd0;
+reg [2:0] soc_litedramcore_dfi_p1_bank = 3'd0;
+reg soc_litedramcore_dfi_p1_cas_n = 1'd1;
+reg soc_litedramcore_dfi_p1_cs_n = 1'd1;
+reg soc_litedramcore_dfi_p1_ras_n = 1'd1;
+reg soc_litedramcore_dfi_p1_we_n = 1'd1;
+wire soc_litedramcore_dfi_p1_cke;
+wire soc_litedramcore_dfi_p1_odt;
+wire soc_litedramcore_dfi_p1_reset_n;
+reg soc_litedramcore_dfi_p1_act_n = 1'd1;
+wire [31:0] soc_litedramcore_dfi_p1_wrdata;
+reg soc_litedramcore_dfi_p1_wrdata_en = 1'd0;
+wire [3:0] soc_litedramcore_dfi_p1_wrdata_mask;
+reg soc_litedramcore_dfi_p1_rddata_en = 1'd0;
+wire [31:0] soc_litedramcore_dfi_p1_rddata;
+wire soc_litedramcore_dfi_p1_rddata_valid;
+reg [13:0] soc_litedramcore_dfi_p2_address = 14'd0;
+reg [2:0] soc_litedramcore_dfi_p2_bank = 3'd0;
+reg soc_litedramcore_dfi_p2_cas_n = 1'd1;
+reg soc_litedramcore_dfi_p2_cs_n = 1'd1;
+reg soc_litedramcore_dfi_p2_ras_n = 1'd1;
+reg soc_litedramcore_dfi_p2_we_n = 1'd1;
+wire soc_litedramcore_dfi_p2_cke;
+wire soc_litedramcore_dfi_p2_odt;
+wire soc_litedramcore_dfi_p2_reset_n;
+reg soc_litedramcore_dfi_p2_act_n = 1'd1;
+wire [31:0] soc_litedramcore_dfi_p2_wrdata;
+reg soc_litedramcore_dfi_p2_wrdata_en = 1'd0;
+wire [3:0] soc_litedramcore_dfi_p2_wrdata_mask;
+reg soc_litedramcore_dfi_p2_rddata_en = 1'd0;
+wire [31:0] soc_litedramcore_dfi_p2_rddata;
+wire soc_litedramcore_dfi_p2_rddata_valid;
+reg [13:0] soc_litedramcore_dfi_p3_address = 14'd0;
+reg [2:0] soc_litedramcore_dfi_p3_bank = 3'd0;
+reg soc_litedramcore_dfi_p3_cas_n = 1'd1;
+reg soc_litedramcore_dfi_p3_cs_n = 1'd1;
+reg soc_litedramcore_dfi_p3_ras_n = 1'd1;
+reg soc_litedramcore_dfi_p3_we_n = 1'd1;
+wire soc_litedramcore_dfi_p3_cke;
+wire soc_litedramcore_dfi_p3_odt;
+wire soc_litedramcore_dfi_p3_reset_n;
+reg soc_litedramcore_dfi_p3_act_n = 1'd1;
+wire [31:0] soc_litedramcore_dfi_p3_wrdata;
+reg soc_litedramcore_dfi_p3_wrdata_en = 1'd0;
+wire [3:0] soc_litedramcore_dfi_p3_wrdata_mask;
+reg soc_litedramcore_dfi_p3_rddata_en = 1'd0;
+wire [31:0] soc_litedramcore_dfi_p3_rddata;
+wire soc_litedramcore_dfi_p3_rddata_valid;
+reg soc_litedramcore_cmd_valid = 1'd0;
+reg soc_litedramcore_cmd_ready = 1'd0;
+reg soc_litedramcore_cmd_last = 1'd0;
+reg [13:0] soc_litedramcore_cmd_payload_a = 14'd0;
+reg [2:0] soc_litedramcore_cmd_payload_ba = 3'd0;
+reg soc_litedramcore_cmd_payload_cas = 1'd0;
+reg soc_litedramcore_cmd_payload_ras = 1'd0;
+reg soc_litedramcore_cmd_payload_we = 1'd0;
+reg soc_litedramcore_cmd_payload_is_read = 1'd0;
+reg soc_litedramcore_cmd_payload_is_write = 1'd0;
+wire soc_litedramcore_wants_refresh;
+wire soc_litedramcore_wants_zqcs;
+wire soc_litedramcore_timer_wait;
+wire soc_litedramcore_timer_done0;
+wire [9:0] soc_litedramcore_timer_count0;
+wire soc_litedramcore_timer_done1;
+reg [9:0] soc_litedramcore_timer_count1 = 10'd781;
+wire soc_litedramcore_postponer_req_i;
+reg soc_litedramcore_postponer_req_o = 1'd0;
+reg soc_litedramcore_postponer_count = 1'd0;
+reg soc_litedramcore_sequencer_start0 = 1'd0;
+wire soc_litedramcore_sequencer_done0;
+wire soc_litedramcore_sequencer_start1;
+reg soc_litedramcore_sequencer_done1 = 1'd0;
+reg [5:0] soc_litedramcore_sequencer_counter = 6'd0;
+reg soc_litedramcore_sequencer_count = 1'd0;
+wire soc_litedramcore_zqcs_timer_wait;
+wire soc_litedramcore_zqcs_timer_done0;
+wire [26:0] soc_litedramcore_zqcs_timer_count0;
+wire soc_litedramcore_zqcs_timer_done1;
+reg [26:0] soc_litedramcore_zqcs_timer_count1 = 27'd99999999;
+reg soc_litedramcore_zqcs_executer_start = 1'd0;
+reg soc_litedramcore_zqcs_executer_done = 1'd0;
+reg [4:0] soc_litedramcore_zqcs_executer_counter = 5'd0;
+wire soc_litedramcore_bankmachine0_req_valid;
+wire soc_litedramcore_bankmachine0_req_ready;
+wire soc_litedramcore_bankmachine0_req_we;
+wire [20:0] soc_litedramcore_bankmachine0_req_addr;
+wire soc_litedramcore_bankmachine0_req_lock;
+reg soc_litedramcore_bankmachine0_req_wdata_ready = 1'd0;
+reg soc_litedramcore_bankmachine0_req_rdata_valid = 1'd0;
+wire soc_litedramcore_bankmachine0_refresh_req;
+reg soc_litedramcore_bankmachine0_refresh_gnt = 1'd0;
+reg soc_litedramcore_bankmachine0_cmd_valid = 1'd0;
+reg soc_litedramcore_bankmachine0_cmd_ready = 1'd0;
+reg [13:0] soc_litedramcore_bankmachine0_cmd_payload_a = 14'd0;
+wire [2:0] soc_litedramcore_bankmachine0_cmd_payload_ba;
+reg soc_litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
+reg soc_litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
+reg soc_litedramcore_bankmachine0_cmd_payload_we = 1'd0;
+reg soc_litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
+reg soc_litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
+reg soc_litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
+reg soc_litedramcore_bankmachine0_auto_precharge = 1'd0;
+wire soc_litedramcore_bankmachine0_sink_valid;
+wire soc_litedramcore_bankmachine0_sink_ready;
+reg soc_litedramcore_bankmachine0_sink_first = 1'd0;
+reg soc_litedramcore_bankmachine0_sink_last = 1'd0;
+wire soc_litedramcore_bankmachine0_sink_payload_we;
+wire [20:0] soc_litedramcore_bankmachine0_sink_payload_addr;
+wire soc_litedramcore_bankmachine0_source_valid;
+wire soc_litedramcore_bankmachine0_source_ready;
+wire soc_litedramcore_bankmachine0_source_first;
+wire soc_litedramcore_bankmachine0_source_last;
+wire soc_litedramcore_bankmachine0_source_payload_we;
+wire [20:0] soc_litedramcore_bankmachine0_source_payload_addr;
+wire soc_litedramcore_bankmachine0_syncfifo0_we;
+wire soc_litedramcore_bankmachine0_syncfifo0_writable;
+wire soc_litedramcore_bankmachine0_syncfifo0_re;
+wire soc_litedramcore_bankmachine0_syncfifo0_readable;
+wire [23:0] soc_litedramcore_bankmachine0_syncfifo0_din;
+wire [23:0] soc_litedramcore_bankmachine0_syncfifo0_dout;
+reg [4:0] soc_litedramcore_bankmachine0_level = 5'd0;
+reg soc_litedramcore_bankmachine0_replace = 1'd0;
+reg [3:0] soc_litedramcore_bankmachine0_produce = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine0_consume = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine0_wrport_adr = 4'd0;
+wire [23:0] soc_litedramcore_bankmachine0_wrport_dat_r;
+wire soc_litedramcore_bankmachine0_wrport_we;
+wire [23:0] soc_litedramcore_bankmachine0_wrport_dat_w;
+wire soc_litedramcore_bankmachine0_do_read;
+wire [3:0] soc_litedramcore_bankmachine0_rdport_adr;
+wire [23:0] soc_litedramcore_bankmachine0_rdport_dat_r;
+wire soc_litedramcore_bankmachine0_fifo_in_payload_we;
+wire [20:0] soc_litedramcore_bankmachine0_fifo_in_payload_addr;
+wire soc_litedramcore_bankmachine0_fifo_in_first;
+wire soc_litedramcore_bankmachine0_fifo_in_last;
+wire soc_litedramcore_bankmachine0_fifo_out_payload_we;
+wire [20:0] soc_litedramcore_bankmachine0_fifo_out_payload_addr;
+wire soc_litedramcore_bankmachine0_fifo_out_first;
+wire soc_litedramcore_bankmachine0_fifo_out_last;
+wire soc_litedramcore_bankmachine0_sink_sink_valid;
+wire soc_litedramcore_bankmachine0_sink_sink_ready;
+wire soc_litedramcore_bankmachine0_sink_sink_first;
+wire soc_litedramcore_bankmachine0_sink_sink_last;
+wire soc_litedramcore_bankmachine0_sink_sink_payload_we;
+wire [20:0] soc_litedramcore_bankmachine0_sink_sink_payload_addr;
+wire soc_litedramcore_bankmachine0_source_source_valid;
+wire soc_litedramcore_bankmachine0_source_source_ready;
+wire soc_litedramcore_bankmachine0_source_source_first;
+wire soc_litedramcore_bankmachine0_source_source_last;
+wire soc_litedramcore_bankmachine0_source_source_payload_we;
+wire [20:0] soc_litedramcore_bankmachine0_source_source_payload_addr;
+wire soc_litedramcore_bankmachine0_pipe_valid_sink_valid;
+wire soc_litedramcore_bankmachine0_pipe_valid_sink_ready;
+wire soc_litedramcore_bankmachine0_pipe_valid_sink_first;
+wire soc_litedramcore_bankmachine0_pipe_valid_sink_last;
+wire soc_litedramcore_bankmachine0_pipe_valid_sink_payload_we;
+wire [20:0] soc_litedramcore_bankmachine0_pipe_valid_sink_payload_addr;
+reg soc_litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0;
+wire soc_litedramcore_bankmachine0_pipe_valid_source_ready;
+reg soc_litedramcore_bankmachine0_pipe_valid_source_first = 1'd0;
+reg soc_litedramcore_bankmachine0_pipe_valid_source_last = 1'd0;
+reg soc_litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0;
+reg [20:0] soc_litedramcore_bankmachine0_pipe_valid_source_payload_addr = 21'd0;
+reg [13:0] soc_litedramcore_bankmachine0_row = 14'd0;
+reg soc_litedramcore_bankmachine0_row_opened = 1'd0;
+wire soc_litedramcore_bankmachine0_row_hit;
+reg soc_litedramcore_bankmachine0_row_open = 1'd0;
+reg soc_litedramcore_bankmachine0_row_close = 1'd0;
+reg soc_litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
+wire soc_litedramcore_bankmachine0_twtpcon_valid;
+reg soc_litedramcore_bankmachine0_twtpcon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine0_twtpcon_count = 3'd0;
+wire soc_litedramcore_bankmachine0_trccon_valid;
+reg soc_litedramcore_bankmachine0_trccon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine0_trccon_count = 3'd0;
+wire soc_litedramcore_bankmachine0_trascon_valid;
+reg soc_litedramcore_bankmachine0_trascon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine0_trascon_count = 3'd0;
+wire soc_litedramcore_bankmachine1_req_valid;
+wire soc_litedramcore_bankmachine1_req_ready;
+wire soc_litedramcore_bankmachine1_req_we;
+wire [20:0] soc_litedramcore_bankmachine1_req_addr;
+wire soc_litedramcore_bankmachine1_req_lock;
+reg soc_litedramcore_bankmachine1_req_wdata_ready = 1'd0;
+reg soc_litedramcore_bankmachine1_req_rdata_valid = 1'd0;
+wire soc_litedramcore_bankmachine1_refresh_req;
+reg soc_litedramcore_bankmachine1_refresh_gnt = 1'd0;
+reg soc_litedramcore_bankmachine1_cmd_valid = 1'd0;
+reg soc_litedramcore_bankmachine1_cmd_ready = 1'd0;
+reg [13:0] soc_litedramcore_bankmachine1_cmd_payload_a = 14'd0;
+wire [2:0] soc_litedramcore_bankmachine1_cmd_payload_ba;
+reg soc_litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
+reg soc_litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
+reg soc_litedramcore_bankmachine1_cmd_payload_we = 1'd0;
+reg soc_litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
+reg soc_litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
+reg soc_litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
+reg soc_litedramcore_bankmachine1_auto_precharge = 1'd0;
+wire soc_litedramcore_bankmachine1_sink_valid;
+wire soc_litedramcore_bankmachine1_sink_ready;
+reg soc_litedramcore_bankmachine1_sink_first = 1'd0;
+reg soc_litedramcore_bankmachine1_sink_last = 1'd0;
+wire soc_litedramcore_bankmachine1_sink_payload_we;
+wire [20:0] soc_litedramcore_bankmachine1_sink_payload_addr;
+wire soc_litedramcore_bankmachine1_source_valid;
+wire soc_litedramcore_bankmachine1_source_ready;
+wire soc_litedramcore_bankmachine1_source_first;
+wire soc_litedramcore_bankmachine1_source_last;
+wire soc_litedramcore_bankmachine1_source_payload_we;
+wire [20:0] soc_litedramcore_bankmachine1_source_payload_addr;
+wire soc_litedramcore_bankmachine1_syncfifo1_we;
+wire soc_litedramcore_bankmachine1_syncfifo1_writable;
+wire soc_litedramcore_bankmachine1_syncfifo1_re;
+wire soc_litedramcore_bankmachine1_syncfifo1_readable;
+wire [23:0] soc_litedramcore_bankmachine1_syncfifo1_din;
+wire [23:0] soc_litedramcore_bankmachine1_syncfifo1_dout;
+reg [4:0] soc_litedramcore_bankmachine1_level = 5'd0;
+reg soc_litedramcore_bankmachine1_replace = 1'd0;
+reg [3:0] soc_litedramcore_bankmachine1_produce = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine1_consume = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine1_wrport_adr = 4'd0;
+wire [23:0] soc_litedramcore_bankmachine1_wrport_dat_r;
+wire soc_litedramcore_bankmachine1_wrport_we;
+wire [23:0] soc_litedramcore_bankmachine1_wrport_dat_w;
+wire soc_litedramcore_bankmachine1_do_read;
+wire [3:0] soc_litedramcore_bankmachine1_rdport_adr;
+wire [23:0] soc_litedramcore_bankmachine1_rdport_dat_r;
+wire soc_litedramcore_bankmachine1_fifo_in_payload_we;
+wire [20:0] soc_litedramcore_bankmachine1_fifo_in_payload_addr;
+wire soc_litedramcore_bankmachine1_fifo_in_first;
+wire soc_litedramcore_bankmachine1_fifo_in_last;
+wire soc_litedramcore_bankmachine1_fifo_out_payload_we;
+wire [20:0] soc_litedramcore_bankmachine1_fifo_out_payload_addr;
+wire soc_litedramcore_bankmachine1_fifo_out_first;
+wire soc_litedramcore_bankmachine1_fifo_out_last;
+wire soc_litedramcore_bankmachine1_sink_sink_valid;
+wire soc_litedramcore_bankmachine1_sink_sink_ready;
+wire soc_litedramcore_bankmachine1_sink_sink_first;
+wire soc_litedramcore_bankmachine1_sink_sink_last;
+wire soc_litedramcore_bankmachine1_sink_sink_payload_we;
+wire [20:0] soc_litedramcore_bankmachine1_sink_sink_payload_addr;
+wire soc_litedramcore_bankmachine1_source_source_valid;
+wire soc_litedramcore_bankmachine1_source_source_ready;
+wire soc_litedramcore_bankmachine1_source_source_first;
+wire soc_litedramcore_bankmachine1_source_source_last;
+wire soc_litedramcore_bankmachine1_source_source_payload_we;
+wire [20:0] soc_litedramcore_bankmachine1_source_source_payload_addr;
+wire soc_litedramcore_bankmachine1_pipe_valid_sink_valid;
+wire soc_litedramcore_bankmachine1_pipe_valid_sink_ready;
+wire soc_litedramcore_bankmachine1_pipe_valid_sink_first;
+wire soc_litedramcore_bankmachine1_pipe_valid_sink_last;
+wire soc_litedramcore_bankmachine1_pipe_valid_sink_payload_we;
+wire [20:0] soc_litedramcore_bankmachine1_pipe_valid_sink_payload_addr;
+reg soc_litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0;
+wire soc_litedramcore_bankmachine1_pipe_valid_source_ready;
+reg soc_litedramcore_bankmachine1_pipe_valid_source_first = 1'd0;
+reg soc_litedramcore_bankmachine1_pipe_valid_source_last = 1'd0;
+reg soc_litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0;
+reg [20:0] soc_litedramcore_bankmachine1_pipe_valid_source_payload_addr = 21'd0;
+reg [13:0] soc_litedramcore_bankmachine1_row = 14'd0;
+reg soc_litedramcore_bankmachine1_row_opened = 1'd0;
+wire soc_litedramcore_bankmachine1_row_hit;
+reg soc_litedramcore_bankmachine1_row_open = 1'd0;
+reg soc_litedramcore_bankmachine1_row_close = 1'd0;
+reg soc_litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
+wire soc_litedramcore_bankmachine1_twtpcon_valid;
+reg soc_litedramcore_bankmachine1_twtpcon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine1_twtpcon_count = 3'd0;
+wire soc_litedramcore_bankmachine1_trccon_valid;
+reg soc_litedramcore_bankmachine1_trccon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine1_trccon_count = 3'd0;
+wire soc_litedramcore_bankmachine1_trascon_valid;
+reg soc_litedramcore_bankmachine1_trascon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine1_trascon_count = 3'd0;
+wire soc_litedramcore_bankmachine2_req_valid;
+wire soc_litedramcore_bankmachine2_req_ready;
+wire soc_litedramcore_bankmachine2_req_we;
+wire [20:0] soc_litedramcore_bankmachine2_req_addr;
+wire soc_litedramcore_bankmachine2_req_lock;
+reg soc_litedramcore_bankmachine2_req_wdata_ready = 1'd0;
+reg soc_litedramcore_bankmachine2_req_rdata_valid = 1'd0;
+wire soc_litedramcore_bankmachine2_refresh_req;
+reg soc_litedramcore_bankmachine2_refresh_gnt = 1'd0;
+reg soc_litedramcore_bankmachine2_cmd_valid = 1'd0;
+reg soc_litedramcore_bankmachine2_cmd_ready = 1'd0;
+reg [13:0] soc_litedramcore_bankmachine2_cmd_payload_a = 14'd0;
+wire [2:0] soc_litedramcore_bankmachine2_cmd_payload_ba;
+reg soc_litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
+reg soc_litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
+reg soc_litedramcore_bankmachine2_cmd_payload_we = 1'd0;
+reg soc_litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
+reg soc_litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
+reg soc_litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
+reg soc_litedramcore_bankmachine2_auto_precharge = 1'd0;
+wire soc_litedramcore_bankmachine2_sink_valid;
+wire soc_litedramcore_bankmachine2_sink_ready;
+reg soc_litedramcore_bankmachine2_sink_first = 1'd0;
+reg soc_litedramcore_bankmachine2_sink_last = 1'd0;
+wire soc_litedramcore_bankmachine2_sink_payload_we;
+wire [20:0] soc_litedramcore_bankmachine2_sink_payload_addr;
+wire soc_litedramcore_bankmachine2_source_valid;
+wire soc_litedramcore_bankmachine2_source_ready;
+wire soc_litedramcore_bankmachine2_source_first;
+wire soc_litedramcore_bankmachine2_source_last;
+wire soc_litedramcore_bankmachine2_source_payload_we;
+wire [20:0] soc_litedramcore_bankmachine2_source_payload_addr;
+wire soc_litedramcore_bankmachine2_syncfifo2_we;
+wire soc_litedramcore_bankmachine2_syncfifo2_writable;
+wire soc_litedramcore_bankmachine2_syncfifo2_re;
+wire soc_litedramcore_bankmachine2_syncfifo2_readable;
+wire [23:0] soc_litedramcore_bankmachine2_syncfifo2_din;
+wire [23:0] soc_litedramcore_bankmachine2_syncfifo2_dout;
+reg [4:0] soc_litedramcore_bankmachine2_level = 5'd0;
+reg soc_litedramcore_bankmachine2_replace = 1'd0;
+reg [3:0] soc_litedramcore_bankmachine2_produce = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine2_consume = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine2_wrport_adr = 4'd0;
+wire [23:0] soc_litedramcore_bankmachine2_wrport_dat_r;
+wire soc_litedramcore_bankmachine2_wrport_we;
+wire [23:0] soc_litedramcore_bankmachine2_wrport_dat_w;
+wire soc_litedramcore_bankmachine2_do_read;
+wire [3:0] soc_litedramcore_bankmachine2_rdport_adr;
+wire [23:0] soc_litedramcore_bankmachine2_rdport_dat_r;
+wire soc_litedramcore_bankmachine2_fifo_in_payload_we;
+wire [20:0] soc_litedramcore_bankmachine2_fifo_in_payload_addr;
+wire soc_litedramcore_bankmachine2_fifo_in_first;
+wire soc_litedramcore_bankmachine2_fifo_in_last;
+wire soc_litedramcore_bankmachine2_fifo_out_payload_we;
+wire [20:0] soc_litedramcore_bankmachine2_fifo_out_payload_addr;
+wire soc_litedramcore_bankmachine2_fifo_out_first;
+wire soc_litedramcore_bankmachine2_fifo_out_last;
+wire soc_litedramcore_bankmachine2_sink_sink_valid;
+wire soc_litedramcore_bankmachine2_sink_sink_ready;
+wire soc_litedramcore_bankmachine2_sink_sink_first;
+wire soc_litedramcore_bankmachine2_sink_sink_last;
+wire soc_litedramcore_bankmachine2_sink_sink_payload_we;
+wire [20:0] soc_litedramcore_bankmachine2_sink_sink_payload_addr;
+wire soc_litedramcore_bankmachine2_source_source_valid;
+wire soc_litedramcore_bankmachine2_source_source_ready;
+wire soc_litedramcore_bankmachine2_source_source_first;
+wire soc_litedramcore_bankmachine2_source_source_last;
+wire soc_litedramcore_bankmachine2_source_source_payload_we;
+wire [20:0] soc_litedramcore_bankmachine2_source_source_payload_addr;
+wire soc_litedramcore_bankmachine2_pipe_valid_sink_valid;
+wire soc_litedramcore_bankmachine2_pipe_valid_sink_ready;
+wire soc_litedramcore_bankmachine2_pipe_valid_sink_first;
+wire soc_litedramcore_bankmachine2_pipe_valid_sink_last;
+wire soc_litedramcore_bankmachine2_pipe_valid_sink_payload_we;
+wire [20:0] soc_litedramcore_bankmachine2_pipe_valid_sink_payload_addr;
+reg soc_litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0;
+wire soc_litedramcore_bankmachine2_pipe_valid_source_ready;
+reg soc_litedramcore_bankmachine2_pipe_valid_source_first = 1'd0;
+reg soc_litedramcore_bankmachine2_pipe_valid_source_last = 1'd0;
+reg soc_litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0;
+reg [20:0] soc_litedramcore_bankmachine2_pipe_valid_source_payload_addr = 21'd0;
+reg [13:0] soc_litedramcore_bankmachine2_row = 14'd0;
+reg soc_litedramcore_bankmachine2_row_opened = 1'd0;
+wire soc_litedramcore_bankmachine2_row_hit;
+reg soc_litedramcore_bankmachine2_row_open = 1'd0;
+reg soc_litedramcore_bankmachine2_row_close = 1'd0;
+reg soc_litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
+wire soc_litedramcore_bankmachine2_twtpcon_valid;
+reg soc_litedramcore_bankmachine2_twtpcon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine2_twtpcon_count = 3'd0;
+wire soc_litedramcore_bankmachine2_trccon_valid;
+reg soc_litedramcore_bankmachine2_trccon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine2_trccon_count = 3'd0;
+wire soc_litedramcore_bankmachine2_trascon_valid;
+reg soc_litedramcore_bankmachine2_trascon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine2_trascon_count = 3'd0;
+wire soc_litedramcore_bankmachine3_req_valid;
+wire soc_litedramcore_bankmachine3_req_ready;
+wire soc_litedramcore_bankmachine3_req_we;
+wire [20:0] soc_litedramcore_bankmachine3_req_addr;
+wire soc_litedramcore_bankmachine3_req_lock;
+reg soc_litedramcore_bankmachine3_req_wdata_ready = 1'd0;
+reg soc_litedramcore_bankmachine3_req_rdata_valid = 1'd0;
+wire soc_litedramcore_bankmachine3_refresh_req;
+reg soc_litedramcore_bankmachine3_refresh_gnt = 1'd0;
+reg soc_litedramcore_bankmachine3_cmd_valid = 1'd0;
+reg soc_litedramcore_bankmachine3_cmd_ready = 1'd0;
+reg [13:0] soc_litedramcore_bankmachine3_cmd_payload_a = 14'd0;
+wire [2:0] soc_litedramcore_bankmachine3_cmd_payload_ba;
+reg soc_litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
+reg soc_litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
+reg soc_litedramcore_bankmachine3_cmd_payload_we = 1'd0;
+reg soc_litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
+reg soc_litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
+reg soc_litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
+reg soc_litedramcore_bankmachine3_auto_precharge = 1'd0;
+wire soc_litedramcore_bankmachine3_sink_valid;
+wire soc_litedramcore_bankmachine3_sink_ready;
+reg soc_litedramcore_bankmachine3_sink_first = 1'd0;
+reg soc_litedramcore_bankmachine3_sink_last = 1'd0;
+wire soc_litedramcore_bankmachine3_sink_payload_we;
+wire [20:0] soc_litedramcore_bankmachine3_sink_payload_addr;
+wire soc_litedramcore_bankmachine3_source_valid;
+wire soc_litedramcore_bankmachine3_source_ready;
+wire soc_litedramcore_bankmachine3_source_first;
+wire soc_litedramcore_bankmachine3_source_last;
+wire soc_litedramcore_bankmachine3_source_payload_we;
+wire [20:0] soc_litedramcore_bankmachine3_source_payload_addr;
+wire soc_litedramcore_bankmachine3_syncfifo3_we;
+wire soc_litedramcore_bankmachine3_syncfifo3_writable;
+wire soc_litedramcore_bankmachine3_syncfifo3_re;
+wire soc_litedramcore_bankmachine3_syncfifo3_readable;
+wire [23:0] soc_litedramcore_bankmachine3_syncfifo3_din;
+wire [23:0] soc_litedramcore_bankmachine3_syncfifo3_dout;
+reg [4:0] soc_litedramcore_bankmachine3_level = 5'd0;
+reg soc_litedramcore_bankmachine3_replace = 1'd0;
+reg [3:0] soc_litedramcore_bankmachine3_produce = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine3_consume = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine3_wrport_adr = 4'd0;
+wire [23:0] soc_litedramcore_bankmachine3_wrport_dat_r;
+wire soc_litedramcore_bankmachine3_wrport_we;
+wire [23:0] soc_litedramcore_bankmachine3_wrport_dat_w;
+wire soc_litedramcore_bankmachine3_do_read;
+wire [3:0] soc_litedramcore_bankmachine3_rdport_adr;
+wire [23:0] soc_litedramcore_bankmachine3_rdport_dat_r;
+wire soc_litedramcore_bankmachine3_fifo_in_payload_we;
+wire [20:0] soc_litedramcore_bankmachine3_fifo_in_payload_addr;
+wire soc_litedramcore_bankmachine3_fifo_in_first;
+wire soc_litedramcore_bankmachine3_fifo_in_last;
+wire soc_litedramcore_bankmachine3_fifo_out_payload_we;
+wire [20:0] soc_litedramcore_bankmachine3_fifo_out_payload_addr;
+wire soc_litedramcore_bankmachine3_fifo_out_first;
+wire soc_litedramcore_bankmachine3_fifo_out_last;
+wire soc_litedramcore_bankmachine3_sink_sink_valid;
+wire soc_litedramcore_bankmachine3_sink_sink_ready;
+wire soc_litedramcore_bankmachine3_sink_sink_first;
+wire soc_litedramcore_bankmachine3_sink_sink_last;
+wire soc_litedramcore_bankmachine3_sink_sink_payload_we;
+wire [20:0] soc_litedramcore_bankmachine3_sink_sink_payload_addr;
+wire soc_litedramcore_bankmachine3_source_source_valid;
+wire soc_litedramcore_bankmachine3_source_source_ready;
+wire soc_litedramcore_bankmachine3_source_source_first;
+wire soc_litedramcore_bankmachine3_source_source_last;
+wire soc_litedramcore_bankmachine3_source_source_payload_we;
+wire [20:0] soc_litedramcore_bankmachine3_source_source_payload_addr;
+wire soc_litedramcore_bankmachine3_pipe_valid_sink_valid;
+wire soc_litedramcore_bankmachine3_pipe_valid_sink_ready;
+wire soc_litedramcore_bankmachine3_pipe_valid_sink_first;
+wire soc_litedramcore_bankmachine3_pipe_valid_sink_last;
+wire soc_litedramcore_bankmachine3_pipe_valid_sink_payload_we;
+wire [20:0] soc_litedramcore_bankmachine3_pipe_valid_sink_payload_addr;
+reg soc_litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0;
+wire soc_litedramcore_bankmachine3_pipe_valid_source_ready;
+reg soc_litedramcore_bankmachine3_pipe_valid_source_first = 1'd0;
+reg soc_litedramcore_bankmachine3_pipe_valid_source_last = 1'd0;
+reg soc_litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0;
+reg [20:0] soc_litedramcore_bankmachine3_pipe_valid_source_payload_addr = 21'd0;
+reg [13:0] soc_litedramcore_bankmachine3_row = 14'd0;
+reg soc_litedramcore_bankmachine3_row_opened = 1'd0;
+wire soc_litedramcore_bankmachine3_row_hit;
+reg soc_litedramcore_bankmachine3_row_open = 1'd0;
+reg soc_litedramcore_bankmachine3_row_close = 1'd0;
+reg soc_litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
+wire soc_litedramcore_bankmachine3_twtpcon_valid;
+reg soc_litedramcore_bankmachine3_twtpcon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine3_twtpcon_count = 3'd0;
+wire soc_litedramcore_bankmachine3_trccon_valid;
+reg soc_litedramcore_bankmachine3_trccon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine3_trccon_count = 3'd0;
+wire soc_litedramcore_bankmachine3_trascon_valid;
+reg soc_litedramcore_bankmachine3_trascon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine3_trascon_count = 3'd0;
+wire soc_litedramcore_bankmachine4_req_valid;
+wire soc_litedramcore_bankmachine4_req_ready;
+wire soc_litedramcore_bankmachine4_req_we;
+wire [20:0] soc_litedramcore_bankmachine4_req_addr;
+wire soc_litedramcore_bankmachine4_req_lock;
+reg soc_litedramcore_bankmachine4_req_wdata_ready = 1'd0;
+reg soc_litedramcore_bankmachine4_req_rdata_valid = 1'd0;
+wire soc_litedramcore_bankmachine4_refresh_req;
+reg soc_litedramcore_bankmachine4_refresh_gnt = 1'd0;
+reg soc_litedramcore_bankmachine4_cmd_valid = 1'd0;
+reg soc_litedramcore_bankmachine4_cmd_ready = 1'd0;
+reg [13:0] soc_litedramcore_bankmachine4_cmd_payload_a = 14'd0;
+wire [2:0] soc_litedramcore_bankmachine4_cmd_payload_ba;
+reg soc_litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
+reg soc_litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
+reg soc_litedramcore_bankmachine4_cmd_payload_we = 1'd0;
+reg soc_litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
+reg soc_litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
+reg soc_litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
+reg soc_litedramcore_bankmachine4_auto_precharge = 1'd0;
+wire soc_litedramcore_bankmachine4_sink_valid;
+wire soc_litedramcore_bankmachine4_sink_ready;
+reg soc_litedramcore_bankmachine4_sink_first = 1'd0;
+reg soc_litedramcore_bankmachine4_sink_last = 1'd0;
+wire soc_litedramcore_bankmachine4_sink_payload_we;
+wire [20:0] soc_litedramcore_bankmachine4_sink_payload_addr;
+wire soc_litedramcore_bankmachine4_source_valid;
+wire soc_litedramcore_bankmachine4_source_ready;
+wire soc_litedramcore_bankmachine4_source_first;
+wire soc_litedramcore_bankmachine4_source_last;
+wire soc_litedramcore_bankmachine4_source_payload_we;
+wire [20:0] soc_litedramcore_bankmachine4_source_payload_addr;
+wire soc_litedramcore_bankmachine4_syncfifo4_we;
+wire soc_litedramcore_bankmachine4_syncfifo4_writable;
+wire soc_litedramcore_bankmachine4_syncfifo4_re;
+wire soc_litedramcore_bankmachine4_syncfifo4_readable;
+wire [23:0] soc_litedramcore_bankmachine4_syncfifo4_din;
+wire [23:0] soc_litedramcore_bankmachine4_syncfifo4_dout;
+reg [4:0] soc_litedramcore_bankmachine4_level = 5'd0;
+reg soc_litedramcore_bankmachine4_replace = 1'd0;
+reg [3:0] soc_litedramcore_bankmachine4_produce = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine4_consume = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine4_wrport_adr = 4'd0;
+wire [23:0] soc_litedramcore_bankmachine4_wrport_dat_r;
+wire soc_litedramcore_bankmachine4_wrport_we;
+wire [23:0] soc_litedramcore_bankmachine4_wrport_dat_w;
+wire soc_litedramcore_bankmachine4_do_read;
+wire [3:0] soc_litedramcore_bankmachine4_rdport_adr;
+wire [23:0] soc_litedramcore_bankmachine4_rdport_dat_r;
+wire soc_litedramcore_bankmachine4_fifo_in_payload_we;
+wire [20:0] soc_litedramcore_bankmachine4_fifo_in_payload_addr;
+wire soc_litedramcore_bankmachine4_fifo_in_first;
+wire soc_litedramcore_bankmachine4_fifo_in_last;
+wire soc_litedramcore_bankmachine4_fifo_out_payload_we;
+wire [20:0] soc_litedramcore_bankmachine4_fifo_out_payload_addr;
+wire soc_litedramcore_bankmachine4_fifo_out_first;
+wire soc_litedramcore_bankmachine4_fifo_out_last;
+wire soc_litedramcore_bankmachine4_sink_sink_valid;
+wire soc_litedramcore_bankmachine4_sink_sink_ready;
+wire soc_litedramcore_bankmachine4_sink_sink_first;
+wire soc_litedramcore_bankmachine4_sink_sink_last;
+wire soc_litedramcore_bankmachine4_sink_sink_payload_we;
+wire [20:0] soc_litedramcore_bankmachine4_sink_sink_payload_addr;
+wire soc_litedramcore_bankmachine4_source_source_valid;
+wire soc_litedramcore_bankmachine4_source_source_ready;
+wire soc_litedramcore_bankmachine4_source_source_first;
+wire soc_litedramcore_bankmachine4_source_source_last;
+wire soc_litedramcore_bankmachine4_source_source_payload_we;
+wire [20:0] soc_litedramcore_bankmachine4_source_source_payload_addr;
+wire soc_litedramcore_bankmachine4_pipe_valid_sink_valid;
+wire soc_litedramcore_bankmachine4_pipe_valid_sink_ready;
+wire soc_litedramcore_bankmachine4_pipe_valid_sink_first;
+wire soc_litedramcore_bankmachine4_pipe_valid_sink_last;
+wire soc_litedramcore_bankmachine4_pipe_valid_sink_payload_we;
+wire [20:0] soc_litedramcore_bankmachine4_pipe_valid_sink_payload_addr;
+reg soc_litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0;
+wire soc_litedramcore_bankmachine4_pipe_valid_source_ready;
+reg soc_litedramcore_bankmachine4_pipe_valid_source_first = 1'd0;
+reg soc_litedramcore_bankmachine4_pipe_valid_source_last = 1'd0;
+reg soc_litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0;
+reg [20:0] soc_litedramcore_bankmachine4_pipe_valid_source_payload_addr = 21'd0;
+reg [13:0] soc_litedramcore_bankmachine4_row = 14'd0;
+reg soc_litedramcore_bankmachine4_row_opened = 1'd0;
+wire soc_litedramcore_bankmachine4_row_hit;
+reg soc_litedramcore_bankmachine4_row_open = 1'd0;
+reg soc_litedramcore_bankmachine4_row_close = 1'd0;
+reg soc_litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
+wire soc_litedramcore_bankmachine4_twtpcon_valid;
+reg soc_litedramcore_bankmachine4_twtpcon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine4_twtpcon_count = 3'd0;
+wire soc_litedramcore_bankmachine4_trccon_valid;
+reg soc_litedramcore_bankmachine4_trccon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine4_trccon_count = 3'd0;
+wire soc_litedramcore_bankmachine4_trascon_valid;
+reg soc_litedramcore_bankmachine4_trascon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine4_trascon_count = 3'd0;
+wire soc_litedramcore_bankmachine5_req_valid;
+wire soc_litedramcore_bankmachine5_req_ready;
+wire soc_litedramcore_bankmachine5_req_we;
+wire [20:0] soc_litedramcore_bankmachine5_req_addr;
+wire soc_litedramcore_bankmachine5_req_lock;
+reg soc_litedramcore_bankmachine5_req_wdata_ready = 1'd0;
+reg soc_litedramcore_bankmachine5_req_rdata_valid = 1'd0;
+wire soc_litedramcore_bankmachine5_refresh_req;
+reg soc_litedramcore_bankmachine5_refresh_gnt = 1'd0;
+reg soc_litedramcore_bankmachine5_cmd_valid = 1'd0;
+reg soc_litedramcore_bankmachine5_cmd_ready = 1'd0;
+reg [13:0] soc_litedramcore_bankmachine5_cmd_payload_a = 14'd0;
+wire [2:0] soc_litedramcore_bankmachine5_cmd_payload_ba;
+reg soc_litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
+reg soc_litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
+reg soc_litedramcore_bankmachine5_cmd_payload_we = 1'd0;
+reg soc_litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
+reg soc_litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
+reg soc_litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
+reg soc_litedramcore_bankmachine5_auto_precharge = 1'd0;
+wire soc_litedramcore_bankmachine5_sink_valid;
+wire soc_litedramcore_bankmachine5_sink_ready;
+reg soc_litedramcore_bankmachine5_sink_first = 1'd0;
+reg soc_litedramcore_bankmachine5_sink_last = 1'd0;
+wire soc_litedramcore_bankmachine5_sink_payload_we;
+wire [20:0] soc_litedramcore_bankmachine5_sink_payload_addr;
+wire soc_litedramcore_bankmachine5_source_valid;
+wire soc_litedramcore_bankmachine5_source_ready;
+wire soc_litedramcore_bankmachine5_source_first;
+wire soc_litedramcore_bankmachine5_source_last;
+wire soc_litedramcore_bankmachine5_source_payload_we;
+wire [20:0] soc_litedramcore_bankmachine5_source_payload_addr;
+wire soc_litedramcore_bankmachine5_syncfifo5_we;
+wire soc_litedramcore_bankmachine5_syncfifo5_writable;
+wire soc_litedramcore_bankmachine5_syncfifo5_re;
+wire soc_litedramcore_bankmachine5_syncfifo5_readable;
+wire [23:0] soc_litedramcore_bankmachine5_syncfifo5_din;
+wire [23:0] soc_litedramcore_bankmachine5_syncfifo5_dout;
+reg [4:0] soc_litedramcore_bankmachine5_level = 5'd0;
+reg soc_litedramcore_bankmachine5_replace = 1'd0;
+reg [3:0] soc_litedramcore_bankmachine5_produce = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine5_consume = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine5_wrport_adr = 4'd0;
+wire [23:0] soc_litedramcore_bankmachine5_wrport_dat_r;
+wire soc_litedramcore_bankmachine5_wrport_we;
+wire [23:0] soc_litedramcore_bankmachine5_wrport_dat_w;
+wire soc_litedramcore_bankmachine5_do_read;
+wire [3:0] soc_litedramcore_bankmachine5_rdport_adr;
+wire [23:0] soc_litedramcore_bankmachine5_rdport_dat_r;
+wire soc_litedramcore_bankmachine5_fifo_in_payload_we;
+wire [20:0] soc_litedramcore_bankmachine5_fifo_in_payload_addr;
+wire soc_litedramcore_bankmachine5_fifo_in_first;
+wire soc_litedramcore_bankmachine5_fifo_in_last;
+wire soc_litedramcore_bankmachine5_fifo_out_payload_we;
+wire [20:0] soc_litedramcore_bankmachine5_fifo_out_payload_addr;
+wire soc_litedramcore_bankmachine5_fifo_out_first;
+wire soc_litedramcore_bankmachine5_fifo_out_last;
+wire soc_litedramcore_bankmachine5_sink_sink_valid;
+wire soc_litedramcore_bankmachine5_sink_sink_ready;
+wire soc_litedramcore_bankmachine5_sink_sink_first;
+wire soc_litedramcore_bankmachine5_sink_sink_last;
+wire soc_litedramcore_bankmachine5_sink_sink_payload_we;
+wire [20:0] soc_litedramcore_bankmachine5_sink_sink_payload_addr;
+wire soc_litedramcore_bankmachine5_source_source_valid;
+wire soc_litedramcore_bankmachine5_source_source_ready;
+wire soc_litedramcore_bankmachine5_source_source_first;
+wire soc_litedramcore_bankmachine5_source_source_last;
+wire soc_litedramcore_bankmachine5_source_source_payload_we;
+wire [20:0] soc_litedramcore_bankmachine5_source_source_payload_addr;
+wire soc_litedramcore_bankmachine5_pipe_valid_sink_valid;
+wire soc_litedramcore_bankmachine5_pipe_valid_sink_ready;
+wire soc_litedramcore_bankmachine5_pipe_valid_sink_first;
+wire soc_litedramcore_bankmachine5_pipe_valid_sink_last;
+wire soc_litedramcore_bankmachine5_pipe_valid_sink_payload_we;
+wire [20:0] soc_litedramcore_bankmachine5_pipe_valid_sink_payload_addr;
+reg soc_litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0;
+wire soc_litedramcore_bankmachine5_pipe_valid_source_ready;
+reg soc_litedramcore_bankmachine5_pipe_valid_source_first = 1'd0;
+reg soc_litedramcore_bankmachine5_pipe_valid_source_last = 1'd0;
+reg soc_litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0;
+reg [20:0] soc_litedramcore_bankmachine5_pipe_valid_source_payload_addr = 21'd0;
+reg [13:0] soc_litedramcore_bankmachine5_row = 14'd0;
+reg soc_litedramcore_bankmachine5_row_opened = 1'd0;
+wire soc_litedramcore_bankmachine5_row_hit;
+reg soc_litedramcore_bankmachine5_row_open = 1'd0;
+reg soc_litedramcore_bankmachine5_row_close = 1'd0;
+reg soc_litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
+wire soc_litedramcore_bankmachine5_twtpcon_valid;
+reg soc_litedramcore_bankmachine5_twtpcon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine5_twtpcon_count = 3'd0;
+wire soc_litedramcore_bankmachine5_trccon_valid;
+reg soc_litedramcore_bankmachine5_trccon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine5_trccon_count = 3'd0;
+wire soc_litedramcore_bankmachine5_trascon_valid;
+reg soc_litedramcore_bankmachine5_trascon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine5_trascon_count = 3'd0;
+wire soc_litedramcore_bankmachine6_req_valid;
+wire soc_litedramcore_bankmachine6_req_ready;
+wire soc_litedramcore_bankmachine6_req_we;
+wire [20:0] soc_litedramcore_bankmachine6_req_addr;
+wire soc_litedramcore_bankmachine6_req_lock;
+reg soc_litedramcore_bankmachine6_req_wdata_ready = 1'd0;
+reg soc_litedramcore_bankmachine6_req_rdata_valid = 1'd0;
+wire soc_litedramcore_bankmachine6_refresh_req;
+reg soc_litedramcore_bankmachine6_refresh_gnt = 1'd0;
+reg soc_litedramcore_bankmachine6_cmd_valid = 1'd0;
+reg soc_litedramcore_bankmachine6_cmd_ready = 1'd0;
+reg [13:0] soc_litedramcore_bankmachine6_cmd_payload_a = 14'd0;
+wire [2:0] soc_litedramcore_bankmachine6_cmd_payload_ba;
+reg soc_litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
+reg soc_litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
+reg soc_litedramcore_bankmachine6_cmd_payload_we = 1'd0;
+reg soc_litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
+reg soc_litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
+reg soc_litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
+reg soc_litedramcore_bankmachine6_auto_precharge = 1'd0;
+wire soc_litedramcore_bankmachine6_sink_valid;
+wire soc_litedramcore_bankmachine6_sink_ready;
+reg soc_litedramcore_bankmachine6_sink_first = 1'd0;
+reg soc_litedramcore_bankmachine6_sink_last = 1'd0;
+wire soc_litedramcore_bankmachine6_sink_payload_we;
+wire [20:0] soc_litedramcore_bankmachine6_sink_payload_addr;
+wire soc_litedramcore_bankmachine6_source_valid;
+wire soc_litedramcore_bankmachine6_source_ready;
+wire soc_litedramcore_bankmachine6_source_first;
+wire soc_litedramcore_bankmachine6_source_last;
+wire soc_litedramcore_bankmachine6_source_payload_we;
+wire [20:0] soc_litedramcore_bankmachine6_source_payload_addr;
+wire soc_litedramcore_bankmachine6_syncfifo6_we;
+wire soc_litedramcore_bankmachine6_syncfifo6_writable;
+wire soc_litedramcore_bankmachine6_syncfifo6_re;
+wire soc_litedramcore_bankmachine6_syncfifo6_readable;
+wire [23:0] soc_litedramcore_bankmachine6_syncfifo6_din;
+wire [23:0] soc_litedramcore_bankmachine6_syncfifo6_dout;
+reg [4:0] soc_litedramcore_bankmachine6_level = 5'd0;
+reg soc_litedramcore_bankmachine6_replace = 1'd0;
+reg [3:0] soc_litedramcore_bankmachine6_produce = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine6_consume = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine6_wrport_adr = 4'd0;
+wire [23:0] soc_litedramcore_bankmachine6_wrport_dat_r;
+wire soc_litedramcore_bankmachine6_wrport_we;
+wire [23:0] soc_litedramcore_bankmachine6_wrport_dat_w;
+wire soc_litedramcore_bankmachine6_do_read;
+wire [3:0] soc_litedramcore_bankmachine6_rdport_adr;
+wire [23:0] soc_litedramcore_bankmachine6_rdport_dat_r;
+wire soc_litedramcore_bankmachine6_fifo_in_payload_we;
+wire [20:0] soc_litedramcore_bankmachine6_fifo_in_payload_addr;
+wire soc_litedramcore_bankmachine6_fifo_in_first;
+wire soc_litedramcore_bankmachine6_fifo_in_last;
+wire soc_litedramcore_bankmachine6_fifo_out_payload_we;
+wire [20:0] soc_litedramcore_bankmachine6_fifo_out_payload_addr;
+wire soc_litedramcore_bankmachine6_fifo_out_first;
+wire soc_litedramcore_bankmachine6_fifo_out_last;
+wire soc_litedramcore_bankmachine6_sink_sink_valid;
+wire soc_litedramcore_bankmachine6_sink_sink_ready;
+wire soc_litedramcore_bankmachine6_sink_sink_first;
+wire soc_litedramcore_bankmachine6_sink_sink_last;
+wire soc_litedramcore_bankmachine6_sink_sink_payload_we;
+wire [20:0] soc_litedramcore_bankmachine6_sink_sink_payload_addr;
+wire soc_litedramcore_bankmachine6_source_source_valid;
+wire soc_litedramcore_bankmachine6_source_source_ready;
+wire soc_litedramcore_bankmachine6_source_source_first;
+wire soc_litedramcore_bankmachine6_source_source_last;
+wire soc_litedramcore_bankmachine6_source_source_payload_we;
+wire [20:0] soc_litedramcore_bankmachine6_source_source_payload_addr;
+wire soc_litedramcore_bankmachine6_pipe_valid_sink_valid;
+wire soc_litedramcore_bankmachine6_pipe_valid_sink_ready;
+wire soc_litedramcore_bankmachine6_pipe_valid_sink_first;
+wire soc_litedramcore_bankmachine6_pipe_valid_sink_last;
+wire soc_litedramcore_bankmachine6_pipe_valid_sink_payload_we;
+wire [20:0] soc_litedramcore_bankmachine6_pipe_valid_sink_payload_addr;
+reg soc_litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0;
+wire soc_litedramcore_bankmachine6_pipe_valid_source_ready;
+reg soc_litedramcore_bankmachine6_pipe_valid_source_first = 1'd0;
+reg soc_litedramcore_bankmachine6_pipe_valid_source_last = 1'd0;
+reg soc_litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0;
+reg [20:0] soc_litedramcore_bankmachine6_pipe_valid_source_payload_addr = 21'd0;
+reg [13:0] soc_litedramcore_bankmachine6_row = 14'd0;
+reg soc_litedramcore_bankmachine6_row_opened = 1'd0;
+wire soc_litedramcore_bankmachine6_row_hit;
+reg soc_litedramcore_bankmachine6_row_open = 1'd0;
+reg soc_litedramcore_bankmachine6_row_close = 1'd0;
+reg soc_litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
+wire soc_litedramcore_bankmachine6_twtpcon_valid;
+reg soc_litedramcore_bankmachine6_twtpcon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine6_twtpcon_count = 3'd0;
+wire soc_litedramcore_bankmachine6_trccon_valid;
+reg soc_litedramcore_bankmachine6_trccon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine6_trccon_count = 3'd0;
+wire soc_litedramcore_bankmachine6_trascon_valid;
+reg soc_litedramcore_bankmachine6_trascon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine6_trascon_count = 3'd0;
+wire soc_litedramcore_bankmachine7_req_valid;
+wire soc_litedramcore_bankmachine7_req_ready;
+wire soc_litedramcore_bankmachine7_req_we;
+wire [20:0] soc_litedramcore_bankmachine7_req_addr;
+wire soc_litedramcore_bankmachine7_req_lock;
+reg soc_litedramcore_bankmachine7_req_wdata_ready = 1'd0;
+reg soc_litedramcore_bankmachine7_req_rdata_valid = 1'd0;
+wire soc_litedramcore_bankmachine7_refresh_req;
+reg soc_litedramcore_bankmachine7_refresh_gnt = 1'd0;
+reg soc_litedramcore_bankmachine7_cmd_valid = 1'd0;
+reg soc_litedramcore_bankmachine7_cmd_ready = 1'd0;
+reg [13:0] soc_litedramcore_bankmachine7_cmd_payload_a = 14'd0;
+wire [2:0] soc_litedramcore_bankmachine7_cmd_payload_ba;
+reg soc_litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
+reg soc_litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
+reg soc_litedramcore_bankmachine7_cmd_payload_we = 1'd0;
+reg soc_litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
+reg soc_litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
+reg soc_litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
+reg soc_litedramcore_bankmachine7_auto_precharge = 1'd0;
+wire soc_litedramcore_bankmachine7_sink_valid;
+wire soc_litedramcore_bankmachine7_sink_ready;
+reg soc_litedramcore_bankmachine7_sink_first = 1'd0;
+reg soc_litedramcore_bankmachine7_sink_last = 1'd0;
+wire soc_litedramcore_bankmachine7_sink_payload_we;
+wire [20:0] soc_litedramcore_bankmachine7_sink_payload_addr;
+wire soc_litedramcore_bankmachine7_source_valid;
+wire soc_litedramcore_bankmachine7_source_ready;
+wire soc_litedramcore_bankmachine7_source_first;
+wire soc_litedramcore_bankmachine7_source_last;
+wire soc_litedramcore_bankmachine7_source_payload_we;
+wire [20:0] soc_litedramcore_bankmachine7_source_payload_addr;
+wire soc_litedramcore_bankmachine7_syncfifo7_we;
+wire soc_litedramcore_bankmachine7_syncfifo7_writable;
+wire soc_litedramcore_bankmachine7_syncfifo7_re;
+wire soc_litedramcore_bankmachine7_syncfifo7_readable;
+wire [23:0] soc_litedramcore_bankmachine7_syncfifo7_din;
+wire [23:0] soc_litedramcore_bankmachine7_syncfifo7_dout;
+reg [4:0] soc_litedramcore_bankmachine7_level = 5'd0;
+reg soc_litedramcore_bankmachine7_replace = 1'd0;
+reg [3:0] soc_litedramcore_bankmachine7_produce = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine7_consume = 4'd0;
+reg [3:0] soc_litedramcore_bankmachine7_wrport_adr = 4'd0;
+wire [23:0] soc_litedramcore_bankmachine7_wrport_dat_r;
+wire soc_litedramcore_bankmachine7_wrport_we;
+wire [23:0] soc_litedramcore_bankmachine7_wrport_dat_w;
+wire soc_litedramcore_bankmachine7_do_read;
+wire [3:0] soc_litedramcore_bankmachine7_rdport_adr;
+wire [23:0] soc_litedramcore_bankmachine7_rdport_dat_r;
+wire soc_litedramcore_bankmachine7_fifo_in_payload_we;
+wire [20:0] soc_litedramcore_bankmachine7_fifo_in_payload_addr;
+wire soc_litedramcore_bankmachine7_fifo_in_first;
+wire soc_litedramcore_bankmachine7_fifo_in_last;
+wire soc_litedramcore_bankmachine7_fifo_out_payload_we;
+wire [20:0] soc_litedramcore_bankmachine7_fifo_out_payload_addr;
+wire soc_litedramcore_bankmachine7_fifo_out_first;
+wire soc_litedramcore_bankmachine7_fifo_out_last;
+wire soc_litedramcore_bankmachine7_sink_sink_valid;
+wire soc_litedramcore_bankmachine7_sink_sink_ready;
+wire soc_litedramcore_bankmachine7_sink_sink_first;
+wire soc_litedramcore_bankmachine7_sink_sink_last;
+wire soc_litedramcore_bankmachine7_sink_sink_payload_we;
+wire [20:0] soc_litedramcore_bankmachine7_sink_sink_payload_addr;
+wire soc_litedramcore_bankmachine7_source_source_valid;
+wire soc_litedramcore_bankmachine7_source_source_ready;
+wire soc_litedramcore_bankmachine7_source_source_first;
+wire soc_litedramcore_bankmachine7_source_source_last;
+wire soc_litedramcore_bankmachine7_source_source_payload_we;
+wire [20:0] soc_litedramcore_bankmachine7_source_source_payload_addr;
+wire soc_litedramcore_bankmachine7_pipe_valid_sink_valid;
+wire soc_litedramcore_bankmachine7_pipe_valid_sink_ready;
+wire soc_litedramcore_bankmachine7_pipe_valid_sink_first;
+wire soc_litedramcore_bankmachine7_pipe_valid_sink_last;
+wire soc_litedramcore_bankmachine7_pipe_valid_sink_payload_we;
+wire [20:0] soc_litedramcore_bankmachine7_pipe_valid_sink_payload_addr;
+reg soc_litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0;
+wire soc_litedramcore_bankmachine7_pipe_valid_source_ready;
+reg soc_litedramcore_bankmachine7_pipe_valid_source_first = 1'd0;
+reg soc_litedramcore_bankmachine7_pipe_valid_source_last = 1'd0;
+reg soc_litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0;
+reg [20:0] soc_litedramcore_bankmachine7_pipe_valid_source_payload_addr = 21'd0;
+reg [13:0] soc_litedramcore_bankmachine7_row = 14'd0;
+reg soc_litedramcore_bankmachine7_row_opened = 1'd0;
+wire soc_litedramcore_bankmachine7_row_hit;
+reg soc_litedramcore_bankmachine7_row_open = 1'd0;
+reg soc_litedramcore_bankmachine7_row_close = 1'd0;
+reg soc_litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
+wire soc_litedramcore_bankmachine7_twtpcon_valid;
+reg soc_litedramcore_bankmachine7_twtpcon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine7_twtpcon_count = 3'd0;
+wire soc_litedramcore_bankmachine7_trccon_valid;
+reg soc_litedramcore_bankmachine7_trccon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine7_trccon_count = 3'd0;
+wire soc_litedramcore_bankmachine7_trascon_valid;
+reg soc_litedramcore_bankmachine7_trascon_ready = 1'd0;
+reg [2:0] soc_litedramcore_bankmachine7_trascon_count = 3'd0;
+wire soc_litedramcore_ras_allowed;
+wire soc_litedramcore_cas_allowed;
+reg soc_litedramcore_choose_cmd_want_reads = 1'd0;
+reg soc_litedramcore_choose_cmd_want_writes = 1'd0;
+reg soc_litedramcore_choose_cmd_want_cmds = 1'd0;
+reg soc_litedramcore_choose_cmd_want_activates = 1'd0;
+wire soc_litedramcore_choose_cmd_cmd_valid;
+reg soc_litedramcore_choose_cmd_cmd_ready = 1'd0;
+wire [13:0] soc_litedramcore_choose_cmd_cmd_payload_a;
+wire [2:0] soc_litedramcore_choose_cmd_cmd_payload_ba;
+reg soc_litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
+reg soc_litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
+reg soc_litedramcore_choose_cmd_cmd_payload_we = 1'd0;
+wire soc_litedramcore_choose_cmd_cmd_payload_is_cmd;
+wire soc_litedramcore_choose_cmd_cmd_payload_is_read;
+wire soc_litedramcore_choose_cmd_cmd_payload_is_write;
+reg [7:0] soc_litedramcore_choose_cmd_valids = 8'd0;
+wire [7:0] soc_litedramcore_choose_cmd_request;
+reg [2:0] soc_litedramcore_choose_cmd_grant = 3'd0;
+wire soc_litedramcore_choose_cmd_ce;
+reg soc_litedramcore_choose_req_want_reads = 1'd0;
+reg soc_litedramcore_choose_req_want_writes = 1'd0;
+reg soc_litedramcore_choose_req_want_cmds = 1'd0;
+reg soc_litedramcore_choose_req_want_activates = 1'd0;
+wire soc_litedramcore_choose_req_cmd_valid;
+reg soc_litedramcore_choose_req_cmd_ready = 1'd0;
+wire [13:0] soc_litedramcore_choose_req_cmd_payload_a;
+wire [2:0] soc_litedramcore_choose_req_cmd_payload_ba;
+reg soc_litedramcore_choose_req_cmd_payload_cas = 1'd0;
+reg soc_litedramcore_choose_req_cmd_payload_ras = 1'd0;
+reg soc_litedramcore_choose_req_cmd_payload_we = 1'd0;
+wire soc_litedramcore_choose_req_cmd_payload_is_cmd;
+wire soc_litedramcore_choose_req_cmd_payload_is_read;
+wire soc_litedramcore_choose_req_cmd_payload_is_write;
+reg [7:0] soc_litedramcore_choose_req_valids = 8'd0;
+wire [7:0] soc_litedramcore_choose_req_request;
+reg [2:0] soc_litedramcore_choose_req_grant = 3'd0;
+wire soc_litedramcore_choose_req_ce;
+reg [13:0] soc_litedramcore_nop_a = 14'd0;
+reg [2:0] soc_litedramcore_nop_ba = 3'd0;
+reg [1:0] soc_litedramcore_steerer_sel0 = 2'd0;
+reg [1:0] soc_litedramcore_steerer_sel1 = 2'd0;
+reg [1:0] soc_litedramcore_steerer_sel2 = 2'd0;
+reg [1:0] soc_litedramcore_steerer_sel3 = 2'd0;
+reg soc_litedramcore_steerer0 = 1'd1;
+reg soc_litedramcore_steerer1 = 1'd1;
+reg soc_litedramcore_steerer2 = 1'd1;
+reg soc_litedramcore_steerer3 = 1'd1;
+reg soc_litedramcore_steerer4 = 1'd1;
+reg soc_litedramcore_steerer5 = 1'd1;
+reg soc_litedramcore_steerer6 = 1'd1;
+reg soc_litedramcore_steerer7 = 1'd1;
+wire soc_litedramcore_trrdcon_valid;
+reg soc_litedramcore_trrdcon_ready = 1'd0;
+reg soc_litedramcore_trrdcon_count = 1'd0;
+wire soc_litedramcore_tfawcon_valid;
+reg soc_litedramcore_tfawcon_ready = 1'd1;
+wire [2:0] soc_litedramcore_tfawcon_count;
+reg [4:0] soc_litedramcore_tfawcon_window = 5'd0;
+wire soc_litedramcore_tccdcon_valid;
+reg soc_litedramcore_tccdcon_ready = 1'd0;
+reg soc_litedramcore_tccdcon_count = 1'd0;
+wire soc_litedramcore_twtrcon_valid;
+reg soc_litedramcore_twtrcon_ready = 1'd0;
+reg [2:0] soc_litedramcore_twtrcon_count = 3'd0;
+wire soc_litedramcore_read_available;
+wire soc_litedramcore_write_available;
+reg soc_litedramcore_en0 = 1'd0;
+wire soc_litedramcore_max_time0;
+reg [4:0] soc_litedramcore_time0 = 5'd0;
+reg soc_litedramcore_en1 = 1'd0;
+wire soc_litedramcore_max_time1;
+reg [3:0] soc_litedramcore_time1 = 4'd0;
+wire soc_litedramcore_go_to_refresh;
+reg soc_init_done_storage = 1'd0;
+reg soc_init_done_re = 1'd0;
+reg soc_init_error_storage = 1'd0;
+reg soc_init_error_re = 1'd0;
+wire [29:0] soc_wb_bus_adr;
+wire [31:0] soc_wb_bus_dat_w;
+wire [31:0] soc_wb_bus_dat_r;
+wire [3:0] soc_wb_bus_sel;
+wire soc_wb_bus_cyc;
+wire soc_wb_bus_stb;
+wire soc_wb_bus_ack;
+wire soc_wb_bus_we;
+wire [2:0] soc_wb_bus_cti;
+wire [1:0] soc_wb_bus_bte;
+wire soc_wb_bus_err;
+wire soc_user_enable;
+wire soc_user_port_cmd_valid;
+wire soc_user_port_cmd_ready;
+wire soc_user_port_cmd_payload_we;
+wire [23:0] soc_user_port_cmd_payload_addr;
+wire soc_user_port_wdata_valid;
+wire soc_user_port_wdata_ready;
+wire [127:0] soc_user_port_wdata_payload_data;
+wire [15:0] soc_user_port_wdata_payload_we;
+wire soc_user_port_rdata_valid;
+wire soc_user_port_rdata_ready;
+wire [127:0] soc_user_port_rdata_payload_data;
+reg [13:0] litedramcore_adr = 14'd0;
+reg litedramcore_we = 1'd0;
+reg [31:0] litedramcore_dat_w = 32'd0;
+wire [31:0] litedramcore_dat_r;
+wire [29:0] litedramcore_wishbone_adr;
+wire [31:0] litedramcore_wishbone_dat_w;
+reg [31:0] litedramcore_wishbone_dat_r = 32'd0;
+wire [3:0] litedramcore_wishbone_sel;
+wire litedramcore_wishbone_cyc;
+wire litedramcore_wishbone_stb;
+reg litedramcore_wishbone_ack = 1'd0;
+wire litedramcore_wishbone_we;
+wire [2:0] litedramcore_wishbone_cti;
+wire [1:0] litedramcore_wishbone_bte;
+reg litedramcore_wishbone_err = 1'd0;
+wire [13:0] interface0_bank_bus_adr;
+wire interface0_bank_bus_we;
+wire [31:0] interface0_bank_bus_dat_w;
+reg [31:0] interface0_bank_bus_dat_r = 32'd0;
+reg csrbank0_init_done0_re = 1'd0;
+wire csrbank0_init_done0_r;
+reg csrbank0_init_done0_we = 1'd0;
+wire csrbank0_init_done0_w;
+reg csrbank0_init_error0_re = 1'd0;
+wire csrbank0_init_error0_r;
+reg csrbank0_init_error0_we = 1'd0;
+wire csrbank0_init_error0_w;
+wire csrbank0_sel;
+wire [13:0] interface1_bank_bus_adr;
+wire interface1_bank_bus_we;
+wire [31:0] interface1_bank_bus_dat_w;
+reg [31:0] interface1_bank_bus_dat_r = 32'd0;
+reg csrbank1_dfii_control0_re = 1'd0;
+wire [3:0] csrbank1_dfii_control0_r;
+reg csrbank1_dfii_control0_we = 1'd0;
+wire [3:0] csrbank1_dfii_control0_w;
+reg csrbank1_dfii_pi0_command0_re = 1'd0;
+wire [5:0] csrbank1_dfii_pi0_command0_r;
+reg csrbank1_dfii_pi0_command0_we = 1'd0;
+wire [5:0] csrbank1_dfii_pi0_command0_w;
+reg csrbank1_dfii_pi0_address0_re = 1'd0;
+wire [13:0] csrbank1_dfii_pi0_address0_r;
+reg csrbank1_dfii_pi0_address0_we = 1'd0;
+wire [13:0] csrbank1_dfii_pi0_address0_w;
+reg csrbank1_dfii_pi0_baddress0_re = 1'd0;
+wire [2:0] csrbank1_dfii_pi0_baddress0_r;
+reg csrbank1_dfii_pi0_baddress0_we = 1'd0;
+wire [2:0] csrbank1_dfii_pi0_baddress0_w;
+reg csrbank1_dfii_pi0_wrdata0_re = 1'd0;
+wire [31:0] csrbank1_dfii_pi0_wrdata0_r;
+reg csrbank1_dfii_pi0_wrdata0_we = 1'd0;
+wire [31:0] csrbank1_dfii_pi0_wrdata0_w;
+reg csrbank1_dfii_pi0_rddata_re = 1'd0;
+wire [31:0] csrbank1_dfii_pi0_rddata_r;
+reg csrbank1_dfii_pi0_rddata_we = 1'd0;
+wire [31:0] csrbank1_dfii_pi0_rddata_w;
+reg csrbank1_dfii_pi1_command0_re = 1'd0;
+wire [5:0] csrbank1_dfii_pi1_command0_r;
+reg csrbank1_dfii_pi1_command0_we = 1'd0;
+wire [5:0] csrbank1_dfii_pi1_command0_w;
+reg csrbank1_dfii_pi1_address0_re = 1'd0;
+wire [13:0] csrbank1_dfii_pi1_address0_r;
+reg csrbank1_dfii_pi1_address0_we = 1'd0;
+wire [13:0] csrbank1_dfii_pi1_address0_w;
+reg csrbank1_dfii_pi1_baddress0_re = 1'd0;
+wire [2:0] csrbank1_dfii_pi1_baddress0_r;
+reg csrbank1_dfii_pi1_baddress0_we = 1'd0;
+wire [2:0] csrbank1_dfii_pi1_baddress0_w;
+reg csrbank1_dfii_pi1_wrdata0_re = 1'd0;
+wire [31:0] csrbank1_dfii_pi1_wrdata0_r;
+reg csrbank1_dfii_pi1_wrdata0_we = 1'd0;
+wire [31:0] csrbank1_dfii_pi1_wrdata0_w;
+reg csrbank1_dfii_pi1_rddata_re = 1'd0;
+wire [31:0] csrbank1_dfii_pi1_rddata_r;
+reg csrbank1_dfii_pi1_rddata_we = 1'd0;
+wire [31:0] csrbank1_dfii_pi1_rddata_w;
+reg csrbank1_dfii_pi2_command0_re = 1'd0;
+wire [5:0] csrbank1_dfii_pi2_command0_r;
+reg csrbank1_dfii_pi2_command0_we = 1'd0;
+wire [5:0] csrbank1_dfii_pi2_command0_w;
+reg csrbank1_dfii_pi2_address0_re = 1'd0;
+wire [13:0] csrbank1_dfii_pi2_address0_r;
+reg csrbank1_dfii_pi2_address0_we = 1'd0;
+wire [13:0] csrbank1_dfii_pi2_address0_w;
+reg csrbank1_dfii_pi2_baddress0_re = 1'd0;
+wire [2:0] csrbank1_dfii_pi2_baddress0_r;
+reg csrbank1_dfii_pi2_baddress0_we = 1'd0;
+wire [2:0] csrbank1_dfii_pi2_baddress0_w;
+reg csrbank1_dfii_pi2_wrdata0_re = 1'd0;
+wire [31:0] csrbank1_dfii_pi2_wrdata0_r;
+reg csrbank1_dfii_pi2_wrdata0_we = 1'd0;
+wire [31:0] csrbank1_dfii_pi2_wrdata0_w;
+reg csrbank1_dfii_pi2_rddata_re = 1'd0;
+wire [31:0] csrbank1_dfii_pi2_rddata_r;
+reg csrbank1_dfii_pi2_rddata_we = 1'd0;
+wire [31:0] csrbank1_dfii_pi2_rddata_w;
+reg csrbank1_dfii_pi3_command0_re = 1'd0;
+wire [5:0] csrbank1_dfii_pi3_command0_r;
+reg csrbank1_dfii_pi3_command0_we = 1'd0;
+wire [5:0] csrbank1_dfii_pi3_command0_w;
+reg csrbank1_dfii_pi3_address0_re = 1'd0;
+wire [13:0] csrbank1_dfii_pi3_address0_r;
+reg csrbank1_dfii_pi3_address0_we = 1'd0;
+wire [13:0] csrbank1_dfii_pi3_address0_w;
+reg csrbank1_dfii_pi3_baddress0_re = 1'd0;
+wire [2:0] csrbank1_dfii_pi3_baddress0_r;
+reg csrbank1_dfii_pi3_baddress0_we = 1'd0;
+wire [2:0] csrbank1_dfii_pi3_baddress0_w;
+reg csrbank1_dfii_pi3_wrdata0_re = 1'd0;
+wire [31:0] csrbank1_dfii_pi3_wrdata0_r;
+reg csrbank1_dfii_pi3_wrdata0_we = 1'd0;
+wire [31:0] csrbank1_dfii_pi3_wrdata0_w;
+reg csrbank1_dfii_pi3_rddata_re = 1'd0;
+wire [31:0] csrbank1_dfii_pi3_rddata_r;
+reg csrbank1_dfii_pi3_rddata_we = 1'd0;
+wire [31:0] csrbank1_dfii_pi3_rddata_w;
+wire csrbank1_sel;
+wire [13:0] csr_interconnect_adr;
+wire csr_interconnect_we;
+wire [31:0] csr_interconnect_dat_w;
+wire [31:0] csr_interconnect_dat_r;
+reg [1:0] litedramcore_refresher_state = 2'd0;
+reg [1:0] litedramcore_refresher_next_state = 2'd0;
+reg [3:0] litedramcore_bankmachine0_state = 4'd0;
+reg [3:0] litedramcore_bankmachine0_next_state = 4'd0;
+reg [3:0] litedramcore_bankmachine1_state = 4'd0;
+reg [3:0] litedramcore_bankmachine1_next_state = 4'd0;
+reg [3:0] litedramcore_bankmachine2_state = 4'd0;
+reg [3:0] litedramcore_bankmachine2_next_state = 4'd0;
+reg [3:0] litedramcore_bankmachine3_state = 4'd0;
+reg [3:0] litedramcore_bankmachine3_next_state = 4'd0;
+reg [3:0] litedramcore_bankmachine4_state = 4'd0;
+reg [3:0] litedramcore_bankmachine4_next_state = 4'd0;
+reg [3:0] litedramcore_bankmachine5_state = 4'd0;
+reg [3:0] litedramcore_bankmachine5_next_state = 4'd0;
+reg [3:0] litedramcore_bankmachine6_state = 4'd0;
+reg [3:0] litedramcore_bankmachine6_next_state = 4'd0;
+reg [3:0] litedramcore_bankmachine7_state = 4'd0;
+reg [3:0] litedramcore_bankmachine7_next_state = 4'd0;
+reg [3:0] litedramcore_multiplexer_state = 4'd0;
+reg [3:0] litedramcore_multiplexer_next_state = 4'd0;
+wire litedramcore_roundrobin0_request;
+wire litedramcore_roundrobin0_grant;
+wire litedramcore_roundrobin0_ce;
+wire litedramcore_roundrobin1_request;
+wire litedramcore_roundrobin1_grant;
+wire litedramcore_roundrobin1_ce;
+wire litedramcore_roundrobin2_request;
+wire litedramcore_roundrobin2_grant;
+wire litedramcore_roundrobin2_ce;
+wire litedramcore_roundrobin3_request;
+wire litedramcore_roundrobin3_grant;
+wire litedramcore_roundrobin3_ce;
+wire litedramcore_roundrobin4_request;
+wire litedramcore_roundrobin4_grant;
+wire litedramcore_roundrobin4_ce;
+wire litedramcore_roundrobin5_request;
+wire litedramcore_roundrobin5_grant;
+wire litedramcore_roundrobin5_ce;
+wire litedramcore_roundrobin6_request;
+wire litedramcore_roundrobin6_grant;
+wire litedramcore_roundrobin6_ce;
+wire litedramcore_roundrobin7_request;
+wire litedramcore_roundrobin7_grant;
+wire litedramcore_roundrobin7_ce;
+reg litedramcore_locked0 = 1'd0;
+reg litedramcore_locked1 = 1'd0;
+reg litedramcore_locked2 = 1'd0;
+reg litedramcore_locked3 = 1'd0;
+reg litedramcore_locked4 = 1'd0;
+reg litedramcore_locked5 = 1'd0;
+reg litedramcore_locked6 = 1'd0;
+reg litedramcore_locked7 = 1'd0;
+reg litedramcore_new_master_wdata_ready0 = 1'd0;
+reg litedramcore_new_master_wdata_ready1 = 1'd0;
+reg litedramcore_new_master_rdata_valid0 = 1'd0;
+reg litedramcore_new_master_rdata_valid1 = 1'd0;
+reg litedramcore_new_master_rdata_valid2 = 1'd0;
+reg litedramcore_new_master_rdata_valid3 = 1'd0;
+reg litedramcore_new_master_rdata_valid4 = 1'd0;
+reg litedramcore_new_master_rdata_valid5 = 1'd0;
+reg litedramcore_new_master_rdata_valid6 = 1'd0;
+reg litedramcore_new_master_rdata_valid7 = 1'd0;
+reg litedramcore_new_master_rdata_valid8 = 1'd0;
+reg [1:0] litedramcore_state = 2'd0;
+reg [1:0] litedramcore_next_state = 2'd0;
+reg [31:0] litedramcore_dat_w_next_value0 = 32'd0;
+reg litedramcore_dat_w_next_value_ce0 = 1'd0;
+reg [13:0] litedramcore_adr_next_value1 = 14'd0;
+reg litedramcore_adr_next_value_ce1 = 1'd0;
+reg litedramcore_we_next_value2 = 1'd0;
+reg litedramcore_we_next_value_ce2 = 1'd0;
+wire [24:0] slice_proxy0;
+wire [24:0] slice_proxy1;
+wire [24:0] slice_proxy2;
+wire [24:0] slice_proxy3;
+wire [24:0] slice_proxy4;
+wire [24:0] slice_proxy5;
+wire [24:0] slice_proxy6;
+wire [24:0] slice_proxy7;
+wire [24:0] slice_proxy8;
+wire [24:0] slice_proxy9;
+wire [24:0] slice_proxy10;
+wire [24:0] slice_proxy11;
+wire [24:0] slice_proxy12;
+wire [24:0] slice_proxy13;
+wire [24:0] slice_proxy14;
+wire [24:0] slice_proxy15;
+reg rhs_array_muxed0 = 1'd0;
+reg [13:0] rhs_array_muxed1 = 14'd0;
+reg [2:0] rhs_array_muxed2 = 3'd0;
+reg rhs_array_muxed3 = 1'd0;
+reg rhs_array_muxed4 = 1'd0;
+reg rhs_array_muxed5 = 1'd0;
+reg t_array_muxed0 = 1'd0;
+reg t_array_muxed1 = 1'd0;
+reg t_array_muxed2 = 1'd0;
+reg rhs_array_muxed6 = 1'd0;
+reg [13:0] rhs_array_muxed7 = 14'd0;
+reg [2:0] rhs_array_muxed8 = 3'd0;
+reg rhs_array_muxed9 = 1'd0;
+reg rhs_array_muxed10 = 1'd0;
+reg rhs_array_muxed11 = 1'd0;
+reg t_array_muxed3 = 1'd0;
+reg t_array_muxed4 = 1'd0;
+reg t_array_muxed5 = 1'd0;
+reg [20:0] rhs_array_muxed12 = 21'd0;
+reg rhs_array_muxed13 = 1'd0;
+reg rhs_array_muxed14 = 1'd0;
+reg [20:0] rhs_array_muxed15 = 21'd0;
+reg rhs_array_muxed16 = 1'd0;
+reg rhs_array_muxed17 = 1'd0;
+reg [20:0] rhs_array_muxed18 = 21'd0;
+reg rhs_array_muxed19 = 1'd0;
+reg rhs_array_muxed20 = 1'd0;
+reg [20:0] rhs_array_muxed21 = 21'd0;
+reg rhs_array_muxed22 = 1'd0;
+reg rhs_array_muxed23 = 1'd0;
+reg [20:0] rhs_array_muxed24 = 21'd0;
+reg rhs_array_muxed25 = 1'd0;
+reg rhs_array_muxed26 = 1'd0;
+reg [20:0] rhs_array_muxed27 = 21'd0;
+reg rhs_array_muxed28 = 1'd0;
+reg rhs_array_muxed29 = 1'd0;
+reg [20:0] rhs_array_muxed30 = 21'd0;
+reg rhs_array_muxed31 = 1'd0;
+reg rhs_array_muxed32 = 1'd0;
+reg [20:0] rhs_array_muxed33 = 21'd0;
+reg rhs_array_muxed34 = 1'd0;
+reg rhs_array_muxed35 = 1'd0;
+reg [2:0] array_muxed0 = 3'd0;
+reg [13:0] array_muxed1 = 14'd0;
+reg array_muxed2 = 1'd0;
+reg array_muxed3 = 1'd0;
+reg array_muxed4 = 1'd0;
+reg array_muxed5 = 1'd0;
+reg array_muxed6 = 1'd0;
+reg [2:0] array_muxed7 = 3'd0;
+reg [13:0] array_muxed8 = 14'd0;
+reg array_muxed9 = 1'd0;
+reg array_muxed10 = 1'd0;
+reg array_muxed11 = 1'd0;
+reg array_muxed12 = 1'd0;
+reg array_muxed13 = 1'd0;
+reg [2:0] array_muxed14 = 3'd0;
+reg [13:0] array_muxed15 = 14'd0;
+reg array_muxed16 = 1'd0;
+reg array_muxed17 = 1'd0;
+reg array_muxed18 = 1'd0;
+reg array_muxed19 = 1'd0;
+reg array_muxed20 = 1'd0;
+reg [2:0] array_muxed21 = 3'd0;
+reg [13:0] array_muxed22 = 14'd0;
+reg array_muxed23 = 1'd0;
+reg array_muxed24 = 1'd0;
+reg array_muxed25 = 1'd0;
+reg array_muxed26 = 1'd0;
+reg array_muxed27 = 1'd0;
//------------------------------------------------------------------------------
// Combinatorial Logic
assign por_clk = clk;
assign sys_rst = soc_int_rst;
always @(*) begin
- soc_ddrphy_activates0 <= 4'd0;
- soc_ddrphy_activates0[0] <= soc_ddrphy_dfiphasemodel0_activate;
- soc_ddrphy_activates0[1] <= soc_ddrphy_dfiphasemodel1_activate;
- soc_ddrphy_activates0[2] <= soc_ddrphy_dfiphasemodel2_activate;
- soc_ddrphy_activates0[3] <= soc_ddrphy_dfiphasemodel3_activate;
-end
-always @(*) begin
- soc_ddrphy_bankmodel0_activate_row <= 14'd0;
- case (soc_ddrphy_activates0)
- 1'd1: begin
- soc_ddrphy_bankmodel0_activate_row <= soc_ddrphy_dfi_p0_address;
- end
- 2'd2: begin
- soc_ddrphy_bankmodel0_activate_row <= soc_ddrphy_dfi_p1_address;
- end
- 3'd4: begin
- soc_ddrphy_bankmodel0_activate_row <= soc_ddrphy_dfi_p2_address;
- end
- 4'd8: begin
- soc_ddrphy_bankmodel0_activate_row <= soc_ddrphy_dfi_p3_address;
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_bankmodel0_activate <= 1'd0;
- case (soc_ddrphy_activates0)
- 1'd1: begin
- soc_ddrphy_bankmodel0_activate <= (soc_ddrphy_dfi_p0_bank == 1'd0);
- end
- 2'd2: begin
- soc_ddrphy_bankmodel0_activate <= (soc_ddrphy_dfi_p1_bank == 1'd0);
- end
- 3'd4: begin
- soc_ddrphy_bankmodel0_activate <= (soc_ddrphy_dfi_p2_bank == 1'd0);
- end
- 4'd8: begin
- soc_ddrphy_bankmodel0_activate <= (soc_ddrphy_dfi_p3_bank == 1'd0);
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_precharges0 <= 4'd0;
- soc_ddrphy_precharges0[0] <= soc_ddrphy_dfiphasemodel0_precharge;
- soc_ddrphy_precharges0[1] <= soc_ddrphy_dfiphasemodel1_precharge;
- soc_ddrphy_precharges0[2] <= soc_ddrphy_dfiphasemodel2_precharge;
- soc_ddrphy_precharges0[3] <= soc_ddrphy_dfiphasemodel3_precharge;
-end
-always @(*) begin
- soc_ddrphy_bankmodel0_precharge <= 1'd0;
- case (soc_ddrphy_precharges0)
- 1'd1: begin
- soc_ddrphy_bankmodel0_precharge <= ((soc_ddrphy_dfi_p0_bank == 1'd0) | soc_ddrphy_dfi_p0_address[10]);
- end
- 2'd2: begin
- soc_ddrphy_bankmodel0_precharge <= ((soc_ddrphy_dfi_p1_bank == 1'd0) | soc_ddrphy_dfi_p1_address[10]);
- end
- 3'd4: begin
- soc_ddrphy_bankmodel0_precharge <= ((soc_ddrphy_dfi_p2_bank == 1'd0) | soc_ddrphy_dfi_p2_address[10]);
- end
- 4'd8: begin
- soc_ddrphy_bankmodel0_precharge <= ((soc_ddrphy_dfi_p3_bank == 1'd0) | soc_ddrphy_dfi_p3_address[10]);
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_writes0 <= 4'd0;
- soc_ddrphy_writes0[0] <= soc_ddrphy_dfiphasemodel0_write;
- soc_ddrphy_writes0[1] <= soc_ddrphy_dfiphasemodel1_write;
- soc_ddrphy_writes0[2] <= soc_ddrphy_dfiphasemodel2_write;
- soc_ddrphy_writes0[3] <= soc_ddrphy_dfiphasemodel3_write;
-end
-always @(*) begin
- soc_ddrphy_bank_write0 <= 1'd0;
- case (soc_ddrphy_writes0)
- 1'd1: begin
- soc_ddrphy_bank_write0 <= (soc_ddrphy_dfi_p0_bank == 1'd0);
- end
- 2'd2: begin
- soc_ddrphy_bank_write0 <= (soc_ddrphy_dfi_p1_bank == 1'd0);
- end
- 3'd4: begin
- soc_ddrphy_bank_write0 <= (soc_ddrphy_dfi_p2_bank == 1'd0);
- end
- 4'd8: begin
- soc_ddrphy_bank_write0 <= (soc_ddrphy_dfi_p3_bank == 1'd0);
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_bank_write_col0 <= 10'd0;
- case (soc_ddrphy_writes0)
- 1'd1: begin
- soc_ddrphy_bank_write_col0 <= soc_ddrphy_dfi_p0_address;
- end
- 2'd2: begin
- soc_ddrphy_bank_write_col0 <= soc_ddrphy_dfi_p1_address;
- end
- 3'd4: begin
- soc_ddrphy_bank_write_col0 <= soc_ddrphy_dfi_p2_address;
- end
- 4'd8: begin
- soc_ddrphy_bank_write_col0 <= soc_ddrphy_dfi_p3_address;
- end
- endcase
+ soc_ddrphy_activates0 <= 4'd0;
+ soc_ddrphy_activates0[0] <= soc_ddrphy_dfiphasemodel0_activate;
+ soc_ddrphy_activates0[1] <= soc_ddrphy_dfiphasemodel1_activate;
+ soc_ddrphy_activates0[2] <= soc_ddrphy_dfiphasemodel2_activate;
+ soc_ddrphy_activates0[3] <= soc_ddrphy_dfiphasemodel3_activate;
+end
+always @(*) begin
+ soc_ddrphy_bankmodel0_activate_row <= 14'd0;
+ case (soc_ddrphy_activates0)
+ 1'd1: begin
+ soc_ddrphy_bankmodel0_activate_row <= soc_ddrphy_dfi_p0_address;
+ end
+ 2'd2: begin
+ soc_ddrphy_bankmodel0_activate_row <= soc_ddrphy_dfi_p1_address;
+ end
+ 3'd4: begin
+ soc_ddrphy_bankmodel0_activate_row <= soc_ddrphy_dfi_p2_address;
+ end
+ 4'd8: begin
+ soc_ddrphy_bankmodel0_activate_row <= soc_ddrphy_dfi_p3_address;
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_bankmodel0_activate <= 1'd0;
+ case (soc_ddrphy_activates0)
+ 1'd1: begin
+ soc_ddrphy_bankmodel0_activate <= (soc_ddrphy_dfi_p0_bank == 1'd0);
+ end
+ 2'd2: begin
+ soc_ddrphy_bankmodel0_activate <= (soc_ddrphy_dfi_p1_bank == 1'd0);
+ end
+ 3'd4: begin
+ soc_ddrphy_bankmodel0_activate <= (soc_ddrphy_dfi_p2_bank == 1'd0);
+ end
+ 4'd8: begin
+ soc_ddrphy_bankmodel0_activate <= (soc_ddrphy_dfi_p3_bank == 1'd0);
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_precharges0 <= 4'd0;
+ soc_ddrphy_precharges0[0] <= soc_ddrphy_dfiphasemodel0_precharge;
+ soc_ddrphy_precharges0[1] <= soc_ddrphy_dfiphasemodel1_precharge;
+ soc_ddrphy_precharges0[2] <= soc_ddrphy_dfiphasemodel2_precharge;
+ soc_ddrphy_precharges0[3] <= soc_ddrphy_dfiphasemodel3_precharge;
+end
+always @(*) begin
+ soc_ddrphy_bankmodel0_precharge <= 1'd0;
+ case (soc_ddrphy_precharges0)
+ 1'd1: begin
+ soc_ddrphy_bankmodel0_precharge <= ((soc_ddrphy_dfi_p0_bank == 1'd0) | soc_ddrphy_dfi_p0_address[10]);
+ end
+ 2'd2: begin
+ soc_ddrphy_bankmodel0_precharge <= ((soc_ddrphy_dfi_p1_bank == 1'd0) | soc_ddrphy_dfi_p1_address[10]);
+ end
+ 3'd4: begin
+ soc_ddrphy_bankmodel0_precharge <= ((soc_ddrphy_dfi_p2_bank == 1'd0) | soc_ddrphy_dfi_p2_address[10]);
+ end
+ 4'd8: begin
+ soc_ddrphy_bankmodel0_precharge <= ((soc_ddrphy_dfi_p3_bank == 1'd0) | soc_ddrphy_dfi_p3_address[10]);
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_writes0 <= 4'd0;
+ soc_ddrphy_writes0[0] <= soc_ddrphy_dfiphasemodel0_write;
+ soc_ddrphy_writes0[1] <= soc_ddrphy_dfiphasemodel1_write;
+ soc_ddrphy_writes0[2] <= soc_ddrphy_dfiphasemodel2_write;
+ soc_ddrphy_writes0[3] <= soc_ddrphy_dfiphasemodel3_write;
+end
+always @(*) begin
+ soc_ddrphy_bank_write0 <= 1'd0;
+ case (soc_ddrphy_writes0)
+ 1'd1: begin
+ soc_ddrphy_bank_write0 <= (soc_ddrphy_dfi_p0_bank == 1'd0);
+ end
+ 2'd2: begin
+ soc_ddrphy_bank_write0 <= (soc_ddrphy_dfi_p1_bank == 1'd0);
+ end
+ 3'd4: begin
+ soc_ddrphy_bank_write0 <= (soc_ddrphy_dfi_p2_bank == 1'd0);
+ end
+ 4'd8: begin
+ soc_ddrphy_bank_write0 <= (soc_ddrphy_dfi_p3_bank == 1'd0);
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_bank_write_col0 <= 10'd0;
+ case (soc_ddrphy_writes0)
+ 1'd1: begin
+ soc_ddrphy_bank_write_col0 <= soc_ddrphy_dfi_p0_address;
+ end
+ 2'd2: begin
+ soc_ddrphy_bank_write_col0 <= soc_ddrphy_dfi_p1_address;
+ end
+ 3'd4: begin
+ soc_ddrphy_bank_write_col0 <= soc_ddrphy_dfi_p2_address;
+ end
+ 4'd8: begin
+ soc_ddrphy_bank_write_col0 <= soc_ddrphy_dfi_p3_address;
+ end
+ endcase
end
assign soc_ddrphy_bankmodel0_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata};
assign soc_ddrphy_bankmodel0_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask};
assign soc_ddrphy_bankmodel0_write = soc_ddrphy_new_bank_write0;
assign soc_ddrphy_bankmodel0_write_col = soc_ddrphy_new_bank_write_col0;
always @(*) begin
- soc_ddrphy_reads0 <= 4'd0;
- soc_ddrphy_reads0[0] <= soc_ddrphy_dfiphasemodel0_read;
- soc_ddrphy_reads0[1] <= soc_ddrphy_dfiphasemodel1_read;
- soc_ddrphy_reads0[2] <= soc_ddrphy_dfiphasemodel2_read;
- soc_ddrphy_reads0[3] <= soc_ddrphy_dfiphasemodel3_read;
-end
-always @(*) begin
- soc_ddrphy_bankmodel0_read <= 1'd0;
- case (soc_ddrphy_reads0)
- 1'd1: begin
- soc_ddrphy_bankmodel0_read <= (soc_ddrphy_dfi_p0_bank == 1'd0);
- end
- 2'd2: begin
- soc_ddrphy_bankmodel0_read <= (soc_ddrphy_dfi_p1_bank == 1'd0);
- end
- 3'd4: begin
- soc_ddrphy_bankmodel0_read <= (soc_ddrphy_dfi_p2_bank == 1'd0);
- end
- 4'd8: begin
- soc_ddrphy_bankmodel0_read <= (soc_ddrphy_dfi_p3_bank == 1'd0);
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_bankmodel0_read_col <= 10'd0;
- case (soc_ddrphy_reads0)
- 1'd1: begin
- soc_ddrphy_bankmodel0_read_col <= soc_ddrphy_dfi_p0_address;
- end
- 2'd2: begin
- soc_ddrphy_bankmodel0_read_col <= soc_ddrphy_dfi_p1_address;
- end
- 3'd4: begin
- soc_ddrphy_bankmodel0_read_col <= soc_ddrphy_dfi_p2_address;
- end
- 4'd8: begin
- soc_ddrphy_bankmodel0_read_col <= soc_ddrphy_dfi_p3_address;
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_activates1 <= 4'd0;
- soc_ddrphy_activates1[0] <= soc_ddrphy_dfiphasemodel0_activate;
- soc_ddrphy_activates1[1] <= soc_ddrphy_dfiphasemodel1_activate;
- soc_ddrphy_activates1[2] <= soc_ddrphy_dfiphasemodel2_activate;
- soc_ddrphy_activates1[3] <= soc_ddrphy_dfiphasemodel3_activate;
-end
-always @(*) begin
- soc_ddrphy_bankmodel1_activate <= 1'd0;
- case (soc_ddrphy_activates1)
- 1'd1: begin
- soc_ddrphy_bankmodel1_activate <= (soc_ddrphy_dfi_p0_bank == 1'd1);
- end
- 2'd2: begin
- soc_ddrphy_bankmodel1_activate <= (soc_ddrphy_dfi_p1_bank == 1'd1);
- end
- 3'd4: begin
- soc_ddrphy_bankmodel1_activate <= (soc_ddrphy_dfi_p2_bank == 1'd1);
- end
- 4'd8: begin
- soc_ddrphy_bankmodel1_activate <= (soc_ddrphy_dfi_p3_bank == 1'd1);
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_bankmodel1_activate_row <= 14'd0;
- case (soc_ddrphy_activates1)
- 1'd1: begin
- soc_ddrphy_bankmodel1_activate_row <= soc_ddrphy_dfi_p0_address;
- end
- 2'd2: begin
- soc_ddrphy_bankmodel1_activate_row <= soc_ddrphy_dfi_p1_address;
- end
- 3'd4: begin
- soc_ddrphy_bankmodel1_activate_row <= soc_ddrphy_dfi_p2_address;
- end
- 4'd8: begin
- soc_ddrphy_bankmodel1_activate_row <= soc_ddrphy_dfi_p3_address;
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_precharges1 <= 4'd0;
- soc_ddrphy_precharges1[0] <= soc_ddrphy_dfiphasemodel0_precharge;
- soc_ddrphy_precharges1[1] <= soc_ddrphy_dfiphasemodel1_precharge;
- soc_ddrphy_precharges1[2] <= soc_ddrphy_dfiphasemodel2_precharge;
- soc_ddrphy_precharges1[3] <= soc_ddrphy_dfiphasemodel3_precharge;
-end
-always @(*) begin
- soc_ddrphy_bankmodel1_precharge <= 1'd0;
- case (soc_ddrphy_precharges1)
- 1'd1: begin
- soc_ddrphy_bankmodel1_precharge <= ((soc_ddrphy_dfi_p0_bank == 1'd1) | soc_ddrphy_dfi_p0_address[10]);
- end
- 2'd2: begin
- soc_ddrphy_bankmodel1_precharge <= ((soc_ddrphy_dfi_p1_bank == 1'd1) | soc_ddrphy_dfi_p1_address[10]);
- end
- 3'd4: begin
- soc_ddrphy_bankmodel1_precharge <= ((soc_ddrphy_dfi_p2_bank == 1'd1) | soc_ddrphy_dfi_p2_address[10]);
- end
- 4'd8: begin
- soc_ddrphy_bankmodel1_precharge <= ((soc_ddrphy_dfi_p3_bank == 1'd1) | soc_ddrphy_dfi_p3_address[10]);
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_writes1 <= 4'd0;
- soc_ddrphy_writes1[0] <= soc_ddrphy_dfiphasemodel0_write;
- soc_ddrphy_writes1[1] <= soc_ddrphy_dfiphasemodel1_write;
- soc_ddrphy_writes1[2] <= soc_ddrphy_dfiphasemodel2_write;
- soc_ddrphy_writes1[3] <= soc_ddrphy_dfiphasemodel3_write;
-end
-always @(*) begin
- soc_ddrphy_bank_write1 <= 1'd0;
- case (soc_ddrphy_writes1)
- 1'd1: begin
- soc_ddrphy_bank_write1 <= (soc_ddrphy_dfi_p0_bank == 1'd1);
- end
- 2'd2: begin
- soc_ddrphy_bank_write1 <= (soc_ddrphy_dfi_p1_bank == 1'd1);
- end
- 3'd4: begin
- soc_ddrphy_bank_write1 <= (soc_ddrphy_dfi_p2_bank == 1'd1);
- end
- 4'd8: begin
- soc_ddrphy_bank_write1 <= (soc_ddrphy_dfi_p3_bank == 1'd1);
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_bank_write_col1 <= 10'd0;
- case (soc_ddrphy_writes1)
- 1'd1: begin
- soc_ddrphy_bank_write_col1 <= soc_ddrphy_dfi_p0_address;
- end
- 2'd2: begin
- soc_ddrphy_bank_write_col1 <= soc_ddrphy_dfi_p1_address;
- end
- 3'd4: begin
- soc_ddrphy_bank_write_col1 <= soc_ddrphy_dfi_p2_address;
- end
- 4'd8: begin
- soc_ddrphy_bank_write_col1 <= soc_ddrphy_dfi_p3_address;
- end
- endcase
+ soc_ddrphy_reads0 <= 4'd0;
+ soc_ddrphy_reads0[0] <= soc_ddrphy_dfiphasemodel0_read;
+ soc_ddrphy_reads0[1] <= soc_ddrphy_dfiphasemodel1_read;
+ soc_ddrphy_reads0[2] <= soc_ddrphy_dfiphasemodel2_read;
+ soc_ddrphy_reads0[3] <= soc_ddrphy_dfiphasemodel3_read;
+end
+always @(*) begin
+ soc_ddrphy_bankmodel0_read <= 1'd0;
+ case (soc_ddrphy_reads0)
+ 1'd1: begin
+ soc_ddrphy_bankmodel0_read <= (soc_ddrphy_dfi_p0_bank == 1'd0);
+ end
+ 2'd2: begin
+ soc_ddrphy_bankmodel0_read <= (soc_ddrphy_dfi_p1_bank == 1'd0);
+ end
+ 3'd4: begin
+ soc_ddrphy_bankmodel0_read <= (soc_ddrphy_dfi_p2_bank == 1'd0);
+ end
+ 4'd8: begin
+ soc_ddrphy_bankmodel0_read <= (soc_ddrphy_dfi_p3_bank == 1'd0);
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_bankmodel0_read_col <= 10'd0;
+ case (soc_ddrphy_reads0)
+ 1'd1: begin
+ soc_ddrphy_bankmodel0_read_col <= soc_ddrphy_dfi_p0_address;
+ end
+ 2'd2: begin
+ soc_ddrphy_bankmodel0_read_col <= soc_ddrphy_dfi_p1_address;
+ end
+ 3'd4: begin
+ soc_ddrphy_bankmodel0_read_col <= soc_ddrphy_dfi_p2_address;
+ end
+ 4'd8: begin
+ soc_ddrphy_bankmodel0_read_col <= soc_ddrphy_dfi_p3_address;
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_activates1 <= 4'd0;
+ soc_ddrphy_activates1[0] <= soc_ddrphy_dfiphasemodel0_activate;
+ soc_ddrphy_activates1[1] <= soc_ddrphy_dfiphasemodel1_activate;
+ soc_ddrphy_activates1[2] <= soc_ddrphy_dfiphasemodel2_activate;
+ soc_ddrphy_activates1[3] <= soc_ddrphy_dfiphasemodel3_activate;
+end
+always @(*) begin
+ soc_ddrphy_bankmodel1_activate <= 1'd0;
+ case (soc_ddrphy_activates1)
+ 1'd1: begin
+ soc_ddrphy_bankmodel1_activate <= (soc_ddrphy_dfi_p0_bank == 1'd1);
+ end
+ 2'd2: begin
+ soc_ddrphy_bankmodel1_activate <= (soc_ddrphy_dfi_p1_bank == 1'd1);
+ end
+ 3'd4: begin
+ soc_ddrphy_bankmodel1_activate <= (soc_ddrphy_dfi_p2_bank == 1'd1);
+ end
+ 4'd8: begin
+ soc_ddrphy_bankmodel1_activate <= (soc_ddrphy_dfi_p3_bank == 1'd1);
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_bankmodel1_activate_row <= 14'd0;
+ case (soc_ddrphy_activates1)
+ 1'd1: begin
+ soc_ddrphy_bankmodel1_activate_row <= soc_ddrphy_dfi_p0_address;
+ end
+ 2'd2: begin
+ soc_ddrphy_bankmodel1_activate_row <= soc_ddrphy_dfi_p1_address;
+ end
+ 3'd4: begin
+ soc_ddrphy_bankmodel1_activate_row <= soc_ddrphy_dfi_p2_address;
+ end
+ 4'd8: begin
+ soc_ddrphy_bankmodel1_activate_row <= soc_ddrphy_dfi_p3_address;
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_precharges1 <= 4'd0;
+ soc_ddrphy_precharges1[0] <= soc_ddrphy_dfiphasemodel0_precharge;
+ soc_ddrphy_precharges1[1] <= soc_ddrphy_dfiphasemodel1_precharge;
+ soc_ddrphy_precharges1[2] <= soc_ddrphy_dfiphasemodel2_precharge;
+ soc_ddrphy_precharges1[3] <= soc_ddrphy_dfiphasemodel3_precharge;
+end
+always @(*) begin
+ soc_ddrphy_bankmodel1_precharge <= 1'd0;
+ case (soc_ddrphy_precharges1)
+ 1'd1: begin
+ soc_ddrphy_bankmodel1_precharge <= ((soc_ddrphy_dfi_p0_bank == 1'd1) | soc_ddrphy_dfi_p0_address[10]);
+ end
+ 2'd2: begin
+ soc_ddrphy_bankmodel1_precharge <= ((soc_ddrphy_dfi_p1_bank == 1'd1) | soc_ddrphy_dfi_p1_address[10]);
+ end
+ 3'd4: begin
+ soc_ddrphy_bankmodel1_precharge <= ((soc_ddrphy_dfi_p2_bank == 1'd1) | soc_ddrphy_dfi_p2_address[10]);
+ end
+ 4'd8: begin
+ soc_ddrphy_bankmodel1_precharge <= ((soc_ddrphy_dfi_p3_bank == 1'd1) | soc_ddrphy_dfi_p3_address[10]);
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_writes1 <= 4'd0;
+ soc_ddrphy_writes1[0] <= soc_ddrphy_dfiphasemodel0_write;
+ soc_ddrphy_writes1[1] <= soc_ddrphy_dfiphasemodel1_write;
+ soc_ddrphy_writes1[2] <= soc_ddrphy_dfiphasemodel2_write;
+ soc_ddrphy_writes1[3] <= soc_ddrphy_dfiphasemodel3_write;
+end
+always @(*) begin
+ soc_ddrphy_bank_write1 <= 1'd0;
+ case (soc_ddrphy_writes1)
+ 1'd1: begin
+ soc_ddrphy_bank_write1 <= (soc_ddrphy_dfi_p0_bank == 1'd1);
+ end
+ 2'd2: begin
+ soc_ddrphy_bank_write1 <= (soc_ddrphy_dfi_p1_bank == 1'd1);
+ end
+ 3'd4: begin
+ soc_ddrphy_bank_write1 <= (soc_ddrphy_dfi_p2_bank == 1'd1);
+ end
+ 4'd8: begin
+ soc_ddrphy_bank_write1 <= (soc_ddrphy_dfi_p3_bank == 1'd1);
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_bank_write_col1 <= 10'd0;
+ case (soc_ddrphy_writes1)
+ 1'd1: begin
+ soc_ddrphy_bank_write_col1 <= soc_ddrphy_dfi_p0_address;
+ end
+ 2'd2: begin
+ soc_ddrphy_bank_write_col1 <= soc_ddrphy_dfi_p1_address;
+ end
+ 3'd4: begin
+ soc_ddrphy_bank_write_col1 <= soc_ddrphy_dfi_p2_address;
+ end
+ 4'd8: begin
+ soc_ddrphy_bank_write_col1 <= soc_ddrphy_dfi_p3_address;
+ end
+ endcase
end
assign soc_ddrphy_bankmodel1_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata};
assign soc_ddrphy_bankmodel1_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask};
assign soc_ddrphy_bankmodel1_write = soc_ddrphy_new_bank_write1;
assign soc_ddrphy_bankmodel1_write_col = soc_ddrphy_new_bank_write_col1;
always @(*) begin
- soc_ddrphy_reads1 <= 4'd0;
- soc_ddrphy_reads1[0] <= soc_ddrphy_dfiphasemodel0_read;
- soc_ddrphy_reads1[1] <= soc_ddrphy_dfiphasemodel1_read;
- soc_ddrphy_reads1[2] <= soc_ddrphy_dfiphasemodel2_read;
- soc_ddrphy_reads1[3] <= soc_ddrphy_dfiphasemodel3_read;
-end
-always @(*) begin
- soc_ddrphy_bankmodel1_read_col <= 10'd0;
- case (soc_ddrphy_reads1)
- 1'd1: begin
- soc_ddrphy_bankmodel1_read_col <= soc_ddrphy_dfi_p0_address;
- end
- 2'd2: begin
- soc_ddrphy_bankmodel1_read_col <= soc_ddrphy_dfi_p1_address;
- end
- 3'd4: begin
- soc_ddrphy_bankmodel1_read_col <= soc_ddrphy_dfi_p2_address;
- end
- 4'd8: begin
- soc_ddrphy_bankmodel1_read_col <= soc_ddrphy_dfi_p3_address;
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_bankmodel1_read <= 1'd0;
- case (soc_ddrphy_reads1)
- 1'd1: begin
- soc_ddrphy_bankmodel1_read <= (soc_ddrphy_dfi_p0_bank == 1'd1);
- end
- 2'd2: begin
- soc_ddrphy_bankmodel1_read <= (soc_ddrphy_dfi_p1_bank == 1'd1);
- end
- 3'd4: begin
- soc_ddrphy_bankmodel1_read <= (soc_ddrphy_dfi_p2_bank == 1'd1);
- end
- 4'd8: begin
- soc_ddrphy_bankmodel1_read <= (soc_ddrphy_dfi_p3_bank == 1'd1);
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_activates2 <= 4'd0;
- soc_ddrphy_activates2[0] <= soc_ddrphy_dfiphasemodel0_activate;
- soc_ddrphy_activates2[1] <= soc_ddrphy_dfiphasemodel1_activate;
- soc_ddrphy_activates2[2] <= soc_ddrphy_dfiphasemodel2_activate;
- soc_ddrphy_activates2[3] <= soc_ddrphy_dfiphasemodel3_activate;
-end
-always @(*) begin
- soc_ddrphy_bankmodel2_activate <= 1'd0;
- case (soc_ddrphy_activates2)
- 1'd1: begin
- soc_ddrphy_bankmodel2_activate <= (soc_ddrphy_dfi_p0_bank == 2'd2);
- end
- 2'd2: begin
- soc_ddrphy_bankmodel2_activate <= (soc_ddrphy_dfi_p1_bank == 2'd2);
- end
- 3'd4: begin
- soc_ddrphy_bankmodel2_activate <= (soc_ddrphy_dfi_p2_bank == 2'd2);
- end
- 4'd8: begin
- soc_ddrphy_bankmodel2_activate <= (soc_ddrphy_dfi_p3_bank == 2'd2);
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_bankmodel2_activate_row <= 14'd0;
- case (soc_ddrphy_activates2)
- 1'd1: begin
- soc_ddrphy_bankmodel2_activate_row <= soc_ddrphy_dfi_p0_address;
- end
- 2'd2: begin
- soc_ddrphy_bankmodel2_activate_row <= soc_ddrphy_dfi_p1_address;
- end
- 3'd4: begin
- soc_ddrphy_bankmodel2_activate_row <= soc_ddrphy_dfi_p2_address;
- end
- 4'd8: begin
- soc_ddrphy_bankmodel2_activate_row <= soc_ddrphy_dfi_p3_address;
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_precharges2 <= 4'd0;
- soc_ddrphy_precharges2[0] <= soc_ddrphy_dfiphasemodel0_precharge;
- soc_ddrphy_precharges2[1] <= soc_ddrphy_dfiphasemodel1_precharge;
- soc_ddrphy_precharges2[2] <= soc_ddrphy_dfiphasemodel2_precharge;
- soc_ddrphy_precharges2[3] <= soc_ddrphy_dfiphasemodel3_precharge;
-end
-always @(*) begin
- soc_ddrphy_bankmodel2_precharge <= 1'd0;
- case (soc_ddrphy_precharges2)
- 1'd1: begin
- soc_ddrphy_bankmodel2_precharge <= ((soc_ddrphy_dfi_p0_bank == 2'd2) | soc_ddrphy_dfi_p0_address[10]);
- end
- 2'd2: begin
- soc_ddrphy_bankmodel2_precharge <= ((soc_ddrphy_dfi_p1_bank == 2'd2) | soc_ddrphy_dfi_p1_address[10]);
- end
- 3'd4: begin
- soc_ddrphy_bankmodel2_precharge <= ((soc_ddrphy_dfi_p2_bank == 2'd2) | soc_ddrphy_dfi_p2_address[10]);
- end
- 4'd8: begin
- soc_ddrphy_bankmodel2_precharge <= ((soc_ddrphy_dfi_p3_bank == 2'd2) | soc_ddrphy_dfi_p3_address[10]);
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_writes2 <= 4'd0;
- soc_ddrphy_writes2[0] <= soc_ddrphy_dfiphasemodel0_write;
- soc_ddrphy_writes2[1] <= soc_ddrphy_dfiphasemodel1_write;
- soc_ddrphy_writes2[2] <= soc_ddrphy_dfiphasemodel2_write;
- soc_ddrphy_writes2[3] <= soc_ddrphy_dfiphasemodel3_write;
-end
-always @(*) begin
- soc_ddrphy_bank_write_col2 <= 10'd0;
- case (soc_ddrphy_writes2)
- 1'd1: begin
- soc_ddrphy_bank_write_col2 <= soc_ddrphy_dfi_p0_address;
- end
- 2'd2: begin
- soc_ddrphy_bank_write_col2 <= soc_ddrphy_dfi_p1_address;
- end
- 3'd4: begin
- soc_ddrphy_bank_write_col2 <= soc_ddrphy_dfi_p2_address;
- end
- 4'd8: begin
- soc_ddrphy_bank_write_col2 <= soc_ddrphy_dfi_p3_address;
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_bank_write2 <= 1'd0;
- case (soc_ddrphy_writes2)
- 1'd1: begin
- soc_ddrphy_bank_write2 <= (soc_ddrphy_dfi_p0_bank == 2'd2);
- end
- 2'd2: begin
- soc_ddrphy_bank_write2 <= (soc_ddrphy_dfi_p1_bank == 2'd2);
- end
- 3'd4: begin
- soc_ddrphy_bank_write2 <= (soc_ddrphy_dfi_p2_bank == 2'd2);
- end
- 4'd8: begin
- soc_ddrphy_bank_write2 <= (soc_ddrphy_dfi_p3_bank == 2'd2);
- end
- endcase
+ soc_ddrphy_reads1 <= 4'd0;
+ soc_ddrphy_reads1[0] <= soc_ddrphy_dfiphasemodel0_read;
+ soc_ddrphy_reads1[1] <= soc_ddrphy_dfiphasemodel1_read;
+ soc_ddrphy_reads1[2] <= soc_ddrphy_dfiphasemodel2_read;
+ soc_ddrphy_reads1[3] <= soc_ddrphy_dfiphasemodel3_read;
+end
+always @(*) begin
+ soc_ddrphy_bankmodel1_read_col <= 10'd0;
+ case (soc_ddrphy_reads1)
+ 1'd1: begin
+ soc_ddrphy_bankmodel1_read_col <= soc_ddrphy_dfi_p0_address;
+ end
+ 2'd2: begin
+ soc_ddrphy_bankmodel1_read_col <= soc_ddrphy_dfi_p1_address;
+ end
+ 3'd4: begin
+ soc_ddrphy_bankmodel1_read_col <= soc_ddrphy_dfi_p2_address;
+ end
+ 4'd8: begin
+ soc_ddrphy_bankmodel1_read_col <= soc_ddrphy_dfi_p3_address;
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_bankmodel1_read <= 1'd0;
+ case (soc_ddrphy_reads1)
+ 1'd1: begin
+ soc_ddrphy_bankmodel1_read <= (soc_ddrphy_dfi_p0_bank == 1'd1);
+ end
+ 2'd2: begin
+ soc_ddrphy_bankmodel1_read <= (soc_ddrphy_dfi_p1_bank == 1'd1);
+ end
+ 3'd4: begin
+ soc_ddrphy_bankmodel1_read <= (soc_ddrphy_dfi_p2_bank == 1'd1);
+ end
+ 4'd8: begin
+ soc_ddrphy_bankmodel1_read <= (soc_ddrphy_dfi_p3_bank == 1'd1);
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_activates2 <= 4'd0;
+ soc_ddrphy_activates2[0] <= soc_ddrphy_dfiphasemodel0_activate;
+ soc_ddrphy_activates2[1] <= soc_ddrphy_dfiphasemodel1_activate;
+ soc_ddrphy_activates2[2] <= soc_ddrphy_dfiphasemodel2_activate;
+ soc_ddrphy_activates2[3] <= soc_ddrphy_dfiphasemodel3_activate;
+end
+always @(*) begin
+ soc_ddrphy_bankmodel2_activate <= 1'd0;
+ case (soc_ddrphy_activates2)
+ 1'd1: begin
+ soc_ddrphy_bankmodel2_activate <= (soc_ddrphy_dfi_p0_bank == 2'd2);
+ end
+ 2'd2: begin
+ soc_ddrphy_bankmodel2_activate <= (soc_ddrphy_dfi_p1_bank == 2'd2);
+ end
+ 3'd4: begin
+ soc_ddrphy_bankmodel2_activate <= (soc_ddrphy_dfi_p2_bank == 2'd2);
+ end
+ 4'd8: begin
+ soc_ddrphy_bankmodel2_activate <= (soc_ddrphy_dfi_p3_bank == 2'd2);
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_bankmodel2_activate_row <= 14'd0;
+ case (soc_ddrphy_activates2)
+ 1'd1: begin
+ soc_ddrphy_bankmodel2_activate_row <= soc_ddrphy_dfi_p0_address;
+ end
+ 2'd2: begin
+ soc_ddrphy_bankmodel2_activate_row <= soc_ddrphy_dfi_p1_address;
+ end
+ 3'd4: begin
+ soc_ddrphy_bankmodel2_activate_row <= soc_ddrphy_dfi_p2_address;
+ end
+ 4'd8: begin
+ soc_ddrphy_bankmodel2_activate_row <= soc_ddrphy_dfi_p3_address;
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_precharges2 <= 4'd0;
+ soc_ddrphy_precharges2[0] <= soc_ddrphy_dfiphasemodel0_precharge;
+ soc_ddrphy_precharges2[1] <= soc_ddrphy_dfiphasemodel1_precharge;
+ soc_ddrphy_precharges2[2] <= soc_ddrphy_dfiphasemodel2_precharge;
+ soc_ddrphy_precharges2[3] <= soc_ddrphy_dfiphasemodel3_precharge;
+end
+always @(*) begin
+ soc_ddrphy_bankmodel2_precharge <= 1'd0;
+ case (soc_ddrphy_precharges2)
+ 1'd1: begin
+ soc_ddrphy_bankmodel2_precharge <= ((soc_ddrphy_dfi_p0_bank == 2'd2) | soc_ddrphy_dfi_p0_address[10]);
+ end
+ 2'd2: begin
+ soc_ddrphy_bankmodel2_precharge <= ((soc_ddrphy_dfi_p1_bank == 2'd2) | soc_ddrphy_dfi_p1_address[10]);
+ end
+ 3'd4: begin
+ soc_ddrphy_bankmodel2_precharge <= ((soc_ddrphy_dfi_p2_bank == 2'd2) | soc_ddrphy_dfi_p2_address[10]);
+ end
+ 4'd8: begin
+ soc_ddrphy_bankmodel2_precharge <= ((soc_ddrphy_dfi_p3_bank == 2'd2) | soc_ddrphy_dfi_p3_address[10]);
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_writes2 <= 4'd0;
+ soc_ddrphy_writes2[0] <= soc_ddrphy_dfiphasemodel0_write;
+ soc_ddrphy_writes2[1] <= soc_ddrphy_dfiphasemodel1_write;
+ soc_ddrphy_writes2[2] <= soc_ddrphy_dfiphasemodel2_write;
+ soc_ddrphy_writes2[3] <= soc_ddrphy_dfiphasemodel3_write;
+end
+always @(*) begin
+ soc_ddrphy_bank_write_col2 <= 10'd0;
+ case (soc_ddrphy_writes2)
+ 1'd1: begin
+ soc_ddrphy_bank_write_col2 <= soc_ddrphy_dfi_p0_address;
+ end
+ 2'd2: begin
+ soc_ddrphy_bank_write_col2 <= soc_ddrphy_dfi_p1_address;
+ end
+ 3'd4: begin
+ soc_ddrphy_bank_write_col2 <= soc_ddrphy_dfi_p2_address;
+ end
+ 4'd8: begin
+ soc_ddrphy_bank_write_col2 <= soc_ddrphy_dfi_p3_address;
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_bank_write2 <= 1'd0;
+ case (soc_ddrphy_writes2)
+ 1'd1: begin
+ soc_ddrphy_bank_write2 <= (soc_ddrphy_dfi_p0_bank == 2'd2);
+ end
+ 2'd2: begin
+ soc_ddrphy_bank_write2 <= (soc_ddrphy_dfi_p1_bank == 2'd2);
+ end
+ 3'd4: begin
+ soc_ddrphy_bank_write2 <= (soc_ddrphy_dfi_p2_bank == 2'd2);
+ end
+ 4'd8: begin
+ soc_ddrphy_bank_write2 <= (soc_ddrphy_dfi_p3_bank == 2'd2);
+ end
+ endcase
end
assign soc_ddrphy_bankmodel2_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata};
assign soc_ddrphy_bankmodel2_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask};
assign soc_ddrphy_bankmodel2_write = soc_ddrphy_new_bank_write2;
assign soc_ddrphy_bankmodel2_write_col = soc_ddrphy_new_bank_write_col2;
always @(*) begin
- soc_ddrphy_reads2 <= 4'd0;
- soc_ddrphy_reads2[0] <= soc_ddrphy_dfiphasemodel0_read;
- soc_ddrphy_reads2[1] <= soc_ddrphy_dfiphasemodel1_read;
- soc_ddrphy_reads2[2] <= soc_ddrphy_dfiphasemodel2_read;
- soc_ddrphy_reads2[3] <= soc_ddrphy_dfiphasemodel3_read;
-end
-always @(*) begin
- soc_ddrphy_bankmodel2_read <= 1'd0;
- case (soc_ddrphy_reads2)
- 1'd1: begin
- soc_ddrphy_bankmodel2_read <= (soc_ddrphy_dfi_p0_bank == 2'd2);
- end
- 2'd2: begin
- soc_ddrphy_bankmodel2_read <= (soc_ddrphy_dfi_p1_bank == 2'd2);
- end
- 3'd4: begin
- soc_ddrphy_bankmodel2_read <= (soc_ddrphy_dfi_p2_bank == 2'd2);
- end
- 4'd8: begin
- soc_ddrphy_bankmodel2_read <= (soc_ddrphy_dfi_p3_bank == 2'd2);
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_bankmodel2_read_col <= 10'd0;
- case (soc_ddrphy_reads2)
- 1'd1: begin
- soc_ddrphy_bankmodel2_read_col <= soc_ddrphy_dfi_p0_address;
- end
- 2'd2: begin
- soc_ddrphy_bankmodel2_read_col <= soc_ddrphy_dfi_p1_address;
- end
- 3'd4: begin
- soc_ddrphy_bankmodel2_read_col <= soc_ddrphy_dfi_p2_address;
- end
- 4'd8: begin
- soc_ddrphy_bankmodel2_read_col <= soc_ddrphy_dfi_p3_address;
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_activates3 <= 4'd0;
- soc_ddrphy_activates3[0] <= soc_ddrphy_dfiphasemodel0_activate;
- soc_ddrphy_activates3[1] <= soc_ddrphy_dfiphasemodel1_activate;
- soc_ddrphy_activates3[2] <= soc_ddrphy_dfiphasemodel2_activate;
- soc_ddrphy_activates3[3] <= soc_ddrphy_dfiphasemodel3_activate;
-end
-always @(*) begin
- soc_ddrphy_bankmodel3_activate_row <= 14'd0;
- case (soc_ddrphy_activates3)
- 1'd1: begin
- soc_ddrphy_bankmodel3_activate_row <= soc_ddrphy_dfi_p0_address;
- end
- 2'd2: begin
- soc_ddrphy_bankmodel3_activate_row <= soc_ddrphy_dfi_p1_address;
- end
- 3'd4: begin
- soc_ddrphy_bankmodel3_activate_row <= soc_ddrphy_dfi_p2_address;
- end
- 4'd8: begin
- soc_ddrphy_bankmodel3_activate_row <= soc_ddrphy_dfi_p3_address;
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_bankmodel3_activate <= 1'd0;
- case (soc_ddrphy_activates3)
- 1'd1: begin
- soc_ddrphy_bankmodel3_activate <= (soc_ddrphy_dfi_p0_bank == 2'd3);
- end
- 2'd2: begin
- soc_ddrphy_bankmodel3_activate <= (soc_ddrphy_dfi_p1_bank == 2'd3);
- end
- 3'd4: begin
- soc_ddrphy_bankmodel3_activate <= (soc_ddrphy_dfi_p2_bank == 2'd3);
- end
- 4'd8: begin
- soc_ddrphy_bankmodel3_activate <= (soc_ddrphy_dfi_p3_bank == 2'd3);
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_precharges3 <= 4'd0;
- soc_ddrphy_precharges3[0] <= soc_ddrphy_dfiphasemodel0_precharge;
- soc_ddrphy_precharges3[1] <= soc_ddrphy_dfiphasemodel1_precharge;
- soc_ddrphy_precharges3[2] <= soc_ddrphy_dfiphasemodel2_precharge;
- soc_ddrphy_precharges3[3] <= soc_ddrphy_dfiphasemodel3_precharge;
-end
-always @(*) begin
- soc_ddrphy_bankmodel3_precharge <= 1'd0;
- case (soc_ddrphy_precharges3)
- 1'd1: begin
- soc_ddrphy_bankmodel3_precharge <= ((soc_ddrphy_dfi_p0_bank == 2'd3) | soc_ddrphy_dfi_p0_address[10]);
- end
- 2'd2: begin
- soc_ddrphy_bankmodel3_precharge <= ((soc_ddrphy_dfi_p1_bank == 2'd3) | soc_ddrphy_dfi_p1_address[10]);
- end
- 3'd4: begin
- soc_ddrphy_bankmodel3_precharge <= ((soc_ddrphy_dfi_p2_bank == 2'd3) | soc_ddrphy_dfi_p2_address[10]);
- end
- 4'd8: begin
- soc_ddrphy_bankmodel3_precharge <= ((soc_ddrphy_dfi_p3_bank == 2'd3) | soc_ddrphy_dfi_p3_address[10]);
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_writes3 <= 4'd0;
- soc_ddrphy_writes3[0] <= soc_ddrphy_dfiphasemodel0_write;
- soc_ddrphy_writes3[1] <= soc_ddrphy_dfiphasemodel1_write;
- soc_ddrphy_writes3[2] <= soc_ddrphy_dfiphasemodel2_write;
- soc_ddrphy_writes3[3] <= soc_ddrphy_dfiphasemodel3_write;
-end
-always @(*) begin
- soc_ddrphy_bank_write3 <= 1'd0;
- case (soc_ddrphy_writes3)
- 1'd1: begin
- soc_ddrphy_bank_write3 <= (soc_ddrphy_dfi_p0_bank == 2'd3);
- end
- 2'd2: begin
- soc_ddrphy_bank_write3 <= (soc_ddrphy_dfi_p1_bank == 2'd3);
- end
- 3'd4: begin
- soc_ddrphy_bank_write3 <= (soc_ddrphy_dfi_p2_bank == 2'd3);
- end
- 4'd8: begin
- soc_ddrphy_bank_write3 <= (soc_ddrphy_dfi_p3_bank == 2'd3);
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_bank_write_col3 <= 10'd0;
- case (soc_ddrphy_writes3)
- 1'd1: begin
- soc_ddrphy_bank_write_col3 <= soc_ddrphy_dfi_p0_address;
- end
- 2'd2: begin
- soc_ddrphy_bank_write_col3 <= soc_ddrphy_dfi_p1_address;
- end
- 3'd4: begin
- soc_ddrphy_bank_write_col3 <= soc_ddrphy_dfi_p2_address;
- end
- 4'd8: begin
- soc_ddrphy_bank_write_col3 <= soc_ddrphy_dfi_p3_address;
- end
- endcase
+ soc_ddrphy_reads2 <= 4'd0;
+ soc_ddrphy_reads2[0] <= soc_ddrphy_dfiphasemodel0_read;
+ soc_ddrphy_reads2[1] <= soc_ddrphy_dfiphasemodel1_read;
+ soc_ddrphy_reads2[2] <= soc_ddrphy_dfiphasemodel2_read;
+ soc_ddrphy_reads2[3] <= soc_ddrphy_dfiphasemodel3_read;
+end
+always @(*) begin
+ soc_ddrphy_bankmodel2_read <= 1'd0;
+ case (soc_ddrphy_reads2)
+ 1'd1: begin
+ soc_ddrphy_bankmodel2_read <= (soc_ddrphy_dfi_p0_bank == 2'd2);
+ end
+ 2'd2: begin
+ soc_ddrphy_bankmodel2_read <= (soc_ddrphy_dfi_p1_bank == 2'd2);
+ end
+ 3'd4: begin
+ soc_ddrphy_bankmodel2_read <= (soc_ddrphy_dfi_p2_bank == 2'd2);
+ end
+ 4'd8: begin
+ soc_ddrphy_bankmodel2_read <= (soc_ddrphy_dfi_p3_bank == 2'd2);
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_bankmodel2_read_col <= 10'd0;
+ case (soc_ddrphy_reads2)
+ 1'd1: begin
+ soc_ddrphy_bankmodel2_read_col <= soc_ddrphy_dfi_p0_address;
+ end
+ 2'd2: begin
+ soc_ddrphy_bankmodel2_read_col <= soc_ddrphy_dfi_p1_address;
+ end
+ 3'd4: begin
+ soc_ddrphy_bankmodel2_read_col <= soc_ddrphy_dfi_p2_address;
+ end
+ 4'd8: begin
+ soc_ddrphy_bankmodel2_read_col <= soc_ddrphy_dfi_p3_address;
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_activates3 <= 4'd0;
+ soc_ddrphy_activates3[0] <= soc_ddrphy_dfiphasemodel0_activate;
+ soc_ddrphy_activates3[1] <= soc_ddrphy_dfiphasemodel1_activate;
+ soc_ddrphy_activates3[2] <= soc_ddrphy_dfiphasemodel2_activate;
+ soc_ddrphy_activates3[3] <= soc_ddrphy_dfiphasemodel3_activate;
+end
+always @(*) begin
+ soc_ddrphy_bankmodel3_activate_row <= 14'd0;
+ case (soc_ddrphy_activates3)
+ 1'd1: begin
+ soc_ddrphy_bankmodel3_activate_row <= soc_ddrphy_dfi_p0_address;
+ end
+ 2'd2: begin
+ soc_ddrphy_bankmodel3_activate_row <= soc_ddrphy_dfi_p1_address;
+ end
+ 3'd4: begin
+ soc_ddrphy_bankmodel3_activate_row <= soc_ddrphy_dfi_p2_address;
+ end
+ 4'd8: begin
+ soc_ddrphy_bankmodel3_activate_row <= soc_ddrphy_dfi_p3_address;
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_bankmodel3_activate <= 1'd0;
+ case (soc_ddrphy_activates3)
+ 1'd1: begin
+ soc_ddrphy_bankmodel3_activate <= (soc_ddrphy_dfi_p0_bank == 2'd3);
+ end
+ 2'd2: begin
+ soc_ddrphy_bankmodel3_activate <= (soc_ddrphy_dfi_p1_bank == 2'd3);
+ end
+ 3'd4: begin
+ soc_ddrphy_bankmodel3_activate <= (soc_ddrphy_dfi_p2_bank == 2'd3);
+ end
+ 4'd8: begin
+ soc_ddrphy_bankmodel3_activate <= (soc_ddrphy_dfi_p3_bank == 2'd3);
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_precharges3 <= 4'd0;
+ soc_ddrphy_precharges3[0] <= soc_ddrphy_dfiphasemodel0_precharge;
+ soc_ddrphy_precharges3[1] <= soc_ddrphy_dfiphasemodel1_precharge;
+ soc_ddrphy_precharges3[2] <= soc_ddrphy_dfiphasemodel2_precharge;
+ soc_ddrphy_precharges3[3] <= soc_ddrphy_dfiphasemodel3_precharge;
+end
+always @(*) begin
+ soc_ddrphy_bankmodel3_precharge <= 1'd0;
+ case (soc_ddrphy_precharges3)
+ 1'd1: begin
+ soc_ddrphy_bankmodel3_precharge <= ((soc_ddrphy_dfi_p0_bank == 2'd3) | soc_ddrphy_dfi_p0_address[10]);
+ end
+ 2'd2: begin
+ soc_ddrphy_bankmodel3_precharge <= ((soc_ddrphy_dfi_p1_bank == 2'd3) | soc_ddrphy_dfi_p1_address[10]);
+ end
+ 3'd4: begin
+ soc_ddrphy_bankmodel3_precharge <= ((soc_ddrphy_dfi_p2_bank == 2'd3) | soc_ddrphy_dfi_p2_address[10]);
+ end
+ 4'd8: begin
+ soc_ddrphy_bankmodel3_precharge <= ((soc_ddrphy_dfi_p3_bank == 2'd3) | soc_ddrphy_dfi_p3_address[10]);
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_writes3 <= 4'd0;
+ soc_ddrphy_writes3[0] <= soc_ddrphy_dfiphasemodel0_write;
+ soc_ddrphy_writes3[1] <= soc_ddrphy_dfiphasemodel1_write;
+ soc_ddrphy_writes3[2] <= soc_ddrphy_dfiphasemodel2_write;
+ soc_ddrphy_writes3[3] <= soc_ddrphy_dfiphasemodel3_write;
+end
+always @(*) begin
+ soc_ddrphy_bank_write3 <= 1'd0;
+ case (soc_ddrphy_writes3)
+ 1'd1: begin
+ soc_ddrphy_bank_write3 <= (soc_ddrphy_dfi_p0_bank == 2'd3);
+ end
+ 2'd2: begin
+ soc_ddrphy_bank_write3 <= (soc_ddrphy_dfi_p1_bank == 2'd3);
+ end
+ 3'd4: begin
+ soc_ddrphy_bank_write3 <= (soc_ddrphy_dfi_p2_bank == 2'd3);
+ end
+ 4'd8: begin
+ soc_ddrphy_bank_write3 <= (soc_ddrphy_dfi_p3_bank == 2'd3);
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_bank_write_col3 <= 10'd0;
+ case (soc_ddrphy_writes3)
+ 1'd1: begin
+ soc_ddrphy_bank_write_col3 <= soc_ddrphy_dfi_p0_address;
+ end
+ 2'd2: begin
+ soc_ddrphy_bank_write_col3 <= soc_ddrphy_dfi_p1_address;
+ end
+ 3'd4: begin
+ soc_ddrphy_bank_write_col3 <= soc_ddrphy_dfi_p2_address;
+ end
+ 4'd8: begin
+ soc_ddrphy_bank_write_col3 <= soc_ddrphy_dfi_p3_address;
+ end
+ endcase
end
assign soc_ddrphy_bankmodel3_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata};
assign soc_ddrphy_bankmodel3_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask};
assign soc_ddrphy_bankmodel3_write = soc_ddrphy_new_bank_write3;
assign soc_ddrphy_bankmodel3_write_col = soc_ddrphy_new_bank_write_col3;
always @(*) begin
- soc_ddrphy_reads3 <= 4'd0;
- soc_ddrphy_reads3[0] <= soc_ddrphy_dfiphasemodel0_read;
- soc_ddrphy_reads3[1] <= soc_ddrphy_dfiphasemodel1_read;
- soc_ddrphy_reads3[2] <= soc_ddrphy_dfiphasemodel2_read;
- soc_ddrphy_reads3[3] <= soc_ddrphy_dfiphasemodel3_read;
-end
-always @(*) begin
- soc_ddrphy_bankmodel3_read <= 1'd0;
- case (soc_ddrphy_reads3)
- 1'd1: begin
- soc_ddrphy_bankmodel3_read <= (soc_ddrphy_dfi_p0_bank == 2'd3);
- end
- 2'd2: begin
- soc_ddrphy_bankmodel3_read <= (soc_ddrphy_dfi_p1_bank == 2'd3);
- end
- 3'd4: begin
- soc_ddrphy_bankmodel3_read <= (soc_ddrphy_dfi_p2_bank == 2'd3);
- end
- 4'd8: begin
- soc_ddrphy_bankmodel3_read <= (soc_ddrphy_dfi_p3_bank == 2'd3);
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_bankmodel3_read_col <= 10'd0;
- case (soc_ddrphy_reads3)
- 1'd1: begin
- soc_ddrphy_bankmodel3_read_col <= soc_ddrphy_dfi_p0_address;
- end
- 2'd2: begin
- soc_ddrphy_bankmodel3_read_col <= soc_ddrphy_dfi_p1_address;
- end
- 3'd4: begin
- soc_ddrphy_bankmodel3_read_col <= soc_ddrphy_dfi_p2_address;
- end
- 4'd8: begin
- soc_ddrphy_bankmodel3_read_col <= soc_ddrphy_dfi_p3_address;
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_activates4 <= 4'd0;
- soc_ddrphy_activates4[0] <= soc_ddrphy_dfiphasemodel0_activate;
- soc_ddrphy_activates4[1] <= soc_ddrphy_dfiphasemodel1_activate;
- soc_ddrphy_activates4[2] <= soc_ddrphy_dfiphasemodel2_activate;
- soc_ddrphy_activates4[3] <= soc_ddrphy_dfiphasemodel3_activate;
-end
-always @(*) begin
- soc_ddrphy_bankmodel4_activate <= 1'd0;
- case (soc_ddrphy_activates4)
- 1'd1: begin
- soc_ddrphy_bankmodel4_activate <= (soc_ddrphy_dfi_p0_bank == 3'd4);
- end
- 2'd2: begin
- soc_ddrphy_bankmodel4_activate <= (soc_ddrphy_dfi_p1_bank == 3'd4);
- end
- 3'd4: begin
- soc_ddrphy_bankmodel4_activate <= (soc_ddrphy_dfi_p2_bank == 3'd4);
- end
- 4'd8: begin
- soc_ddrphy_bankmodel4_activate <= (soc_ddrphy_dfi_p3_bank == 3'd4);
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_bankmodel4_activate_row <= 14'd0;
- case (soc_ddrphy_activates4)
- 1'd1: begin
- soc_ddrphy_bankmodel4_activate_row <= soc_ddrphy_dfi_p0_address;
- end
- 2'd2: begin
- soc_ddrphy_bankmodel4_activate_row <= soc_ddrphy_dfi_p1_address;
- end
- 3'd4: begin
- soc_ddrphy_bankmodel4_activate_row <= soc_ddrphy_dfi_p2_address;
- end
- 4'd8: begin
- soc_ddrphy_bankmodel4_activate_row <= soc_ddrphy_dfi_p3_address;
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_precharges4 <= 4'd0;
- soc_ddrphy_precharges4[0] <= soc_ddrphy_dfiphasemodel0_precharge;
- soc_ddrphy_precharges4[1] <= soc_ddrphy_dfiphasemodel1_precharge;
- soc_ddrphy_precharges4[2] <= soc_ddrphy_dfiphasemodel2_precharge;
- soc_ddrphy_precharges4[3] <= soc_ddrphy_dfiphasemodel3_precharge;
-end
-always @(*) begin
- soc_ddrphy_bankmodel4_precharge <= 1'd0;
- case (soc_ddrphy_precharges4)
- 1'd1: begin
- soc_ddrphy_bankmodel4_precharge <= ((soc_ddrphy_dfi_p0_bank == 3'd4) | soc_ddrphy_dfi_p0_address[10]);
- end
- 2'd2: begin
- soc_ddrphy_bankmodel4_precharge <= ((soc_ddrphy_dfi_p1_bank == 3'd4) | soc_ddrphy_dfi_p1_address[10]);
- end
- 3'd4: begin
- soc_ddrphy_bankmodel4_precharge <= ((soc_ddrphy_dfi_p2_bank == 3'd4) | soc_ddrphy_dfi_p2_address[10]);
- end
- 4'd8: begin
- soc_ddrphy_bankmodel4_precharge <= ((soc_ddrphy_dfi_p3_bank == 3'd4) | soc_ddrphy_dfi_p3_address[10]);
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_writes4 <= 4'd0;
- soc_ddrphy_writes4[0] <= soc_ddrphy_dfiphasemodel0_write;
- soc_ddrphy_writes4[1] <= soc_ddrphy_dfiphasemodel1_write;
- soc_ddrphy_writes4[2] <= soc_ddrphy_dfiphasemodel2_write;
- soc_ddrphy_writes4[3] <= soc_ddrphy_dfiphasemodel3_write;
-end
-always @(*) begin
- soc_ddrphy_bank_write4 <= 1'd0;
- case (soc_ddrphy_writes4)
- 1'd1: begin
- soc_ddrphy_bank_write4 <= (soc_ddrphy_dfi_p0_bank == 3'd4);
- end
- 2'd2: begin
- soc_ddrphy_bank_write4 <= (soc_ddrphy_dfi_p1_bank == 3'd4);
- end
- 3'd4: begin
- soc_ddrphy_bank_write4 <= (soc_ddrphy_dfi_p2_bank == 3'd4);
- end
- 4'd8: begin
- soc_ddrphy_bank_write4 <= (soc_ddrphy_dfi_p3_bank == 3'd4);
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_bank_write_col4 <= 10'd0;
- case (soc_ddrphy_writes4)
- 1'd1: begin
- soc_ddrphy_bank_write_col4 <= soc_ddrphy_dfi_p0_address;
- end
- 2'd2: begin
- soc_ddrphy_bank_write_col4 <= soc_ddrphy_dfi_p1_address;
- end
- 3'd4: begin
- soc_ddrphy_bank_write_col4 <= soc_ddrphy_dfi_p2_address;
- end
- 4'd8: begin
- soc_ddrphy_bank_write_col4 <= soc_ddrphy_dfi_p3_address;
- end
- endcase
+ soc_ddrphy_reads3 <= 4'd0;
+ soc_ddrphy_reads3[0] <= soc_ddrphy_dfiphasemodel0_read;
+ soc_ddrphy_reads3[1] <= soc_ddrphy_dfiphasemodel1_read;
+ soc_ddrphy_reads3[2] <= soc_ddrphy_dfiphasemodel2_read;
+ soc_ddrphy_reads3[3] <= soc_ddrphy_dfiphasemodel3_read;
+end
+always @(*) begin
+ soc_ddrphy_bankmodel3_read <= 1'd0;
+ case (soc_ddrphy_reads3)
+ 1'd1: begin
+ soc_ddrphy_bankmodel3_read <= (soc_ddrphy_dfi_p0_bank == 2'd3);
+ end
+ 2'd2: begin
+ soc_ddrphy_bankmodel3_read <= (soc_ddrphy_dfi_p1_bank == 2'd3);
+ end
+ 3'd4: begin
+ soc_ddrphy_bankmodel3_read <= (soc_ddrphy_dfi_p2_bank == 2'd3);
+ end
+ 4'd8: begin
+ soc_ddrphy_bankmodel3_read <= (soc_ddrphy_dfi_p3_bank == 2'd3);
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_bankmodel3_read_col <= 10'd0;
+ case (soc_ddrphy_reads3)
+ 1'd1: begin
+ soc_ddrphy_bankmodel3_read_col <= soc_ddrphy_dfi_p0_address;
+ end
+ 2'd2: begin
+ soc_ddrphy_bankmodel3_read_col <= soc_ddrphy_dfi_p1_address;
+ end
+ 3'd4: begin
+ soc_ddrphy_bankmodel3_read_col <= soc_ddrphy_dfi_p2_address;
+ end
+ 4'd8: begin
+ soc_ddrphy_bankmodel3_read_col <= soc_ddrphy_dfi_p3_address;
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_activates4 <= 4'd0;
+ soc_ddrphy_activates4[0] <= soc_ddrphy_dfiphasemodel0_activate;
+ soc_ddrphy_activates4[1] <= soc_ddrphy_dfiphasemodel1_activate;
+ soc_ddrphy_activates4[2] <= soc_ddrphy_dfiphasemodel2_activate;
+ soc_ddrphy_activates4[3] <= soc_ddrphy_dfiphasemodel3_activate;
+end
+always @(*) begin
+ soc_ddrphy_bankmodel4_activate <= 1'd0;
+ case (soc_ddrphy_activates4)
+ 1'd1: begin
+ soc_ddrphy_bankmodel4_activate <= (soc_ddrphy_dfi_p0_bank == 3'd4);
+ end
+ 2'd2: begin
+ soc_ddrphy_bankmodel4_activate <= (soc_ddrphy_dfi_p1_bank == 3'd4);
+ end
+ 3'd4: begin
+ soc_ddrphy_bankmodel4_activate <= (soc_ddrphy_dfi_p2_bank == 3'd4);
+ end
+ 4'd8: begin
+ soc_ddrphy_bankmodel4_activate <= (soc_ddrphy_dfi_p3_bank == 3'd4);
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_bankmodel4_activate_row <= 14'd0;
+ case (soc_ddrphy_activates4)
+ 1'd1: begin
+ soc_ddrphy_bankmodel4_activate_row <= soc_ddrphy_dfi_p0_address;
+ end
+ 2'd2: begin
+ soc_ddrphy_bankmodel4_activate_row <= soc_ddrphy_dfi_p1_address;
+ end
+ 3'd4: begin
+ soc_ddrphy_bankmodel4_activate_row <= soc_ddrphy_dfi_p2_address;
+ end
+ 4'd8: begin
+ soc_ddrphy_bankmodel4_activate_row <= soc_ddrphy_dfi_p3_address;
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_precharges4 <= 4'd0;
+ soc_ddrphy_precharges4[0] <= soc_ddrphy_dfiphasemodel0_precharge;
+ soc_ddrphy_precharges4[1] <= soc_ddrphy_dfiphasemodel1_precharge;
+ soc_ddrphy_precharges4[2] <= soc_ddrphy_dfiphasemodel2_precharge;
+ soc_ddrphy_precharges4[3] <= soc_ddrphy_dfiphasemodel3_precharge;
+end
+always @(*) begin
+ soc_ddrphy_bankmodel4_precharge <= 1'd0;
+ case (soc_ddrphy_precharges4)
+ 1'd1: begin
+ soc_ddrphy_bankmodel4_precharge <= ((soc_ddrphy_dfi_p0_bank == 3'd4) | soc_ddrphy_dfi_p0_address[10]);
+ end
+ 2'd2: begin
+ soc_ddrphy_bankmodel4_precharge <= ((soc_ddrphy_dfi_p1_bank == 3'd4) | soc_ddrphy_dfi_p1_address[10]);
+ end
+ 3'd4: begin
+ soc_ddrphy_bankmodel4_precharge <= ((soc_ddrphy_dfi_p2_bank == 3'd4) | soc_ddrphy_dfi_p2_address[10]);
+ end
+ 4'd8: begin
+ soc_ddrphy_bankmodel4_precharge <= ((soc_ddrphy_dfi_p3_bank == 3'd4) | soc_ddrphy_dfi_p3_address[10]);
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_writes4 <= 4'd0;
+ soc_ddrphy_writes4[0] <= soc_ddrphy_dfiphasemodel0_write;
+ soc_ddrphy_writes4[1] <= soc_ddrphy_dfiphasemodel1_write;
+ soc_ddrphy_writes4[2] <= soc_ddrphy_dfiphasemodel2_write;
+ soc_ddrphy_writes4[3] <= soc_ddrphy_dfiphasemodel3_write;
+end
+always @(*) begin
+ soc_ddrphy_bank_write4 <= 1'd0;
+ case (soc_ddrphy_writes4)
+ 1'd1: begin
+ soc_ddrphy_bank_write4 <= (soc_ddrphy_dfi_p0_bank == 3'd4);
+ end
+ 2'd2: begin
+ soc_ddrphy_bank_write4 <= (soc_ddrphy_dfi_p1_bank == 3'd4);
+ end
+ 3'd4: begin
+ soc_ddrphy_bank_write4 <= (soc_ddrphy_dfi_p2_bank == 3'd4);
+ end
+ 4'd8: begin
+ soc_ddrphy_bank_write4 <= (soc_ddrphy_dfi_p3_bank == 3'd4);
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_bank_write_col4 <= 10'd0;
+ case (soc_ddrphy_writes4)
+ 1'd1: begin
+ soc_ddrphy_bank_write_col4 <= soc_ddrphy_dfi_p0_address;
+ end
+ 2'd2: begin
+ soc_ddrphy_bank_write_col4 <= soc_ddrphy_dfi_p1_address;
+ end
+ 3'd4: begin
+ soc_ddrphy_bank_write_col4 <= soc_ddrphy_dfi_p2_address;
+ end
+ 4'd8: begin
+ soc_ddrphy_bank_write_col4 <= soc_ddrphy_dfi_p3_address;
+ end
+ endcase
end
assign soc_ddrphy_bankmodel4_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata};
assign soc_ddrphy_bankmodel4_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask};
assign soc_ddrphy_bankmodel4_write = soc_ddrphy_new_bank_write4;
assign soc_ddrphy_bankmodel4_write_col = soc_ddrphy_new_bank_write_col4;
always @(*) begin
- soc_ddrphy_reads4 <= 4'd0;
- soc_ddrphy_reads4[0] <= soc_ddrphy_dfiphasemodel0_read;
- soc_ddrphy_reads4[1] <= soc_ddrphy_dfiphasemodel1_read;
- soc_ddrphy_reads4[2] <= soc_ddrphy_dfiphasemodel2_read;
- soc_ddrphy_reads4[3] <= soc_ddrphy_dfiphasemodel3_read;
-end
-always @(*) begin
- soc_ddrphy_bankmodel4_read <= 1'd0;
- case (soc_ddrphy_reads4)
- 1'd1: begin
- soc_ddrphy_bankmodel4_read <= (soc_ddrphy_dfi_p0_bank == 3'd4);
- end
- 2'd2: begin
- soc_ddrphy_bankmodel4_read <= (soc_ddrphy_dfi_p1_bank == 3'd4);
- end
- 3'd4: begin
- soc_ddrphy_bankmodel4_read <= (soc_ddrphy_dfi_p2_bank == 3'd4);
- end
- 4'd8: begin
- soc_ddrphy_bankmodel4_read <= (soc_ddrphy_dfi_p3_bank == 3'd4);
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_bankmodel4_read_col <= 10'd0;
- case (soc_ddrphy_reads4)
- 1'd1: begin
- soc_ddrphy_bankmodel4_read_col <= soc_ddrphy_dfi_p0_address;
- end
- 2'd2: begin
- soc_ddrphy_bankmodel4_read_col <= soc_ddrphy_dfi_p1_address;
- end
- 3'd4: begin
- soc_ddrphy_bankmodel4_read_col <= soc_ddrphy_dfi_p2_address;
- end
- 4'd8: begin
- soc_ddrphy_bankmodel4_read_col <= soc_ddrphy_dfi_p3_address;
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_activates5 <= 4'd0;
- soc_ddrphy_activates5[0] <= soc_ddrphy_dfiphasemodel0_activate;
- soc_ddrphy_activates5[1] <= soc_ddrphy_dfiphasemodel1_activate;
- soc_ddrphy_activates5[2] <= soc_ddrphy_dfiphasemodel2_activate;
- soc_ddrphy_activates5[3] <= soc_ddrphy_dfiphasemodel3_activate;
-end
-always @(*) begin
- soc_ddrphy_bankmodel5_activate <= 1'd0;
- case (soc_ddrphy_activates5)
- 1'd1: begin
- soc_ddrphy_bankmodel5_activate <= (soc_ddrphy_dfi_p0_bank == 3'd5);
- end
- 2'd2: begin
- soc_ddrphy_bankmodel5_activate <= (soc_ddrphy_dfi_p1_bank == 3'd5);
- end
- 3'd4: begin
- soc_ddrphy_bankmodel5_activate <= (soc_ddrphy_dfi_p2_bank == 3'd5);
- end
- 4'd8: begin
- soc_ddrphy_bankmodel5_activate <= (soc_ddrphy_dfi_p3_bank == 3'd5);
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_bankmodel5_activate_row <= 14'd0;
- case (soc_ddrphy_activates5)
- 1'd1: begin
- soc_ddrphy_bankmodel5_activate_row <= soc_ddrphy_dfi_p0_address;
- end
- 2'd2: begin
- soc_ddrphy_bankmodel5_activate_row <= soc_ddrphy_dfi_p1_address;
- end
- 3'd4: begin
- soc_ddrphy_bankmodel5_activate_row <= soc_ddrphy_dfi_p2_address;
- end
- 4'd8: begin
- soc_ddrphy_bankmodel5_activate_row <= soc_ddrphy_dfi_p3_address;
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_precharges5 <= 4'd0;
- soc_ddrphy_precharges5[0] <= soc_ddrphy_dfiphasemodel0_precharge;
- soc_ddrphy_precharges5[1] <= soc_ddrphy_dfiphasemodel1_precharge;
- soc_ddrphy_precharges5[2] <= soc_ddrphy_dfiphasemodel2_precharge;
- soc_ddrphy_precharges5[3] <= soc_ddrphy_dfiphasemodel3_precharge;
-end
-always @(*) begin
- soc_ddrphy_bankmodel5_precharge <= 1'd0;
- case (soc_ddrphy_precharges5)
- 1'd1: begin
- soc_ddrphy_bankmodel5_precharge <= ((soc_ddrphy_dfi_p0_bank == 3'd5) | soc_ddrphy_dfi_p0_address[10]);
- end
- 2'd2: begin
- soc_ddrphy_bankmodel5_precharge <= ((soc_ddrphy_dfi_p1_bank == 3'd5) | soc_ddrphy_dfi_p1_address[10]);
- end
- 3'd4: begin
- soc_ddrphy_bankmodel5_precharge <= ((soc_ddrphy_dfi_p2_bank == 3'd5) | soc_ddrphy_dfi_p2_address[10]);
- end
- 4'd8: begin
- soc_ddrphy_bankmodel5_precharge <= ((soc_ddrphy_dfi_p3_bank == 3'd5) | soc_ddrphy_dfi_p3_address[10]);
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_writes5 <= 4'd0;
- soc_ddrphy_writes5[0] <= soc_ddrphy_dfiphasemodel0_write;
- soc_ddrphy_writes5[1] <= soc_ddrphy_dfiphasemodel1_write;
- soc_ddrphy_writes5[2] <= soc_ddrphy_dfiphasemodel2_write;
- soc_ddrphy_writes5[3] <= soc_ddrphy_dfiphasemodel3_write;
-end
-always @(*) begin
- soc_ddrphy_bank_write5 <= 1'd0;
- case (soc_ddrphy_writes5)
- 1'd1: begin
- soc_ddrphy_bank_write5 <= (soc_ddrphy_dfi_p0_bank == 3'd5);
- end
- 2'd2: begin
- soc_ddrphy_bank_write5 <= (soc_ddrphy_dfi_p1_bank == 3'd5);
- end
- 3'd4: begin
- soc_ddrphy_bank_write5 <= (soc_ddrphy_dfi_p2_bank == 3'd5);
- end
- 4'd8: begin
- soc_ddrphy_bank_write5 <= (soc_ddrphy_dfi_p3_bank == 3'd5);
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_bank_write_col5 <= 10'd0;
- case (soc_ddrphy_writes5)
- 1'd1: begin
- soc_ddrphy_bank_write_col5 <= soc_ddrphy_dfi_p0_address;
- end
- 2'd2: begin
- soc_ddrphy_bank_write_col5 <= soc_ddrphy_dfi_p1_address;
- end
- 3'd4: begin
- soc_ddrphy_bank_write_col5 <= soc_ddrphy_dfi_p2_address;
- end
- 4'd8: begin
- soc_ddrphy_bank_write_col5 <= soc_ddrphy_dfi_p3_address;
- end
- endcase
+ soc_ddrphy_reads4 <= 4'd0;
+ soc_ddrphy_reads4[0] <= soc_ddrphy_dfiphasemodel0_read;
+ soc_ddrphy_reads4[1] <= soc_ddrphy_dfiphasemodel1_read;
+ soc_ddrphy_reads4[2] <= soc_ddrphy_dfiphasemodel2_read;
+ soc_ddrphy_reads4[3] <= soc_ddrphy_dfiphasemodel3_read;
+end
+always @(*) begin
+ soc_ddrphy_bankmodel4_read <= 1'd0;
+ case (soc_ddrphy_reads4)
+ 1'd1: begin
+ soc_ddrphy_bankmodel4_read <= (soc_ddrphy_dfi_p0_bank == 3'd4);
+ end
+ 2'd2: begin
+ soc_ddrphy_bankmodel4_read <= (soc_ddrphy_dfi_p1_bank == 3'd4);
+ end
+ 3'd4: begin
+ soc_ddrphy_bankmodel4_read <= (soc_ddrphy_dfi_p2_bank == 3'd4);
+ end
+ 4'd8: begin
+ soc_ddrphy_bankmodel4_read <= (soc_ddrphy_dfi_p3_bank == 3'd4);
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_bankmodel4_read_col <= 10'd0;
+ case (soc_ddrphy_reads4)
+ 1'd1: begin
+ soc_ddrphy_bankmodel4_read_col <= soc_ddrphy_dfi_p0_address;
+ end
+ 2'd2: begin
+ soc_ddrphy_bankmodel4_read_col <= soc_ddrphy_dfi_p1_address;
+ end
+ 3'd4: begin
+ soc_ddrphy_bankmodel4_read_col <= soc_ddrphy_dfi_p2_address;
+ end
+ 4'd8: begin
+ soc_ddrphy_bankmodel4_read_col <= soc_ddrphy_dfi_p3_address;
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_activates5 <= 4'd0;
+ soc_ddrphy_activates5[0] <= soc_ddrphy_dfiphasemodel0_activate;
+ soc_ddrphy_activates5[1] <= soc_ddrphy_dfiphasemodel1_activate;
+ soc_ddrphy_activates5[2] <= soc_ddrphy_dfiphasemodel2_activate;
+ soc_ddrphy_activates5[3] <= soc_ddrphy_dfiphasemodel3_activate;
+end
+always @(*) begin
+ soc_ddrphy_bankmodel5_activate <= 1'd0;
+ case (soc_ddrphy_activates5)
+ 1'd1: begin
+ soc_ddrphy_bankmodel5_activate <= (soc_ddrphy_dfi_p0_bank == 3'd5);
+ end
+ 2'd2: begin
+ soc_ddrphy_bankmodel5_activate <= (soc_ddrphy_dfi_p1_bank == 3'd5);
+ end
+ 3'd4: begin
+ soc_ddrphy_bankmodel5_activate <= (soc_ddrphy_dfi_p2_bank == 3'd5);
+ end
+ 4'd8: begin
+ soc_ddrphy_bankmodel5_activate <= (soc_ddrphy_dfi_p3_bank == 3'd5);
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_bankmodel5_activate_row <= 14'd0;
+ case (soc_ddrphy_activates5)
+ 1'd1: begin
+ soc_ddrphy_bankmodel5_activate_row <= soc_ddrphy_dfi_p0_address;
+ end
+ 2'd2: begin
+ soc_ddrphy_bankmodel5_activate_row <= soc_ddrphy_dfi_p1_address;
+ end
+ 3'd4: begin
+ soc_ddrphy_bankmodel5_activate_row <= soc_ddrphy_dfi_p2_address;
+ end
+ 4'd8: begin
+ soc_ddrphy_bankmodel5_activate_row <= soc_ddrphy_dfi_p3_address;
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_precharges5 <= 4'd0;
+ soc_ddrphy_precharges5[0] <= soc_ddrphy_dfiphasemodel0_precharge;
+ soc_ddrphy_precharges5[1] <= soc_ddrphy_dfiphasemodel1_precharge;
+ soc_ddrphy_precharges5[2] <= soc_ddrphy_dfiphasemodel2_precharge;
+ soc_ddrphy_precharges5[3] <= soc_ddrphy_dfiphasemodel3_precharge;
+end
+always @(*) begin
+ soc_ddrphy_bankmodel5_precharge <= 1'd0;
+ case (soc_ddrphy_precharges5)
+ 1'd1: begin
+ soc_ddrphy_bankmodel5_precharge <= ((soc_ddrphy_dfi_p0_bank == 3'd5) | soc_ddrphy_dfi_p0_address[10]);
+ end
+ 2'd2: begin
+ soc_ddrphy_bankmodel5_precharge <= ((soc_ddrphy_dfi_p1_bank == 3'd5) | soc_ddrphy_dfi_p1_address[10]);
+ end
+ 3'd4: begin
+ soc_ddrphy_bankmodel5_precharge <= ((soc_ddrphy_dfi_p2_bank == 3'd5) | soc_ddrphy_dfi_p2_address[10]);
+ end
+ 4'd8: begin
+ soc_ddrphy_bankmodel5_precharge <= ((soc_ddrphy_dfi_p3_bank == 3'd5) | soc_ddrphy_dfi_p3_address[10]);
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_writes5 <= 4'd0;
+ soc_ddrphy_writes5[0] <= soc_ddrphy_dfiphasemodel0_write;
+ soc_ddrphy_writes5[1] <= soc_ddrphy_dfiphasemodel1_write;
+ soc_ddrphy_writes5[2] <= soc_ddrphy_dfiphasemodel2_write;
+ soc_ddrphy_writes5[3] <= soc_ddrphy_dfiphasemodel3_write;
+end
+always @(*) begin
+ soc_ddrphy_bank_write5 <= 1'd0;
+ case (soc_ddrphy_writes5)
+ 1'd1: begin
+ soc_ddrphy_bank_write5 <= (soc_ddrphy_dfi_p0_bank == 3'd5);
+ end
+ 2'd2: begin
+ soc_ddrphy_bank_write5 <= (soc_ddrphy_dfi_p1_bank == 3'd5);
+ end
+ 3'd4: begin
+ soc_ddrphy_bank_write5 <= (soc_ddrphy_dfi_p2_bank == 3'd5);
+ end
+ 4'd8: begin
+ soc_ddrphy_bank_write5 <= (soc_ddrphy_dfi_p3_bank == 3'd5);
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_bank_write_col5 <= 10'd0;
+ case (soc_ddrphy_writes5)
+ 1'd1: begin
+ soc_ddrphy_bank_write_col5 <= soc_ddrphy_dfi_p0_address;
+ end
+ 2'd2: begin
+ soc_ddrphy_bank_write_col5 <= soc_ddrphy_dfi_p1_address;
+ end
+ 3'd4: begin
+ soc_ddrphy_bank_write_col5 <= soc_ddrphy_dfi_p2_address;
+ end
+ 4'd8: begin
+ soc_ddrphy_bank_write_col5 <= soc_ddrphy_dfi_p3_address;
+ end
+ endcase
end
assign soc_ddrphy_bankmodel5_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata};
assign soc_ddrphy_bankmodel5_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask};
assign soc_ddrphy_bankmodel5_write = soc_ddrphy_new_bank_write5;
assign soc_ddrphy_bankmodel5_write_col = soc_ddrphy_new_bank_write_col5;
always @(*) begin
- soc_ddrphy_reads5 <= 4'd0;
- soc_ddrphy_reads5[0] <= soc_ddrphy_dfiphasemodel0_read;
- soc_ddrphy_reads5[1] <= soc_ddrphy_dfiphasemodel1_read;
- soc_ddrphy_reads5[2] <= soc_ddrphy_dfiphasemodel2_read;
- soc_ddrphy_reads5[3] <= soc_ddrphy_dfiphasemodel3_read;
-end
-always @(*) begin
- soc_ddrphy_bankmodel5_read <= 1'd0;
- case (soc_ddrphy_reads5)
- 1'd1: begin
- soc_ddrphy_bankmodel5_read <= (soc_ddrphy_dfi_p0_bank == 3'd5);
- end
- 2'd2: begin
- soc_ddrphy_bankmodel5_read <= (soc_ddrphy_dfi_p1_bank == 3'd5);
- end
- 3'd4: begin
- soc_ddrphy_bankmodel5_read <= (soc_ddrphy_dfi_p2_bank == 3'd5);
- end
- 4'd8: begin
- soc_ddrphy_bankmodel5_read <= (soc_ddrphy_dfi_p3_bank == 3'd5);
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_bankmodel5_read_col <= 10'd0;
- case (soc_ddrphy_reads5)
- 1'd1: begin
- soc_ddrphy_bankmodel5_read_col <= soc_ddrphy_dfi_p0_address;
- end
- 2'd2: begin
- soc_ddrphy_bankmodel5_read_col <= soc_ddrphy_dfi_p1_address;
- end
- 3'd4: begin
- soc_ddrphy_bankmodel5_read_col <= soc_ddrphy_dfi_p2_address;
- end
- 4'd8: begin
- soc_ddrphy_bankmodel5_read_col <= soc_ddrphy_dfi_p3_address;
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_activates6 <= 4'd0;
- soc_ddrphy_activates6[0] <= soc_ddrphy_dfiphasemodel0_activate;
- soc_ddrphy_activates6[1] <= soc_ddrphy_dfiphasemodel1_activate;
- soc_ddrphy_activates6[2] <= soc_ddrphy_dfiphasemodel2_activate;
- soc_ddrphy_activates6[3] <= soc_ddrphy_dfiphasemodel3_activate;
-end
-always @(*) begin
- soc_ddrphy_bankmodel6_activate <= 1'd0;
- case (soc_ddrphy_activates6)
- 1'd1: begin
- soc_ddrphy_bankmodel6_activate <= (soc_ddrphy_dfi_p0_bank == 3'd6);
- end
- 2'd2: begin
- soc_ddrphy_bankmodel6_activate <= (soc_ddrphy_dfi_p1_bank == 3'd6);
- end
- 3'd4: begin
- soc_ddrphy_bankmodel6_activate <= (soc_ddrphy_dfi_p2_bank == 3'd6);
- end
- 4'd8: begin
- soc_ddrphy_bankmodel6_activate <= (soc_ddrphy_dfi_p3_bank == 3'd6);
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_bankmodel6_activate_row <= 14'd0;
- case (soc_ddrphy_activates6)
- 1'd1: begin
- soc_ddrphy_bankmodel6_activate_row <= soc_ddrphy_dfi_p0_address;
- end
- 2'd2: begin
- soc_ddrphy_bankmodel6_activate_row <= soc_ddrphy_dfi_p1_address;
- end
- 3'd4: begin
- soc_ddrphy_bankmodel6_activate_row <= soc_ddrphy_dfi_p2_address;
- end
- 4'd8: begin
- soc_ddrphy_bankmodel6_activate_row <= soc_ddrphy_dfi_p3_address;
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_precharges6 <= 4'd0;
- soc_ddrphy_precharges6[0] <= soc_ddrphy_dfiphasemodel0_precharge;
- soc_ddrphy_precharges6[1] <= soc_ddrphy_dfiphasemodel1_precharge;
- soc_ddrphy_precharges6[2] <= soc_ddrphy_dfiphasemodel2_precharge;
- soc_ddrphy_precharges6[3] <= soc_ddrphy_dfiphasemodel3_precharge;
-end
-always @(*) begin
- soc_ddrphy_bankmodel6_precharge <= 1'd0;
- case (soc_ddrphy_precharges6)
- 1'd1: begin
- soc_ddrphy_bankmodel6_precharge <= ((soc_ddrphy_dfi_p0_bank == 3'd6) | soc_ddrphy_dfi_p0_address[10]);
- end
- 2'd2: begin
- soc_ddrphy_bankmodel6_precharge <= ((soc_ddrphy_dfi_p1_bank == 3'd6) | soc_ddrphy_dfi_p1_address[10]);
- end
- 3'd4: begin
- soc_ddrphy_bankmodel6_precharge <= ((soc_ddrphy_dfi_p2_bank == 3'd6) | soc_ddrphy_dfi_p2_address[10]);
- end
- 4'd8: begin
- soc_ddrphy_bankmodel6_precharge <= ((soc_ddrphy_dfi_p3_bank == 3'd6) | soc_ddrphy_dfi_p3_address[10]);
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_writes6 <= 4'd0;
- soc_ddrphy_writes6[0] <= soc_ddrphy_dfiphasemodel0_write;
- soc_ddrphy_writes6[1] <= soc_ddrphy_dfiphasemodel1_write;
- soc_ddrphy_writes6[2] <= soc_ddrphy_dfiphasemodel2_write;
- soc_ddrphy_writes6[3] <= soc_ddrphy_dfiphasemodel3_write;
-end
-always @(*) begin
- soc_ddrphy_bank_write_col6 <= 10'd0;
- case (soc_ddrphy_writes6)
- 1'd1: begin
- soc_ddrphy_bank_write_col6 <= soc_ddrphy_dfi_p0_address;
- end
- 2'd2: begin
- soc_ddrphy_bank_write_col6 <= soc_ddrphy_dfi_p1_address;
- end
- 3'd4: begin
- soc_ddrphy_bank_write_col6 <= soc_ddrphy_dfi_p2_address;
- end
- 4'd8: begin
- soc_ddrphy_bank_write_col6 <= soc_ddrphy_dfi_p3_address;
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_bank_write6 <= 1'd0;
- case (soc_ddrphy_writes6)
- 1'd1: begin
- soc_ddrphy_bank_write6 <= (soc_ddrphy_dfi_p0_bank == 3'd6);
- end
- 2'd2: begin
- soc_ddrphy_bank_write6 <= (soc_ddrphy_dfi_p1_bank == 3'd6);
- end
- 3'd4: begin
- soc_ddrphy_bank_write6 <= (soc_ddrphy_dfi_p2_bank == 3'd6);
- end
- 4'd8: begin
- soc_ddrphy_bank_write6 <= (soc_ddrphy_dfi_p3_bank == 3'd6);
- end
- endcase
+ soc_ddrphy_reads5 <= 4'd0;
+ soc_ddrphy_reads5[0] <= soc_ddrphy_dfiphasemodel0_read;
+ soc_ddrphy_reads5[1] <= soc_ddrphy_dfiphasemodel1_read;
+ soc_ddrphy_reads5[2] <= soc_ddrphy_dfiphasemodel2_read;
+ soc_ddrphy_reads5[3] <= soc_ddrphy_dfiphasemodel3_read;
+end
+always @(*) begin
+ soc_ddrphy_bankmodel5_read <= 1'd0;
+ case (soc_ddrphy_reads5)
+ 1'd1: begin
+ soc_ddrphy_bankmodel5_read <= (soc_ddrphy_dfi_p0_bank == 3'd5);
+ end
+ 2'd2: begin
+ soc_ddrphy_bankmodel5_read <= (soc_ddrphy_dfi_p1_bank == 3'd5);
+ end
+ 3'd4: begin
+ soc_ddrphy_bankmodel5_read <= (soc_ddrphy_dfi_p2_bank == 3'd5);
+ end
+ 4'd8: begin
+ soc_ddrphy_bankmodel5_read <= (soc_ddrphy_dfi_p3_bank == 3'd5);
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_bankmodel5_read_col <= 10'd0;
+ case (soc_ddrphy_reads5)
+ 1'd1: begin
+ soc_ddrphy_bankmodel5_read_col <= soc_ddrphy_dfi_p0_address;
+ end
+ 2'd2: begin
+ soc_ddrphy_bankmodel5_read_col <= soc_ddrphy_dfi_p1_address;
+ end
+ 3'd4: begin
+ soc_ddrphy_bankmodel5_read_col <= soc_ddrphy_dfi_p2_address;
+ end
+ 4'd8: begin
+ soc_ddrphy_bankmodel5_read_col <= soc_ddrphy_dfi_p3_address;
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_activates6 <= 4'd0;
+ soc_ddrphy_activates6[0] <= soc_ddrphy_dfiphasemodel0_activate;
+ soc_ddrphy_activates6[1] <= soc_ddrphy_dfiphasemodel1_activate;
+ soc_ddrphy_activates6[2] <= soc_ddrphy_dfiphasemodel2_activate;
+ soc_ddrphy_activates6[3] <= soc_ddrphy_dfiphasemodel3_activate;
+end
+always @(*) begin
+ soc_ddrphy_bankmodel6_activate <= 1'd0;
+ case (soc_ddrphy_activates6)
+ 1'd1: begin
+ soc_ddrphy_bankmodel6_activate <= (soc_ddrphy_dfi_p0_bank == 3'd6);
+ end
+ 2'd2: begin
+ soc_ddrphy_bankmodel6_activate <= (soc_ddrphy_dfi_p1_bank == 3'd6);
+ end
+ 3'd4: begin
+ soc_ddrphy_bankmodel6_activate <= (soc_ddrphy_dfi_p2_bank == 3'd6);
+ end
+ 4'd8: begin
+ soc_ddrphy_bankmodel6_activate <= (soc_ddrphy_dfi_p3_bank == 3'd6);
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_bankmodel6_activate_row <= 14'd0;
+ case (soc_ddrphy_activates6)
+ 1'd1: begin
+ soc_ddrphy_bankmodel6_activate_row <= soc_ddrphy_dfi_p0_address;
+ end
+ 2'd2: begin
+ soc_ddrphy_bankmodel6_activate_row <= soc_ddrphy_dfi_p1_address;
+ end
+ 3'd4: begin
+ soc_ddrphy_bankmodel6_activate_row <= soc_ddrphy_dfi_p2_address;
+ end
+ 4'd8: begin
+ soc_ddrphy_bankmodel6_activate_row <= soc_ddrphy_dfi_p3_address;
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_precharges6 <= 4'd0;
+ soc_ddrphy_precharges6[0] <= soc_ddrphy_dfiphasemodel0_precharge;
+ soc_ddrphy_precharges6[1] <= soc_ddrphy_dfiphasemodel1_precharge;
+ soc_ddrphy_precharges6[2] <= soc_ddrphy_dfiphasemodel2_precharge;
+ soc_ddrphy_precharges6[3] <= soc_ddrphy_dfiphasemodel3_precharge;
+end
+always @(*) begin
+ soc_ddrphy_bankmodel6_precharge <= 1'd0;
+ case (soc_ddrphy_precharges6)
+ 1'd1: begin
+ soc_ddrphy_bankmodel6_precharge <= ((soc_ddrphy_dfi_p0_bank == 3'd6) | soc_ddrphy_dfi_p0_address[10]);
+ end
+ 2'd2: begin
+ soc_ddrphy_bankmodel6_precharge <= ((soc_ddrphy_dfi_p1_bank == 3'd6) | soc_ddrphy_dfi_p1_address[10]);
+ end
+ 3'd4: begin
+ soc_ddrphy_bankmodel6_precharge <= ((soc_ddrphy_dfi_p2_bank == 3'd6) | soc_ddrphy_dfi_p2_address[10]);
+ end
+ 4'd8: begin
+ soc_ddrphy_bankmodel6_precharge <= ((soc_ddrphy_dfi_p3_bank == 3'd6) | soc_ddrphy_dfi_p3_address[10]);
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_writes6 <= 4'd0;
+ soc_ddrphy_writes6[0] <= soc_ddrphy_dfiphasemodel0_write;
+ soc_ddrphy_writes6[1] <= soc_ddrphy_dfiphasemodel1_write;
+ soc_ddrphy_writes6[2] <= soc_ddrphy_dfiphasemodel2_write;
+ soc_ddrphy_writes6[3] <= soc_ddrphy_dfiphasemodel3_write;
+end
+always @(*) begin
+ soc_ddrphy_bank_write_col6 <= 10'd0;
+ case (soc_ddrphy_writes6)
+ 1'd1: begin
+ soc_ddrphy_bank_write_col6 <= soc_ddrphy_dfi_p0_address;
+ end
+ 2'd2: begin
+ soc_ddrphy_bank_write_col6 <= soc_ddrphy_dfi_p1_address;
+ end
+ 3'd4: begin
+ soc_ddrphy_bank_write_col6 <= soc_ddrphy_dfi_p2_address;
+ end
+ 4'd8: begin
+ soc_ddrphy_bank_write_col6 <= soc_ddrphy_dfi_p3_address;
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_bank_write6 <= 1'd0;
+ case (soc_ddrphy_writes6)
+ 1'd1: begin
+ soc_ddrphy_bank_write6 <= (soc_ddrphy_dfi_p0_bank == 3'd6);
+ end
+ 2'd2: begin
+ soc_ddrphy_bank_write6 <= (soc_ddrphy_dfi_p1_bank == 3'd6);
+ end
+ 3'd4: begin
+ soc_ddrphy_bank_write6 <= (soc_ddrphy_dfi_p2_bank == 3'd6);
+ end
+ 4'd8: begin
+ soc_ddrphy_bank_write6 <= (soc_ddrphy_dfi_p3_bank == 3'd6);
+ end
+ endcase
end
assign soc_ddrphy_bankmodel6_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata};
assign soc_ddrphy_bankmodel6_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask};
assign soc_ddrphy_bankmodel6_write = soc_ddrphy_new_bank_write6;
assign soc_ddrphy_bankmodel6_write_col = soc_ddrphy_new_bank_write_col6;
always @(*) begin
- soc_ddrphy_reads6 <= 4'd0;
- soc_ddrphy_reads6[0] <= soc_ddrphy_dfiphasemodel0_read;
- soc_ddrphy_reads6[1] <= soc_ddrphy_dfiphasemodel1_read;
- soc_ddrphy_reads6[2] <= soc_ddrphy_dfiphasemodel2_read;
- soc_ddrphy_reads6[3] <= soc_ddrphy_dfiphasemodel3_read;
-end
-always @(*) begin
- soc_ddrphy_bankmodel6_read_col <= 10'd0;
- case (soc_ddrphy_reads6)
- 1'd1: begin
- soc_ddrphy_bankmodel6_read_col <= soc_ddrphy_dfi_p0_address;
- end
- 2'd2: begin
- soc_ddrphy_bankmodel6_read_col <= soc_ddrphy_dfi_p1_address;
- end
- 3'd4: begin
- soc_ddrphy_bankmodel6_read_col <= soc_ddrphy_dfi_p2_address;
- end
- 4'd8: begin
- soc_ddrphy_bankmodel6_read_col <= soc_ddrphy_dfi_p3_address;
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_bankmodel6_read <= 1'd0;
- case (soc_ddrphy_reads6)
- 1'd1: begin
- soc_ddrphy_bankmodel6_read <= (soc_ddrphy_dfi_p0_bank == 3'd6);
- end
- 2'd2: begin
- soc_ddrphy_bankmodel6_read <= (soc_ddrphy_dfi_p1_bank == 3'd6);
- end
- 3'd4: begin
- soc_ddrphy_bankmodel6_read <= (soc_ddrphy_dfi_p2_bank == 3'd6);
- end
- 4'd8: begin
- soc_ddrphy_bankmodel6_read <= (soc_ddrphy_dfi_p3_bank == 3'd6);
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_activates7 <= 4'd0;
- soc_ddrphy_activates7[0] <= soc_ddrphy_dfiphasemodel0_activate;
- soc_ddrphy_activates7[1] <= soc_ddrphy_dfiphasemodel1_activate;
- soc_ddrphy_activates7[2] <= soc_ddrphy_dfiphasemodel2_activate;
- soc_ddrphy_activates7[3] <= soc_ddrphy_dfiphasemodel3_activate;
-end
-always @(*) begin
- soc_ddrphy_bankmodel7_activate <= 1'd0;
- case (soc_ddrphy_activates7)
- 1'd1: begin
- soc_ddrphy_bankmodel7_activate <= (soc_ddrphy_dfi_p0_bank == 3'd7);
- end
- 2'd2: begin
- soc_ddrphy_bankmodel7_activate <= (soc_ddrphy_dfi_p1_bank == 3'd7);
- end
- 3'd4: begin
- soc_ddrphy_bankmodel7_activate <= (soc_ddrphy_dfi_p2_bank == 3'd7);
- end
- 4'd8: begin
- soc_ddrphy_bankmodel7_activate <= (soc_ddrphy_dfi_p3_bank == 3'd7);
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_bankmodel7_activate_row <= 14'd0;
- case (soc_ddrphy_activates7)
- 1'd1: begin
- soc_ddrphy_bankmodel7_activate_row <= soc_ddrphy_dfi_p0_address;
- end
- 2'd2: begin
- soc_ddrphy_bankmodel7_activate_row <= soc_ddrphy_dfi_p1_address;
- end
- 3'd4: begin
- soc_ddrphy_bankmodel7_activate_row <= soc_ddrphy_dfi_p2_address;
- end
- 4'd8: begin
- soc_ddrphy_bankmodel7_activate_row <= soc_ddrphy_dfi_p3_address;
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_precharges7 <= 4'd0;
- soc_ddrphy_precharges7[0] <= soc_ddrphy_dfiphasemodel0_precharge;
- soc_ddrphy_precharges7[1] <= soc_ddrphy_dfiphasemodel1_precharge;
- soc_ddrphy_precharges7[2] <= soc_ddrphy_dfiphasemodel2_precharge;
- soc_ddrphy_precharges7[3] <= soc_ddrphy_dfiphasemodel3_precharge;
-end
-always @(*) begin
- soc_ddrphy_bankmodel7_precharge <= 1'd0;
- case (soc_ddrphy_precharges7)
- 1'd1: begin
- soc_ddrphy_bankmodel7_precharge <= ((soc_ddrphy_dfi_p0_bank == 3'd7) | soc_ddrphy_dfi_p0_address[10]);
- end
- 2'd2: begin
- soc_ddrphy_bankmodel7_precharge <= ((soc_ddrphy_dfi_p1_bank == 3'd7) | soc_ddrphy_dfi_p1_address[10]);
- end
- 3'd4: begin
- soc_ddrphy_bankmodel7_precharge <= ((soc_ddrphy_dfi_p2_bank == 3'd7) | soc_ddrphy_dfi_p2_address[10]);
- end
- 4'd8: begin
- soc_ddrphy_bankmodel7_precharge <= ((soc_ddrphy_dfi_p3_bank == 3'd7) | soc_ddrphy_dfi_p3_address[10]);
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_writes7 <= 4'd0;
- soc_ddrphy_writes7[0] <= soc_ddrphy_dfiphasemodel0_write;
- soc_ddrphy_writes7[1] <= soc_ddrphy_dfiphasemodel1_write;
- soc_ddrphy_writes7[2] <= soc_ddrphy_dfiphasemodel2_write;
- soc_ddrphy_writes7[3] <= soc_ddrphy_dfiphasemodel3_write;
-end
-always @(*) begin
- soc_ddrphy_bank_write7 <= 1'd0;
- case (soc_ddrphy_writes7)
- 1'd1: begin
- soc_ddrphy_bank_write7 <= (soc_ddrphy_dfi_p0_bank == 3'd7);
- end
- 2'd2: begin
- soc_ddrphy_bank_write7 <= (soc_ddrphy_dfi_p1_bank == 3'd7);
- end
- 3'd4: begin
- soc_ddrphy_bank_write7 <= (soc_ddrphy_dfi_p2_bank == 3'd7);
- end
- 4'd8: begin
- soc_ddrphy_bank_write7 <= (soc_ddrphy_dfi_p3_bank == 3'd7);
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_bank_write_col7 <= 10'd0;
- case (soc_ddrphy_writes7)
- 1'd1: begin
- soc_ddrphy_bank_write_col7 <= soc_ddrphy_dfi_p0_address;
- end
- 2'd2: begin
- soc_ddrphy_bank_write_col7 <= soc_ddrphy_dfi_p1_address;
- end
- 3'd4: begin
- soc_ddrphy_bank_write_col7 <= soc_ddrphy_dfi_p2_address;
- end
- 4'd8: begin
- soc_ddrphy_bank_write_col7 <= soc_ddrphy_dfi_p3_address;
- end
- endcase
+ soc_ddrphy_reads6 <= 4'd0;
+ soc_ddrphy_reads6[0] <= soc_ddrphy_dfiphasemodel0_read;
+ soc_ddrphy_reads6[1] <= soc_ddrphy_dfiphasemodel1_read;
+ soc_ddrphy_reads6[2] <= soc_ddrphy_dfiphasemodel2_read;
+ soc_ddrphy_reads6[3] <= soc_ddrphy_dfiphasemodel3_read;
+end
+always @(*) begin
+ soc_ddrphy_bankmodel6_read_col <= 10'd0;
+ case (soc_ddrphy_reads6)
+ 1'd1: begin
+ soc_ddrphy_bankmodel6_read_col <= soc_ddrphy_dfi_p0_address;
+ end
+ 2'd2: begin
+ soc_ddrphy_bankmodel6_read_col <= soc_ddrphy_dfi_p1_address;
+ end
+ 3'd4: begin
+ soc_ddrphy_bankmodel6_read_col <= soc_ddrphy_dfi_p2_address;
+ end
+ 4'd8: begin
+ soc_ddrphy_bankmodel6_read_col <= soc_ddrphy_dfi_p3_address;
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_bankmodel6_read <= 1'd0;
+ case (soc_ddrphy_reads6)
+ 1'd1: begin
+ soc_ddrphy_bankmodel6_read <= (soc_ddrphy_dfi_p0_bank == 3'd6);
+ end
+ 2'd2: begin
+ soc_ddrphy_bankmodel6_read <= (soc_ddrphy_dfi_p1_bank == 3'd6);
+ end
+ 3'd4: begin
+ soc_ddrphy_bankmodel6_read <= (soc_ddrphy_dfi_p2_bank == 3'd6);
+ end
+ 4'd8: begin
+ soc_ddrphy_bankmodel6_read <= (soc_ddrphy_dfi_p3_bank == 3'd6);
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_activates7 <= 4'd0;
+ soc_ddrphy_activates7[0] <= soc_ddrphy_dfiphasemodel0_activate;
+ soc_ddrphy_activates7[1] <= soc_ddrphy_dfiphasemodel1_activate;
+ soc_ddrphy_activates7[2] <= soc_ddrphy_dfiphasemodel2_activate;
+ soc_ddrphy_activates7[3] <= soc_ddrphy_dfiphasemodel3_activate;
+end
+always @(*) begin
+ soc_ddrphy_bankmodel7_activate <= 1'd0;
+ case (soc_ddrphy_activates7)
+ 1'd1: begin
+ soc_ddrphy_bankmodel7_activate <= (soc_ddrphy_dfi_p0_bank == 3'd7);
+ end
+ 2'd2: begin
+ soc_ddrphy_bankmodel7_activate <= (soc_ddrphy_dfi_p1_bank == 3'd7);
+ end
+ 3'd4: begin
+ soc_ddrphy_bankmodel7_activate <= (soc_ddrphy_dfi_p2_bank == 3'd7);
+ end
+ 4'd8: begin
+ soc_ddrphy_bankmodel7_activate <= (soc_ddrphy_dfi_p3_bank == 3'd7);
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_bankmodel7_activate_row <= 14'd0;
+ case (soc_ddrphy_activates7)
+ 1'd1: begin
+ soc_ddrphy_bankmodel7_activate_row <= soc_ddrphy_dfi_p0_address;
+ end
+ 2'd2: begin
+ soc_ddrphy_bankmodel7_activate_row <= soc_ddrphy_dfi_p1_address;
+ end
+ 3'd4: begin
+ soc_ddrphy_bankmodel7_activate_row <= soc_ddrphy_dfi_p2_address;
+ end
+ 4'd8: begin
+ soc_ddrphy_bankmodel7_activate_row <= soc_ddrphy_dfi_p3_address;
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_precharges7 <= 4'd0;
+ soc_ddrphy_precharges7[0] <= soc_ddrphy_dfiphasemodel0_precharge;
+ soc_ddrphy_precharges7[1] <= soc_ddrphy_dfiphasemodel1_precharge;
+ soc_ddrphy_precharges7[2] <= soc_ddrphy_dfiphasemodel2_precharge;
+ soc_ddrphy_precharges7[3] <= soc_ddrphy_dfiphasemodel3_precharge;
+end
+always @(*) begin
+ soc_ddrphy_bankmodel7_precharge <= 1'd0;
+ case (soc_ddrphy_precharges7)
+ 1'd1: begin
+ soc_ddrphy_bankmodel7_precharge <= ((soc_ddrphy_dfi_p0_bank == 3'd7) | soc_ddrphy_dfi_p0_address[10]);
+ end
+ 2'd2: begin
+ soc_ddrphy_bankmodel7_precharge <= ((soc_ddrphy_dfi_p1_bank == 3'd7) | soc_ddrphy_dfi_p1_address[10]);
+ end
+ 3'd4: begin
+ soc_ddrphy_bankmodel7_precharge <= ((soc_ddrphy_dfi_p2_bank == 3'd7) | soc_ddrphy_dfi_p2_address[10]);
+ end
+ 4'd8: begin
+ soc_ddrphy_bankmodel7_precharge <= ((soc_ddrphy_dfi_p3_bank == 3'd7) | soc_ddrphy_dfi_p3_address[10]);
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_writes7 <= 4'd0;
+ soc_ddrphy_writes7[0] <= soc_ddrphy_dfiphasemodel0_write;
+ soc_ddrphy_writes7[1] <= soc_ddrphy_dfiphasemodel1_write;
+ soc_ddrphy_writes7[2] <= soc_ddrphy_dfiphasemodel2_write;
+ soc_ddrphy_writes7[3] <= soc_ddrphy_dfiphasemodel3_write;
+end
+always @(*) begin
+ soc_ddrphy_bank_write7 <= 1'd0;
+ case (soc_ddrphy_writes7)
+ 1'd1: begin
+ soc_ddrphy_bank_write7 <= (soc_ddrphy_dfi_p0_bank == 3'd7);
+ end
+ 2'd2: begin
+ soc_ddrphy_bank_write7 <= (soc_ddrphy_dfi_p1_bank == 3'd7);
+ end
+ 3'd4: begin
+ soc_ddrphy_bank_write7 <= (soc_ddrphy_dfi_p2_bank == 3'd7);
+ end
+ 4'd8: begin
+ soc_ddrphy_bank_write7 <= (soc_ddrphy_dfi_p3_bank == 3'd7);
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_bank_write_col7 <= 10'd0;
+ case (soc_ddrphy_writes7)
+ 1'd1: begin
+ soc_ddrphy_bank_write_col7 <= soc_ddrphy_dfi_p0_address;
+ end
+ 2'd2: begin
+ soc_ddrphy_bank_write_col7 <= soc_ddrphy_dfi_p1_address;
+ end
+ 3'd4: begin
+ soc_ddrphy_bank_write_col7 <= soc_ddrphy_dfi_p2_address;
+ end
+ 4'd8: begin
+ soc_ddrphy_bank_write_col7 <= soc_ddrphy_dfi_p3_address;
+ end
+ endcase
end
assign soc_ddrphy_bankmodel7_write_data = {soc_ddrphy_dfi_p3_wrdata, soc_ddrphy_dfi_p2_wrdata, soc_ddrphy_dfi_p1_wrdata, soc_ddrphy_dfi_p0_wrdata};
assign soc_ddrphy_bankmodel7_write_mask = {soc_ddrphy_dfi_p3_wrdata_mask, soc_ddrphy_dfi_p2_wrdata_mask, soc_ddrphy_dfi_p1_wrdata_mask, soc_ddrphy_dfi_p0_wrdata_mask};
assign soc_ddrphy_bankmodel7_write = soc_ddrphy_new_bank_write7;
assign soc_ddrphy_bankmodel7_write_col = soc_ddrphy_new_bank_write_col7;
always @(*) begin
- soc_ddrphy_reads7 <= 4'd0;
- soc_ddrphy_reads7[0] <= soc_ddrphy_dfiphasemodel0_read;
- soc_ddrphy_reads7[1] <= soc_ddrphy_dfiphasemodel1_read;
- soc_ddrphy_reads7[2] <= soc_ddrphy_dfiphasemodel2_read;
- soc_ddrphy_reads7[3] <= soc_ddrphy_dfiphasemodel3_read;
-end
-always @(*) begin
- soc_ddrphy_bankmodel7_read <= 1'd0;
- case (soc_ddrphy_reads7)
- 1'd1: begin
- soc_ddrphy_bankmodel7_read <= (soc_ddrphy_dfi_p0_bank == 3'd7);
- end
- 2'd2: begin
- soc_ddrphy_bankmodel7_read <= (soc_ddrphy_dfi_p1_bank == 3'd7);
- end
- 3'd4: begin
- soc_ddrphy_bankmodel7_read <= (soc_ddrphy_dfi_p2_bank == 3'd7);
- end
- 4'd8: begin
- soc_ddrphy_bankmodel7_read <= (soc_ddrphy_dfi_p3_bank == 3'd7);
- end
- endcase
-end
-always @(*) begin
- soc_ddrphy_bankmodel7_read_col <= 10'd0;
- case (soc_ddrphy_reads7)
- 1'd1: begin
- soc_ddrphy_bankmodel7_read_col <= soc_ddrphy_dfi_p0_address;
- end
- 2'd2: begin
- soc_ddrphy_bankmodel7_read_col <= soc_ddrphy_dfi_p1_address;
- end
- 3'd4: begin
- soc_ddrphy_bankmodel7_read_col <= soc_ddrphy_dfi_p2_address;
- end
- 4'd8: begin
- soc_ddrphy_bankmodel7_read_col <= soc_ddrphy_dfi_p3_address;
- end
- endcase
+ soc_ddrphy_reads7 <= 4'd0;
+ soc_ddrphy_reads7[0] <= soc_ddrphy_dfiphasemodel0_read;
+ soc_ddrphy_reads7[1] <= soc_ddrphy_dfiphasemodel1_read;
+ soc_ddrphy_reads7[2] <= soc_ddrphy_dfiphasemodel2_read;
+ soc_ddrphy_reads7[3] <= soc_ddrphy_dfiphasemodel3_read;
+end
+always @(*) begin
+ soc_ddrphy_bankmodel7_read <= 1'd0;
+ case (soc_ddrphy_reads7)
+ 1'd1: begin
+ soc_ddrphy_bankmodel7_read <= (soc_ddrphy_dfi_p0_bank == 3'd7);
+ end
+ 2'd2: begin
+ soc_ddrphy_bankmodel7_read <= (soc_ddrphy_dfi_p1_bank == 3'd7);
+ end
+ 3'd4: begin
+ soc_ddrphy_bankmodel7_read <= (soc_ddrphy_dfi_p2_bank == 3'd7);
+ end
+ 4'd8: begin
+ soc_ddrphy_bankmodel7_read <= (soc_ddrphy_dfi_p3_bank == 3'd7);
+ end
+ endcase
+end
+always @(*) begin
+ soc_ddrphy_bankmodel7_read_col <= 10'd0;
+ case (soc_ddrphy_reads7)
+ 1'd1: begin
+ soc_ddrphy_bankmodel7_read_col <= soc_ddrphy_dfi_p0_address;
+ end
+ 2'd2: begin
+ soc_ddrphy_bankmodel7_read_col <= soc_ddrphy_dfi_p1_address;
+ end
+ 3'd4: begin
+ soc_ddrphy_bankmodel7_read_col <= soc_ddrphy_dfi_p2_address;
+ end
+ 4'd8: begin
+ soc_ddrphy_bankmodel7_read_col <= soc_ddrphy_dfi_p3_address;
+ end
+ endcase
end
assign soc_ddrphy_banks_read = (((((((soc_ddrphy_bankmodel0_read | soc_ddrphy_bankmodel1_read) | soc_ddrphy_bankmodel2_read) | soc_ddrphy_bankmodel3_read) | soc_ddrphy_bankmodel4_read) | soc_ddrphy_bankmodel5_read) | soc_ddrphy_bankmodel6_read) | soc_ddrphy_bankmodel7_read);
assign soc_ddrphy_banks_read_data = (((((((soc_ddrphy_bankmodel0_read_data | soc_ddrphy_bankmodel1_read_data) | soc_ddrphy_bankmodel2_read_data) | soc_ddrphy_bankmodel3_read_data) | soc_ddrphy_bankmodel4_read_data) | soc_ddrphy_bankmodel5_read_data) | soc_ddrphy_bankmodel6_read_data) | soc_ddrphy_bankmodel7_read_data);
assign {soc_ddrphy_dfi_p3_rddata, soc_ddrphy_dfi_p2_rddata, soc_ddrphy_dfi_p1_rddata, soc_ddrphy_dfi_p0_rddata} = soc_ddrphy_new_banks_read_data7;
assign {soc_ddrphy_dfi_p3_rddata, soc_ddrphy_dfi_p2_rddata, soc_ddrphy_dfi_p1_rddata, soc_ddrphy_dfi_p0_rddata} = soc_ddrphy_new_banks_read_data7;
always @(*) begin
- soc_ddrphy_dfiphasemodel0_precharge <= 1'd0;
- if ((((~soc_ddrphy_dfi_p0_cs_n) & (~soc_ddrphy_dfi_p0_ras_n)) & soc_ddrphy_dfi_p0_cas_n)) begin
- soc_ddrphy_dfiphasemodel0_precharge <= (~soc_ddrphy_dfi_p0_we_n);
- end
+ soc_ddrphy_dfiphasemodel0_precharge <= 1'd0;
+ if ((((~soc_ddrphy_dfi_p0_cs_n) & (~soc_ddrphy_dfi_p0_ras_n)) & soc_ddrphy_dfi_p0_cas_n)) begin
+ soc_ddrphy_dfiphasemodel0_precharge <= (~soc_ddrphy_dfi_p0_we_n);
+ end
end
always @(*) begin
- soc_ddrphy_dfiphasemodel0_activate <= 1'd0;
- if ((((~soc_ddrphy_dfi_p0_cs_n) & (~soc_ddrphy_dfi_p0_ras_n)) & soc_ddrphy_dfi_p0_cas_n)) begin
- soc_ddrphy_dfiphasemodel0_activate <= soc_ddrphy_dfi_p0_we_n;
- end
+ soc_ddrphy_dfiphasemodel0_activate <= 1'd0;
+ if ((((~soc_ddrphy_dfi_p0_cs_n) & (~soc_ddrphy_dfi_p0_ras_n)) & soc_ddrphy_dfi_p0_cas_n)) begin
+ soc_ddrphy_dfiphasemodel0_activate <= soc_ddrphy_dfi_p0_we_n;
+ end
end
always @(*) begin
- soc_ddrphy_dfiphasemodel0_write <= 1'd0;
- if ((((~soc_ddrphy_dfi_p0_cs_n) & soc_ddrphy_dfi_p0_ras_n) & (~soc_ddrphy_dfi_p0_cas_n))) begin
- soc_ddrphy_dfiphasemodel0_write <= (~soc_ddrphy_dfi_p0_we_n);
- end
+ soc_ddrphy_dfiphasemodel0_write <= 1'd0;
+ if ((((~soc_ddrphy_dfi_p0_cs_n) & soc_ddrphy_dfi_p0_ras_n) & (~soc_ddrphy_dfi_p0_cas_n))) begin
+ soc_ddrphy_dfiphasemodel0_write <= (~soc_ddrphy_dfi_p0_we_n);
+ end
end
always @(*) begin
- soc_ddrphy_dfiphasemodel0_read <= 1'd0;
- if ((((~soc_ddrphy_dfi_p0_cs_n) & soc_ddrphy_dfi_p0_ras_n) & (~soc_ddrphy_dfi_p0_cas_n))) begin
- soc_ddrphy_dfiphasemodel0_read <= soc_ddrphy_dfi_p0_we_n;
- end
+ soc_ddrphy_dfiphasemodel0_read <= 1'd0;
+ if ((((~soc_ddrphy_dfi_p0_cs_n) & soc_ddrphy_dfi_p0_ras_n) & (~soc_ddrphy_dfi_p0_cas_n))) begin
+ soc_ddrphy_dfiphasemodel0_read <= soc_ddrphy_dfi_p0_we_n;
+ end
end
always @(*) begin
- soc_ddrphy_dfiphasemodel1_activate <= 1'd0;
- if ((((~soc_ddrphy_dfi_p1_cs_n) & (~soc_ddrphy_dfi_p1_ras_n)) & soc_ddrphy_dfi_p1_cas_n)) begin
- soc_ddrphy_dfiphasemodel1_activate <= soc_ddrphy_dfi_p1_we_n;
- end
+ soc_ddrphy_dfiphasemodel1_activate <= 1'd0;
+ if ((((~soc_ddrphy_dfi_p1_cs_n) & (~soc_ddrphy_dfi_p1_ras_n)) & soc_ddrphy_dfi_p1_cas_n)) begin
+ soc_ddrphy_dfiphasemodel1_activate <= soc_ddrphy_dfi_p1_we_n;
+ end
end
always @(*) begin
- soc_ddrphy_dfiphasemodel1_precharge <= 1'd0;
- if ((((~soc_ddrphy_dfi_p1_cs_n) & (~soc_ddrphy_dfi_p1_ras_n)) & soc_ddrphy_dfi_p1_cas_n)) begin
- soc_ddrphy_dfiphasemodel1_precharge <= (~soc_ddrphy_dfi_p1_we_n);
- end
+ soc_ddrphy_dfiphasemodel1_precharge <= 1'd0;
+ if ((((~soc_ddrphy_dfi_p1_cs_n) & (~soc_ddrphy_dfi_p1_ras_n)) & soc_ddrphy_dfi_p1_cas_n)) begin
+ soc_ddrphy_dfiphasemodel1_precharge <= (~soc_ddrphy_dfi_p1_we_n);
+ end
end
always @(*) begin
- soc_ddrphy_dfiphasemodel1_write <= 1'd0;
- if ((((~soc_ddrphy_dfi_p1_cs_n) & soc_ddrphy_dfi_p1_ras_n) & (~soc_ddrphy_dfi_p1_cas_n))) begin
- soc_ddrphy_dfiphasemodel1_write <= (~soc_ddrphy_dfi_p1_we_n);
- end
+ soc_ddrphy_dfiphasemodel1_write <= 1'd0;
+ if ((((~soc_ddrphy_dfi_p1_cs_n) & soc_ddrphy_dfi_p1_ras_n) & (~soc_ddrphy_dfi_p1_cas_n))) begin
+ soc_ddrphy_dfiphasemodel1_write <= (~soc_ddrphy_dfi_p1_we_n);
+ end
end
always @(*) begin
- soc_ddrphy_dfiphasemodel1_read <= 1'd0;
- if ((((~soc_ddrphy_dfi_p1_cs_n) & soc_ddrphy_dfi_p1_ras_n) & (~soc_ddrphy_dfi_p1_cas_n))) begin
- soc_ddrphy_dfiphasemodel1_read <= soc_ddrphy_dfi_p1_we_n;
- end
+ soc_ddrphy_dfiphasemodel1_read <= 1'd0;
+ if ((((~soc_ddrphy_dfi_p1_cs_n) & soc_ddrphy_dfi_p1_ras_n) & (~soc_ddrphy_dfi_p1_cas_n))) begin
+ soc_ddrphy_dfiphasemodel1_read <= soc_ddrphy_dfi_p1_we_n;
+ end
end
always @(*) begin
- soc_ddrphy_dfiphasemodel2_activate <= 1'd0;
- if ((((~soc_ddrphy_dfi_p2_cs_n) & (~soc_ddrphy_dfi_p2_ras_n)) & soc_ddrphy_dfi_p2_cas_n)) begin
- soc_ddrphy_dfiphasemodel2_activate <= soc_ddrphy_dfi_p2_we_n;
- end
+ soc_ddrphy_dfiphasemodel2_activate <= 1'd0;
+ if ((((~soc_ddrphy_dfi_p2_cs_n) & (~soc_ddrphy_dfi_p2_ras_n)) & soc_ddrphy_dfi_p2_cas_n)) begin
+ soc_ddrphy_dfiphasemodel2_activate <= soc_ddrphy_dfi_p2_we_n;
+ end
end
always @(*) begin
- soc_ddrphy_dfiphasemodel2_precharge <= 1'd0;
- if ((((~soc_ddrphy_dfi_p2_cs_n) & (~soc_ddrphy_dfi_p2_ras_n)) & soc_ddrphy_dfi_p2_cas_n)) begin
- soc_ddrphy_dfiphasemodel2_precharge <= (~soc_ddrphy_dfi_p2_we_n);
- end
+ soc_ddrphy_dfiphasemodel2_precharge <= 1'd0;
+ if ((((~soc_ddrphy_dfi_p2_cs_n) & (~soc_ddrphy_dfi_p2_ras_n)) & soc_ddrphy_dfi_p2_cas_n)) begin
+ soc_ddrphy_dfiphasemodel2_precharge <= (~soc_ddrphy_dfi_p2_we_n);
+ end
end
always @(*) begin
- soc_ddrphy_dfiphasemodel2_read <= 1'd0;
- if ((((~soc_ddrphy_dfi_p2_cs_n) & soc_ddrphy_dfi_p2_ras_n) & (~soc_ddrphy_dfi_p2_cas_n))) begin
- soc_ddrphy_dfiphasemodel2_read <= soc_ddrphy_dfi_p2_we_n;
- end
+ soc_ddrphy_dfiphasemodel2_read <= 1'd0;
+ if ((((~soc_ddrphy_dfi_p2_cs_n) & soc_ddrphy_dfi_p2_ras_n) & (~soc_ddrphy_dfi_p2_cas_n))) begin
+ soc_ddrphy_dfiphasemodel2_read <= soc_ddrphy_dfi_p2_we_n;
+ end
end
always @(*) begin
- soc_ddrphy_dfiphasemodel2_write <= 1'd0;
- if ((((~soc_ddrphy_dfi_p2_cs_n) & soc_ddrphy_dfi_p2_ras_n) & (~soc_ddrphy_dfi_p2_cas_n))) begin
- soc_ddrphy_dfiphasemodel2_write <= (~soc_ddrphy_dfi_p2_we_n);
- end
+ soc_ddrphy_dfiphasemodel2_write <= 1'd0;
+ if ((((~soc_ddrphy_dfi_p2_cs_n) & soc_ddrphy_dfi_p2_ras_n) & (~soc_ddrphy_dfi_p2_cas_n))) begin
+ soc_ddrphy_dfiphasemodel2_write <= (~soc_ddrphy_dfi_p2_we_n);
+ end
end
always @(*) begin
- soc_ddrphy_dfiphasemodel3_activate <= 1'd0;
- if ((((~soc_ddrphy_dfi_p3_cs_n) & (~soc_ddrphy_dfi_p3_ras_n)) & soc_ddrphy_dfi_p3_cas_n)) begin
- soc_ddrphy_dfiphasemodel3_activate <= soc_ddrphy_dfi_p3_we_n;
- end
+ soc_ddrphy_dfiphasemodel3_activate <= 1'd0;
+ if ((((~soc_ddrphy_dfi_p3_cs_n) & (~soc_ddrphy_dfi_p3_ras_n)) & soc_ddrphy_dfi_p3_cas_n)) begin
+ soc_ddrphy_dfiphasemodel3_activate <= soc_ddrphy_dfi_p3_we_n;
+ end
end
always @(*) begin
- soc_ddrphy_dfiphasemodel3_precharge <= 1'd0;
- if ((((~soc_ddrphy_dfi_p3_cs_n) & (~soc_ddrphy_dfi_p3_ras_n)) & soc_ddrphy_dfi_p3_cas_n)) begin
- soc_ddrphy_dfiphasemodel3_precharge <= (~soc_ddrphy_dfi_p3_we_n);
- end
+ soc_ddrphy_dfiphasemodel3_precharge <= 1'd0;
+ if ((((~soc_ddrphy_dfi_p3_cs_n) & (~soc_ddrphy_dfi_p3_ras_n)) & soc_ddrphy_dfi_p3_cas_n)) begin
+ soc_ddrphy_dfiphasemodel3_precharge <= (~soc_ddrphy_dfi_p3_we_n);
+ end
end
always @(*) begin
- soc_ddrphy_dfiphasemodel3_write <= 1'd0;
- if ((((~soc_ddrphy_dfi_p3_cs_n) & soc_ddrphy_dfi_p3_ras_n) & (~soc_ddrphy_dfi_p3_cas_n))) begin
- soc_ddrphy_dfiphasemodel3_write <= (~soc_ddrphy_dfi_p3_we_n);
- end
+ soc_ddrphy_dfiphasemodel3_write <= 1'd0;
+ if ((((~soc_ddrphy_dfi_p3_cs_n) & soc_ddrphy_dfi_p3_ras_n) & (~soc_ddrphy_dfi_p3_cas_n))) begin
+ soc_ddrphy_dfiphasemodel3_write <= (~soc_ddrphy_dfi_p3_we_n);
+ end
end
always @(*) begin
- soc_ddrphy_dfiphasemodel3_read <= 1'd0;
- if ((((~soc_ddrphy_dfi_p3_cs_n) & soc_ddrphy_dfi_p3_ras_n) & (~soc_ddrphy_dfi_p3_cas_n))) begin
- soc_ddrphy_dfiphasemodel3_read <= soc_ddrphy_dfi_p3_we_n;
- end
+ soc_ddrphy_dfiphasemodel3_read <= 1'd0;
+ if ((((~soc_ddrphy_dfi_p3_cs_n) & soc_ddrphy_dfi_p3_ras_n) & (~soc_ddrphy_dfi_p3_cas_n))) begin
+ soc_ddrphy_dfiphasemodel3_read <= soc_ddrphy_dfi_p3_we_n;
+ end
end
assign soc_ddrphy_bankmodel0_wraddr = slice_proxy0[24:3];
assign soc_ddrphy_bankmodel0_rdaddr = slice_proxy1[24:3];
always @(*) begin
- soc_ddrphy_bankmodel0_read_data <= 128'd0;
- if (soc_ddrphy_bankmodel0_active) begin
- if (soc_ddrphy_bankmodel0_read) begin
- soc_ddrphy_bankmodel0_read_data <= soc_ddrphy_bankmodel0_read_port_dat_r;
- end
- end
+ soc_ddrphy_bankmodel0_read_data <= 128'd0;
+ if (soc_ddrphy_bankmodel0_active) begin
+ if (soc_ddrphy_bankmodel0_read) begin
+ soc_ddrphy_bankmodel0_read_data <= soc_ddrphy_bankmodel0_read_port_dat_r;
+ end
+ end
end
always @(*) begin
- soc_ddrphy_bankmodel0_write_port_adr <= 21'd0;
- if (soc_ddrphy_bankmodel0_active) begin
- soc_ddrphy_bankmodel0_write_port_adr <= soc_ddrphy_bankmodel0_wraddr;
- end
+ soc_ddrphy_bankmodel0_write_port_adr <= 21'd0;
+ if (soc_ddrphy_bankmodel0_active) begin
+ soc_ddrphy_bankmodel0_write_port_adr <= soc_ddrphy_bankmodel0_wraddr;
+ end
end
always @(*) begin
- soc_ddrphy_bankmodel0_write_port_we <= 16'd0;
- if (soc_ddrphy_bankmodel0_active) begin
- if (4'd8) begin
- soc_ddrphy_bankmodel0_write_port_we <= ({16{soc_ddrphy_bankmodel0_write}} & (~soc_ddrphy_bankmodel0_write_mask));
- end else begin
- soc_ddrphy_bankmodel0_write_port_we <= soc_ddrphy_bankmodel0_write;
- end
- end
+ soc_ddrphy_bankmodel0_write_port_we <= 16'd0;
+ if (soc_ddrphy_bankmodel0_active) begin
+ if (4'd8) begin
+ soc_ddrphy_bankmodel0_write_port_we <= ({16{soc_ddrphy_bankmodel0_write}} & (~soc_ddrphy_bankmodel0_write_mask));
+ end else begin
+ soc_ddrphy_bankmodel0_write_port_we <= soc_ddrphy_bankmodel0_write;
+ end
+ end
end
always @(*) begin
- soc_ddrphy_bankmodel0_write_port_dat_w <= 128'd0;
- if (soc_ddrphy_bankmodel0_active) begin
- soc_ddrphy_bankmodel0_write_port_dat_w <= soc_ddrphy_bankmodel0_write_data;
- end
+ soc_ddrphy_bankmodel0_write_port_dat_w <= 128'd0;
+ if (soc_ddrphy_bankmodel0_active) begin
+ soc_ddrphy_bankmodel0_write_port_dat_w <= soc_ddrphy_bankmodel0_write_data;
+ end
end
always @(*) begin
- soc_ddrphy_bankmodel0_read_port_adr <= 21'd0;
- if (soc_ddrphy_bankmodel0_active) begin
- if (soc_ddrphy_bankmodel0_read) begin
- soc_ddrphy_bankmodel0_read_port_adr <= soc_ddrphy_bankmodel0_rdaddr;
- end
- end
+ soc_ddrphy_bankmodel0_read_port_adr <= 21'd0;
+ if (soc_ddrphy_bankmodel0_active) begin
+ if (soc_ddrphy_bankmodel0_read) begin
+ soc_ddrphy_bankmodel0_read_port_adr <= soc_ddrphy_bankmodel0_rdaddr;
+ end
+ end
end
assign soc_ddrphy_bankmodel1_wraddr = slice_proxy2[24:3];
assign soc_ddrphy_bankmodel1_rdaddr = slice_proxy3[24:3];
always @(*) begin
- soc_ddrphy_bankmodel1_read_data <= 128'd0;
- if (soc_ddrphy_bankmodel1_active) begin
- if (soc_ddrphy_bankmodel1_read) begin
- soc_ddrphy_bankmodel1_read_data <= soc_ddrphy_bankmodel1_read_port_dat_r;
- end
- end
+ soc_ddrphy_bankmodel1_read_data <= 128'd0;
+ if (soc_ddrphy_bankmodel1_active) begin
+ if (soc_ddrphy_bankmodel1_read) begin
+ soc_ddrphy_bankmodel1_read_data <= soc_ddrphy_bankmodel1_read_port_dat_r;
+ end
+ end
end
always @(*) begin
- soc_ddrphy_bankmodel1_write_port_adr <= 21'd0;
- if (soc_ddrphy_bankmodel1_active) begin
- soc_ddrphy_bankmodel1_write_port_adr <= soc_ddrphy_bankmodel1_wraddr;
- end
+ soc_ddrphy_bankmodel1_write_port_adr <= 21'd0;
+ if (soc_ddrphy_bankmodel1_active) begin
+ soc_ddrphy_bankmodel1_write_port_adr <= soc_ddrphy_bankmodel1_wraddr;
+ end
end
always @(*) begin
- soc_ddrphy_bankmodel1_write_port_we <= 16'd0;
- if (soc_ddrphy_bankmodel1_active) begin
- if (4'd8) begin
- soc_ddrphy_bankmodel1_write_port_we <= ({16{soc_ddrphy_bankmodel1_write}} & (~soc_ddrphy_bankmodel1_write_mask));
- end else begin
- soc_ddrphy_bankmodel1_write_port_we <= soc_ddrphy_bankmodel1_write;
- end
- end
+ soc_ddrphy_bankmodel1_write_port_we <= 16'd0;
+ if (soc_ddrphy_bankmodel1_active) begin
+ if (4'd8) begin
+ soc_ddrphy_bankmodel1_write_port_we <= ({16{soc_ddrphy_bankmodel1_write}} & (~soc_ddrphy_bankmodel1_write_mask));
+ end else begin
+ soc_ddrphy_bankmodel1_write_port_we <= soc_ddrphy_bankmodel1_write;
+ end
+ end
end
always @(*) begin
- soc_ddrphy_bankmodel1_write_port_dat_w <= 128'd0;
- if (soc_ddrphy_bankmodel1_active) begin
- soc_ddrphy_bankmodel1_write_port_dat_w <= soc_ddrphy_bankmodel1_write_data;
- end
+ soc_ddrphy_bankmodel1_write_port_dat_w <= 128'd0;
+ if (soc_ddrphy_bankmodel1_active) begin
+ soc_ddrphy_bankmodel1_write_port_dat_w <= soc_ddrphy_bankmodel1_write_data;
+ end
end
always @(*) begin
- soc_ddrphy_bankmodel1_read_port_adr <= 21'd0;
- if (soc_ddrphy_bankmodel1_active) begin
- if (soc_ddrphy_bankmodel1_read) begin
- soc_ddrphy_bankmodel1_read_port_adr <= soc_ddrphy_bankmodel1_rdaddr;
- end
- end
+ soc_ddrphy_bankmodel1_read_port_adr <= 21'd0;
+ if (soc_ddrphy_bankmodel1_active) begin
+ if (soc_ddrphy_bankmodel1_read) begin
+ soc_ddrphy_bankmodel1_read_port_adr <= soc_ddrphy_bankmodel1_rdaddr;
+ end
+ end
end
assign soc_ddrphy_bankmodel2_wraddr = slice_proxy4[24:3];
assign soc_ddrphy_bankmodel2_rdaddr = slice_proxy5[24:3];
always @(*) begin
- soc_ddrphy_bankmodel2_write_port_adr <= 21'd0;
- if (soc_ddrphy_bankmodel2_active) begin
- soc_ddrphy_bankmodel2_write_port_adr <= soc_ddrphy_bankmodel2_wraddr;
- end
+ soc_ddrphy_bankmodel2_write_port_adr <= 21'd0;
+ if (soc_ddrphy_bankmodel2_active) begin
+ soc_ddrphy_bankmodel2_write_port_adr <= soc_ddrphy_bankmodel2_wraddr;
+ end
end
always @(*) begin
- soc_ddrphy_bankmodel2_write_port_we <= 16'd0;
- if (soc_ddrphy_bankmodel2_active) begin
- if (4'd8) begin
- soc_ddrphy_bankmodel2_write_port_we <= ({16{soc_ddrphy_bankmodel2_write}} & (~soc_ddrphy_bankmodel2_write_mask));
- end else begin
- soc_ddrphy_bankmodel2_write_port_we <= soc_ddrphy_bankmodel2_write;
- end
- end
+ soc_ddrphy_bankmodel2_write_port_we <= 16'd0;
+ if (soc_ddrphy_bankmodel2_active) begin
+ if (4'd8) begin
+ soc_ddrphy_bankmodel2_write_port_we <= ({16{soc_ddrphy_bankmodel2_write}} & (~soc_ddrphy_bankmodel2_write_mask));
+ end else begin
+ soc_ddrphy_bankmodel2_write_port_we <= soc_ddrphy_bankmodel2_write;
+ end
+ end
end
always @(*) begin
- soc_ddrphy_bankmodel2_write_port_dat_w <= 128'd0;
- if (soc_ddrphy_bankmodel2_active) begin
- soc_ddrphy_bankmodel2_write_port_dat_w <= soc_ddrphy_bankmodel2_write_data;
- end
+ soc_ddrphy_bankmodel2_write_port_dat_w <= 128'd0;
+ if (soc_ddrphy_bankmodel2_active) begin
+ soc_ddrphy_bankmodel2_write_port_dat_w <= soc_ddrphy_bankmodel2_write_data;
+ end
end
always @(*) begin
- soc_ddrphy_bankmodel2_read_port_adr <= 21'd0;
- if (soc_ddrphy_bankmodel2_active) begin
- if (soc_ddrphy_bankmodel2_read) begin
- soc_ddrphy_bankmodel2_read_port_adr <= soc_ddrphy_bankmodel2_rdaddr;
- end
- end
+ soc_ddrphy_bankmodel2_read_port_adr <= 21'd0;
+ if (soc_ddrphy_bankmodel2_active) begin
+ if (soc_ddrphy_bankmodel2_read) begin
+ soc_ddrphy_bankmodel2_read_port_adr <= soc_ddrphy_bankmodel2_rdaddr;
+ end
+ end
end
always @(*) begin
- soc_ddrphy_bankmodel2_read_data <= 128'd0;
- if (soc_ddrphy_bankmodel2_active) begin
- if (soc_ddrphy_bankmodel2_read) begin
- soc_ddrphy_bankmodel2_read_data <= soc_ddrphy_bankmodel2_read_port_dat_r;
- end
- end
+ soc_ddrphy_bankmodel2_read_data <= 128'd0;
+ if (soc_ddrphy_bankmodel2_active) begin
+ if (soc_ddrphy_bankmodel2_read) begin
+ soc_ddrphy_bankmodel2_read_data <= soc_ddrphy_bankmodel2_read_port_dat_r;
+ end
+ end
end
assign soc_ddrphy_bankmodel3_wraddr = slice_proxy6[24:3];
assign soc_ddrphy_bankmodel3_rdaddr = slice_proxy7[24:3];
always @(*) begin
- soc_ddrphy_bankmodel3_write_port_adr <= 21'd0;
- if (soc_ddrphy_bankmodel3_active) begin
- soc_ddrphy_bankmodel3_write_port_adr <= soc_ddrphy_bankmodel3_wraddr;
- end
+ soc_ddrphy_bankmodel3_write_port_adr <= 21'd0;
+ if (soc_ddrphy_bankmodel3_active) begin
+ soc_ddrphy_bankmodel3_write_port_adr <= soc_ddrphy_bankmodel3_wraddr;
+ end
end
always @(*) begin
- soc_ddrphy_bankmodel3_write_port_we <= 16'd0;
- if (soc_ddrphy_bankmodel3_active) begin
- if (4'd8) begin
- soc_ddrphy_bankmodel3_write_port_we <= ({16{soc_ddrphy_bankmodel3_write}} & (~soc_ddrphy_bankmodel3_write_mask));
- end else begin
- soc_ddrphy_bankmodel3_write_port_we <= soc_ddrphy_bankmodel3_write;
- end
- end
+ soc_ddrphy_bankmodel3_write_port_we <= 16'd0;
+ if (soc_ddrphy_bankmodel3_active) begin
+ if (4'd8) begin
+ soc_ddrphy_bankmodel3_write_port_we <= ({16{soc_ddrphy_bankmodel3_write}} & (~soc_ddrphy_bankmodel3_write_mask));
+ end else begin
+ soc_ddrphy_bankmodel3_write_port_we <= soc_ddrphy_bankmodel3_write;
+ end
+ end
end
always @(*) begin
- soc_ddrphy_bankmodel3_write_port_dat_w <= 128'd0;
- if (soc_ddrphy_bankmodel3_active) begin
- soc_ddrphy_bankmodel3_write_port_dat_w <= soc_ddrphy_bankmodel3_write_data;
- end
+ soc_ddrphy_bankmodel3_write_port_dat_w <= 128'd0;
+ if (soc_ddrphy_bankmodel3_active) begin
+ soc_ddrphy_bankmodel3_write_port_dat_w <= soc_ddrphy_bankmodel3_write_data;
+ end
end
always @(*) begin
- soc_ddrphy_bankmodel3_read_port_adr <= 21'd0;
- if (soc_ddrphy_bankmodel3_active) begin
- if (soc_ddrphy_bankmodel3_read) begin
- soc_ddrphy_bankmodel3_read_port_adr <= soc_ddrphy_bankmodel3_rdaddr;
- end
- end
+ soc_ddrphy_bankmodel3_read_port_adr <= 21'd0;
+ if (soc_ddrphy_bankmodel3_active) begin
+ if (soc_ddrphy_bankmodel3_read) begin
+ soc_ddrphy_bankmodel3_read_port_adr <= soc_ddrphy_bankmodel3_rdaddr;
+ end
+ end
end
always @(*) begin
- soc_ddrphy_bankmodel3_read_data <= 128'd0;
- if (soc_ddrphy_bankmodel3_active) begin
- if (soc_ddrphy_bankmodel3_read) begin
- soc_ddrphy_bankmodel3_read_data <= soc_ddrphy_bankmodel3_read_port_dat_r;
- end
- end
+ soc_ddrphy_bankmodel3_read_data <= 128'd0;
+ if (soc_ddrphy_bankmodel3_active) begin
+ if (soc_ddrphy_bankmodel3_read) begin
+ soc_ddrphy_bankmodel3_read_data <= soc_ddrphy_bankmodel3_read_port_dat_r;
+ end
+ end
end
assign soc_ddrphy_bankmodel4_wraddr = slice_proxy8[24:3];
assign soc_ddrphy_bankmodel4_rdaddr = slice_proxy9[24:3];
always @(*) begin
- soc_ddrphy_bankmodel4_write_port_we <= 16'd0;
- if (soc_ddrphy_bankmodel4_active) begin
- if (4'd8) begin
- soc_ddrphy_bankmodel4_write_port_we <= ({16{soc_ddrphy_bankmodel4_write}} & (~soc_ddrphy_bankmodel4_write_mask));
- end else begin
- soc_ddrphy_bankmodel4_write_port_we <= soc_ddrphy_bankmodel4_write;
- end
- end
+ soc_ddrphy_bankmodel4_write_port_we <= 16'd0;
+ if (soc_ddrphy_bankmodel4_active) begin
+ if (4'd8) begin
+ soc_ddrphy_bankmodel4_write_port_we <= ({16{soc_ddrphy_bankmodel4_write}} & (~soc_ddrphy_bankmodel4_write_mask));
+ end else begin
+ soc_ddrphy_bankmodel4_write_port_we <= soc_ddrphy_bankmodel4_write;
+ end
+ end
end
always @(*) begin
- soc_ddrphy_bankmodel4_write_port_dat_w <= 128'd0;
- if (soc_ddrphy_bankmodel4_active) begin
- soc_ddrphy_bankmodel4_write_port_dat_w <= soc_ddrphy_bankmodel4_write_data;
- end
+ soc_ddrphy_bankmodel4_write_port_dat_w <= 128'd0;
+ if (soc_ddrphy_bankmodel4_active) begin
+ soc_ddrphy_bankmodel4_write_port_dat_w <= soc_ddrphy_bankmodel4_write_data;
+ end
end
always @(*) begin
- soc_ddrphy_bankmodel4_read_port_adr <= 21'd0;
- if (soc_ddrphy_bankmodel4_active) begin
- if (soc_ddrphy_bankmodel4_read) begin
- soc_ddrphy_bankmodel4_read_port_adr <= soc_ddrphy_bankmodel4_rdaddr;
- end
- end
+ soc_ddrphy_bankmodel4_read_port_adr <= 21'd0;
+ if (soc_ddrphy_bankmodel4_active) begin
+ if (soc_ddrphy_bankmodel4_read) begin
+ soc_ddrphy_bankmodel4_read_port_adr <= soc_ddrphy_bankmodel4_rdaddr;
+ end
+ end
end
always @(*) begin
- soc_ddrphy_bankmodel4_read_data <= 128'd0;
- if (soc_ddrphy_bankmodel4_active) begin
- if (soc_ddrphy_bankmodel4_read) begin
- soc_ddrphy_bankmodel4_read_data <= soc_ddrphy_bankmodel4_read_port_dat_r;
- end
- end
+ soc_ddrphy_bankmodel4_read_data <= 128'd0;
+ if (soc_ddrphy_bankmodel4_active) begin
+ if (soc_ddrphy_bankmodel4_read) begin
+ soc_ddrphy_bankmodel4_read_data <= soc_ddrphy_bankmodel4_read_port_dat_r;
+ end
+ end
end
always @(*) begin
- soc_ddrphy_bankmodel4_write_port_adr <= 21'd0;
- if (soc_ddrphy_bankmodel4_active) begin
- soc_ddrphy_bankmodel4_write_port_adr <= soc_ddrphy_bankmodel4_wraddr;
- end
+ soc_ddrphy_bankmodel4_write_port_adr <= 21'd0;
+ if (soc_ddrphy_bankmodel4_active) begin
+ soc_ddrphy_bankmodel4_write_port_adr <= soc_ddrphy_bankmodel4_wraddr;
+ end
end
assign soc_ddrphy_bankmodel5_wraddr = slice_proxy10[24:3];
assign soc_ddrphy_bankmodel5_rdaddr = slice_proxy11[24:3];
always @(*) begin
- soc_ddrphy_bankmodel5_read_port_adr <= 21'd0;
- if (soc_ddrphy_bankmodel5_active) begin
- if (soc_ddrphy_bankmodel5_read) begin
- soc_ddrphy_bankmodel5_read_port_adr <= soc_ddrphy_bankmodel5_rdaddr;
- end
- end
+ soc_ddrphy_bankmodel5_read_port_adr <= 21'd0;
+ if (soc_ddrphy_bankmodel5_active) begin
+ if (soc_ddrphy_bankmodel5_read) begin
+ soc_ddrphy_bankmodel5_read_port_adr <= soc_ddrphy_bankmodel5_rdaddr;
+ end
+ end
end
always @(*) begin
- soc_ddrphy_bankmodel5_read_data <= 128'd0;
- if (soc_ddrphy_bankmodel5_active) begin
- if (soc_ddrphy_bankmodel5_read) begin
- soc_ddrphy_bankmodel5_read_data <= soc_ddrphy_bankmodel5_read_port_dat_r;
- end
- end
+ soc_ddrphy_bankmodel5_read_data <= 128'd0;
+ if (soc_ddrphy_bankmodel5_active) begin
+ if (soc_ddrphy_bankmodel5_read) begin
+ soc_ddrphy_bankmodel5_read_data <= soc_ddrphy_bankmodel5_read_port_dat_r;
+ end
+ end
end
always @(*) begin
- soc_ddrphy_bankmodel5_write_port_adr <= 21'd0;
- if (soc_ddrphy_bankmodel5_active) begin
- soc_ddrphy_bankmodel5_write_port_adr <= soc_ddrphy_bankmodel5_wraddr;
- end
+ soc_ddrphy_bankmodel5_write_port_adr <= 21'd0;
+ if (soc_ddrphy_bankmodel5_active) begin
+ soc_ddrphy_bankmodel5_write_port_adr <= soc_ddrphy_bankmodel5_wraddr;
+ end
end
always @(*) begin
- soc_ddrphy_bankmodel5_write_port_we <= 16'd0;
- if (soc_ddrphy_bankmodel5_active) begin
- if (4'd8) begin
- soc_ddrphy_bankmodel5_write_port_we <= ({16{soc_ddrphy_bankmodel5_write}} & (~soc_ddrphy_bankmodel5_write_mask));
- end else begin
- soc_ddrphy_bankmodel5_write_port_we <= soc_ddrphy_bankmodel5_write;
- end
- end
+ soc_ddrphy_bankmodel5_write_port_we <= 16'd0;
+ if (soc_ddrphy_bankmodel5_active) begin
+ if (4'd8) begin
+ soc_ddrphy_bankmodel5_write_port_we <= ({16{soc_ddrphy_bankmodel5_write}} & (~soc_ddrphy_bankmodel5_write_mask));
+ end else begin
+ soc_ddrphy_bankmodel5_write_port_we <= soc_ddrphy_bankmodel5_write;
+ end
+ end
end
always @(*) begin
- soc_ddrphy_bankmodel5_write_port_dat_w <= 128'd0;
- if (soc_ddrphy_bankmodel5_active) begin
- soc_ddrphy_bankmodel5_write_port_dat_w <= soc_ddrphy_bankmodel5_write_data;
- end
+ soc_ddrphy_bankmodel5_write_port_dat_w <= 128'd0;
+ if (soc_ddrphy_bankmodel5_active) begin
+ soc_ddrphy_bankmodel5_write_port_dat_w <= soc_ddrphy_bankmodel5_write_data;
+ end
end
assign soc_ddrphy_bankmodel6_wraddr = slice_proxy12[24:3];
assign soc_ddrphy_bankmodel6_rdaddr = slice_proxy13[24:3];
always @(*) begin
- soc_ddrphy_bankmodel6_read_data <= 128'd0;
- if (soc_ddrphy_bankmodel6_active) begin
- if (soc_ddrphy_bankmodel6_read) begin
- soc_ddrphy_bankmodel6_read_data <= soc_ddrphy_bankmodel6_read_port_dat_r;
- end
- end
+ soc_ddrphy_bankmodel6_read_data <= 128'd0;
+ if (soc_ddrphy_bankmodel6_active) begin
+ if (soc_ddrphy_bankmodel6_read) begin
+ soc_ddrphy_bankmodel6_read_data <= soc_ddrphy_bankmodel6_read_port_dat_r;
+ end
+ end
end
always @(*) begin
- soc_ddrphy_bankmodel6_write_port_adr <= 21'd0;
- if (soc_ddrphy_bankmodel6_active) begin
- soc_ddrphy_bankmodel6_write_port_adr <= soc_ddrphy_bankmodel6_wraddr;
- end
+ soc_ddrphy_bankmodel6_write_port_adr <= 21'd0;
+ if (soc_ddrphy_bankmodel6_active) begin
+ soc_ddrphy_bankmodel6_write_port_adr <= soc_ddrphy_bankmodel6_wraddr;
+ end
end
always @(*) begin
- soc_ddrphy_bankmodel6_write_port_we <= 16'd0;
- if (soc_ddrphy_bankmodel6_active) begin
- if (4'd8) begin
- soc_ddrphy_bankmodel6_write_port_we <= ({16{soc_ddrphy_bankmodel6_write}} & (~soc_ddrphy_bankmodel6_write_mask));
- end else begin
- soc_ddrphy_bankmodel6_write_port_we <= soc_ddrphy_bankmodel6_write;
- end
- end
+ soc_ddrphy_bankmodel6_write_port_we <= 16'd0;
+ if (soc_ddrphy_bankmodel6_active) begin
+ if (4'd8) begin
+ soc_ddrphy_bankmodel6_write_port_we <= ({16{soc_ddrphy_bankmodel6_write}} & (~soc_ddrphy_bankmodel6_write_mask));
+ end else begin
+ soc_ddrphy_bankmodel6_write_port_we <= soc_ddrphy_bankmodel6_write;
+ end
+ end
end
always @(*) begin
- soc_ddrphy_bankmodel6_write_port_dat_w <= 128'd0;
- if (soc_ddrphy_bankmodel6_active) begin
- soc_ddrphy_bankmodel6_write_port_dat_w <= soc_ddrphy_bankmodel6_write_data;
- end
+ soc_ddrphy_bankmodel6_write_port_dat_w <= 128'd0;
+ if (soc_ddrphy_bankmodel6_active) begin
+ soc_ddrphy_bankmodel6_write_port_dat_w <= soc_ddrphy_bankmodel6_write_data;
+ end
end
always @(*) begin
- soc_ddrphy_bankmodel6_read_port_adr <= 21'd0;
- if (soc_ddrphy_bankmodel6_active) begin
- if (soc_ddrphy_bankmodel6_read) begin
- soc_ddrphy_bankmodel6_read_port_adr <= soc_ddrphy_bankmodel6_rdaddr;
- end
- end
+ soc_ddrphy_bankmodel6_read_port_adr <= 21'd0;
+ if (soc_ddrphy_bankmodel6_active) begin
+ if (soc_ddrphy_bankmodel6_read) begin
+ soc_ddrphy_bankmodel6_read_port_adr <= soc_ddrphy_bankmodel6_rdaddr;
+ end
+ end
end
assign soc_ddrphy_bankmodel7_wraddr = slice_proxy14[24:3];
assign soc_ddrphy_bankmodel7_rdaddr = slice_proxy15[24:3];
always @(*) begin
- soc_ddrphy_bankmodel7_read_data <= 128'd0;
- if (soc_ddrphy_bankmodel7_active) begin
- if (soc_ddrphy_bankmodel7_read) begin
- soc_ddrphy_bankmodel7_read_data <= soc_ddrphy_bankmodel7_read_port_dat_r;
- end
- end
+ soc_ddrphy_bankmodel7_read_data <= 128'd0;
+ if (soc_ddrphy_bankmodel7_active) begin
+ if (soc_ddrphy_bankmodel7_read) begin
+ soc_ddrphy_bankmodel7_read_data <= soc_ddrphy_bankmodel7_read_port_dat_r;
+ end
+ end
end
always @(*) begin
- soc_ddrphy_bankmodel7_write_port_adr <= 21'd0;
- if (soc_ddrphy_bankmodel7_active) begin
- soc_ddrphy_bankmodel7_write_port_adr <= soc_ddrphy_bankmodel7_wraddr;
- end
+ soc_ddrphy_bankmodel7_write_port_adr <= 21'd0;
+ if (soc_ddrphy_bankmodel7_active) begin
+ soc_ddrphy_bankmodel7_write_port_adr <= soc_ddrphy_bankmodel7_wraddr;
+ end
end
always @(*) begin
- soc_ddrphy_bankmodel7_write_port_we <= 16'd0;
- if (soc_ddrphy_bankmodel7_active) begin
- if (4'd8) begin
- soc_ddrphy_bankmodel7_write_port_we <= ({16{soc_ddrphy_bankmodel7_write}} & (~soc_ddrphy_bankmodel7_write_mask));
- end else begin
- soc_ddrphy_bankmodel7_write_port_we <= soc_ddrphy_bankmodel7_write;
- end
- end
+ soc_ddrphy_bankmodel7_write_port_we <= 16'd0;
+ if (soc_ddrphy_bankmodel7_active) begin
+ if (4'd8) begin
+ soc_ddrphy_bankmodel7_write_port_we <= ({16{soc_ddrphy_bankmodel7_write}} & (~soc_ddrphy_bankmodel7_write_mask));
+ end else begin
+ soc_ddrphy_bankmodel7_write_port_we <= soc_ddrphy_bankmodel7_write;
+ end
+ end
end
always @(*) begin
- soc_ddrphy_bankmodel7_write_port_dat_w <= 128'd0;
- if (soc_ddrphy_bankmodel7_active) begin
- soc_ddrphy_bankmodel7_write_port_dat_w <= soc_ddrphy_bankmodel7_write_data;
- end
+ soc_ddrphy_bankmodel7_write_port_dat_w <= 128'd0;
+ if (soc_ddrphy_bankmodel7_active) begin
+ soc_ddrphy_bankmodel7_write_port_dat_w <= soc_ddrphy_bankmodel7_write_data;
+ end
end
always @(*) begin
- soc_ddrphy_bankmodel7_read_port_adr <= 21'd0;
- if (soc_ddrphy_bankmodel7_active) begin
- if (soc_ddrphy_bankmodel7_read) begin
- soc_ddrphy_bankmodel7_read_port_adr <= soc_ddrphy_bankmodel7_rdaddr;
- end
- end
+ soc_ddrphy_bankmodel7_read_port_adr <= 21'd0;
+ if (soc_ddrphy_bankmodel7_active) begin
+ if (soc_ddrphy_bankmodel7_read) begin
+ soc_ddrphy_bankmodel7_read_port_adr <= soc_ddrphy_bankmodel7_rdaddr;
+ end
+ end
end
assign soc_ddrphy_dfi_p0_address = soc_litedramcore_master_p0_address;
assign soc_ddrphy_dfi_p0_bank = soc_litedramcore_master_p0_bank;
assign soc_litedramcore_dfi_p3_rddata = soc_litedramcore_slave_p3_rddata;
assign soc_litedramcore_dfi_p3_rddata_valid = soc_litedramcore_slave_p3_rddata_valid;
always @(*) begin
- soc_litedramcore_ext_dfi_p3_rddata <= 32'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_ext_dfi_p3_rddata <= soc_litedramcore_master_p3_rddata;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- soc_litedramcore_ext_dfi_p3_rddata_valid <= 1'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_ext_dfi_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- soc_litedramcore_slave_p1_rddata <= 32'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- end else begin
- soc_litedramcore_slave_p1_rddata <= soc_litedramcore_master_p1_rddata;
- end
- end else begin
- end
-end
-always @(*) begin
- soc_litedramcore_slave_p1_rddata_valid <= 1'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- end else begin
- soc_litedramcore_slave_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid;
- end
- end else begin
- end
-end
-always @(*) begin
- soc_litedramcore_slave_p2_rddata <= 32'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- end else begin
- soc_litedramcore_slave_p2_rddata <= soc_litedramcore_master_p2_rddata;
- end
- end else begin
- end
-end
-always @(*) begin
- soc_litedramcore_slave_p2_rddata_valid <= 1'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- end else begin
- soc_litedramcore_slave_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid;
- end
- end else begin
- end
-end
-always @(*) begin
- soc_litedramcore_slave_p3_rddata <= 32'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- end else begin
- soc_litedramcore_slave_p3_rddata <= soc_litedramcore_master_p3_rddata;
- end
- end else begin
- end
-end
-always @(*) begin
- soc_litedramcore_slave_p3_rddata_valid <= 1'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- end else begin
- soc_litedramcore_slave_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid;
- end
- end else begin
- end
-end
-always @(*) begin
- soc_litedramcore_master_p0_address <= 14'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p0_address <= soc_litedramcore_ext_dfi_p0_address;
- end else begin
- soc_litedramcore_master_p0_address <= soc_litedramcore_slave_p0_address;
- end
- end else begin
- soc_litedramcore_master_p0_address <= soc_litedramcore_csr_dfi_p0_address;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p0_bank <= 3'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p0_bank <= soc_litedramcore_ext_dfi_p0_bank;
- end else begin
- soc_litedramcore_master_p0_bank <= soc_litedramcore_slave_p0_bank;
- end
- end else begin
- soc_litedramcore_master_p0_bank <= soc_litedramcore_csr_dfi_p0_bank;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p0_cas_n <= 1'd1;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p0_cas_n <= soc_litedramcore_ext_dfi_p0_cas_n;
- end else begin
- soc_litedramcore_master_p0_cas_n <= soc_litedramcore_slave_p0_cas_n;
- end
- end else begin
- soc_litedramcore_master_p0_cas_n <= soc_litedramcore_csr_dfi_p0_cas_n;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p0_cs_n <= 1'd1;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p0_cs_n <= soc_litedramcore_ext_dfi_p0_cs_n;
- end else begin
- soc_litedramcore_master_p0_cs_n <= soc_litedramcore_slave_p0_cs_n;
- end
- end else begin
- soc_litedramcore_master_p0_cs_n <= soc_litedramcore_csr_dfi_p0_cs_n;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p0_ras_n <= 1'd1;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p0_ras_n <= soc_litedramcore_ext_dfi_p0_ras_n;
- end else begin
- soc_litedramcore_master_p0_ras_n <= soc_litedramcore_slave_p0_ras_n;
- end
- end else begin
- soc_litedramcore_master_p0_ras_n <= soc_litedramcore_csr_dfi_p0_ras_n;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p0_we_n <= 1'd1;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p0_we_n <= soc_litedramcore_ext_dfi_p0_we_n;
- end else begin
- soc_litedramcore_master_p0_we_n <= soc_litedramcore_slave_p0_we_n;
- end
- end else begin
- soc_litedramcore_master_p0_we_n <= soc_litedramcore_csr_dfi_p0_we_n;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p0_cke <= 1'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p0_cke <= soc_litedramcore_ext_dfi_p0_cke;
- end else begin
- soc_litedramcore_master_p0_cke <= soc_litedramcore_slave_p0_cke;
- end
- end else begin
- soc_litedramcore_master_p0_cke <= soc_litedramcore_csr_dfi_p0_cke;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p0_odt <= 1'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p0_odt <= soc_litedramcore_ext_dfi_p0_odt;
- end else begin
- soc_litedramcore_master_p0_odt <= soc_litedramcore_slave_p0_odt;
- end
- end else begin
- soc_litedramcore_master_p0_odt <= soc_litedramcore_csr_dfi_p0_odt;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p0_reset_n <= 1'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p0_reset_n <= soc_litedramcore_ext_dfi_p0_reset_n;
- end else begin
- soc_litedramcore_master_p0_reset_n <= soc_litedramcore_slave_p0_reset_n;
- end
- end else begin
- soc_litedramcore_master_p0_reset_n <= soc_litedramcore_csr_dfi_p0_reset_n;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p0_act_n <= 1'd1;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p0_act_n <= soc_litedramcore_ext_dfi_p0_act_n;
- end else begin
- soc_litedramcore_master_p0_act_n <= soc_litedramcore_slave_p0_act_n;
- end
- end else begin
- soc_litedramcore_master_p0_act_n <= soc_litedramcore_csr_dfi_p0_act_n;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p0_wrdata <= 32'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p0_wrdata <= soc_litedramcore_ext_dfi_p0_wrdata;
- end else begin
- soc_litedramcore_master_p0_wrdata <= soc_litedramcore_slave_p0_wrdata;
- end
- end else begin
- soc_litedramcore_master_p0_wrdata <= soc_litedramcore_csr_dfi_p0_wrdata;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p0_wrdata_en <= 1'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_ext_dfi_p0_wrdata_en;
- end else begin
- soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_slave_p0_wrdata_en;
- end
- end else begin
- soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_csr_dfi_p0_wrdata_en;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p0_wrdata_mask <= 4'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_ext_dfi_p0_wrdata_mask;
- end else begin
- soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_slave_p0_wrdata_mask;
- end
- end else begin
- soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_csr_dfi_p0_wrdata_mask;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p0_rddata_en <= 1'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_ext_dfi_p0_rddata_en;
- end else begin
- soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_slave_p0_rddata_en;
- end
- end else begin
- soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_csr_dfi_p0_rddata_en;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p1_address <= 14'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p1_address <= soc_litedramcore_ext_dfi_p1_address;
- end else begin
- soc_litedramcore_master_p1_address <= soc_litedramcore_slave_p1_address;
- end
- end else begin
- soc_litedramcore_master_p1_address <= soc_litedramcore_csr_dfi_p1_address;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p1_bank <= 3'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p1_bank <= soc_litedramcore_ext_dfi_p1_bank;
- end else begin
- soc_litedramcore_master_p1_bank <= soc_litedramcore_slave_p1_bank;
- end
- end else begin
- soc_litedramcore_master_p1_bank <= soc_litedramcore_csr_dfi_p1_bank;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p1_cas_n <= 1'd1;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p1_cas_n <= soc_litedramcore_ext_dfi_p1_cas_n;
- end else begin
- soc_litedramcore_master_p1_cas_n <= soc_litedramcore_slave_p1_cas_n;
- end
- end else begin
- soc_litedramcore_master_p1_cas_n <= soc_litedramcore_csr_dfi_p1_cas_n;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p1_cs_n <= 1'd1;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p1_cs_n <= soc_litedramcore_ext_dfi_p1_cs_n;
- end else begin
- soc_litedramcore_master_p1_cs_n <= soc_litedramcore_slave_p1_cs_n;
- end
- end else begin
- soc_litedramcore_master_p1_cs_n <= soc_litedramcore_csr_dfi_p1_cs_n;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p1_ras_n <= 1'd1;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p1_ras_n <= soc_litedramcore_ext_dfi_p1_ras_n;
- end else begin
- soc_litedramcore_master_p1_ras_n <= soc_litedramcore_slave_p1_ras_n;
- end
- end else begin
- soc_litedramcore_master_p1_ras_n <= soc_litedramcore_csr_dfi_p1_ras_n;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p1_we_n <= 1'd1;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p1_we_n <= soc_litedramcore_ext_dfi_p1_we_n;
- end else begin
- soc_litedramcore_master_p1_we_n <= soc_litedramcore_slave_p1_we_n;
- end
- end else begin
- soc_litedramcore_master_p1_we_n <= soc_litedramcore_csr_dfi_p1_we_n;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p1_cke <= 1'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p1_cke <= soc_litedramcore_ext_dfi_p1_cke;
- end else begin
- soc_litedramcore_master_p1_cke <= soc_litedramcore_slave_p1_cke;
- end
- end else begin
- soc_litedramcore_master_p1_cke <= soc_litedramcore_csr_dfi_p1_cke;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p1_odt <= 1'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p1_odt <= soc_litedramcore_ext_dfi_p1_odt;
- end else begin
- soc_litedramcore_master_p1_odt <= soc_litedramcore_slave_p1_odt;
- end
- end else begin
- soc_litedramcore_master_p1_odt <= soc_litedramcore_csr_dfi_p1_odt;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p1_reset_n <= 1'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p1_reset_n <= soc_litedramcore_ext_dfi_p1_reset_n;
- end else begin
- soc_litedramcore_master_p1_reset_n <= soc_litedramcore_slave_p1_reset_n;
- end
- end else begin
- soc_litedramcore_master_p1_reset_n <= soc_litedramcore_csr_dfi_p1_reset_n;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p1_act_n <= 1'd1;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p1_act_n <= soc_litedramcore_ext_dfi_p1_act_n;
- end else begin
- soc_litedramcore_master_p1_act_n <= soc_litedramcore_slave_p1_act_n;
- end
- end else begin
- soc_litedramcore_master_p1_act_n <= soc_litedramcore_csr_dfi_p1_act_n;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p1_wrdata <= 32'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p1_wrdata <= soc_litedramcore_ext_dfi_p1_wrdata;
- end else begin
- soc_litedramcore_master_p1_wrdata <= soc_litedramcore_slave_p1_wrdata;
- end
- end else begin
- soc_litedramcore_master_p1_wrdata <= soc_litedramcore_csr_dfi_p1_wrdata;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p1_wrdata_en <= 1'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_ext_dfi_p1_wrdata_en;
- end else begin
- soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_slave_p1_wrdata_en;
- end
- end else begin
- soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_csr_dfi_p1_wrdata_en;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p1_wrdata_mask <= 4'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_ext_dfi_p1_wrdata_mask;
- end else begin
- soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_slave_p1_wrdata_mask;
- end
- end else begin
- soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_csr_dfi_p1_wrdata_mask;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p1_rddata_en <= 1'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_ext_dfi_p1_rddata_en;
- end else begin
- soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_slave_p1_rddata_en;
- end
- end else begin
- soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_csr_dfi_p1_rddata_en;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p2_address <= 14'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p2_address <= soc_litedramcore_ext_dfi_p2_address;
- end else begin
- soc_litedramcore_master_p2_address <= soc_litedramcore_slave_p2_address;
- end
- end else begin
- soc_litedramcore_master_p2_address <= soc_litedramcore_csr_dfi_p2_address;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p2_bank <= 3'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p2_bank <= soc_litedramcore_ext_dfi_p2_bank;
- end else begin
- soc_litedramcore_master_p2_bank <= soc_litedramcore_slave_p2_bank;
- end
- end else begin
- soc_litedramcore_master_p2_bank <= soc_litedramcore_csr_dfi_p2_bank;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p2_cas_n <= 1'd1;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p2_cas_n <= soc_litedramcore_ext_dfi_p2_cas_n;
- end else begin
- soc_litedramcore_master_p2_cas_n <= soc_litedramcore_slave_p2_cas_n;
- end
- end else begin
- soc_litedramcore_master_p2_cas_n <= soc_litedramcore_csr_dfi_p2_cas_n;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p2_cs_n <= 1'd1;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p2_cs_n <= soc_litedramcore_ext_dfi_p2_cs_n;
- end else begin
- soc_litedramcore_master_p2_cs_n <= soc_litedramcore_slave_p2_cs_n;
- end
- end else begin
- soc_litedramcore_master_p2_cs_n <= soc_litedramcore_csr_dfi_p2_cs_n;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p2_ras_n <= 1'd1;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p2_ras_n <= soc_litedramcore_ext_dfi_p2_ras_n;
- end else begin
- soc_litedramcore_master_p2_ras_n <= soc_litedramcore_slave_p2_ras_n;
- end
- end else begin
- soc_litedramcore_master_p2_ras_n <= soc_litedramcore_csr_dfi_p2_ras_n;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p2_we_n <= 1'd1;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p2_we_n <= soc_litedramcore_ext_dfi_p2_we_n;
- end else begin
- soc_litedramcore_master_p2_we_n <= soc_litedramcore_slave_p2_we_n;
- end
- end else begin
- soc_litedramcore_master_p2_we_n <= soc_litedramcore_csr_dfi_p2_we_n;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p2_cke <= 1'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p2_cke <= soc_litedramcore_ext_dfi_p2_cke;
- end else begin
- soc_litedramcore_master_p2_cke <= soc_litedramcore_slave_p2_cke;
- end
- end else begin
- soc_litedramcore_master_p2_cke <= soc_litedramcore_csr_dfi_p2_cke;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p2_odt <= 1'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p2_odt <= soc_litedramcore_ext_dfi_p2_odt;
- end else begin
- soc_litedramcore_master_p2_odt <= soc_litedramcore_slave_p2_odt;
- end
- end else begin
- soc_litedramcore_master_p2_odt <= soc_litedramcore_csr_dfi_p2_odt;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p2_reset_n <= 1'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p2_reset_n <= soc_litedramcore_ext_dfi_p2_reset_n;
- end else begin
- soc_litedramcore_master_p2_reset_n <= soc_litedramcore_slave_p2_reset_n;
- end
- end else begin
- soc_litedramcore_master_p2_reset_n <= soc_litedramcore_csr_dfi_p2_reset_n;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p2_act_n <= 1'd1;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p2_act_n <= soc_litedramcore_ext_dfi_p2_act_n;
- end else begin
- soc_litedramcore_master_p2_act_n <= soc_litedramcore_slave_p2_act_n;
- end
- end else begin
- soc_litedramcore_master_p2_act_n <= soc_litedramcore_csr_dfi_p2_act_n;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p2_wrdata <= 32'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p2_wrdata <= soc_litedramcore_ext_dfi_p2_wrdata;
- end else begin
- soc_litedramcore_master_p2_wrdata <= soc_litedramcore_slave_p2_wrdata;
- end
- end else begin
- soc_litedramcore_master_p2_wrdata <= soc_litedramcore_csr_dfi_p2_wrdata;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p2_wrdata_en <= 1'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_ext_dfi_p2_wrdata_en;
- end else begin
- soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_slave_p2_wrdata_en;
- end
- end else begin
- soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_csr_dfi_p2_wrdata_en;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p2_wrdata_mask <= 4'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_ext_dfi_p2_wrdata_mask;
- end else begin
- soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_slave_p2_wrdata_mask;
- end
- end else begin
- soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_csr_dfi_p2_wrdata_mask;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p2_rddata_en <= 1'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_ext_dfi_p2_rddata_en;
- end else begin
- soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_slave_p2_rddata_en;
- end
- end else begin
- soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_csr_dfi_p2_rddata_en;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p3_address <= 14'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p3_address <= soc_litedramcore_ext_dfi_p3_address;
- end else begin
- soc_litedramcore_master_p3_address <= soc_litedramcore_slave_p3_address;
- end
- end else begin
- soc_litedramcore_master_p3_address <= soc_litedramcore_csr_dfi_p3_address;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p3_bank <= 3'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p3_bank <= soc_litedramcore_ext_dfi_p3_bank;
- end else begin
- soc_litedramcore_master_p3_bank <= soc_litedramcore_slave_p3_bank;
- end
- end else begin
- soc_litedramcore_master_p3_bank <= soc_litedramcore_csr_dfi_p3_bank;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p3_cas_n <= 1'd1;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p3_cas_n <= soc_litedramcore_ext_dfi_p3_cas_n;
- end else begin
- soc_litedramcore_master_p3_cas_n <= soc_litedramcore_slave_p3_cas_n;
- end
- end else begin
- soc_litedramcore_master_p3_cas_n <= soc_litedramcore_csr_dfi_p3_cas_n;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p3_cs_n <= 1'd1;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p3_cs_n <= soc_litedramcore_ext_dfi_p3_cs_n;
- end else begin
- soc_litedramcore_master_p3_cs_n <= soc_litedramcore_slave_p3_cs_n;
- end
- end else begin
- soc_litedramcore_master_p3_cs_n <= soc_litedramcore_csr_dfi_p3_cs_n;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p3_ras_n <= 1'd1;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p3_ras_n <= soc_litedramcore_ext_dfi_p3_ras_n;
- end else begin
- soc_litedramcore_master_p3_ras_n <= soc_litedramcore_slave_p3_ras_n;
- end
- end else begin
- soc_litedramcore_master_p3_ras_n <= soc_litedramcore_csr_dfi_p3_ras_n;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p3_we_n <= 1'd1;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p3_we_n <= soc_litedramcore_ext_dfi_p3_we_n;
- end else begin
- soc_litedramcore_master_p3_we_n <= soc_litedramcore_slave_p3_we_n;
- end
- end else begin
- soc_litedramcore_master_p3_we_n <= soc_litedramcore_csr_dfi_p3_we_n;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p3_cke <= 1'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p3_cke <= soc_litedramcore_ext_dfi_p3_cke;
- end else begin
- soc_litedramcore_master_p3_cke <= soc_litedramcore_slave_p3_cke;
- end
- end else begin
- soc_litedramcore_master_p3_cke <= soc_litedramcore_csr_dfi_p3_cke;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p3_odt <= 1'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p3_odt <= soc_litedramcore_ext_dfi_p3_odt;
- end else begin
- soc_litedramcore_master_p3_odt <= soc_litedramcore_slave_p3_odt;
- end
- end else begin
- soc_litedramcore_master_p3_odt <= soc_litedramcore_csr_dfi_p3_odt;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p3_reset_n <= 1'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p3_reset_n <= soc_litedramcore_ext_dfi_p3_reset_n;
- end else begin
- soc_litedramcore_master_p3_reset_n <= soc_litedramcore_slave_p3_reset_n;
- end
- end else begin
- soc_litedramcore_master_p3_reset_n <= soc_litedramcore_csr_dfi_p3_reset_n;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p3_act_n <= 1'd1;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p3_act_n <= soc_litedramcore_ext_dfi_p3_act_n;
- end else begin
- soc_litedramcore_master_p3_act_n <= soc_litedramcore_slave_p3_act_n;
- end
- end else begin
- soc_litedramcore_master_p3_act_n <= soc_litedramcore_csr_dfi_p3_act_n;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p3_wrdata <= 32'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p3_wrdata <= soc_litedramcore_ext_dfi_p3_wrdata;
- end else begin
- soc_litedramcore_master_p3_wrdata <= soc_litedramcore_slave_p3_wrdata;
- end
- end else begin
- soc_litedramcore_master_p3_wrdata <= soc_litedramcore_csr_dfi_p3_wrdata;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p3_wrdata_en <= 1'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_ext_dfi_p3_wrdata_en;
- end else begin
- soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_slave_p3_wrdata_en;
- end
- end else begin
- soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_csr_dfi_p3_wrdata_en;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p3_wrdata_mask <= 4'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_ext_dfi_p3_wrdata_mask;
- end else begin
- soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_slave_p3_wrdata_mask;
- end
- end else begin
- soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_csr_dfi_p3_wrdata_mask;
- end
-end
-always @(*) begin
- soc_litedramcore_master_p3_rddata_en <= 1'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_ext_dfi_p3_rddata_en;
- end else begin
- soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_slave_p3_rddata_en;
- end
- end else begin
- soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_csr_dfi_p3_rddata_en;
- end
-end
-always @(*) begin
- soc_litedramcore_csr_dfi_p0_rddata <= 32'd0;
- if (soc_litedramcore_sel) begin
- end else begin
- soc_litedramcore_csr_dfi_p0_rddata <= soc_litedramcore_master_p0_rddata;
- end
-end
-always @(*) begin
- soc_litedramcore_csr_dfi_p0_rddata_valid <= 1'd0;
- if (soc_litedramcore_sel) begin
- end else begin
- soc_litedramcore_csr_dfi_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid;
- end
-end
-always @(*) begin
- soc_litedramcore_csr_dfi_p1_rddata <= 32'd0;
- if (soc_litedramcore_sel) begin
- end else begin
- soc_litedramcore_csr_dfi_p1_rddata <= soc_litedramcore_master_p1_rddata;
- end
-end
-always @(*) begin
- soc_litedramcore_csr_dfi_p1_rddata_valid <= 1'd0;
- if (soc_litedramcore_sel) begin
- end else begin
- soc_litedramcore_csr_dfi_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid;
- end
-end
-always @(*) begin
- soc_litedramcore_csr_dfi_p2_rddata <= 32'd0;
- if (soc_litedramcore_sel) begin
- end else begin
- soc_litedramcore_csr_dfi_p2_rddata <= soc_litedramcore_master_p2_rddata;
- end
-end
-always @(*) begin
- soc_litedramcore_csr_dfi_p2_rddata_valid <= 1'd0;
- if (soc_litedramcore_sel) begin
- end else begin
- soc_litedramcore_csr_dfi_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid;
- end
-end
-always @(*) begin
- soc_litedramcore_csr_dfi_p3_rddata <= 32'd0;
- if (soc_litedramcore_sel) begin
- end else begin
- soc_litedramcore_csr_dfi_p3_rddata <= soc_litedramcore_master_p3_rddata;
- end
-end
-always @(*) begin
- soc_litedramcore_csr_dfi_p3_rddata_valid <= 1'd0;
- if (soc_litedramcore_sel) begin
- end else begin
- soc_litedramcore_csr_dfi_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid;
- end
-end
-always @(*) begin
- soc_litedramcore_ext_dfi_p0_rddata <= 32'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_ext_dfi_p0_rddata <= soc_litedramcore_master_p0_rddata;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- soc_litedramcore_ext_dfi_p0_rddata_valid <= 1'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_ext_dfi_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- soc_litedramcore_ext_dfi_p1_rddata <= 32'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_ext_dfi_p1_rddata <= soc_litedramcore_master_p1_rddata;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- soc_litedramcore_ext_dfi_p1_rddata_valid <= 1'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_ext_dfi_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- soc_litedramcore_ext_dfi_p2_rddata <= 32'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_ext_dfi_p2_rddata <= soc_litedramcore_master_p2_rddata;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- soc_litedramcore_ext_dfi_p2_rddata_valid <= 1'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- soc_litedramcore_ext_dfi_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- soc_litedramcore_slave_p0_rddata <= 32'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- end else begin
- soc_litedramcore_slave_p0_rddata <= soc_litedramcore_master_p0_rddata;
- end
- end else begin
- end
-end
-always @(*) begin
- soc_litedramcore_slave_p0_rddata_valid <= 1'd0;
- if (soc_litedramcore_sel) begin
- if (soc_litedramcore_ext_dfi_sel) begin
- end else begin
- soc_litedramcore_slave_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid;
- end
- end else begin
- end
+ soc_litedramcore_ext_dfi_p3_rddata <= 32'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_ext_dfi_p3_rddata <= soc_litedramcore_master_p3_rddata;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ soc_litedramcore_ext_dfi_p3_rddata_valid <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_ext_dfi_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ soc_litedramcore_slave_p1_rddata <= 32'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ end else begin
+ soc_litedramcore_slave_p1_rddata <= soc_litedramcore_master_p1_rddata;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ soc_litedramcore_slave_p1_rddata_valid <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ end else begin
+ soc_litedramcore_slave_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ soc_litedramcore_slave_p2_rddata <= 32'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ end else begin
+ soc_litedramcore_slave_p2_rddata <= soc_litedramcore_master_p2_rddata;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ soc_litedramcore_slave_p2_rddata_valid <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ end else begin
+ soc_litedramcore_slave_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ soc_litedramcore_slave_p3_rddata <= 32'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ end else begin
+ soc_litedramcore_slave_p3_rddata <= soc_litedramcore_master_p3_rddata;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ soc_litedramcore_slave_p3_rddata_valid <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ end else begin
+ soc_litedramcore_slave_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p0_address <= 14'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p0_address <= soc_litedramcore_ext_dfi_p0_address;
+ end else begin
+ soc_litedramcore_master_p0_address <= soc_litedramcore_slave_p0_address;
+ end
+ end else begin
+ soc_litedramcore_master_p0_address <= soc_litedramcore_csr_dfi_p0_address;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p0_bank <= 3'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p0_bank <= soc_litedramcore_ext_dfi_p0_bank;
+ end else begin
+ soc_litedramcore_master_p0_bank <= soc_litedramcore_slave_p0_bank;
+ end
+ end else begin
+ soc_litedramcore_master_p0_bank <= soc_litedramcore_csr_dfi_p0_bank;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p0_cas_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p0_cas_n <= soc_litedramcore_ext_dfi_p0_cas_n;
+ end else begin
+ soc_litedramcore_master_p0_cas_n <= soc_litedramcore_slave_p0_cas_n;
+ end
+ end else begin
+ soc_litedramcore_master_p0_cas_n <= soc_litedramcore_csr_dfi_p0_cas_n;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p0_cs_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p0_cs_n <= soc_litedramcore_ext_dfi_p0_cs_n;
+ end else begin
+ soc_litedramcore_master_p0_cs_n <= soc_litedramcore_slave_p0_cs_n;
+ end
+ end else begin
+ soc_litedramcore_master_p0_cs_n <= soc_litedramcore_csr_dfi_p0_cs_n;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p0_ras_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p0_ras_n <= soc_litedramcore_ext_dfi_p0_ras_n;
+ end else begin
+ soc_litedramcore_master_p0_ras_n <= soc_litedramcore_slave_p0_ras_n;
+ end
+ end else begin
+ soc_litedramcore_master_p0_ras_n <= soc_litedramcore_csr_dfi_p0_ras_n;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p0_we_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p0_we_n <= soc_litedramcore_ext_dfi_p0_we_n;
+ end else begin
+ soc_litedramcore_master_p0_we_n <= soc_litedramcore_slave_p0_we_n;
+ end
+ end else begin
+ soc_litedramcore_master_p0_we_n <= soc_litedramcore_csr_dfi_p0_we_n;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p0_cke <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p0_cke <= soc_litedramcore_ext_dfi_p0_cke;
+ end else begin
+ soc_litedramcore_master_p0_cke <= soc_litedramcore_slave_p0_cke;
+ end
+ end else begin
+ soc_litedramcore_master_p0_cke <= soc_litedramcore_csr_dfi_p0_cke;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p0_odt <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p0_odt <= soc_litedramcore_ext_dfi_p0_odt;
+ end else begin
+ soc_litedramcore_master_p0_odt <= soc_litedramcore_slave_p0_odt;
+ end
+ end else begin
+ soc_litedramcore_master_p0_odt <= soc_litedramcore_csr_dfi_p0_odt;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p0_reset_n <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p0_reset_n <= soc_litedramcore_ext_dfi_p0_reset_n;
+ end else begin
+ soc_litedramcore_master_p0_reset_n <= soc_litedramcore_slave_p0_reset_n;
+ end
+ end else begin
+ soc_litedramcore_master_p0_reset_n <= soc_litedramcore_csr_dfi_p0_reset_n;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p0_act_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p0_act_n <= soc_litedramcore_ext_dfi_p0_act_n;
+ end else begin
+ soc_litedramcore_master_p0_act_n <= soc_litedramcore_slave_p0_act_n;
+ end
+ end else begin
+ soc_litedramcore_master_p0_act_n <= soc_litedramcore_csr_dfi_p0_act_n;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p0_wrdata <= 32'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p0_wrdata <= soc_litedramcore_ext_dfi_p0_wrdata;
+ end else begin
+ soc_litedramcore_master_p0_wrdata <= soc_litedramcore_slave_p0_wrdata;
+ end
+ end else begin
+ soc_litedramcore_master_p0_wrdata <= soc_litedramcore_csr_dfi_p0_wrdata;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p0_wrdata_en <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_ext_dfi_p0_wrdata_en;
+ end else begin
+ soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_slave_p0_wrdata_en;
+ end
+ end else begin
+ soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_csr_dfi_p0_wrdata_en;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p0_wrdata_mask <= 4'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_ext_dfi_p0_wrdata_mask;
+ end else begin
+ soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_slave_p0_wrdata_mask;
+ end
+ end else begin
+ soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_csr_dfi_p0_wrdata_mask;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p0_rddata_en <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_ext_dfi_p0_rddata_en;
+ end else begin
+ soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_slave_p0_rddata_en;
+ end
+ end else begin
+ soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_csr_dfi_p0_rddata_en;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p1_address <= 14'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p1_address <= soc_litedramcore_ext_dfi_p1_address;
+ end else begin
+ soc_litedramcore_master_p1_address <= soc_litedramcore_slave_p1_address;
+ end
+ end else begin
+ soc_litedramcore_master_p1_address <= soc_litedramcore_csr_dfi_p1_address;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p1_bank <= 3'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p1_bank <= soc_litedramcore_ext_dfi_p1_bank;
+ end else begin
+ soc_litedramcore_master_p1_bank <= soc_litedramcore_slave_p1_bank;
+ end
+ end else begin
+ soc_litedramcore_master_p1_bank <= soc_litedramcore_csr_dfi_p1_bank;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p1_cas_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p1_cas_n <= soc_litedramcore_ext_dfi_p1_cas_n;
+ end else begin
+ soc_litedramcore_master_p1_cas_n <= soc_litedramcore_slave_p1_cas_n;
+ end
+ end else begin
+ soc_litedramcore_master_p1_cas_n <= soc_litedramcore_csr_dfi_p1_cas_n;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p1_cs_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p1_cs_n <= soc_litedramcore_ext_dfi_p1_cs_n;
+ end else begin
+ soc_litedramcore_master_p1_cs_n <= soc_litedramcore_slave_p1_cs_n;
+ end
+ end else begin
+ soc_litedramcore_master_p1_cs_n <= soc_litedramcore_csr_dfi_p1_cs_n;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p1_ras_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p1_ras_n <= soc_litedramcore_ext_dfi_p1_ras_n;
+ end else begin
+ soc_litedramcore_master_p1_ras_n <= soc_litedramcore_slave_p1_ras_n;
+ end
+ end else begin
+ soc_litedramcore_master_p1_ras_n <= soc_litedramcore_csr_dfi_p1_ras_n;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p1_we_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p1_we_n <= soc_litedramcore_ext_dfi_p1_we_n;
+ end else begin
+ soc_litedramcore_master_p1_we_n <= soc_litedramcore_slave_p1_we_n;
+ end
+ end else begin
+ soc_litedramcore_master_p1_we_n <= soc_litedramcore_csr_dfi_p1_we_n;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p1_cke <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p1_cke <= soc_litedramcore_ext_dfi_p1_cke;
+ end else begin
+ soc_litedramcore_master_p1_cke <= soc_litedramcore_slave_p1_cke;
+ end
+ end else begin
+ soc_litedramcore_master_p1_cke <= soc_litedramcore_csr_dfi_p1_cke;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p1_odt <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p1_odt <= soc_litedramcore_ext_dfi_p1_odt;
+ end else begin
+ soc_litedramcore_master_p1_odt <= soc_litedramcore_slave_p1_odt;
+ end
+ end else begin
+ soc_litedramcore_master_p1_odt <= soc_litedramcore_csr_dfi_p1_odt;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p1_reset_n <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p1_reset_n <= soc_litedramcore_ext_dfi_p1_reset_n;
+ end else begin
+ soc_litedramcore_master_p1_reset_n <= soc_litedramcore_slave_p1_reset_n;
+ end
+ end else begin
+ soc_litedramcore_master_p1_reset_n <= soc_litedramcore_csr_dfi_p1_reset_n;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p1_act_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p1_act_n <= soc_litedramcore_ext_dfi_p1_act_n;
+ end else begin
+ soc_litedramcore_master_p1_act_n <= soc_litedramcore_slave_p1_act_n;
+ end
+ end else begin
+ soc_litedramcore_master_p1_act_n <= soc_litedramcore_csr_dfi_p1_act_n;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p1_wrdata <= 32'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p1_wrdata <= soc_litedramcore_ext_dfi_p1_wrdata;
+ end else begin
+ soc_litedramcore_master_p1_wrdata <= soc_litedramcore_slave_p1_wrdata;
+ end
+ end else begin
+ soc_litedramcore_master_p1_wrdata <= soc_litedramcore_csr_dfi_p1_wrdata;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p1_wrdata_en <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_ext_dfi_p1_wrdata_en;
+ end else begin
+ soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_slave_p1_wrdata_en;
+ end
+ end else begin
+ soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_csr_dfi_p1_wrdata_en;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p1_wrdata_mask <= 4'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_ext_dfi_p1_wrdata_mask;
+ end else begin
+ soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_slave_p1_wrdata_mask;
+ end
+ end else begin
+ soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_csr_dfi_p1_wrdata_mask;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p1_rddata_en <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_ext_dfi_p1_rddata_en;
+ end else begin
+ soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_slave_p1_rddata_en;
+ end
+ end else begin
+ soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_csr_dfi_p1_rddata_en;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p2_address <= 14'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p2_address <= soc_litedramcore_ext_dfi_p2_address;
+ end else begin
+ soc_litedramcore_master_p2_address <= soc_litedramcore_slave_p2_address;
+ end
+ end else begin
+ soc_litedramcore_master_p2_address <= soc_litedramcore_csr_dfi_p2_address;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p2_bank <= 3'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p2_bank <= soc_litedramcore_ext_dfi_p2_bank;
+ end else begin
+ soc_litedramcore_master_p2_bank <= soc_litedramcore_slave_p2_bank;
+ end
+ end else begin
+ soc_litedramcore_master_p2_bank <= soc_litedramcore_csr_dfi_p2_bank;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p2_cas_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p2_cas_n <= soc_litedramcore_ext_dfi_p2_cas_n;
+ end else begin
+ soc_litedramcore_master_p2_cas_n <= soc_litedramcore_slave_p2_cas_n;
+ end
+ end else begin
+ soc_litedramcore_master_p2_cas_n <= soc_litedramcore_csr_dfi_p2_cas_n;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p2_cs_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p2_cs_n <= soc_litedramcore_ext_dfi_p2_cs_n;
+ end else begin
+ soc_litedramcore_master_p2_cs_n <= soc_litedramcore_slave_p2_cs_n;
+ end
+ end else begin
+ soc_litedramcore_master_p2_cs_n <= soc_litedramcore_csr_dfi_p2_cs_n;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p2_ras_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p2_ras_n <= soc_litedramcore_ext_dfi_p2_ras_n;
+ end else begin
+ soc_litedramcore_master_p2_ras_n <= soc_litedramcore_slave_p2_ras_n;
+ end
+ end else begin
+ soc_litedramcore_master_p2_ras_n <= soc_litedramcore_csr_dfi_p2_ras_n;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p2_we_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p2_we_n <= soc_litedramcore_ext_dfi_p2_we_n;
+ end else begin
+ soc_litedramcore_master_p2_we_n <= soc_litedramcore_slave_p2_we_n;
+ end
+ end else begin
+ soc_litedramcore_master_p2_we_n <= soc_litedramcore_csr_dfi_p2_we_n;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p2_cke <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p2_cke <= soc_litedramcore_ext_dfi_p2_cke;
+ end else begin
+ soc_litedramcore_master_p2_cke <= soc_litedramcore_slave_p2_cke;
+ end
+ end else begin
+ soc_litedramcore_master_p2_cke <= soc_litedramcore_csr_dfi_p2_cke;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p2_odt <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p2_odt <= soc_litedramcore_ext_dfi_p2_odt;
+ end else begin
+ soc_litedramcore_master_p2_odt <= soc_litedramcore_slave_p2_odt;
+ end
+ end else begin
+ soc_litedramcore_master_p2_odt <= soc_litedramcore_csr_dfi_p2_odt;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p2_reset_n <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p2_reset_n <= soc_litedramcore_ext_dfi_p2_reset_n;
+ end else begin
+ soc_litedramcore_master_p2_reset_n <= soc_litedramcore_slave_p2_reset_n;
+ end
+ end else begin
+ soc_litedramcore_master_p2_reset_n <= soc_litedramcore_csr_dfi_p2_reset_n;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p2_act_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p2_act_n <= soc_litedramcore_ext_dfi_p2_act_n;
+ end else begin
+ soc_litedramcore_master_p2_act_n <= soc_litedramcore_slave_p2_act_n;
+ end
+ end else begin
+ soc_litedramcore_master_p2_act_n <= soc_litedramcore_csr_dfi_p2_act_n;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p2_wrdata <= 32'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p2_wrdata <= soc_litedramcore_ext_dfi_p2_wrdata;
+ end else begin
+ soc_litedramcore_master_p2_wrdata <= soc_litedramcore_slave_p2_wrdata;
+ end
+ end else begin
+ soc_litedramcore_master_p2_wrdata <= soc_litedramcore_csr_dfi_p2_wrdata;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p2_wrdata_en <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_ext_dfi_p2_wrdata_en;
+ end else begin
+ soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_slave_p2_wrdata_en;
+ end
+ end else begin
+ soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_csr_dfi_p2_wrdata_en;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p2_wrdata_mask <= 4'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_ext_dfi_p2_wrdata_mask;
+ end else begin
+ soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_slave_p2_wrdata_mask;
+ end
+ end else begin
+ soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_csr_dfi_p2_wrdata_mask;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p2_rddata_en <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_ext_dfi_p2_rddata_en;
+ end else begin
+ soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_slave_p2_rddata_en;
+ end
+ end else begin
+ soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_csr_dfi_p2_rddata_en;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p3_address <= 14'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p3_address <= soc_litedramcore_ext_dfi_p3_address;
+ end else begin
+ soc_litedramcore_master_p3_address <= soc_litedramcore_slave_p3_address;
+ end
+ end else begin
+ soc_litedramcore_master_p3_address <= soc_litedramcore_csr_dfi_p3_address;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p3_bank <= 3'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p3_bank <= soc_litedramcore_ext_dfi_p3_bank;
+ end else begin
+ soc_litedramcore_master_p3_bank <= soc_litedramcore_slave_p3_bank;
+ end
+ end else begin
+ soc_litedramcore_master_p3_bank <= soc_litedramcore_csr_dfi_p3_bank;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p3_cas_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p3_cas_n <= soc_litedramcore_ext_dfi_p3_cas_n;
+ end else begin
+ soc_litedramcore_master_p3_cas_n <= soc_litedramcore_slave_p3_cas_n;
+ end
+ end else begin
+ soc_litedramcore_master_p3_cas_n <= soc_litedramcore_csr_dfi_p3_cas_n;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p3_cs_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p3_cs_n <= soc_litedramcore_ext_dfi_p3_cs_n;
+ end else begin
+ soc_litedramcore_master_p3_cs_n <= soc_litedramcore_slave_p3_cs_n;
+ end
+ end else begin
+ soc_litedramcore_master_p3_cs_n <= soc_litedramcore_csr_dfi_p3_cs_n;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p3_ras_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p3_ras_n <= soc_litedramcore_ext_dfi_p3_ras_n;
+ end else begin
+ soc_litedramcore_master_p3_ras_n <= soc_litedramcore_slave_p3_ras_n;
+ end
+ end else begin
+ soc_litedramcore_master_p3_ras_n <= soc_litedramcore_csr_dfi_p3_ras_n;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p3_we_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p3_we_n <= soc_litedramcore_ext_dfi_p3_we_n;
+ end else begin
+ soc_litedramcore_master_p3_we_n <= soc_litedramcore_slave_p3_we_n;
+ end
+ end else begin
+ soc_litedramcore_master_p3_we_n <= soc_litedramcore_csr_dfi_p3_we_n;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p3_cke <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p3_cke <= soc_litedramcore_ext_dfi_p3_cke;
+ end else begin
+ soc_litedramcore_master_p3_cke <= soc_litedramcore_slave_p3_cke;
+ end
+ end else begin
+ soc_litedramcore_master_p3_cke <= soc_litedramcore_csr_dfi_p3_cke;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p3_odt <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p3_odt <= soc_litedramcore_ext_dfi_p3_odt;
+ end else begin
+ soc_litedramcore_master_p3_odt <= soc_litedramcore_slave_p3_odt;
+ end
+ end else begin
+ soc_litedramcore_master_p3_odt <= soc_litedramcore_csr_dfi_p3_odt;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p3_reset_n <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p3_reset_n <= soc_litedramcore_ext_dfi_p3_reset_n;
+ end else begin
+ soc_litedramcore_master_p3_reset_n <= soc_litedramcore_slave_p3_reset_n;
+ end
+ end else begin
+ soc_litedramcore_master_p3_reset_n <= soc_litedramcore_csr_dfi_p3_reset_n;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p3_act_n <= 1'd1;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p3_act_n <= soc_litedramcore_ext_dfi_p3_act_n;
+ end else begin
+ soc_litedramcore_master_p3_act_n <= soc_litedramcore_slave_p3_act_n;
+ end
+ end else begin
+ soc_litedramcore_master_p3_act_n <= soc_litedramcore_csr_dfi_p3_act_n;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p3_wrdata <= 32'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p3_wrdata <= soc_litedramcore_ext_dfi_p3_wrdata;
+ end else begin
+ soc_litedramcore_master_p3_wrdata <= soc_litedramcore_slave_p3_wrdata;
+ end
+ end else begin
+ soc_litedramcore_master_p3_wrdata <= soc_litedramcore_csr_dfi_p3_wrdata;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p3_wrdata_en <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_ext_dfi_p3_wrdata_en;
+ end else begin
+ soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_slave_p3_wrdata_en;
+ end
+ end else begin
+ soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_csr_dfi_p3_wrdata_en;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p3_wrdata_mask <= 4'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_ext_dfi_p3_wrdata_mask;
+ end else begin
+ soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_slave_p3_wrdata_mask;
+ end
+ end else begin
+ soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_csr_dfi_p3_wrdata_mask;
+ end
+end
+always @(*) begin
+ soc_litedramcore_master_p3_rddata_en <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_ext_dfi_p3_rddata_en;
+ end else begin
+ soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_slave_p3_rddata_en;
+ end
+ end else begin
+ soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_csr_dfi_p3_rddata_en;
+ end
+end
+always @(*) begin
+ soc_litedramcore_csr_dfi_p0_rddata <= 32'd0;
+ if (soc_litedramcore_sel) begin
+ end else begin
+ soc_litedramcore_csr_dfi_p0_rddata <= soc_litedramcore_master_p0_rddata;
+ end
+end
+always @(*) begin
+ soc_litedramcore_csr_dfi_p0_rddata_valid <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ end else begin
+ soc_litedramcore_csr_dfi_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid;
+ end
+end
+always @(*) begin
+ soc_litedramcore_csr_dfi_p1_rddata <= 32'd0;
+ if (soc_litedramcore_sel) begin
+ end else begin
+ soc_litedramcore_csr_dfi_p1_rddata <= soc_litedramcore_master_p1_rddata;
+ end
+end
+always @(*) begin
+ soc_litedramcore_csr_dfi_p1_rddata_valid <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ end else begin
+ soc_litedramcore_csr_dfi_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid;
+ end
+end
+always @(*) begin
+ soc_litedramcore_csr_dfi_p2_rddata <= 32'd0;
+ if (soc_litedramcore_sel) begin
+ end else begin
+ soc_litedramcore_csr_dfi_p2_rddata <= soc_litedramcore_master_p2_rddata;
+ end
+end
+always @(*) begin
+ soc_litedramcore_csr_dfi_p2_rddata_valid <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ end else begin
+ soc_litedramcore_csr_dfi_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid;
+ end
+end
+always @(*) begin
+ soc_litedramcore_csr_dfi_p3_rddata <= 32'd0;
+ if (soc_litedramcore_sel) begin
+ end else begin
+ soc_litedramcore_csr_dfi_p3_rddata <= soc_litedramcore_master_p3_rddata;
+ end
+end
+always @(*) begin
+ soc_litedramcore_csr_dfi_p3_rddata_valid <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ end else begin
+ soc_litedramcore_csr_dfi_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid;
+ end
+end
+always @(*) begin
+ soc_litedramcore_ext_dfi_p0_rddata <= 32'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_ext_dfi_p0_rddata <= soc_litedramcore_master_p0_rddata;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ soc_litedramcore_ext_dfi_p0_rddata_valid <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_ext_dfi_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ soc_litedramcore_ext_dfi_p1_rddata <= 32'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_ext_dfi_p1_rddata <= soc_litedramcore_master_p1_rddata;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ soc_litedramcore_ext_dfi_p1_rddata_valid <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_ext_dfi_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ soc_litedramcore_ext_dfi_p2_rddata <= 32'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_ext_dfi_p2_rddata <= soc_litedramcore_master_p2_rddata;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ soc_litedramcore_ext_dfi_p2_rddata_valid <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ soc_litedramcore_ext_dfi_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ soc_litedramcore_slave_p0_rddata <= 32'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ end else begin
+ soc_litedramcore_slave_p0_rddata <= soc_litedramcore_master_p0_rddata;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ soc_litedramcore_slave_p0_rddata_valid <= 1'd0;
+ if (soc_litedramcore_sel) begin
+ if (soc_litedramcore_ext_dfi_sel) begin
+ end else begin
+ soc_litedramcore_slave_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid;
+ end
+ end else begin
+ end
end
assign soc_litedramcore_csr_dfi_p0_cke = soc_litedramcore_cke;
assign soc_litedramcore_csr_dfi_p1_cke = soc_litedramcore_cke;
assign soc_litedramcore_csr_dfi_p2_reset_n = soc_litedramcore_reset_n;
assign soc_litedramcore_csr_dfi_p3_reset_n = soc_litedramcore_reset_n;
always @(*) begin
- soc_litedramcore_csr_dfi_p0_cs_n <= 1'd1;
- if (soc_litedramcore_phaseinjector0_command_issue_re) begin
- soc_litedramcore_csr_dfi_p0_cs_n <= {1{(~soc_litedramcore_phaseinjector0_csrfield_cs)}};
- end else begin
- soc_litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}};
- end
+ soc_litedramcore_csr_dfi_p0_cs_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector0_command_issue_re) begin
+ soc_litedramcore_csr_dfi_p0_cs_n <= {1{(~soc_litedramcore_phaseinjector0_csrfield_cs)}};
+ end else begin
+ soc_litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}};
+ end
end
always @(*) begin
- soc_litedramcore_csr_dfi_p0_ras_n <= 1'd1;
- if (soc_litedramcore_phaseinjector0_command_issue_re) begin
- soc_litedramcore_csr_dfi_p0_ras_n <= (~soc_litedramcore_phaseinjector0_csrfield_ras);
- end else begin
- soc_litedramcore_csr_dfi_p0_ras_n <= 1'd1;
- end
+ soc_litedramcore_csr_dfi_p0_ras_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector0_command_issue_re) begin
+ soc_litedramcore_csr_dfi_p0_ras_n <= (~soc_litedramcore_phaseinjector0_csrfield_ras);
+ end else begin
+ soc_litedramcore_csr_dfi_p0_ras_n <= 1'd1;
+ end
end
always @(*) begin
- soc_litedramcore_csr_dfi_p0_we_n <= 1'd1;
- if (soc_litedramcore_phaseinjector0_command_issue_re) begin
- soc_litedramcore_csr_dfi_p0_we_n <= (~soc_litedramcore_phaseinjector0_csrfield_we);
- end else begin
- soc_litedramcore_csr_dfi_p0_we_n <= 1'd1;
- end
+ soc_litedramcore_csr_dfi_p0_we_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector0_command_issue_re) begin
+ soc_litedramcore_csr_dfi_p0_we_n <= (~soc_litedramcore_phaseinjector0_csrfield_we);
+ end else begin
+ soc_litedramcore_csr_dfi_p0_we_n <= 1'd1;
+ end
end
always @(*) begin
- soc_litedramcore_csr_dfi_p0_cas_n <= 1'd1;
- if (soc_litedramcore_phaseinjector0_command_issue_re) begin
- soc_litedramcore_csr_dfi_p0_cas_n <= (~soc_litedramcore_phaseinjector0_csrfield_cas);
- end else begin
- soc_litedramcore_csr_dfi_p0_cas_n <= 1'd1;
- end
+ soc_litedramcore_csr_dfi_p0_cas_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector0_command_issue_re) begin
+ soc_litedramcore_csr_dfi_p0_cas_n <= (~soc_litedramcore_phaseinjector0_csrfield_cas);
+ end else begin
+ soc_litedramcore_csr_dfi_p0_cas_n <= 1'd1;
+ end
end
assign soc_litedramcore_csr_dfi_p0_address = soc_litedramcore_phaseinjector0_address_storage;
assign soc_litedramcore_csr_dfi_p0_bank = soc_litedramcore_phaseinjector0_baddress_storage;
assign soc_litedramcore_csr_dfi_p0_wrdata = soc_litedramcore_phaseinjector0_wrdata_storage;
assign soc_litedramcore_csr_dfi_p0_wrdata_mask = 1'd0;
always @(*) begin
- soc_litedramcore_csr_dfi_p1_cs_n <= 1'd1;
- if (soc_litedramcore_phaseinjector1_command_issue_re) begin
- soc_litedramcore_csr_dfi_p1_cs_n <= {1{(~soc_litedramcore_phaseinjector1_csrfield_cs)}};
- end else begin
- soc_litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}};
- end
+ soc_litedramcore_csr_dfi_p1_cs_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector1_command_issue_re) begin
+ soc_litedramcore_csr_dfi_p1_cs_n <= {1{(~soc_litedramcore_phaseinjector1_csrfield_cs)}};
+ end else begin
+ soc_litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}};
+ end
end
always @(*) begin
- soc_litedramcore_csr_dfi_p1_ras_n <= 1'd1;
- if (soc_litedramcore_phaseinjector1_command_issue_re) begin
- soc_litedramcore_csr_dfi_p1_ras_n <= (~soc_litedramcore_phaseinjector1_csrfield_ras);
- end else begin
- soc_litedramcore_csr_dfi_p1_ras_n <= 1'd1;
- end
+ soc_litedramcore_csr_dfi_p1_ras_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector1_command_issue_re) begin
+ soc_litedramcore_csr_dfi_p1_ras_n <= (~soc_litedramcore_phaseinjector1_csrfield_ras);
+ end else begin
+ soc_litedramcore_csr_dfi_p1_ras_n <= 1'd1;
+ end
end
always @(*) begin
- soc_litedramcore_csr_dfi_p1_we_n <= 1'd1;
- if (soc_litedramcore_phaseinjector1_command_issue_re) begin
- soc_litedramcore_csr_dfi_p1_we_n <= (~soc_litedramcore_phaseinjector1_csrfield_we);
- end else begin
- soc_litedramcore_csr_dfi_p1_we_n <= 1'd1;
- end
+ soc_litedramcore_csr_dfi_p1_we_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector1_command_issue_re) begin
+ soc_litedramcore_csr_dfi_p1_we_n <= (~soc_litedramcore_phaseinjector1_csrfield_we);
+ end else begin
+ soc_litedramcore_csr_dfi_p1_we_n <= 1'd1;
+ end
end
always @(*) begin
- soc_litedramcore_csr_dfi_p1_cas_n <= 1'd1;
- if (soc_litedramcore_phaseinjector1_command_issue_re) begin
- soc_litedramcore_csr_dfi_p1_cas_n <= (~soc_litedramcore_phaseinjector1_csrfield_cas);
- end else begin
- soc_litedramcore_csr_dfi_p1_cas_n <= 1'd1;
- end
+ soc_litedramcore_csr_dfi_p1_cas_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector1_command_issue_re) begin
+ soc_litedramcore_csr_dfi_p1_cas_n <= (~soc_litedramcore_phaseinjector1_csrfield_cas);
+ end else begin
+ soc_litedramcore_csr_dfi_p1_cas_n <= 1'd1;
+ end
end
assign soc_litedramcore_csr_dfi_p1_address = soc_litedramcore_phaseinjector1_address_storage;
assign soc_litedramcore_csr_dfi_p1_bank = soc_litedramcore_phaseinjector1_baddress_storage;
assign soc_litedramcore_csr_dfi_p1_wrdata = soc_litedramcore_phaseinjector1_wrdata_storage;
assign soc_litedramcore_csr_dfi_p1_wrdata_mask = 1'd0;
always @(*) begin
- soc_litedramcore_csr_dfi_p2_cs_n <= 1'd1;
- if (soc_litedramcore_phaseinjector2_command_issue_re) begin
- soc_litedramcore_csr_dfi_p2_cs_n <= {1{(~soc_litedramcore_phaseinjector2_csrfield_cs)}};
- end else begin
- soc_litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}};
- end
+ soc_litedramcore_csr_dfi_p2_cs_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector2_command_issue_re) begin
+ soc_litedramcore_csr_dfi_p2_cs_n <= {1{(~soc_litedramcore_phaseinjector2_csrfield_cs)}};
+ end else begin
+ soc_litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}};
+ end
end
always @(*) begin
- soc_litedramcore_csr_dfi_p2_ras_n <= 1'd1;
- if (soc_litedramcore_phaseinjector2_command_issue_re) begin
- soc_litedramcore_csr_dfi_p2_ras_n <= (~soc_litedramcore_phaseinjector2_csrfield_ras);
- end else begin
- soc_litedramcore_csr_dfi_p2_ras_n <= 1'd1;
- end
+ soc_litedramcore_csr_dfi_p2_ras_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector2_command_issue_re) begin
+ soc_litedramcore_csr_dfi_p2_ras_n <= (~soc_litedramcore_phaseinjector2_csrfield_ras);
+ end else begin
+ soc_litedramcore_csr_dfi_p2_ras_n <= 1'd1;
+ end
end
always @(*) begin
- soc_litedramcore_csr_dfi_p2_we_n <= 1'd1;
- if (soc_litedramcore_phaseinjector2_command_issue_re) begin
- soc_litedramcore_csr_dfi_p2_we_n <= (~soc_litedramcore_phaseinjector2_csrfield_we);
- end else begin
- soc_litedramcore_csr_dfi_p2_we_n <= 1'd1;
- end
+ soc_litedramcore_csr_dfi_p2_we_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector2_command_issue_re) begin
+ soc_litedramcore_csr_dfi_p2_we_n <= (~soc_litedramcore_phaseinjector2_csrfield_we);
+ end else begin
+ soc_litedramcore_csr_dfi_p2_we_n <= 1'd1;
+ end
end
always @(*) begin
- soc_litedramcore_csr_dfi_p2_cas_n <= 1'd1;
- if (soc_litedramcore_phaseinjector2_command_issue_re) begin
- soc_litedramcore_csr_dfi_p2_cas_n <= (~soc_litedramcore_phaseinjector2_csrfield_cas);
- end else begin
- soc_litedramcore_csr_dfi_p2_cas_n <= 1'd1;
- end
+ soc_litedramcore_csr_dfi_p2_cas_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector2_command_issue_re) begin
+ soc_litedramcore_csr_dfi_p2_cas_n <= (~soc_litedramcore_phaseinjector2_csrfield_cas);
+ end else begin
+ soc_litedramcore_csr_dfi_p2_cas_n <= 1'd1;
+ end
end
assign soc_litedramcore_csr_dfi_p2_address = soc_litedramcore_phaseinjector2_address_storage;
assign soc_litedramcore_csr_dfi_p2_bank = soc_litedramcore_phaseinjector2_baddress_storage;
assign soc_litedramcore_csr_dfi_p2_wrdata = soc_litedramcore_phaseinjector2_wrdata_storage;
assign soc_litedramcore_csr_dfi_p2_wrdata_mask = 1'd0;
always @(*) begin
- soc_litedramcore_csr_dfi_p3_cs_n <= 1'd1;
- if (soc_litedramcore_phaseinjector3_command_issue_re) begin
- soc_litedramcore_csr_dfi_p3_cs_n <= {1{(~soc_litedramcore_phaseinjector3_csrfield_cs)}};
- end else begin
- soc_litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}};
- end
+ soc_litedramcore_csr_dfi_p3_cs_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector3_command_issue_re) begin
+ soc_litedramcore_csr_dfi_p3_cs_n <= {1{(~soc_litedramcore_phaseinjector3_csrfield_cs)}};
+ end else begin
+ soc_litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}};
+ end
end
always @(*) begin
- soc_litedramcore_csr_dfi_p3_ras_n <= 1'd1;
- if (soc_litedramcore_phaseinjector3_command_issue_re) begin
- soc_litedramcore_csr_dfi_p3_ras_n <= (~soc_litedramcore_phaseinjector3_csrfield_ras);
- end else begin
- soc_litedramcore_csr_dfi_p3_ras_n <= 1'd1;
- end
+ soc_litedramcore_csr_dfi_p3_ras_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector3_command_issue_re) begin
+ soc_litedramcore_csr_dfi_p3_ras_n <= (~soc_litedramcore_phaseinjector3_csrfield_ras);
+ end else begin
+ soc_litedramcore_csr_dfi_p3_ras_n <= 1'd1;
+ end
end
always @(*) begin
- soc_litedramcore_csr_dfi_p3_we_n <= 1'd1;
- if (soc_litedramcore_phaseinjector3_command_issue_re) begin
- soc_litedramcore_csr_dfi_p3_we_n <= (~soc_litedramcore_phaseinjector3_csrfield_we);
- end else begin
- soc_litedramcore_csr_dfi_p3_we_n <= 1'd1;
- end
+ soc_litedramcore_csr_dfi_p3_we_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector3_command_issue_re) begin
+ soc_litedramcore_csr_dfi_p3_we_n <= (~soc_litedramcore_phaseinjector3_csrfield_we);
+ end else begin
+ soc_litedramcore_csr_dfi_p3_we_n <= 1'd1;
+ end
end
always @(*) begin
- soc_litedramcore_csr_dfi_p3_cas_n <= 1'd1;
- if (soc_litedramcore_phaseinjector3_command_issue_re) begin
- soc_litedramcore_csr_dfi_p3_cas_n <= (~soc_litedramcore_phaseinjector3_csrfield_cas);
- end else begin
- soc_litedramcore_csr_dfi_p3_cas_n <= 1'd1;
- end
+ soc_litedramcore_csr_dfi_p3_cas_n <= 1'd1;
+ if (soc_litedramcore_phaseinjector3_command_issue_re) begin
+ soc_litedramcore_csr_dfi_p3_cas_n <= (~soc_litedramcore_phaseinjector3_csrfield_cas);
+ end else begin
+ soc_litedramcore_csr_dfi_p3_cas_n <= 1'd1;
+ end
end
assign soc_litedramcore_csr_dfi_p3_address = soc_litedramcore_phaseinjector3_address_storage;
assign soc_litedramcore_csr_dfi_p3_bank = soc_litedramcore_phaseinjector3_baddress_storage;
assign soc_litedramcore_zqcs_timer_done0 = soc_litedramcore_zqcs_timer_done1;
assign soc_litedramcore_zqcs_timer_count0 = soc_litedramcore_zqcs_timer_count1;
always @(*) begin
- litedramcore_refresher_next_state <= 2'd0;
- litedramcore_refresher_next_state <= litedramcore_refresher_state;
- case (litedramcore_refresher_state)
- 1'd1: begin
- if (soc_litedramcore_cmd_ready) begin
- litedramcore_refresher_next_state <= 2'd2;
- end
- end
- 2'd2: begin
- if (soc_litedramcore_sequencer_done0) begin
- if (soc_litedramcore_wants_zqcs) begin
- litedramcore_refresher_next_state <= 2'd3;
- end else begin
- litedramcore_refresher_next_state <= 1'd0;
- end
- end
- end
- 2'd3: begin
- if (soc_litedramcore_zqcs_executer_done) begin
- litedramcore_refresher_next_state <= 1'd0;
- end
- end
- default: begin
- if (1'd1) begin
- if (soc_litedramcore_wants_refresh) begin
- litedramcore_refresher_next_state <= 1'd1;
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_sequencer_start0 <= 1'd0;
- case (litedramcore_refresher_state)
- 1'd1: begin
- if (soc_litedramcore_cmd_ready) begin
- soc_litedramcore_sequencer_start0 <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_cmd_valid <= 1'd0;
- case (litedramcore_refresher_state)
- 1'd1: begin
- soc_litedramcore_cmd_valid <= 1'd1;
- end
- 2'd2: begin
- soc_litedramcore_cmd_valid <= 1'd1;
- if (soc_litedramcore_sequencer_done0) begin
- if (soc_litedramcore_wants_zqcs) begin
- end else begin
- soc_litedramcore_cmd_valid <= 1'd0;
- end
- end
- end
- 2'd3: begin
- soc_litedramcore_cmd_valid <= 1'd1;
- if (soc_litedramcore_zqcs_executer_done) begin
- soc_litedramcore_cmd_valid <= 1'd0;
- end
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_zqcs_executer_start <= 1'd0;
- case (litedramcore_refresher_state)
- 1'd1: begin
- end
- 2'd2: begin
- if (soc_litedramcore_sequencer_done0) begin
- if (soc_litedramcore_wants_zqcs) begin
- soc_litedramcore_zqcs_executer_start <= 1'd1;
- end else begin
- end
- end
- end
- 2'd3: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_cmd_last <= 1'd0;
- case (litedramcore_refresher_state)
- 1'd1: begin
- end
- 2'd2: begin
- if (soc_litedramcore_sequencer_done0) begin
- if (soc_litedramcore_wants_zqcs) begin
- end else begin
- soc_litedramcore_cmd_last <= 1'd1;
- end
- end
- end
- 2'd3: begin
- if (soc_litedramcore_zqcs_executer_done) begin
- soc_litedramcore_cmd_last <= 1'd1;
- end
- end
- default: begin
- end
- endcase
-end
-assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine0_req_valid;
-assign soc_litedramcore_bankmachine0_req_ready = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
-assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine0_req_we;
-assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine0_req_addr;
-assign soc_litedramcore_bankmachine0_cmd_buffer_sink_valid = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
-assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine0_cmd_buffer_sink_ready;
-assign soc_litedramcore_bankmachine0_cmd_buffer_sink_first = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
-assign soc_litedramcore_bankmachine0_cmd_buffer_sink_last = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
-assign soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
-assign soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
-assign soc_litedramcore_bankmachine0_cmd_buffer_source_ready = (soc_litedramcore_bankmachine0_req_wdata_ready | soc_litedramcore_bankmachine0_req_rdata_valid);
-assign soc_litedramcore_bankmachine0_req_lock = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine0_cmd_buffer_source_valid);
-assign soc_litedramcore_bankmachine0_row_hit = (soc_litedramcore_bankmachine0_row == soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]);
+ litedramcore_refresher_next_state <= 2'd0;
+ litedramcore_refresher_next_state <= litedramcore_refresher_state;
+ case (litedramcore_refresher_state)
+ 1'd1: begin
+ if (soc_litedramcore_cmd_ready) begin
+ litedramcore_refresher_next_state <= 2'd2;
+ end
+ end
+ 2'd2: begin
+ if (soc_litedramcore_sequencer_done0) begin
+ if (soc_litedramcore_wants_zqcs) begin
+ litedramcore_refresher_next_state <= 2'd3;
+ end else begin
+ litedramcore_refresher_next_state <= 1'd0;
+ end
+ end
+ end
+ 2'd3: begin
+ if (soc_litedramcore_zqcs_executer_done) begin
+ litedramcore_refresher_next_state <= 1'd0;
+ end
+ end
+ default: begin
+ if (1'd1) begin
+ if (soc_litedramcore_wants_refresh) begin
+ litedramcore_refresher_next_state <= 1'd1;
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_sequencer_start0 <= 1'd0;
+ case (litedramcore_refresher_state)
+ 1'd1: begin
+ if (soc_litedramcore_cmd_ready) begin
+ soc_litedramcore_sequencer_start0 <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_cmd_valid <= 1'd0;
+ case (litedramcore_refresher_state)
+ 1'd1: begin
+ soc_litedramcore_cmd_valid <= 1'd1;
+ end
+ 2'd2: begin
+ soc_litedramcore_cmd_valid <= 1'd1;
+ if (soc_litedramcore_sequencer_done0) begin
+ if (soc_litedramcore_wants_zqcs) begin
+ end else begin
+ soc_litedramcore_cmd_valid <= 1'd0;
+ end
+ end
+ end
+ 2'd3: begin
+ soc_litedramcore_cmd_valid <= 1'd1;
+ if (soc_litedramcore_zqcs_executer_done) begin
+ soc_litedramcore_cmd_valid <= 1'd0;
+ end
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_zqcs_executer_start <= 1'd0;
+ case (litedramcore_refresher_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ if (soc_litedramcore_sequencer_done0) begin
+ if (soc_litedramcore_wants_zqcs) begin
+ soc_litedramcore_zqcs_executer_start <= 1'd1;
+ end else begin
+ end
+ end
+ end
+ 2'd3: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_cmd_last <= 1'd0;
+ case (litedramcore_refresher_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ if (soc_litedramcore_sequencer_done0) begin
+ if (soc_litedramcore_wants_zqcs) begin
+ end else begin
+ soc_litedramcore_cmd_last <= 1'd1;
+ end
+ end
+ end
+ 2'd3: begin
+ if (soc_litedramcore_zqcs_executer_done) begin
+ soc_litedramcore_cmd_last <= 1'd1;
+ end
+ end
+ default: begin
+ end
+ endcase
+end
+assign soc_litedramcore_bankmachine0_sink_valid = soc_litedramcore_bankmachine0_req_valid;
+assign soc_litedramcore_bankmachine0_req_ready = soc_litedramcore_bankmachine0_sink_ready;
+assign soc_litedramcore_bankmachine0_sink_payload_we = soc_litedramcore_bankmachine0_req_we;
+assign soc_litedramcore_bankmachine0_sink_payload_addr = soc_litedramcore_bankmachine0_req_addr;
+assign soc_litedramcore_bankmachine0_sink_sink_valid = soc_litedramcore_bankmachine0_source_valid;
+assign soc_litedramcore_bankmachine0_source_ready = soc_litedramcore_bankmachine0_sink_sink_ready;
+assign soc_litedramcore_bankmachine0_sink_sink_first = soc_litedramcore_bankmachine0_source_first;
+assign soc_litedramcore_bankmachine0_sink_sink_last = soc_litedramcore_bankmachine0_source_last;
+assign soc_litedramcore_bankmachine0_sink_sink_payload_we = soc_litedramcore_bankmachine0_source_payload_we;
+assign soc_litedramcore_bankmachine0_sink_sink_payload_addr = soc_litedramcore_bankmachine0_source_payload_addr;
+assign soc_litedramcore_bankmachine0_source_source_ready = (soc_litedramcore_bankmachine0_req_wdata_ready | soc_litedramcore_bankmachine0_req_rdata_valid);
+assign soc_litedramcore_bankmachine0_req_lock = (soc_litedramcore_bankmachine0_source_valid | soc_litedramcore_bankmachine0_source_source_valid);
+assign soc_litedramcore_bankmachine0_row_hit = (soc_litedramcore_bankmachine0_row == soc_litedramcore_bankmachine0_source_source_payload_addr[20:7]);
assign soc_litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
always @(*) begin
- soc_litedramcore_bankmachine0_cmd_payload_a <= 14'd0;
- if (soc_litedramcore_bankmachine0_row_col_n_addr_sel) begin
- soc_litedramcore_bankmachine0_cmd_payload_a <= soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7];
- end else begin
- soc_litedramcore_bankmachine0_cmd_payload_a <= ((soc_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ soc_litedramcore_bankmachine0_cmd_payload_a <= 14'd0;
+ if (soc_litedramcore_bankmachine0_row_col_n_addr_sel) begin
+ soc_litedramcore_bankmachine0_cmd_payload_a <= soc_litedramcore_bankmachine0_source_source_payload_addr[20:7];
+ end else begin
+ soc_litedramcore_bankmachine0_cmd_payload_a <= ((soc_litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine0_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign soc_litedramcore_bankmachine0_twtpcon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_cmd_payload_is_write);
assign soc_litedramcore_bankmachine0_trccon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_row_open);
assign soc_litedramcore_bankmachine0_trascon_valid = ((soc_litedramcore_bankmachine0_cmd_valid & soc_litedramcore_bankmachine0_cmd_ready) & soc_litedramcore_bankmachine0_row_open);
always @(*) begin
- soc_litedramcore_bankmachine0_auto_precharge <= 1'd0;
- if ((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine0_cmd_buffer_source_valid)) begin
- if ((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7])) begin
- soc_litedramcore_bankmachine0_auto_precharge <= (soc_litedramcore_bankmachine0_row_close == 1'd0);
- end
- end
-end
-assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
-assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
-assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first;
-assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last;
-assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
-assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
-assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
-assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
-assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
-assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
-assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin
- soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce;
- end
-end
-assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
-assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace));
-assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re);
-assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume;
-assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
-assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16);
-assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
-assign soc_litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine0_cmd_buffer_source_valid) | soc_litedramcore_bankmachine0_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine0_next_state <= 4'd0;
- litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
- if (soc_litedramcore_bankmachine0_cmd_ready) begin
- litedramcore_bankmachine0_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine0_trccon_ready) begin
- if (soc_litedramcore_bankmachine0_cmd_ready) begin
- litedramcore_bankmachine0_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~soc_litedramcore_bankmachine0_refresh_req)) begin
- litedramcore_bankmachine0_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine0_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine0_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine0_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine0_next_state <= 1'd0;
- end
- default: begin
- if (soc_litedramcore_bankmachine0_refresh_req) begin
- litedramcore_bankmachine0_next_state <= 3'd4;
- end else begin
- if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine0_row_opened) begin
- if (soc_litedramcore_bankmachine0_row_hit) begin
- if ((soc_litedramcore_bankmachine0_cmd_ready & soc_litedramcore_bankmachine0_auto_precharge)) begin
- litedramcore_bankmachine0_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine0_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine0_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine0_row_open <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine0_trccon_ready) begin
- soc_litedramcore_bankmachine0_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine0_row_close <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- soc_litedramcore_bankmachine0_row_close <= 1'd1;
- end
- 2'd2: begin
- soc_litedramcore_bankmachine0_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- soc_litedramcore_bankmachine0_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine0_row_opened) begin
- if (soc_litedramcore_bankmachine0_row_hit) begin
- soc_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
- soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine0_trccon_ready) begin
- soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
- soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine0_row_opened) begin
- if (soc_litedramcore_bankmachine0_row_hit) begin
- if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine0_trccon_ready) begin
- soc_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
- soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine0_trccon_ready) begin
- soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine0_row_opened) begin
- if (soc_litedramcore_bankmachine0_row_hit) begin
- if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- end else begin
- soc_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine0_row_opened) begin
- if (soc_litedramcore_bankmachine0_row_hit) begin
- if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- soc_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine0_row_opened) begin
- if (soc_litedramcore_bankmachine0_row_hit) begin
- if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- soc_litedramcore_bankmachine0_req_wdata_ready <= soc_litedramcore_bankmachine0_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine0_row_opened) begin
- if (soc_litedramcore_bankmachine0_row_hit) begin
- if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- end else begin
- soc_litedramcore_bankmachine0_req_rdata_valid <= soc_litedramcore_bankmachine0_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine0_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (soc_litedramcore_bankmachine0_twtpcon_ready) begin
- soc_litedramcore_bankmachine0_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine0_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
- soc_litedramcore_bankmachine0_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine0_trccon_ready) begin
- soc_litedramcore_bankmachine0_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine0_row_opened) begin
- if (soc_litedramcore_bankmachine0_row_hit) begin
- soc_litedramcore_bankmachine0_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine1_req_valid;
-assign soc_litedramcore_bankmachine1_req_ready = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
-assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine1_req_we;
-assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine1_req_addr;
-assign soc_litedramcore_bankmachine1_cmd_buffer_sink_valid = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
-assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine1_cmd_buffer_sink_ready;
-assign soc_litedramcore_bankmachine1_cmd_buffer_sink_first = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
-assign soc_litedramcore_bankmachine1_cmd_buffer_sink_last = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
-assign soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
-assign soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
-assign soc_litedramcore_bankmachine1_cmd_buffer_source_ready = (soc_litedramcore_bankmachine1_req_wdata_ready | soc_litedramcore_bankmachine1_req_rdata_valid);
-assign soc_litedramcore_bankmachine1_req_lock = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine1_cmd_buffer_source_valid);
-assign soc_litedramcore_bankmachine1_row_hit = (soc_litedramcore_bankmachine1_row == soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]);
+ soc_litedramcore_bankmachine0_auto_precharge <= 1'd0;
+ if ((soc_litedramcore_bankmachine0_source_valid & soc_litedramcore_bankmachine0_source_source_valid)) begin
+ if ((soc_litedramcore_bankmachine0_source_payload_addr[20:7] != soc_litedramcore_bankmachine0_source_source_payload_addr[20:7])) begin
+ soc_litedramcore_bankmachine0_auto_precharge <= (soc_litedramcore_bankmachine0_row_close == 1'd0);
+ end
+ end
+end
+assign soc_litedramcore_bankmachine0_syncfifo0_din = {soc_litedramcore_bankmachine0_fifo_in_last, soc_litedramcore_bankmachine0_fifo_in_first, soc_litedramcore_bankmachine0_fifo_in_payload_addr, soc_litedramcore_bankmachine0_fifo_in_payload_we};
+assign {soc_litedramcore_bankmachine0_fifo_out_last, soc_litedramcore_bankmachine0_fifo_out_first, soc_litedramcore_bankmachine0_fifo_out_payload_addr, soc_litedramcore_bankmachine0_fifo_out_payload_we} = soc_litedramcore_bankmachine0_syncfifo0_dout;
+assign {soc_litedramcore_bankmachine0_fifo_out_last, soc_litedramcore_bankmachine0_fifo_out_first, soc_litedramcore_bankmachine0_fifo_out_payload_addr, soc_litedramcore_bankmachine0_fifo_out_payload_we} = soc_litedramcore_bankmachine0_syncfifo0_dout;
+assign {soc_litedramcore_bankmachine0_fifo_out_last, soc_litedramcore_bankmachine0_fifo_out_first, soc_litedramcore_bankmachine0_fifo_out_payload_addr, soc_litedramcore_bankmachine0_fifo_out_payload_we} = soc_litedramcore_bankmachine0_syncfifo0_dout;
+assign {soc_litedramcore_bankmachine0_fifo_out_last, soc_litedramcore_bankmachine0_fifo_out_first, soc_litedramcore_bankmachine0_fifo_out_payload_addr, soc_litedramcore_bankmachine0_fifo_out_payload_we} = soc_litedramcore_bankmachine0_syncfifo0_dout;
+assign soc_litedramcore_bankmachine0_sink_ready = soc_litedramcore_bankmachine0_syncfifo0_writable;
+assign soc_litedramcore_bankmachine0_syncfifo0_we = soc_litedramcore_bankmachine0_sink_valid;
+assign soc_litedramcore_bankmachine0_fifo_in_first = soc_litedramcore_bankmachine0_sink_first;
+assign soc_litedramcore_bankmachine0_fifo_in_last = soc_litedramcore_bankmachine0_sink_last;
+assign soc_litedramcore_bankmachine0_fifo_in_payload_we = soc_litedramcore_bankmachine0_sink_payload_we;
+assign soc_litedramcore_bankmachine0_fifo_in_payload_addr = soc_litedramcore_bankmachine0_sink_payload_addr;
+assign soc_litedramcore_bankmachine0_source_valid = soc_litedramcore_bankmachine0_syncfifo0_readable;
+assign soc_litedramcore_bankmachine0_source_first = soc_litedramcore_bankmachine0_fifo_out_first;
+assign soc_litedramcore_bankmachine0_source_last = soc_litedramcore_bankmachine0_fifo_out_last;
+assign soc_litedramcore_bankmachine0_source_payload_we = soc_litedramcore_bankmachine0_fifo_out_payload_we;
+assign soc_litedramcore_bankmachine0_source_payload_addr = soc_litedramcore_bankmachine0_fifo_out_payload_addr;
+assign soc_litedramcore_bankmachine0_syncfifo0_re = soc_litedramcore_bankmachine0_source_ready;
+always @(*) begin
+ soc_litedramcore_bankmachine0_wrport_adr <= 4'd0;
+ if (soc_litedramcore_bankmachine0_replace) begin
+ soc_litedramcore_bankmachine0_wrport_adr <= (soc_litedramcore_bankmachine0_produce - 1'd1);
+ end else begin
+ soc_litedramcore_bankmachine0_wrport_adr <= soc_litedramcore_bankmachine0_produce;
+ end
+end
+assign soc_litedramcore_bankmachine0_wrport_dat_w = soc_litedramcore_bankmachine0_syncfifo0_din;
+assign soc_litedramcore_bankmachine0_wrport_we = (soc_litedramcore_bankmachine0_syncfifo0_we & (soc_litedramcore_bankmachine0_syncfifo0_writable | soc_litedramcore_bankmachine0_replace));
+assign soc_litedramcore_bankmachine0_do_read = (soc_litedramcore_bankmachine0_syncfifo0_readable & soc_litedramcore_bankmachine0_syncfifo0_re);
+assign soc_litedramcore_bankmachine0_rdport_adr = soc_litedramcore_bankmachine0_consume;
+assign soc_litedramcore_bankmachine0_syncfifo0_dout = soc_litedramcore_bankmachine0_rdport_dat_r;
+assign soc_litedramcore_bankmachine0_syncfifo0_writable = (soc_litedramcore_bankmachine0_level != 5'd16);
+assign soc_litedramcore_bankmachine0_syncfifo0_readable = (soc_litedramcore_bankmachine0_level != 1'd0);
+assign soc_litedramcore_bankmachine0_pipe_valid_sink_ready = ((~soc_litedramcore_bankmachine0_pipe_valid_source_valid) | soc_litedramcore_bankmachine0_pipe_valid_source_ready);
+assign soc_litedramcore_bankmachine0_pipe_valid_sink_valid = soc_litedramcore_bankmachine0_sink_sink_valid;
+assign soc_litedramcore_bankmachine0_sink_sink_ready = soc_litedramcore_bankmachine0_pipe_valid_sink_ready;
+assign soc_litedramcore_bankmachine0_pipe_valid_sink_first = soc_litedramcore_bankmachine0_sink_sink_first;
+assign soc_litedramcore_bankmachine0_pipe_valid_sink_last = soc_litedramcore_bankmachine0_sink_sink_last;
+assign soc_litedramcore_bankmachine0_pipe_valid_sink_payload_we = soc_litedramcore_bankmachine0_sink_sink_payload_we;
+assign soc_litedramcore_bankmachine0_pipe_valid_sink_payload_addr = soc_litedramcore_bankmachine0_sink_sink_payload_addr;
+assign soc_litedramcore_bankmachine0_source_source_valid = soc_litedramcore_bankmachine0_pipe_valid_source_valid;
+assign soc_litedramcore_bankmachine0_pipe_valid_source_ready = soc_litedramcore_bankmachine0_source_source_ready;
+assign soc_litedramcore_bankmachine0_source_source_first = soc_litedramcore_bankmachine0_pipe_valid_source_first;
+assign soc_litedramcore_bankmachine0_source_source_last = soc_litedramcore_bankmachine0_pipe_valid_source_last;
+assign soc_litedramcore_bankmachine0_source_source_payload_we = soc_litedramcore_bankmachine0_pipe_valid_source_payload_we;
+assign soc_litedramcore_bankmachine0_source_source_payload_addr = soc_litedramcore_bankmachine0_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine0_next_state <= 4'd0;
+ litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
+ if (soc_litedramcore_bankmachine0_cmd_ready) begin
+ litedramcore_bankmachine0_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine0_trccon_ready) begin
+ if (soc_litedramcore_bankmachine0_cmd_ready) begin
+ litedramcore_bankmachine0_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~soc_litedramcore_bankmachine0_refresh_req)) begin
+ litedramcore_bankmachine0_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine0_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine0_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine0_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine0_next_state <= 1'd0;
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine0_refresh_req) begin
+ litedramcore_bankmachine0_next_state <= 3'd4;
+ end else begin
+ if (soc_litedramcore_bankmachine0_source_source_valid) begin
+ if (soc_litedramcore_bankmachine0_row_opened) begin
+ if (soc_litedramcore_bankmachine0_row_hit) begin
+ if ((soc_litedramcore_bankmachine0_cmd_ready & soc_litedramcore_bankmachine0_auto_precharge)) begin
+ litedramcore_bankmachine0_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine0_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine0_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine0_trccon_ready) begin
+ soc_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine0_source_source_valid) begin
+ if (soc_litedramcore_bankmachine0_row_opened) begin
+ if (soc_litedramcore_bankmachine0_row_hit) begin
+ soc_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
+ soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine0_trccon_ready) begin
+ soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
+ soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine0_source_source_valid) begin
+ if (soc_litedramcore_bankmachine0_row_opened) begin
+ if (soc_litedramcore_bankmachine0_row_hit) begin
+ if (soc_litedramcore_bankmachine0_source_source_payload_we) begin
+ soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
+ soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine0_trccon_ready) begin
+ soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine0_source_source_valid) begin
+ if (soc_litedramcore_bankmachine0_row_opened) begin
+ if (soc_litedramcore_bankmachine0_row_hit) begin
+ if (soc_litedramcore_bankmachine0_source_source_payload_we) begin
+ end else begin
+ soc_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine0_source_source_valid) begin
+ if (soc_litedramcore_bankmachine0_row_opened) begin
+ if (soc_litedramcore_bankmachine0_row_hit) begin
+ if (soc_litedramcore_bankmachine0_source_source_payload_we) begin
+ soc_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine0_source_source_valid) begin
+ if (soc_litedramcore_bankmachine0_row_opened) begin
+ if (soc_litedramcore_bankmachine0_row_hit) begin
+ if (soc_litedramcore_bankmachine0_source_source_payload_we) begin
+ soc_litedramcore_bankmachine0_req_wdata_ready <= soc_litedramcore_bankmachine0_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine0_source_source_valid) begin
+ if (soc_litedramcore_bankmachine0_row_opened) begin
+ if (soc_litedramcore_bankmachine0_row_hit) begin
+ if (soc_litedramcore_bankmachine0_source_source_payload_we) begin
+ end else begin
+ soc_litedramcore_bankmachine0_req_rdata_valid <= soc_litedramcore_bankmachine0_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine0_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (soc_litedramcore_bankmachine0_twtpcon_ready) begin
+ soc_litedramcore_bankmachine0_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine0_row_open <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine0_trccon_ready) begin
+ soc_litedramcore_bankmachine0_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine0_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
+ soc_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine0_trccon_ready) begin
+ soc_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine0_source_source_valid) begin
+ if (soc_litedramcore_bankmachine0_row_opened) begin
+ if (soc_litedramcore_bankmachine0_row_hit) begin
+ soc_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine0_row_close <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ soc_litedramcore_bankmachine0_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ soc_litedramcore_bankmachine0_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ soc_litedramcore_bankmachine0_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+assign soc_litedramcore_bankmachine1_sink_valid = soc_litedramcore_bankmachine1_req_valid;
+assign soc_litedramcore_bankmachine1_req_ready = soc_litedramcore_bankmachine1_sink_ready;
+assign soc_litedramcore_bankmachine1_sink_payload_we = soc_litedramcore_bankmachine1_req_we;
+assign soc_litedramcore_bankmachine1_sink_payload_addr = soc_litedramcore_bankmachine1_req_addr;
+assign soc_litedramcore_bankmachine1_sink_sink_valid = soc_litedramcore_bankmachine1_source_valid;
+assign soc_litedramcore_bankmachine1_source_ready = soc_litedramcore_bankmachine1_sink_sink_ready;
+assign soc_litedramcore_bankmachine1_sink_sink_first = soc_litedramcore_bankmachine1_source_first;
+assign soc_litedramcore_bankmachine1_sink_sink_last = soc_litedramcore_bankmachine1_source_last;
+assign soc_litedramcore_bankmachine1_sink_sink_payload_we = soc_litedramcore_bankmachine1_source_payload_we;
+assign soc_litedramcore_bankmachine1_sink_sink_payload_addr = soc_litedramcore_bankmachine1_source_payload_addr;
+assign soc_litedramcore_bankmachine1_source_source_ready = (soc_litedramcore_bankmachine1_req_wdata_ready | soc_litedramcore_bankmachine1_req_rdata_valid);
+assign soc_litedramcore_bankmachine1_req_lock = (soc_litedramcore_bankmachine1_source_valid | soc_litedramcore_bankmachine1_source_source_valid);
+assign soc_litedramcore_bankmachine1_row_hit = (soc_litedramcore_bankmachine1_row == soc_litedramcore_bankmachine1_source_source_payload_addr[20:7]);
assign soc_litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
always @(*) begin
- soc_litedramcore_bankmachine1_cmd_payload_a <= 14'd0;
- if (soc_litedramcore_bankmachine1_row_col_n_addr_sel) begin
- soc_litedramcore_bankmachine1_cmd_payload_a <= soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7];
- end else begin
- soc_litedramcore_bankmachine1_cmd_payload_a <= ((soc_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ soc_litedramcore_bankmachine1_cmd_payload_a <= 14'd0;
+ if (soc_litedramcore_bankmachine1_row_col_n_addr_sel) begin
+ soc_litedramcore_bankmachine1_cmd_payload_a <= soc_litedramcore_bankmachine1_source_source_payload_addr[20:7];
+ end else begin
+ soc_litedramcore_bankmachine1_cmd_payload_a <= ((soc_litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine1_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign soc_litedramcore_bankmachine1_twtpcon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_cmd_payload_is_write);
assign soc_litedramcore_bankmachine1_trccon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_row_open);
assign soc_litedramcore_bankmachine1_trascon_valid = ((soc_litedramcore_bankmachine1_cmd_valid & soc_litedramcore_bankmachine1_cmd_ready) & soc_litedramcore_bankmachine1_row_open);
always @(*) begin
- soc_litedramcore_bankmachine1_auto_precharge <= 1'd0;
- if ((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine1_cmd_buffer_source_valid)) begin
- if ((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7])) begin
- soc_litedramcore_bankmachine1_auto_precharge <= (soc_litedramcore_bankmachine1_row_close == 1'd0);
- end
- end
-end
-assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
-assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
-assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first;
-assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last;
-assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
-assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
-assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
-assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
-assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
-assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
-assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin
- soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce;
- end
-end
-assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
-assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace));
-assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re);
-assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume;
-assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
-assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16);
-assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
-assign soc_litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine1_cmd_buffer_source_valid) | soc_litedramcore_bankmachine1_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine1_next_state <= 4'd0;
- litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
- if (soc_litedramcore_bankmachine1_cmd_ready) begin
- litedramcore_bankmachine1_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine1_trccon_ready) begin
- if (soc_litedramcore_bankmachine1_cmd_ready) begin
- litedramcore_bankmachine1_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~soc_litedramcore_bankmachine1_refresh_req)) begin
- litedramcore_bankmachine1_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine1_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine1_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine1_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine1_next_state <= 1'd0;
- end
- default: begin
- if (soc_litedramcore_bankmachine1_refresh_req) begin
- litedramcore_bankmachine1_next_state <= 3'd4;
- end else begin
- if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine1_row_opened) begin
- if (soc_litedramcore_bankmachine1_row_hit) begin
- if ((soc_litedramcore_bankmachine1_cmd_ready & soc_litedramcore_bankmachine1_auto_precharge)) begin
- litedramcore_bankmachine1_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine1_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine1_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine1_row_open <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine1_trccon_ready) begin
- soc_litedramcore_bankmachine1_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine1_row_close <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- soc_litedramcore_bankmachine1_row_close <= 1'd1;
- end
- 2'd2: begin
- soc_litedramcore_bankmachine1_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- soc_litedramcore_bankmachine1_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine1_row_opened) begin
- if (soc_litedramcore_bankmachine1_row_hit) begin
- soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
- soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine1_trccon_ready) begin
- soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
- soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine1_row_opened) begin
- if (soc_litedramcore_bankmachine1_row_hit) begin
- if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine1_trccon_ready) begin
- soc_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
- soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine1_trccon_ready) begin
- soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine1_row_opened) begin
- if (soc_litedramcore_bankmachine1_row_hit) begin
- if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- end else begin
- soc_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine1_row_opened) begin
- if (soc_litedramcore_bankmachine1_row_hit) begin
- if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- soc_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine1_row_opened) begin
- if (soc_litedramcore_bankmachine1_row_hit) begin
- if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- soc_litedramcore_bankmachine1_req_wdata_ready <= soc_litedramcore_bankmachine1_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine1_row_opened) begin
- if (soc_litedramcore_bankmachine1_row_hit) begin
- if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- end else begin
- soc_litedramcore_bankmachine1_req_rdata_valid <= soc_litedramcore_bankmachine1_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine1_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (soc_litedramcore_bankmachine1_twtpcon_ready) begin
- soc_litedramcore_bankmachine1_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine1_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
- soc_litedramcore_bankmachine1_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine1_trccon_ready) begin
- soc_litedramcore_bankmachine1_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine1_row_opened) begin
- if (soc_litedramcore_bankmachine1_row_hit) begin
- soc_litedramcore_bankmachine1_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine2_req_valid;
-assign soc_litedramcore_bankmachine2_req_ready = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
-assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine2_req_we;
-assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine2_req_addr;
-assign soc_litedramcore_bankmachine2_cmd_buffer_sink_valid = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
-assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine2_cmd_buffer_sink_ready;
-assign soc_litedramcore_bankmachine2_cmd_buffer_sink_first = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
-assign soc_litedramcore_bankmachine2_cmd_buffer_sink_last = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
-assign soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
-assign soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
-assign soc_litedramcore_bankmachine2_cmd_buffer_source_ready = (soc_litedramcore_bankmachine2_req_wdata_ready | soc_litedramcore_bankmachine2_req_rdata_valid);
-assign soc_litedramcore_bankmachine2_req_lock = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine2_cmd_buffer_source_valid);
-assign soc_litedramcore_bankmachine2_row_hit = (soc_litedramcore_bankmachine2_row == soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]);
+ soc_litedramcore_bankmachine1_auto_precharge <= 1'd0;
+ if ((soc_litedramcore_bankmachine1_source_valid & soc_litedramcore_bankmachine1_source_source_valid)) begin
+ if ((soc_litedramcore_bankmachine1_source_payload_addr[20:7] != soc_litedramcore_bankmachine1_source_source_payload_addr[20:7])) begin
+ soc_litedramcore_bankmachine1_auto_precharge <= (soc_litedramcore_bankmachine1_row_close == 1'd0);
+ end
+ end
+end
+assign soc_litedramcore_bankmachine1_syncfifo1_din = {soc_litedramcore_bankmachine1_fifo_in_last, soc_litedramcore_bankmachine1_fifo_in_first, soc_litedramcore_bankmachine1_fifo_in_payload_addr, soc_litedramcore_bankmachine1_fifo_in_payload_we};
+assign {soc_litedramcore_bankmachine1_fifo_out_last, soc_litedramcore_bankmachine1_fifo_out_first, soc_litedramcore_bankmachine1_fifo_out_payload_addr, soc_litedramcore_bankmachine1_fifo_out_payload_we} = soc_litedramcore_bankmachine1_syncfifo1_dout;
+assign {soc_litedramcore_bankmachine1_fifo_out_last, soc_litedramcore_bankmachine1_fifo_out_first, soc_litedramcore_bankmachine1_fifo_out_payload_addr, soc_litedramcore_bankmachine1_fifo_out_payload_we} = soc_litedramcore_bankmachine1_syncfifo1_dout;
+assign {soc_litedramcore_bankmachine1_fifo_out_last, soc_litedramcore_bankmachine1_fifo_out_first, soc_litedramcore_bankmachine1_fifo_out_payload_addr, soc_litedramcore_bankmachine1_fifo_out_payload_we} = soc_litedramcore_bankmachine1_syncfifo1_dout;
+assign {soc_litedramcore_bankmachine1_fifo_out_last, soc_litedramcore_bankmachine1_fifo_out_first, soc_litedramcore_bankmachine1_fifo_out_payload_addr, soc_litedramcore_bankmachine1_fifo_out_payload_we} = soc_litedramcore_bankmachine1_syncfifo1_dout;
+assign soc_litedramcore_bankmachine1_sink_ready = soc_litedramcore_bankmachine1_syncfifo1_writable;
+assign soc_litedramcore_bankmachine1_syncfifo1_we = soc_litedramcore_bankmachine1_sink_valid;
+assign soc_litedramcore_bankmachine1_fifo_in_first = soc_litedramcore_bankmachine1_sink_first;
+assign soc_litedramcore_bankmachine1_fifo_in_last = soc_litedramcore_bankmachine1_sink_last;
+assign soc_litedramcore_bankmachine1_fifo_in_payload_we = soc_litedramcore_bankmachine1_sink_payload_we;
+assign soc_litedramcore_bankmachine1_fifo_in_payload_addr = soc_litedramcore_bankmachine1_sink_payload_addr;
+assign soc_litedramcore_bankmachine1_source_valid = soc_litedramcore_bankmachine1_syncfifo1_readable;
+assign soc_litedramcore_bankmachine1_source_first = soc_litedramcore_bankmachine1_fifo_out_first;
+assign soc_litedramcore_bankmachine1_source_last = soc_litedramcore_bankmachine1_fifo_out_last;
+assign soc_litedramcore_bankmachine1_source_payload_we = soc_litedramcore_bankmachine1_fifo_out_payload_we;
+assign soc_litedramcore_bankmachine1_source_payload_addr = soc_litedramcore_bankmachine1_fifo_out_payload_addr;
+assign soc_litedramcore_bankmachine1_syncfifo1_re = soc_litedramcore_bankmachine1_source_ready;
+always @(*) begin
+ soc_litedramcore_bankmachine1_wrport_adr <= 4'd0;
+ if (soc_litedramcore_bankmachine1_replace) begin
+ soc_litedramcore_bankmachine1_wrport_adr <= (soc_litedramcore_bankmachine1_produce - 1'd1);
+ end else begin
+ soc_litedramcore_bankmachine1_wrport_adr <= soc_litedramcore_bankmachine1_produce;
+ end
+end
+assign soc_litedramcore_bankmachine1_wrport_dat_w = soc_litedramcore_bankmachine1_syncfifo1_din;
+assign soc_litedramcore_bankmachine1_wrport_we = (soc_litedramcore_bankmachine1_syncfifo1_we & (soc_litedramcore_bankmachine1_syncfifo1_writable | soc_litedramcore_bankmachine1_replace));
+assign soc_litedramcore_bankmachine1_do_read = (soc_litedramcore_bankmachine1_syncfifo1_readable & soc_litedramcore_bankmachine1_syncfifo1_re);
+assign soc_litedramcore_bankmachine1_rdport_adr = soc_litedramcore_bankmachine1_consume;
+assign soc_litedramcore_bankmachine1_syncfifo1_dout = soc_litedramcore_bankmachine1_rdport_dat_r;
+assign soc_litedramcore_bankmachine1_syncfifo1_writable = (soc_litedramcore_bankmachine1_level != 5'd16);
+assign soc_litedramcore_bankmachine1_syncfifo1_readable = (soc_litedramcore_bankmachine1_level != 1'd0);
+assign soc_litedramcore_bankmachine1_pipe_valid_sink_ready = ((~soc_litedramcore_bankmachine1_pipe_valid_source_valid) | soc_litedramcore_bankmachine1_pipe_valid_source_ready);
+assign soc_litedramcore_bankmachine1_pipe_valid_sink_valid = soc_litedramcore_bankmachine1_sink_sink_valid;
+assign soc_litedramcore_bankmachine1_sink_sink_ready = soc_litedramcore_bankmachine1_pipe_valid_sink_ready;
+assign soc_litedramcore_bankmachine1_pipe_valid_sink_first = soc_litedramcore_bankmachine1_sink_sink_first;
+assign soc_litedramcore_bankmachine1_pipe_valid_sink_last = soc_litedramcore_bankmachine1_sink_sink_last;
+assign soc_litedramcore_bankmachine1_pipe_valid_sink_payload_we = soc_litedramcore_bankmachine1_sink_sink_payload_we;
+assign soc_litedramcore_bankmachine1_pipe_valid_sink_payload_addr = soc_litedramcore_bankmachine1_sink_sink_payload_addr;
+assign soc_litedramcore_bankmachine1_source_source_valid = soc_litedramcore_bankmachine1_pipe_valid_source_valid;
+assign soc_litedramcore_bankmachine1_pipe_valid_source_ready = soc_litedramcore_bankmachine1_source_source_ready;
+assign soc_litedramcore_bankmachine1_source_source_first = soc_litedramcore_bankmachine1_pipe_valid_source_first;
+assign soc_litedramcore_bankmachine1_source_source_last = soc_litedramcore_bankmachine1_pipe_valid_source_last;
+assign soc_litedramcore_bankmachine1_source_source_payload_we = soc_litedramcore_bankmachine1_pipe_valid_source_payload_we;
+assign soc_litedramcore_bankmachine1_source_source_payload_addr = soc_litedramcore_bankmachine1_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine1_next_state <= 4'd0;
+ litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
+ if (soc_litedramcore_bankmachine1_cmd_ready) begin
+ litedramcore_bankmachine1_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine1_trccon_ready) begin
+ if (soc_litedramcore_bankmachine1_cmd_ready) begin
+ litedramcore_bankmachine1_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~soc_litedramcore_bankmachine1_refresh_req)) begin
+ litedramcore_bankmachine1_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine1_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine1_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine1_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine1_next_state <= 1'd0;
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine1_refresh_req) begin
+ litedramcore_bankmachine1_next_state <= 3'd4;
+ end else begin
+ if (soc_litedramcore_bankmachine1_source_source_valid) begin
+ if (soc_litedramcore_bankmachine1_row_opened) begin
+ if (soc_litedramcore_bankmachine1_row_hit) begin
+ if ((soc_litedramcore_bankmachine1_cmd_ready & soc_litedramcore_bankmachine1_auto_precharge)) begin
+ litedramcore_bankmachine1_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine1_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine1_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
+ soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine1_trccon_ready) begin
+ soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
+ soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine1_source_source_valid) begin
+ if (soc_litedramcore_bankmachine1_row_opened) begin
+ if (soc_litedramcore_bankmachine1_row_hit) begin
+ if (soc_litedramcore_bankmachine1_source_source_payload_we) begin
+ soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
+ soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine1_trccon_ready) begin
+ soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine1_source_source_valid) begin
+ if (soc_litedramcore_bankmachine1_row_opened) begin
+ if (soc_litedramcore_bankmachine1_row_hit) begin
+ if (soc_litedramcore_bankmachine1_source_source_payload_we) begin
+ end else begin
+ soc_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine1_source_source_valid) begin
+ if (soc_litedramcore_bankmachine1_row_opened) begin
+ if (soc_litedramcore_bankmachine1_row_hit) begin
+ if (soc_litedramcore_bankmachine1_source_source_payload_we) begin
+ soc_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine1_source_source_valid) begin
+ if (soc_litedramcore_bankmachine1_row_opened) begin
+ if (soc_litedramcore_bankmachine1_row_hit) begin
+ if (soc_litedramcore_bankmachine1_source_source_payload_we) begin
+ soc_litedramcore_bankmachine1_req_wdata_ready <= soc_litedramcore_bankmachine1_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine1_source_source_valid) begin
+ if (soc_litedramcore_bankmachine1_row_opened) begin
+ if (soc_litedramcore_bankmachine1_row_hit) begin
+ if (soc_litedramcore_bankmachine1_source_source_payload_we) begin
+ end else begin
+ soc_litedramcore_bankmachine1_req_rdata_valid <= soc_litedramcore_bankmachine1_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine1_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (soc_litedramcore_bankmachine1_twtpcon_ready) begin
+ soc_litedramcore_bankmachine1_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine1_row_open <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine1_trccon_ready) begin
+ soc_litedramcore_bankmachine1_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine1_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
+ soc_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine1_trccon_ready) begin
+ soc_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine1_source_source_valid) begin
+ if (soc_litedramcore_bankmachine1_row_opened) begin
+ if (soc_litedramcore_bankmachine1_row_hit) begin
+ soc_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine1_row_close <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ soc_litedramcore_bankmachine1_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ soc_litedramcore_bankmachine1_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ soc_litedramcore_bankmachine1_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine1_trccon_ready) begin
+ soc_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine1_source_source_valid) begin
+ if (soc_litedramcore_bankmachine1_row_opened) begin
+ if (soc_litedramcore_bankmachine1_row_hit) begin
+ soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+assign soc_litedramcore_bankmachine2_sink_valid = soc_litedramcore_bankmachine2_req_valid;
+assign soc_litedramcore_bankmachine2_req_ready = soc_litedramcore_bankmachine2_sink_ready;
+assign soc_litedramcore_bankmachine2_sink_payload_we = soc_litedramcore_bankmachine2_req_we;
+assign soc_litedramcore_bankmachine2_sink_payload_addr = soc_litedramcore_bankmachine2_req_addr;
+assign soc_litedramcore_bankmachine2_sink_sink_valid = soc_litedramcore_bankmachine2_source_valid;
+assign soc_litedramcore_bankmachine2_source_ready = soc_litedramcore_bankmachine2_sink_sink_ready;
+assign soc_litedramcore_bankmachine2_sink_sink_first = soc_litedramcore_bankmachine2_source_first;
+assign soc_litedramcore_bankmachine2_sink_sink_last = soc_litedramcore_bankmachine2_source_last;
+assign soc_litedramcore_bankmachine2_sink_sink_payload_we = soc_litedramcore_bankmachine2_source_payload_we;
+assign soc_litedramcore_bankmachine2_sink_sink_payload_addr = soc_litedramcore_bankmachine2_source_payload_addr;
+assign soc_litedramcore_bankmachine2_source_source_ready = (soc_litedramcore_bankmachine2_req_wdata_ready | soc_litedramcore_bankmachine2_req_rdata_valid);
+assign soc_litedramcore_bankmachine2_req_lock = (soc_litedramcore_bankmachine2_source_valid | soc_litedramcore_bankmachine2_source_source_valid);
+assign soc_litedramcore_bankmachine2_row_hit = (soc_litedramcore_bankmachine2_row == soc_litedramcore_bankmachine2_source_source_payload_addr[20:7]);
assign soc_litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
always @(*) begin
- soc_litedramcore_bankmachine2_cmd_payload_a <= 14'd0;
- if (soc_litedramcore_bankmachine2_row_col_n_addr_sel) begin
- soc_litedramcore_bankmachine2_cmd_payload_a <= soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7];
- end else begin
- soc_litedramcore_bankmachine2_cmd_payload_a <= ((soc_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ soc_litedramcore_bankmachine2_cmd_payload_a <= 14'd0;
+ if (soc_litedramcore_bankmachine2_row_col_n_addr_sel) begin
+ soc_litedramcore_bankmachine2_cmd_payload_a <= soc_litedramcore_bankmachine2_source_source_payload_addr[20:7];
+ end else begin
+ soc_litedramcore_bankmachine2_cmd_payload_a <= ((soc_litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine2_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign soc_litedramcore_bankmachine2_twtpcon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_cmd_payload_is_write);
assign soc_litedramcore_bankmachine2_trccon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_row_open);
assign soc_litedramcore_bankmachine2_trascon_valid = ((soc_litedramcore_bankmachine2_cmd_valid & soc_litedramcore_bankmachine2_cmd_ready) & soc_litedramcore_bankmachine2_row_open);
always @(*) begin
- soc_litedramcore_bankmachine2_auto_precharge <= 1'd0;
- if ((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine2_cmd_buffer_source_valid)) begin
- if ((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7])) begin
- soc_litedramcore_bankmachine2_auto_precharge <= (soc_litedramcore_bankmachine2_row_close == 1'd0);
- end
- end
-end
-assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
-assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
-assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first;
-assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last;
-assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
-assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
-assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
-assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
-assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
-assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
-assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin
- soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce;
- end
-end
-assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
-assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace));
-assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re);
-assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume;
-assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
-assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16);
-assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
-assign soc_litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine2_cmd_buffer_source_valid) | soc_litedramcore_bankmachine2_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine2_next_state <= 4'd0;
- litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
- if (soc_litedramcore_bankmachine2_cmd_ready) begin
- litedramcore_bankmachine2_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine2_trccon_ready) begin
- if (soc_litedramcore_bankmachine2_cmd_ready) begin
- litedramcore_bankmachine2_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~soc_litedramcore_bankmachine2_refresh_req)) begin
- litedramcore_bankmachine2_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine2_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine2_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine2_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine2_next_state <= 1'd0;
- end
- default: begin
- if (soc_litedramcore_bankmachine2_refresh_req) begin
- litedramcore_bankmachine2_next_state <= 3'd4;
- end else begin
- if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine2_row_opened) begin
- if (soc_litedramcore_bankmachine2_row_hit) begin
- if ((soc_litedramcore_bankmachine2_cmd_ready & soc_litedramcore_bankmachine2_auto_precharge)) begin
- litedramcore_bankmachine2_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine2_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine2_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine2_row_open <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine2_trccon_ready) begin
- soc_litedramcore_bankmachine2_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine2_row_close <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- soc_litedramcore_bankmachine2_row_close <= 1'd1;
- end
- 2'd2: begin
- soc_litedramcore_bankmachine2_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- soc_litedramcore_bankmachine2_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine2_row_opened) begin
- if (soc_litedramcore_bankmachine2_row_hit) begin
- soc_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
- soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine2_trccon_ready) begin
- soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
- soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine2_row_opened) begin
- if (soc_litedramcore_bankmachine2_row_hit) begin
- if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine2_trccon_ready) begin
- soc_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
- soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine2_trccon_ready) begin
- soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine2_row_opened) begin
- if (soc_litedramcore_bankmachine2_row_hit) begin
- if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- end else begin
- soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine2_row_opened) begin
- if (soc_litedramcore_bankmachine2_row_hit) begin
- if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- soc_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine2_row_opened) begin
- if (soc_litedramcore_bankmachine2_row_hit) begin
- if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- soc_litedramcore_bankmachine2_req_wdata_ready <= soc_litedramcore_bankmachine2_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine2_row_opened) begin
- if (soc_litedramcore_bankmachine2_row_hit) begin
- if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- end else begin
- soc_litedramcore_bankmachine2_req_rdata_valid <= soc_litedramcore_bankmachine2_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine2_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (soc_litedramcore_bankmachine2_twtpcon_ready) begin
- soc_litedramcore_bankmachine2_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine2_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
- soc_litedramcore_bankmachine2_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine2_trccon_ready) begin
- soc_litedramcore_bankmachine2_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine2_row_opened) begin
- if (soc_litedramcore_bankmachine2_row_hit) begin
- soc_litedramcore_bankmachine2_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine3_req_valid;
-assign soc_litedramcore_bankmachine3_req_ready = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
-assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine3_req_we;
-assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine3_req_addr;
-assign soc_litedramcore_bankmachine3_cmd_buffer_sink_valid = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
-assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine3_cmd_buffer_sink_ready;
-assign soc_litedramcore_bankmachine3_cmd_buffer_sink_first = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
-assign soc_litedramcore_bankmachine3_cmd_buffer_sink_last = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
-assign soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
-assign soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
-assign soc_litedramcore_bankmachine3_cmd_buffer_source_ready = (soc_litedramcore_bankmachine3_req_wdata_ready | soc_litedramcore_bankmachine3_req_rdata_valid);
-assign soc_litedramcore_bankmachine3_req_lock = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine3_cmd_buffer_source_valid);
-assign soc_litedramcore_bankmachine3_row_hit = (soc_litedramcore_bankmachine3_row == soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]);
+ soc_litedramcore_bankmachine2_auto_precharge <= 1'd0;
+ if ((soc_litedramcore_bankmachine2_source_valid & soc_litedramcore_bankmachine2_source_source_valid)) begin
+ if ((soc_litedramcore_bankmachine2_source_payload_addr[20:7] != soc_litedramcore_bankmachine2_source_source_payload_addr[20:7])) begin
+ soc_litedramcore_bankmachine2_auto_precharge <= (soc_litedramcore_bankmachine2_row_close == 1'd0);
+ end
+ end
+end
+assign soc_litedramcore_bankmachine2_syncfifo2_din = {soc_litedramcore_bankmachine2_fifo_in_last, soc_litedramcore_bankmachine2_fifo_in_first, soc_litedramcore_bankmachine2_fifo_in_payload_addr, soc_litedramcore_bankmachine2_fifo_in_payload_we};
+assign {soc_litedramcore_bankmachine2_fifo_out_last, soc_litedramcore_bankmachine2_fifo_out_first, soc_litedramcore_bankmachine2_fifo_out_payload_addr, soc_litedramcore_bankmachine2_fifo_out_payload_we} = soc_litedramcore_bankmachine2_syncfifo2_dout;
+assign {soc_litedramcore_bankmachine2_fifo_out_last, soc_litedramcore_bankmachine2_fifo_out_first, soc_litedramcore_bankmachine2_fifo_out_payload_addr, soc_litedramcore_bankmachine2_fifo_out_payload_we} = soc_litedramcore_bankmachine2_syncfifo2_dout;
+assign {soc_litedramcore_bankmachine2_fifo_out_last, soc_litedramcore_bankmachine2_fifo_out_first, soc_litedramcore_bankmachine2_fifo_out_payload_addr, soc_litedramcore_bankmachine2_fifo_out_payload_we} = soc_litedramcore_bankmachine2_syncfifo2_dout;
+assign {soc_litedramcore_bankmachine2_fifo_out_last, soc_litedramcore_bankmachine2_fifo_out_first, soc_litedramcore_bankmachine2_fifo_out_payload_addr, soc_litedramcore_bankmachine2_fifo_out_payload_we} = soc_litedramcore_bankmachine2_syncfifo2_dout;
+assign soc_litedramcore_bankmachine2_sink_ready = soc_litedramcore_bankmachine2_syncfifo2_writable;
+assign soc_litedramcore_bankmachine2_syncfifo2_we = soc_litedramcore_bankmachine2_sink_valid;
+assign soc_litedramcore_bankmachine2_fifo_in_first = soc_litedramcore_bankmachine2_sink_first;
+assign soc_litedramcore_bankmachine2_fifo_in_last = soc_litedramcore_bankmachine2_sink_last;
+assign soc_litedramcore_bankmachine2_fifo_in_payload_we = soc_litedramcore_bankmachine2_sink_payload_we;
+assign soc_litedramcore_bankmachine2_fifo_in_payload_addr = soc_litedramcore_bankmachine2_sink_payload_addr;
+assign soc_litedramcore_bankmachine2_source_valid = soc_litedramcore_bankmachine2_syncfifo2_readable;
+assign soc_litedramcore_bankmachine2_source_first = soc_litedramcore_bankmachine2_fifo_out_first;
+assign soc_litedramcore_bankmachine2_source_last = soc_litedramcore_bankmachine2_fifo_out_last;
+assign soc_litedramcore_bankmachine2_source_payload_we = soc_litedramcore_bankmachine2_fifo_out_payload_we;
+assign soc_litedramcore_bankmachine2_source_payload_addr = soc_litedramcore_bankmachine2_fifo_out_payload_addr;
+assign soc_litedramcore_bankmachine2_syncfifo2_re = soc_litedramcore_bankmachine2_source_ready;
+always @(*) begin
+ soc_litedramcore_bankmachine2_wrport_adr <= 4'd0;
+ if (soc_litedramcore_bankmachine2_replace) begin
+ soc_litedramcore_bankmachine2_wrport_adr <= (soc_litedramcore_bankmachine2_produce - 1'd1);
+ end else begin
+ soc_litedramcore_bankmachine2_wrport_adr <= soc_litedramcore_bankmachine2_produce;
+ end
+end
+assign soc_litedramcore_bankmachine2_wrport_dat_w = soc_litedramcore_bankmachine2_syncfifo2_din;
+assign soc_litedramcore_bankmachine2_wrport_we = (soc_litedramcore_bankmachine2_syncfifo2_we & (soc_litedramcore_bankmachine2_syncfifo2_writable | soc_litedramcore_bankmachine2_replace));
+assign soc_litedramcore_bankmachine2_do_read = (soc_litedramcore_bankmachine2_syncfifo2_readable & soc_litedramcore_bankmachine2_syncfifo2_re);
+assign soc_litedramcore_bankmachine2_rdport_adr = soc_litedramcore_bankmachine2_consume;
+assign soc_litedramcore_bankmachine2_syncfifo2_dout = soc_litedramcore_bankmachine2_rdport_dat_r;
+assign soc_litedramcore_bankmachine2_syncfifo2_writable = (soc_litedramcore_bankmachine2_level != 5'd16);
+assign soc_litedramcore_bankmachine2_syncfifo2_readable = (soc_litedramcore_bankmachine2_level != 1'd0);
+assign soc_litedramcore_bankmachine2_pipe_valid_sink_ready = ((~soc_litedramcore_bankmachine2_pipe_valid_source_valid) | soc_litedramcore_bankmachine2_pipe_valid_source_ready);
+assign soc_litedramcore_bankmachine2_pipe_valid_sink_valid = soc_litedramcore_bankmachine2_sink_sink_valid;
+assign soc_litedramcore_bankmachine2_sink_sink_ready = soc_litedramcore_bankmachine2_pipe_valid_sink_ready;
+assign soc_litedramcore_bankmachine2_pipe_valid_sink_first = soc_litedramcore_bankmachine2_sink_sink_first;
+assign soc_litedramcore_bankmachine2_pipe_valid_sink_last = soc_litedramcore_bankmachine2_sink_sink_last;
+assign soc_litedramcore_bankmachine2_pipe_valid_sink_payload_we = soc_litedramcore_bankmachine2_sink_sink_payload_we;
+assign soc_litedramcore_bankmachine2_pipe_valid_sink_payload_addr = soc_litedramcore_bankmachine2_sink_sink_payload_addr;
+assign soc_litedramcore_bankmachine2_source_source_valid = soc_litedramcore_bankmachine2_pipe_valid_source_valid;
+assign soc_litedramcore_bankmachine2_pipe_valid_source_ready = soc_litedramcore_bankmachine2_source_source_ready;
+assign soc_litedramcore_bankmachine2_source_source_first = soc_litedramcore_bankmachine2_pipe_valid_source_first;
+assign soc_litedramcore_bankmachine2_source_source_last = soc_litedramcore_bankmachine2_pipe_valid_source_last;
+assign soc_litedramcore_bankmachine2_source_source_payload_we = soc_litedramcore_bankmachine2_pipe_valid_source_payload_we;
+assign soc_litedramcore_bankmachine2_source_source_payload_addr = soc_litedramcore_bankmachine2_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine2_next_state <= 4'd0;
+ litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
+ if (soc_litedramcore_bankmachine2_cmd_ready) begin
+ litedramcore_bankmachine2_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine2_trccon_ready) begin
+ if (soc_litedramcore_bankmachine2_cmd_ready) begin
+ litedramcore_bankmachine2_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~soc_litedramcore_bankmachine2_refresh_req)) begin
+ litedramcore_bankmachine2_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine2_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine2_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine2_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine2_next_state <= 1'd0;
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine2_refresh_req) begin
+ litedramcore_bankmachine2_next_state <= 3'd4;
+ end else begin
+ if (soc_litedramcore_bankmachine2_source_source_valid) begin
+ if (soc_litedramcore_bankmachine2_row_opened) begin
+ if (soc_litedramcore_bankmachine2_row_hit) begin
+ if ((soc_litedramcore_bankmachine2_cmd_ready & soc_litedramcore_bankmachine2_auto_precharge)) begin
+ litedramcore_bankmachine2_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine2_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine2_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine2_source_source_valid) begin
+ if (soc_litedramcore_bankmachine2_row_opened) begin
+ if (soc_litedramcore_bankmachine2_row_hit) begin
+ if (soc_litedramcore_bankmachine2_source_source_payload_we) begin
+ soc_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine2_source_source_valid) begin
+ if (soc_litedramcore_bankmachine2_row_opened) begin
+ if (soc_litedramcore_bankmachine2_row_hit) begin
+ if (soc_litedramcore_bankmachine2_source_source_payload_we) begin
+ soc_litedramcore_bankmachine2_req_wdata_ready <= soc_litedramcore_bankmachine2_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine2_source_source_valid) begin
+ if (soc_litedramcore_bankmachine2_row_opened) begin
+ if (soc_litedramcore_bankmachine2_row_hit) begin
+ if (soc_litedramcore_bankmachine2_source_source_payload_we) begin
+ end else begin
+ soc_litedramcore_bankmachine2_req_rdata_valid <= soc_litedramcore_bankmachine2_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine2_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (soc_litedramcore_bankmachine2_twtpcon_ready) begin
+ soc_litedramcore_bankmachine2_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine2_row_open <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine2_trccon_ready) begin
+ soc_litedramcore_bankmachine2_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine2_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
+ soc_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine2_trccon_ready) begin
+ soc_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine2_source_source_valid) begin
+ if (soc_litedramcore_bankmachine2_row_opened) begin
+ if (soc_litedramcore_bankmachine2_row_hit) begin
+ soc_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine2_row_close <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ soc_litedramcore_bankmachine2_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ soc_litedramcore_bankmachine2_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ soc_litedramcore_bankmachine2_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine2_trccon_ready) begin
+ soc_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine2_source_source_valid) begin
+ if (soc_litedramcore_bankmachine2_row_opened) begin
+ if (soc_litedramcore_bankmachine2_row_hit) begin
+ soc_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
+ soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine2_trccon_ready) begin
+ soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
+ soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine2_source_source_valid) begin
+ if (soc_litedramcore_bankmachine2_row_opened) begin
+ if (soc_litedramcore_bankmachine2_row_hit) begin
+ if (soc_litedramcore_bankmachine2_source_source_payload_we) begin
+ soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
+ soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine2_trccon_ready) begin
+ soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine2_source_source_valid) begin
+ if (soc_litedramcore_bankmachine2_row_opened) begin
+ if (soc_litedramcore_bankmachine2_row_hit) begin
+ if (soc_litedramcore_bankmachine2_source_source_payload_we) begin
+ end else begin
+ soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+assign soc_litedramcore_bankmachine3_sink_valid = soc_litedramcore_bankmachine3_req_valid;
+assign soc_litedramcore_bankmachine3_req_ready = soc_litedramcore_bankmachine3_sink_ready;
+assign soc_litedramcore_bankmachine3_sink_payload_we = soc_litedramcore_bankmachine3_req_we;
+assign soc_litedramcore_bankmachine3_sink_payload_addr = soc_litedramcore_bankmachine3_req_addr;
+assign soc_litedramcore_bankmachine3_sink_sink_valid = soc_litedramcore_bankmachine3_source_valid;
+assign soc_litedramcore_bankmachine3_source_ready = soc_litedramcore_bankmachine3_sink_sink_ready;
+assign soc_litedramcore_bankmachine3_sink_sink_first = soc_litedramcore_bankmachine3_source_first;
+assign soc_litedramcore_bankmachine3_sink_sink_last = soc_litedramcore_bankmachine3_source_last;
+assign soc_litedramcore_bankmachine3_sink_sink_payload_we = soc_litedramcore_bankmachine3_source_payload_we;
+assign soc_litedramcore_bankmachine3_sink_sink_payload_addr = soc_litedramcore_bankmachine3_source_payload_addr;
+assign soc_litedramcore_bankmachine3_source_source_ready = (soc_litedramcore_bankmachine3_req_wdata_ready | soc_litedramcore_bankmachine3_req_rdata_valid);
+assign soc_litedramcore_bankmachine3_req_lock = (soc_litedramcore_bankmachine3_source_valid | soc_litedramcore_bankmachine3_source_source_valid);
+assign soc_litedramcore_bankmachine3_row_hit = (soc_litedramcore_bankmachine3_row == soc_litedramcore_bankmachine3_source_source_payload_addr[20:7]);
assign soc_litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
always @(*) begin
- soc_litedramcore_bankmachine3_cmd_payload_a <= 14'd0;
- if (soc_litedramcore_bankmachine3_row_col_n_addr_sel) begin
- soc_litedramcore_bankmachine3_cmd_payload_a <= soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7];
- end else begin
- soc_litedramcore_bankmachine3_cmd_payload_a <= ((soc_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ soc_litedramcore_bankmachine3_cmd_payload_a <= 14'd0;
+ if (soc_litedramcore_bankmachine3_row_col_n_addr_sel) begin
+ soc_litedramcore_bankmachine3_cmd_payload_a <= soc_litedramcore_bankmachine3_source_source_payload_addr[20:7];
+ end else begin
+ soc_litedramcore_bankmachine3_cmd_payload_a <= ((soc_litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine3_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign soc_litedramcore_bankmachine3_twtpcon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_cmd_payload_is_write);
assign soc_litedramcore_bankmachine3_trccon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_row_open);
assign soc_litedramcore_bankmachine3_trascon_valid = ((soc_litedramcore_bankmachine3_cmd_valid & soc_litedramcore_bankmachine3_cmd_ready) & soc_litedramcore_bankmachine3_row_open);
always @(*) begin
- soc_litedramcore_bankmachine3_auto_precharge <= 1'd0;
- if ((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine3_cmd_buffer_source_valid)) begin
- if ((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7])) begin
- soc_litedramcore_bankmachine3_auto_precharge <= (soc_litedramcore_bankmachine3_row_close == 1'd0);
- end
- end
-end
-assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
-assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
-assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first;
-assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last;
-assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
-assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
-assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
-assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
-assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
-assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
-assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin
- soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce;
- end
-end
-assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
-assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace));
-assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re);
-assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume;
-assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
-assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16);
-assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
-assign soc_litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine3_cmd_buffer_source_valid) | soc_litedramcore_bankmachine3_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine3_next_state <= 4'd0;
- litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
- if (soc_litedramcore_bankmachine3_cmd_ready) begin
- litedramcore_bankmachine3_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine3_trccon_ready) begin
- if (soc_litedramcore_bankmachine3_cmd_ready) begin
- litedramcore_bankmachine3_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~soc_litedramcore_bankmachine3_refresh_req)) begin
- litedramcore_bankmachine3_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine3_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine3_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine3_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine3_next_state <= 1'd0;
- end
- default: begin
- if (soc_litedramcore_bankmachine3_refresh_req) begin
- litedramcore_bankmachine3_next_state <= 3'd4;
- end else begin
- if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine3_row_opened) begin
- if (soc_litedramcore_bankmachine3_row_hit) begin
- if ((soc_litedramcore_bankmachine3_cmd_ready & soc_litedramcore_bankmachine3_auto_precharge)) begin
- litedramcore_bankmachine3_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine3_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine3_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine3_row_open <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine3_trccon_ready) begin
- soc_litedramcore_bankmachine3_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine3_row_close <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- soc_litedramcore_bankmachine3_row_close <= 1'd1;
- end
- 2'd2: begin
- soc_litedramcore_bankmachine3_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- soc_litedramcore_bankmachine3_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine3_row_opened) begin
- if (soc_litedramcore_bankmachine3_row_hit) begin
- soc_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
- soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine3_trccon_ready) begin
- soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
- soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine3_row_opened) begin
- if (soc_litedramcore_bankmachine3_row_hit) begin
- if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine3_trccon_ready) begin
- soc_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
- soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine3_trccon_ready) begin
- soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine3_row_opened) begin
- if (soc_litedramcore_bankmachine3_row_hit) begin
- if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- end else begin
- soc_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine3_row_opened) begin
- if (soc_litedramcore_bankmachine3_row_hit) begin
- if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- soc_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine3_row_opened) begin
- if (soc_litedramcore_bankmachine3_row_hit) begin
- if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- soc_litedramcore_bankmachine3_req_wdata_ready <= soc_litedramcore_bankmachine3_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine3_row_opened) begin
- if (soc_litedramcore_bankmachine3_row_hit) begin
- if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- end else begin
- soc_litedramcore_bankmachine3_req_rdata_valid <= soc_litedramcore_bankmachine3_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine3_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (soc_litedramcore_bankmachine3_twtpcon_ready) begin
- soc_litedramcore_bankmachine3_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine3_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
- soc_litedramcore_bankmachine3_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine3_trccon_ready) begin
- soc_litedramcore_bankmachine3_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine3_row_opened) begin
- if (soc_litedramcore_bankmachine3_row_hit) begin
- soc_litedramcore_bankmachine3_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine4_req_valid;
-assign soc_litedramcore_bankmachine4_req_ready = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
-assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine4_req_we;
-assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine4_req_addr;
-assign soc_litedramcore_bankmachine4_cmd_buffer_sink_valid = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
-assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine4_cmd_buffer_sink_ready;
-assign soc_litedramcore_bankmachine4_cmd_buffer_sink_first = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
-assign soc_litedramcore_bankmachine4_cmd_buffer_sink_last = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
-assign soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
-assign soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
-assign soc_litedramcore_bankmachine4_cmd_buffer_source_ready = (soc_litedramcore_bankmachine4_req_wdata_ready | soc_litedramcore_bankmachine4_req_rdata_valid);
-assign soc_litedramcore_bankmachine4_req_lock = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine4_cmd_buffer_source_valid);
-assign soc_litedramcore_bankmachine4_row_hit = (soc_litedramcore_bankmachine4_row == soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]);
+ soc_litedramcore_bankmachine3_auto_precharge <= 1'd0;
+ if ((soc_litedramcore_bankmachine3_source_valid & soc_litedramcore_bankmachine3_source_source_valid)) begin
+ if ((soc_litedramcore_bankmachine3_source_payload_addr[20:7] != soc_litedramcore_bankmachine3_source_source_payload_addr[20:7])) begin
+ soc_litedramcore_bankmachine3_auto_precharge <= (soc_litedramcore_bankmachine3_row_close == 1'd0);
+ end
+ end
+end
+assign soc_litedramcore_bankmachine3_syncfifo3_din = {soc_litedramcore_bankmachine3_fifo_in_last, soc_litedramcore_bankmachine3_fifo_in_first, soc_litedramcore_bankmachine3_fifo_in_payload_addr, soc_litedramcore_bankmachine3_fifo_in_payload_we};
+assign {soc_litedramcore_bankmachine3_fifo_out_last, soc_litedramcore_bankmachine3_fifo_out_first, soc_litedramcore_bankmachine3_fifo_out_payload_addr, soc_litedramcore_bankmachine3_fifo_out_payload_we} = soc_litedramcore_bankmachine3_syncfifo3_dout;
+assign {soc_litedramcore_bankmachine3_fifo_out_last, soc_litedramcore_bankmachine3_fifo_out_first, soc_litedramcore_bankmachine3_fifo_out_payload_addr, soc_litedramcore_bankmachine3_fifo_out_payload_we} = soc_litedramcore_bankmachine3_syncfifo3_dout;
+assign {soc_litedramcore_bankmachine3_fifo_out_last, soc_litedramcore_bankmachine3_fifo_out_first, soc_litedramcore_bankmachine3_fifo_out_payload_addr, soc_litedramcore_bankmachine3_fifo_out_payload_we} = soc_litedramcore_bankmachine3_syncfifo3_dout;
+assign {soc_litedramcore_bankmachine3_fifo_out_last, soc_litedramcore_bankmachine3_fifo_out_first, soc_litedramcore_bankmachine3_fifo_out_payload_addr, soc_litedramcore_bankmachine3_fifo_out_payload_we} = soc_litedramcore_bankmachine3_syncfifo3_dout;
+assign soc_litedramcore_bankmachine3_sink_ready = soc_litedramcore_bankmachine3_syncfifo3_writable;
+assign soc_litedramcore_bankmachine3_syncfifo3_we = soc_litedramcore_bankmachine3_sink_valid;
+assign soc_litedramcore_bankmachine3_fifo_in_first = soc_litedramcore_bankmachine3_sink_first;
+assign soc_litedramcore_bankmachine3_fifo_in_last = soc_litedramcore_bankmachine3_sink_last;
+assign soc_litedramcore_bankmachine3_fifo_in_payload_we = soc_litedramcore_bankmachine3_sink_payload_we;
+assign soc_litedramcore_bankmachine3_fifo_in_payload_addr = soc_litedramcore_bankmachine3_sink_payload_addr;
+assign soc_litedramcore_bankmachine3_source_valid = soc_litedramcore_bankmachine3_syncfifo3_readable;
+assign soc_litedramcore_bankmachine3_source_first = soc_litedramcore_bankmachine3_fifo_out_first;
+assign soc_litedramcore_bankmachine3_source_last = soc_litedramcore_bankmachine3_fifo_out_last;
+assign soc_litedramcore_bankmachine3_source_payload_we = soc_litedramcore_bankmachine3_fifo_out_payload_we;
+assign soc_litedramcore_bankmachine3_source_payload_addr = soc_litedramcore_bankmachine3_fifo_out_payload_addr;
+assign soc_litedramcore_bankmachine3_syncfifo3_re = soc_litedramcore_bankmachine3_source_ready;
+always @(*) begin
+ soc_litedramcore_bankmachine3_wrport_adr <= 4'd0;
+ if (soc_litedramcore_bankmachine3_replace) begin
+ soc_litedramcore_bankmachine3_wrport_adr <= (soc_litedramcore_bankmachine3_produce - 1'd1);
+ end else begin
+ soc_litedramcore_bankmachine3_wrport_adr <= soc_litedramcore_bankmachine3_produce;
+ end
+end
+assign soc_litedramcore_bankmachine3_wrport_dat_w = soc_litedramcore_bankmachine3_syncfifo3_din;
+assign soc_litedramcore_bankmachine3_wrport_we = (soc_litedramcore_bankmachine3_syncfifo3_we & (soc_litedramcore_bankmachine3_syncfifo3_writable | soc_litedramcore_bankmachine3_replace));
+assign soc_litedramcore_bankmachine3_do_read = (soc_litedramcore_bankmachine3_syncfifo3_readable & soc_litedramcore_bankmachine3_syncfifo3_re);
+assign soc_litedramcore_bankmachine3_rdport_adr = soc_litedramcore_bankmachine3_consume;
+assign soc_litedramcore_bankmachine3_syncfifo3_dout = soc_litedramcore_bankmachine3_rdport_dat_r;
+assign soc_litedramcore_bankmachine3_syncfifo3_writable = (soc_litedramcore_bankmachine3_level != 5'd16);
+assign soc_litedramcore_bankmachine3_syncfifo3_readable = (soc_litedramcore_bankmachine3_level != 1'd0);
+assign soc_litedramcore_bankmachine3_pipe_valid_sink_ready = ((~soc_litedramcore_bankmachine3_pipe_valid_source_valid) | soc_litedramcore_bankmachine3_pipe_valid_source_ready);
+assign soc_litedramcore_bankmachine3_pipe_valid_sink_valid = soc_litedramcore_bankmachine3_sink_sink_valid;
+assign soc_litedramcore_bankmachine3_sink_sink_ready = soc_litedramcore_bankmachine3_pipe_valid_sink_ready;
+assign soc_litedramcore_bankmachine3_pipe_valid_sink_first = soc_litedramcore_bankmachine3_sink_sink_first;
+assign soc_litedramcore_bankmachine3_pipe_valid_sink_last = soc_litedramcore_bankmachine3_sink_sink_last;
+assign soc_litedramcore_bankmachine3_pipe_valid_sink_payload_we = soc_litedramcore_bankmachine3_sink_sink_payload_we;
+assign soc_litedramcore_bankmachine3_pipe_valid_sink_payload_addr = soc_litedramcore_bankmachine3_sink_sink_payload_addr;
+assign soc_litedramcore_bankmachine3_source_source_valid = soc_litedramcore_bankmachine3_pipe_valid_source_valid;
+assign soc_litedramcore_bankmachine3_pipe_valid_source_ready = soc_litedramcore_bankmachine3_source_source_ready;
+assign soc_litedramcore_bankmachine3_source_source_first = soc_litedramcore_bankmachine3_pipe_valid_source_first;
+assign soc_litedramcore_bankmachine3_source_source_last = soc_litedramcore_bankmachine3_pipe_valid_source_last;
+assign soc_litedramcore_bankmachine3_source_source_payload_we = soc_litedramcore_bankmachine3_pipe_valid_source_payload_we;
+assign soc_litedramcore_bankmachine3_source_source_payload_addr = soc_litedramcore_bankmachine3_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine3_next_state <= 4'd0;
+ litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
+ if (soc_litedramcore_bankmachine3_cmd_ready) begin
+ litedramcore_bankmachine3_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine3_trccon_ready) begin
+ if (soc_litedramcore_bankmachine3_cmd_ready) begin
+ litedramcore_bankmachine3_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~soc_litedramcore_bankmachine3_refresh_req)) begin
+ litedramcore_bankmachine3_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine3_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine3_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine3_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine3_next_state <= 1'd0;
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine3_refresh_req) begin
+ litedramcore_bankmachine3_next_state <= 3'd4;
+ end else begin
+ if (soc_litedramcore_bankmachine3_source_source_valid) begin
+ if (soc_litedramcore_bankmachine3_row_opened) begin
+ if (soc_litedramcore_bankmachine3_row_hit) begin
+ if ((soc_litedramcore_bankmachine3_cmd_ready & soc_litedramcore_bankmachine3_auto_precharge)) begin
+ litedramcore_bankmachine3_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine3_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine3_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine3_row_open <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine3_trccon_ready) begin
+ soc_litedramcore_bankmachine3_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine3_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
+ soc_litedramcore_bankmachine3_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine3_trccon_ready) begin
+ soc_litedramcore_bankmachine3_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine3_source_source_valid) begin
+ if (soc_litedramcore_bankmachine3_row_opened) begin
+ if (soc_litedramcore_bankmachine3_row_hit) begin
+ soc_litedramcore_bankmachine3_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine3_row_close <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ soc_litedramcore_bankmachine3_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ soc_litedramcore_bankmachine3_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ soc_litedramcore_bankmachine3_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine3_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (soc_litedramcore_bankmachine3_twtpcon_ready) begin
+ soc_litedramcore_bankmachine3_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine3_trccon_ready) begin
+ soc_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine3_source_source_valid) begin
+ if (soc_litedramcore_bankmachine3_row_opened) begin
+ if (soc_litedramcore_bankmachine3_row_hit) begin
+ soc_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
+ soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine3_trccon_ready) begin
+ soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
+ soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine3_source_source_valid) begin
+ if (soc_litedramcore_bankmachine3_row_opened) begin
+ if (soc_litedramcore_bankmachine3_row_hit) begin
+ if (soc_litedramcore_bankmachine3_source_source_payload_we) begin
+ soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
+ soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine3_trccon_ready) begin
+ soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine3_source_source_valid) begin
+ if (soc_litedramcore_bankmachine3_row_opened) begin
+ if (soc_litedramcore_bankmachine3_row_hit) begin
+ if (soc_litedramcore_bankmachine3_source_source_payload_we) begin
+ end else begin
+ soc_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine3_source_source_valid) begin
+ if (soc_litedramcore_bankmachine3_row_opened) begin
+ if (soc_litedramcore_bankmachine3_row_hit) begin
+ if (soc_litedramcore_bankmachine3_source_source_payload_we) begin
+ soc_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine3_source_source_valid) begin
+ if (soc_litedramcore_bankmachine3_row_opened) begin
+ if (soc_litedramcore_bankmachine3_row_hit) begin
+ if (soc_litedramcore_bankmachine3_source_source_payload_we) begin
+ soc_litedramcore_bankmachine3_req_wdata_ready <= soc_litedramcore_bankmachine3_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine3_source_source_valid) begin
+ if (soc_litedramcore_bankmachine3_row_opened) begin
+ if (soc_litedramcore_bankmachine3_row_hit) begin
+ if (soc_litedramcore_bankmachine3_source_source_payload_we) begin
+ end else begin
+ soc_litedramcore_bankmachine3_req_rdata_valid <= soc_litedramcore_bankmachine3_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+assign soc_litedramcore_bankmachine4_sink_valid = soc_litedramcore_bankmachine4_req_valid;
+assign soc_litedramcore_bankmachine4_req_ready = soc_litedramcore_bankmachine4_sink_ready;
+assign soc_litedramcore_bankmachine4_sink_payload_we = soc_litedramcore_bankmachine4_req_we;
+assign soc_litedramcore_bankmachine4_sink_payload_addr = soc_litedramcore_bankmachine4_req_addr;
+assign soc_litedramcore_bankmachine4_sink_sink_valid = soc_litedramcore_bankmachine4_source_valid;
+assign soc_litedramcore_bankmachine4_source_ready = soc_litedramcore_bankmachine4_sink_sink_ready;
+assign soc_litedramcore_bankmachine4_sink_sink_first = soc_litedramcore_bankmachine4_source_first;
+assign soc_litedramcore_bankmachine4_sink_sink_last = soc_litedramcore_bankmachine4_source_last;
+assign soc_litedramcore_bankmachine4_sink_sink_payload_we = soc_litedramcore_bankmachine4_source_payload_we;
+assign soc_litedramcore_bankmachine4_sink_sink_payload_addr = soc_litedramcore_bankmachine4_source_payload_addr;
+assign soc_litedramcore_bankmachine4_source_source_ready = (soc_litedramcore_bankmachine4_req_wdata_ready | soc_litedramcore_bankmachine4_req_rdata_valid);
+assign soc_litedramcore_bankmachine4_req_lock = (soc_litedramcore_bankmachine4_source_valid | soc_litedramcore_bankmachine4_source_source_valid);
+assign soc_litedramcore_bankmachine4_row_hit = (soc_litedramcore_bankmachine4_row == soc_litedramcore_bankmachine4_source_source_payload_addr[20:7]);
assign soc_litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
always @(*) begin
- soc_litedramcore_bankmachine4_cmd_payload_a <= 14'd0;
- if (soc_litedramcore_bankmachine4_row_col_n_addr_sel) begin
- soc_litedramcore_bankmachine4_cmd_payload_a <= soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7];
- end else begin
- soc_litedramcore_bankmachine4_cmd_payload_a <= ((soc_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ soc_litedramcore_bankmachine4_cmd_payload_a <= 14'd0;
+ if (soc_litedramcore_bankmachine4_row_col_n_addr_sel) begin
+ soc_litedramcore_bankmachine4_cmd_payload_a <= soc_litedramcore_bankmachine4_source_source_payload_addr[20:7];
+ end else begin
+ soc_litedramcore_bankmachine4_cmd_payload_a <= ((soc_litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine4_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign soc_litedramcore_bankmachine4_twtpcon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_cmd_payload_is_write);
assign soc_litedramcore_bankmachine4_trccon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_row_open);
assign soc_litedramcore_bankmachine4_trascon_valid = ((soc_litedramcore_bankmachine4_cmd_valid & soc_litedramcore_bankmachine4_cmd_ready) & soc_litedramcore_bankmachine4_row_open);
always @(*) begin
- soc_litedramcore_bankmachine4_auto_precharge <= 1'd0;
- if ((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine4_cmd_buffer_source_valid)) begin
- if ((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7])) begin
- soc_litedramcore_bankmachine4_auto_precharge <= (soc_litedramcore_bankmachine4_row_close == 1'd0);
- end
- end
-end
-assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
-assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
-assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first;
-assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last;
-assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
-assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
-assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
-assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
-assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
-assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
-assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin
- soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce;
- end
-end
-assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
-assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace));
-assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re);
-assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume;
-assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
-assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16);
-assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
-assign soc_litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine4_cmd_buffer_source_valid) | soc_litedramcore_bankmachine4_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine4_next_state <= 4'd0;
- litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
- if (soc_litedramcore_bankmachine4_cmd_ready) begin
- litedramcore_bankmachine4_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine4_trccon_ready) begin
- if (soc_litedramcore_bankmachine4_cmd_ready) begin
- litedramcore_bankmachine4_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~soc_litedramcore_bankmachine4_refresh_req)) begin
- litedramcore_bankmachine4_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine4_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine4_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine4_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine4_next_state <= 1'd0;
- end
- default: begin
- if (soc_litedramcore_bankmachine4_refresh_req) begin
- litedramcore_bankmachine4_next_state <= 3'd4;
- end else begin
- if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine4_row_opened) begin
- if (soc_litedramcore_bankmachine4_row_hit) begin
- if ((soc_litedramcore_bankmachine4_cmd_ready & soc_litedramcore_bankmachine4_auto_precharge)) begin
- litedramcore_bankmachine4_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine4_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine4_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine4_row_open <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine4_trccon_ready) begin
- soc_litedramcore_bankmachine4_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine4_row_close <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- soc_litedramcore_bankmachine4_row_close <= 1'd1;
- end
- 2'd2: begin
- soc_litedramcore_bankmachine4_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- soc_litedramcore_bankmachine4_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine4_row_opened) begin
- if (soc_litedramcore_bankmachine4_row_hit) begin
- soc_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
- soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine4_trccon_ready) begin
- soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
- soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine4_row_opened) begin
- if (soc_litedramcore_bankmachine4_row_hit) begin
- if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine4_trccon_ready) begin
- soc_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
- soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine4_trccon_ready) begin
- soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine4_row_opened) begin
- if (soc_litedramcore_bankmachine4_row_hit) begin
- if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- end else begin
- soc_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine4_row_opened) begin
- if (soc_litedramcore_bankmachine4_row_hit) begin
- if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- soc_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine4_row_opened) begin
- if (soc_litedramcore_bankmachine4_row_hit) begin
- if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- soc_litedramcore_bankmachine4_req_wdata_ready <= soc_litedramcore_bankmachine4_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine4_row_opened) begin
- if (soc_litedramcore_bankmachine4_row_hit) begin
- if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- end else begin
- soc_litedramcore_bankmachine4_req_rdata_valid <= soc_litedramcore_bankmachine4_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine4_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (soc_litedramcore_bankmachine4_twtpcon_ready) begin
- soc_litedramcore_bankmachine4_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine4_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
- soc_litedramcore_bankmachine4_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine4_trccon_ready) begin
- soc_litedramcore_bankmachine4_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine4_row_opened) begin
- if (soc_litedramcore_bankmachine4_row_hit) begin
- soc_litedramcore_bankmachine4_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine5_req_valid;
-assign soc_litedramcore_bankmachine5_req_ready = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
-assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine5_req_we;
-assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine5_req_addr;
-assign soc_litedramcore_bankmachine5_cmd_buffer_sink_valid = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
-assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine5_cmd_buffer_sink_ready;
-assign soc_litedramcore_bankmachine5_cmd_buffer_sink_first = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
-assign soc_litedramcore_bankmachine5_cmd_buffer_sink_last = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
-assign soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
-assign soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
-assign soc_litedramcore_bankmachine5_cmd_buffer_source_ready = (soc_litedramcore_bankmachine5_req_wdata_ready | soc_litedramcore_bankmachine5_req_rdata_valid);
-assign soc_litedramcore_bankmachine5_req_lock = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine5_cmd_buffer_source_valid);
-assign soc_litedramcore_bankmachine5_row_hit = (soc_litedramcore_bankmachine5_row == soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]);
+ soc_litedramcore_bankmachine4_auto_precharge <= 1'd0;
+ if ((soc_litedramcore_bankmachine4_source_valid & soc_litedramcore_bankmachine4_source_source_valid)) begin
+ if ((soc_litedramcore_bankmachine4_source_payload_addr[20:7] != soc_litedramcore_bankmachine4_source_source_payload_addr[20:7])) begin
+ soc_litedramcore_bankmachine4_auto_precharge <= (soc_litedramcore_bankmachine4_row_close == 1'd0);
+ end
+ end
+end
+assign soc_litedramcore_bankmachine4_syncfifo4_din = {soc_litedramcore_bankmachine4_fifo_in_last, soc_litedramcore_bankmachine4_fifo_in_first, soc_litedramcore_bankmachine4_fifo_in_payload_addr, soc_litedramcore_bankmachine4_fifo_in_payload_we};
+assign {soc_litedramcore_bankmachine4_fifo_out_last, soc_litedramcore_bankmachine4_fifo_out_first, soc_litedramcore_bankmachine4_fifo_out_payload_addr, soc_litedramcore_bankmachine4_fifo_out_payload_we} = soc_litedramcore_bankmachine4_syncfifo4_dout;
+assign {soc_litedramcore_bankmachine4_fifo_out_last, soc_litedramcore_bankmachine4_fifo_out_first, soc_litedramcore_bankmachine4_fifo_out_payload_addr, soc_litedramcore_bankmachine4_fifo_out_payload_we} = soc_litedramcore_bankmachine4_syncfifo4_dout;
+assign {soc_litedramcore_bankmachine4_fifo_out_last, soc_litedramcore_bankmachine4_fifo_out_first, soc_litedramcore_bankmachine4_fifo_out_payload_addr, soc_litedramcore_bankmachine4_fifo_out_payload_we} = soc_litedramcore_bankmachine4_syncfifo4_dout;
+assign {soc_litedramcore_bankmachine4_fifo_out_last, soc_litedramcore_bankmachine4_fifo_out_first, soc_litedramcore_bankmachine4_fifo_out_payload_addr, soc_litedramcore_bankmachine4_fifo_out_payload_we} = soc_litedramcore_bankmachine4_syncfifo4_dout;
+assign soc_litedramcore_bankmachine4_sink_ready = soc_litedramcore_bankmachine4_syncfifo4_writable;
+assign soc_litedramcore_bankmachine4_syncfifo4_we = soc_litedramcore_bankmachine4_sink_valid;
+assign soc_litedramcore_bankmachine4_fifo_in_first = soc_litedramcore_bankmachine4_sink_first;
+assign soc_litedramcore_bankmachine4_fifo_in_last = soc_litedramcore_bankmachine4_sink_last;
+assign soc_litedramcore_bankmachine4_fifo_in_payload_we = soc_litedramcore_bankmachine4_sink_payload_we;
+assign soc_litedramcore_bankmachine4_fifo_in_payload_addr = soc_litedramcore_bankmachine4_sink_payload_addr;
+assign soc_litedramcore_bankmachine4_source_valid = soc_litedramcore_bankmachine4_syncfifo4_readable;
+assign soc_litedramcore_bankmachine4_source_first = soc_litedramcore_bankmachine4_fifo_out_first;
+assign soc_litedramcore_bankmachine4_source_last = soc_litedramcore_bankmachine4_fifo_out_last;
+assign soc_litedramcore_bankmachine4_source_payload_we = soc_litedramcore_bankmachine4_fifo_out_payload_we;
+assign soc_litedramcore_bankmachine4_source_payload_addr = soc_litedramcore_bankmachine4_fifo_out_payload_addr;
+assign soc_litedramcore_bankmachine4_syncfifo4_re = soc_litedramcore_bankmachine4_source_ready;
+always @(*) begin
+ soc_litedramcore_bankmachine4_wrport_adr <= 4'd0;
+ if (soc_litedramcore_bankmachine4_replace) begin
+ soc_litedramcore_bankmachine4_wrport_adr <= (soc_litedramcore_bankmachine4_produce - 1'd1);
+ end else begin
+ soc_litedramcore_bankmachine4_wrport_adr <= soc_litedramcore_bankmachine4_produce;
+ end
+end
+assign soc_litedramcore_bankmachine4_wrport_dat_w = soc_litedramcore_bankmachine4_syncfifo4_din;
+assign soc_litedramcore_bankmachine4_wrport_we = (soc_litedramcore_bankmachine4_syncfifo4_we & (soc_litedramcore_bankmachine4_syncfifo4_writable | soc_litedramcore_bankmachine4_replace));
+assign soc_litedramcore_bankmachine4_do_read = (soc_litedramcore_bankmachine4_syncfifo4_readable & soc_litedramcore_bankmachine4_syncfifo4_re);
+assign soc_litedramcore_bankmachine4_rdport_adr = soc_litedramcore_bankmachine4_consume;
+assign soc_litedramcore_bankmachine4_syncfifo4_dout = soc_litedramcore_bankmachine4_rdport_dat_r;
+assign soc_litedramcore_bankmachine4_syncfifo4_writable = (soc_litedramcore_bankmachine4_level != 5'd16);
+assign soc_litedramcore_bankmachine4_syncfifo4_readable = (soc_litedramcore_bankmachine4_level != 1'd0);
+assign soc_litedramcore_bankmachine4_pipe_valid_sink_ready = ((~soc_litedramcore_bankmachine4_pipe_valid_source_valid) | soc_litedramcore_bankmachine4_pipe_valid_source_ready);
+assign soc_litedramcore_bankmachine4_pipe_valid_sink_valid = soc_litedramcore_bankmachine4_sink_sink_valid;
+assign soc_litedramcore_bankmachine4_sink_sink_ready = soc_litedramcore_bankmachine4_pipe_valid_sink_ready;
+assign soc_litedramcore_bankmachine4_pipe_valid_sink_first = soc_litedramcore_bankmachine4_sink_sink_first;
+assign soc_litedramcore_bankmachine4_pipe_valid_sink_last = soc_litedramcore_bankmachine4_sink_sink_last;
+assign soc_litedramcore_bankmachine4_pipe_valid_sink_payload_we = soc_litedramcore_bankmachine4_sink_sink_payload_we;
+assign soc_litedramcore_bankmachine4_pipe_valid_sink_payload_addr = soc_litedramcore_bankmachine4_sink_sink_payload_addr;
+assign soc_litedramcore_bankmachine4_source_source_valid = soc_litedramcore_bankmachine4_pipe_valid_source_valid;
+assign soc_litedramcore_bankmachine4_pipe_valid_source_ready = soc_litedramcore_bankmachine4_source_source_ready;
+assign soc_litedramcore_bankmachine4_source_source_first = soc_litedramcore_bankmachine4_pipe_valid_source_first;
+assign soc_litedramcore_bankmachine4_source_source_last = soc_litedramcore_bankmachine4_pipe_valid_source_last;
+assign soc_litedramcore_bankmachine4_source_source_payload_we = soc_litedramcore_bankmachine4_pipe_valid_source_payload_we;
+assign soc_litedramcore_bankmachine4_source_source_payload_addr = soc_litedramcore_bankmachine4_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine4_next_state <= 4'd0;
+ litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
+ if (soc_litedramcore_bankmachine4_cmd_ready) begin
+ litedramcore_bankmachine4_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine4_trccon_ready) begin
+ if (soc_litedramcore_bankmachine4_cmd_ready) begin
+ litedramcore_bankmachine4_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~soc_litedramcore_bankmachine4_refresh_req)) begin
+ litedramcore_bankmachine4_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine4_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine4_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine4_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine4_next_state <= 1'd0;
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine4_refresh_req) begin
+ litedramcore_bankmachine4_next_state <= 3'd4;
+ end else begin
+ if (soc_litedramcore_bankmachine4_source_source_valid) begin
+ if (soc_litedramcore_bankmachine4_row_opened) begin
+ if (soc_litedramcore_bankmachine4_row_hit) begin
+ if ((soc_litedramcore_bankmachine4_cmd_ready & soc_litedramcore_bankmachine4_auto_precharge)) begin
+ litedramcore_bankmachine4_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine4_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine4_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine4_trccon_ready) begin
+ soc_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine4_source_source_valid) begin
+ if (soc_litedramcore_bankmachine4_row_opened) begin
+ if (soc_litedramcore_bankmachine4_row_hit) begin
+ soc_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
+ soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine4_trccon_ready) begin
+ soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
+ soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine4_source_source_valid) begin
+ if (soc_litedramcore_bankmachine4_row_opened) begin
+ if (soc_litedramcore_bankmachine4_row_hit) begin
+ if (soc_litedramcore_bankmachine4_source_source_payload_we) begin
+ soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
+ soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine4_trccon_ready) begin
+ soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine4_source_source_valid) begin
+ if (soc_litedramcore_bankmachine4_row_opened) begin
+ if (soc_litedramcore_bankmachine4_row_hit) begin
+ if (soc_litedramcore_bankmachine4_source_source_payload_we) begin
+ end else begin
+ soc_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine4_source_source_valid) begin
+ if (soc_litedramcore_bankmachine4_row_opened) begin
+ if (soc_litedramcore_bankmachine4_row_hit) begin
+ if (soc_litedramcore_bankmachine4_source_source_payload_we) begin
+ soc_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine4_source_source_valid) begin
+ if (soc_litedramcore_bankmachine4_row_opened) begin
+ if (soc_litedramcore_bankmachine4_row_hit) begin
+ if (soc_litedramcore_bankmachine4_source_source_payload_we) begin
+ soc_litedramcore_bankmachine4_req_wdata_ready <= soc_litedramcore_bankmachine4_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine4_source_source_valid) begin
+ if (soc_litedramcore_bankmachine4_row_opened) begin
+ if (soc_litedramcore_bankmachine4_row_hit) begin
+ if (soc_litedramcore_bankmachine4_source_source_payload_we) begin
+ end else begin
+ soc_litedramcore_bankmachine4_req_rdata_valid <= soc_litedramcore_bankmachine4_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine4_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (soc_litedramcore_bankmachine4_twtpcon_ready) begin
+ soc_litedramcore_bankmachine4_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine4_row_open <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine4_trccon_ready) begin
+ soc_litedramcore_bankmachine4_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine4_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
+ soc_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine4_trccon_ready) begin
+ soc_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine4_source_source_valid) begin
+ if (soc_litedramcore_bankmachine4_row_opened) begin
+ if (soc_litedramcore_bankmachine4_row_hit) begin
+ soc_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine4_row_close <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ soc_litedramcore_bankmachine4_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ soc_litedramcore_bankmachine4_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ soc_litedramcore_bankmachine4_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+assign soc_litedramcore_bankmachine5_sink_valid = soc_litedramcore_bankmachine5_req_valid;
+assign soc_litedramcore_bankmachine5_req_ready = soc_litedramcore_bankmachine5_sink_ready;
+assign soc_litedramcore_bankmachine5_sink_payload_we = soc_litedramcore_bankmachine5_req_we;
+assign soc_litedramcore_bankmachine5_sink_payload_addr = soc_litedramcore_bankmachine5_req_addr;
+assign soc_litedramcore_bankmachine5_sink_sink_valid = soc_litedramcore_bankmachine5_source_valid;
+assign soc_litedramcore_bankmachine5_source_ready = soc_litedramcore_bankmachine5_sink_sink_ready;
+assign soc_litedramcore_bankmachine5_sink_sink_first = soc_litedramcore_bankmachine5_source_first;
+assign soc_litedramcore_bankmachine5_sink_sink_last = soc_litedramcore_bankmachine5_source_last;
+assign soc_litedramcore_bankmachine5_sink_sink_payload_we = soc_litedramcore_bankmachine5_source_payload_we;
+assign soc_litedramcore_bankmachine5_sink_sink_payload_addr = soc_litedramcore_bankmachine5_source_payload_addr;
+assign soc_litedramcore_bankmachine5_source_source_ready = (soc_litedramcore_bankmachine5_req_wdata_ready | soc_litedramcore_bankmachine5_req_rdata_valid);
+assign soc_litedramcore_bankmachine5_req_lock = (soc_litedramcore_bankmachine5_source_valid | soc_litedramcore_bankmachine5_source_source_valid);
+assign soc_litedramcore_bankmachine5_row_hit = (soc_litedramcore_bankmachine5_row == soc_litedramcore_bankmachine5_source_source_payload_addr[20:7]);
assign soc_litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
always @(*) begin
- soc_litedramcore_bankmachine5_cmd_payload_a <= 14'd0;
- if (soc_litedramcore_bankmachine5_row_col_n_addr_sel) begin
- soc_litedramcore_bankmachine5_cmd_payload_a <= soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7];
- end else begin
- soc_litedramcore_bankmachine5_cmd_payload_a <= ((soc_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ soc_litedramcore_bankmachine5_cmd_payload_a <= 14'd0;
+ if (soc_litedramcore_bankmachine5_row_col_n_addr_sel) begin
+ soc_litedramcore_bankmachine5_cmd_payload_a <= soc_litedramcore_bankmachine5_source_source_payload_addr[20:7];
+ end else begin
+ soc_litedramcore_bankmachine5_cmd_payload_a <= ((soc_litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine5_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign soc_litedramcore_bankmachine5_twtpcon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_cmd_payload_is_write);
assign soc_litedramcore_bankmachine5_trccon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_row_open);
assign soc_litedramcore_bankmachine5_trascon_valid = ((soc_litedramcore_bankmachine5_cmd_valid & soc_litedramcore_bankmachine5_cmd_ready) & soc_litedramcore_bankmachine5_row_open);
always @(*) begin
- soc_litedramcore_bankmachine5_auto_precharge <= 1'd0;
- if ((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine5_cmd_buffer_source_valid)) begin
- if ((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7])) begin
- soc_litedramcore_bankmachine5_auto_precharge <= (soc_litedramcore_bankmachine5_row_close == 1'd0);
- end
- end
-end
-assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
-assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
-assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first;
-assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last;
-assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
-assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
-assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
-assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
-assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
-assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
-assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin
- soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce;
- end
-end
-assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
-assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace));
-assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re);
-assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume;
-assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
-assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16);
-assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
-assign soc_litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine5_cmd_buffer_source_valid) | soc_litedramcore_bankmachine5_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine5_next_state <= 4'd0;
- litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
- if (soc_litedramcore_bankmachine5_cmd_ready) begin
- litedramcore_bankmachine5_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine5_trccon_ready) begin
- if (soc_litedramcore_bankmachine5_cmd_ready) begin
- litedramcore_bankmachine5_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~soc_litedramcore_bankmachine5_refresh_req)) begin
- litedramcore_bankmachine5_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine5_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine5_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine5_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine5_next_state <= 1'd0;
- end
- default: begin
- if (soc_litedramcore_bankmachine5_refresh_req) begin
- litedramcore_bankmachine5_next_state <= 3'd4;
- end else begin
- if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine5_row_opened) begin
- if (soc_litedramcore_bankmachine5_row_hit) begin
- if ((soc_litedramcore_bankmachine5_cmd_ready & soc_litedramcore_bankmachine5_auto_precharge)) begin
- litedramcore_bankmachine5_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine5_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine5_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine5_row_open <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine5_trccon_ready) begin
- soc_litedramcore_bankmachine5_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine5_row_close <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- soc_litedramcore_bankmachine5_row_close <= 1'd1;
- end
- 2'd2: begin
- soc_litedramcore_bankmachine5_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- soc_litedramcore_bankmachine5_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine5_row_opened) begin
- if (soc_litedramcore_bankmachine5_row_hit) begin
- soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
- soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine5_trccon_ready) begin
- soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
- soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine5_row_opened) begin
- if (soc_litedramcore_bankmachine5_row_hit) begin
- if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine5_trccon_ready) begin
- soc_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
- soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine5_trccon_ready) begin
- soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine5_row_opened) begin
- if (soc_litedramcore_bankmachine5_row_hit) begin
- if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- end else begin
- soc_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine5_row_opened) begin
- if (soc_litedramcore_bankmachine5_row_hit) begin
- if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- soc_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine5_row_opened) begin
- if (soc_litedramcore_bankmachine5_row_hit) begin
- if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- soc_litedramcore_bankmachine5_req_wdata_ready <= soc_litedramcore_bankmachine5_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine5_row_opened) begin
- if (soc_litedramcore_bankmachine5_row_hit) begin
- if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- end else begin
- soc_litedramcore_bankmachine5_req_rdata_valid <= soc_litedramcore_bankmachine5_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine5_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (soc_litedramcore_bankmachine5_twtpcon_ready) begin
- soc_litedramcore_bankmachine5_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine5_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
- soc_litedramcore_bankmachine5_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine5_trccon_ready) begin
- soc_litedramcore_bankmachine5_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine5_row_opened) begin
- if (soc_litedramcore_bankmachine5_row_hit) begin
- soc_litedramcore_bankmachine5_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine6_req_valid;
-assign soc_litedramcore_bankmachine6_req_ready = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
-assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine6_req_we;
-assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine6_req_addr;
-assign soc_litedramcore_bankmachine6_cmd_buffer_sink_valid = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
-assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine6_cmd_buffer_sink_ready;
-assign soc_litedramcore_bankmachine6_cmd_buffer_sink_first = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
-assign soc_litedramcore_bankmachine6_cmd_buffer_sink_last = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
-assign soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
-assign soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
-assign soc_litedramcore_bankmachine6_cmd_buffer_source_ready = (soc_litedramcore_bankmachine6_req_wdata_ready | soc_litedramcore_bankmachine6_req_rdata_valid);
-assign soc_litedramcore_bankmachine6_req_lock = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine6_cmd_buffer_source_valid);
-assign soc_litedramcore_bankmachine6_row_hit = (soc_litedramcore_bankmachine6_row == soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]);
+ soc_litedramcore_bankmachine5_auto_precharge <= 1'd0;
+ if ((soc_litedramcore_bankmachine5_source_valid & soc_litedramcore_bankmachine5_source_source_valid)) begin
+ if ((soc_litedramcore_bankmachine5_source_payload_addr[20:7] != soc_litedramcore_bankmachine5_source_source_payload_addr[20:7])) begin
+ soc_litedramcore_bankmachine5_auto_precharge <= (soc_litedramcore_bankmachine5_row_close == 1'd0);
+ end
+ end
+end
+assign soc_litedramcore_bankmachine5_syncfifo5_din = {soc_litedramcore_bankmachine5_fifo_in_last, soc_litedramcore_bankmachine5_fifo_in_first, soc_litedramcore_bankmachine5_fifo_in_payload_addr, soc_litedramcore_bankmachine5_fifo_in_payload_we};
+assign {soc_litedramcore_bankmachine5_fifo_out_last, soc_litedramcore_bankmachine5_fifo_out_first, soc_litedramcore_bankmachine5_fifo_out_payload_addr, soc_litedramcore_bankmachine5_fifo_out_payload_we} = soc_litedramcore_bankmachine5_syncfifo5_dout;
+assign {soc_litedramcore_bankmachine5_fifo_out_last, soc_litedramcore_bankmachine5_fifo_out_first, soc_litedramcore_bankmachine5_fifo_out_payload_addr, soc_litedramcore_bankmachine5_fifo_out_payload_we} = soc_litedramcore_bankmachine5_syncfifo5_dout;
+assign {soc_litedramcore_bankmachine5_fifo_out_last, soc_litedramcore_bankmachine5_fifo_out_first, soc_litedramcore_bankmachine5_fifo_out_payload_addr, soc_litedramcore_bankmachine5_fifo_out_payload_we} = soc_litedramcore_bankmachine5_syncfifo5_dout;
+assign {soc_litedramcore_bankmachine5_fifo_out_last, soc_litedramcore_bankmachine5_fifo_out_first, soc_litedramcore_bankmachine5_fifo_out_payload_addr, soc_litedramcore_bankmachine5_fifo_out_payload_we} = soc_litedramcore_bankmachine5_syncfifo5_dout;
+assign soc_litedramcore_bankmachine5_sink_ready = soc_litedramcore_bankmachine5_syncfifo5_writable;
+assign soc_litedramcore_bankmachine5_syncfifo5_we = soc_litedramcore_bankmachine5_sink_valid;
+assign soc_litedramcore_bankmachine5_fifo_in_first = soc_litedramcore_bankmachine5_sink_first;
+assign soc_litedramcore_bankmachine5_fifo_in_last = soc_litedramcore_bankmachine5_sink_last;
+assign soc_litedramcore_bankmachine5_fifo_in_payload_we = soc_litedramcore_bankmachine5_sink_payload_we;
+assign soc_litedramcore_bankmachine5_fifo_in_payload_addr = soc_litedramcore_bankmachine5_sink_payload_addr;
+assign soc_litedramcore_bankmachine5_source_valid = soc_litedramcore_bankmachine5_syncfifo5_readable;
+assign soc_litedramcore_bankmachine5_source_first = soc_litedramcore_bankmachine5_fifo_out_first;
+assign soc_litedramcore_bankmachine5_source_last = soc_litedramcore_bankmachine5_fifo_out_last;
+assign soc_litedramcore_bankmachine5_source_payload_we = soc_litedramcore_bankmachine5_fifo_out_payload_we;
+assign soc_litedramcore_bankmachine5_source_payload_addr = soc_litedramcore_bankmachine5_fifo_out_payload_addr;
+assign soc_litedramcore_bankmachine5_syncfifo5_re = soc_litedramcore_bankmachine5_source_ready;
+always @(*) begin
+ soc_litedramcore_bankmachine5_wrport_adr <= 4'd0;
+ if (soc_litedramcore_bankmachine5_replace) begin
+ soc_litedramcore_bankmachine5_wrport_adr <= (soc_litedramcore_bankmachine5_produce - 1'd1);
+ end else begin
+ soc_litedramcore_bankmachine5_wrport_adr <= soc_litedramcore_bankmachine5_produce;
+ end
+end
+assign soc_litedramcore_bankmachine5_wrport_dat_w = soc_litedramcore_bankmachine5_syncfifo5_din;
+assign soc_litedramcore_bankmachine5_wrport_we = (soc_litedramcore_bankmachine5_syncfifo5_we & (soc_litedramcore_bankmachine5_syncfifo5_writable | soc_litedramcore_bankmachine5_replace));
+assign soc_litedramcore_bankmachine5_do_read = (soc_litedramcore_bankmachine5_syncfifo5_readable & soc_litedramcore_bankmachine5_syncfifo5_re);
+assign soc_litedramcore_bankmachine5_rdport_adr = soc_litedramcore_bankmachine5_consume;
+assign soc_litedramcore_bankmachine5_syncfifo5_dout = soc_litedramcore_bankmachine5_rdport_dat_r;
+assign soc_litedramcore_bankmachine5_syncfifo5_writable = (soc_litedramcore_bankmachine5_level != 5'd16);
+assign soc_litedramcore_bankmachine5_syncfifo5_readable = (soc_litedramcore_bankmachine5_level != 1'd0);
+assign soc_litedramcore_bankmachine5_pipe_valid_sink_ready = ((~soc_litedramcore_bankmachine5_pipe_valid_source_valid) | soc_litedramcore_bankmachine5_pipe_valid_source_ready);
+assign soc_litedramcore_bankmachine5_pipe_valid_sink_valid = soc_litedramcore_bankmachine5_sink_sink_valid;
+assign soc_litedramcore_bankmachine5_sink_sink_ready = soc_litedramcore_bankmachine5_pipe_valid_sink_ready;
+assign soc_litedramcore_bankmachine5_pipe_valid_sink_first = soc_litedramcore_bankmachine5_sink_sink_first;
+assign soc_litedramcore_bankmachine5_pipe_valid_sink_last = soc_litedramcore_bankmachine5_sink_sink_last;
+assign soc_litedramcore_bankmachine5_pipe_valid_sink_payload_we = soc_litedramcore_bankmachine5_sink_sink_payload_we;
+assign soc_litedramcore_bankmachine5_pipe_valid_sink_payload_addr = soc_litedramcore_bankmachine5_sink_sink_payload_addr;
+assign soc_litedramcore_bankmachine5_source_source_valid = soc_litedramcore_bankmachine5_pipe_valid_source_valid;
+assign soc_litedramcore_bankmachine5_pipe_valid_source_ready = soc_litedramcore_bankmachine5_source_source_ready;
+assign soc_litedramcore_bankmachine5_source_source_first = soc_litedramcore_bankmachine5_pipe_valid_source_first;
+assign soc_litedramcore_bankmachine5_source_source_last = soc_litedramcore_bankmachine5_pipe_valid_source_last;
+assign soc_litedramcore_bankmachine5_source_source_payload_we = soc_litedramcore_bankmachine5_pipe_valid_source_payload_we;
+assign soc_litedramcore_bankmachine5_source_source_payload_addr = soc_litedramcore_bankmachine5_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine5_next_state <= 4'd0;
+ litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
+ if (soc_litedramcore_bankmachine5_cmd_ready) begin
+ litedramcore_bankmachine5_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine5_trccon_ready) begin
+ if (soc_litedramcore_bankmachine5_cmd_ready) begin
+ litedramcore_bankmachine5_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~soc_litedramcore_bankmachine5_refresh_req)) begin
+ litedramcore_bankmachine5_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine5_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine5_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine5_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine5_next_state <= 1'd0;
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine5_refresh_req) begin
+ litedramcore_bankmachine5_next_state <= 3'd4;
+ end else begin
+ if (soc_litedramcore_bankmachine5_source_source_valid) begin
+ if (soc_litedramcore_bankmachine5_row_opened) begin
+ if (soc_litedramcore_bankmachine5_row_hit) begin
+ if ((soc_litedramcore_bankmachine5_cmd_ready & soc_litedramcore_bankmachine5_auto_precharge)) begin
+ litedramcore_bankmachine5_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine5_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine5_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
+ soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine5_trccon_ready) begin
+ soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
+ soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine5_source_source_valid) begin
+ if (soc_litedramcore_bankmachine5_row_opened) begin
+ if (soc_litedramcore_bankmachine5_row_hit) begin
+ if (soc_litedramcore_bankmachine5_source_source_payload_we) begin
+ soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
+ soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine5_trccon_ready) begin
+ soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine5_source_source_valid) begin
+ if (soc_litedramcore_bankmachine5_row_opened) begin
+ if (soc_litedramcore_bankmachine5_row_hit) begin
+ if (soc_litedramcore_bankmachine5_source_source_payload_we) begin
+ end else begin
+ soc_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine5_source_source_valid) begin
+ if (soc_litedramcore_bankmachine5_row_opened) begin
+ if (soc_litedramcore_bankmachine5_row_hit) begin
+ if (soc_litedramcore_bankmachine5_source_source_payload_we) begin
+ soc_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine5_source_source_valid) begin
+ if (soc_litedramcore_bankmachine5_row_opened) begin
+ if (soc_litedramcore_bankmachine5_row_hit) begin
+ if (soc_litedramcore_bankmachine5_source_source_payload_we) begin
+ soc_litedramcore_bankmachine5_req_wdata_ready <= soc_litedramcore_bankmachine5_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine5_source_source_valid) begin
+ if (soc_litedramcore_bankmachine5_row_opened) begin
+ if (soc_litedramcore_bankmachine5_row_hit) begin
+ if (soc_litedramcore_bankmachine5_source_source_payload_we) begin
+ end else begin
+ soc_litedramcore_bankmachine5_req_rdata_valid <= soc_litedramcore_bankmachine5_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine5_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (soc_litedramcore_bankmachine5_twtpcon_ready) begin
+ soc_litedramcore_bankmachine5_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine5_row_open <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine5_trccon_ready) begin
+ soc_litedramcore_bankmachine5_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine5_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
+ soc_litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine5_trccon_ready) begin
+ soc_litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine5_source_source_valid) begin
+ if (soc_litedramcore_bankmachine5_row_opened) begin
+ if (soc_litedramcore_bankmachine5_row_hit) begin
+ soc_litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine5_row_close <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ soc_litedramcore_bankmachine5_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ soc_litedramcore_bankmachine5_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ soc_litedramcore_bankmachine5_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine5_trccon_ready) begin
+ soc_litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine5_source_source_valid) begin
+ if (soc_litedramcore_bankmachine5_row_opened) begin
+ if (soc_litedramcore_bankmachine5_row_hit) begin
+ soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+assign soc_litedramcore_bankmachine6_sink_valid = soc_litedramcore_bankmachine6_req_valid;
+assign soc_litedramcore_bankmachine6_req_ready = soc_litedramcore_bankmachine6_sink_ready;
+assign soc_litedramcore_bankmachine6_sink_payload_we = soc_litedramcore_bankmachine6_req_we;
+assign soc_litedramcore_bankmachine6_sink_payload_addr = soc_litedramcore_bankmachine6_req_addr;
+assign soc_litedramcore_bankmachine6_sink_sink_valid = soc_litedramcore_bankmachine6_source_valid;
+assign soc_litedramcore_bankmachine6_source_ready = soc_litedramcore_bankmachine6_sink_sink_ready;
+assign soc_litedramcore_bankmachine6_sink_sink_first = soc_litedramcore_bankmachine6_source_first;
+assign soc_litedramcore_bankmachine6_sink_sink_last = soc_litedramcore_bankmachine6_source_last;
+assign soc_litedramcore_bankmachine6_sink_sink_payload_we = soc_litedramcore_bankmachine6_source_payload_we;
+assign soc_litedramcore_bankmachine6_sink_sink_payload_addr = soc_litedramcore_bankmachine6_source_payload_addr;
+assign soc_litedramcore_bankmachine6_source_source_ready = (soc_litedramcore_bankmachine6_req_wdata_ready | soc_litedramcore_bankmachine6_req_rdata_valid);
+assign soc_litedramcore_bankmachine6_req_lock = (soc_litedramcore_bankmachine6_source_valid | soc_litedramcore_bankmachine6_source_source_valid);
+assign soc_litedramcore_bankmachine6_row_hit = (soc_litedramcore_bankmachine6_row == soc_litedramcore_bankmachine6_source_source_payload_addr[20:7]);
assign soc_litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
always @(*) begin
- soc_litedramcore_bankmachine6_cmd_payload_a <= 14'd0;
- if (soc_litedramcore_bankmachine6_row_col_n_addr_sel) begin
- soc_litedramcore_bankmachine6_cmd_payload_a <= soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7];
- end else begin
- soc_litedramcore_bankmachine6_cmd_payload_a <= ((soc_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ soc_litedramcore_bankmachine6_cmd_payload_a <= 14'd0;
+ if (soc_litedramcore_bankmachine6_row_col_n_addr_sel) begin
+ soc_litedramcore_bankmachine6_cmd_payload_a <= soc_litedramcore_bankmachine6_source_source_payload_addr[20:7];
+ end else begin
+ soc_litedramcore_bankmachine6_cmd_payload_a <= ((soc_litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine6_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign soc_litedramcore_bankmachine6_twtpcon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_cmd_payload_is_write);
assign soc_litedramcore_bankmachine6_trccon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_row_open);
assign soc_litedramcore_bankmachine6_trascon_valid = ((soc_litedramcore_bankmachine6_cmd_valid & soc_litedramcore_bankmachine6_cmd_ready) & soc_litedramcore_bankmachine6_row_open);
always @(*) begin
- soc_litedramcore_bankmachine6_auto_precharge <= 1'd0;
- if ((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine6_cmd_buffer_source_valid)) begin
- if ((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7])) begin
- soc_litedramcore_bankmachine6_auto_precharge <= (soc_litedramcore_bankmachine6_row_close == 1'd0);
- end
- end
-end
-assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
-assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
-assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first;
-assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last;
-assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
-assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
-assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
-assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
-assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
-assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
-assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin
- soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce;
- end
-end
-assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
-assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace));
-assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re);
-assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume;
-assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
-assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16);
-assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
-assign soc_litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine6_cmd_buffer_source_valid) | soc_litedramcore_bankmachine6_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine6_next_state <= 4'd0;
- litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
- if (soc_litedramcore_bankmachine6_cmd_ready) begin
- litedramcore_bankmachine6_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine6_trccon_ready) begin
- if (soc_litedramcore_bankmachine6_cmd_ready) begin
- litedramcore_bankmachine6_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~soc_litedramcore_bankmachine6_refresh_req)) begin
- litedramcore_bankmachine6_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine6_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine6_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine6_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine6_next_state <= 1'd0;
- end
- default: begin
- if (soc_litedramcore_bankmachine6_refresh_req) begin
- litedramcore_bankmachine6_next_state <= 3'd4;
- end else begin
- if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine6_row_opened) begin
- if (soc_litedramcore_bankmachine6_row_hit) begin
- if ((soc_litedramcore_bankmachine6_cmd_ready & soc_litedramcore_bankmachine6_auto_precharge)) begin
- litedramcore_bankmachine6_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine6_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine6_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine6_row_open <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine6_trccon_ready) begin
- soc_litedramcore_bankmachine6_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine6_row_close <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- soc_litedramcore_bankmachine6_row_close <= 1'd1;
- end
- 2'd2: begin
- soc_litedramcore_bankmachine6_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- soc_litedramcore_bankmachine6_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine6_row_opened) begin
- if (soc_litedramcore_bankmachine6_row_hit) begin
- soc_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
- soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine6_trccon_ready) begin
- soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
- soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine6_row_opened) begin
- if (soc_litedramcore_bankmachine6_row_hit) begin
- if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine6_trccon_ready) begin
- soc_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
- soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine6_trccon_ready) begin
- soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine6_row_opened) begin
- if (soc_litedramcore_bankmachine6_row_hit) begin
- if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- end else begin
- soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine6_row_opened) begin
- if (soc_litedramcore_bankmachine6_row_hit) begin
- if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- soc_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine6_row_opened) begin
- if (soc_litedramcore_bankmachine6_row_hit) begin
- if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- soc_litedramcore_bankmachine6_req_wdata_ready <= soc_litedramcore_bankmachine6_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine6_row_opened) begin
- if (soc_litedramcore_bankmachine6_row_hit) begin
- if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- end else begin
- soc_litedramcore_bankmachine6_req_rdata_valid <= soc_litedramcore_bankmachine6_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine6_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (soc_litedramcore_bankmachine6_twtpcon_ready) begin
- soc_litedramcore_bankmachine6_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine6_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
- soc_litedramcore_bankmachine6_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine6_trccon_ready) begin
- soc_litedramcore_bankmachine6_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine6_row_opened) begin
- if (soc_litedramcore_bankmachine6_row_hit) begin
- soc_litedramcore_bankmachine6_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = soc_litedramcore_bankmachine7_req_valid;
-assign soc_litedramcore_bankmachine7_req_ready = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
-assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = soc_litedramcore_bankmachine7_req_we;
-assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = soc_litedramcore_bankmachine7_req_addr;
-assign soc_litedramcore_bankmachine7_cmd_buffer_sink_valid = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
-assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = soc_litedramcore_bankmachine7_cmd_buffer_sink_ready;
-assign soc_litedramcore_bankmachine7_cmd_buffer_sink_first = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
-assign soc_litedramcore_bankmachine7_cmd_buffer_sink_last = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
-assign soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
-assign soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
-assign soc_litedramcore_bankmachine7_cmd_buffer_source_ready = (soc_litedramcore_bankmachine7_req_wdata_ready | soc_litedramcore_bankmachine7_req_rdata_valid);
-assign soc_litedramcore_bankmachine7_req_lock = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | soc_litedramcore_bankmachine7_cmd_buffer_source_valid);
-assign soc_litedramcore_bankmachine7_row_hit = (soc_litedramcore_bankmachine7_row == soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]);
+ soc_litedramcore_bankmachine6_auto_precharge <= 1'd0;
+ if ((soc_litedramcore_bankmachine6_source_valid & soc_litedramcore_bankmachine6_source_source_valid)) begin
+ if ((soc_litedramcore_bankmachine6_source_payload_addr[20:7] != soc_litedramcore_bankmachine6_source_source_payload_addr[20:7])) begin
+ soc_litedramcore_bankmachine6_auto_precharge <= (soc_litedramcore_bankmachine6_row_close == 1'd0);
+ end
+ end
+end
+assign soc_litedramcore_bankmachine6_syncfifo6_din = {soc_litedramcore_bankmachine6_fifo_in_last, soc_litedramcore_bankmachine6_fifo_in_first, soc_litedramcore_bankmachine6_fifo_in_payload_addr, soc_litedramcore_bankmachine6_fifo_in_payload_we};
+assign {soc_litedramcore_bankmachine6_fifo_out_last, soc_litedramcore_bankmachine6_fifo_out_first, soc_litedramcore_bankmachine6_fifo_out_payload_addr, soc_litedramcore_bankmachine6_fifo_out_payload_we} = soc_litedramcore_bankmachine6_syncfifo6_dout;
+assign {soc_litedramcore_bankmachine6_fifo_out_last, soc_litedramcore_bankmachine6_fifo_out_first, soc_litedramcore_bankmachine6_fifo_out_payload_addr, soc_litedramcore_bankmachine6_fifo_out_payload_we} = soc_litedramcore_bankmachine6_syncfifo6_dout;
+assign {soc_litedramcore_bankmachine6_fifo_out_last, soc_litedramcore_bankmachine6_fifo_out_first, soc_litedramcore_bankmachine6_fifo_out_payload_addr, soc_litedramcore_bankmachine6_fifo_out_payload_we} = soc_litedramcore_bankmachine6_syncfifo6_dout;
+assign {soc_litedramcore_bankmachine6_fifo_out_last, soc_litedramcore_bankmachine6_fifo_out_first, soc_litedramcore_bankmachine6_fifo_out_payload_addr, soc_litedramcore_bankmachine6_fifo_out_payload_we} = soc_litedramcore_bankmachine6_syncfifo6_dout;
+assign soc_litedramcore_bankmachine6_sink_ready = soc_litedramcore_bankmachine6_syncfifo6_writable;
+assign soc_litedramcore_bankmachine6_syncfifo6_we = soc_litedramcore_bankmachine6_sink_valid;
+assign soc_litedramcore_bankmachine6_fifo_in_first = soc_litedramcore_bankmachine6_sink_first;
+assign soc_litedramcore_bankmachine6_fifo_in_last = soc_litedramcore_bankmachine6_sink_last;
+assign soc_litedramcore_bankmachine6_fifo_in_payload_we = soc_litedramcore_bankmachine6_sink_payload_we;
+assign soc_litedramcore_bankmachine6_fifo_in_payload_addr = soc_litedramcore_bankmachine6_sink_payload_addr;
+assign soc_litedramcore_bankmachine6_source_valid = soc_litedramcore_bankmachine6_syncfifo6_readable;
+assign soc_litedramcore_bankmachine6_source_first = soc_litedramcore_bankmachine6_fifo_out_first;
+assign soc_litedramcore_bankmachine6_source_last = soc_litedramcore_bankmachine6_fifo_out_last;
+assign soc_litedramcore_bankmachine6_source_payload_we = soc_litedramcore_bankmachine6_fifo_out_payload_we;
+assign soc_litedramcore_bankmachine6_source_payload_addr = soc_litedramcore_bankmachine6_fifo_out_payload_addr;
+assign soc_litedramcore_bankmachine6_syncfifo6_re = soc_litedramcore_bankmachine6_source_ready;
+always @(*) begin
+ soc_litedramcore_bankmachine6_wrport_adr <= 4'd0;
+ if (soc_litedramcore_bankmachine6_replace) begin
+ soc_litedramcore_bankmachine6_wrport_adr <= (soc_litedramcore_bankmachine6_produce - 1'd1);
+ end else begin
+ soc_litedramcore_bankmachine6_wrport_adr <= soc_litedramcore_bankmachine6_produce;
+ end
+end
+assign soc_litedramcore_bankmachine6_wrport_dat_w = soc_litedramcore_bankmachine6_syncfifo6_din;
+assign soc_litedramcore_bankmachine6_wrport_we = (soc_litedramcore_bankmachine6_syncfifo6_we & (soc_litedramcore_bankmachine6_syncfifo6_writable | soc_litedramcore_bankmachine6_replace));
+assign soc_litedramcore_bankmachine6_do_read = (soc_litedramcore_bankmachine6_syncfifo6_readable & soc_litedramcore_bankmachine6_syncfifo6_re);
+assign soc_litedramcore_bankmachine6_rdport_adr = soc_litedramcore_bankmachine6_consume;
+assign soc_litedramcore_bankmachine6_syncfifo6_dout = soc_litedramcore_bankmachine6_rdport_dat_r;
+assign soc_litedramcore_bankmachine6_syncfifo6_writable = (soc_litedramcore_bankmachine6_level != 5'd16);
+assign soc_litedramcore_bankmachine6_syncfifo6_readable = (soc_litedramcore_bankmachine6_level != 1'd0);
+assign soc_litedramcore_bankmachine6_pipe_valid_sink_ready = ((~soc_litedramcore_bankmachine6_pipe_valid_source_valid) | soc_litedramcore_bankmachine6_pipe_valid_source_ready);
+assign soc_litedramcore_bankmachine6_pipe_valid_sink_valid = soc_litedramcore_bankmachine6_sink_sink_valid;
+assign soc_litedramcore_bankmachine6_sink_sink_ready = soc_litedramcore_bankmachine6_pipe_valid_sink_ready;
+assign soc_litedramcore_bankmachine6_pipe_valid_sink_first = soc_litedramcore_bankmachine6_sink_sink_first;
+assign soc_litedramcore_bankmachine6_pipe_valid_sink_last = soc_litedramcore_bankmachine6_sink_sink_last;
+assign soc_litedramcore_bankmachine6_pipe_valid_sink_payload_we = soc_litedramcore_bankmachine6_sink_sink_payload_we;
+assign soc_litedramcore_bankmachine6_pipe_valid_sink_payload_addr = soc_litedramcore_bankmachine6_sink_sink_payload_addr;
+assign soc_litedramcore_bankmachine6_source_source_valid = soc_litedramcore_bankmachine6_pipe_valid_source_valid;
+assign soc_litedramcore_bankmachine6_pipe_valid_source_ready = soc_litedramcore_bankmachine6_source_source_ready;
+assign soc_litedramcore_bankmachine6_source_source_first = soc_litedramcore_bankmachine6_pipe_valid_source_first;
+assign soc_litedramcore_bankmachine6_source_source_last = soc_litedramcore_bankmachine6_pipe_valid_source_last;
+assign soc_litedramcore_bankmachine6_source_source_payload_we = soc_litedramcore_bankmachine6_pipe_valid_source_payload_we;
+assign soc_litedramcore_bankmachine6_source_source_payload_addr = soc_litedramcore_bankmachine6_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine6_next_state <= 4'd0;
+ litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
+ if (soc_litedramcore_bankmachine6_cmd_ready) begin
+ litedramcore_bankmachine6_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine6_trccon_ready) begin
+ if (soc_litedramcore_bankmachine6_cmd_ready) begin
+ litedramcore_bankmachine6_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~soc_litedramcore_bankmachine6_refresh_req)) begin
+ litedramcore_bankmachine6_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine6_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine6_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine6_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine6_next_state <= 1'd0;
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine6_refresh_req) begin
+ litedramcore_bankmachine6_next_state <= 3'd4;
+ end else begin
+ if (soc_litedramcore_bankmachine6_source_source_valid) begin
+ if (soc_litedramcore_bankmachine6_row_opened) begin
+ if (soc_litedramcore_bankmachine6_row_hit) begin
+ if ((soc_litedramcore_bankmachine6_cmd_ready & soc_litedramcore_bankmachine6_auto_precharge)) begin
+ litedramcore_bankmachine6_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine6_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine6_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine6_source_source_valid) begin
+ if (soc_litedramcore_bankmachine6_row_opened) begin
+ if (soc_litedramcore_bankmachine6_row_hit) begin
+ if (soc_litedramcore_bankmachine6_source_source_payload_we) begin
+ soc_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine6_source_source_valid) begin
+ if (soc_litedramcore_bankmachine6_row_opened) begin
+ if (soc_litedramcore_bankmachine6_row_hit) begin
+ if (soc_litedramcore_bankmachine6_source_source_payload_we) begin
+ soc_litedramcore_bankmachine6_req_wdata_ready <= soc_litedramcore_bankmachine6_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine6_source_source_valid) begin
+ if (soc_litedramcore_bankmachine6_row_opened) begin
+ if (soc_litedramcore_bankmachine6_row_hit) begin
+ if (soc_litedramcore_bankmachine6_source_source_payload_we) begin
+ end else begin
+ soc_litedramcore_bankmachine6_req_rdata_valid <= soc_litedramcore_bankmachine6_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine6_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (soc_litedramcore_bankmachine6_twtpcon_ready) begin
+ soc_litedramcore_bankmachine6_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine6_row_open <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine6_trccon_ready) begin
+ soc_litedramcore_bankmachine6_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine6_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
+ soc_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine6_trccon_ready) begin
+ soc_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine6_source_source_valid) begin
+ if (soc_litedramcore_bankmachine6_row_opened) begin
+ if (soc_litedramcore_bankmachine6_row_hit) begin
+ soc_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine6_row_close <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ soc_litedramcore_bankmachine6_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ soc_litedramcore_bankmachine6_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ soc_litedramcore_bankmachine6_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine6_trccon_ready) begin
+ soc_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine6_source_source_valid) begin
+ if (soc_litedramcore_bankmachine6_row_opened) begin
+ if (soc_litedramcore_bankmachine6_row_hit) begin
+ soc_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
+ soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine6_trccon_ready) begin
+ soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
+ soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine6_source_source_valid) begin
+ if (soc_litedramcore_bankmachine6_row_opened) begin
+ if (soc_litedramcore_bankmachine6_row_hit) begin
+ if (soc_litedramcore_bankmachine6_source_source_payload_we) begin
+ soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
+ soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine6_trccon_ready) begin
+ soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine6_source_source_valid) begin
+ if (soc_litedramcore_bankmachine6_row_opened) begin
+ if (soc_litedramcore_bankmachine6_row_hit) begin
+ if (soc_litedramcore_bankmachine6_source_source_payload_we) begin
+ end else begin
+ soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+assign soc_litedramcore_bankmachine7_sink_valid = soc_litedramcore_bankmachine7_req_valid;
+assign soc_litedramcore_bankmachine7_req_ready = soc_litedramcore_bankmachine7_sink_ready;
+assign soc_litedramcore_bankmachine7_sink_payload_we = soc_litedramcore_bankmachine7_req_we;
+assign soc_litedramcore_bankmachine7_sink_payload_addr = soc_litedramcore_bankmachine7_req_addr;
+assign soc_litedramcore_bankmachine7_sink_sink_valid = soc_litedramcore_bankmachine7_source_valid;
+assign soc_litedramcore_bankmachine7_source_ready = soc_litedramcore_bankmachine7_sink_sink_ready;
+assign soc_litedramcore_bankmachine7_sink_sink_first = soc_litedramcore_bankmachine7_source_first;
+assign soc_litedramcore_bankmachine7_sink_sink_last = soc_litedramcore_bankmachine7_source_last;
+assign soc_litedramcore_bankmachine7_sink_sink_payload_we = soc_litedramcore_bankmachine7_source_payload_we;
+assign soc_litedramcore_bankmachine7_sink_sink_payload_addr = soc_litedramcore_bankmachine7_source_payload_addr;
+assign soc_litedramcore_bankmachine7_source_source_ready = (soc_litedramcore_bankmachine7_req_wdata_ready | soc_litedramcore_bankmachine7_req_rdata_valid);
+assign soc_litedramcore_bankmachine7_req_lock = (soc_litedramcore_bankmachine7_source_valid | soc_litedramcore_bankmachine7_source_source_valid);
+assign soc_litedramcore_bankmachine7_row_hit = (soc_litedramcore_bankmachine7_row == soc_litedramcore_bankmachine7_source_source_payload_addr[20:7]);
assign soc_litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
always @(*) begin
- soc_litedramcore_bankmachine7_cmd_payload_a <= 14'd0;
- if (soc_litedramcore_bankmachine7_row_col_n_addr_sel) begin
- soc_litedramcore_bankmachine7_cmd_payload_a <= soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7];
- end else begin
- soc_litedramcore_bankmachine7_cmd_payload_a <= ((soc_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ soc_litedramcore_bankmachine7_cmd_payload_a <= 14'd0;
+ if (soc_litedramcore_bankmachine7_row_col_n_addr_sel) begin
+ soc_litedramcore_bankmachine7_cmd_payload_a <= soc_litedramcore_bankmachine7_source_source_payload_addr[20:7];
+ end else begin
+ soc_litedramcore_bankmachine7_cmd_payload_a <= ((soc_litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {soc_litedramcore_bankmachine7_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign soc_litedramcore_bankmachine7_twtpcon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_cmd_payload_is_write);
assign soc_litedramcore_bankmachine7_trccon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_row_open);
assign soc_litedramcore_bankmachine7_trascon_valid = ((soc_litedramcore_bankmachine7_cmd_valid & soc_litedramcore_bankmachine7_cmd_ready) & soc_litedramcore_bankmachine7_row_open);
always @(*) begin
- soc_litedramcore_bankmachine7_auto_precharge <= 1'd0;
- if ((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & soc_litedramcore_bankmachine7_cmd_buffer_source_valid)) begin
- if ((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[20:7] != soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7])) begin
- soc_litedramcore_bankmachine7_auto_precharge <= (soc_litedramcore_bankmachine7_row_close == 1'd0);
- end
- end
-end
-assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
-assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
-assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first;
-assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last;
-assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
-assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
-assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
-assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
-assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
-assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
-assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin
- soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce;
- end
-end
-assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
-assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace));
-assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re);
-assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume;
-assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
-assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16);
-assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
-assign soc_litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~soc_litedramcore_bankmachine7_cmd_buffer_source_valid) | soc_litedramcore_bankmachine7_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine7_next_state <= 4'd0;
- litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
- if (soc_litedramcore_bankmachine7_cmd_ready) begin
- litedramcore_bankmachine7_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine7_trccon_ready) begin
- if (soc_litedramcore_bankmachine7_cmd_ready) begin
- litedramcore_bankmachine7_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~soc_litedramcore_bankmachine7_refresh_req)) begin
- litedramcore_bankmachine7_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine7_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine7_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine7_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine7_next_state <= 1'd0;
- end
- default: begin
- if (soc_litedramcore_bankmachine7_refresh_req) begin
- litedramcore_bankmachine7_next_state <= 3'd4;
- end else begin
- if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine7_row_opened) begin
- if (soc_litedramcore_bankmachine7_row_hit) begin
- if ((soc_litedramcore_bankmachine7_cmd_ready & soc_litedramcore_bankmachine7_auto_precharge)) begin
- litedramcore_bankmachine7_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine7_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine7_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine7_row_open <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine7_trccon_ready) begin
- soc_litedramcore_bankmachine7_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine7_row_close <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- soc_litedramcore_bankmachine7_row_close <= 1'd1;
- end
- 2'd2: begin
- soc_litedramcore_bankmachine7_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- soc_litedramcore_bankmachine7_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine7_row_opened) begin
- if (soc_litedramcore_bankmachine7_row_hit) begin
- soc_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
- soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine7_trccon_ready) begin
- soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
- soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine7_row_opened) begin
- if (soc_litedramcore_bankmachine7_row_hit) begin
- if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine7_trccon_ready) begin
- soc_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
- soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine7_trccon_ready) begin
- soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine7_row_opened) begin
- if (soc_litedramcore_bankmachine7_row_hit) begin
- if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- end else begin
- soc_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine7_row_opened) begin
- if (soc_litedramcore_bankmachine7_row_hit) begin
- if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- soc_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine7_row_opened) begin
- if (soc_litedramcore_bankmachine7_row_hit) begin
- if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- soc_litedramcore_bankmachine7_req_wdata_ready <= soc_litedramcore_bankmachine7_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine7_row_opened) begin
- if (soc_litedramcore_bankmachine7_row_hit) begin
- if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- end else begin
- soc_litedramcore_bankmachine7_req_rdata_valid <= soc_litedramcore_bankmachine7_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine7_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (soc_litedramcore_bankmachine7_twtpcon_ready) begin
- soc_litedramcore_bankmachine7_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_bankmachine7_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
- soc_litedramcore_bankmachine7_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (soc_litedramcore_bankmachine7_trccon_ready) begin
- soc_litedramcore_bankmachine7_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (soc_litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (soc_litedramcore_bankmachine7_row_opened) begin
- if (soc_litedramcore_bankmachine7_row_hit) begin
- soc_litedramcore_bankmachine7_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
+ soc_litedramcore_bankmachine7_auto_precharge <= 1'd0;
+ if ((soc_litedramcore_bankmachine7_source_valid & soc_litedramcore_bankmachine7_source_source_valid)) begin
+ if ((soc_litedramcore_bankmachine7_source_payload_addr[20:7] != soc_litedramcore_bankmachine7_source_source_payload_addr[20:7])) begin
+ soc_litedramcore_bankmachine7_auto_precharge <= (soc_litedramcore_bankmachine7_row_close == 1'd0);
+ end
+ end
+end
+assign soc_litedramcore_bankmachine7_syncfifo7_din = {soc_litedramcore_bankmachine7_fifo_in_last, soc_litedramcore_bankmachine7_fifo_in_first, soc_litedramcore_bankmachine7_fifo_in_payload_addr, soc_litedramcore_bankmachine7_fifo_in_payload_we};
+assign {soc_litedramcore_bankmachine7_fifo_out_last, soc_litedramcore_bankmachine7_fifo_out_first, soc_litedramcore_bankmachine7_fifo_out_payload_addr, soc_litedramcore_bankmachine7_fifo_out_payload_we} = soc_litedramcore_bankmachine7_syncfifo7_dout;
+assign {soc_litedramcore_bankmachine7_fifo_out_last, soc_litedramcore_bankmachine7_fifo_out_first, soc_litedramcore_bankmachine7_fifo_out_payload_addr, soc_litedramcore_bankmachine7_fifo_out_payload_we} = soc_litedramcore_bankmachine7_syncfifo7_dout;
+assign {soc_litedramcore_bankmachine7_fifo_out_last, soc_litedramcore_bankmachine7_fifo_out_first, soc_litedramcore_bankmachine7_fifo_out_payload_addr, soc_litedramcore_bankmachine7_fifo_out_payload_we} = soc_litedramcore_bankmachine7_syncfifo7_dout;
+assign {soc_litedramcore_bankmachine7_fifo_out_last, soc_litedramcore_bankmachine7_fifo_out_first, soc_litedramcore_bankmachine7_fifo_out_payload_addr, soc_litedramcore_bankmachine7_fifo_out_payload_we} = soc_litedramcore_bankmachine7_syncfifo7_dout;
+assign soc_litedramcore_bankmachine7_sink_ready = soc_litedramcore_bankmachine7_syncfifo7_writable;
+assign soc_litedramcore_bankmachine7_syncfifo7_we = soc_litedramcore_bankmachine7_sink_valid;
+assign soc_litedramcore_bankmachine7_fifo_in_first = soc_litedramcore_bankmachine7_sink_first;
+assign soc_litedramcore_bankmachine7_fifo_in_last = soc_litedramcore_bankmachine7_sink_last;
+assign soc_litedramcore_bankmachine7_fifo_in_payload_we = soc_litedramcore_bankmachine7_sink_payload_we;
+assign soc_litedramcore_bankmachine7_fifo_in_payload_addr = soc_litedramcore_bankmachine7_sink_payload_addr;
+assign soc_litedramcore_bankmachine7_source_valid = soc_litedramcore_bankmachine7_syncfifo7_readable;
+assign soc_litedramcore_bankmachine7_source_first = soc_litedramcore_bankmachine7_fifo_out_first;
+assign soc_litedramcore_bankmachine7_source_last = soc_litedramcore_bankmachine7_fifo_out_last;
+assign soc_litedramcore_bankmachine7_source_payload_we = soc_litedramcore_bankmachine7_fifo_out_payload_we;
+assign soc_litedramcore_bankmachine7_source_payload_addr = soc_litedramcore_bankmachine7_fifo_out_payload_addr;
+assign soc_litedramcore_bankmachine7_syncfifo7_re = soc_litedramcore_bankmachine7_source_ready;
+always @(*) begin
+ soc_litedramcore_bankmachine7_wrport_adr <= 4'd0;
+ if (soc_litedramcore_bankmachine7_replace) begin
+ soc_litedramcore_bankmachine7_wrport_adr <= (soc_litedramcore_bankmachine7_produce - 1'd1);
+ end else begin
+ soc_litedramcore_bankmachine7_wrport_adr <= soc_litedramcore_bankmachine7_produce;
+ end
+end
+assign soc_litedramcore_bankmachine7_wrport_dat_w = soc_litedramcore_bankmachine7_syncfifo7_din;
+assign soc_litedramcore_bankmachine7_wrport_we = (soc_litedramcore_bankmachine7_syncfifo7_we & (soc_litedramcore_bankmachine7_syncfifo7_writable | soc_litedramcore_bankmachine7_replace));
+assign soc_litedramcore_bankmachine7_do_read = (soc_litedramcore_bankmachine7_syncfifo7_readable & soc_litedramcore_bankmachine7_syncfifo7_re);
+assign soc_litedramcore_bankmachine7_rdport_adr = soc_litedramcore_bankmachine7_consume;
+assign soc_litedramcore_bankmachine7_syncfifo7_dout = soc_litedramcore_bankmachine7_rdport_dat_r;
+assign soc_litedramcore_bankmachine7_syncfifo7_writable = (soc_litedramcore_bankmachine7_level != 5'd16);
+assign soc_litedramcore_bankmachine7_syncfifo7_readable = (soc_litedramcore_bankmachine7_level != 1'd0);
+assign soc_litedramcore_bankmachine7_pipe_valid_sink_ready = ((~soc_litedramcore_bankmachine7_pipe_valid_source_valid) | soc_litedramcore_bankmachine7_pipe_valid_source_ready);
+assign soc_litedramcore_bankmachine7_pipe_valid_sink_valid = soc_litedramcore_bankmachine7_sink_sink_valid;
+assign soc_litedramcore_bankmachine7_sink_sink_ready = soc_litedramcore_bankmachine7_pipe_valid_sink_ready;
+assign soc_litedramcore_bankmachine7_pipe_valid_sink_first = soc_litedramcore_bankmachine7_sink_sink_first;
+assign soc_litedramcore_bankmachine7_pipe_valid_sink_last = soc_litedramcore_bankmachine7_sink_sink_last;
+assign soc_litedramcore_bankmachine7_pipe_valid_sink_payload_we = soc_litedramcore_bankmachine7_sink_sink_payload_we;
+assign soc_litedramcore_bankmachine7_pipe_valid_sink_payload_addr = soc_litedramcore_bankmachine7_sink_sink_payload_addr;
+assign soc_litedramcore_bankmachine7_source_source_valid = soc_litedramcore_bankmachine7_pipe_valid_source_valid;
+assign soc_litedramcore_bankmachine7_pipe_valid_source_ready = soc_litedramcore_bankmachine7_source_source_ready;
+assign soc_litedramcore_bankmachine7_source_source_first = soc_litedramcore_bankmachine7_pipe_valid_source_first;
+assign soc_litedramcore_bankmachine7_source_source_last = soc_litedramcore_bankmachine7_pipe_valid_source_last;
+assign soc_litedramcore_bankmachine7_source_source_payload_we = soc_litedramcore_bankmachine7_pipe_valid_source_payload_we;
+assign soc_litedramcore_bankmachine7_source_source_payload_addr = soc_litedramcore_bankmachine7_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine7_next_state <= 4'd0;
+ litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
+ if (soc_litedramcore_bankmachine7_cmd_ready) begin
+ litedramcore_bankmachine7_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine7_trccon_ready) begin
+ if (soc_litedramcore_bankmachine7_cmd_ready) begin
+ litedramcore_bankmachine7_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~soc_litedramcore_bankmachine7_refresh_req)) begin
+ litedramcore_bankmachine7_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine7_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine7_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine7_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine7_next_state <= 1'd0;
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine7_refresh_req) begin
+ litedramcore_bankmachine7_next_state <= 3'd4;
+ end else begin
+ if (soc_litedramcore_bankmachine7_source_source_valid) begin
+ if (soc_litedramcore_bankmachine7_row_opened) begin
+ if (soc_litedramcore_bankmachine7_row_hit) begin
+ if ((soc_litedramcore_bankmachine7_cmd_ready & soc_litedramcore_bankmachine7_auto_precharge)) begin
+ litedramcore_bankmachine7_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine7_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine7_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine7_row_open <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine7_trccon_ready) begin
+ soc_litedramcore_bankmachine7_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine7_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
+ soc_litedramcore_bankmachine7_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine7_trccon_ready) begin
+ soc_litedramcore_bankmachine7_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine7_source_source_valid) begin
+ if (soc_litedramcore_bankmachine7_row_opened) begin
+ if (soc_litedramcore_bankmachine7_row_hit) begin
+ soc_litedramcore_bankmachine7_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine7_row_close <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ soc_litedramcore_bankmachine7_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ soc_litedramcore_bankmachine7_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ soc_litedramcore_bankmachine7_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine7_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (soc_litedramcore_bankmachine7_twtpcon_ready) begin
+ soc_litedramcore_bankmachine7_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine7_trccon_ready) begin
+ soc_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine7_source_source_valid) begin
+ if (soc_litedramcore_bankmachine7_row_opened) begin
+ if (soc_litedramcore_bankmachine7_row_hit) begin
+ soc_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
+ soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine7_trccon_ready) begin
+ soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
+ soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine7_source_source_valid) begin
+ if (soc_litedramcore_bankmachine7_row_opened) begin
+ if (soc_litedramcore_bankmachine7_row_hit) begin
+ if (soc_litedramcore_bankmachine7_source_source_payload_we) begin
+ soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
+ soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (soc_litedramcore_bankmachine7_trccon_ready) begin
+ soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine7_source_source_valid) begin
+ if (soc_litedramcore_bankmachine7_row_opened) begin
+ if (soc_litedramcore_bankmachine7_row_hit) begin
+ if (soc_litedramcore_bankmachine7_source_source_payload_we) begin
+ end else begin
+ soc_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine7_source_source_valid) begin
+ if (soc_litedramcore_bankmachine7_row_opened) begin
+ if (soc_litedramcore_bankmachine7_row_hit) begin
+ if (soc_litedramcore_bankmachine7_source_source_payload_we) begin
+ soc_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine7_source_source_valid) begin
+ if (soc_litedramcore_bankmachine7_row_opened) begin
+ if (soc_litedramcore_bankmachine7_row_hit) begin
+ if (soc_litedramcore_bankmachine7_source_source_payload_we) begin
+ soc_litedramcore_bankmachine7_req_wdata_ready <= soc_litedramcore_bankmachine7_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (soc_litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (soc_litedramcore_bankmachine7_source_source_valid) begin
+ if (soc_litedramcore_bankmachine7_row_opened) begin
+ if (soc_litedramcore_bankmachine7_row_hit) begin
+ if (soc_litedramcore_bankmachine7_source_source_payload_we) begin
+ end else begin
+ soc_litedramcore_bankmachine7_req_rdata_valid <= soc_litedramcore_bankmachine7_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
end
assign soc_litedramcore_trrdcon_valid = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & ((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we)));
assign soc_litedramcore_tfawcon_valid = ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & ((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we)));
assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we);
assign {soc_litedramcore_dfi_p3_wrdata_mask, soc_litedramcore_dfi_p2_wrdata_mask, soc_litedramcore_dfi_p1_wrdata_mask, soc_litedramcore_dfi_p0_wrdata_mask} = (~soc_litedramcore_interface_wdata_we);
always @(*) begin
- soc_litedramcore_choose_cmd_valids <= 8'd0;
- soc_litedramcore_choose_cmd_valids[0] <= (soc_litedramcore_bankmachine0_cmd_valid & (((soc_litedramcore_bankmachine0_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine0_cmd_payload_ras & (~soc_litedramcore_bankmachine0_cmd_payload_cas)) & (~soc_litedramcore_bankmachine0_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine0_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine0_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
- soc_litedramcore_choose_cmd_valids[1] <= (soc_litedramcore_bankmachine1_cmd_valid & (((soc_litedramcore_bankmachine1_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine1_cmd_payload_ras & (~soc_litedramcore_bankmachine1_cmd_payload_cas)) & (~soc_litedramcore_bankmachine1_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine1_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine1_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
- soc_litedramcore_choose_cmd_valids[2] <= (soc_litedramcore_bankmachine2_cmd_valid & (((soc_litedramcore_bankmachine2_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine2_cmd_payload_ras & (~soc_litedramcore_bankmachine2_cmd_payload_cas)) & (~soc_litedramcore_bankmachine2_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine2_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine2_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
- soc_litedramcore_choose_cmd_valids[3] <= (soc_litedramcore_bankmachine3_cmd_valid & (((soc_litedramcore_bankmachine3_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine3_cmd_payload_ras & (~soc_litedramcore_bankmachine3_cmd_payload_cas)) & (~soc_litedramcore_bankmachine3_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine3_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine3_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
- soc_litedramcore_choose_cmd_valids[4] <= (soc_litedramcore_bankmachine4_cmd_valid & (((soc_litedramcore_bankmachine4_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine4_cmd_payload_ras & (~soc_litedramcore_bankmachine4_cmd_payload_cas)) & (~soc_litedramcore_bankmachine4_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine4_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine4_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
- soc_litedramcore_choose_cmd_valids[5] <= (soc_litedramcore_bankmachine5_cmd_valid & (((soc_litedramcore_bankmachine5_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine5_cmd_payload_ras & (~soc_litedramcore_bankmachine5_cmd_payload_cas)) & (~soc_litedramcore_bankmachine5_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine5_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine5_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
- soc_litedramcore_choose_cmd_valids[6] <= (soc_litedramcore_bankmachine6_cmd_valid & (((soc_litedramcore_bankmachine6_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine6_cmd_payload_ras & (~soc_litedramcore_bankmachine6_cmd_payload_cas)) & (~soc_litedramcore_bankmachine6_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine6_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine6_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
- soc_litedramcore_choose_cmd_valids[7] <= (soc_litedramcore_bankmachine7_cmd_valid & (((soc_litedramcore_bankmachine7_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine7_cmd_payload_ras & (~soc_litedramcore_bankmachine7_cmd_payload_cas)) & (~soc_litedramcore_bankmachine7_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine7_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine7_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
+ soc_litedramcore_choose_cmd_valids <= 8'd0;
+ soc_litedramcore_choose_cmd_valids[0] <= (soc_litedramcore_bankmachine0_cmd_valid & (((soc_litedramcore_bankmachine0_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine0_cmd_payload_ras & (~soc_litedramcore_bankmachine0_cmd_payload_cas)) & (~soc_litedramcore_bankmachine0_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine0_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine0_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
+ soc_litedramcore_choose_cmd_valids[1] <= (soc_litedramcore_bankmachine1_cmd_valid & (((soc_litedramcore_bankmachine1_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine1_cmd_payload_ras & (~soc_litedramcore_bankmachine1_cmd_payload_cas)) & (~soc_litedramcore_bankmachine1_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine1_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine1_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
+ soc_litedramcore_choose_cmd_valids[2] <= (soc_litedramcore_bankmachine2_cmd_valid & (((soc_litedramcore_bankmachine2_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine2_cmd_payload_ras & (~soc_litedramcore_bankmachine2_cmd_payload_cas)) & (~soc_litedramcore_bankmachine2_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine2_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine2_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
+ soc_litedramcore_choose_cmd_valids[3] <= (soc_litedramcore_bankmachine3_cmd_valid & (((soc_litedramcore_bankmachine3_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine3_cmd_payload_ras & (~soc_litedramcore_bankmachine3_cmd_payload_cas)) & (~soc_litedramcore_bankmachine3_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine3_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine3_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
+ soc_litedramcore_choose_cmd_valids[4] <= (soc_litedramcore_bankmachine4_cmd_valid & (((soc_litedramcore_bankmachine4_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine4_cmd_payload_ras & (~soc_litedramcore_bankmachine4_cmd_payload_cas)) & (~soc_litedramcore_bankmachine4_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine4_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine4_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
+ soc_litedramcore_choose_cmd_valids[5] <= (soc_litedramcore_bankmachine5_cmd_valid & (((soc_litedramcore_bankmachine5_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine5_cmd_payload_ras & (~soc_litedramcore_bankmachine5_cmd_payload_cas)) & (~soc_litedramcore_bankmachine5_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine5_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine5_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
+ soc_litedramcore_choose_cmd_valids[6] <= (soc_litedramcore_bankmachine6_cmd_valid & (((soc_litedramcore_bankmachine6_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine6_cmd_payload_ras & (~soc_litedramcore_bankmachine6_cmd_payload_cas)) & (~soc_litedramcore_bankmachine6_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine6_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine6_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
+ soc_litedramcore_choose_cmd_valids[7] <= (soc_litedramcore_bankmachine7_cmd_valid & (((soc_litedramcore_bankmachine7_cmd_payload_is_cmd & soc_litedramcore_choose_cmd_want_cmds) & ((~((soc_litedramcore_bankmachine7_cmd_payload_ras & (~soc_litedramcore_bankmachine7_cmd_payload_cas)) & (~soc_litedramcore_bankmachine7_cmd_payload_we))) | soc_litedramcore_choose_cmd_want_activates)) | ((soc_litedramcore_bankmachine7_cmd_payload_is_read == soc_litedramcore_choose_cmd_want_reads) & (soc_litedramcore_bankmachine7_cmd_payload_is_write == soc_litedramcore_choose_cmd_want_writes))));
end
assign soc_litedramcore_choose_cmd_request = soc_litedramcore_choose_cmd_valids;
assign soc_litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0;
assign soc_litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4;
assign soc_litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5;
always @(*) begin
- soc_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
- if (soc_litedramcore_choose_cmd_cmd_valid) begin
- soc_litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0;
- end
+ soc_litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
+ if (soc_litedramcore_choose_cmd_cmd_valid) begin
+ soc_litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0;
+ end
end
always @(*) begin
- soc_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
- if (soc_litedramcore_choose_cmd_cmd_valid) begin
- soc_litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1;
- end
+ soc_litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
+ if (soc_litedramcore_choose_cmd_cmd_valid) begin
+ soc_litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1;
+ end
end
always @(*) begin
- soc_litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
- if (soc_litedramcore_choose_cmd_cmd_valid) begin
- soc_litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2;
- end
+ soc_litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
+ if (soc_litedramcore_choose_cmd_cmd_valid) begin
+ soc_litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2;
+ end
end
always @(*) begin
- soc_litedramcore_bankmachine0_cmd_ready <= 1'd0;
- if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 1'd0))) begin
- soc_litedramcore_bankmachine0_cmd_ready <= 1'd1;
- end
- if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 1'd0))) begin
- soc_litedramcore_bankmachine0_cmd_ready <= 1'd1;
- end
+ soc_litedramcore_bankmachine0_cmd_ready <= 1'd0;
+ if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 1'd0))) begin
+ soc_litedramcore_bankmachine0_cmd_ready <= 1'd1;
+ end
+ if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 1'd0))) begin
+ soc_litedramcore_bankmachine0_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- soc_litedramcore_bankmachine1_cmd_ready <= 1'd0;
- if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 1'd1))) begin
- soc_litedramcore_bankmachine1_cmd_ready <= 1'd1;
- end
- if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 1'd1))) begin
- soc_litedramcore_bankmachine1_cmd_ready <= 1'd1;
- end
+ soc_litedramcore_bankmachine1_cmd_ready <= 1'd0;
+ if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 1'd1))) begin
+ soc_litedramcore_bankmachine1_cmd_ready <= 1'd1;
+ end
+ if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 1'd1))) begin
+ soc_litedramcore_bankmachine1_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- soc_litedramcore_bankmachine2_cmd_ready <= 1'd0;
- if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 2'd2))) begin
- soc_litedramcore_bankmachine2_cmd_ready <= 1'd1;
- end
- if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 2'd2))) begin
- soc_litedramcore_bankmachine2_cmd_ready <= 1'd1;
- end
+ soc_litedramcore_bankmachine2_cmd_ready <= 1'd0;
+ if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 2'd2))) begin
+ soc_litedramcore_bankmachine2_cmd_ready <= 1'd1;
+ end
+ if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 2'd2))) begin
+ soc_litedramcore_bankmachine2_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- soc_litedramcore_bankmachine3_cmd_ready <= 1'd0;
- if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 2'd3))) begin
- soc_litedramcore_bankmachine3_cmd_ready <= 1'd1;
- end
- if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 2'd3))) begin
- soc_litedramcore_bankmachine3_cmd_ready <= 1'd1;
- end
+ soc_litedramcore_bankmachine3_cmd_ready <= 1'd0;
+ if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 2'd3))) begin
+ soc_litedramcore_bankmachine3_cmd_ready <= 1'd1;
+ end
+ if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 2'd3))) begin
+ soc_litedramcore_bankmachine3_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- soc_litedramcore_bankmachine4_cmd_ready <= 1'd0;
- if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd4))) begin
- soc_litedramcore_bankmachine4_cmd_ready <= 1'd1;
- end
- if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd4))) begin
- soc_litedramcore_bankmachine4_cmd_ready <= 1'd1;
- end
+ soc_litedramcore_bankmachine4_cmd_ready <= 1'd0;
+ if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd4))) begin
+ soc_litedramcore_bankmachine4_cmd_ready <= 1'd1;
+ end
+ if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd4))) begin
+ soc_litedramcore_bankmachine4_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- soc_litedramcore_bankmachine5_cmd_ready <= 1'd0;
- if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd5))) begin
- soc_litedramcore_bankmachine5_cmd_ready <= 1'd1;
- end
- if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd5))) begin
- soc_litedramcore_bankmachine5_cmd_ready <= 1'd1;
- end
+ soc_litedramcore_bankmachine5_cmd_ready <= 1'd0;
+ if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd5))) begin
+ soc_litedramcore_bankmachine5_cmd_ready <= 1'd1;
+ end
+ if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd5))) begin
+ soc_litedramcore_bankmachine5_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- soc_litedramcore_bankmachine6_cmd_ready <= 1'd0;
- if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd6))) begin
- soc_litedramcore_bankmachine6_cmd_ready <= 1'd1;
- end
- if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd6))) begin
- soc_litedramcore_bankmachine6_cmd_ready <= 1'd1;
- end
+ soc_litedramcore_bankmachine6_cmd_ready <= 1'd0;
+ if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd6))) begin
+ soc_litedramcore_bankmachine6_cmd_ready <= 1'd1;
+ end
+ if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd6))) begin
+ soc_litedramcore_bankmachine6_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- soc_litedramcore_bankmachine7_cmd_ready <= 1'd0;
- if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd7))) begin
- soc_litedramcore_bankmachine7_cmd_ready <= 1'd1;
- end
- if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd7))) begin
- soc_litedramcore_bankmachine7_cmd_ready <= 1'd1;
- end
+ soc_litedramcore_bankmachine7_cmd_ready <= 1'd0;
+ if (((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & (soc_litedramcore_choose_cmd_grant == 3'd7))) begin
+ soc_litedramcore_bankmachine7_cmd_ready <= 1'd1;
+ end
+ if (((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & (soc_litedramcore_choose_req_grant == 3'd7))) begin
+ soc_litedramcore_bankmachine7_cmd_ready <= 1'd1;
+ end
end
assign soc_litedramcore_choose_cmd_ce = (soc_litedramcore_choose_cmd_cmd_ready | (~soc_litedramcore_choose_cmd_cmd_valid));
always @(*) begin
- soc_litedramcore_choose_req_valids <= 8'd0;
- soc_litedramcore_choose_req_valids[0] <= (soc_litedramcore_bankmachine0_cmd_valid & (((soc_litedramcore_bankmachine0_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine0_cmd_payload_ras & (~soc_litedramcore_bankmachine0_cmd_payload_cas)) & (~soc_litedramcore_bankmachine0_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine0_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine0_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
- soc_litedramcore_choose_req_valids[1] <= (soc_litedramcore_bankmachine1_cmd_valid & (((soc_litedramcore_bankmachine1_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine1_cmd_payload_ras & (~soc_litedramcore_bankmachine1_cmd_payload_cas)) & (~soc_litedramcore_bankmachine1_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine1_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine1_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
- soc_litedramcore_choose_req_valids[2] <= (soc_litedramcore_bankmachine2_cmd_valid & (((soc_litedramcore_bankmachine2_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine2_cmd_payload_ras & (~soc_litedramcore_bankmachine2_cmd_payload_cas)) & (~soc_litedramcore_bankmachine2_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine2_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine2_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
- soc_litedramcore_choose_req_valids[3] <= (soc_litedramcore_bankmachine3_cmd_valid & (((soc_litedramcore_bankmachine3_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine3_cmd_payload_ras & (~soc_litedramcore_bankmachine3_cmd_payload_cas)) & (~soc_litedramcore_bankmachine3_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine3_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine3_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
- soc_litedramcore_choose_req_valids[4] <= (soc_litedramcore_bankmachine4_cmd_valid & (((soc_litedramcore_bankmachine4_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine4_cmd_payload_ras & (~soc_litedramcore_bankmachine4_cmd_payload_cas)) & (~soc_litedramcore_bankmachine4_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine4_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine4_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
- soc_litedramcore_choose_req_valids[5] <= (soc_litedramcore_bankmachine5_cmd_valid & (((soc_litedramcore_bankmachine5_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine5_cmd_payload_ras & (~soc_litedramcore_bankmachine5_cmd_payload_cas)) & (~soc_litedramcore_bankmachine5_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine5_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine5_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
- soc_litedramcore_choose_req_valids[6] <= (soc_litedramcore_bankmachine6_cmd_valid & (((soc_litedramcore_bankmachine6_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine6_cmd_payload_ras & (~soc_litedramcore_bankmachine6_cmd_payload_cas)) & (~soc_litedramcore_bankmachine6_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine6_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine6_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
- soc_litedramcore_choose_req_valids[7] <= (soc_litedramcore_bankmachine7_cmd_valid & (((soc_litedramcore_bankmachine7_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine7_cmd_payload_ras & (~soc_litedramcore_bankmachine7_cmd_payload_cas)) & (~soc_litedramcore_bankmachine7_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine7_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine7_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
+ soc_litedramcore_choose_req_valids <= 8'd0;
+ soc_litedramcore_choose_req_valids[0] <= (soc_litedramcore_bankmachine0_cmd_valid & (((soc_litedramcore_bankmachine0_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine0_cmd_payload_ras & (~soc_litedramcore_bankmachine0_cmd_payload_cas)) & (~soc_litedramcore_bankmachine0_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine0_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine0_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
+ soc_litedramcore_choose_req_valids[1] <= (soc_litedramcore_bankmachine1_cmd_valid & (((soc_litedramcore_bankmachine1_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine1_cmd_payload_ras & (~soc_litedramcore_bankmachine1_cmd_payload_cas)) & (~soc_litedramcore_bankmachine1_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine1_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine1_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
+ soc_litedramcore_choose_req_valids[2] <= (soc_litedramcore_bankmachine2_cmd_valid & (((soc_litedramcore_bankmachine2_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine2_cmd_payload_ras & (~soc_litedramcore_bankmachine2_cmd_payload_cas)) & (~soc_litedramcore_bankmachine2_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine2_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine2_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
+ soc_litedramcore_choose_req_valids[3] <= (soc_litedramcore_bankmachine3_cmd_valid & (((soc_litedramcore_bankmachine3_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine3_cmd_payload_ras & (~soc_litedramcore_bankmachine3_cmd_payload_cas)) & (~soc_litedramcore_bankmachine3_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine3_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine3_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
+ soc_litedramcore_choose_req_valids[4] <= (soc_litedramcore_bankmachine4_cmd_valid & (((soc_litedramcore_bankmachine4_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine4_cmd_payload_ras & (~soc_litedramcore_bankmachine4_cmd_payload_cas)) & (~soc_litedramcore_bankmachine4_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine4_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine4_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
+ soc_litedramcore_choose_req_valids[5] <= (soc_litedramcore_bankmachine5_cmd_valid & (((soc_litedramcore_bankmachine5_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine5_cmd_payload_ras & (~soc_litedramcore_bankmachine5_cmd_payload_cas)) & (~soc_litedramcore_bankmachine5_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine5_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine5_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
+ soc_litedramcore_choose_req_valids[6] <= (soc_litedramcore_bankmachine6_cmd_valid & (((soc_litedramcore_bankmachine6_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine6_cmd_payload_ras & (~soc_litedramcore_bankmachine6_cmd_payload_cas)) & (~soc_litedramcore_bankmachine6_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine6_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine6_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
+ soc_litedramcore_choose_req_valids[7] <= (soc_litedramcore_bankmachine7_cmd_valid & (((soc_litedramcore_bankmachine7_cmd_payload_is_cmd & soc_litedramcore_choose_req_want_cmds) & ((~((soc_litedramcore_bankmachine7_cmd_payload_ras & (~soc_litedramcore_bankmachine7_cmd_payload_cas)) & (~soc_litedramcore_bankmachine7_cmd_payload_we))) | soc_litedramcore_choose_req_want_activates)) | ((soc_litedramcore_bankmachine7_cmd_payload_is_read == soc_litedramcore_choose_req_want_reads) & (soc_litedramcore_bankmachine7_cmd_payload_is_write == soc_litedramcore_choose_req_want_writes))));
end
assign soc_litedramcore_choose_req_request = soc_litedramcore_choose_req_valids;
assign soc_litedramcore_choose_req_cmd_valid = rhs_array_muxed6;
assign soc_litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10;
assign soc_litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11;
always @(*) begin
- soc_litedramcore_choose_req_cmd_payload_cas <= 1'd0;
- if (soc_litedramcore_choose_req_cmd_valid) begin
- soc_litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3;
- end
+ soc_litedramcore_choose_req_cmd_payload_cas <= 1'd0;
+ if (soc_litedramcore_choose_req_cmd_valid) begin
+ soc_litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3;
+ end
end
always @(*) begin
- soc_litedramcore_choose_req_cmd_payload_ras <= 1'd0;
- if (soc_litedramcore_choose_req_cmd_valid) begin
- soc_litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4;
- end
+ soc_litedramcore_choose_req_cmd_payload_ras <= 1'd0;
+ if (soc_litedramcore_choose_req_cmd_valid) begin
+ soc_litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4;
+ end
end
always @(*) begin
- soc_litedramcore_choose_req_cmd_payload_we <= 1'd0;
- if (soc_litedramcore_choose_req_cmd_valid) begin
- soc_litedramcore_choose_req_cmd_payload_we <= t_array_muxed5;
- end
+ soc_litedramcore_choose_req_cmd_payload_we <= 1'd0;
+ if (soc_litedramcore_choose_req_cmd_valid) begin
+ soc_litedramcore_choose_req_cmd_payload_we <= t_array_muxed5;
+ end
end
assign soc_litedramcore_choose_req_ce = (soc_litedramcore_choose_req_cmd_ready | (~soc_litedramcore_choose_req_cmd_valid));
assign soc_litedramcore_dfi_p0_reset_n = 1'd1;
assign soc_litedramcore_dfi_p3_odt = {1{soc_litedramcore_steerer7}};
assign soc_litedramcore_tfawcon_count = ((((soc_litedramcore_tfawcon_window[0] + soc_litedramcore_tfawcon_window[1]) + soc_litedramcore_tfawcon_window[2]) + soc_litedramcore_tfawcon_window[3]) + soc_litedramcore_tfawcon_window[4]);
always @(*) begin
- litedramcore_multiplexer_next_state <= 4'd0;
- litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- if (soc_litedramcore_read_available) begin
- if (((~soc_litedramcore_write_available) | soc_litedramcore_max_time1)) begin
- litedramcore_multiplexer_next_state <= 2'd3;
- end
- end
- if (soc_litedramcore_go_to_refresh) begin
- litedramcore_multiplexer_next_state <= 2'd2;
- end
- end
- 2'd2: begin
- if (soc_litedramcore_cmd_last) begin
- litedramcore_multiplexer_next_state <= 1'd0;
- end
- end
- 2'd3: begin
- if (soc_litedramcore_twtrcon_ready) begin
- litedramcore_multiplexer_next_state <= 1'd0;
- end
- end
- 3'd4: begin
- litedramcore_multiplexer_next_state <= 3'd5;
- end
- 3'd5: begin
- litedramcore_multiplexer_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_multiplexer_next_state <= 3'd7;
- end
- 3'd7: begin
- litedramcore_multiplexer_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_multiplexer_next_state <= 4'd9;
- end
- 4'd9: begin
- litedramcore_multiplexer_next_state <= 4'd10;
- end
- 4'd10: begin
- litedramcore_multiplexer_next_state <= 1'd1;
- end
- default: begin
- if (soc_litedramcore_write_available) begin
- if (((~soc_litedramcore_read_available) | soc_litedramcore_max_time0)) begin
- litedramcore_multiplexer_next_state <= 3'd4;
- end
- end
- if (soc_litedramcore_go_to_refresh) begin
- litedramcore_multiplexer_next_state <= 2'd2;
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_choose_req_cmd_ready <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- if (1'd0) begin
- soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed));
- end else begin
- soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- if (1'd0) begin
- soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed));
- end else begin
- soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed;
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_en1 <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- soc_litedramcore_en1 <= 1'd1;
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_steerer_sel0 <= 2'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- soc_litedramcore_steerer_sel0 <= 1'd0;
- if (1'd0) begin
- soc_litedramcore_steerer_sel0 <= 2'd2;
- end
- if (1'd0) begin
- soc_litedramcore_steerer_sel0 <= 1'd1;
- end
- end
- 2'd2: begin
- soc_litedramcore_steerer_sel0 <= 2'd3;
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- soc_litedramcore_steerer_sel0 <= 1'd0;
- if (1'd0) begin
- soc_litedramcore_steerer_sel0 <= 2'd2;
- end
- if (1'd0) begin
- soc_litedramcore_steerer_sel0 <= 1'd1;
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_steerer_sel1 <= 2'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- soc_litedramcore_steerer_sel1 <= 1'd0;
- if (1'd0) begin
- soc_litedramcore_steerer_sel1 <= 2'd2;
- end
- if (1'd0) begin
- soc_litedramcore_steerer_sel1 <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- soc_litedramcore_steerer_sel1 <= 1'd0;
- if (1'd0) begin
- soc_litedramcore_steerer_sel1 <= 2'd2;
- end
- if (1'd1) begin
- soc_litedramcore_steerer_sel1 <= 1'd1;
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_steerer_sel2 <= 2'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- soc_litedramcore_steerer_sel2 <= 1'd0;
- if (1'd0) begin
- soc_litedramcore_steerer_sel2 <= 2'd2;
- end
- if (1'd1) begin
- soc_litedramcore_steerer_sel2 <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- soc_litedramcore_steerer_sel2 <= 1'd0;
- if (1'd1) begin
- soc_litedramcore_steerer_sel2 <= 2'd2;
- end
- if (1'd0) begin
- soc_litedramcore_steerer_sel2 <= 1'd1;
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_choose_cmd_want_activates <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- if (1'd0) begin
- end else begin
- soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- if (1'd0) begin
- end else begin
- soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed;
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_steerer_sel3 <= 2'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- soc_litedramcore_steerer_sel3 <= 1'd0;
- if (1'd1) begin
- soc_litedramcore_steerer_sel3 <= 2'd2;
- end
- if (1'd0) begin
- soc_litedramcore_steerer_sel3 <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- soc_litedramcore_steerer_sel3 <= 1'd0;
- if (1'd0) begin
- soc_litedramcore_steerer_sel3 <= 2'd2;
- end
- if (1'd0) begin
- soc_litedramcore_steerer_sel3 <= 1'd1;
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_en0 <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- soc_litedramcore_en0 <= 1'd1;
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_cmd_ready <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- end
- 2'd2: begin
- soc_litedramcore_cmd_ready <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_choose_cmd_cmd_ready <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- if (1'd0) begin
- end else begin
- soc_litedramcore_choose_cmd_cmd_ready <= ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed);
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- if (1'd0) begin
- end else begin
- soc_litedramcore_choose_cmd_cmd_ready <= ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed);
- end
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_choose_req_want_reads <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- soc_litedramcore_choose_req_want_reads <= 1'd1;
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_choose_req_want_writes <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- soc_litedramcore_choose_req_want_writes <= 1'd1;
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- end
- endcase
+ litedramcore_multiplexer_next_state <= 4'd0;
+ litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ if (soc_litedramcore_read_available) begin
+ if (((~soc_litedramcore_write_available) | soc_litedramcore_max_time1)) begin
+ litedramcore_multiplexer_next_state <= 2'd3;
+ end
+ end
+ if (soc_litedramcore_go_to_refresh) begin
+ litedramcore_multiplexer_next_state <= 2'd2;
+ end
+ end
+ 2'd2: begin
+ if (soc_litedramcore_cmd_last) begin
+ litedramcore_multiplexer_next_state <= 1'd0;
+ end
+ end
+ 2'd3: begin
+ if (soc_litedramcore_twtrcon_ready) begin
+ litedramcore_multiplexer_next_state <= 1'd0;
+ end
+ end
+ 3'd4: begin
+ litedramcore_multiplexer_next_state <= 3'd5;
+ end
+ 3'd5: begin
+ litedramcore_multiplexer_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_multiplexer_next_state <= 3'd7;
+ end
+ 3'd7: begin
+ litedramcore_multiplexer_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_multiplexer_next_state <= 4'd9;
+ end
+ 4'd9: begin
+ litedramcore_multiplexer_next_state <= 4'd10;
+ end
+ 4'd10: begin
+ litedramcore_multiplexer_next_state <= 1'd1;
+ end
+ default: begin
+ if (soc_litedramcore_write_available) begin
+ if (((~soc_litedramcore_read_available) | soc_litedramcore_max_time0)) begin
+ litedramcore_multiplexer_next_state <= 3'd4;
+ end
+ end
+ if (soc_litedramcore_go_to_refresh) begin
+ litedramcore_multiplexer_next_state <= 2'd2;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_choose_req_cmd_ready <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ if (1'd0) begin
+ soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed));
+ end else begin
+ soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ if (1'd0) begin
+ soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed));
+ end else begin
+ soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_en1 <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ soc_litedramcore_en1 <= 1'd1;
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_steerer_sel0 <= 2'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ soc_litedramcore_steerer_sel0 <= 1'd0;
+ if (1'd0) begin
+ soc_litedramcore_steerer_sel0 <= 2'd2;
+ end
+ if (1'd0) begin
+ soc_litedramcore_steerer_sel0 <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ soc_litedramcore_steerer_sel0 <= 2'd3;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ soc_litedramcore_steerer_sel0 <= 1'd0;
+ if (1'd0) begin
+ soc_litedramcore_steerer_sel0 <= 2'd2;
+ end
+ if (1'd0) begin
+ soc_litedramcore_steerer_sel0 <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_steerer_sel1 <= 2'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ soc_litedramcore_steerer_sel1 <= 1'd0;
+ if (1'd0) begin
+ soc_litedramcore_steerer_sel1 <= 2'd2;
+ end
+ if (1'd0) begin
+ soc_litedramcore_steerer_sel1 <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ soc_litedramcore_steerer_sel1 <= 1'd0;
+ if (1'd0) begin
+ soc_litedramcore_steerer_sel1 <= 2'd2;
+ end
+ if (1'd1) begin
+ soc_litedramcore_steerer_sel1 <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_steerer_sel2 <= 2'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ soc_litedramcore_steerer_sel2 <= 1'd0;
+ if (1'd0) begin
+ soc_litedramcore_steerer_sel2 <= 2'd2;
+ end
+ if (1'd1) begin
+ soc_litedramcore_steerer_sel2 <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ soc_litedramcore_steerer_sel2 <= 1'd0;
+ if (1'd1) begin
+ soc_litedramcore_steerer_sel2 <= 2'd2;
+ end
+ if (1'd0) begin
+ soc_litedramcore_steerer_sel2 <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_choose_cmd_want_activates <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ if (1'd0) begin
+ end else begin
+ soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ if (1'd0) begin
+ end else begin
+ soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_steerer_sel3 <= 2'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ soc_litedramcore_steerer_sel3 <= 1'd0;
+ if (1'd1) begin
+ soc_litedramcore_steerer_sel3 <= 2'd2;
+ end
+ if (1'd0) begin
+ soc_litedramcore_steerer_sel3 <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ soc_litedramcore_steerer_sel3 <= 1'd0;
+ if (1'd0) begin
+ soc_litedramcore_steerer_sel3 <= 2'd2;
+ end
+ if (1'd0) begin
+ soc_litedramcore_steerer_sel3 <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_en0 <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ soc_litedramcore_en0 <= 1'd1;
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_cmd_ready <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ soc_litedramcore_cmd_ready <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_choose_cmd_cmd_ready <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ if (1'd0) begin
+ end else begin
+ soc_litedramcore_choose_cmd_cmd_ready <= ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed);
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ if (1'd0) begin
+ end else begin
+ soc_litedramcore_choose_cmd_cmd_ready <= ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed);
+ end
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_choose_req_want_reads <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ soc_litedramcore_choose_req_want_reads <= 1'd1;
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_choose_req_want_writes <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ soc_litedramcore_choose_req_want_writes <= 1'd1;
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ end
+ endcase
end
assign litedramcore_roundrobin0_request = {(((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid)};
assign litedramcore_roundrobin0_ce = ((~soc_litedramcore_interface_bank0_valid) & (~soc_litedramcore_interface_bank0_lock));
assign soc_user_port_wdata_ready = litedramcore_new_master_wdata_ready1;
assign soc_user_port_rdata_valid = litedramcore_new_master_rdata_valid8;
always @(*) begin
- soc_litedramcore_interface_wdata <= 128'd0;
- case ({litedramcore_new_master_wdata_ready1})
- 1'd1: begin
- soc_litedramcore_interface_wdata <= soc_user_port_wdata_payload_data;
- end
- default: begin
- soc_litedramcore_interface_wdata <= 1'd0;
- end
- endcase
-end
-always @(*) begin
- soc_litedramcore_interface_wdata_we <= 16'd0;
- case ({litedramcore_new_master_wdata_ready1})
- 1'd1: begin
- soc_litedramcore_interface_wdata_we <= soc_user_port_wdata_payload_we;
- end
- default: begin
- soc_litedramcore_interface_wdata_we <= 1'd0;
- end
- endcase
+ soc_litedramcore_interface_wdata <= 128'd0;
+ case ({litedramcore_new_master_wdata_ready1})
+ 1'd1: begin
+ soc_litedramcore_interface_wdata <= soc_user_port_wdata_payload_data;
+ end
+ default: begin
+ soc_litedramcore_interface_wdata <= 1'd0;
+ end
+ endcase
+end
+always @(*) begin
+ soc_litedramcore_interface_wdata_we <= 16'd0;
+ case ({litedramcore_new_master_wdata_ready1})
+ 1'd1: begin
+ soc_litedramcore_interface_wdata_we <= soc_user_port_wdata_payload_we;
+ end
+ default: begin
+ soc_litedramcore_interface_wdata_we <= 1'd0;
+ end
+ endcase
end
assign soc_user_port_rdata_payload_data = soc_litedramcore_interface_rdata;
assign litedramcore_roundrobin0_grant = 1'd0;
assign litedramcore_roundrobin6_grant = 1'd0;
assign litedramcore_roundrobin7_grant = 1'd0;
always @(*) begin
- litedramcore_next_state <= 2'd0;
- litedramcore_next_state <= litedramcore_state;
- case (litedramcore_state)
- 1'd1: begin
- litedramcore_next_state <= 2'd2;
- end
- 2'd2: begin
- litedramcore_next_state <= 1'd0;
- end
- default: begin
- if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_next_state <= 1'd1;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_dat_w_next_value0 <= 32'd0;
- case (litedramcore_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- default: begin
- litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w;
- end
- endcase
-end
-always @(*) begin
- litedramcore_dat_w_next_value_ce0 <= 1'd0;
- case (litedramcore_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- default: begin
- litedramcore_dat_w_next_value_ce0 <= 1'd1;
- end
- endcase
-end
-always @(*) begin
- litedramcore_wishbone_ack <= 1'd0;
- case (litedramcore_state)
- 1'd1: begin
- end
- 2'd2: begin
- litedramcore_wishbone_ack <= 1'd1;
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_adr_next_value1 <= 14'd0;
- case (litedramcore_state)
- 1'd1: begin
- litedramcore_adr_next_value1 <= 1'd0;
- end
- 2'd2: begin
- end
- default: begin
- if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_adr_next_value1 <= litedramcore_wishbone_adr;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_adr_next_value_ce1 <= 1'd0;
- case (litedramcore_state)
- 1'd1: begin
- litedramcore_adr_next_value_ce1 <= 1'd1;
- end
- 2'd2: begin
- end
- default: begin
- if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_adr_next_value_ce1 <= 1'd1;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_we_next_value2 <= 1'd0;
- case (litedramcore_state)
- 1'd1: begin
- litedramcore_we_next_value2 <= 1'd0;
- end
- 2'd2: begin
- end
- default: begin
- if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_we_next_value_ce2 <= 1'd0;
- case (litedramcore_state)
- 1'd1: begin
- litedramcore_we_next_value_ce2 <= 1'd1;
- end
- 2'd2: begin
- end
- default: begin
- if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_we_next_value_ce2 <= 1'd1;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_wishbone_dat_r <= 32'd0;
- case (litedramcore_state)
- 1'd1: begin
- end
- 2'd2: begin
- litedramcore_wishbone_dat_r <= litedramcore_dat_r;
- end
- default: begin
- end
- endcase
+ litedramcore_next_state <= 2'd0;
+ litedramcore_next_state <= litedramcore_state;
+ case (litedramcore_state)
+ 1'd1: begin
+ litedramcore_next_state <= 2'd2;
+ end
+ 2'd2: begin
+ litedramcore_next_state <= 1'd0;
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_next_state <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_dat_w_next_value0 <= 32'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ default: begin
+ litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w;
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_dat_w_next_value_ce0 <= 1'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ default: begin
+ litedramcore_dat_w_next_value_ce0 <= 1'd1;
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_wishbone_ack <= 1'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ litedramcore_wishbone_ack <= 1'd1;
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_adr_next_value1 <= 14'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ litedramcore_adr_next_value1 <= 1'd0;
+ end
+ 2'd2: begin
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_adr_next_value1 <= litedramcore_wishbone_adr;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_adr_next_value_ce1 <= 1'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ litedramcore_adr_next_value_ce1 <= 1'd1;
+ end
+ 2'd2: begin
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_adr_next_value_ce1 <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_we_next_value2 <= 1'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ litedramcore_we_next_value2 <= 1'd0;
+ end
+ 2'd2: begin
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_we_next_value_ce2 <= 1'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ litedramcore_we_next_value_ce2 <= 1'd1;
+ end
+ 2'd2: begin
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_we_next_value_ce2 <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_wishbone_dat_r <= 32'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ litedramcore_wishbone_dat_r <= litedramcore_dat_r;
+ end
+ default: begin
+ end
+ endcase
end
assign litedramcore_wishbone_adr = soc_wb_bus_adr;
assign litedramcore_wishbone_dat_w = soc_wb_bus_dat_w;
assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0);
assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
always @(*) begin
- csrbank0_init_done0_re <= 1'd0;
- if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
- csrbank0_init_done0_re <= interface0_bank_bus_we;
- end
+ csrbank0_init_done0_re <= 1'd0;
+ if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank0_init_done0_re <= interface0_bank_bus_we;
+ end
end
always @(*) begin
- csrbank0_init_done0_we <= 1'd0;
- if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
- csrbank0_init_done0_we <= (~interface0_bank_bus_we);
- end
+ csrbank0_init_done0_we <= 1'd0;
+ if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank0_init_done0_we <= (~interface0_bank_bus_we);
+ end
end
assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0];
always @(*) begin
- csrbank0_init_error0_we <= 1'd0;
- if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
- csrbank0_init_error0_we <= (~interface0_bank_bus_we);
- end
+ csrbank0_init_error0_we <= 1'd0;
+ if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
+ csrbank0_init_error0_we <= (~interface0_bank_bus_we);
+ end
end
always @(*) begin
- csrbank0_init_error0_re <= 1'd0;
- if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
- csrbank0_init_error0_re <= interface0_bank_bus_we;
- end
+ csrbank0_init_error0_re <= 1'd0;
+ if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
+ csrbank0_init_error0_re <= interface0_bank_bus_we;
+ end
end
assign csrbank0_init_done0_w = soc_init_done_storage;
assign csrbank0_init_error0_w = soc_init_error_storage;
assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1);
assign csrbank1_dfii_control0_r = interface1_bank_bus_dat_w[3:0];
always @(*) begin
- csrbank1_dfii_control0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
- csrbank1_dfii_control0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_dfii_control0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank1_dfii_control0_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- csrbank1_dfii_control0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
- csrbank1_dfii_control0_re <= interface1_bank_bus_we;
- end
+ csrbank1_dfii_control0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank1_dfii_control0_re <= interface1_bank_bus_we;
+ end
end
assign csrbank1_dfii_pi0_command0_r = interface1_bank_bus_dat_w[5:0];
always @(*) begin
- csrbank1_dfii_pi0_command0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
- csrbank1_dfii_pi0_command0_re <= interface1_bank_bus_we;
- end
+ csrbank1_dfii_pi0_command0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
+ csrbank1_dfii_pi0_command0_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- csrbank1_dfii_pi0_command0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
- csrbank1_dfii_pi0_command0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_dfii_pi0_command0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
+ csrbank1_dfii_pi0_command0_we <= (~interface1_bank_bus_we);
+ end
end
assign soc_litedramcore_phaseinjector0_command_issue_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- soc_litedramcore_phaseinjector0_command_issue_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
- soc_litedramcore_phaseinjector0_command_issue_we <= (~interface1_bank_bus_we);
- end
+ soc_litedramcore_phaseinjector0_command_issue_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
+ soc_litedramcore_phaseinjector0_command_issue_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- soc_litedramcore_phaseinjector0_command_issue_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
- soc_litedramcore_phaseinjector0_command_issue_re <= interface1_bank_bus_we;
- end
+ soc_litedramcore_phaseinjector0_command_issue_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
+ soc_litedramcore_phaseinjector0_command_issue_re <= interface1_bank_bus_we;
+ end
end
assign csrbank1_dfii_pi0_address0_r = interface1_bank_bus_dat_w[13:0];
always @(*) begin
- csrbank1_dfii_pi0_address0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
- csrbank1_dfii_pi0_address0_re <= interface1_bank_bus_we;
- end
+ csrbank1_dfii_pi0_address0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
+ csrbank1_dfii_pi0_address0_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- csrbank1_dfii_pi0_address0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
- csrbank1_dfii_pi0_address0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_dfii_pi0_address0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
+ csrbank1_dfii_pi0_address0_we <= (~interface1_bank_bus_we);
+ end
end
assign csrbank1_dfii_pi0_baddress0_r = interface1_bank_bus_dat_w[2:0];
always @(*) begin
- csrbank1_dfii_pi0_baddress0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
- csrbank1_dfii_pi0_baddress0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_dfii_pi0_baddress0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
+ csrbank1_dfii_pi0_baddress0_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- csrbank1_dfii_pi0_baddress0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
- csrbank1_dfii_pi0_baddress0_re <= interface1_bank_bus_we;
- end
+ csrbank1_dfii_pi0_baddress0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
+ csrbank1_dfii_pi0_baddress0_re <= interface1_bank_bus_we;
+ end
end
assign csrbank1_dfii_pi0_wrdata0_r = interface1_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank1_dfii_pi0_wrdata0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
- csrbank1_dfii_pi0_wrdata0_re <= interface1_bank_bus_we;
- end
+ csrbank1_dfii_pi0_wrdata0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
+ csrbank1_dfii_pi0_wrdata0_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- csrbank1_dfii_pi0_wrdata0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
- csrbank1_dfii_pi0_wrdata0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_dfii_pi0_wrdata0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
+ csrbank1_dfii_pi0_wrdata0_we <= (~interface1_bank_bus_we);
+ end
end
assign csrbank1_dfii_pi0_rddata_r = interface1_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank1_dfii_pi0_rddata_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
- csrbank1_dfii_pi0_rddata_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_dfii_pi0_rddata_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
+ csrbank1_dfii_pi0_rddata_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- csrbank1_dfii_pi0_rddata_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
- csrbank1_dfii_pi0_rddata_re <= interface1_bank_bus_we;
- end
+ csrbank1_dfii_pi0_rddata_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
+ csrbank1_dfii_pi0_rddata_re <= interface1_bank_bus_we;
+ end
end
assign csrbank1_dfii_pi1_command0_r = interface1_bank_bus_dat_w[5:0];
always @(*) begin
- csrbank1_dfii_pi1_command0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
- csrbank1_dfii_pi1_command0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_dfii_pi1_command0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
+ csrbank1_dfii_pi1_command0_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- csrbank1_dfii_pi1_command0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
- csrbank1_dfii_pi1_command0_re <= interface1_bank_bus_we;
- end
+ csrbank1_dfii_pi1_command0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
+ csrbank1_dfii_pi1_command0_re <= interface1_bank_bus_we;
+ end
end
assign soc_litedramcore_phaseinjector1_command_issue_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- soc_litedramcore_phaseinjector1_command_issue_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
- soc_litedramcore_phaseinjector1_command_issue_re <= interface1_bank_bus_we;
- end
+ soc_litedramcore_phaseinjector1_command_issue_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
+ soc_litedramcore_phaseinjector1_command_issue_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- soc_litedramcore_phaseinjector1_command_issue_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
- soc_litedramcore_phaseinjector1_command_issue_we <= (~interface1_bank_bus_we);
- end
+ soc_litedramcore_phaseinjector1_command_issue_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
+ soc_litedramcore_phaseinjector1_command_issue_we <= (~interface1_bank_bus_we);
+ end
end
assign csrbank1_dfii_pi1_address0_r = interface1_bank_bus_dat_w[13:0];
always @(*) begin
- csrbank1_dfii_pi1_address0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
- csrbank1_dfii_pi1_address0_re <= interface1_bank_bus_we;
- end
+ csrbank1_dfii_pi1_address0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
+ csrbank1_dfii_pi1_address0_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- csrbank1_dfii_pi1_address0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
- csrbank1_dfii_pi1_address0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_dfii_pi1_address0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
+ csrbank1_dfii_pi1_address0_we <= (~interface1_bank_bus_we);
+ end
end
assign csrbank1_dfii_pi1_baddress0_r = interface1_bank_bus_dat_w[2:0];
always @(*) begin
- csrbank1_dfii_pi1_baddress0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
- csrbank1_dfii_pi1_baddress0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_dfii_pi1_baddress0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
+ csrbank1_dfii_pi1_baddress0_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- csrbank1_dfii_pi1_baddress0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
- csrbank1_dfii_pi1_baddress0_re <= interface1_bank_bus_we;
- end
+ csrbank1_dfii_pi1_baddress0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
+ csrbank1_dfii_pi1_baddress0_re <= interface1_bank_bus_we;
+ end
end
assign csrbank1_dfii_pi1_wrdata0_r = interface1_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank1_dfii_pi1_wrdata0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
- csrbank1_dfii_pi1_wrdata0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_dfii_pi1_wrdata0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
+ csrbank1_dfii_pi1_wrdata0_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- csrbank1_dfii_pi1_wrdata0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
- csrbank1_dfii_pi1_wrdata0_re <= interface1_bank_bus_we;
- end
+ csrbank1_dfii_pi1_wrdata0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
+ csrbank1_dfii_pi1_wrdata0_re <= interface1_bank_bus_we;
+ end
end
assign csrbank1_dfii_pi1_rddata_r = interface1_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank1_dfii_pi1_rddata_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
- csrbank1_dfii_pi1_rddata_re <= interface1_bank_bus_we;
- end
+ csrbank1_dfii_pi1_rddata_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
+ csrbank1_dfii_pi1_rddata_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- csrbank1_dfii_pi1_rddata_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
- csrbank1_dfii_pi1_rddata_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_dfii_pi1_rddata_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
+ csrbank1_dfii_pi1_rddata_we <= (~interface1_bank_bus_we);
+ end
end
assign csrbank1_dfii_pi2_command0_r = interface1_bank_bus_dat_w[5:0];
always @(*) begin
- csrbank1_dfii_pi2_command0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin
- csrbank1_dfii_pi2_command0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_dfii_pi2_command0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin
+ csrbank1_dfii_pi2_command0_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- csrbank1_dfii_pi2_command0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin
- csrbank1_dfii_pi2_command0_re <= interface1_bank_bus_we;
- end
+ csrbank1_dfii_pi2_command0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd13))) begin
+ csrbank1_dfii_pi2_command0_re <= interface1_bank_bus_we;
+ end
end
assign soc_litedramcore_phaseinjector2_command_issue_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- soc_litedramcore_phaseinjector2_command_issue_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin
- soc_litedramcore_phaseinjector2_command_issue_re <= interface1_bank_bus_we;
- end
+ soc_litedramcore_phaseinjector2_command_issue_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin
+ soc_litedramcore_phaseinjector2_command_issue_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- soc_litedramcore_phaseinjector2_command_issue_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin
- soc_litedramcore_phaseinjector2_command_issue_we <= (~interface1_bank_bus_we);
- end
+ soc_litedramcore_phaseinjector2_command_issue_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd14))) begin
+ soc_litedramcore_phaseinjector2_command_issue_we <= (~interface1_bank_bus_we);
+ end
end
assign csrbank1_dfii_pi2_address0_r = interface1_bank_bus_dat_w[13:0];
always @(*) begin
- csrbank1_dfii_pi2_address0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin
- csrbank1_dfii_pi2_address0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_dfii_pi2_address0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin
+ csrbank1_dfii_pi2_address0_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- csrbank1_dfii_pi2_address0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin
- csrbank1_dfii_pi2_address0_re <= interface1_bank_bus_we;
- end
+ csrbank1_dfii_pi2_address0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd15))) begin
+ csrbank1_dfii_pi2_address0_re <= interface1_bank_bus_we;
+ end
end
assign csrbank1_dfii_pi2_baddress0_r = interface1_bank_bus_dat_w[2:0];
always @(*) begin
- csrbank1_dfii_pi2_baddress0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd16))) begin
- csrbank1_dfii_pi2_baddress0_re <= interface1_bank_bus_we;
- end
+ csrbank1_dfii_pi2_baddress0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd16))) begin
+ csrbank1_dfii_pi2_baddress0_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- csrbank1_dfii_pi2_baddress0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd16))) begin
- csrbank1_dfii_pi2_baddress0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_dfii_pi2_baddress0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd16))) begin
+ csrbank1_dfii_pi2_baddress0_we <= (~interface1_bank_bus_we);
+ end
end
assign csrbank1_dfii_pi2_wrdata0_r = interface1_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank1_dfii_pi2_wrdata0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd17))) begin
- csrbank1_dfii_pi2_wrdata0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_dfii_pi2_wrdata0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd17))) begin
+ csrbank1_dfii_pi2_wrdata0_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- csrbank1_dfii_pi2_wrdata0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd17))) begin
- csrbank1_dfii_pi2_wrdata0_re <= interface1_bank_bus_we;
- end
+ csrbank1_dfii_pi2_wrdata0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd17))) begin
+ csrbank1_dfii_pi2_wrdata0_re <= interface1_bank_bus_we;
+ end
end
assign csrbank1_dfii_pi2_rddata_r = interface1_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank1_dfii_pi2_rddata_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd18))) begin
- csrbank1_dfii_pi2_rddata_re <= interface1_bank_bus_we;
- end
+ csrbank1_dfii_pi2_rddata_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd18))) begin
+ csrbank1_dfii_pi2_rddata_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- csrbank1_dfii_pi2_rddata_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd18))) begin
- csrbank1_dfii_pi2_rddata_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_dfii_pi2_rddata_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd18))) begin
+ csrbank1_dfii_pi2_rddata_we <= (~interface1_bank_bus_we);
+ end
end
assign csrbank1_dfii_pi3_command0_r = interface1_bank_bus_dat_w[5:0];
always @(*) begin
- csrbank1_dfii_pi3_command0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd19))) begin
- csrbank1_dfii_pi3_command0_re <= interface1_bank_bus_we;
- end
+ csrbank1_dfii_pi3_command0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd19))) begin
+ csrbank1_dfii_pi3_command0_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- csrbank1_dfii_pi3_command0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd19))) begin
- csrbank1_dfii_pi3_command0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_dfii_pi3_command0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd19))) begin
+ csrbank1_dfii_pi3_command0_we <= (~interface1_bank_bus_we);
+ end
end
assign soc_litedramcore_phaseinjector3_command_issue_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- soc_litedramcore_phaseinjector3_command_issue_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd20))) begin
- soc_litedramcore_phaseinjector3_command_issue_we <= (~interface1_bank_bus_we);
- end
+ soc_litedramcore_phaseinjector3_command_issue_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd20))) begin
+ soc_litedramcore_phaseinjector3_command_issue_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- soc_litedramcore_phaseinjector3_command_issue_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd20))) begin
- soc_litedramcore_phaseinjector3_command_issue_re <= interface1_bank_bus_we;
- end
+ soc_litedramcore_phaseinjector3_command_issue_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd20))) begin
+ soc_litedramcore_phaseinjector3_command_issue_re <= interface1_bank_bus_we;
+ end
end
assign csrbank1_dfii_pi3_address0_r = interface1_bank_bus_dat_w[13:0];
always @(*) begin
- csrbank1_dfii_pi3_address0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd21))) begin
- csrbank1_dfii_pi3_address0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_dfii_pi3_address0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd21))) begin
+ csrbank1_dfii_pi3_address0_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- csrbank1_dfii_pi3_address0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd21))) begin
- csrbank1_dfii_pi3_address0_re <= interface1_bank_bus_we;
- end
+ csrbank1_dfii_pi3_address0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd21))) begin
+ csrbank1_dfii_pi3_address0_re <= interface1_bank_bus_we;
+ end
end
assign csrbank1_dfii_pi3_baddress0_r = interface1_bank_bus_dat_w[2:0];
always @(*) begin
- csrbank1_dfii_pi3_baddress0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd22))) begin
- csrbank1_dfii_pi3_baddress0_re <= interface1_bank_bus_we;
- end
+ csrbank1_dfii_pi3_baddress0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd22))) begin
+ csrbank1_dfii_pi3_baddress0_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- csrbank1_dfii_pi3_baddress0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd22))) begin
- csrbank1_dfii_pi3_baddress0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_dfii_pi3_baddress0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd22))) begin
+ csrbank1_dfii_pi3_baddress0_we <= (~interface1_bank_bus_we);
+ end
end
assign csrbank1_dfii_pi3_wrdata0_r = interface1_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank1_dfii_pi3_wrdata0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd23))) begin
- csrbank1_dfii_pi3_wrdata0_re <= interface1_bank_bus_we;
- end
+ csrbank1_dfii_pi3_wrdata0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd23))) begin
+ csrbank1_dfii_pi3_wrdata0_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- csrbank1_dfii_pi3_wrdata0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd23))) begin
- csrbank1_dfii_pi3_wrdata0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_dfii_pi3_wrdata0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd23))) begin
+ csrbank1_dfii_pi3_wrdata0_we <= (~interface1_bank_bus_we);
+ end
end
assign csrbank1_dfii_pi3_rddata_r = interface1_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank1_dfii_pi3_rddata_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd24))) begin
- csrbank1_dfii_pi3_rddata_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_dfii_pi3_rddata_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd24))) begin
+ csrbank1_dfii_pi3_rddata_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- csrbank1_dfii_pi3_rddata_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd24))) begin
- csrbank1_dfii_pi3_rddata_re <= interface1_bank_bus_we;
- end
+ csrbank1_dfii_pi3_rddata_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 5'd24))) begin
+ csrbank1_dfii_pi3_rddata_re <= interface1_bank_bus_we;
+ end
end
assign soc_litedramcore_sel = soc_litedramcore_storage[0];
assign soc_litedramcore_cke = soc_litedramcore_storage[1];
assign slice_proxy14 = ((soc_ddrphy_bankmodel7_row * 11'd1024) | soc_ddrphy_bankmodel7_write_col);
assign slice_proxy15 = ((soc_ddrphy_bankmodel7_row * 11'd1024) | soc_ddrphy_bankmodel7_read_col);
always @(*) begin
- rhs_array_muxed0 <= 1'd0;
- case (soc_litedramcore_choose_cmd_grant)
- 1'd0: begin
- rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[0];
- end
- 1'd1: begin
- rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[1];
- end
- 2'd2: begin
- rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[2];
- end
- 2'd3: begin
- rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[3];
- end
- 3'd4: begin
- rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[4];
- end
- 3'd5: begin
- rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[5];
- end
- 3'd6: begin
- rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[6];
- end
- default: begin
- rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[7];
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed1 <= 14'd0;
- case (soc_litedramcore_choose_cmd_grant)
- 1'd0: begin
- rhs_array_muxed1 <= soc_litedramcore_bankmachine0_cmd_payload_a;
- end
- 1'd1: begin
- rhs_array_muxed1 <= soc_litedramcore_bankmachine1_cmd_payload_a;
- end
- 2'd2: begin
- rhs_array_muxed1 <= soc_litedramcore_bankmachine2_cmd_payload_a;
- end
- 2'd3: begin
- rhs_array_muxed1 <= soc_litedramcore_bankmachine3_cmd_payload_a;
- end
- 3'd4: begin
- rhs_array_muxed1 <= soc_litedramcore_bankmachine4_cmd_payload_a;
- end
- 3'd5: begin
- rhs_array_muxed1 <= soc_litedramcore_bankmachine5_cmd_payload_a;
- end
- 3'd6: begin
- rhs_array_muxed1 <= soc_litedramcore_bankmachine6_cmd_payload_a;
- end
- default: begin
- rhs_array_muxed1 <= soc_litedramcore_bankmachine7_cmd_payload_a;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed2 <= 3'd0;
- case (soc_litedramcore_choose_cmd_grant)
- 1'd0: begin
- rhs_array_muxed2 <= soc_litedramcore_bankmachine0_cmd_payload_ba;
- end
- 1'd1: begin
- rhs_array_muxed2 <= soc_litedramcore_bankmachine1_cmd_payload_ba;
- end
- 2'd2: begin
- rhs_array_muxed2 <= soc_litedramcore_bankmachine2_cmd_payload_ba;
- end
- 2'd3: begin
- rhs_array_muxed2 <= soc_litedramcore_bankmachine3_cmd_payload_ba;
- end
- 3'd4: begin
- rhs_array_muxed2 <= soc_litedramcore_bankmachine4_cmd_payload_ba;
- end
- 3'd5: begin
- rhs_array_muxed2 <= soc_litedramcore_bankmachine5_cmd_payload_ba;
- end
- 3'd6: begin
- rhs_array_muxed2 <= soc_litedramcore_bankmachine6_cmd_payload_ba;
- end
- default: begin
- rhs_array_muxed2 <= soc_litedramcore_bankmachine7_cmd_payload_ba;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed3 <= 1'd0;
- case (soc_litedramcore_choose_cmd_grant)
- 1'd0: begin
- rhs_array_muxed3 <= soc_litedramcore_bankmachine0_cmd_payload_is_read;
- end
- 1'd1: begin
- rhs_array_muxed3 <= soc_litedramcore_bankmachine1_cmd_payload_is_read;
- end
- 2'd2: begin
- rhs_array_muxed3 <= soc_litedramcore_bankmachine2_cmd_payload_is_read;
- end
- 2'd3: begin
- rhs_array_muxed3 <= soc_litedramcore_bankmachine3_cmd_payload_is_read;
- end
- 3'd4: begin
- rhs_array_muxed3 <= soc_litedramcore_bankmachine4_cmd_payload_is_read;
- end
- 3'd5: begin
- rhs_array_muxed3 <= soc_litedramcore_bankmachine5_cmd_payload_is_read;
- end
- 3'd6: begin
- rhs_array_muxed3 <= soc_litedramcore_bankmachine6_cmd_payload_is_read;
- end
- default: begin
- rhs_array_muxed3 <= soc_litedramcore_bankmachine7_cmd_payload_is_read;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed4 <= 1'd0;
- case (soc_litedramcore_choose_cmd_grant)
- 1'd0: begin
- rhs_array_muxed4 <= soc_litedramcore_bankmachine0_cmd_payload_is_write;
- end
- 1'd1: begin
- rhs_array_muxed4 <= soc_litedramcore_bankmachine1_cmd_payload_is_write;
- end
- 2'd2: begin
- rhs_array_muxed4 <= soc_litedramcore_bankmachine2_cmd_payload_is_write;
- end
- 2'd3: begin
- rhs_array_muxed4 <= soc_litedramcore_bankmachine3_cmd_payload_is_write;
- end
- 3'd4: begin
- rhs_array_muxed4 <= soc_litedramcore_bankmachine4_cmd_payload_is_write;
- end
- 3'd5: begin
- rhs_array_muxed4 <= soc_litedramcore_bankmachine5_cmd_payload_is_write;
- end
- 3'd6: begin
- rhs_array_muxed4 <= soc_litedramcore_bankmachine6_cmd_payload_is_write;
- end
- default: begin
- rhs_array_muxed4 <= soc_litedramcore_bankmachine7_cmd_payload_is_write;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed5 <= 1'd0;
- case (soc_litedramcore_choose_cmd_grant)
- 1'd0: begin
- rhs_array_muxed5 <= soc_litedramcore_bankmachine0_cmd_payload_is_cmd;
- end
- 1'd1: begin
- rhs_array_muxed5 <= soc_litedramcore_bankmachine1_cmd_payload_is_cmd;
- end
- 2'd2: begin
- rhs_array_muxed5 <= soc_litedramcore_bankmachine2_cmd_payload_is_cmd;
- end
- 2'd3: begin
- rhs_array_muxed5 <= soc_litedramcore_bankmachine3_cmd_payload_is_cmd;
- end
- 3'd4: begin
- rhs_array_muxed5 <= soc_litedramcore_bankmachine4_cmd_payload_is_cmd;
- end
- 3'd5: begin
- rhs_array_muxed5 <= soc_litedramcore_bankmachine5_cmd_payload_is_cmd;
- end
- 3'd6: begin
- rhs_array_muxed5 <= soc_litedramcore_bankmachine6_cmd_payload_is_cmd;
- end
- default: begin
- rhs_array_muxed5 <= soc_litedramcore_bankmachine7_cmd_payload_is_cmd;
- end
- endcase
-end
-always @(*) begin
- t_array_muxed0 <= 1'd0;
- case (soc_litedramcore_choose_cmd_grant)
- 1'd0: begin
- t_array_muxed0 <= soc_litedramcore_bankmachine0_cmd_payload_cas;
- end
- 1'd1: begin
- t_array_muxed0 <= soc_litedramcore_bankmachine1_cmd_payload_cas;
- end
- 2'd2: begin
- t_array_muxed0 <= soc_litedramcore_bankmachine2_cmd_payload_cas;
- end
- 2'd3: begin
- t_array_muxed0 <= soc_litedramcore_bankmachine3_cmd_payload_cas;
- end
- 3'd4: begin
- t_array_muxed0 <= soc_litedramcore_bankmachine4_cmd_payload_cas;
- end
- 3'd5: begin
- t_array_muxed0 <= soc_litedramcore_bankmachine5_cmd_payload_cas;
- end
- 3'd6: begin
- t_array_muxed0 <= soc_litedramcore_bankmachine6_cmd_payload_cas;
- end
- default: begin
- t_array_muxed0 <= soc_litedramcore_bankmachine7_cmd_payload_cas;
- end
- endcase
-end
-always @(*) begin
- t_array_muxed1 <= 1'd0;
- case (soc_litedramcore_choose_cmd_grant)
- 1'd0: begin
- t_array_muxed1 <= soc_litedramcore_bankmachine0_cmd_payload_ras;
- end
- 1'd1: begin
- t_array_muxed1 <= soc_litedramcore_bankmachine1_cmd_payload_ras;
- end
- 2'd2: begin
- t_array_muxed1 <= soc_litedramcore_bankmachine2_cmd_payload_ras;
- end
- 2'd3: begin
- t_array_muxed1 <= soc_litedramcore_bankmachine3_cmd_payload_ras;
- end
- 3'd4: begin
- t_array_muxed1 <= soc_litedramcore_bankmachine4_cmd_payload_ras;
- end
- 3'd5: begin
- t_array_muxed1 <= soc_litedramcore_bankmachine5_cmd_payload_ras;
- end
- 3'd6: begin
- t_array_muxed1 <= soc_litedramcore_bankmachine6_cmd_payload_ras;
- end
- default: begin
- t_array_muxed1 <= soc_litedramcore_bankmachine7_cmd_payload_ras;
- end
- endcase
-end
-always @(*) begin
- t_array_muxed2 <= 1'd0;
- case (soc_litedramcore_choose_cmd_grant)
- 1'd0: begin
- t_array_muxed2 <= soc_litedramcore_bankmachine0_cmd_payload_we;
- end
- 1'd1: begin
- t_array_muxed2 <= soc_litedramcore_bankmachine1_cmd_payload_we;
- end
- 2'd2: begin
- t_array_muxed2 <= soc_litedramcore_bankmachine2_cmd_payload_we;
- end
- 2'd3: begin
- t_array_muxed2 <= soc_litedramcore_bankmachine3_cmd_payload_we;
- end
- 3'd4: begin
- t_array_muxed2 <= soc_litedramcore_bankmachine4_cmd_payload_we;
- end
- 3'd5: begin
- t_array_muxed2 <= soc_litedramcore_bankmachine5_cmd_payload_we;
- end
- 3'd6: begin
- t_array_muxed2 <= soc_litedramcore_bankmachine6_cmd_payload_we;
- end
- default: begin
- t_array_muxed2 <= soc_litedramcore_bankmachine7_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed6 <= 1'd0;
- case (soc_litedramcore_choose_req_grant)
- 1'd0: begin
- rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[0];
- end
- 1'd1: begin
- rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[1];
- end
- 2'd2: begin
- rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[2];
- end
- 2'd3: begin
- rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[3];
- end
- 3'd4: begin
- rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[4];
- end
- 3'd5: begin
- rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[5];
- end
- 3'd6: begin
- rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[6];
- end
- default: begin
- rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[7];
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed7 <= 14'd0;
- case (soc_litedramcore_choose_req_grant)
- 1'd0: begin
- rhs_array_muxed7 <= soc_litedramcore_bankmachine0_cmd_payload_a;
- end
- 1'd1: begin
- rhs_array_muxed7 <= soc_litedramcore_bankmachine1_cmd_payload_a;
- end
- 2'd2: begin
- rhs_array_muxed7 <= soc_litedramcore_bankmachine2_cmd_payload_a;
- end
- 2'd3: begin
- rhs_array_muxed7 <= soc_litedramcore_bankmachine3_cmd_payload_a;
- end
- 3'd4: begin
- rhs_array_muxed7 <= soc_litedramcore_bankmachine4_cmd_payload_a;
- end
- 3'd5: begin
- rhs_array_muxed7 <= soc_litedramcore_bankmachine5_cmd_payload_a;
- end
- 3'd6: begin
- rhs_array_muxed7 <= soc_litedramcore_bankmachine6_cmd_payload_a;
- end
- default: begin
- rhs_array_muxed7 <= soc_litedramcore_bankmachine7_cmd_payload_a;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed8 <= 3'd0;
- case (soc_litedramcore_choose_req_grant)
- 1'd0: begin
- rhs_array_muxed8 <= soc_litedramcore_bankmachine0_cmd_payload_ba;
- end
- 1'd1: begin
- rhs_array_muxed8 <= soc_litedramcore_bankmachine1_cmd_payload_ba;
- end
- 2'd2: begin
- rhs_array_muxed8 <= soc_litedramcore_bankmachine2_cmd_payload_ba;
- end
- 2'd3: begin
- rhs_array_muxed8 <= soc_litedramcore_bankmachine3_cmd_payload_ba;
- end
- 3'd4: begin
- rhs_array_muxed8 <= soc_litedramcore_bankmachine4_cmd_payload_ba;
- end
- 3'd5: begin
- rhs_array_muxed8 <= soc_litedramcore_bankmachine5_cmd_payload_ba;
- end
- 3'd6: begin
- rhs_array_muxed8 <= soc_litedramcore_bankmachine6_cmd_payload_ba;
- end
- default: begin
- rhs_array_muxed8 <= soc_litedramcore_bankmachine7_cmd_payload_ba;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed9 <= 1'd0;
- case (soc_litedramcore_choose_req_grant)
- 1'd0: begin
- rhs_array_muxed9 <= soc_litedramcore_bankmachine0_cmd_payload_is_read;
- end
- 1'd1: begin
- rhs_array_muxed9 <= soc_litedramcore_bankmachine1_cmd_payload_is_read;
- end
- 2'd2: begin
- rhs_array_muxed9 <= soc_litedramcore_bankmachine2_cmd_payload_is_read;
- end
- 2'd3: begin
- rhs_array_muxed9 <= soc_litedramcore_bankmachine3_cmd_payload_is_read;
- end
- 3'd4: begin
- rhs_array_muxed9 <= soc_litedramcore_bankmachine4_cmd_payload_is_read;
- end
- 3'd5: begin
- rhs_array_muxed9 <= soc_litedramcore_bankmachine5_cmd_payload_is_read;
- end
- 3'd6: begin
- rhs_array_muxed9 <= soc_litedramcore_bankmachine6_cmd_payload_is_read;
- end
- default: begin
- rhs_array_muxed9 <= soc_litedramcore_bankmachine7_cmd_payload_is_read;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed10 <= 1'd0;
- case (soc_litedramcore_choose_req_grant)
- 1'd0: begin
- rhs_array_muxed10 <= soc_litedramcore_bankmachine0_cmd_payload_is_write;
- end
- 1'd1: begin
- rhs_array_muxed10 <= soc_litedramcore_bankmachine1_cmd_payload_is_write;
- end
- 2'd2: begin
- rhs_array_muxed10 <= soc_litedramcore_bankmachine2_cmd_payload_is_write;
- end
- 2'd3: begin
- rhs_array_muxed10 <= soc_litedramcore_bankmachine3_cmd_payload_is_write;
- end
- 3'd4: begin
- rhs_array_muxed10 <= soc_litedramcore_bankmachine4_cmd_payload_is_write;
- end
- 3'd5: begin
- rhs_array_muxed10 <= soc_litedramcore_bankmachine5_cmd_payload_is_write;
- end
- 3'd6: begin
- rhs_array_muxed10 <= soc_litedramcore_bankmachine6_cmd_payload_is_write;
- end
- default: begin
- rhs_array_muxed10 <= soc_litedramcore_bankmachine7_cmd_payload_is_write;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed11 <= 1'd0;
- case (soc_litedramcore_choose_req_grant)
- 1'd0: begin
- rhs_array_muxed11 <= soc_litedramcore_bankmachine0_cmd_payload_is_cmd;
- end
- 1'd1: begin
- rhs_array_muxed11 <= soc_litedramcore_bankmachine1_cmd_payload_is_cmd;
- end
- 2'd2: begin
- rhs_array_muxed11 <= soc_litedramcore_bankmachine2_cmd_payload_is_cmd;
- end
- 2'd3: begin
- rhs_array_muxed11 <= soc_litedramcore_bankmachine3_cmd_payload_is_cmd;
- end
- 3'd4: begin
- rhs_array_muxed11 <= soc_litedramcore_bankmachine4_cmd_payload_is_cmd;
- end
- 3'd5: begin
- rhs_array_muxed11 <= soc_litedramcore_bankmachine5_cmd_payload_is_cmd;
- end
- 3'd6: begin
- rhs_array_muxed11 <= soc_litedramcore_bankmachine6_cmd_payload_is_cmd;
- end
- default: begin
- rhs_array_muxed11 <= soc_litedramcore_bankmachine7_cmd_payload_is_cmd;
- end
- endcase
-end
-always @(*) begin
- t_array_muxed3 <= 1'd0;
- case (soc_litedramcore_choose_req_grant)
- 1'd0: begin
- t_array_muxed3 <= soc_litedramcore_bankmachine0_cmd_payload_cas;
- end
- 1'd1: begin
- t_array_muxed3 <= soc_litedramcore_bankmachine1_cmd_payload_cas;
- end
- 2'd2: begin
- t_array_muxed3 <= soc_litedramcore_bankmachine2_cmd_payload_cas;
- end
- 2'd3: begin
- t_array_muxed3 <= soc_litedramcore_bankmachine3_cmd_payload_cas;
- end
- 3'd4: begin
- t_array_muxed3 <= soc_litedramcore_bankmachine4_cmd_payload_cas;
- end
- 3'd5: begin
- t_array_muxed3 <= soc_litedramcore_bankmachine5_cmd_payload_cas;
- end
- 3'd6: begin
- t_array_muxed3 <= soc_litedramcore_bankmachine6_cmd_payload_cas;
- end
- default: begin
- t_array_muxed3 <= soc_litedramcore_bankmachine7_cmd_payload_cas;
- end
- endcase
-end
-always @(*) begin
- t_array_muxed4 <= 1'd0;
- case (soc_litedramcore_choose_req_grant)
- 1'd0: begin
- t_array_muxed4 <= soc_litedramcore_bankmachine0_cmd_payload_ras;
- end
- 1'd1: begin
- t_array_muxed4 <= soc_litedramcore_bankmachine1_cmd_payload_ras;
- end
- 2'd2: begin
- t_array_muxed4 <= soc_litedramcore_bankmachine2_cmd_payload_ras;
- end
- 2'd3: begin
- t_array_muxed4 <= soc_litedramcore_bankmachine3_cmd_payload_ras;
- end
- 3'd4: begin
- t_array_muxed4 <= soc_litedramcore_bankmachine4_cmd_payload_ras;
- end
- 3'd5: begin
- t_array_muxed4 <= soc_litedramcore_bankmachine5_cmd_payload_ras;
- end
- 3'd6: begin
- t_array_muxed4 <= soc_litedramcore_bankmachine6_cmd_payload_ras;
- end
- default: begin
- t_array_muxed4 <= soc_litedramcore_bankmachine7_cmd_payload_ras;
- end
- endcase
-end
-always @(*) begin
- t_array_muxed5 <= 1'd0;
- case (soc_litedramcore_choose_req_grant)
- 1'd0: begin
- t_array_muxed5 <= soc_litedramcore_bankmachine0_cmd_payload_we;
- end
- 1'd1: begin
- t_array_muxed5 <= soc_litedramcore_bankmachine1_cmd_payload_we;
- end
- 2'd2: begin
- t_array_muxed5 <= soc_litedramcore_bankmachine2_cmd_payload_we;
- end
- 2'd3: begin
- t_array_muxed5 <= soc_litedramcore_bankmachine3_cmd_payload_we;
- end
- 3'd4: begin
- t_array_muxed5 <= soc_litedramcore_bankmachine4_cmd_payload_we;
- end
- 3'd5: begin
- t_array_muxed5 <= soc_litedramcore_bankmachine5_cmd_payload_we;
- end
- 3'd6: begin
- t_array_muxed5 <= soc_litedramcore_bankmachine6_cmd_payload_we;
- end
- default: begin
- t_array_muxed5 <= soc_litedramcore_bankmachine7_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed12 <= 21'd0;
- case (litedramcore_roundrobin0_grant)
- default: begin
- rhs_array_muxed12 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed13 <= 1'd0;
- case (litedramcore_roundrobin0_grant)
- default: begin
- rhs_array_muxed13 <= soc_user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed14 <= 1'd0;
- case (litedramcore_roundrobin0_grant)
- default: begin
- rhs_array_muxed14 <= (((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed15 <= 21'd0;
- case (litedramcore_roundrobin1_grant)
- default: begin
- rhs_array_muxed15 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed16 <= 1'd0;
- case (litedramcore_roundrobin1_grant)
- default: begin
- rhs_array_muxed16 <= soc_user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed17 <= 1'd0;
- case (litedramcore_roundrobin1_grant)
- default: begin
- rhs_array_muxed17 <= (((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed18 <= 21'd0;
- case (litedramcore_roundrobin2_grant)
- default: begin
- rhs_array_muxed18 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed19 <= 1'd0;
- case (litedramcore_roundrobin2_grant)
- default: begin
- rhs_array_muxed19 <= soc_user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed20 <= 1'd0;
- case (litedramcore_roundrobin2_grant)
- default: begin
- rhs_array_muxed20 <= (((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed21 <= 21'd0;
- case (litedramcore_roundrobin3_grant)
- default: begin
- rhs_array_muxed21 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed22 <= 1'd0;
- case (litedramcore_roundrobin3_grant)
- default: begin
- rhs_array_muxed22 <= soc_user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed23 <= 1'd0;
- case (litedramcore_roundrobin3_grant)
- default: begin
- rhs_array_muxed23 <= (((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
- end
- endcase
+ rhs_array_muxed0 <= 1'd0;
+ case (soc_litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[0];
+ end
+ 1'd1: begin
+ rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[1];
+ end
+ 2'd2: begin
+ rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[2];
+ end
+ 2'd3: begin
+ rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[3];
+ end
+ 3'd4: begin
+ rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[4];
+ end
+ 3'd5: begin
+ rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[5];
+ end
+ 3'd6: begin
+ rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[6];
+ end
+ default: begin
+ rhs_array_muxed0 <= soc_litedramcore_choose_cmd_valids[7];
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed1 <= 14'd0;
+ case (soc_litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed1 <= soc_litedramcore_bankmachine0_cmd_payload_a;
+ end
+ 1'd1: begin
+ rhs_array_muxed1 <= soc_litedramcore_bankmachine1_cmd_payload_a;
+ end
+ 2'd2: begin
+ rhs_array_muxed1 <= soc_litedramcore_bankmachine2_cmd_payload_a;
+ end
+ 2'd3: begin
+ rhs_array_muxed1 <= soc_litedramcore_bankmachine3_cmd_payload_a;
+ end
+ 3'd4: begin
+ rhs_array_muxed1 <= soc_litedramcore_bankmachine4_cmd_payload_a;
+ end
+ 3'd5: begin
+ rhs_array_muxed1 <= soc_litedramcore_bankmachine5_cmd_payload_a;
+ end
+ 3'd6: begin
+ rhs_array_muxed1 <= soc_litedramcore_bankmachine6_cmd_payload_a;
+ end
+ default: begin
+ rhs_array_muxed1 <= soc_litedramcore_bankmachine7_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed2 <= 3'd0;
+ case (soc_litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed2 <= soc_litedramcore_bankmachine0_cmd_payload_ba;
+ end
+ 1'd1: begin
+ rhs_array_muxed2 <= soc_litedramcore_bankmachine1_cmd_payload_ba;
+ end
+ 2'd2: begin
+ rhs_array_muxed2 <= soc_litedramcore_bankmachine2_cmd_payload_ba;
+ end
+ 2'd3: begin
+ rhs_array_muxed2 <= soc_litedramcore_bankmachine3_cmd_payload_ba;
+ end
+ 3'd4: begin
+ rhs_array_muxed2 <= soc_litedramcore_bankmachine4_cmd_payload_ba;
+ end
+ 3'd5: begin
+ rhs_array_muxed2 <= soc_litedramcore_bankmachine5_cmd_payload_ba;
+ end
+ 3'd6: begin
+ rhs_array_muxed2 <= soc_litedramcore_bankmachine6_cmd_payload_ba;
+ end
+ default: begin
+ rhs_array_muxed2 <= soc_litedramcore_bankmachine7_cmd_payload_ba;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed3 <= 1'd0;
+ case (soc_litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed3 <= soc_litedramcore_bankmachine0_cmd_payload_is_read;
+ end
+ 1'd1: begin
+ rhs_array_muxed3 <= soc_litedramcore_bankmachine1_cmd_payload_is_read;
+ end
+ 2'd2: begin
+ rhs_array_muxed3 <= soc_litedramcore_bankmachine2_cmd_payload_is_read;
+ end
+ 2'd3: begin
+ rhs_array_muxed3 <= soc_litedramcore_bankmachine3_cmd_payload_is_read;
+ end
+ 3'd4: begin
+ rhs_array_muxed3 <= soc_litedramcore_bankmachine4_cmd_payload_is_read;
+ end
+ 3'd5: begin
+ rhs_array_muxed3 <= soc_litedramcore_bankmachine5_cmd_payload_is_read;
+ end
+ 3'd6: begin
+ rhs_array_muxed3 <= soc_litedramcore_bankmachine6_cmd_payload_is_read;
+ end
+ default: begin
+ rhs_array_muxed3 <= soc_litedramcore_bankmachine7_cmd_payload_is_read;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed4 <= 1'd0;
+ case (soc_litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed4 <= soc_litedramcore_bankmachine0_cmd_payload_is_write;
+ end
+ 1'd1: begin
+ rhs_array_muxed4 <= soc_litedramcore_bankmachine1_cmd_payload_is_write;
+ end
+ 2'd2: begin
+ rhs_array_muxed4 <= soc_litedramcore_bankmachine2_cmd_payload_is_write;
+ end
+ 2'd3: begin
+ rhs_array_muxed4 <= soc_litedramcore_bankmachine3_cmd_payload_is_write;
+ end
+ 3'd4: begin
+ rhs_array_muxed4 <= soc_litedramcore_bankmachine4_cmd_payload_is_write;
+ end
+ 3'd5: begin
+ rhs_array_muxed4 <= soc_litedramcore_bankmachine5_cmd_payload_is_write;
+ end
+ 3'd6: begin
+ rhs_array_muxed4 <= soc_litedramcore_bankmachine6_cmd_payload_is_write;
+ end
+ default: begin
+ rhs_array_muxed4 <= soc_litedramcore_bankmachine7_cmd_payload_is_write;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed5 <= 1'd0;
+ case (soc_litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed5 <= soc_litedramcore_bankmachine0_cmd_payload_is_cmd;
+ end
+ 1'd1: begin
+ rhs_array_muxed5 <= soc_litedramcore_bankmachine1_cmd_payload_is_cmd;
+ end
+ 2'd2: begin
+ rhs_array_muxed5 <= soc_litedramcore_bankmachine2_cmd_payload_is_cmd;
+ end
+ 2'd3: begin
+ rhs_array_muxed5 <= soc_litedramcore_bankmachine3_cmd_payload_is_cmd;
+ end
+ 3'd4: begin
+ rhs_array_muxed5 <= soc_litedramcore_bankmachine4_cmd_payload_is_cmd;
+ end
+ 3'd5: begin
+ rhs_array_muxed5 <= soc_litedramcore_bankmachine5_cmd_payload_is_cmd;
+ end
+ 3'd6: begin
+ rhs_array_muxed5 <= soc_litedramcore_bankmachine6_cmd_payload_is_cmd;
+ end
+ default: begin
+ rhs_array_muxed5 <= soc_litedramcore_bankmachine7_cmd_payload_is_cmd;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed0 <= 1'd0;
+ case (soc_litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ t_array_muxed0 <= soc_litedramcore_bankmachine0_cmd_payload_cas;
+ end
+ 1'd1: begin
+ t_array_muxed0 <= soc_litedramcore_bankmachine1_cmd_payload_cas;
+ end
+ 2'd2: begin
+ t_array_muxed0 <= soc_litedramcore_bankmachine2_cmd_payload_cas;
+ end
+ 2'd3: begin
+ t_array_muxed0 <= soc_litedramcore_bankmachine3_cmd_payload_cas;
+ end
+ 3'd4: begin
+ t_array_muxed0 <= soc_litedramcore_bankmachine4_cmd_payload_cas;
+ end
+ 3'd5: begin
+ t_array_muxed0 <= soc_litedramcore_bankmachine5_cmd_payload_cas;
+ end
+ 3'd6: begin
+ t_array_muxed0 <= soc_litedramcore_bankmachine6_cmd_payload_cas;
+ end
+ default: begin
+ t_array_muxed0 <= soc_litedramcore_bankmachine7_cmd_payload_cas;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed1 <= 1'd0;
+ case (soc_litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ t_array_muxed1 <= soc_litedramcore_bankmachine0_cmd_payload_ras;
+ end
+ 1'd1: begin
+ t_array_muxed1 <= soc_litedramcore_bankmachine1_cmd_payload_ras;
+ end
+ 2'd2: begin
+ t_array_muxed1 <= soc_litedramcore_bankmachine2_cmd_payload_ras;
+ end
+ 2'd3: begin
+ t_array_muxed1 <= soc_litedramcore_bankmachine3_cmd_payload_ras;
+ end
+ 3'd4: begin
+ t_array_muxed1 <= soc_litedramcore_bankmachine4_cmd_payload_ras;
+ end
+ 3'd5: begin
+ t_array_muxed1 <= soc_litedramcore_bankmachine5_cmd_payload_ras;
+ end
+ 3'd6: begin
+ t_array_muxed1 <= soc_litedramcore_bankmachine6_cmd_payload_ras;
+ end
+ default: begin
+ t_array_muxed1 <= soc_litedramcore_bankmachine7_cmd_payload_ras;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed2 <= 1'd0;
+ case (soc_litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ t_array_muxed2 <= soc_litedramcore_bankmachine0_cmd_payload_we;
+ end
+ 1'd1: begin
+ t_array_muxed2 <= soc_litedramcore_bankmachine1_cmd_payload_we;
+ end
+ 2'd2: begin
+ t_array_muxed2 <= soc_litedramcore_bankmachine2_cmd_payload_we;
+ end
+ 2'd3: begin
+ t_array_muxed2 <= soc_litedramcore_bankmachine3_cmd_payload_we;
+ end
+ 3'd4: begin
+ t_array_muxed2 <= soc_litedramcore_bankmachine4_cmd_payload_we;
+ end
+ 3'd5: begin
+ t_array_muxed2 <= soc_litedramcore_bankmachine5_cmd_payload_we;
+ end
+ 3'd6: begin
+ t_array_muxed2 <= soc_litedramcore_bankmachine6_cmd_payload_we;
+ end
+ default: begin
+ t_array_muxed2 <= soc_litedramcore_bankmachine7_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed6 <= 1'd0;
+ case (soc_litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[0];
+ end
+ 1'd1: begin
+ rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[1];
+ end
+ 2'd2: begin
+ rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[2];
+ end
+ 2'd3: begin
+ rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[3];
+ end
+ 3'd4: begin
+ rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[4];
+ end
+ 3'd5: begin
+ rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[5];
+ end
+ 3'd6: begin
+ rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[6];
+ end
+ default: begin
+ rhs_array_muxed6 <= soc_litedramcore_choose_req_valids[7];
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed7 <= 14'd0;
+ case (soc_litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed7 <= soc_litedramcore_bankmachine0_cmd_payload_a;
+ end
+ 1'd1: begin
+ rhs_array_muxed7 <= soc_litedramcore_bankmachine1_cmd_payload_a;
+ end
+ 2'd2: begin
+ rhs_array_muxed7 <= soc_litedramcore_bankmachine2_cmd_payload_a;
+ end
+ 2'd3: begin
+ rhs_array_muxed7 <= soc_litedramcore_bankmachine3_cmd_payload_a;
+ end
+ 3'd4: begin
+ rhs_array_muxed7 <= soc_litedramcore_bankmachine4_cmd_payload_a;
+ end
+ 3'd5: begin
+ rhs_array_muxed7 <= soc_litedramcore_bankmachine5_cmd_payload_a;
+ end
+ 3'd6: begin
+ rhs_array_muxed7 <= soc_litedramcore_bankmachine6_cmd_payload_a;
+ end
+ default: begin
+ rhs_array_muxed7 <= soc_litedramcore_bankmachine7_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed8 <= 3'd0;
+ case (soc_litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed8 <= soc_litedramcore_bankmachine0_cmd_payload_ba;
+ end
+ 1'd1: begin
+ rhs_array_muxed8 <= soc_litedramcore_bankmachine1_cmd_payload_ba;
+ end
+ 2'd2: begin
+ rhs_array_muxed8 <= soc_litedramcore_bankmachine2_cmd_payload_ba;
+ end
+ 2'd3: begin
+ rhs_array_muxed8 <= soc_litedramcore_bankmachine3_cmd_payload_ba;
+ end
+ 3'd4: begin
+ rhs_array_muxed8 <= soc_litedramcore_bankmachine4_cmd_payload_ba;
+ end
+ 3'd5: begin
+ rhs_array_muxed8 <= soc_litedramcore_bankmachine5_cmd_payload_ba;
+ end
+ 3'd6: begin
+ rhs_array_muxed8 <= soc_litedramcore_bankmachine6_cmd_payload_ba;
+ end
+ default: begin
+ rhs_array_muxed8 <= soc_litedramcore_bankmachine7_cmd_payload_ba;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed9 <= 1'd0;
+ case (soc_litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed9 <= soc_litedramcore_bankmachine0_cmd_payload_is_read;
+ end
+ 1'd1: begin
+ rhs_array_muxed9 <= soc_litedramcore_bankmachine1_cmd_payload_is_read;
+ end
+ 2'd2: begin
+ rhs_array_muxed9 <= soc_litedramcore_bankmachine2_cmd_payload_is_read;
+ end
+ 2'd3: begin
+ rhs_array_muxed9 <= soc_litedramcore_bankmachine3_cmd_payload_is_read;
+ end
+ 3'd4: begin
+ rhs_array_muxed9 <= soc_litedramcore_bankmachine4_cmd_payload_is_read;
+ end
+ 3'd5: begin
+ rhs_array_muxed9 <= soc_litedramcore_bankmachine5_cmd_payload_is_read;
+ end
+ 3'd6: begin
+ rhs_array_muxed9 <= soc_litedramcore_bankmachine6_cmd_payload_is_read;
+ end
+ default: begin
+ rhs_array_muxed9 <= soc_litedramcore_bankmachine7_cmd_payload_is_read;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed10 <= 1'd0;
+ case (soc_litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed10 <= soc_litedramcore_bankmachine0_cmd_payload_is_write;
+ end
+ 1'd1: begin
+ rhs_array_muxed10 <= soc_litedramcore_bankmachine1_cmd_payload_is_write;
+ end
+ 2'd2: begin
+ rhs_array_muxed10 <= soc_litedramcore_bankmachine2_cmd_payload_is_write;
+ end
+ 2'd3: begin
+ rhs_array_muxed10 <= soc_litedramcore_bankmachine3_cmd_payload_is_write;
+ end
+ 3'd4: begin
+ rhs_array_muxed10 <= soc_litedramcore_bankmachine4_cmd_payload_is_write;
+ end
+ 3'd5: begin
+ rhs_array_muxed10 <= soc_litedramcore_bankmachine5_cmd_payload_is_write;
+ end
+ 3'd6: begin
+ rhs_array_muxed10 <= soc_litedramcore_bankmachine6_cmd_payload_is_write;
+ end
+ default: begin
+ rhs_array_muxed10 <= soc_litedramcore_bankmachine7_cmd_payload_is_write;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed11 <= 1'd0;
+ case (soc_litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed11 <= soc_litedramcore_bankmachine0_cmd_payload_is_cmd;
+ end
+ 1'd1: begin
+ rhs_array_muxed11 <= soc_litedramcore_bankmachine1_cmd_payload_is_cmd;
+ end
+ 2'd2: begin
+ rhs_array_muxed11 <= soc_litedramcore_bankmachine2_cmd_payload_is_cmd;
+ end
+ 2'd3: begin
+ rhs_array_muxed11 <= soc_litedramcore_bankmachine3_cmd_payload_is_cmd;
+ end
+ 3'd4: begin
+ rhs_array_muxed11 <= soc_litedramcore_bankmachine4_cmd_payload_is_cmd;
+ end
+ 3'd5: begin
+ rhs_array_muxed11 <= soc_litedramcore_bankmachine5_cmd_payload_is_cmd;
+ end
+ 3'd6: begin
+ rhs_array_muxed11 <= soc_litedramcore_bankmachine6_cmd_payload_is_cmd;
+ end
+ default: begin
+ rhs_array_muxed11 <= soc_litedramcore_bankmachine7_cmd_payload_is_cmd;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed3 <= 1'd0;
+ case (soc_litedramcore_choose_req_grant)
+ 1'd0: begin
+ t_array_muxed3 <= soc_litedramcore_bankmachine0_cmd_payload_cas;
+ end
+ 1'd1: begin
+ t_array_muxed3 <= soc_litedramcore_bankmachine1_cmd_payload_cas;
+ end
+ 2'd2: begin
+ t_array_muxed3 <= soc_litedramcore_bankmachine2_cmd_payload_cas;
+ end
+ 2'd3: begin
+ t_array_muxed3 <= soc_litedramcore_bankmachine3_cmd_payload_cas;
+ end
+ 3'd4: begin
+ t_array_muxed3 <= soc_litedramcore_bankmachine4_cmd_payload_cas;
+ end
+ 3'd5: begin
+ t_array_muxed3 <= soc_litedramcore_bankmachine5_cmd_payload_cas;
+ end
+ 3'd6: begin
+ t_array_muxed3 <= soc_litedramcore_bankmachine6_cmd_payload_cas;
+ end
+ default: begin
+ t_array_muxed3 <= soc_litedramcore_bankmachine7_cmd_payload_cas;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed4 <= 1'd0;
+ case (soc_litedramcore_choose_req_grant)
+ 1'd0: begin
+ t_array_muxed4 <= soc_litedramcore_bankmachine0_cmd_payload_ras;
+ end
+ 1'd1: begin
+ t_array_muxed4 <= soc_litedramcore_bankmachine1_cmd_payload_ras;
+ end
+ 2'd2: begin
+ t_array_muxed4 <= soc_litedramcore_bankmachine2_cmd_payload_ras;
+ end
+ 2'd3: begin
+ t_array_muxed4 <= soc_litedramcore_bankmachine3_cmd_payload_ras;
+ end
+ 3'd4: begin
+ t_array_muxed4 <= soc_litedramcore_bankmachine4_cmd_payload_ras;
+ end
+ 3'd5: begin
+ t_array_muxed4 <= soc_litedramcore_bankmachine5_cmd_payload_ras;
+ end
+ 3'd6: begin
+ t_array_muxed4 <= soc_litedramcore_bankmachine6_cmd_payload_ras;
+ end
+ default: begin
+ t_array_muxed4 <= soc_litedramcore_bankmachine7_cmd_payload_ras;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed5 <= 1'd0;
+ case (soc_litedramcore_choose_req_grant)
+ 1'd0: begin
+ t_array_muxed5 <= soc_litedramcore_bankmachine0_cmd_payload_we;
+ end
+ 1'd1: begin
+ t_array_muxed5 <= soc_litedramcore_bankmachine1_cmd_payload_we;
+ end
+ 2'd2: begin
+ t_array_muxed5 <= soc_litedramcore_bankmachine2_cmd_payload_we;
+ end
+ 2'd3: begin
+ t_array_muxed5 <= soc_litedramcore_bankmachine3_cmd_payload_we;
+ end
+ 3'd4: begin
+ t_array_muxed5 <= soc_litedramcore_bankmachine4_cmd_payload_we;
+ end
+ 3'd5: begin
+ t_array_muxed5 <= soc_litedramcore_bankmachine5_cmd_payload_we;
+ end
+ 3'd6: begin
+ t_array_muxed5 <= soc_litedramcore_bankmachine6_cmd_payload_we;
+ end
+ default: begin
+ t_array_muxed5 <= soc_litedramcore_bankmachine7_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed12 <= 21'd0;
+ case (litedramcore_roundrobin0_grant)
+ default: begin
+ rhs_array_muxed12 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed13 <= 1'd0;
+ case (litedramcore_roundrobin0_grant)
+ default: begin
+ rhs_array_muxed13 <= soc_user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed14 <= 1'd0;
+ case (litedramcore_roundrobin0_grant)
+ default: begin
+ rhs_array_muxed14 <= (((soc_user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed15 <= 21'd0;
+ case (litedramcore_roundrobin1_grant)
+ default: begin
+ rhs_array_muxed15 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed16 <= 1'd0;
+ case (litedramcore_roundrobin1_grant)
+ default: begin
+ rhs_array_muxed16 <= soc_user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed17 <= 1'd0;
+ case (litedramcore_roundrobin1_grant)
+ default: begin
+ rhs_array_muxed17 <= (((soc_user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed18 <= 21'd0;
+ case (litedramcore_roundrobin2_grant)
+ default: begin
+ rhs_array_muxed18 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed19 <= 1'd0;
+ case (litedramcore_roundrobin2_grant)
+ default: begin
+ rhs_array_muxed19 <= soc_user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed20 <= 1'd0;
+ case (litedramcore_roundrobin2_grant)
+ default: begin
+ rhs_array_muxed20 <= (((soc_user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed21 <= 21'd0;
+ case (litedramcore_roundrobin3_grant)
+ default: begin
+ rhs_array_muxed21 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed22 <= 1'd0;
+ case (litedramcore_roundrobin3_grant)
+ default: begin
+ rhs_array_muxed22 <= soc_user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed23 <= 1'd0;
+ case (litedramcore_roundrobin3_grant)
+ default: begin
+ rhs_array_muxed23 <= (((soc_user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
+ end
+ endcase
end
always @(*) begin
- rhs_array_muxed24 <= 21'd0;
- case (litedramcore_roundrobin4_grant)
- default: begin
- rhs_array_muxed24 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed25 <= 1'd0;
- case (litedramcore_roundrobin4_grant)
- default: begin
- rhs_array_muxed25 <= soc_user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed26 <= 1'd0;
- case (litedramcore_roundrobin4_grant)
- default: begin
- rhs_array_muxed26 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed27 <= 21'd0;
- case (litedramcore_roundrobin5_grant)
- default: begin
- rhs_array_muxed27 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed28 <= 1'd0;
- case (litedramcore_roundrobin5_grant)
- default: begin
- rhs_array_muxed28 <= soc_user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed29 <= 1'd0;
- case (litedramcore_roundrobin5_grant)
- default: begin
- rhs_array_muxed29 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed30 <= 21'd0;
- case (litedramcore_roundrobin6_grant)
- default: begin
- rhs_array_muxed30 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed31 <= 1'd0;
- case (litedramcore_roundrobin6_grant)
- default: begin
- rhs_array_muxed31 <= soc_user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed32 <= 1'd0;
- case (litedramcore_roundrobin6_grant)
- default: begin
- rhs_array_muxed32 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed33 <= 21'd0;
- case (litedramcore_roundrobin7_grant)
- default: begin
- rhs_array_muxed33 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed34 <= 1'd0;
- case (litedramcore_roundrobin7_grant)
- default: begin
- rhs_array_muxed34 <= soc_user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed35 <= 1'd0;
- case (litedramcore_roundrobin7_grant)
- default: begin
- rhs_array_muxed35 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & soc_user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- array_muxed0 <= 3'd0;
- case (soc_litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed0 <= soc_litedramcore_nop_ba[2:0];
- end
- 1'd1: begin
- array_muxed0 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0];
- end
- 2'd2: begin
- array_muxed0 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0];
- end
- default: begin
- array_muxed0 <= soc_litedramcore_cmd_payload_ba[2:0];
- end
- endcase
-end
-always @(*) begin
- array_muxed1 <= 14'd0;
- case (soc_litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed1 <= soc_litedramcore_nop_a;
- end
- 1'd1: begin
- array_muxed1 <= soc_litedramcore_choose_cmd_cmd_payload_a;
- end
- 2'd2: begin
- array_muxed1 <= soc_litedramcore_choose_req_cmd_payload_a;
- end
- default: begin
- array_muxed1 <= soc_litedramcore_cmd_payload_a;
- end
- endcase
-end
-always @(*) begin
- array_muxed2 <= 1'd0;
- case (soc_litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed2 <= 1'd0;
- end
- 1'd1: begin
- array_muxed2 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas);
- end
- 2'd2: begin
- array_muxed2 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas);
- end
- default: begin
- array_muxed2 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas);
- end
- endcase
-end
-always @(*) begin
- array_muxed3 <= 1'd0;
- case (soc_litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed3 <= 1'd0;
- end
- 1'd1: begin
- array_muxed3 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras);
- end
- 2'd2: begin
- array_muxed3 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras);
- end
- default: begin
- array_muxed3 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras);
- end
- endcase
-end
-always @(*) begin
- array_muxed4 <= 1'd0;
- case (soc_litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed4 <= 1'd0;
- end
- 1'd1: begin
- array_muxed4 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we);
- end
- 2'd2: begin
- array_muxed4 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we);
- end
- default: begin
- array_muxed4 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we);
- end
- endcase
-end
-always @(*) begin
- array_muxed5 <= 1'd0;
- case (soc_litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed5 <= 1'd0;
- end
- 1'd1: begin
- array_muxed5 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read);
- end
- 2'd2: begin
- array_muxed5 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read);
- end
- default: begin
- array_muxed5 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read);
- end
- endcase
-end
-always @(*) begin
- array_muxed6 <= 1'd0;
- case (soc_litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed6 <= 1'd0;
- end
- 1'd1: begin
- array_muxed6 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write);
- end
- 2'd2: begin
- array_muxed6 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write);
- end
- default: begin
- array_muxed6 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write);
- end
- endcase
-end
-always @(*) begin
- array_muxed7 <= 3'd0;
- case (soc_litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed7 <= soc_litedramcore_nop_ba[2:0];
- end
- 1'd1: begin
- array_muxed7 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0];
- end
- 2'd2: begin
- array_muxed7 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0];
- end
- default: begin
- array_muxed7 <= soc_litedramcore_cmd_payload_ba[2:0];
- end
- endcase
-end
-always @(*) begin
- array_muxed8 <= 14'd0;
- case (soc_litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed8 <= soc_litedramcore_nop_a;
- end
- 1'd1: begin
- array_muxed8 <= soc_litedramcore_choose_cmd_cmd_payload_a;
- end
- 2'd2: begin
- array_muxed8 <= soc_litedramcore_choose_req_cmd_payload_a;
- end
- default: begin
- array_muxed8 <= soc_litedramcore_cmd_payload_a;
- end
- endcase
-end
-always @(*) begin
- array_muxed9 <= 1'd0;
- case (soc_litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed9 <= 1'd0;
- end
- 1'd1: begin
- array_muxed9 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas);
- end
- 2'd2: begin
- array_muxed9 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas);
- end
- default: begin
- array_muxed9 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas);
- end
- endcase
-end
-always @(*) begin
- array_muxed10 <= 1'd0;
- case (soc_litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed10 <= 1'd0;
- end
- 1'd1: begin
- array_muxed10 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras);
- end
- 2'd2: begin
- array_muxed10 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras);
- end
- default: begin
- array_muxed10 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras);
- end
- endcase
-end
-always @(*) begin
- array_muxed11 <= 1'd0;
- case (soc_litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed11 <= 1'd0;
- end
- 1'd1: begin
- array_muxed11 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we);
- end
- 2'd2: begin
- array_muxed11 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we);
- end
- default: begin
- array_muxed11 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we);
- end
- endcase
-end
-always @(*) begin
- array_muxed12 <= 1'd0;
- case (soc_litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed12 <= 1'd0;
- end
- 1'd1: begin
- array_muxed12 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read);
- end
- 2'd2: begin
- array_muxed12 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read);
- end
- default: begin
- array_muxed12 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read);
- end
- endcase
-end
-always @(*) begin
- array_muxed13 <= 1'd0;
- case (soc_litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed13 <= 1'd0;
- end
- 1'd1: begin
- array_muxed13 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write);
- end
- 2'd2: begin
- array_muxed13 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write);
- end
- default: begin
- array_muxed13 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write);
- end
- endcase
-end
-always @(*) begin
- array_muxed14 <= 3'd0;
- case (soc_litedramcore_steerer_sel2)
- 1'd0: begin
- array_muxed14 <= soc_litedramcore_nop_ba[2:0];
- end
- 1'd1: begin
- array_muxed14 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0];
- end
- 2'd2: begin
- array_muxed14 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0];
- end
- default: begin
- array_muxed14 <= soc_litedramcore_cmd_payload_ba[2:0];
- end
- endcase
-end
-always @(*) begin
- array_muxed15 <= 14'd0;
- case (soc_litedramcore_steerer_sel2)
- 1'd0: begin
- array_muxed15 <= soc_litedramcore_nop_a;
- end
- 1'd1: begin
- array_muxed15 <= soc_litedramcore_choose_cmd_cmd_payload_a;
- end
- 2'd2: begin
- array_muxed15 <= soc_litedramcore_choose_req_cmd_payload_a;
- end
- default: begin
- array_muxed15 <= soc_litedramcore_cmd_payload_a;
- end
- endcase
-end
-always @(*) begin
- array_muxed16 <= 1'd0;
- case (soc_litedramcore_steerer_sel2)
- 1'd0: begin
- array_muxed16 <= 1'd0;
- end
- 1'd1: begin
- array_muxed16 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas);
- end
- 2'd2: begin
- array_muxed16 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas);
- end
- default: begin
- array_muxed16 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas);
- end
- endcase
-end
-always @(*) begin
- array_muxed17 <= 1'd0;
- case (soc_litedramcore_steerer_sel2)
- 1'd0: begin
- array_muxed17 <= 1'd0;
- end
- 1'd1: begin
- array_muxed17 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras);
- end
- 2'd2: begin
- array_muxed17 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras);
- end
- default: begin
- array_muxed17 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras);
- end
- endcase
-end
-always @(*) begin
- array_muxed18 <= 1'd0;
- case (soc_litedramcore_steerer_sel2)
- 1'd0: begin
- array_muxed18 <= 1'd0;
- end
- 1'd1: begin
- array_muxed18 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we);
- end
- 2'd2: begin
- array_muxed18 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we);
- end
- default: begin
- array_muxed18 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we);
- end
- endcase
-end
-always @(*) begin
- array_muxed19 <= 1'd0;
- case (soc_litedramcore_steerer_sel2)
- 1'd0: begin
- array_muxed19 <= 1'd0;
- end
- 1'd1: begin
- array_muxed19 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read);
- end
- 2'd2: begin
- array_muxed19 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read);
- end
- default: begin
- array_muxed19 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read);
- end
- endcase
-end
-always @(*) begin
- array_muxed20 <= 1'd0;
- case (soc_litedramcore_steerer_sel2)
- 1'd0: begin
- array_muxed20 <= 1'd0;
- end
- 1'd1: begin
- array_muxed20 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write);
- end
- 2'd2: begin
- array_muxed20 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write);
- end
- default: begin
- array_muxed20 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write);
- end
- endcase
-end
-always @(*) begin
- array_muxed21 <= 3'd0;
- case (soc_litedramcore_steerer_sel3)
- 1'd0: begin
- array_muxed21 <= soc_litedramcore_nop_ba[2:0];
- end
- 1'd1: begin
- array_muxed21 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0];
- end
- 2'd2: begin
- array_muxed21 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0];
- end
- default: begin
- array_muxed21 <= soc_litedramcore_cmd_payload_ba[2:0];
- end
- endcase
-end
-always @(*) begin
- array_muxed22 <= 14'd0;
- case (soc_litedramcore_steerer_sel3)
- 1'd0: begin
- array_muxed22 <= soc_litedramcore_nop_a;
- end
- 1'd1: begin
- array_muxed22 <= soc_litedramcore_choose_cmd_cmd_payload_a;
- end
- 2'd2: begin
- array_muxed22 <= soc_litedramcore_choose_req_cmd_payload_a;
- end
- default: begin
- array_muxed22 <= soc_litedramcore_cmd_payload_a;
- end
- endcase
-end
-always @(*) begin
- array_muxed23 <= 1'd0;
- case (soc_litedramcore_steerer_sel3)
- 1'd0: begin
- array_muxed23 <= 1'd0;
- end
- 1'd1: begin
- array_muxed23 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas);
- end
- 2'd2: begin
- array_muxed23 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas);
- end
- default: begin
- array_muxed23 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas);
- end
- endcase
-end
-always @(*) begin
- array_muxed24 <= 1'd0;
- case (soc_litedramcore_steerer_sel3)
- 1'd0: begin
- array_muxed24 <= 1'd0;
- end
- 1'd1: begin
- array_muxed24 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras);
- end
- 2'd2: begin
- array_muxed24 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras);
- end
- default: begin
- array_muxed24 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras);
- end
- endcase
-end
-always @(*) begin
- array_muxed25 <= 1'd0;
- case (soc_litedramcore_steerer_sel3)
- 1'd0: begin
- array_muxed25 <= 1'd0;
- end
- 1'd1: begin
- array_muxed25 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we);
- end
- 2'd2: begin
- array_muxed25 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we);
- end
- default: begin
- array_muxed25 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we);
- end
- endcase
-end
-always @(*) begin
- array_muxed26 <= 1'd0;
- case (soc_litedramcore_steerer_sel3)
- 1'd0: begin
- array_muxed26 <= 1'd0;
- end
- 1'd1: begin
- array_muxed26 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read);
- end
- 2'd2: begin
- array_muxed26 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read);
- end
- default: begin
- array_muxed26 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read);
- end
- endcase
-end
-always @(*) begin
- array_muxed27 <= 1'd0;
- case (soc_litedramcore_steerer_sel3)
- 1'd0: begin
- array_muxed27 <= 1'd0;
- end
- 1'd1: begin
- array_muxed27 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write);
- end
- 2'd2: begin
- array_muxed27 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write);
- end
- default: begin
- array_muxed27 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write);
- end
- endcase
+ rhs_array_muxed24 <= 21'd0;
+ case (litedramcore_roundrobin4_grant)
+ default: begin
+ rhs_array_muxed24 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed25 <= 1'd0;
+ case (litedramcore_roundrobin4_grant)
+ default: begin
+ rhs_array_muxed25 <= soc_user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed26 <= 1'd0;
+ case (litedramcore_roundrobin4_grant)
+ default: begin
+ rhs_array_muxed26 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed27 <= 21'd0;
+ case (litedramcore_roundrobin5_grant)
+ default: begin
+ rhs_array_muxed27 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed28 <= 1'd0;
+ case (litedramcore_roundrobin5_grant)
+ default: begin
+ rhs_array_muxed28 <= soc_user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed29 <= 1'd0;
+ case (litedramcore_roundrobin5_grant)
+ default: begin
+ rhs_array_muxed29 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed30 <= 21'd0;
+ case (litedramcore_roundrobin6_grant)
+ default: begin
+ rhs_array_muxed30 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed31 <= 1'd0;
+ case (litedramcore_roundrobin6_grant)
+ default: begin
+ rhs_array_muxed31 <= soc_user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed32 <= 1'd0;
+ case (litedramcore_roundrobin6_grant)
+ default: begin
+ rhs_array_muxed32 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & soc_user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed33 <= 21'd0;
+ case (litedramcore_roundrobin7_grant)
+ default: begin
+ rhs_array_muxed33 <= {soc_user_port_cmd_payload_addr[23:10], soc_user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed34 <= 1'd0;
+ case (litedramcore_roundrobin7_grant)
+ default: begin
+ rhs_array_muxed34 <= soc_user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed35 <= 1'd0;
+ case (litedramcore_roundrobin7_grant)
+ default: begin
+ rhs_array_muxed35 <= (((soc_user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (soc_litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (soc_litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (soc_litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (soc_litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (soc_litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (soc_litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (soc_litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & soc_user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed0 <= 3'd0;
+ case (soc_litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed0 <= soc_litedramcore_nop_ba[2:0];
+ end
+ 1'd1: begin
+ array_muxed0 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+ end
+ 2'd2: begin
+ array_muxed0 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0];
+ end
+ default: begin
+ array_muxed0 <= soc_litedramcore_cmd_payload_ba[2:0];
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed1 <= 14'd0;
+ case (soc_litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed1 <= soc_litedramcore_nop_a;
+ end
+ 1'd1: begin
+ array_muxed1 <= soc_litedramcore_choose_cmd_cmd_payload_a;
+ end
+ 2'd2: begin
+ array_muxed1 <= soc_litedramcore_choose_req_cmd_payload_a;
+ end
+ default: begin
+ array_muxed1 <= soc_litedramcore_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed2 <= 1'd0;
+ case (soc_litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed2 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed2 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas);
+ end
+ 2'd2: begin
+ array_muxed2 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas);
+ end
+ default: begin
+ array_muxed2 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed3 <= 1'd0;
+ case (soc_litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed3 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed3 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras);
+ end
+ 2'd2: begin
+ array_muxed3 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras);
+ end
+ default: begin
+ array_muxed3 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed4 <= 1'd0;
+ case (soc_litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed4 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed4 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we);
+ end
+ 2'd2: begin
+ array_muxed4 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we);
+ end
+ default: begin
+ array_muxed4 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed5 <= 1'd0;
+ case (soc_litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed5 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed5 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read);
+ end
+ 2'd2: begin
+ array_muxed5 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read);
+ end
+ default: begin
+ array_muxed5 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed6 <= 1'd0;
+ case (soc_litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed6 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed6 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write);
+ end
+ 2'd2: begin
+ array_muxed6 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write);
+ end
+ default: begin
+ array_muxed6 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed7 <= 3'd0;
+ case (soc_litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed7 <= soc_litedramcore_nop_ba[2:0];
+ end
+ 1'd1: begin
+ array_muxed7 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+ end
+ 2'd2: begin
+ array_muxed7 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0];
+ end
+ default: begin
+ array_muxed7 <= soc_litedramcore_cmd_payload_ba[2:0];
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed8 <= 14'd0;
+ case (soc_litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed8 <= soc_litedramcore_nop_a;
+ end
+ 1'd1: begin
+ array_muxed8 <= soc_litedramcore_choose_cmd_cmd_payload_a;
+ end
+ 2'd2: begin
+ array_muxed8 <= soc_litedramcore_choose_req_cmd_payload_a;
+ end
+ default: begin
+ array_muxed8 <= soc_litedramcore_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed9 <= 1'd0;
+ case (soc_litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed9 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed9 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas);
+ end
+ 2'd2: begin
+ array_muxed9 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas);
+ end
+ default: begin
+ array_muxed9 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed10 <= 1'd0;
+ case (soc_litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed10 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed10 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras);
+ end
+ 2'd2: begin
+ array_muxed10 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras);
+ end
+ default: begin
+ array_muxed10 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed11 <= 1'd0;
+ case (soc_litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed11 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed11 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we);
+ end
+ 2'd2: begin
+ array_muxed11 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we);
+ end
+ default: begin
+ array_muxed11 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed12 <= 1'd0;
+ case (soc_litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed12 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed12 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read);
+ end
+ 2'd2: begin
+ array_muxed12 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read);
+ end
+ default: begin
+ array_muxed12 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed13 <= 1'd0;
+ case (soc_litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed13 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed13 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write);
+ end
+ 2'd2: begin
+ array_muxed13 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write);
+ end
+ default: begin
+ array_muxed13 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed14 <= 3'd0;
+ case (soc_litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed14 <= soc_litedramcore_nop_ba[2:0];
+ end
+ 1'd1: begin
+ array_muxed14 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+ end
+ 2'd2: begin
+ array_muxed14 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0];
+ end
+ default: begin
+ array_muxed14 <= soc_litedramcore_cmd_payload_ba[2:0];
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed15 <= 14'd0;
+ case (soc_litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed15 <= soc_litedramcore_nop_a;
+ end
+ 1'd1: begin
+ array_muxed15 <= soc_litedramcore_choose_cmd_cmd_payload_a;
+ end
+ 2'd2: begin
+ array_muxed15 <= soc_litedramcore_choose_req_cmd_payload_a;
+ end
+ default: begin
+ array_muxed15 <= soc_litedramcore_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed16 <= 1'd0;
+ case (soc_litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed16 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed16 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas);
+ end
+ 2'd2: begin
+ array_muxed16 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas);
+ end
+ default: begin
+ array_muxed16 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed17 <= 1'd0;
+ case (soc_litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed17 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed17 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras);
+ end
+ 2'd2: begin
+ array_muxed17 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras);
+ end
+ default: begin
+ array_muxed17 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed18 <= 1'd0;
+ case (soc_litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed18 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed18 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we);
+ end
+ 2'd2: begin
+ array_muxed18 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we);
+ end
+ default: begin
+ array_muxed18 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed19 <= 1'd0;
+ case (soc_litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed19 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed19 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read);
+ end
+ 2'd2: begin
+ array_muxed19 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read);
+ end
+ default: begin
+ array_muxed19 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed20 <= 1'd0;
+ case (soc_litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed20 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed20 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write);
+ end
+ 2'd2: begin
+ array_muxed20 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write);
+ end
+ default: begin
+ array_muxed20 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed21 <= 3'd0;
+ case (soc_litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed21 <= soc_litedramcore_nop_ba[2:0];
+ end
+ 1'd1: begin
+ array_muxed21 <= soc_litedramcore_choose_cmd_cmd_payload_ba[2:0];
+ end
+ 2'd2: begin
+ array_muxed21 <= soc_litedramcore_choose_req_cmd_payload_ba[2:0];
+ end
+ default: begin
+ array_muxed21 <= soc_litedramcore_cmd_payload_ba[2:0];
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed22 <= 14'd0;
+ case (soc_litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed22 <= soc_litedramcore_nop_a;
+ end
+ 1'd1: begin
+ array_muxed22 <= soc_litedramcore_choose_cmd_cmd_payload_a;
+ end
+ 2'd2: begin
+ array_muxed22 <= soc_litedramcore_choose_req_cmd_payload_a;
+ end
+ default: begin
+ array_muxed22 <= soc_litedramcore_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed23 <= 1'd0;
+ case (soc_litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed23 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed23 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_cas);
+ end
+ 2'd2: begin
+ array_muxed23 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_cas);
+ end
+ default: begin
+ array_muxed23 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_cas);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed24 <= 1'd0;
+ case (soc_litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed24 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed24 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_ras);
+ end
+ 2'd2: begin
+ array_muxed24 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_ras);
+ end
+ default: begin
+ array_muxed24 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_ras);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed25 <= 1'd0;
+ case (soc_litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed25 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed25 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_we);
+ end
+ 2'd2: begin
+ array_muxed25 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_we);
+ end
+ default: begin
+ array_muxed25 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_we);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed26 <= 1'd0;
+ case (soc_litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed26 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed26 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_read);
+ end
+ 2'd2: begin
+ array_muxed26 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_read);
+ end
+ default: begin
+ array_muxed26 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_read);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed27 <= 1'd0;
+ case (soc_litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed27 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed27 <= ((soc_litedramcore_choose_cmd_cmd_valid & soc_litedramcore_choose_cmd_cmd_ready) & soc_litedramcore_choose_cmd_cmd_payload_is_write);
+ end
+ 2'd2: begin
+ array_muxed27 <= ((soc_litedramcore_choose_req_cmd_valid & soc_litedramcore_choose_req_cmd_ready) & soc_litedramcore_choose_req_cmd_payload_is_write);
+ end
+ default: begin
+ array_muxed27 <= ((soc_litedramcore_cmd_valid & soc_litedramcore_cmd_ready) & soc_litedramcore_cmd_payload_is_write);
+ end
+ endcase
end
//------------------------------------------------------------------------------
always @(posedge por_clk) begin
- soc_int_rst <= 1'd0;
+ soc_int_rst <= 1'd0;
end
always @(posedge sys_clk) begin
- soc_ddrphy_new_bank_write0 <= soc_ddrphy_bank_write0;
- soc_ddrphy_new_bank_write_col0 <= soc_ddrphy_bank_write_col0;
- soc_ddrphy_new_bank_write1 <= soc_ddrphy_bank_write1;
- soc_ddrphy_new_bank_write_col1 <= soc_ddrphy_bank_write_col1;
- soc_ddrphy_new_bank_write2 <= soc_ddrphy_bank_write2;
- soc_ddrphy_new_bank_write_col2 <= soc_ddrphy_bank_write_col2;
- soc_ddrphy_new_bank_write3 <= soc_ddrphy_bank_write3;
- soc_ddrphy_new_bank_write_col3 <= soc_ddrphy_bank_write_col3;
- soc_ddrphy_new_bank_write4 <= soc_ddrphy_bank_write4;
- soc_ddrphy_new_bank_write_col4 <= soc_ddrphy_bank_write_col4;
- soc_ddrphy_new_bank_write5 <= soc_ddrphy_bank_write5;
- soc_ddrphy_new_bank_write_col5 <= soc_ddrphy_bank_write_col5;
- soc_ddrphy_new_bank_write6 <= soc_ddrphy_bank_write6;
- soc_ddrphy_new_bank_write_col6 <= soc_ddrphy_bank_write_col6;
- soc_ddrphy_new_bank_write7 <= soc_ddrphy_bank_write7;
- soc_ddrphy_new_bank_write_col7 <= soc_ddrphy_bank_write_col7;
- soc_ddrphy_new_banks_read0 <= soc_ddrphy_banks_read;
- soc_ddrphy_new_banks_read_data0 <= soc_ddrphy_banks_read_data;
- soc_ddrphy_new_banks_read1 <= soc_ddrphy_new_banks_read0;
- soc_ddrphy_new_banks_read_data1 <= soc_ddrphy_new_banks_read_data0;
- soc_ddrphy_new_banks_read2 <= soc_ddrphy_new_banks_read1;
- soc_ddrphy_new_banks_read_data2 <= soc_ddrphy_new_banks_read_data1;
- soc_ddrphy_new_banks_read3 <= soc_ddrphy_new_banks_read2;
- soc_ddrphy_new_banks_read_data3 <= soc_ddrphy_new_banks_read_data2;
- soc_ddrphy_new_banks_read4 <= soc_ddrphy_new_banks_read3;
- soc_ddrphy_new_banks_read_data4 <= soc_ddrphy_new_banks_read_data3;
- soc_ddrphy_new_banks_read5 <= soc_ddrphy_new_banks_read4;
- soc_ddrphy_new_banks_read_data5 <= soc_ddrphy_new_banks_read_data4;
- soc_ddrphy_new_banks_read6 <= soc_ddrphy_new_banks_read5;
- soc_ddrphy_new_banks_read_data6 <= soc_ddrphy_new_banks_read_data5;
- soc_ddrphy_new_banks_read7 <= soc_ddrphy_new_banks_read6;
- soc_ddrphy_new_banks_read_data7 <= soc_ddrphy_new_banks_read_data6;
- if (soc_ddrphy_bankmodel0_precharge) begin
- soc_ddrphy_bankmodel0_active <= 1'd0;
- end else begin
- if (soc_ddrphy_bankmodel0_activate) begin
- soc_ddrphy_bankmodel0_active <= 1'd1;
- soc_ddrphy_bankmodel0_row <= soc_ddrphy_bankmodel0_activate_row;
- end
- end
- if (soc_ddrphy_bankmodel1_precharge) begin
- soc_ddrphy_bankmodel1_active <= 1'd0;
- end else begin
- if (soc_ddrphy_bankmodel1_activate) begin
- soc_ddrphy_bankmodel1_active <= 1'd1;
- soc_ddrphy_bankmodel1_row <= soc_ddrphy_bankmodel1_activate_row;
- end
- end
- if (soc_ddrphy_bankmodel2_precharge) begin
- soc_ddrphy_bankmodel2_active <= 1'd0;
- end else begin
- if (soc_ddrphy_bankmodel2_activate) begin
- soc_ddrphy_bankmodel2_active <= 1'd1;
- soc_ddrphy_bankmodel2_row <= soc_ddrphy_bankmodel2_activate_row;
- end
- end
- if (soc_ddrphy_bankmodel3_precharge) begin
- soc_ddrphy_bankmodel3_active <= 1'd0;
- end else begin
- if (soc_ddrphy_bankmodel3_activate) begin
- soc_ddrphy_bankmodel3_active <= 1'd1;
- soc_ddrphy_bankmodel3_row <= soc_ddrphy_bankmodel3_activate_row;
- end
- end
- if (soc_ddrphy_bankmodel4_precharge) begin
- soc_ddrphy_bankmodel4_active <= 1'd0;
- end else begin
- if (soc_ddrphy_bankmodel4_activate) begin
- soc_ddrphy_bankmodel4_active <= 1'd1;
- soc_ddrphy_bankmodel4_row <= soc_ddrphy_bankmodel4_activate_row;
- end
- end
- if (soc_ddrphy_bankmodel5_precharge) begin
- soc_ddrphy_bankmodel5_active <= 1'd0;
- end else begin
- if (soc_ddrphy_bankmodel5_activate) begin
- soc_ddrphy_bankmodel5_active <= 1'd1;
- soc_ddrphy_bankmodel5_row <= soc_ddrphy_bankmodel5_activate_row;
- end
- end
- if (soc_ddrphy_bankmodel6_precharge) begin
- soc_ddrphy_bankmodel6_active <= 1'd0;
- end else begin
- if (soc_ddrphy_bankmodel6_activate) begin
- soc_ddrphy_bankmodel6_active <= 1'd1;
- soc_ddrphy_bankmodel6_row <= soc_ddrphy_bankmodel6_activate_row;
- end
- end
- if (soc_ddrphy_bankmodel7_precharge) begin
- soc_ddrphy_bankmodel7_active <= 1'd0;
- end else begin
- if (soc_ddrphy_bankmodel7_activate) begin
- soc_ddrphy_bankmodel7_active <= 1'd1;
- soc_ddrphy_bankmodel7_row <= soc_ddrphy_bankmodel7_activate_row;
- end
- end
- if (soc_litedramcore_csr_dfi_p0_rddata_valid) begin
- soc_litedramcore_phaseinjector0_rddata_status <= soc_litedramcore_csr_dfi_p0_rddata;
- end
- if (soc_litedramcore_csr_dfi_p1_rddata_valid) begin
- soc_litedramcore_phaseinjector1_rddata_status <= soc_litedramcore_csr_dfi_p1_rddata;
- end
- if (soc_litedramcore_csr_dfi_p2_rddata_valid) begin
- soc_litedramcore_phaseinjector2_rddata_status <= soc_litedramcore_csr_dfi_p2_rddata;
- end
- if (soc_litedramcore_csr_dfi_p3_rddata_valid) begin
- soc_litedramcore_phaseinjector3_rddata_status <= soc_litedramcore_csr_dfi_p3_rddata;
- end
- if ((soc_litedramcore_timer_wait & (~soc_litedramcore_timer_done0))) begin
- soc_litedramcore_timer_count1 <= (soc_litedramcore_timer_count1 - 1'd1);
- end else begin
- soc_litedramcore_timer_count1 <= 10'd781;
- end
- soc_litedramcore_postponer_req_o <= 1'd0;
- if (soc_litedramcore_postponer_req_i) begin
- soc_litedramcore_postponer_count <= (soc_litedramcore_postponer_count - 1'd1);
- if ((soc_litedramcore_postponer_count == 1'd0)) begin
- soc_litedramcore_postponer_count <= 1'd0;
- soc_litedramcore_postponer_req_o <= 1'd1;
- end
- end
- if (soc_litedramcore_sequencer_start0) begin
- soc_litedramcore_sequencer_count <= 1'd0;
- end else begin
- if (soc_litedramcore_sequencer_done1) begin
- if ((soc_litedramcore_sequencer_count != 1'd0)) begin
- soc_litedramcore_sequencer_count <= (soc_litedramcore_sequencer_count - 1'd1);
- end
- end
- end
- soc_litedramcore_cmd_payload_a <= 1'd0;
- soc_litedramcore_cmd_payload_ba <= 1'd0;
- soc_litedramcore_cmd_payload_cas <= 1'd0;
- soc_litedramcore_cmd_payload_ras <= 1'd0;
- soc_litedramcore_cmd_payload_we <= 1'd0;
- soc_litedramcore_sequencer_done1 <= 1'd0;
- if ((soc_litedramcore_sequencer_start1 & (soc_litedramcore_sequencer_counter == 1'd0))) begin
- soc_litedramcore_cmd_payload_a <= 11'd1024;
- soc_litedramcore_cmd_payload_ba <= 1'd0;
- soc_litedramcore_cmd_payload_cas <= 1'd0;
- soc_litedramcore_cmd_payload_ras <= 1'd1;
- soc_litedramcore_cmd_payload_we <= 1'd1;
- end
- if ((soc_litedramcore_sequencer_counter == 2'd3)) begin
- soc_litedramcore_cmd_payload_a <= 11'd1024;
- soc_litedramcore_cmd_payload_ba <= 1'd0;
- soc_litedramcore_cmd_payload_cas <= 1'd1;
- soc_litedramcore_cmd_payload_ras <= 1'd1;
- soc_litedramcore_cmd_payload_we <= 1'd0;
- end
- if ((soc_litedramcore_sequencer_counter == 6'd35)) begin
- soc_litedramcore_cmd_payload_a <= 1'd0;
- soc_litedramcore_cmd_payload_ba <= 1'd0;
- soc_litedramcore_cmd_payload_cas <= 1'd0;
- soc_litedramcore_cmd_payload_ras <= 1'd0;
- soc_litedramcore_cmd_payload_we <= 1'd0;
- soc_litedramcore_sequencer_done1 <= 1'd1;
- end
- if ((soc_litedramcore_sequencer_counter == 6'd35)) begin
- soc_litedramcore_sequencer_counter <= 1'd0;
- end else begin
- if ((soc_litedramcore_sequencer_counter != 1'd0)) begin
- soc_litedramcore_sequencer_counter <= (soc_litedramcore_sequencer_counter + 1'd1);
- end else begin
- if (soc_litedramcore_sequencer_start1) begin
- soc_litedramcore_sequencer_counter <= 1'd1;
- end
- end
- end
- if ((soc_litedramcore_zqcs_timer_wait & (~soc_litedramcore_zqcs_timer_done0))) begin
- soc_litedramcore_zqcs_timer_count1 <= (soc_litedramcore_zqcs_timer_count1 - 1'd1);
- end else begin
- soc_litedramcore_zqcs_timer_count1 <= 27'd99999999;
- end
- soc_litedramcore_zqcs_executer_done <= 1'd0;
- if ((soc_litedramcore_zqcs_executer_start & (soc_litedramcore_zqcs_executer_counter == 1'd0))) begin
- soc_litedramcore_cmd_payload_a <= 11'd1024;
- soc_litedramcore_cmd_payload_ba <= 1'd0;
- soc_litedramcore_cmd_payload_cas <= 1'd0;
- soc_litedramcore_cmd_payload_ras <= 1'd1;
- soc_litedramcore_cmd_payload_we <= 1'd1;
- end
- if ((soc_litedramcore_zqcs_executer_counter == 2'd3)) begin
- soc_litedramcore_cmd_payload_a <= 1'd0;
- soc_litedramcore_cmd_payload_ba <= 1'd0;
- soc_litedramcore_cmd_payload_cas <= 1'd0;
- soc_litedramcore_cmd_payload_ras <= 1'd0;
- soc_litedramcore_cmd_payload_we <= 1'd1;
- end
- if ((soc_litedramcore_zqcs_executer_counter == 5'd19)) begin
- soc_litedramcore_cmd_payload_a <= 1'd0;
- soc_litedramcore_cmd_payload_ba <= 1'd0;
- soc_litedramcore_cmd_payload_cas <= 1'd0;
- soc_litedramcore_cmd_payload_ras <= 1'd0;
- soc_litedramcore_cmd_payload_we <= 1'd0;
- soc_litedramcore_zqcs_executer_done <= 1'd1;
- end
- if ((soc_litedramcore_zqcs_executer_counter == 5'd19)) begin
- soc_litedramcore_zqcs_executer_counter <= 1'd0;
- end else begin
- if ((soc_litedramcore_zqcs_executer_counter != 1'd0)) begin
- soc_litedramcore_zqcs_executer_counter <= (soc_litedramcore_zqcs_executer_counter + 1'd1);
- end else begin
- if (soc_litedramcore_zqcs_executer_start) begin
- soc_litedramcore_zqcs_executer_counter <= 1'd1;
- end
- end
- end
- litedramcore_refresher_state <= litedramcore_refresher_next_state;
- if (soc_litedramcore_bankmachine0_row_close) begin
- soc_litedramcore_bankmachine0_row_opened <= 1'd0;
- end else begin
- if (soc_litedramcore_bankmachine0_row_open) begin
- soc_litedramcore_bankmachine0_row_opened <= 1'd1;
- soc_litedramcore_bankmachine0_row <= soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7];
- end
- end
- if (((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
- soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
- soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & soc_litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~soc_litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
- if ((~soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin
- soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
- soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~soc_litedramcore_bankmachine0_cmd_buffer_source_valid) | soc_litedramcore_bankmachine0_cmd_buffer_source_ready)) begin
- soc_litedramcore_bankmachine0_cmd_buffer_source_valid <= soc_litedramcore_bankmachine0_cmd_buffer_sink_valid;
- soc_litedramcore_bankmachine0_cmd_buffer_source_first <= soc_litedramcore_bankmachine0_cmd_buffer_sink_first;
- soc_litedramcore_bankmachine0_cmd_buffer_source_last <= soc_litedramcore_bankmachine0_cmd_buffer_sink_last;
- soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
- soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
- end
- if (soc_litedramcore_bankmachine0_twtpcon_valid) begin
- soc_litedramcore_bankmachine0_twtpcon_count <= 3'd5;
- if (1'd0) begin
- soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
- end else begin
- soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~soc_litedramcore_bankmachine0_twtpcon_ready)) begin
- soc_litedramcore_bankmachine0_twtpcon_count <= (soc_litedramcore_bankmachine0_twtpcon_count - 1'd1);
- if ((soc_litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
- soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (soc_litedramcore_bankmachine0_trccon_valid) begin
- soc_litedramcore_bankmachine0_trccon_count <= 3'd5;
- if (1'd0) begin
- soc_litedramcore_bankmachine0_trccon_ready <= 1'd1;
- end else begin
- soc_litedramcore_bankmachine0_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~soc_litedramcore_bankmachine0_trccon_ready)) begin
- soc_litedramcore_bankmachine0_trccon_count <= (soc_litedramcore_bankmachine0_trccon_count - 1'd1);
- if ((soc_litedramcore_bankmachine0_trccon_count == 1'd1)) begin
- soc_litedramcore_bankmachine0_trccon_ready <= 1'd1;
- end
- end
- end
- if (soc_litedramcore_bankmachine0_trascon_valid) begin
- soc_litedramcore_bankmachine0_trascon_count <= 3'd4;
- if (1'd0) begin
- soc_litedramcore_bankmachine0_trascon_ready <= 1'd1;
- end else begin
- soc_litedramcore_bankmachine0_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~soc_litedramcore_bankmachine0_trascon_ready)) begin
- soc_litedramcore_bankmachine0_trascon_count <= (soc_litedramcore_bankmachine0_trascon_count - 1'd1);
- if ((soc_litedramcore_bankmachine0_trascon_count == 1'd1)) begin
- soc_litedramcore_bankmachine0_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state;
- if (soc_litedramcore_bankmachine1_row_close) begin
- soc_litedramcore_bankmachine1_row_opened <= 1'd0;
- end else begin
- if (soc_litedramcore_bankmachine1_row_open) begin
- soc_litedramcore_bankmachine1_row_opened <= 1'd1;
- soc_litedramcore_bankmachine1_row <= soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7];
- end
- end
- if (((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
- soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
- soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & soc_litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~soc_litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
- if ((~soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin
- soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
- soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~soc_litedramcore_bankmachine1_cmd_buffer_source_valid) | soc_litedramcore_bankmachine1_cmd_buffer_source_ready)) begin
- soc_litedramcore_bankmachine1_cmd_buffer_source_valid <= soc_litedramcore_bankmachine1_cmd_buffer_sink_valid;
- soc_litedramcore_bankmachine1_cmd_buffer_source_first <= soc_litedramcore_bankmachine1_cmd_buffer_sink_first;
- soc_litedramcore_bankmachine1_cmd_buffer_source_last <= soc_litedramcore_bankmachine1_cmd_buffer_sink_last;
- soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
- soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
- end
- if (soc_litedramcore_bankmachine1_twtpcon_valid) begin
- soc_litedramcore_bankmachine1_twtpcon_count <= 3'd5;
- if (1'd0) begin
- soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
- end else begin
- soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~soc_litedramcore_bankmachine1_twtpcon_ready)) begin
- soc_litedramcore_bankmachine1_twtpcon_count <= (soc_litedramcore_bankmachine1_twtpcon_count - 1'd1);
- if ((soc_litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
- soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (soc_litedramcore_bankmachine1_trccon_valid) begin
- soc_litedramcore_bankmachine1_trccon_count <= 3'd5;
- if (1'd0) begin
- soc_litedramcore_bankmachine1_trccon_ready <= 1'd1;
- end else begin
- soc_litedramcore_bankmachine1_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~soc_litedramcore_bankmachine1_trccon_ready)) begin
- soc_litedramcore_bankmachine1_trccon_count <= (soc_litedramcore_bankmachine1_trccon_count - 1'd1);
- if ((soc_litedramcore_bankmachine1_trccon_count == 1'd1)) begin
- soc_litedramcore_bankmachine1_trccon_ready <= 1'd1;
- end
- end
- end
- if (soc_litedramcore_bankmachine1_trascon_valid) begin
- soc_litedramcore_bankmachine1_trascon_count <= 3'd4;
- if (1'd0) begin
- soc_litedramcore_bankmachine1_trascon_ready <= 1'd1;
- end else begin
- soc_litedramcore_bankmachine1_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~soc_litedramcore_bankmachine1_trascon_ready)) begin
- soc_litedramcore_bankmachine1_trascon_count <= (soc_litedramcore_bankmachine1_trascon_count - 1'd1);
- if ((soc_litedramcore_bankmachine1_trascon_count == 1'd1)) begin
- soc_litedramcore_bankmachine1_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state;
- if (soc_litedramcore_bankmachine2_row_close) begin
- soc_litedramcore_bankmachine2_row_opened <= 1'd0;
- end else begin
- if (soc_litedramcore_bankmachine2_row_open) begin
- soc_litedramcore_bankmachine2_row_opened <= 1'd1;
- soc_litedramcore_bankmachine2_row <= soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7];
- end
- end
- if (((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
- soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
- soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & soc_litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~soc_litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
- if ((~soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin
- soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
- soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~soc_litedramcore_bankmachine2_cmd_buffer_source_valid) | soc_litedramcore_bankmachine2_cmd_buffer_source_ready)) begin
- soc_litedramcore_bankmachine2_cmd_buffer_source_valid <= soc_litedramcore_bankmachine2_cmd_buffer_sink_valid;
- soc_litedramcore_bankmachine2_cmd_buffer_source_first <= soc_litedramcore_bankmachine2_cmd_buffer_sink_first;
- soc_litedramcore_bankmachine2_cmd_buffer_source_last <= soc_litedramcore_bankmachine2_cmd_buffer_sink_last;
- soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
- soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
- end
- if (soc_litedramcore_bankmachine2_twtpcon_valid) begin
- soc_litedramcore_bankmachine2_twtpcon_count <= 3'd5;
- if (1'd0) begin
- soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
- end else begin
- soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~soc_litedramcore_bankmachine2_twtpcon_ready)) begin
- soc_litedramcore_bankmachine2_twtpcon_count <= (soc_litedramcore_bankmachine2_twtpcon_count - 1'd1);
- if ((soc_litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
- soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (soc_litedramcore_bankmachine2_trccon_valid) begin
- soc_litedramcore_bankmachine2_trccon_count <= 3'd5;
- if (1'd0) begin
- soc_litedramcore_bankmachine2_trccon_ready <= 1'd1;
- end else begin
- soc_litedramcore_bankmachine2_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~soc_litedramcore_bankmachine2_trccon_ready)) begin
- soc_litedramcore_bankmachine2_trccon_count <= (soc_litedramcore_bankmachine2_trccon_count - 1'd1);
- if ((soc_litedramcore_bankmachine2_trccon_count == 1'd1)) begin
- soc_litedramcore_bankmachine2_trccon_ready <= 1'd1;
- end
- end
- end
- if (soc_litedramcore_bankmachine2_trascon_valid) begin
- soc_litedramcore_bankmachine2_trascon_count <= 3'd4;
- if (1'd0) begin
- soc_litedramcore_bankmachine2_trascon_ready <= 1'd1;
- end else begin
- soc_litedramcore_bankmachine2_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~soc_litedramcore_bankmachine2_trascon_ready)) begin
- soc_litedramcore_bankmachine2_trascon_count <= (soc_litedramcore_bankmachine2_trascon_count - 1'd1);
- if ((soc_litedramcore_bankmachine2_trascon_count == 1'd1)) begin
- soc_litedramcore_bankmachine2_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state;
- if (soc_litedramcore_bankmachine3_row_close) begin
- soc_litedramcore_bankmachine3_row_opened <= 1'd0;
- end else begin
- if (soc_litedramcore_bankmachine3_row_open) begin
- soc_litedramcore_bankmachine3_row_opened <= 1'd1;
- soc_litedramcore_bankmachine3_row <= soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7];
- end
- end
- if (((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
- soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
- soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & soc_litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~soc_litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
- if ((~soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin
- soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
- soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~soc_litedramcore_bankmachine3_cmd_buffer_source_valid) | soc_litedramcore_bankmachine3_cmd_buffer_source_ready)) begin
- soc_litedramcore_bankmachine3_cmd_buffer_source_valid <= soc_litedramcore_bankmachine3_cmd_buffer_sink_valid;
- soc_litedramcore_bankmachine3_cmd_buffer_source_first <= soc_litedramcore_bankmachine3_cmd_buffer_sink_first;
- soc_litedramcore_bankmachine3_cmd_buffer_source_last <= soc_litedramcore_bankmachine3_cmd_buffer_sink_last;
- soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
- soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
- end
- if (soc_litedramcore_bankmachine3_twtpcon_valid) begin
- soc_litedramcore_bankmachine3_twtpcon_count <= 3'd5;
- if (1'd0) begin
- soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
- end else begin
- soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~soc_litedramcore_bankmachine3_twtpcon_ready)) begin
- soc_litedramcore_bankmachine3_twtpcon_count <= (soc_litedramcore_bankmachine3_twtpcon_count - 1'd1);
- if ((soc_litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
- soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (soc_litedramcore_bankmachine3_trccon_valid) begin
- soc_litedramcore_bankmachine3_trccon_count <= 3'd5;
- if (1'd0) begin
- soc_litedramcore_bankmachine3_trccon_ready <= 1'd1;
- end else begin
- soc_litedramcore_bankmachine3_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~soc_litedramcore_bankmachine3_trccon_ready)) begin
- soc_litedramcore_bankmachine3_trccon_count <= (soc_litedramcore_bankmachine3_trccon_count - 1'd1);
- if ((soc_litedramcore_bankmachine3_trccon_count == 1'd1)) begin
- soc_litedramcore_bankmachine3_trccon_ready <= 1'd1;
- end
- end
- end
- if (soc_litedramcore_bankmachine3_trascon_valid) begin
- soc_litedramcore_bankmachine3_trascon_count <= 3'd4;
- if (1'd0) begin
- soc_litedramcore_bankmachine3_trascon_ready <= 1'd1;
- end else begin
- soc_litedramcore_bankmachine3_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~soc_litedramcore_bankmachine3_trascon_ready)) begin
- soc_litedramcore_bankmachine3_trascon_count <= (soc_litedramcore_bankmachine3_trascon_count - 1'd1);
- if ((soc_litedramcore_bankmachine3_trascon_count == 1'd1)) begin
- soc_litedramcore_bankmachine3_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state;
- if (soc_litedramcore_bankmachine4_row_close) begin
- soc_litedramcore_bankmachine4_row_opened <= 1'd0;
- end else begin
- if (soc_litedramcore_bankmachine4_row_open) begin
- soc_litedramcore_bankmachine4_row_opened <= 1'd1;
- soc_litedramcore_bankmachine4_row <= soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7];
- end
- end
- if (((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
- soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
- soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & soc_litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~soc_litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
- if ((~soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin
- soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
- soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~soc_litedramcore_bankmachine4_cmd_buffer_source_valid) | soc_litedramcore_bankmachine4_cmd_buffer_source_ready)) begin
- soc_litedramcore_bankmachine4_cmd_buffer_source_valid <= soc_litedramcore_bankmachine4_cmd_buffer_sink_valid;
- soc_litedramcore_bankmachine4_cmd_buffer_source_first <= soc_litedramcore_bankmachine4_cmd_buffer_sink_first;
- soc_litedramcore_bankmachine4_cmd_buffer_source_last <= soc_litedramcore_bankmachine4_cmd_buffer_sink_last;
- soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
- soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
- end
- if (soc_litedramcore_bankmachine4_twtpcon_valid) begin
- soc_litedramcore_bankmachine4_twtpcon_count <= 3'd5;
- if (1'd0) begin
- soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
- end else begin
- soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~soc_litedramcore_bankmachine4_twtpcon_ready)) begin
- soc_litedramcore_bankmachine4_twtpcon_count <= (soc_litedramcore_bankmachine4_twtpcon_count - 1'd1);
- if ((soc_litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
- soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (soc_litedramcore_bankmachine4_trccon_valid) begin
- soc_litedramcore_bankmachine4_trccon_count <= 3'd5;
- if (1'd0) begin
- soc_litedramcore_bankmachine4_trccon_ready <= 1'd1;
- end else begin
- soc_litedramcore_bankmachine4_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~soc_litedramcore_bankmachine4_trccon_ready)) begin
- soc_litedramcore_bankmachine4_trccon_count <= (soc_litedramcore_bankmachine4_trccon_count - 1'd1);
- if ((soc_litedramcore_bankmachine4_trccon_count == 1'd1)) begin
- soc_litedramcore_bankmachine4_trccon_ready <= 1'd1;
- end
- end
- end
- if (soc_litedramcore_bankmachine4_trascon_valid) begin
- soc_litedramcore_bankmachine4_trascon_count <= 3'd4;
- if (1'd0) begin
- soc_litedramcore_bankmachine4_trascon_ready <= 1'd1;
- end else begin
- soc_litedramcore_bankmachine4_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~soc_litedramcore_bankmachine4_trascon_ready)) begin
- soc_litedramcore_bankmachine4_trascon_count <= (soc_litedramcore_bankmachine4_trascon_count - 1'd1);
- if ((soc_litedramcore_bankmachine4_trascon_count == 1'd1)) begin
- soc_litedramcore_bankmachine4_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state;
- if (soc_litedramcore_bankmachine5_row_close) begin
- soc_litedramcore_bankmachine5_row_opened <= 1'd0;
- end else begin
- if (soc_litedramcore_bankmachine5_row_open) begin
- soc_litedramcore_bankmachine5_row_opened <= 1'd1;
- soc_litedramcore_bankmachine5_row <= soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7];
- end
- end
- if (((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
- soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
- soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & soc_litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~soc_litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
- if ((~soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin
- soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
- soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~soc_litedramcore_bankmachine5_cmd_buffer_source_valid) | soc_litedramcore_bankmachine5_cmd_buffer_source_ready)) begin
- soc_litedramcore_bankmachine5_cmd_buffer_source_valid <= soc_litedramcore_bankmachine5_cmd_buffer_sink_valid;
- soc_litedramcore_bankmachine5_cmd_buffer_source_first <= soc_litedramcore_bankmachine5_cmd_buffer_sink_first;
- soc_litedramcore_bankmachine5_cmd_buffer_source_last <= soc_litedramcore_bankmachine5_cmd_buffer_sink_last;
- soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
- soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
- end
- if (soc_litedramcore_bankmachine5_twtpcon_valid) begin
- soc_litedramcore_bankmachine5_twtpcon_count <= 3'd5;
- if (1'd0) begin
- soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
- end else begin
- soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~soc_litedramcore_bankmachine5_twtpcon_ready)) begin
- soc_litedramcore_bankmachine5_twtpcon_count <= (soc_litedramcore_bankmachine5_twtpcon_count - 1'd1);
- if ((soc_litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
- soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (soc_litedramcore_bankmachine5_trccon_valid) begin
- soc_litedramcore_bankmachine5_trccon_count <= 3'd5;
- if (1'd0) begin
- soc_litedramcore_bankmachine5_trccon_ready <= 1'd1;
- end else begin
- soc_litedramcore_bankmachine5_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~soc_litedramcore_bankmachine5_trccon_ready)) begin
- soc_litedramcore_bankmachine5_trccon_count <= (soc_litedramcore_bankmachine5_trccon_count - 1'd1);
- if ((soc_litedramcore_bankmachine5_trccon_count == 1'd1)) begin
- soc_litedramcore_bankmachine5_trccon_ready <= 1'd1;
- end
- end
- end
- if (soc_litedramcore_bankmachine5_trascon_valid) begin
- soc_litedramcore_bankmachine5_trascon_count <= 3'd4;
- if (1'd0) begin
- soc_litedramcore_bankmachine5_trascon_ready <= 1'd1;
- end else begin
- soc_litedramcore_bankmachine5_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~soc_litedramcore_bankmachine5_trascon_ready)) begin
- soc_litedramcore_bankmachine5_trascon_count <= (soc_litedramcore_bankmachine5_trascon_count - 1'd1);
- if ((soc_litedramcore_bankmachine5_trascon_count == 1'd1)) begin
- soc_litedramcore_bankmachine5_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state;
- if (soc_litedramcore_bankmachine6_row_close) begin
- soc_litedramcore_bankmachine6_row_opened <= 1'd0;
- end else begin
- if (soc_litedramcore_bankmachine6_row_open) begin
- soc_litedramcore_bankmachine6_row_opened <= 1'd1;
- soc_litedramcore_bankmachine6_row <= soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7];
- end
- end
- if (((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
- soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
- soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & soc_litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~soc_litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
- if ((~soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin
- soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
- soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~soc_litedramcore_bankmachine6_cmd_buffer_source_valid) | soc_litedramcore_bankmachine6_cmd_buffer_source_ready)) begin
- soc_litedramcore_bankmachine6_cmd_buffer_source_valid <= soc_litedramcore_bankmachine6_cmd_buffer_sink_valid;
- soc_litedramcore_bankmachine6_cmd_buffer_source_first <= soc_litedramcore_bankmachine6_cmd_buffer_sink_first;
- soc_litedramcore_bankmachine6_cmd_buffer_source_last <= soc_litedramcore_bankmachine6_cmd_buffer_sink_last;
- soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
- soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
- end
- if (soc_litedramcore_bankmachine6_twtpcon_valid) begin
- soc_litedramcore_bankmachine6_twtpcon_count <= 3'd5;
- if (1'd0) begin
- soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
- end else begin
- soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~soc_litedramcore_bankmachine6_twtpcon_ready)) begin
- soc_litedramcore_bankmachine6_twtpcon_count <= (soc_litedramcore_bankmachine6_twtpcon_count - 1'd1);
- if ((soc_litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
- soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (soc_litedramcore_bankmachine6_trccon_valid) begin
- soc_litedramcore_bankmachine6_trccon_count <= 3'd5;
- if (1'd0) begin
- soc_litedramcore_bankmachine6_trccon_ready <= 1'd1;
- end else begin
- soc_litedramcore_bankmachine6_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~soc_litedramcore_bankmachine6_trccon_ready)) begin
- soc_litedramcore_bankmachine6_trccon_count <= (soc_litedramcore_bankmachine6_trccon_count - 1'd1);
- if ((soc_litedramcore_bankmachine6_trccon_count == 1'd1)) begin
- soc_litedramcore_bankmachine6_trccon_ready <= 1'd1;
- end
- end
- end
- if (soc_litedramcore_bankmachine6_trascon_valid) begin
- soc_litedramcore_bankmachine6_trascon_count <= 3'd4;
- if (1'd0) begin
- soc_litedramcore_bankmachine6_trascon_ready <= 1'd1;
- end else begin
- soc_litedramcore_bankmachine6_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~soc_litedramcore_bankmachine6_trascon_ready)) begin
- soc_litedramcore_bankmachine6_trascon_count <= (soc_litedramcore_bankmachine6_trascon_count - 1'd1);
- if ((soc_litedramcore_bankmachine6_trascon_count == 1'd1)) begin
- soc_litedramcore_bankmachine6_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state;
- if (soc_litedramcore_bankmachine7_row_close) begin
- soc_litedramcore_bankmachine7_row_opened <= 1'd0;
- end else begin
- if (soc_litedramcore_bankmachine7_row_open) begin
- soc_litedramcore_bankmachine7_row_opened <= 1'd1;
- soc_litedramcore_bankmachine7_row <= soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7];
- end
- end
- if (((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
- soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
- soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & soc_litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~soc_litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
- if ((~soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin
- soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
- soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~soc_litedramcore_bankmachine7_cmd_buffer_source_valid) | soc_litedramcore_bankmachine7_cmd_buffer_source_ready)) begin
- soc_litedramcore_bankmachine7_cmd_buffer_source_valid <= soc_litedramcore_bankmachine7_cmd_buffer_sink_valid;
- soc_litedramcore_bankmachine7_cmd_buffer_source_first <= soc_litedramcore_bankmachine7_cmd_buffer_sink_first;
- soc_litedramcore_bankmachine7_cmd_buffer_source_last <= soc_litedramcore_bankmachine7_cmd_buffer_sink_last;
- soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we <= soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
- soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= soc_litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
- end
- if (soc_litedramcore_bankmachine7_twtpcon_valid) begin
- soc_litedramcore_bankmachine7_twtpcon_count <= 3'd5;
- if (1'd0) begin
- soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
- end else begin
- soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~soc_litedramcore_bankmachine7_twtpcon_ready)) begin
- soc_litedramcore_bankmachine7_twtpcon_count <= (soc_litedramcore_bankmachine7_twtpcon_count - 1'd1);
- if ((soc_litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
- soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (soc_litedramcore_bankmachine7_trccon_valid) begin
- soc_litedramcore_bankmachine7_trccon_count <= 3'd5;
- if (1'd0) begin
- soc_litedramcore_bankmachine7_trccon_ready <= 1'd1;
- end else begin
- soc_litedramcore_bankmachine7_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~soc_litedramcore_bankmachine7_trccon_ready)) begin
- soc_litedramcore_bankmachine7_trccon_count <= (soc_litedramcore_bankmachine7_trccon_count - 1'd1);
- if ((soc_litedramcore_bankmachine7_trccon_count == 1'd1)) begin
- soc_litedramcore_bankmachine7_trccon_ready <= 1'd1;
- end
- end
- end
- if (soc_litedramcore_bankmachine7_trascon_valid) begin
- soc_litedramcore_bankmachine7_trascon_count <= 3'd4;
- if (1'd0) begin
- soc_litedramcore_bankmachine7_trascon_ready <= 1'd1;
- end else begin
- soc_litedramcore_bankmachine7_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~soc_litedramcore_bankmachine7_trascon_ready)) begin
- soc_litedramcore_bankmachine7_trascon_count <= (soc_litedramcore_bankmachine7_trascon_count - 1'd1);
- if ((soc_litedramcore_bankmachine7_trascon_count == 1'd1)) begin
- soc_litedramcore_bankmachine7_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state;
- if ((~soc_litedramcore_en0)) begin
- soc_litedramcore_time0 <= 5'd31;
- end else begin
- if ((~soc_litedramcore_max_time0)) begin
- soc_litedramcore_time0 <= (soc_litedramcore_time0 - 1'd1);
- end
- end
- if ((~soc_litedramcore_en1)) begin
- soc_litedramcore_time1 <= 4'd15;
- end else begin
- if ((~soc_litedramcore_max_time1)) begin
- soc_litedramcore_time1 <= (soc_litedramcore_time1 - 1'd1);
- end
- end
- if (soc_litedramcore_choose_cmd_ce) begin
- case (soc_litedramcore_choose_cmd_grant)
- 1'd0: begin
- if (soc_litedramcore_choose_cmd_request[1]) begin
- soc_litedramcore_choose_cmd_grant <= 1'd1;
- end else begin
- if (soc_litedramcore_choose_cmd_request[2]) begin
- soc_litedramcore_choose_cmd_grant <= 2'd2;
- end else begin
- if (soc_litedramcore_choose_cmd_request[3]) begin
- soc_litedramcore_choose_cmd_grant <= 2'd3;
- end else begin
- if (soc_litedramcore_choose_cmd_request[4]) begin
- soc_litedramcore_choose_cmd_grant <= 3'd4;
- end else begin
- if (soc_litedramcore_choose_cmd_request[5]) begin
- soc_litedramcore_choose_cmd_grant <= 3'd5;
- end else begin
- if (soc_litedramcore_choose_cmd_request[6]) begin
- soc_litedramcore_choose_cmd_grant <= 3'd6;
- end else begin
- if (soc_litedramcore_choose_cmd_request[7]) begin
- soc_litedramcore_choose_cmd_grant <= 3'd7;
- end
- end
- end
- end
- end
- end
- end
- end
- 1'd1: begin
- if (soc_litedramcore_choose_cmd_request[2]) begin
- soc_litedramcore_choose_cmd_grant <= 2'd2;
- end else begin
- if (soc_litedramcore_choose_cmd_request[3]) begin
- soc_litedramcore_choose_cmd_grant <= 2'd3;
- end else begin
- if (soc_litedramcore_choose_cmd_request[4]) begin
- soc_litedramcore_choose_cmd_grant <= 3'd4;
- end else begin
- if (soc_litedramcore_choose_cmd_request[5]) begin
- soc_litedramcore_choose_cmd_grant <= 3'd5;
- end else begin
- if (soc_litedramcore_choose_cmd_request[6]) begin
- soc_litedramcore_choose_cmd_grant <= 3'd6;
- end else begin
- if (soc_litedramcore_choose_cmd_request[7]) begin
- soc_litedramcore_choose_cmd_grant <= 3'd7;
- end else begin
- if (soc_litedramcore_choose_cmd_request[0]) begin
- soc_litedramcore_choose_cmd_grant <= 1'd0;
- end
- end
- end
- end
- end
- end
- end
- end
- 2'd2: begin
- if (soc_litedramcore_choose_cmd_request[3]) begin
- soc_litedramcore_choose_cmd_grant <= 2'd3;
- end else begin
- if (soc_litedramcore_choose_cmd_request[4]) begin
- soc_litedramcore_choose_cmd_grant <= 3'd4;
- end else begin
- if (soc_litedramcore_choose_cmd_request[5]) begin
- soc_litedramcore_choose_cmd_grant <= 3'd5;
- end else begin
- if (soc_litedramcore_choose_cmd_request[6]) begin
- soc_litedramcore_choose_cmd_grant <= 3'd6;
- end else begin
- if (soc_litedramcore_choose_cmd_request[7]) begin
- soc_litedramcore_choose_cmd_grant <= 3'd7;
- end else begin
- if (soc_litedramcore_choose_cmd_request[0]) begin
- soc_litedramcore_choose_cmd_grant <= 1'd0;
- end else begin
- if (soc_litedramcore_choose_cmd_request[1]) begin
- soc_litedramcore_choose_cmd_grant <= 1'd1;
- end
- end
- end
- end
- end
- end
- end
- end
- 2'd3: begin
- if (soc_litedramcore_choose_cmd_request[4]) begin
- soc_litedramcore_choose_cmd_grant <= 3'd4;
- end else begin
- if (soc_litedramcore_choose_cmd_request[5]) begin
- soc_litedramcore_choose_cmd_grant <= 3'd5;
- end else begin
- if (soc_litedramcore_choose_cmd_request[6]) begin
- soc_litedramcore_choose_cmd_grant <= 3'd6;
- end else begin
- if (soc_litedramcore_choose_cmd_request[7]) begin
- soc_litedramcore_choose_cmd_grant <= 3'd7;
- end else begin
- if (soc_litedramcore_choose_cmd_request[0]) begin
- soc_litedramcore_choose_cmd_grant <= 1'd0;
- end else begin
- if (soc_litedramcore_choose_cmd_request[1]) begin
- soc_litedramcore_choose_cmd_grant <= 1'd1;
- end else begin
- if (soc_litedramcore_choose_cmd_request[2]) begin
- soc_litedramcore_choose_cmd_grant <= 2'd2;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd4: begin
- if (soc_litedramcore_choose_cmd_request[5]) begin
- soc_litedramcore_choose_cmd_grant <= 3'd5;
- end else begin
- if (soc_litedramcore_choose_cmd_request[6]) begin
- soc_litedramcore_choose_cmd_grant <= 3'd6;
- end else begin
- if (soc_litedramcore_choose_cmd_request[7]) begin
- soc_litedramcore_choose_cmd_grant <= 3'd7;
- end else begin
- if (soc_litedramcore_choose_cmd_request[0]) begin
- soc_litedramcore_choose_cmd_grant <= 1'd0;
- end else begin
- if (soc_litedramcore_choose_cmd_request[1]) begin
- soc_litedramcore_choose_cmd_grant <= 1'd1;
- end else begin
- if (soc_litedramcore_choose_cmd_request[2]) begin
- soc_litedramcore_choose_cmd_grant <= 2'd2;
- end else begin
- if (soc_litedramcore_choose_cmd_request[3]) begin
- soc_litedramcore_choose_cmd_grant <= 2'd3;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd5: begin
- if (soc_litedramcore_choose_cmd_request[6]) begin
- soc_litedramcore_choose_cmd_grant <= 3'd6;
- end else begin
- if (soc_litedramcore_choose_cmd_request[7]) begin
- soc_litedramcore_choose_cmd_grant <= 3'd7;
- end else begin
- if (soc_litedramcore_choose_cmd_request[0]) begin
- soc_litedramcore_choose_cmd_grant <= 1'd0;
- end else begin
- if (soc_litedramcore_choose_cmd_request[1]) begin
- soc_litedramcore_choose_cmd_grant <= 1'd1;
- end else begin
- if (soc_litedramcore_choose_cmd_request[2]) begin
- soc_litedramcore_choose_cmd_grant <= 2'd2;
- end else begin
- if (soc_litedramcore_choose_cmd_request[3]) begin
- soc_litedramcore_choose_cmd_grant <= 2'd3;
- end else begin
- if (soc_litedramcore_choose_cmd_request[4]) begin
- soc_litedramcore_choose_cmd_grant <= 3'd4;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd6: begin
- if (soc_litedramcore_choose_cmd_request[7]) begin
- soc_litedramcore_choose_cmd_grant <= 3'd7;
- end else begin
- if (soc_litedramcore_choose_cmd_request[0]) begin
- soc_litedramcore_choose_cmd_grant <= 1'd0;
- end else begin
- if (soc_litedramcore_choose_cmd_request[1]) begin
- soc_litedramcore_choose_cmd_grant <= 1'd1;
- end else begin
- if (soc_litedramcore_choose_cmd_request[2]) begin
- soc_litedramcore_choose_cmd_grant <= 2'd2;
- end else begin
- if (soc_litedramcore_choose_cmd_request[3]) begin
- soc_litedramcore_choose_cmd_grant <= 2'd3;
- end else begin
- if (soc_litedramcore_choose_cmd_request[4]) begin
- soc_litedramcore_choose_cmd_grant <= 3'd4;
- end else begin
- if (soc_litedramcore_choose_cmd_request[5]) begin
- soc_litedramcore_choose_cmd_grant <= 3'd5;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd7: begin
- if (soc_litedramcore_choose_cmd_request[0]) begin
- soc_litedramcore_choose_cmd_grant <= 1'd0;
- end else begin
- if (soc_litedramcore_choose_cmd_request[1]) begin
- soc_litedramcore_choose_cmd_grant <= 1'd1;
- end else begin
- if (soc_litedramcore_choose_cmd_request[2]) begin
- soc_litedramcore_choose_cmd_grant <= 2'd2;
- end else begin
- if (soc_litedramcore_choose_cmd_request[3]) begin
- soc_litedramcore_choose_cmd_grant <= 2'd3;
- end else begin
- if (soc_litedramcore_choose_cmd_request[4]) begin
- soc_litedramcore_choose_cmd_grant <= 3'd4;
- end else begin
- if (soc_litedramcore_choose_cmd_request[5]) begin
- soc_litedramcore_choose_cmd_grant <= 3'd5;
- end else begin
- if (soc_litedramcore_choose_cmd_request[6]) begin
- soc_litedramcore_choose_cmd_grant <= 3'd6;
- end
- end
- end
- end
- end
- end
- end
- end
- endcase
- end
- if (soc_litedramcore_choose_req_ce) begin
- case (soc_litedramcore_choose_req_grant)
- 1'd0: begin
- if (soc_litedramcore_choose_req_request[1]) begin
- soc_litedramcore_choose_req_grant <= 1'd1;
- end else begin
- if (soc_litedramcore_choose_req_request[2]) begin
- soc_litedramcore_choose_req_grant <= 2'd2;
- end else begin
- if (soc_litedramcore_choose_req_request[3]) begin
- soc_litedramcore_choose_req_grant <= 2'd3;
- end else begin
- if (soc_litedramcore_choose_req_request[4]) begin
- soc_litedramcore_choose_req_grant <= 3'd4;
- end else begin
- if (soc_litedramcore_choose_req_request[5]) begin
- soc_litedramcore_choose_req_grant <= 3'd5;
- end else begin
- if (soc_litedramcore_choose_req_request[6]) begin
- soc_litedramcore_choose_req_grant <= 3'd6;
- end else begin
- if (soc_litedramcore_choose_req_request[7]) begin
- soc_litedramcore_choose_req_grant <= 3'd7;
- end
- end
- end
- end
- end
- end
- end
- end
- 1'd1: begin
- if (soc_litedramcore_choose_req_request[2]) begin
- soc_litedramcore_choose_req_grant <= 2'd2;
- end else begin
- if (soc_litedramcore_choose_req_request[3]) begin
- soc_litedramcore_choose_req_grant <= 2'd3;
- end else begin
- if (soc_litedramcore_choose_req_request[4]) begin
- soc_litedramcore_choose_req_grant <= 3'd4;
- end else begin
- if (soc_litedramcore_choose_req_request[5]) begin
- soc_litedramcore_choose_req_grant <= 3'd5;
- end else begin
- if (soc_litedramcore_choose_req_request[6]) begin
- soc_litedramcore_choose_req_grant <= 3'd6;
- end else begin
- if (soc_litedramcore_choose_req_request[7]) begin
- soc_litedramcore_choose_req_grant <= 3'd7;
- end else begin
- if (soc_litedramcore_choose_req_request[0]) begin
- soc_litedramcore_choose_req_grant <= 1'd0;
- end
- end
- end
- end
- end
- end
- end
- end
- 2'd2: begin
- if (soc_litedramcore_choose_req_request[3]) begin
- soc_litedramcore_choose_req_grant <= 2'd3;
- end else begin
- if (soc_litedramcore_choose_req_request[4]) begin
- soc_litedramcore_choose_req_grant <= 3'd4;
- end else begin
- if (soc_litedramcore_choose_req_request[5]) begin
- soc_litedramcore_choose_req_grant <= 3'd5;
- end else begin
- if (soc_litedramcore_choose_req_request[6]) begin
- soc_litedramcore_choose_req_grant <= 3'd6;
- end else begin
- if (soc_litedramcore_choose_req_request[7]) begin
- soc_litedramcore_choose_req_grant <= 3'd7;
- end else begin
- if (soc_litedramcore_choose_req_request[0]) begin
- soc_litedramcore_choose_req_grant <= 1'd0;
- end else begin
- if (soc_litedramcore_choose_req_request[1]) begin
- soc_litedramcore_choose_req_grant <= 1'd1;
- end
- end
- end
- end
- end
- end
- end
- end
- 2'd3: begin
- if (soc_litedramcore_choose_req_request[4]) begin
- soc_litedramcore_choose_req_grant <= 3'd4;
- end else begin
- if (soc_litedramcore_choose_req_request[5]) begin
- soc_litedramcore_choose_req_grant <= 3'd5;
- end else begin
- if (soc_litedramcore_choose_req_request[6]) begin
- soc_litedramcore_choose_req_grant <= 3'd6;
- end else begin
- if (soc_litedramcore_choose_req_request[7]) begin
- soc_litedramcore_choose_req_grant <= 3'd7;
- end else begin
- if (soc_litedramcore_choose_req_request[0]) begin
- soc_litedramcore_choose_req_grant <= 1'd0;
- end else begin
- if (soc_litedramcore_choose_req_request[1]) begin
- soc_litedramcore_choose_req_grant <= 1'd1;
- end else begin
- if (soc_litedramcore_choose_req_request[2]) begin
- soc_litedramcore_choose_req_grant <= 2'd2;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd4: begin
- if (soc_litedramcore_choose_req_request[5]) begin
- soc_litedramcore_choose_req_grant <= 3'd5;
- end else begin
- if (soc_litedramcore_choose_req_request[6]) begin
- soc_litedramcore_choose_req_grant <= 3'd6;
- end else begin
- if (soc_litedramcore_choose_req_request[7]) begin
- soc_litedramcore_choose_req_grant <= 3'd7;
- end else begin
- if (soc_litedramcore_choose_req_request[0]) begin
- soc_litedramcore_choose_req_grant <= 1'd0;
- end else begin
- if (soc_litedramcore_choose_req_request[1]) begin
- soc_litedramcore_choose_req_grant <= 1'd1;
- end else begin
- if (soc_litedramcore_choose_req_request[2]) begin
- soc_litedramcore_choose_req_grant <= 2'd2;
- end else begin
- if (soc_litedramcore_choose_req_request[3]) begin
- soc_litedramcore_choose_req_grant <= 2'd3;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd5: begin
- if (soc_litedramcore_choose_req_request[6]) begin
- soc_litedramcore_choose_req_grant <= 3'd6;
- end else begin
- if (soc_litedramcore_choose_req_request[7]) begin
- soc_litedramcore_choose_req_grant <= 3'd7;
- end else begin
- if (soc_litedramcore_choose_req_request[0]) begin
- soc_litedramcore_choose_req_grant <= 1'd0;
- end else begin
- if (soc_litedramcore_choose_req_request[1]) begin
- soc_litedramcore_choose_req_grant <= 1'd1;
- end else begin
- if (soc_litedramcore_choose_req_request[2]) begin
- soc_litedramcore_choose_req_grant <= 2'd2;
- end else begin
- if (soc_litedramcore_choose_req_request[3]) begin
- soc_litedramcore_choose_req_grant <= 2'd3;
- end else begin
- if (soc_litedramcore_choose_req_request[4]) begin
- soc_litedramcore_choose_req_grant <= 3'd4;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd6: begin
- if (soc_litedramcore_choose_req_request[7]) begin
- soc_litedramcore_choose_req_grant <= 3'd7;
- end else begin
- if (soc_litedramcore_choose_req_request[0]) begin
- soc_litedramcore_choose_req_grant <= 1'd0;
- end else begin
- if (soc_litedramcore_choose_req_request[1]) begin
- soc_litedramcore_choose_req_grant <= 1'd1;
- end else begin
- if (soc_litedramcore_choose_req_request[2]) begin
- soc_litedramcore_choose_req_grant <= 2'd2;
- end else begin
- if (soc_litedramcore_choose_req_request[3]) begin
- soc_litedramcore_choose_req_grant <= 2'd3;
- end else begin
- if (soc_litedramcore_choose_req_request[4]) begin
- soc_litedramcore_choose_req_grant <= 3'd4;
- end else begin
- if (soc_litedramcore_choose_req_request[5]) begin
- soc_litedramcore_choose_req_grant <= 3'd5;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd7: begin
- if (soc_litedramcore_choose_req_request[0]) begin
- soc_litedramcore_choose_req_grant <= 1'd0;
- end else begin
- if (soc_litedramcore_choose_req_request[1]) begin
- soc_litedramcore_choose_req_grant <= 1'd1;
- end else begin
- if (soc_litedramcore_choose_req_request[2]) begin
- soc_litedramcore_choose_req_grant <= 2'd2;
- end else begin
- if (soc_litedramcore_choose_req_request[3]) begin
- soc_litedramcore_choose_req_grant <= 2'd3;
- end else begin
- if (soc_litedramcore_choose_req_request[4]) begin
- soc_litedramcore_choose_req_grant <= 3'd4;
- end else begin
- if (soc_litedramcore_choose_req_request[5]) begin
- soc_litedramcore_choose_req_grant <= 3'd5;
- end else begin
- if (soc_litedramcore_choose_req_request[6]) begin
- soc_litedramcore_choose_req_grant <= 3'd6;
- end
- end
- end
- end
- end
- end
- end
- end
- endcase
- end
- soc_litedramcore_dfi_p0_cs_n <= 1'd0;
- soc_litedramcore_dfi_p0_bank <= array_muxed0;
- soc_litedramcore_dfi_p0_address <= array_muxed1;
- soc_litedramcore_dfi_p0_cas_n <= (~array_muxed2);
- soc_litedramcore_dfi_p0_ras_n <= (~array_muxed3);
- soc_litedramcore_dfi_p0_we_n <= (~array_muxed4);
- soc_litedramcore_dfi_p0_rddata_en <= array_muxed5;
- soc_litedramcore_dfi_p0_wrdata_en <= array_muxed6;
- soc_litedramcore_dfi_p1_cs_n <= 1'd0;
- soc_litedramcore_dfi_p1_bank <= array_muxed7;
- soc_litedramcore_dfi_p1_address <= array_muxed8;
- soc_litedramcore_dfi_p1_cas_n <= (~array_muxed9);
- soc_litedramcore_dfi_p1_ras_n <= (~array_muxed10);
- soc_litedramcore_dfi_p1_we_n <= (~array_muxed11);
- soc_litedramcore_dfi_p1_rddata_en <= array_muxed12;
- soc_litedramcore_dfi_p1_wrdata_en <= array_muxed13;
- soc_litedramcore_dfi_p2_cs_n <= 1'd0;
- soc_litedramcore_dfi_p2_bank <= array_muxed14;
- soc_litedramcore_dfi_p2_address <= array_muxed15;
- soc_litedramcore_dfi_p2_cas_n <= (~array_muxed16);
- soc_litedramcore_dfi_p2_ras_n <= (~array_muxed17);
- soc_litedramcore_dfi_p2_we_n <= (~array_muxed18);
- soc_litedramcore_dfi_p2_rddata_en <= array_muxed19;
- soc_litedramcore_dfi_p2_wrdata_en <= array_muxed20;
- soc_litedramcore_dfi_p3_cs_n <= 1'd0;
- soc_litedramcore_dfi_p3_bank <= array_muxed21;
- soc_litedramcore_dfi_p3_address <= array_muxed22;
- soc_litedramcore_dfi_p3_cas_n <= (~array_muxed23);
- soc_litedramcore_dfi_p3_ras_n <= (~array_muxed24);
- soc_litedramcore_dfi_p3_we_n <= (~array_muxed25);
- soc_litedramcore_dfi_p3_rddata_en <= array_muxed26;
- soc_litedramcore_dfi_p3_wrdata_en <= array_muxed27;
- if (soc_litedramcore_trrdcon_valid) begin
- soc_litedramcore_trrdcon_count <= 1'd1;
- if (1'd0) begin
- soc_litedramcore_trrdcon_ready <= 1'd1;
- end else begin
- soc_litedramcore_trrdcon_ready <= 1'd0;
- end
- end else begin
- if ((~soc_litedramcore_trrdcon_ready)) begin
- soc_litedramcore_trrdcon_count <= (soc_litedramcore_trrdcon_count - 1'd1);
- if ((soc_litedramcore_trrdcon_count == 1'd1)) begin
- soc_litedramcore_trrdcon_ready <= 1'd1;
- end
- end
- end
- soc_litedramcore_tfawcon_window <= {soc_litedramcore_tfawcon_window, soc_litedramcore_tfawcon_valid};
- if ((soc_litedramcore_tfawcon_count < 3'd4)) begin
- if ((soc_litedramcore_tfawcon_count == 2'd3)) begin
- soc_litedramcore_tfawcon_ready <= (~soc_litedramcore_tfawcon_valid);
- end else begin
- soc_litedramcore_tfawcon_ready <= 1'd1;
- end
- end
- if (soc_litedramcore_tccdcon_valid) begin
- soc_litedramcore_tccdcon_count <= 1'd0;
- if (1'd1) begin
- soc_litedramcore_tccdcon_ready <= 1'd1;
- end else begin
- soc_litedramcore_tccdcon_ready <= 1'd0;
- end
- end else begin
- if ((~soc_litedramcore_tccdcon_ready)) begin
- soc_litedramcore_tccdcon_count <= (soc_litedramcore_tccdcon_count - 1'd1);
- if ((soc_litedramcore_tccdcon_count == 1'd1)) begin
- soc_litedramcore_tccdcon_ready <= 1'd1;
- end
- end
- end
- if (soc_litedramcore_twtrcon_valid) begin
- soc_litedramcore_twtrcon_count <= 3'd4;
- if (1'd0) begin
- soc_litedramcore_twtrcon_ready <= 1'd1;
- end else begin
- soc_litedramcore_twtrcon_ready <= 1'd0;
- end
- end else begin
- if ((~soc_litedramcore_twtrcon_ready)) begin
- soc_litedramcore_twtrcon_count <= (soc_litedramcore_twtrcon_count - 1'd1);
- if ((soc_litedramcore_twtrcon_count == 1'd1)) begin
- soc_litedramcore_twtrcon_ready <= 1'd1;
- end
- end
- end
- litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state;
- litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & soc_litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & soc_litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & soc_litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & soc_litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & soc_litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & soc_litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & soc_litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & soc_litedramcore_interface_bank7_wdata_ready));
- litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0;
- litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & soc_litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & soc_litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & soc_litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & soc_litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & soc_litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & soc_litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & soc_litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & soc_litedramcore_interface_bank7_rdata_valid));
- litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0;
- litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1;
- litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2;
- litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3;
- litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4;
- litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5;
- litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6;
- litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7;
- litedramcore_state <= litedramcore_next_state;
- if (litedramcore_dat_w_next_value_ce0) begin
- litedramcore_dat_w <= litedramcore_dat_w_next_value0;
- end
- if (litedramcore_adr_next_value_ce1) begin
- litedramcore_adr <= litedramcore_adr_next_value1;
- end
- if (litedramcore_we_next_value_ce2) begin
- litedramcore_we <= litedramcore_we_next_value2;
- end
- interface0_bank_bus_dat_r <= 1'd0;
- if (csrbank0_sel) begin
- case (interface0_bank_bus_adr[8:0])
- 1'd0: begin
- interface0_bank_bus_dat_r <= csrbank0_init_done0_w;
- end
- 1'd1: begin
- interface0_bank_bus_dat_r <= csrbank0_init_error0_w;
- end
- endcase
- end
- if (csrbank0_init_done0_re) begin
- soc_init_done_storage <= csrbank0_init_done0_r;
- end
- soc_init_done_re <= csrbank0_init_done0_re;
- if (csrbank0_init_error0_re) begin
- soc_init_error_storage <= csrbank0_init_error0_r;
- end
- soc_init_error_re <= csrbank0_init_error0_re;
- interface1_bank_bus_dat_r <= 1'd0;
- if (csrbank1_sel) begin
- case (interface1_bank_bus_adr[8:0])
- 1'd0: begin
- interface1_bank_bus_dat_r <= csrbank1_dfii_control0_w;
- end
- 1'd1: begin
- interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_command0_w;
- end
- 2'd2: begin
- interface1_bank_bus_dat_r <= soc_litedramcore_phaseinjector0_command_issue_w;
- end
- 2'd3: begin
- interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_address0_w;
- end
- 3'd4: begin
- interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_baddress0_w;
- end
- 3'd5: begin
- interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata0_w;
- end
- 3'd6: begin
- interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata_w;
- end
- 3'd7: begin
- interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_command0_w;
- end
- 4'd8: begin
- interface1_bank_bus_dat_r <= soc_litedramcore_phaseinjector1_command_issue_w;
- end
- 4'd9: begin
- interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_address0_w;
- end
- 4'd10: begin
- interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_baddress0_w;
- end
- 4'd11: begin
- interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata0_w;
- end
- 4'd12: begin
- interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata_w;
- end
- 4'd13: begin
- interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_command0_w;
- end
- 4'd14: begin
- interface1_bank_bus_dat_r <= soc_litedramcore_phaseinjector2_command_issue_w;
- end
- 4'd15: begin
- interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_address0_w;
- end
- 5'd16: begin
- interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_baddress0_w;
- end
- 5'd17: begin
- interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata0_w;
- end
- 5'd18: begin
- interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata_w;
- end
- 5'd19: begin
- interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_command0_w;
- end
- 5'd20: begin
- interface1_bank_bus_dat_r <= soc_litedramcore_phaseinjector3_command_issue_w;
- end
- 5'd21: begin
- interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_address0_w;
- end
- 5'd22: begin
- interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_baddress0_w;
- end
- 5'd23: begin
- interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata0_w;
- end
- 5'd24: begin
- interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata_w;
- end
- endcase
- end
- if (csrbank1_dfii_control0_re) begin
- soc_litedramcore_storage[3:0] <= csrbank1_dfii_control0_r;
- end
- soc_litedramcore_re <= csrbank1_dfii_control0_re;
- if (csrbank1_dfii_pi0_command0_re) begin
- soc_litedramcore_phaseinjector0_command_storage[5:0] <= csrbank1_dfii_pi0_command0_r;
- end
- soc_litedramcore_phaseinjector0_command_re <= csrbank1_dfii_pi0_command0_re;
- if (csrbank1_dfii_pi0_address0_re) begin
- soc_litedramcore_phaseinjector0_address_storage[13:0] <= csrbank1_dfii_pi0_address0_r;
- end
- soc_litedramcore_phaseinjector0_address_re <= csrbank1_dfii_pi0_address0_re;
- if (csrbank1_dfii_pi0_baddress0_re) begin
- soc_litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank1_dfii_pi0_baddress0_r;
- end
- soc_litedramcore_phaseinjector0_baddress_re <= csrbank1_dfii_pi0_baddress0_re;
- if (csrbank1_dfii_pi0_wrdata0_re) begin
- soc_litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank1_dfii_pi0_wrdata0_r;
- end
- soc_litedramcore_phaseinjector0_wrdata_re <= csrbank1_dfii_pi0_wrdata0_re;
- soc_litedramcore_phaseinjector0_rddata_re <= csrbank1_dfii_pi0_rddata_re;
- if (csrbank1_dfii_pi1_command0_re) begin
- soc_litedramcore_phaseinjector1_command_storage[5:0] <= csrbank1_dfii_pi1_command0_r;
- end
- soc_litedramcore_phaseinjector1_command_re <= csrbank1_dfii_pi1_command0_re;
- if (csrbank1_dfii_pi1_address0_re) begin
- soc_litedramcore_phaseinjector1_address_storage[13:0] <= csrbank1_dfii_pi1_address0_r;
- end
- soc_litedramcore_phaseinjector1_address_re <= csrbank1_dfii_pi1_address0_re;
- if (csrbank1_dfii_pi1_baddress0_re) begin
- soc_litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank1_dfii_pi1_baddress0_r;
- end
- soc_litedramcore_phaseinjector1_baddress_re <= csrbank1_dfii_pi1_baddress0_re;
- if (csrbank1_dfii_pi1_wrdata0_re) begin
- soc_litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank1_dfii_pi1_wrdata0_r;
- end
- soc_litedramcore_phaseinjector1_wrdata_re <= csrbank1_dfii_pi1_wrdata0_re;
- soc_litedramcore_phaseinjector1_rddata_re <= csrbank1_dfii_pi1_rddata_re;
- if (csrbank1_dfii_pi2_command0_re) begin
- soc_litedramcore_phaseinjector2_command_storage[5:0] <= csrbank1_dfii_pi2_command0_r;
- end
- soc_litedramcore_phaseinjector2_command_re <= csrbank1_dfii_pi2_command0_re;
- if (csrbank1_dfii_pi2_address0_re) begin
- soc_litedramcore_phaseinjector2_address_storage[13:0] <= csrbank1_dfii_pi2_address0_r;
- end
- soc_litedramcore_phaseinjector2_address_re <= csrbank1_dfii_pi2_address0_re;
- if (csrbank1_dfii_pi2_baddress0_re) begin
- soc_litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank1_dfii_pi2_baddress0_r;
- end
- soc_litedramcore_phaseinjector2_baddress_re <= csrbank1_dfii_pi2_baddress0_re;
- if (csrbank1_dfii_pi2_wrdata0_re) begin
- soc_litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank1_dfii_pi2_wrdata0_r;
- end
- soc_litedramcore_phaseinjector2_wrdata_re <= csrbank1_dfii_pi2_wrdata0_re;
- soc_litedramcore_phaseinjector2_rddata_re <= csrbank1_dfii_pi2_rddata_re;
- if (csrbank1_dfii_pi3_command0_re) begin
- soc_litedramcore_phaseinjector3_command_storage[5:0] <= csrbank1_dfii_pi3_command0_r;
- end
- soc_litedramcore_phaseinjector3_command_re <= csrbank1_dfii_pi3_command0_re;
- if (csrbank1_dfii_pi3_address0_re) begin
- soc_litedramcore_phaseinjector3_address_storage[13:0] <= csrbank1_dfii_pi3_address0_r;
- end
- soc_litedramcore_phaseinjector3_address_re <= csrbank1_dfii_pi3_address0_re;
- if (csrbank1_dfii_pi3_baddress0_re) begin
- soc_litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank1_dfii_pi3_baddress0_r;
- end
- soc_litedramcore_phaseinjector3_baddress_re <= csrbank1_dfii_pi3_baddress0_re;
- if (csrbank1_dfii_pi3_wrdata0_re) begin
- soc_litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank1_dfii_pi3_wrdata0_r;
- end
- soc_litedramcore_phaseinjector3_wrdata_re <= csrbank1_dfii_pi3_wrdata0_re;
- soc_litedramcore_phaseinjector3_rddata_re <= csrbank1_dfii_pi3_rddata_re;
- if (sys_rst) begin
- soc_ddrphy_bankmodel0_active <= 1'd0;
- soc_ddrphy_bankmodel0_row <= 14'd0;
- soc_ddrphy_bankmodel1_active <= 1'd0;
- soc_ddrphy_bankmodel1_row <= 14'd0;
- soc_ddrphy_bankmodel2_active <= 1'd0;
- soc_ddrphy_bankmodel2_row <= 14'd0;
- soc_ddrphy_bankmodel3_active <= 1'd0;
- soc_ddrphy_bankmodel3_row <= 14'd0;
- soc_ddrphy_bankmodel4_active <= 1'd0;
- soc_ddrphy_bankmodel4_row <= 14'd0;
- soc_ddrphy_bankmodel5_active <= 1'd0;
- soc_ddrphy_bankmodel5_row <= 14'd0;
- soc_ddrphy_bankmodel6_active <= 1'd0;
- soc_ddrphy_bankmodel6_row <= 14'd0;
- soc_ddrphy_bankmodel7_active <= 1'd0;
- soc_ddrphy_bankmodel7_row <= 14'd0;
- soc_ddrphy_new_bank_write0 <= 1'd0;
- soc_ddrphy_new_bank_write_col0 <= 10'd0;
- soc_ddrphy_new_bank_write1 <= 1'd0;
- soc_ddrphy_new_bank_write_col1 <= 10'd0;
- soc_ddrphy_new_bank_write2 <= 1'd0;
- soc_ddrphy_new_bank_write_col2 <= 10'd0;
- soc_ddrphy_new_bank_write3 <= 1'd0;
- soc_ddrphy_new_bank_write_col3 <= 10'd0;
- soc_ddrphy_new_bank_write4 <= 1'd0;
- soc_ddrphy_new_bank_write_col4 <= 10'd0;
- soc_ddrphy_new_bank_write5 <= 1'd0;
- soc_ddrphy_new_bank_write_col5 <= 10'd0;
- soc_ddrphy_new_bank_write6 <= 1'd0;
- soc_ddrphy_new_bank_write_col6 <= 10'd0;
- soc_ddrphy_new_bank_write7 <= 1'd0;
- soc_ddrphy_new_bank_write_col7 <= 10'd0;
- soc_ddrphy_new_banks_read0 <= 1'd0;
- soc_ddrphy_new_banks_read_data0 <= 128'd0;
- soc_ddrphy_new_banks_read1 <= 1'd0;
- soc_ddrphy_new_banks_read_data1 <= 128'd0;
- soc_ddrphy_new_banks_read2 <= 1'd0;
- soc_ddrphy_new_banks_read_data2 <= 128'd0;
- soc_ddrphy_new_banks_read3 <= 1'd0;
- soc_ddrphy_new_banks_read_data3 <= 128'd0;
- soc_ddrphy_new_banks_read4 <= 1'd0;
- soc_ddrphy_new_banks_read_data4 <= 128'd0;
- soc_ddrphy_new_banks_read5 <= 1'd0;
- soc_ddrphy_new_banks_read_data5 <= 128'd0;
- soc_ddrphy_new_banks_read6 <= 1'd0;
- soc_ddrphy_new_banks_read_data6 <= 128'd0;
- soc_ddrphy_new_banks_read7 <= 1'd0;
- soc_ddrphy_new_banks_read_data7 <= 128'd0;
- soc_litedramcore_storage <= 4'd1;
- soc_litedramcore_re <= 1'd0;
- soc_litedramcore_phaseinjector0_command_storage <= 6'd0;
- soc_litedramcore_phaseinjector0_command_re <= 1'd0;
- soc_litedramcore_phaseinjector0_address_re <= 1'd0;
- soc_litedramcore_phaseinjector0_baddress_re <= 1'd0;
- soc_litedramcore_phaseinjector0_wrdata_re <= 1'd0;
- soc_litedramcore_phaseinjector0_rddata_status <= 32'd0;
- soc_litedramcore_phaseinjector0_rddata_re <= 1'd0;
- soc_litedramcore_phaseinjector1_command_storage <= 6'd0;
- soc_litedramcore_phaseinjector1_command_re <= 1'd0;
- soc_litedramcore_phaseinjector1_address_re <= 1'd0;
- soc_litedramcore_phaseinjector1_baddress_re <= 1'd0;
- soc_litedramcore_phaseinjector1_wrdata_re <= 1'd0;
- soc_litedramcore_phaseinjector1_rddata_status <= 32'd0;
- soc_litedramcore_phaseinjector1_rddata_re <= 1'd0;
- soc_litedramcore_phaseinjector2_command_storage <= 6'd0;
- soc_litedramcore_phaseinjector2_command_re <= 1'd0;
- soc_litedramcore_phaseinjector2_address_re <= 1'd0;
- soc_litedramcore_phaseinjector2_baddress_re <= 1'd0;
- soc_litedramcore_phaseinjector2_wrdata_re <= 1'd0;
- soc_litedramcore_phaseinjector2_rddata_status <= 32'd0;
- soc_litedramcore_phaseinjector2_rddata_re <= 1'd0;
- soc_litedramcore_phaseinjector3_command_storage <= 6'd0;
- soc_litedramcore_phaseinjector3_command_re <= 1'd0;
- soc_litedramcore_phaseinjector3_address_re <= 1'd0;
- soc_litedramcore_phaseinjector3_baddress_re <= 1'd0;
- soc_litedramcore_phaseinjector3_wrdata_re <= 1'd0;
- soc_litedramcore_phaseinjector3_rddata_status <= 32'd0;
- soc_litedramcore_phaseinjector3_rddata_re <= 1'd0;
- soc_litedramcore_dfi_p0_address <= 14'd0;
- soc_litedramcore_dfi_p0_bank <= 3'd0;
- soc_litedramcore_dfi_p0_cas_n <= 1'd1;
- soc_litedramcore_dfi_p0_cs_n <= 1'd1;
- soc_litedramcore_dfi_p0_ras_n <= 1'd1;
- soc_litedramcore_dfi_p0_we_n <= 1'd1;
- soc_litedramcore_dfi_p0_wrdata_en <= 1'd0;
- soc_litedramcore_dfi_p0_rddata_en <= 1'd0;
- soc_litedramcore_dfi_p1_address <= 14'd0;
- soc_litedramcore_dfi_p1_bank <= 3'd0;
- soc_litedramcore_dfi_p1_cas_n <= 1'd1;
- soc_litedramcore_dfi_p1_cs_n <= 1'd1;
- soc_litedramcore_dfi_p1_ras_n <= 1'd1;
- soc_litedramcore_dfi_p1_we_n <= 1'd1;
- soc_litedramcore_dfi_p1_wrdata_en <= 1'd0;
- soc_litedramcore_dfi_p1_rddata_en <= 1'd0;
- soc_litedramcore_dfi_p2_address <= 14'd0;
- soc_litedramcore_dfi_p2_bank <= 3'd0;
- soc_litedramcore_dfi_p2_cas_n <= 1'd1;
- soc_litedramcore_dfi_p2_cs_n <= 1'd1;
- soc_litedramcore_dfi_p2_ras_n <= 1'd1;
- soc_litedramcore_dfi_p2_we_n <= 1'd1;
- soc_litedramcore_dfi_p2_wrdata_en <= 1'd0;
- soc_litedramcore_dfi_p2_rddata_en <= 1'd0;
- soc_litedramcore_dfi_p3_address <= 14'd0;
- soc_litedramcore_dfi_p3_bank <= 3'd0;
- soc_litedramcore_dfi_p3_cas_n <= 1'd1;
- soc_litedramcore_dfi_p3_cs_n <= 1'd1;
- soc_litedramcore_dfi_p3_ras_n <= 1'd1;
- soc_litedramcore_dfi_p3_we_n <= 1'd1;
- soc_litedramcore_dfi_p3_wrdata_en <= 1'd0;
- soc_litedramcore_dfi_p3_rddata_en <= 1'd0;
- soc_litedramcore_cmd_payload_a <= 14'd0;
- soc_litedramcore_cmd_payload_ba <= 3'd0;
- soc_litedramcore_cmd_payload_cas <= 1'd0;
- soc_litedramcore_cmd_payload_ras <= 1'd0;
- soc_litedramcore_cmd_payload_we <= 1'd0;
- soc_litedramcore_timer_count1 <= 10'd781;
- soc_litedramcore_postponer_req_o <= 1'd0;
- soc_litedramcore_postponer_count <= 1'd0;
- soc_litedramcore_sequencer_done1 <= 1'd0;
- soc_litedramcore_sequencer_counter <= 6'd0;
- soc_litedramcore_sequencer_count <= 1'd0;
- soc_litedramcore_zqcs_timer_count1 <= 27'd99999999;
- soc_litedramcore_zqcs_executer_done <= 1'd0;
- soc_litedramcore_zqcs_executer_counter <= 5'd0;
- soc_litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0;
- soc_litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0;
- soc_litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0;
- soc_litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0;
- soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we <= 1'd0;
- soc_litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= 21'd0;
- soc_litedramcore_bankmachine0_row <= 14'd0;
- soc_litedramcore_bankmachine0_row_opened <= 1'd0;
- soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
- soc_litedramcore_bankmachine0_twtpcon_count <= 3'd0;
- soc_litedramcore_bankmachine0_trccon_ready <= 1'd0;
- soc_litedramcore_bankmachine0_trccon_count <= 3'd0;
- soc_litedramcore_bankmachine0_trascon_ready <= 1'd0;
- soc_litedramcore_bankmachine0_trascon_count <= 3'd0;
- soc_litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0;
- soc_litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0;
- soc_litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0;
- soc_litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0;
- soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we <= 1'd0;
- soc_litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= 21'd0;
- soc_litedramcore_bankmachine1_row <= 14'd0;
- soc_litedramcore_bankmachine1_row_opened <= 1'd0;
- soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
- soc_litedramcore_bankmachine1_twtpcon_count <= 3'd0;
- soc_litedramcore_bankmachine1_trccon_ready <= 1'd0;
- soc_litedramcore_bankmachine1_trccon_count <= 3'd0;
- soc_litedramcore_bankmachine1_trascon_ready <= 1'd0;
- soc_litedramcore_bankmachine1_trascon_count <= 3'd0;
- soc_litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0;
- soc_litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0;
- soc_litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0;
- soc_litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0;
- soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we <= 1'd0;
- soc_litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= 21'd0;
- soc_litedramcore_bankmachine2_row <= 14'd0;
- soc_litedramcore_bankmachine2_row_opened <= 1'd0;
- soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
- soc_litedramcore_bankmachine2_twtpcon_count <= 3'd0;
- soc_litedramcore_bankmachine2_trccon_ready <= 1'd0;
- soc_litedramcore_bankmachine2_trccon_count <= 3'd0;
- soc_litedramcore_bankmachine2_trascon_ready <= 1'd0;
- soc_litedramcore_bankmachine2_trascon_count <= 3'd0;
- soc_litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0;
- soc_litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0;
- soc_litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0;
- soc_litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0;
- soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we <= 1'd0;
- soc_litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= 21'd0;
- soc_litedramcore_bankmachine3_row <= 14'd0;
- soc_litedramcore_bankmachine3_row_opened <= 1'd0;
- soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
- soc_litedramcore_bankmachine3_twtpcon_count <= 3'd0;
- soc_litedramcore_bankmachine3_trccon_ready <= 1'd0;
- soc_litedramcore_bankmachine3_trccon_count <= 3'd0;
- soc_litedramcore_bankmachine3_trascon_ready <= 1'd0;
- soc_litedramcore_bankmachine3_trascon_count <= 3'd0;
- soc_litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0;
- soc_litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0;
- soc_litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0;
- soc_litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0;
- soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we <= 1'd0;
- soc_litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= 21'd0;
- soc_litedramcore_bankmachine4_row <= 14'd0;
- soc_litedramcore_bankmachine4_row_opened <= 1'd0;
- soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
- soc_litedramcore_bankmachine4_twtpcon_count <= 3'd0;
- soc_litedramcore_bankmachine4_trccon_ready <= 1'd0;
- soc_litedramcore_bankmachine4_trccon_count <= 3'd0;
- soc_litedramcore_bankmachine4_trascon_ready <= 1'd0;
- soc_litedramcore_bankmachine4_trascon_count <= 3'd0;
- soc_litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0;
- soc_litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0;
- soc_litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0;
- soc_litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0;
- soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we <= 1'd0;
- soc_litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= 21'd0;
- soc_litedramcore_bankmachine5_row <= 14'd0;
- soc_litedramcore_bankmachine5_row_opened <= 1'd0;
- soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
- soc_litedramcore_bankmachine5_twtpcon_count <= 3'd0;
- soc_litedramcore_bankmachine5_trccon_ready <= 1'd0;
- soc_litedramcore_bankmachine5_trccon_count <= 3'd0;
- soc_litedramcore_bankmachine5_trascon_ready <= 1'd0;
- soc_litedramcore_bankmachine5_trascon_count <= 3'd0;
- soc_litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0;
- soc_litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0;
- soc_litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0;
- soc_litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0;
- soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we <= 1'd0;
- soc_litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= 21'd0;
- soc_litedramcore_bankmachine6_row <= 14'd0;
- soc_litedramcore_bankmachine6_row_opened <= 1'd0;
- soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
- soc_litedramcore_bankmachine6_twtpcon_count <= 3'd0;
- soc_litedramcore_bankmachine6_trccon_ready <= 1'd0;
- soc_litedramcore_bankmachine6_trccon_count <= 3'd0;
- soc_litedramcore_bankmachine6_trascon_ready <= 1'd0;
- soc_litedramcore_bankmachine6_trascon_count <= 3'd0;
- soc_litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0;
- soc_litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0;
- soc_litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0;
- soc_litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0;
- soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we <= 1'd0;
- soc_litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= 21'd0;
- soc_litedramcore_bankmachine7_row <= 14'd0;
- soc_litedramcore_bankmachine7_row_opened <= 1'd0;
- soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
- soc_litedramcore_bankmachine7_twtpcon_count <= 3'd0;
- soc_litedramcore_bankmachine7_trccon_ready <= 1'd0;
- soc_litedramcore_bankmachine7_trccon_count <= 3'd0;
- soc_litedramcore_bankmachine7_trascon_ready <= 1'd0;
- soc_litedramcore_bankmachine7_trascon_count <= 3'd0;
- soc_litedramcore_choose_cmd_grant <= 3'd0;
- soc_litedramcore_choose_req_grant <= 3'd0;
- soc_litedramcore_trrdcon_ready <= 1'd0;
- soc_litedramcore_trrdcon_count <= 1'd0;
- soc_litedramcore_tfawcon_ready <= 1'd1;
- soc_litedramcore_tfawcon_window <= 5'd0;
- soc_litedramcore_tccdcon_ready <= 1'd0;
- soc_litedramcore_tccdcon_count <= 1'd0;
- soc_litedramcore_twtrcon_ready <= 1'd0;
- soc_litedramcore_twtrcon_count <= 3'd0;
- soc_litedramcore_time0 <= 5'd0;
- soc_litedramcore_time1 <= 4'd0;
- soc_init_done_storage <= 1'd0;
- soc_init_done_re <= 1'd0;
- soc_init_error_storage <= 1'd0;
- soc_init_error_re <= 1'd0;
- litedramcore_we <= 1'd0;
- litedramcore_refresher_state <= 2'd0;
- litedramcore_bankmachine0_state <= 4'd0;
- litedramcore_bankmachine1_state <= 4'd0;
- litedramcore_bankmachine2_state <= 4'd0;
- litedramcore_bankmachine3_state <= 4'd0;
- litedramcore_bankmachine4_state <= 4'd0;
- litedramcore_bankmachine5_state <= 4'd0;
- litedramcore_bankmachine6_state <= 4'd0;
- litedramcore_bankmachine7_state <= 4'd0;
- litedramcore_multiplexer_state <= 4'd0;
- litedramcore_new_master_wdata_ready0 <= 1'd0;
- litedramcore_new_master_wdata_ready1 <= 1'd0;
- litedramcore_new_master_rdata_valid0 <= 1'd0;
- litedramcore_new_master_rdata_valid1 <= 1'd0;
- litedramcore_new_master_rdata_valid2 <= 1'd0;
- litedramcore_new_master_rdata_valid3 <= 1'd0;
- litedramcore_new_master_rdata_valid4 <= 1'd0;
- litedramcore_new_master_rdata_valid5 <= 1'd0;
- litedramcore_new_master_rdata_valid6 <= 1'd0;
- litedramcore_new_master_rdata_valid7 <= 1'd0;
- litedramcore_new_master_rdata_valid8 <= 1'd0;
- litedramcore_state <= 2'd0;
- end
+ soc_ddrphy_new_bank_write0 <= soc_ddrphy_bank_write0;
+ soc_ddrphy_new_bank_write_col0 <= soc_ddrphy_bank_write_col0;
+ soc_ddrphy_new_bank_write1 <= soc_ddrphy_bank_write1;
+ soc_ddrphy_new_bank_write_col1 <= soc_ddrphy_bank_write_col1;
+ soc_ddrphy_new_bank_write2 <= soc_ddrphy_bank_write2;
+ soc_ddrphy_new_bank_write_col2 <= soc_ddrphy_bank_write_col2;
+ soc_ddrphy_new_bank_write3 <= soc_ddrphy_bank_write3;
+ soc_ddrphy_new_bank_write_col3 <= soc_ddrphy_bank_write_col3;
+ soc_ddrphy_new_bank_write4 <= soc_ddrphy_bank_write4;
+ soc_ddrphy_new_bank_write_col4 <= soc_ddrphy_bank_write_col4;
+ soc_ddrphy_new_bank_write5 <= soc_ddrphy_bank_write5;
+ soc_ddrphy_new_bank_write_col5 <= soc_ddrphy_bank_write_col5;
+ soc_ddrphy_new_bank_write6 <= soc_ddrphy_bank_write6;
+ soc_ddrphy_new_bank_write_col6 <= soc_ddrphy_bank_write_col6;
+ soc_ddrphy_new_bank_write7 <= soc_ddrphy_bank_write7;
+ soc_ddrphy_new_bank_write_col7 <= soc_ddrphy_bank_write_col7;
+ soc_ddrphy_new_banks_read0 <= soc_ddrphy_banks_read;
+ soc_ddrphy_new_banks_read_data0 <= soc_ddrphy_banks_read_data;
+ soc_ddrphy_new_banks_read1 <= soc_ddrphy_new_banks_read0;
+ soc_ddrphy_new_banks_read_data1 <= soc_ddrphy_new_banks_read_data0;
+ soc_ddrphy_new_banks_read2 <= soc_ddrphy_new_banks_read1;
+ soc_ddrphy_new_banks_read_data2 <= soc_ddrphy_new_banks_read_data1;
+ soc_ddrphy_new_banks_read3 <= soc_ddrphy_new_banks_read2;
+ soc_ddrphy_new_banks_read_data3 <= soc_ddrphy_new_banks_read_data2;
+ soc_ddrphy_new_banks_read4 <= soc_ddrphy_new_banks_read3;
+ soc_ddrphy_new_banks_read_data4 <= soc_ddrphy_new_banks_read_data3;
+ soc_ddrphy_new_banks_read5 <= soc_ddrphy_new_banks_read4;
+ soc_ddrphy_new_banks_read_data5 <= soc_ddrphy_new_banks_read_data4;
+ soc_ddrphy_new_banks_read6 <= soc_ddrphy_new_banks_read5;
+ soc_ddrphy_new_banks_read_data6 <= soc_ddrphy_new_banks_read_data5;
+ soc_ddrphy_new_banks_read7 <= soc_ddrphy_new_banks_read6;
+ soc_ddrphy_new_banks_read_data7 <= soc_ddrphy_new_banks_read_data6;
+ if (soc_ddrphy_bankmodel0_precharge) begin
+ soc_ddrphy_bankmodel0_active <= 1'd0;
+ end else begin
+ if (soc_ddrphy_bankmodel0_activate) begin
+ soc_ddrphy_bankmodel0_active <= 1'd1;
+ soc_ddrphy_bankmodel0_row <= soc_ddrphy_bankmodel0_activate_row;
+ end
+ end
+ if (soc_ddrphy_bankmodel1_precharge) begin
+ soc_ddrphy_bankmodel1_active <= 1'd0;
+ end else begin
+ if (soc_ddrphy_bankmodel1_activate) begin
+ soc_ddrphy_bankmodel1_active <= 1'd1;
+ soc_ddrphy_bankmodel1_row <= soc_ddrphy_bankmodel1_activate_row;
+ end
+ end
+ if (soc_ddrphy_bankmodel2_precharge) begin
+ soc_ddrphy_bankmodel2_active <= 1'd0;
+ end else begin
+ if (soc_ddrphy_bankmodel2_activate) begin
+ soc_ddrphy_bankmodel2_active <= 1'd1;
+ soc_ddrphy_bankmodel2_row <= soc_ddrphy_bankmodel2_activate_row;
+ end
+ end
+ if (soc_ddrphy_bankmodel3_precharge) begin
+ soc_ddrphy_bankmodel3_active <= 1'd0;
+ end else begin
+ if (soc_ddrphy_bankmodel3_activate) begin
+ soc_ddrphy_bankmodel3_active <= 1'd1;
+ soc_ddrphy_bankmodel3_row <= soc_ddrphy_bankmodel3_activate_row;
+ end
+ end
+ if (soc_ddrphy_bankmodel4_precharge) begin
+ soc_ddrphy_bankmodel4_active <= 1'd0;
+ end else begin
+ if (soc_ddrphy_bankmodel4_activate) begin
+ soc_ddrphy_bankmodel4_active <= 1'd1;
+ soc_ddrphy_bankmodel4_row <= soc_ddrphy_bankmodel4_activate_row;
+ end
+ end
+ if (soc_ddrphy_bankmodel5_precharge) begin
+ soc_ddrphy_bankmodel5_active <= 1'd0;
+ end else begin
+ if (soc_ddrphy_bankmodel5_activate) begin
+ soc_ddrphy_bankmodel5_active <= 1'd1;
+ soc_ddrphy_bankmodel5_row <= soc_ddrphy_bankmodel5_activate_row;
+ end
+ end
+ if (soc_ddrphy_bankmodel6_precharge) begin
+ soc_ddrphy_bankmodel6_active <= 1'd0;
+ end else begin
+ if (soc_ddrphy_bankmodel6_activate) begin
+ soc_ddrphy_bankmodel6_active <= 1'd1;
+ soc_ddrphy_bankmodel6_row <= soc_ddrphy_bankmodel6_activate_row;
+ end
+ end
+ if (soc_ddrphy_bankmodel7_precharge) begin
+ soc_ddrphy_bankmodel7_active <= 1'd0;
+ end else begin
+ if (soc_ddrphy_bankmodel7_activate) begin
+ soc_ddrphy_bankmodel7_active <= 1'd1;
+ soc_ddrphy_bankmodel7_row <= soc_ddrphy_bankmodel7_activate_row;
+ end
+ end
+ if (soc_litedramcore_csr_dfi_p0_rddata_valid) begin
+ soc_litedramcore_phaseinjector0_rddata_status <= soc_litedramcore_csr_dfi_p0_rddata;
+ end
+ if (soc_litedramcore_csr_dfi_p1_rddata_valid) begin
+ soc_litedramcore_phaseinjector1_rddata_status <= soc_litedramcore_csr_dfi_p1_rddata;
+ end
+ if (soc_litedramcore_csr_dfi_p2_rddata_valid) begin
+ soc_litedramcore_phaseinjector2_rddata_status <= soc_litedramcore_csr_dfi_p2_rddata;
+ end
+ if (soc_litedramcore_csr_dfi_p3_rddata_valid) begin
+ soc_litedramcore_phaseinjector3_rddata_status <= soc_litedramcore_csr_dfi_p3_rddata;
+ end
+ if ((soc_litedramcore_timer_wait & (~soc_litedramcore_timer_done0))) begin
+ soc_litedramcore_timer_count1 <= (soc_litedramcore_timer_count1 - 1'd1);
+ end else begin
+ soc_litedramcore_timer_count1 <= 10'd781;
+ end
+ soc_litedramcore_postponer_req_o <= 1'd0;
+ if (soc_litedramcore_postponer_req_i) begin
+ soc_litedramcore_postponer_count <= (soc_litedramcore_postponer_count - 1'd1);
+ if ((soc_litedramcore_postponer_count == 1'd0)) begin
+ soc_litedramcore_postponer_count <= 1'd0;
+ soc_litedramcore_postponer_req_o <= 1'd1;
+ end
+ end
+ if (soc_litedramcore_sequencer_start0) begin
+ soc_litedramcore_sequencer_count <= 1'd0;
+ end else begin
+ if (soc_litedramcore_sequencer_done1) begin
+ if ((soc_litedramcore_sequencer_count != 1'd0)) begin
+ soc_litedramcore_sequencer_count <= (soc_litedramcore_sequencer_count - 1'd1);
+ end
+ end
+ end
+ soc_litedramcore_cmd_payload_a <= 1'd0;
+ soc_litedramcore_cmd_payload_ba <= 1'd0;
+ soc_litedramcore_cmd_payload_cas <= 1'd0;
+ soc_litedramcore_cmd_payload_ras <= 1'd0;
+ soc_litedramcore_cmd_payload_we <= 1'd0;
+ soc_litedramcore_sequencer_done1 <= 1'd0;
+ if ((soc_litedramcore_sequencer_start1 & (soc_litedramcore_sequencer_counter == 1'd0))) begin
+ soc_litedramcore_cmd_payload_a <= 11'd1024;
+ soc_litedramcore_cmd_payload_ba <= 1'd0;
+ soc_litedramcore_cmd_payload_cas <= 1'd0;
+ soc_litedramcore_cmd_payload_ras <= 1'd1;
+ soc_litedramcore_cmd_payload_we <= 1'd1;
+ end
+ if ((soc_litedramcore_sequencer_counter == 2'd3)) begin
+ soc_litedramcore_cmd_payload_a <= 11'd1024;
+ soc_litedramcore_cmd_payload_ba <= 1'd0;
+ soc_litedramcore_cmd_payload_cas <= 1'd1;
+ soc_litedramcore_cmd_payload_ras <= 1'd1;
+ soc_litedramcore_cmd_payload_we <= 1'd0;
+ end
+ if ((soc_litedramcore_sequencer_counter == 6'd35)) begin
+ soc_litedramcore_cmd_payload_a <= 1'd0;
+ soc_litedramcore_cmd_payload_ba <= 1'd0;
+ soc_litedramcore_cmd_payload_cas <= 1'd0;
+ soc_litedramcore_cmd_payload_ras <= 1'd0;
+ soc_litedramcore_cmd_payload_we <= 1'd0;
+ soc_litedramcore_sequencer_done1 <= 1'd1;
+ end
+ if ((soc_litedramcore_sequencer_counter == 6'd35)) begin
+ soc_litedramcore_sequencer_counter <= 1'd0;
+ end else begin
+ if ((soc_litedramcore_sequencer_counter != 1'd0)) begin
+ soc_litedramcore_sequencer_counter <= (soc_litedramcore_sequencer_counter + 1'd1);
+ end else begin
+ if (soc_litedramcore_sequencer_start1) begin
+ soc_litedramcore_sequencer_counter <= 1'd1;
+ end
+ end
+ end
+ if ((soc_litedramcore_zqcs_timer_wait & (~soc_litedramcore_zqcs_timer_done0))) begin
+ soc_litedramcore_zqcs_timer_count1 <= (soc_litedramcore_zqcs_timer_count1 - 1'd1);
+ end else begin
+ soc_litedramcore_zqcs_timer_count1 <= 27'd99999999;
+ end
+ soc_litedramcore_zqcs_executer_done <= 1'd0;
+ if ((soc_litedramcore_zqcs_executer_start & (soc_litedramcore_zqcs_executer_counter == 1'd0))) begin
+ soc_litedramcore_cmd_payload_a <= 11'd1024;
+ soc_litedramcore_cmd_payload_ba <= 1'd0;
+ soc_litedramcore_cmd_payload_cas <= 1'd0;
+ soc_litedramcore_cmd_payload_ras <= 1'd1;
+ soc_litedramcore_cmd_payload_we <= 1'd1;
+ end
+ if ((soc_litedramcore_zqcs_executer_counter == 2'd3)) begin
+ soc_litedramcore_cmd_payload_a <= 1'd0;
+ soc_litedramcore_cmd_payload_ba <= 1'd0;
+ soc_litedramcore_cmd_payload_cas <= 1'd0;
+ soc_litedramcore_cmd_payload_ras <= 1'd0;
+ soc_litedramcore_cmd_payload_we <= 1'd1;
+ end
+ if ((soc_litedramcore_zqcs_executer_counter == 5'd19)) begin
+ soc_litedramcore_cmd_payload_a <= 1'd0;
+ soc_litedramcore_cmd_payload_ba <= 1'd0;
+ soc_litedramcore_cmd_payload_cas <= 1'd0;
+ soc_litedramcore_cmd_payload_ras <= 1'd0;
+ soc_litedramcore_cmd_payload_we <= 1'd0;
+ soc_litedramcore_zqcs_executer_done <= 1'd1;
+ end
+ if ((soc_litedramcore_zqcs_executer_counter == 5'd19)) begin
+ soc_litedramcore_zqcs_executer_counter <= 1'd0;
+ end else begin
+ if ((soc_litedramcore_zqcs_executer_counter != 1'd0)) begin
+ soc_litedramcore_zqcs_executer_counter <= (soc_litedramcore_zqcs_executer_counter + 1'd1);
+ end else begin
+ if (soc_litedramcore_zqcs_executer_start) begin
+ soc_litedramcore_zqcs_executer_counter <= 1'd1;
+ end
+ end
+ end
+ litedramcore_refresher_state <= litedramcore_refresher_next_state;
+ if (soc_litedramcore_bankmachine0_row_close) begin
+ soc_litedramcore_bankmachine0_row_opened <= 1'd0;
+ end else begin
+ if (soc_litedramcore_bankmachine0_row_open) begin
+ soc_litedramcore_bankmachine0_row_opened <= 1'd1;
+ soc_litedramcore_bankmachine0_row <= soc_litedramcore_bankmachine0_source_source_payload_addr[20:7];
+ end
+ end
+ if (((soc_litedramcore_bankmachine0_syncfifo0_we & soc_litedramcore_bankmachine0_syncfifo0_writable) & (~soc_litedramcore_bankmachine0_replace))) begin
+ soc_litedramcore_bankmachine0_produce <= (soc_litedramcore_bankmachine0_produce + 1'd1);
+ end
+ if (soc_litedramcore_bankmachine0_do_read) begin
+ soc_litedramcore_bankmachine0_consume <= (soc_litedramcore_bankmachine0_consume + 1'd1);
+ end
+ if (((soc_litedramcore_bankmachine0_syncfifo0_we & soc_litedramcore_bankmachine0_syncfifo0_writable) & (~soc_litedramcore_bankmachine0_replace))) begin
+ if ((~soc_litedramcore_bankmachine0_do_read)) begin
+ soc_litedramcore_bankmachine0_level <= (soc_litedramcore_bankmachine0_level + 1'd1);
+ end
+ end else begin
+ if (soc_litedramcore_bankmachine0_do_read) begin
+ soc_litedramcore_bankmachine0_level <= (soc_litedramcore_bankmachine0_level - 1'd1);
+ end
+ end
+ if (((~soc_litedramcore_bankmachine0_pipe_valid_source_valid) | soc_litedramcore_bankmachine0_pipe_valid_source_ready)) begin
+ soc_litedramcore_bankmachine0_pipe_valid_source_valid <= soc_litedramcore_bankmachine0_pipe_valid_sink_valid;
+ soc_litedramcore_bankmachine0_pipe_valid_source_first <= soc_litedramcore_bankmachine0_pipe_valid_sink_first;
+ soc_litedramcore_bankmachine0_pipe_valid_source_last <= soc_litedramcore_bankmachine0_pipe_valid_sink_last;
+ soc_litedramcore_bankmachine0_pipe_valid_source_payload_we <= soc_litedramcore_bankmachine0_pipe_valid_sink_payload_we;
+ soc_litedramcore_bankmachine0_pipe_valid_source_payload_addr <= soc_litedramcore_bankmachine0_pipe_valid_sink_payload_addr;
+ end
+ if (soc_litedramcore_bankmachine0_twtpcon_valid) begin
+ soc_litedramcore_bankmachine0_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+ end else begin
+ soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_litedramcore_bankmachine0_twtpcon_ready)) begin
+ soc_litedramcore_bankmachine0_twtpcon_count <= (soc_litedramcore_bankmachine0_twtpcon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_litedramcore_bankmachine0_trccon_valid) begin
+ soc_litedramcore_bankmachine0_trccon_count <= 3'd5;
+ if (1'd0) begin
+ soc_litedramcore_bankmachine0_trccon_ready <= 1'd1;
+ end else begin
+ soc_litedramcore_bankmachine0_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_litedramcore_bankmachine0_trccon_ready)) begin
+ soc_litedramcore_bankmachine0_trccon_count <= (soc_litedramcore_bankmachine0_trccon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine0_trccon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine0_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_litedramcore_bankmachine0_trascon_valid) begin
+ soc_litedramcore_bankmachine0_trascon_count <= 3'd4;
+ if (1'd0) begin
+ soc_litedramcore_bankmachine0_trascon_ready <= 1'd1;
+ end else begin
+ soc_litedramcore_bankmachine0_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_litedramcore_bankmachine0_trascon_ready)) begin
+ soc_litedramcore_bankmachine0_trascon_count <= (soc_litedramcore_bankmachine0_trascon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine0_trascon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine0_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state;
+ if (soc_litedramcore_bankmachine1_row_close) begin
+ soc_litedramcore_bankmachine1_row_opened <= 1'd0;
+ end else begin
+ if (soc_litedramcore_bankmachine1_row_open) begin
+ soc_litedramcore_bankmachine1_row_opened <= 1'd1;
+ soc_litedramcore_bankmachine1_row <= soc_litedramcore_bankmachine1_source_source_payload_addr[20:7];
+ end
+ end
+ if (((soc_litedramcore_bankmachine1_syncfifo1_we & soc_litedramcore_bankmachine1_syncfifo1_writable) & (~soc_litedramcore_bankmachine1_replace))) begin
+ soc_litedramcore_bankmachine1_produce <= (soc_litedramcore_bankmachine1_produce + 1'd1);
+ end
+ if (soc_litedramcore_bankmachine1_do_read) begin
+ soc_litedramcore_bankmachine1_consume <= (soc_litedramcore_bankmachine1_consume + 1'd1);
+ end
+ if (((soc_litedramcore_bankmachine1_syncfifo1_we & soc_litedramcore_bankmachine1_syncfifo1_writable) & (~soc_litedramcore_bankmachine1_replace))) begin
+ if ((~soc_litedramcore_bankmachine1_do_read)) begin
+ soc_litedramcore_bankmachine1_level <= (soc_litedramcore_bankmachine1_level + 1'd1);
+ end
+ end else begin
+ if (soc_litedramcore_bankmachine1_do_read) begin
+ soc_litedramcore_bankmachine1_level <= (soc_litedramcore_bankmachine1_level - 1'd1);
+ end
+ end
+ if (((~soc_litedramcore_bankmachine1_pipe_valid_source_valid) | soc_litedramcore_bankmachine1_pipe_valid_source_ready)) begin
+ soc_litedramcore_bankmachine1_pipe_valid_source_valid <= soc_litedramcore_bankmachine1_pipe_valid_sink_valid;
+ soc_litedramcore_bankmachine1_pipe_valid_source_first <= soc_litedramcore_bankmachine1_pipe_valid_sink_first;
+ soc_litedramcore_bankmachine1_pipe_valid_source_last <= soc_litedramcore_bankmachine1_pipe_valid_sink_last;
+ soc_litedramcore_bankmachine1_pipe_valid_source_payload_we <= soc_litedramcore_bankmachine1_pipe_valid_sink_payload_we;
+ soc_litedramcore_bankmachine1_pipe_valid_source_payload_addr <= soc_litedramcore_bankmachine1_pipe_valid_sink_payload_addr;
+ end
+ if (soc_litedramcore_bankmachine1_twtpcon_valid) begin
+ soc_litedramcore_bankmachine1_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+ end else begin
+ soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_litedramcore_bankmachine1_twtpcon_ready)) begin
+ soc_litedramcore_bankmachine1_twtpcon_count <= (soc_litedramcore_bankmachine1_twtpcon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_litedramcore_bankmachine1_trccon_valid) begin
+ soc_litedramcore_bankmachine1_trccon_count <= 3'd5;
+ if (1'd0) begin
+ soc_litedramcore_bankmachine1_trccon_ready <= 1'd1;
+ end else begin
+ soc_litedramcore_bankmachine1_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_litedramcore_bankmachine1_trccon_ready)) begin
+ soc_litedramcore_bankmachine1_trccon_count <= (soc_litedramcore_bankmachine1_trccon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine1_trccon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine1_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_litedramcore_bankmachine1_trascon_valid) begin
+ soc_litedramcore_bankmachine1_trascon_count <= 3'd4;
+ if (1'd0) begin
+ soc_litedramcore_bankmachine1_trascon_ready <= 1'd1;
+ end else begin
+ soc_litedramcore_bankmachine1_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_litedramcore_bankmachine1_trascon_ready)) begin
+ soc_litedramcore_bankmachine1_trascon_count <= (soc_litedramcore_bankmachine1_trascon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine1_trascon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine1_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state;
+ if (soc_litedramcore_bankmachine2_row_close) begin
+ soc_litedramcore_bankmachine2_row_opened <= 1'd0;
+ end else begin
+ if (soc_litedramcore_bankmachine2_row_open) begin
+ soc_litedramcore_bankmachine2_row_opened <= 1'd1;
+ soc_litedramcore_bankmachine2_row <= soc_litedramcore_bankmachine2_source_source_payload_addr[20:7];
+ end
+ end
+ if (((soc_litedramcore_bankmachine2_syncfifo2_we & soc_litedramcore_bankmachine2_syncfifo2_writable) & (~soc_litedramcore_bankmachine2_replace))) begin
+ soc_litedramcore_bankmachine2_produce <= (soc_litedramcore_bankmachine2_produce + 1'd1);
+ end
+ if (soc_litedramcore_bankmachine2_do_read) begin
+ soc_litedramcore_bankmachine2_consume <= (soc_litedramcore_bankmachine2_consume + 1'd1);
+ end
+ if (((soc_litedramcore_bankmachine2_syncfifo2_we & soc_litedramcore_bankmachine2_syncfifo2_writable) & (~soc_litedramcore_bankmachine2_replace))) begin
+ if ((~soc_litedramcore_bankmachine2_do_read)) begin
+ soc_litedramcore_bankmachine2_level <= (soc_litedramcore_bankmachine2_level + 1'd1);
+ end
+ end else begin
+ if (soc_litedramcore_bankmachine2_do_read) begin
+ soc_litedramcore_bankmachine2_level <= (soc_litedramcore_bankmachine2_level - 1'd1);
+ end
+ end
+ if (((~soc_litedramcore_bankmachine2_pipe_valid_source_valid) | soc_litedramcore_bankmachine2_pipe_valid_source_ready)) begin
+ soc_litedramcore_bankmachine2_pipe_valid_source_valid <= soc_litedramcore_bankmachine2_pipe_valid_sink_valid;
+ soc_litedramcore_bankmachine2_pipe_valid_source_first <= soc_litedramcore_bankmachine2_pipe_valid_sink_first;
+ soc_litedramcore_bankmachine2_pipe_valid_source_last <= soc_litedramcore_bankmachine2_pipe_valid_sink_last;
+ soc_litedramcore_bankmachine2_pipe_valid_source_payload_we <= soc_litedramcore_bankmachine2_pipe_valid_sink_payload_we;
+ soc_litedramcore_bankmachine2_pipe_valid_source_payload_addr <= soc_litedramcore_bankmachine2_pipe_valid_sink_payload_addr;
+ end
+ if (soc_litedramcore_bankmachine2_twtpcon_valid) begin
+ soc_litedramcore_bankmachine2_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+ end else begin
+ soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_litedramcore_bankmachine2_twtpcon_ready)) begin
+ soc_litedramcore_bankmachine2_twtpcon_count <= (soc_litedramcore_bankmachine2_twtpcon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_litedramcore_bankmachine2_trccon_valid) begin
+ soc_litedramcore_bankmachine2_trccon_count <= 3'd5;
+ if (1'd0) begin
+ soc_litedramcore_bankmachine2_trccon_ready <= 1'd1;
+ end else begin
+ soc_litedramcore_bankmachine2_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_litedramcore_bankmachine2_trccon_ready)) begin
+ soc_litedramcore_bankmachine2_trccon_count <= (soc_litedramcore_bankmachine2_trccon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine2_trccon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine2_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_litedramcore_bankmachine2_trascon_valid) begin
+ soc_litedramcore_bankmachine2_trascon_count <= 3'd4;
+ if (1'd0) begin
+ soc_litedramcore_bankmachine2_trascon_ready <= 1'd1;
+ end else begin
+ soc_litedramcore_bankmachine2_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_litedramcore_bankmachine2_trascon_ready)) begin
+ soc_litedramcore_bankmachine2_trascon_count <= (soc_litedramcore_bankmachine2_trascon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine2_trascon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine2_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state;
+ if (soc_litedramcore_bankmachine3_row_close) begin
+ soc_litedramcore_bankmachine3_row_opened <= 1'd0;
+ end else begin
+ if (soc_litedramcore_bankmachine3_row_open) begin
+ soc_litedramcore_bankmachine3_row_opened <= 1'd1;
+ soc_litedramcore_bankmachine3_row <= soc_litedramcore_bankmachine3_source_source_payload_addr[20:7];
+ end
+ end
+ if (((soc_litedramcore_bankmachine3_syncfifo3_we & soc_litedramcore_bankmachine3_syncfifo3_writable) & (~soc_litedramcore_bankmachine3_replace))) begin
+ soc_litedramcore_bankmachine3_produce <= (soc_litedramcore_bankmachine3_produce + 1'd1);
+ end
+ if (soc_litedramcore_bankmachine3_do_read) begin
+ soc_litedramcore_bankmachine3_consume <= (soc_litedramcore_bankmachine3_consume + 1'd1);
+ end
+ if (((soc_litedramcore_bankmachine3_syncfifo3_we & soc_litedramcore_bankmachine3_syncfifo3_writable) & (~soc_litedramcore_bankmachine3_replace))) begin
+ if ((~soc_litedramcore_bankmachine3_do_read)) begin
+ soc_litedramcore_bankmachine3_level <= (soc_litedramcore_bankmachine3_level + 1'd1);
+ end
+ end else begin
+ if (soc_litedramcore_bankmachine3_do_read) begin
+ soc_litedramcore_bankmachine3_level <= (soc_litedramcore_bankmachine3_level - 1'd1);
+ end
+ end
+ if (((~soc_litedramcore_bankmachine3_pipe_valid_source_valid) | soc_litedramcore_bankmachine3_pipe_valid_source_ready)) begin
+ soc_litedramcore_bankmachine3_pipe_valid_source_valid <= soc_litedramcore_bankmachine3_pipe_valid_sink_valid;
+ soc_litedramcore_bankmachine3_pipe_valid_source_first <= soc_litedramcore_bankmachine3_pipe_valid_sink_first;
+ soc_litedramcore_bankmachine3_pipe_valid_source_last <= soc_litedramcore_bankmachine3_pipe_valid_sink_last;
+ soc_litedramcore_bankmachine3_pipe_valid_source_payload_we <= soc_litedramcore_bankmachine3_pipe_valid_sink_payload_we;
+ soc_litedramcore_bankmachine3_pipe_valid_source_payload_addr <= soc_litedramcore_bankmachine3_pipe_valid_sink_payload_addr;
+ end
+ if (soc_litedramcore_bankmachine3_twtpcon_valid) begin
+ soc_litedramcore_bankmachine3_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+ end else begin
+ soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_litedramcore_bankmachine3_twtpcon_ready)) begin
+ soc_litedramcore_bankmachine3_twtpcon_count <= (soc_litedramcore_bankmachine3_twtpcon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_litedramcore_bankmachine3_trccon_valid) begin
+ soc_litedramcore_bankmachine3_trccon_count <= 3'd5;
+ if (1'd0) begin
+ soc_litedramcore_bankmachine3_trccon_ready <= 1'd1;
+ end else begin
+ soc_litedramcore_bankmachine3_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_litedramcore_bankmachine3_trccon_ready)) begin
+ soc_litedramcore_bankmachine3_trccon_count <= (soc_litedramcore_bankmachine3_trccon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine3_trccon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine3_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_litedramcore_bankmachine3_trascon_valid) begin
+ soc_litedramcore_bankmachine3_trascon_count <= 3'd4;
+ if (1'd0) begin
+ soc_litedramcore_bankmachine3_trascon_ready <= 1'd1;
+ end else begin
+ soc_litedramcore_bankmachine3_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_litedramcore_bankmachine3_trascon_ready)) begin
+ soc_litedramcore_bankmachine3_trascon_count <= (soc_litedramcore_bankmachine3_trascon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine3_trascon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine3_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state;
+ if (soc_litedramcore_bankmachine4_row_close) begin
+ soc_litedramcore_bankmachine4_row_opened <= 1'd0;
+ end else begin
+ if (soc_litedramcore_bankmachine4_row_open) begin
+ soc_litedramcore_bankmachine4_row_opened <= 1'd1;
+ soc_litedramcore_bankmachine4_row <= soc_litedramcore_bankmachine4_source_source_payload_addr[20:7];
+ end
+ end
+ if (((soc_litedramcore_bankmachine4_syncfifo4_we & soc_litedramcore_bankmachine4_syncfifo4_writable) & (~soc_litedramcore_bankmachine4_replace))) begin
+ soc_litedramcore_bankmachine4_produce <= (soc_litedramcore_bankmachine4_produce + 1'd1);
+ end
+ if (soc_litedramcore_bankmachine4_do_read) begin
+ soc_litedramcore_bankmachine4_consume <= (soc_litedramcore_bankmachine4_consume + 1'd1);
+ end
+ if (((soc_litedramcore_bankmachine4_syncfifo4_we & soc_litedramcore_bankmachine4_syncfifo4_writable) & (~soc_litedramcore_bankmachine4_replace))) begin
+ if ((~soc_litedramcore_bankmachine4_do_read)) begin
+ soc_litedramcore_bankmachine4_level <= (soc_litedramcore_bankmachine4_level + 1'd1);
+ end
+ end else begin
+ if (soc_litedramcore_bankmachine4_do_read) begin
+ soc_litedramcore_bankmachine4_level <= (soc_litedramcore_bankmachine4_level - 1'd1);
+ end
+ end
+ if (((~soc_litedramcore_bankmachine4_pipe_valid_source_valid) | soc_litedramcore_bankmachine4_pipe_valid_source_ready)) begin
+ soc_litedramcore_bankmachine4_pipe_valid_source_valid <= soc_litedramcore_bankmachine4_pipe_valid_sink_valid;
+ soc_litedramcore_bankmachine4_pipe_valid_source_first <= soc_litedramcore_bankmachine4_pipe_valid_sink_first;
+ soc_litedramcore_bankmachine4_pipe_valid_source_last <= soc_litedramcore_bankmachine4_pipe_valid_sink_last;
+ soc_litedramcore_bankmachine4_pipe_valid_source_payload_we <= soc_litedramcore_bankmachine4_pipe_valid_sink_payload_we;
+ soc_litedramcore_bankmachine4_pipe_valid_source_payload_addr <= soc_litedramcore_bankmachine4_pipe_valid_sink_payload_addr;
+ end
+ if (soc_litedramcore_bankmachine4_twtpcon_valid) begin
+ soc_litedramcore_bankmachine4_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+ end else begin
+ soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_litedramcore_bankmachine4_twtpcon_ready)) begin
+ soc_litedramcore_bankmachine4_twtpcon_count <= (soc_litedramcore_bankmachine4_twtpcon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_litedramcore_bankmachine4_trccon_valid) begin
+ soc_litedramcore_bankmachine4_trccon_count <= 3'd5;
+ if (1'd0) begin
+ soc_litedramcore_bankmachine4_trccon_ready <= 1'd1;
+ end else begin
+ soc_litedramcore_bankmachine4_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_litedramcore_bankmachine4_trccon_ready)) begin
+ soc_litedramcore_bankmachine4_trccon_count <= (soc_litedramcore_bankmachine4_trccon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine4_trccon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine4_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_litedramcore_bankmachine4_trascon_valid) begin
+ soc_litedramcore_bankmachine4_trascon_count <= 3'd4;
+ if (1'd0) begin
+ soc_litedramcore_bankmachine4_trascon_ready <= 1'd1;
+ end else begin
+ soc_litedramcore_bankmachine4_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_litedramcore_bankmachine4_trascon_ready)) begin
+ soc_litedramcore_bankmachine4_trascon_count <= (soc_litedramcore_bankmachine4_trascon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine4_trascon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine4_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state;
+ if (soc_litedramcore_bankmachine5_row_close) begin
+ soc_litedramcore_bankmachine5_row_opened <= 1'd0;
+ end else begin
+ if (soc_litedramcore_bankmachine5_row_open) begin
+ soc_litedramcore_bankmachine5_row_opened <= 1'd1;
+ soc_litedramcore_bankmachine5_row <= soc_litedramcore_bankmachine5_source_source_payload_addr[20:7];
+ end
+ end
+ if (((soc_litedramcore_bankmachine5_syncfifo5_we & soc_litedramcore_bankmachine5_syncfifo5_writable) & (~soc_litedramcore_bankmachine5_replace))) begin
+ soc_litedramcore_bankmachine5_produce <= (soc_litedramcore_bankmachine5_produce + 1'd1);
+ end
+ if (soc_litedramcore_bankmachine5_do_read) begin
+ soc_litedramcore_bankmachine5_consume <= (soc_litedramcore_bankmachine5_consume + 1'd1);
+ end
+ if (((soc_litedramcore_bankmachine5_syncfifo5_we & soc_litedramcore_bankmachine5_syncfifo5_writable) & (~soc_litedramcore_bankmachine5_replace))) begin
+ if ((~soc_litedramcore_bankmachine5_do_read)) begin
+ soc_litedramcore_bankmachine5_level <= (soc_litedramcore_bankmachine5_level + 1'd1);
+ end
+ end else begin
+ if (soc_litedramcore_bankmachine5_do_read) begin
+ soc_litedramcore_bankmachine5_level <= (soc_litedramcore_bankmachine5_level - 1'd1);
+ end
+ end
+ if (((~soc_litedramcore_bankmachine5_pipe_valid_source_valid) | soc_litedramcore_bankmachine5_pipe_valid_source_ready)) begin
+ soc_litedramcore_bankmachine5_pipe_valid_source_valid <= soc_litedramcore_bankmachine5_pipe_valid_sink_valid;
+ soc_litedramcore_bankmachine5_pipe_valid_source_first <= soc_litedramcore_bankmachine5_pipe_valid_sink_first;
+ soc_litedramcore_bankmachine5_pipe_valid_source_last <= soc_litedramcore_bankmachine5_pipe_valid_sink_last;
+ soc_litedramcore_bankmachine5_pipe_valid_source_payload_we <= soc_litedramcore_bankmachine5_pipe_valid_sink_payload_we;
+ soc_litedramcore_bankmachine5_pipe_valid_source_payload_addr <= soc_litedramcore_bankmachine5_pipe_valid_sink_payload_addr;
+ end
+ if (soc_litedramcore_bankmachine5_twtpcon_valid) begin
+ soc_litedramcore_bankmachine5_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+ end else begin
+ soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_litedramcore_bankmachine5_twtpcon_ready)) begin
+ soc_litedramcore_bankmachine5_twtpcon_count <= (soc_litedramcore_bankmachine5_twtpcon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_litedramcore_bankmachine5_trccon_valid) begin
+ soc_litedramcore_bankmachine5_trccon_count <= 3'd5;
+ if (1'd0) begin
+ soc_litedramcore_bankmachine5_trccon_ready <= 1'd1;
+ end else begin
+ soc_litedramcore_bankmachine5_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_litedramcore_bankmachine5_trccon_ready)) begin
+ soc_litedramcore_bankmachine5_trccon_count <= (soc_litedramcore_bankmachine5_trccon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine5_trccon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine5_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_litedramcore_bankmachine5_trascon_valid) begin
+ soc_litedramcore_bankmachine5_trascon_count <= 3'd4;
+ if (1'd0) begin
+ soc_litedramcore_bankmachine5_trascon_ready <= 1'd1;
+ end else begin
+ soc_litedramcore_bankmachine5_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_litedramcore_bankmachine5_trascon_ready)) begin
+ soc_litedramcore_bankmachine5_trascon_count <= (soc_litedramcore_bankmachine5_trascon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine5_trascon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine5_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state;
+ if (soc_litedramcore_bankmachine6_row_close) begin
+ soc_litedramcore_bankmachine6_row_opened <= 1'd0;
+ end else begin
+ if (soc_litedramcore_bankmachine6_row_open) begin
+ soc_litedramcore_bankmachine6_row_opened <= 1'd1;
+ soc_litedramcore_bankmachine6_row <= soc_litedramcore_bankmachine6_source_source_payload_addr[20:7];
+ end
+ end
+ if (((soc_litedramcore_bankmachine6_syncfifo6_we & soc_litedramcore_bankmachine6_syncfifo6_writable) & (~soc_litedramcore_bankmachine6_replace))) begin
+ soc_litedramcore_bankmachine6_produce <= (soc_litedramcore_bankmachine6_produce + 1'd1);
+ end
+ if (soc_litedramcore_bankmachine6_do_read) begin
+ soc_litedramcore_bankmachine6_consume <= (soc_litedramcore_bankmachine6_consume + 1'd1);
+ end
+ if (((soc_litedramcore_bankmachine6_syncfifo6_we & soc_litedramcore_bankmachine6_syncfifo6_writable) & (~soc_litedramcore_bankmachine6_replace))) begin
+ if ((~soc_litedramcore_bankmachine6_do_read)) begin
+ soc_litedramcore_bankmachine6_level <= (soc_litedramcore_bankmachine6_level + 1'd1);
+ end
+ end else begin
+ if (soc_litedramcore_bankmachine6_do_read) begin
+ soc_litedramcore_bankmachine6_level <= (soc_litedramcore_bankmachine6_level - 1'd1);
+ end
+ end
+ if (((~soc_litedramcore_bankmachine6_pipe_valid_source_valid) | soc_litedramcore_bankmachine6_pipe_valid_source_ready)) begin
+ soc_litedramcore_bankmachine6_pipe_valid_source_valid <= soc_litedramcore_bankmachine6_pipe_valid_sink_valid;
+ soc_litedramcore_bankmachine6_pipe_valid_source_first <= soc_litedramcore_bankmachine6_pipe_valid_sink_first;
+ soc_litedramcore_bankmachine6_pipe_valid_source_last <= soc_litedramcore_bankmachine6_pipe_valid_sink_last;
+ soc_litedramcore_bankmachine6_pipe_valid_source_payload_we <= soc_litedramcore_bankmachine6_pipe_valid_sink_payload_we;
+ soc_litedramcore_bankmachine6_pipe_valid_source_payload_addr <= soc_litedramcore_bankmachine6_pipe_valid_sink_payload_addr;
+ end
+ if (soc_litedramcore_bankmachine6_twtpcon_valid) begin
+ soc_litedramcore_bankmachine6_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+ end else begin
+ soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_litedramcore_bankmachine6_twtpcon_ready)) begin
+ soc_litedramcore_bankmachine6_twtpcon_count <= (soc_litedramcore_bankmachine6_twtpcon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_litedramcore_bankmachine6_trccon_valid) begin
+ soc_litedramcore_bankmachine6_trccon_count <= 3'd5;
+ if (1'd0) begin
+ soc_litedramcore_bankmachine6_trccon_ready <= 1'd1;
+ end else begin
+ soc_litedramcore_bankmachine6_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_litedramcore_bankmachine6_trccon_ready)) begin
+ soc_litedramcore_bankmachine6_trccon_count <= (soc_litedramcore_bankmachine6_trccon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine6_trccon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine6_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_litedramcore_bankmachine6_trascon_valid) begin
+ soc_litedramcore_bankmachine6_trascon_count <= 3'd4;
+ if (1'd0) begin
+ soc_litedramcore_bankmachine6_trascon_ready <= 1'd1;
+ end else begin
+ soc_litedramcore_bankmachine6_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_litedramcore_bankmachine6_trascon_ready)) begin
+ soc_litedramcore_bankmachine6_trascon_count <= (soc_litedramcore_bankmachine6_trascon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine6_trascon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine6_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state;
+ if (soc_litedramcore_bankmachine7_row_close) begin
+ soc_litedramcore_bankmachine7_row_opened <= 1'd0;
+ end else begin
+ if (soc_litedramcore_bankmachine7_row_open) begin
+ soc_litedramcore_bankmachine7_row_opened <= 1'd1;
+ soc_litedramcore_bankmachine7_row <= soc_litedramcore_bankmachine7_source_source_payload_addr[20:7];
+ end
+ end
+ if (((soc_litedramcore_bankmachine7_syncfifo7_we & soc_litedramcore_bankmachine7_syncfifo7_writable) & (~soc_litedramcore_bankmachine7_replace))) begin
+ soc_litedramcore_bankmachine7_produce <= (soc_litedramcore_bankmachine7_produce + 1'd1);
+ end
+ if (soc_litedramcore_bankmachine7_do_read) begin
+ soc_litedramcore_bankmachine7_consume <= (soc_litedramcore_bankmachine7_consume + 1'd1);
+ end
+ if (((soc_litedramcore_bankmachine7_syncfifo7_we & soc_litedramcore_bankmachine7_syncfifo7_writable) & (~soc_litedramcore_bankmachine7_replace))) begin
+ if ((~soc_litedramcore_bankmachine7_do_read)) begin
+ soc_litedramcore_bankmachine7_level <= (soc_litedramcore_bankmachine7_level + 1'd1);
+ end
+ end else begin
+ if (soc_litedramcore_bankmachine7_do_read) begin
+ soc_litedramcore_bankmachine7_level <= (soc_litedramcore_bankmachine7_level - 1'd1);
+ end
+ end
+ if (((~soc_litedramcore_bankmachine7_pipe_valid_source_valid) | soc_litedramcore_bankmachine7_pipe_valid_source_ready)) begin
+ soc_litedramcore_bankmachine7_pipe_valid_source_valid <= soc_litedramcore_bankmachine7_pipe_valid_sink_valid;
+ soc_litedramcore_bankmachine7_pipe_valid_source_first <= soc_litedramcore_bankmachine7_pipe_valid_sink_first;
+ soc_litedramcore_bankmachine7_pipe_valid_source_last <= soc_litedramcore_bankmachine7_pipe_valid_sink_last;
+ soc_litedramcore_bankmachine7_pipe_valid_source_payload_we <= soc_litedramcore_bankmachine7_pipe_valid_sink_payload_we;
+ soc_litedramcore_bankmachine7_pipe_valid_source_payload_addr <= soc_litedramcore_bankmachine7_pipe_valid_sink_payload_addr;
+ end
+ if (soc_litedramcore_bankmachine7_twtpcon_valid) begin
+ soc_litedramcore_bankmachine7_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+ end else begin
+ soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_litedramcore_bankmachine7_twtpcon_ready)) begin
+ soc_litedramcore_bankmachine7_twtpcon_count <= (soc_litedramcore_bankmachine7_twtpcon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_litedramcore_bankmachine7_trccon_valid) begin
+ soc_litedramcore_bankmachine7_trccon_count <= 3'd5;
+ if (1'd0) begin
+ soc_litedramcore_bankmachine7_trccon_ready <= 1'd1;
+ end else begin
+ soc_litedramcore_bankmachine7_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_litedramcore_bankmachine7_trccon_ready)) begin
+ soc_litedramcore_bankmachine7_trccon_count <= (soc_litedramcore_bankmachine7_trccon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine7_trccon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine7_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_litedramcore_bankmachine7_trascon_valid) begin
+ soc_litedramcore_bankmachine7_trascon_count <= 3'd4;
+ if (1'd0) begin
+ soc_litedramcore_bankmachine7_trascon_ready <= 1'd1;
+ end else begin
+ soc_litedramcore_bankmachine7_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_litedramcore_bankmachine7_trascon_ready)) begin
+ soc_litedramcore_bankmachine7_trascon_count <= (soc_litedramcore_bankmachine7_trascon_count - 1'd1);
+ if ((soc_litedramcore_bankmachine7_trascon_count == 1'd1)) begin
+ soc_litedramcore_bankmachine7_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state;
+ if ((~soc_litedramcore_en0)) begin
+ soc_litedramcore_time0 <= 5'd31;
+ end else begin
+ if ((~soc_litedramcore_max_time0)) begin
+ soc_litedramcore_time0 <= (soc_litedramcore_time0 - 1'd1);
+ end
+ end
+ if ((~soc_litedramcore_en1)) begin
+ soc_litedramcore_time1 <= 4'd15;
+ end else begin
+ if ((~soc_litedramcore_max_time1)) begin
+ soc_litedramcore_time1 <= (soc_litedramcore_time1 - 1'd1);
+ end
+ end
+ if (soc_litedramcore_choose_cmd_ce) begin
+ case (soc_litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ if (soc_litedramcore_choose_cmd_request[1]) begin
+ soc_litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[2]) begin
+ soc_litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[3]) begin
+ soc_litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[4]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[5]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[6]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[7]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd7;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 1'd1: begin
+ if (soc_litedramcore_choose_cmd_request[2]) begin
+ soc_litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[3]) begin
+ soc_litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[4]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[5]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[6]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[7]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[0]) begin
+ soc_litedramcore_choose_cmd_grant <= 1'd0;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 2'd2: begin
+ if (soc_litedramcore_choose_cmd_request[3]) begin
+ soc_litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[4]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[5]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[6]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[7]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[0]) begin
+ soc_litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[1]) begin
+ soc_litedramcore_choose_cmd_grant <= 1'd1;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 2'd3: begin
+ if (soc_litedramcore_choose_cmd_request[4]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[5]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[6]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[7]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[0]) begin
+ soc_litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[1]) begin
+ soc_litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[2]) begin
+ soc_litedramcore_choose_cmd_grant <= 2'd2;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd4: begin
+ if (soc_litedramcore_choose_cmd_request[5]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[6]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[7]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[0]) begin
+ soc_litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[1]) begin
+ soc_litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[2]) begin
+ soc_litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[3]) begin
+ soc_litedramcore_choose_cmd_grant <= 2'd3;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd5: begin
+ if (soc_litedramcore_choose_cmd_request[6]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[7]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[0]) begin
+ soc_litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[1]) begin
+ soc_litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[2]) begin
+ soc_litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[3]) begin
+ soc_litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[4]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd4;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd6: begin
+ if (soc_litedramcore_choose_cmd_request[7]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[0]) begin
+ soc_litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[1]) begin
+ soc_litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[2]) begin
+ soc_litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[3]) begin
+ soc_litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[4]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[5]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd5;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd7: begin
+ if (soc_litedramcore_choose_cmd_request[0]) begin
+ soc_litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[1]) begin
+ soc_litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[2]) begin
+ soc_litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[3]) begin
+ soc_litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[4]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[5]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (soc_litedramcore_choose_cmd_request[6]) begin
+ soc_litedramcore_choose_cmd_grant <= 3'd6;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ endcase
+ end
+ if (soc_litedramcore_choose_req_ce) begin
+ case (soc_litedramcore_choose_req_grant)
+ 1'd0: begin
+ if (soc_litedramcore_choose_req_request[1]) begin
+ soc_litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (soc_litedramcore_choose_req_request[2]) begin
+ soc_litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (soc_litedramcore_choose_req_request[3]) begin
+ soc_litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (soc_litedramcore_choose_req_request[4]) begin
+ soc_litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (soc_litedramcore_choose_req_request[5]) begin
+ soc_litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (soc_litedramcore_choose_req_request[6]) begin
+ soc_litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (soc_litedramcore_choose_req_request[7]) begin
+ soc_litedramcore_choose_req_grant <= 3'd7;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 1'd1: begin
+ if (soc_litedramcore_choose_req_request[2]) begin
+ soc_litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (soc_litedramcore_choose_req_request[3]) begin
+ soc_litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (soc_litedramcore_choose_req_request[4]) begin
+ soc_litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (soc_litedramcore_choose_req_request[5]) begin
+ soc_litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (soc_litedramcore_choose_req_request[6]) begin
+ soc_litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (soc_litedramcore_choose_req_request[7]) begin
+ soc_litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (soc_litedramcore_choose_req_request[0]) begin
+ soc_litedramcore_choose_req_grant <= 1'd0;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 2'd2: begin
+ if (soc_litedramcore_choose_req_request[3]) begin
+ soc_litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (soc_litedramcore_choose_req_request[4]) begin
+ soc_litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (soc_litedramcore_choose_req_request[5]) begin
+ soc_litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (soc_litedramcore_choose_req_request[6]) begin
+ soc_litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (soc_litedramcore_choose_req_request[7]) begin
+ soc_litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (soc_litedramcore_choose_req_request[0]) begin
+ soc_litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (soc_litedramcore_choose_req_request[1]) begin
+ soc_litedramcore_choose_req_grant <= 1'd1;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 2'd3: begin
+ if (soc_litedramcore_choose_req_request[4]) begin
+ soc_litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (soc_litedramcore_choose_req_request[5]) begin
+ soc_litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (soc_litedramcore_choose_req_request[6]) begin
+ soc_litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (soc_litedramcore_choose_req_request[7]) begin
+ soc_litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (soc_litedramcore_choose_req_request[0]) begin
+ soc_litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (soc_litedramcore_choose_req_request[1]) begin
+ soc_litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (soc_litedramcore_choose_req_request[2]) begin
+ soc_litedramcore_choose_req_grant <= 2'd2;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd4: begin
+ if (soc_litedramcore_choose_req_request[5]) begin
+ soc_litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (soc_litedramcore_choose_req_request[6]) begin
+ soc_litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (soc_litedramcore_choose_req_request[7]) begin
+ soc_litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (soc_litedramcore_choose_req_request[0]) begin
+ soc_litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (soc_litedramcore_choose_req_request[1]) begin
+ soc_litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (soc_litedramcore_choose_req_request[2]) begin
+ soc_litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (soc_litedramcore_choose_req_request[3]) begin
+ soc_litedramcore_choose_req_grant <= 2'd3;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd5: begin
+ if (soc_litedramcore_choose_req_request[6]) begin
+ soc_litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (soc_litedramcore_choose_req_request[7]) begin
+ soc_litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (soc_litedramcore_choose_req_request[0]) begin
+ soc_litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (soc_litedramcore_choose_req_request[1]) begin
+ soc_litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (soc_litedramcore_choose_req_request[2]) begin
+ soc_litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (soc_litedramcore_choose_req_request[3]) begin
+ soc_litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (soc_litedramcore_choose_req_request[4]) begin
+ soc_litedramcore_choose_req_grant <= 3'd4;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd6: begin
+ if (soc_litedramcore_choose_req_request[7]) begin
+ soc_litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (soc_litedramcore_choose_req_request[0]) begin
+ soc_litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (soc_litedramcore_choose_req_request[1]) begin
+ soc_litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (soc_litedramcore_choose_req_request[2]) begin
+ soc_litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (soc_litedramcore_choose_req_request[3]) begin
+ soc_litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (soc_litedramcore_choose_req_request[4]) begin
+ soc_litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (soc_litedramcore_choose_req_request[5]) begin
+ soc_litedramcore_choose_req_grant <= 3'd5;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd7: begin
+ if (soc_litedramcore_choose_req_request[0]) begin
+ soc_litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (soc_litedramcore_choose_req_request[1]) begin
+ soc_litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (soc_litedramcore_choose_req_request[2]) begin
+ soc_litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (soc_litedramcore_choose_req_request[3]) begin
+ soc_litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (soc_litedramcore_choose_req_request[4]) begin
+ soc_litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (soc_litedramcore_choose_req_request[5]) begin
+ soc_litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (soc_litedramcore_choose_req_request[6]) begin
+ soc_litedramcore_choose_req_grant <= 3'd6;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ endcase
+ end
+ soc_litedramcore_dfi_p0_cs_n <= 1'd0;
+ soc_litedramcore_dfi_p0_bank <= array_muxed0;
+ soc_litedramcore_dfi_p0_address <= array_muxed1;
+ soc_litedramcore_dfi_p0_cas_n <= (~array_muxed2);
+ soc_litedramcore_dfi_p0_ras_n <= (~array_muxed3);
+ soc_litedramcore_dfi_p0_we_n <= (~array_muxed4);
+ soc_litedramcore_dfi_p0_rddata_en <= array_muxed5;
+ soc_litedramcore_dfi_p0_wrdata_en <= array_muxed6;
+ soc_litedramcore_dfi_p1_cs_n <= 1'd0;
+ soc_litedramcore_dfi_p1_bank <= array_muxed7;
+ soc_litedramcore_dfi_p1_address <= array_muxed8;
+ soc_litedramcore_dfi_p1_cas_n <= (~array_muxed9);
+ soc_litedramcore_dfi_p1_ras_n <= (~array_muxed10);
+ soc_litedramcore_dfi_p1_we_n <= (~array_muxed11);
+ soc_litedramcore_dfi_p1_rddata_en <= array_muxed12;
+ soc_litedramcore_dfi_p1_wrdata_en <= array_muxed13;
+ soc_litedramcore_dfi_p2_cs_n <= 1'd0;
+ soc_litedramcore_dfi_p2_bank <= array_muxed14;
+ soc_litedramcore_dfi_p2_address <= array_muxed15;
+ soc_litedramcore_dfi_p2_cas_n <= (~array_muxed16);
+ soc_litedramcore_dfi_p2_ras_n <= (~array_muxed17);
+ soc_litedramcore_dfi_p2_we_n <= (~array_muxed18);
+ soc_litedramcore_dfi_p2_rddata_en <= array_muxed19;
+ soc_litedramcore_dfi_p2_wrdata_en <= array_muxed20;
+ soc_litedramcore_dfi_p3_cs_n <= 1'd0;
+ soc_litedramcore_dfi_p3_bank <= array_muxed21;
+ soc_litedramcore_dfi_p3_address <= array_muxed22;
+ soc_litedramcore_dfi_p3_cas_n <= (~array_muxed23);
+ soc_litedramcore_dfi_p3_ras_n <= (~array_muxed24);
+ soc_litedramcore_dfi_p3_we_n <= (~array_muxed25);
+ soc_litedramcore_dfi_p3_rddata_en <= array_muxed26;
+ soc_litedramcore_dfi_p3_wrdata_en <= array_muxed27;
+ if (soc_litedramcore_trrdcon_valid) begin
+ soc_litedramcore_trrdcon_count <= 1'd1;
+ if (1'd0) begin
+ soc_litedramcore_trrdcon_ready <= 1'd1;
+ end else begin
+ soc_litedramcore_trrdcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_litedramcore_trrdcon_ready)) begin
+ soc_litedramcore_trrdcon_count <= (soc_litedramcore_trrdcon_count - 1'd1);
+ if ((soc_litedramcore_trrdcon_count == 1'd1)) begin
+ soc_litedramcore_trrdcon_ready <= 1'd1;
+ end
+ end
+ end
+ soc_litedramcore_tfawcon_window <= {soc_litedramcore_tfawcon_window, soc_litedramcore_tfawcon_valid};
+ if ((soc_litedramcore_tfawcon_count < 3'd4)) begin
+ if ((soc_litedramcore_tfawcon_count == 2'd3)) begin
+ soc_litedramcore_tfawcon_ready <= (~soc_litedramcore_tfawcon_valid);
+ end else begin
+ soc_litedramcore_tfawcon_ready <= 1'd1;
+ end
+ end
+ if (soc_litedramcore_tccdcon_valid) begin
+ soc_litedramcore_tccdcon_count <= 1'd0;
+ if (1'd1) begin
+ soc_litedramcore_tccdcon_ready <= 1'd1;
+ end else begin
+ soc_litedramcore_tccdcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_litedramcore_tccdcon_ready)) begin
+ soc_litedramcore_tccdcon_count <= (soc_litedramcore_tccdcon_count - 1'd1);
+ if ((soc_litedramcore_tccdcon_count == 1'd1)) begin
+ soc_litedramcore_tccdcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (soc_litedramcore_twtrcon_valid) begin
+ soc_litedramcore_twtrcon_count <= 3'd4;
+ if (1'd0) begin
+ soc_litedramcore_twtrcon_ready <= 1'd1;
+ end else begin
+ soc_litedramcore_twtrcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~soc_litedramcore_twtrcon_ready)) begin
+ soc_litedramcore_twtrcon_count <= (soc_litedramcore_twtrcon_count - 1'd1);
+ if ((soc_litedramcore_twtrcon_count == 1'd1)) begin
+ soc_litedramcore_twtrcon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state;
+ litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & soc_litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & soc_litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & soc_litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & soc_litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & soc_litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & soc_litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & soc_litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & soc_litedramcore_interface_bank7_wdata_ready));
+ litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0;
+ litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & soc_litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & soc_litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & soc_litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & soc_litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & soc_litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & soc_litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & soc_litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & soc_litedramcore_interface_bank7_rdata_valid));
+ litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0;
+ litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1;
+ litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2;
+ litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3;
+ litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4;
+ litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5;
+ litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6;
+ litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7;
+ litedramcore_state <= litedramcore_next_state;
+ if (litedramcore_dat_w_next_value_ce0) begin
+ litedramcore_dat_w <= litedramcore_dat_w_next_value0;
+ end
+ if (litedramcore_adr_next_value_ce1) begin
+ litedramcore_adr <= litedramcore_adr_next_value1;
+ end
+ if (litedramcore_we_next_value_ce2) begin
+ litedramcore_we <= litedramcore_we_next_value2;
+ end
+ interface0_bank_bus_dat_r <= 1'd0;
+ if (csrbank0_sel) begin
+ case (interface0_bank_bus_adr[8:0])
+ 1'd0: begin
+ interface0_bank_bus_dat_r <= csrbank0_init_done0_w;
+ end
+ 1'd1: begin
+ interface0_bank_bus_dat_r <= csrbank0_init_error0_w;
+ end
+ endcase
+ end
+ if (csrbank0_init_done0_re) begin
+ soc_init_done_storage <= csrbank0_init_done0_r;
+ end
+ soc_init_done_re <= csrbank0_init_done0_re;
+ if (csrbank0_init_error0_re) begin
+ soc_init_error_storage <= csrbank0_init_error0_r;
+ end
+ soc_init_error_re <= csrbank0_init_error0_re;
+ interface1_bank_bus_dat_r <= 1'd0;
+ if (csrbank1_sel) begin
+ case (interface1_bank_bus_adr[8:0])
+ 1'd0: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_control0_w;
+ end
+ 1'd1: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_command0_w;
+ end
+ 2'd2: begin
+ interface1_bank_bus_dat_r <= soc_litedramcore_phaseinjector0_command_issue_w;
+ end
+ 2'd3: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_address0_w;
+ end
+ 3'd4: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_baddress0_w;
+ end
+ 3'd5: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_wrdata0_w;
+ end
+ 3'd6: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi0_rddata_w;
+ end
+ 3'd7: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_command0_w;
+ end
+ 4'd8: begin
+ interface1_bank_bus_dat_r <= soc_litedramcore_phaseinjector1_command_issue_w;
+ end
+ 4'd9: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_address0_w;
+ end
+ 4'd10: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_baddress0_w;
+ end
+ 4'd11: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_wrdata0_w;
+ end
+ 4'd12: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi1_rddata_w;
+ end
+ 4'd13: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_command0_w;
+ end
+ 4'd14: begin
+ interface1_bank_bus_dat_r <= soc_litedramcore_phaseinjector2_command_issue_w;
+ end
+ 4'd15: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_address0_w;
+ end
+ 5'd16: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_baddress0_w;
+ end
+ 5'd17: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_wrdata0_w;
+ end
+ 5'd18: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi2_rddata_w;
+ end
+ 5'd19: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_command0_w;
+ end
+ 5'd20: begin
+ interface1_bank_bus_dat_r <= soc_litedramcore_phaseinjector3_command_issue_w;
+ end
+ 5'd21: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_address0_w;
+ end
+ 5'd22: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_baddress0_w;
+ end
+ 5'd23: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_wrdata0_w;
+ end
+ 5'd24: begin
+ interface1_bank_bus_dat_r <= csrbank1_dfii_pi3_rddata_w;
+ end
+ endcase
+ end
+ if (csrbank1_dfii_control0_re) begin
+ soc_litedramcore_storage[3:0] <= csrbank1_dfii_control0_r;
+ end
+ soc_litedramcore_re <= csrbank1_dfii_control0_re;
+ if (csrbank1_dfii_pi0_command0_re) begin
+ soc_litedramcore_phaseinjector0_command_storage[5:0] <= csrbank1_dfii_pi0_command0_r;
+ end
+ soc_litedramcore_phaseinjector0_command_re <= csrbank1_dfii_pi0_command0_re;
+ if (csrbank1_dfii_pi0_address0_re) begin
+ soc_litedramcore_phaseinjector0_address_storage[13:0] <= csrbank1_dfii_pi0_address0_r;
+ end
+ soc_litedramcore_phaseinjector0_address_re <= csrbank1_dfii_pi0_address0_re;
+ if (csrbank1_dfii_pi0_baddress0_re) begin
+ soc_litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank1_dfii_pi0_baddress0_r;
+ end
+ soc_litedramcore_phaseinjector0_baddress_re <= csrbank1_dfii_pi0_baddress0_re;
+ if (csrbank1_dfii_pi0_wrdata0_re) begin
+ soc_litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank1_dfii_pi0_wrdata0_r;
+ end
+ soc_litedramcore_phaseinjector0_wrdata_re <= csrbank1_dfii_pi0_wrdata0_re;
+ soc_litedramcore_phaseinjector0_rddata_re <= csrbank1_dfii_pi0_rddata_re;
+ if (csrbank1_dfii_pi1_command0_re) begin
+ soc_litedramcore_phaseinjector1_command_storage[5:0] <= csrbank1_dfii_pi1_command0_r;
+ end
+ soc_litedramcore_phaseinjector1_command_re <= csrbank1_dfii_pi1_command0_re;
+ if (csrbank1_dfii_pi1_address0_re) begin
+ soc_litedramcore_phaseinjector1_address_storage[13:0] <= csrbank1_dfii_pi1_address0_r;
+ end
+ soc_litedramcore_phaseinjector1_address_re <= csrbank1_dfii_pi1_address0_re;
+ if (csrbank1_dfii_pi1_baddress0_re) begin
+ soc_litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank1_dfii_pi1_baddress0_r;
+ end
+ soc_litedramcore_phaseinjector1_baddress_re <= csrbank1_dfii_pi1_baddress0_re;
+ if (csrbank1_dfii_pi1_wrdata0_re) begin
+ soc_litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank1_dfii_pi1_wrdata0_r;
+ end
+ soc_litedramcore_phaseinjector1_wrdata_re <= csrbank1_dfii_pi1_wrdata0_re;
+ soc_litedramcore_phaseinjector1_rddata_re <= csrbank1_dfii_pi1_rddata_re;
+ if (csrbank1_dfii_pi2_command0_re) begin
+ soc_litedramcore_phaseinjector2_command_storage[5:0] <= csrbank1_dfii_pi2_command0_r;
+ end
+ soc_litedramcore_phaseinjector2_command_re <= csrbank1_dfii_pi2_command0_re;
+ if (csrbank1_dfii_pi2_address0_re) begin
+ soc_litedramcore_phaseinjector2_address_storage[13:0] <= csrbank1_dfii_pi2_address0_r;
+ end
+ soc_litedramcore_phaseinjector2_address_re <= csrbank1_dfii_pi2_address0_re;
+ if (csrbank1_dfii_pi2_baddress0_re) begin
+ soc_litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank1_dfii_pi2_baddress0_r;
+ end
+ soc_litedramcore_phaseinjector2_baddress_re <= csrbank1_dfii_pi2_baddress0_re;
+ if (csrbank1_dfii_pi2_wrdata0_re) begin
+ soc_litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank1_dfii_pi2_wrdata0_r;
+ end
+ soc_litedramcore_phaseinjector2_wrdata_re <= csrbank1_dfii_pi2_wrdata0_re;
+ soc_litedramcore_phaseinjector2_rddata_re <= csrbank1_dfii_pi2_rddata_re;
+ if (csrbank1_dfii_pi3_command0_re) begin
+ soc_litedramcore_phaseinjector3_command_storage[5:0] <= csrbank1_dfii_pi3_command0_r;
+ end
+ soc_litedramcore_phaseinjector3_command_re <= csrbank1_dfii_pi3_command0_re;
+ if (csrbank1_dfii_pi3_address0_re) begin
+ soc_litedramcore_phaseinjector3_address_storage[13:0] <= csrbank1_dfii_pi3_address0_r;
+ end
+ soc_litedramcore_phaseinjector3_address_re <= csrbank1_dfii_pi3_address0_re;
+ if (csrbank1_dfii_pi3_baddress0_re) begin
+ soc_litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank1_dfii_pi3_baddress0_r;
+ end
+ soc_litedramcore_phaseinjector3_baddress_re <= csrbank1_dfii_pi3_baddress0_re;
+ if (csrbank1_dfii_pi3_wrdata0_re) begin
+ soc_litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank1_dfii_pi3_wrdata0_r;
+ end
+ soc_litedramcore_phaseinjector3_wrdata_re <= csrbank1_dfii_pi3_wrdata0_re;
+ soc_litedramcore_phaseinjector3_rddata_re <= csrbank1_dfii_pi3_rddata_re;
+ if (sys_rst) begin
+ soc_ddrphy_bankmodel0_active <= 1'd0;
+ soc_ddrphy_bankmodel0_row <= 14'd0;
+ soc_ddrphy_bankmodel1_active <= 1'd0;
+ soc_ddrphy_bankmodel1_row <= 14'd0;
+ soc_ddrphy_bankmodel2_active <= 1'd0;
+ soc_ddrphy_bankmodel2_row <= 14'd0;
+ soc_ddrphy_bankmodel3_active <= 1'd0;
+ soc_ddrphy_bankmodel3_row <= 14'd0;
+ soc_ddrphy_bankmodel4_active <= 1'd0;
+ soc_ddrphy_bankmodel4_row <= 14'd0;
+ soc_ddrphy_bankmodel5_active <= 1'd0;
+ soc_ddrphy_bankmodel5_row <= 14'd0;
+ soc_ddrphy_bankmodel6_active <= 1'd0;
+ soc_ddrphy_bankmodel6_row <= 14'd0;
+ soc_ddrphy_bankmodel7_active <= 1'd0;
+ soc_ddrphy_bankmodel7_row <= 14'd0;
+ soc_ddrphy_new_bank_write0 <= 1'd0;
+ soc_ddrphy_new_bank_write_col0 <= 10'd0;
+ soc_ddrphy_new_bank_write1 <= 1'd0;
+ soc_ddrphy_new_bank_write_col1 <= 10'd0;
+ soc_ddrphy_new_bank_write2 <= 1'd0;
+ soc_ddrphy_new_bank_write_col2 <= 10'd0;
+ soc_ddrphy_new_bank_write3 <= 1'd0;
+ soc_ddrphy_new_bank_write_col3 <= 10'd0;
+ soc_ddrphy_new_bank_write4 <= 1'd0;
+ soc_ddrphy_new_bank_write_col4 <= 10'd0;
+ soc_ddrphy_new_bank_write5 <= 1'd0;
+ soc_ddrphy_new_bank_write_col5 <= 10'd0;
+ soc_ddrphy_new_bank_write6 <= 1'd0;
+ soc_ddrphy_new_bank_write_col6 <= 10'd0;
+ soc_ddrphy_new_bank_write7 <= 1'd0;
+ soc_ddrphy_new_bank_write_col7 <= 10'd0;
+ soc_ddrphy_new_banks_read0 <= 1'd0;
+ soc_ddrphy_new_banks_read_data0 <= 128'd0;
+ soc_ddrphy_new_banks_read1 <= 1'd0;
+ soc_ddrphy_new_banks_read_data1 <= 128'd0;
+ soc_ddrphy_new_banks_read2 <= 1'd0;
+ soc_ddrphy_new_banks_read_data2 <= 128'd0;
+ soc_ddrphy_new_banks_read3 <= 1'd0;
+ soc_ddrphy_new_banks_read_data3 <= 128'd0;
+ soc_ddrphy_new_banks_read4 <= 1'd0;
+ soc_ddrphy_new_banks_read_data4 <= 128'd0;
+ soc_ddrphy_new_banks_read5 <= 1'd0;
+ soc_ddrphy_new_banks_read_data5 <= 128'd0;
+ soc_ddrphy_new_banks_read6 <= 1'd0;
+ soc_ddrphy_new_banks_read_data6 <= 128'd0;
+ soc_ddrphy_new_banks_read7 <= 1'd0;
+ soc_ddrphy_new_banks_read_data7 <= 128'd0;
+ soc_litedramcore_storage <= 4'd1;
+ soc_litedramcore_re <= 1'd0;
+ soc_litedramcore_phaseinjector0_command_storage <= 6'd0;
+ soc_litedramcore_phaseinjector0_command_re <= 1'd0;
+ soc_litedramcore_phaseinjector0_address_re <= 1'd0;
+ soc_litedramcore_phaseinjector0_baddress_re <= 1'd0;
+ soc_litedramcore_phaseinjector0_wrdata_re <= 1'd0;
+ soc_litedramcore_phaseinjector0_rddata_status <= 32'd0;
+ soc_litedramcore_phaseinjector0_rddata_re <= 1'd0;
+ soc_litedramcore_phaseinjector1_command_storage <= 6'd0;
+ soc_litedramcore_phaseinjector1_command_re <= 1'd0;
+ soc_litedramcore_phaseinjector1_address_re <= 1'd0;
+ soc_litedramcore_phaseinjector1_baddress_re <= 1'd0;
+ soc_litedramcore_phaseinjector1_wrdata_re <= 1'd0;
+ soc_litedramcore_phaseinjector1_rddata_status <= 32'd0;
+ soc_litedramcore_phaseinjector1_rddata_re <= 1'd0;
+ soc_litedramcore_phaseinjector2_command_storage <= 6'd0;
+ soc_litedramcore_phaseinjector2_command_re <= 1'd0;
+ soc_litedramcore_phaseinjector2_address_re <= 1'd0;
+ soc_litedramcore_phaseinjector2_baddress_re <= 1'd0;
+ soc_litedramcore_phaseinjector2_wrdata_re <= 1'd0;
+ soc_litedramcore_phaseinjector2_rddata_status <= 32'd0;
+ soc_litedramcore_phaseinjector2_rddata_re <= 1'd0;
+ soc_litedramcore_phaseinjector3_command_storage <= 6'd0;
+ soc_litedramcore_phaseinjector3_command_re <= 1'd0;
+ soc_litedramcore_phaseinjector3_address_re <= 1'd0;
+ soc_litedramcore_phaseinjector3_baddress_re <= 1'd0;
+ soc_litedramcore_phaseinjector3_wrdata_re <= 1'd0;
+ soc_litedramcore_phaseinjector3_rddata_status <= 32'd0;
+ soc_litedramcore_phaseinjector3_rddata_re <= 1'd0;
+ soc_litedramcore_dfi_p0_address <= 14'd0;
+ soc_litedramcore_dfi_p0_bank <= 3'd0;
+ soc_litedramcore_dfi_p0_cas_n <= 1'd1;
+ soc_litedramcore_dfi_p0_cs_n <= 1'd1;
+ soc_litedramcore_dfi_p0_ras_n <= 1'd1;
+ soc_litedramcore_dfi_p0_we_n <= 1'd1;
+ soc_litedramcore_dfi_p0_wrdata_en <= 1'd0;
+ soc_litedramcore_dfi_p0_rddata_en <= 1'd0;
+ soc_litedramcore_dfi_p1_address <= 14'd0;
+ soc_litedramcore_dfi_p1_bank <= 3'd0;
+ soc_litedramcore_dfi_p1_cas_n <= 1'd1;
+ soc_litedramcore_dfi_p1_cs_n <= 1'd1;
+ soc_litedramcore_dfi_p1_ras_n <= 1'd1;
+ soc_litedramcore_dfi_p1_we_n <= 1'd1;
+ soc_litedramcore_dfi_p1_wrdata_en <= 1'd0;
+ soc_litedramcore_dfi_p1_rddata_en <= 1'd0;
+ soc_litedramcore_dfi_p2_address <= 14'd0;
+ soc_litedramcore_dfi_p2_bank <= 3'd0;
+ soc_litedramcore_dfi_p2_cas_n <= 1'd1;
+ soc_litedramcore_dfi_p2_cs_n <= 1'd1;
+ soc_litedramcore_dfi_p2_ras_n <= 1'd1;
+ soc_litedramcore_dfi_p2_we_n <= 1'd1;
+ soc_litedramcore_dfi_p2_wrdata_en <= 1'd0;
+ soc_litedramcore_dfi_p2_rddata_en <= 1'd0;
+ soc_litedramcore_dfi_p3_address <= 14'd0;
+ soc_litedramcore_dfi_p3_bank <= 3'd0;
+ soc_litedramcore_dfi_p3_cas_n <= 1'd1;
+ soc_litedramcore_dfi_p3_cs_n <= 1'd1;
+ soc_litedramcore_dfi_p3_ras_n <= 1'd1;
+ soc_litedramcore_dfi_p3_we_n <= 1'd1;
+ soc_litedramcore_dfi_p3_wrdata_en <= 1'd0;
+ soc_litedramcore_dfi_p3_rddata_en <= 1'd0;
+ soc_litedramcore_cmd_payload_a <= 14'd0;
+ soc_litedramcore_cmd_payload_ba <= 3'd0;
+ soc_litedramcore_cmd_payload_cas <= 1'd0;
+ soc_litedramcore_cmd_payload_ras <= 1'd0;
+ soc_litedramcore_cmd_payload_we <= 1'd0;
+ soc_litedramcore_timer_count1 <= 10'd781;
+ soc_litedramcore_postponer_req_o <= 1'd0;
+ soc_litedramcore_postponer_count <= 1'd0;
+ soc_litedramcore_sequencer_done1 <= 1'd0;
+ soc_litedramcore_sequencer_counter <= 6'd0;
+ soc_litedramcore_sequencer_count <= 1'd0;
+ soc_litedramcore_zqcs_timer_count1 <= 27'd99999999;
+ soc_litedramcore_zqcs_executer_done <= 1'd0;
+ soc_litedramcore_zqcs_executer_counter <= 5'd0;
+ soc_litedramcore_bankmachine0_level <= 5'd0;
+ soc_litedramcore_bankmachine0_produce <= 4'd0;
+ soc_litedramcore_bankmachine0_consume <= 4'd0;
+ soc_litedramcore_bankmachine0_pipe_valid_source_valid <= 1'd0;
+ soc_litedramcore_bankmachine0_pipe_valid_source_payload_we <= 1'd0;
+ soc_litedramcore_bankmachine0_pipe_valid_source_payload_addr <= 21'd0;
+ soc_litedramcore_bankmachine0_row <= 14'd0;
+ soc_litedramcore_bankmachine0_row_opened <= 1'd0;
+ soc_litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
+ soc_litedramcore_bankmachine0_twtpcon_count <= 3'd0;
+ soc_litedramcore_bankmachine0_trccon_ready <= 1'd0;
+ soc_litedramcore_bankmachine0_trccon_count <= 3'd0;
+ soc_litedramcore_bankmachine0_trascon_ready <= 1'd0;
+ soc_litedramcore_bankmachine0_trascon_count <= 3'd0;
+ soc_litedramcore_bankmachine1_level <= 5'd0;
+ soc_litedramcore_bankmachine1_produce <= 4'd0;
+ soc_litedramcore_bankmachine1_consume <= 4'd0;
+ soc_litedramcore_bankmachine1_pipe_valid_source_valid <= 1'd0;
+ soc_litedramcore_bankmachine1_pipe_valid_source_payload_we <= 1'd0;
+ soc_litedramcore_bankmachine1_pipe_valid_source_payload_addr <= 21'd0;
+ soc_litedramcore_bankmachine1_row <= 14'd0;
+ soc_litedramcore_bankmachine1_row_opened <= 1'd0;
+ soc_litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
+ soc_litedramcore_bankmachine1_twtpcon_count <= 3'd0;
+ soc_litedramcore_bankmachine1_trccon_ready <= 1'd0;
+ soc_litedramcore_bankmachine1_trccon_count <= 3'd0;
+ soc_litedramcore_bankmachine1_trascon_ready <= 1'd0;
+ soc_litedramcore_bankmachine1_trascon_count <= 3'd0;
+ soc_litedramcore_bankmachine2_level <= 5'd0;
+ soc_litedramcore_bankmachine2_produce <= 4'd0;
+ soc_litedramcore_bankmachine2_consume <= 4'd0;
+ soc_litedramcore_bankmachine2_pipe_valid_source_valid <= 1'd0;
+ soc_litedramcore_bankmachine2_pipe_valid_source_payload_we <= 1'd0;
+ soc_litedramcore_bankmachine2_pipe_valid_source_payload_addr <= 21'd0;
+ soc_litedramcore_bankmachine2_row <= 14'd0;
+ soc_litedramcore_bankmachine2_row_opened <= 1'd0;
+ soc_litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
+ soc_litedramcore_bankmachine2_twtpcon_count <= 3'd0;
+ soc_litedramcore_bankmachine2_trccon_ready <= 1'd0;
+ soc_litedramcore_bankmachine2_trccon_count <= 3'd0;
+ soc_litedramcore_bankmachine2_trascon_ready <= 1'd0;
+ soc_litedramcore_bankmachine2_trascon_count <= 3'd0;
+ soc_litedramcore_bankmachine3_level <= 5'd0;
+ soc_litedramcore_bankmachine3_produce <= 4'd0;
+ soc_litedramcore_bankmachine3_consume <= 4'd0;
+ soc_litedramcore_bankmachine3_pipe_valid_source_valid <= 1'd0;
+ soc_litedramcore_bankmachine3_pipe_valid_source_payload_we <= 1'd0;
+ soc_litedramcore_bankmachine3_pipe_valid_source_payload_addr <= 21'd0;
+ soc_litedramcore_bankmachine3_row <= 14'd0;
+ soc_litedramcore_bankmachine3_row_opened <= 1'd0;
+ soc_litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
+ soc_litedramcore_bankmachine3_twtpcon_count <= 3'd0;
+ soc_litedramcore_bankmachine3_trccon_ready <= 1'd0;
+ soc_litedramcore_bankmachine3_trccon_count <= 3'd0;
+ soc_litedramcore_bankmachine3_trascon_ready <= 1'd0;
+ soc_litedramcore_bankmachine3_trascon_count <= 3'd0;
+ soc_litedramcore_bankmachine4_level <= 5'd0;
+ soc_litedramcore_bankmachine4_produce <= 4'd0;
+ soc_litedramcore_bankmachine4_consume <= 4'd0;
+ soc_litedramcore_bankmachine4_pipe_valid_source_valid <= 1'd0;
+ soc_litedramcore_bankmachine4_pipe_valid_source_payload_we <= 1'd0;
+ soc_litedramcore_bankmachine4_pipe_valid_source_payload_addr <= 21'd0;
+ soc_litedramcore_bankmachine4_row <= 14'd0;
+ soc_litedramcore_bankmachine4_row_opened <= 1'd0;
+ soc_litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
+ soc_litedramcore_bankmachine4_twtpcon_count <= 3'd0;
+ soc_litedramcore_bankmachine4_trccon_ready <= 1'd0;
+ soc_litedramcore_bankmachine4_trccon_count <= 3'd0;
+ soc_litedramcore_bankmachine4_trascon_ready <= 1'd0;
+ soc_litedramcore_bankmachine4_trascon_count <= 3'd0;
+ soc_litedramcore_bankmachine5_level <= 5'd0;
+ soc_litedramcore_bankmachine5_produce <= 4'd0;
+ soc_litedramcore_bankmachine5_consume <= 4'd0;
+ soc_litedramcore_bankmachine5_pipe_valid_source_valid <= 1'd0;
+ soc_litedramcore_bankmachine5_pipe_valid_source_payload_we <= 1'd0;
+ soc_litedramcore_bankmachine5_pipe_valid_source_payload_addr <= 21'd0;
+ soc_litedramcore_bankmachine5_row <= 14'd0;
+ soc_litedramcore_bankmachine5_row_opened <= 1'd0;
+ soc_litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
+ soc_litedramcore_bankmachine5_twtpcon_count <= 3'd0;
+ soc_litedramcore_bankmachine5_trccon_ready <= 1'd0;
+ soc_litedramcore_bankmachine5_trccon_count <= 3'd0;
+ soc_litedramcore_bankmachine5_trascon_ready <= 1'd0;
+ soc_litedramcore_bankmachine5_trascon_count <= 3'd0;
+ soc_litedramcore_bankmachine6_level <= 5'd0;
+ soc_litedramcore_bankmachine6_produce <= 4'd0;
+ soc_litedramcore_bankmachine6_consume <= 4'd0;
+ soc_litedramcore_bankmachine6_pipe_valid_source_valid <= 1'd0;
+ soc_litedramcore_bankmachine6_pipe_valid_source_payload_we <= 1'd0;
+ soc_litedramcore_bankmachine6_pipe_valid_source_payload_addr <= 21'd0;
+ soc_litedramcore_bankmachine6_row <= 14'd0;
+ soc_litedramcore_bankmachine6_row_opened <= 1'd0;
+ soc_litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
+ soc_litedramcore_bankmachine6_twtpcon_count <= 3'd0;
+ soc_litedramcore_bankmachine6_trccon_ready <= 1'd0;
+ soc_litedramcore_bankmachine6_trccon_count <= 3'd0;
+ soc_litedramcore_bankmachine6_trascon_ready <= 1'd0;
+ soc_litedramcore_bankmachine6_trascon_count <= 3'd0;
+ soc_litedramcore_bankmachine7_level <= 5'd0;
+ soc_litedramcore_bankmachine7_produce <= 4'd0;
+ soc_litedramcore_bankmachine7_consume <= 4'd0;
+ soc_litedramcore_bankmachine7_pipe_valid_source_valid <= 1'd0;
+ soc_litedramcore_bankmachine7_pipe_valid_source_payload_we <= 1'd0;
+ soc_litedramcore_bankmachine7_pipe_valid_source_payload_addr <= 21'd0;
+ soc_litedramcore_bankmachine7_row <= 14'd0;
+ soc_litedramcore_bankmachine7_row_opened <= 1'd0;
+ soc_litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
+ soc_litedramcore_bankmachine7_twtpcon_count <= 3'd0;
+ soc_litedramcore_bankmachine7_trccon_ready <= 1'd0;
+ soc_litedramcore_bankmachine7_trccon_count <= 3'd0;
+ soc_litedramcore_bankmachine7_trascon_ready <= 1'd0;
+ soc_litedramcore_bankmachine7_trascon_count <= 3'd0;
+ soc_litedramcore_choose_cmd_grant <= 3'd0;
+ soc_litedramcore_choose_req_grant <= 3'd0;
+ soc_litedramcore_trrdcon_ready <= 1'd0;
+ soc_litedramcore_trrdcon_count <= 1'd0;
+ soc_litedramcore_tfawcon_ready <= 1'd1;
+ soc_litedramcore_tfawcon_window <= 5'd0;
+ soc_litedramcore_tccdcon_ready <= 1'd0;
+ soc_litedramcore_tccdcon_count <= 1'd0;
+ soc_litedramcore_twtrcon_ready <= 1'd0;
+ soc_litedramcore_twtrcon_count <= 3'd0;
+ soc_litedramcore_time0 <= 5'd0;
+ soc_litedramcore_time1 <= 4'd0;
+ soc_init_done_storage <= 1'd0;
+ soc_init_done_re <= 1'd0;
+ soc_init_error_storage <= 1'd0;
+ soc_init_error_re <= 1'd0;
+ litedramcore_we <= 1'd0;
+ litedramcore_refresher_state <= 2'd0;
+ litedramcore_bankmachine0_state <= 4'd0;
+ litedramcore_bankmachine1_state <= 4'd0;
+ litedramcore_bankmachine2_state <= 4'd0;
+ litedramcore_bankmachine3_state <= 4'd0;
+ litedramcore_bankmachine4_state <= 4'd0;
+ litedramcore_bankmachine5_state <= 4'd0;
+ litedramcore_bankmachine6_state <= 4'd0;
+ litedramcore_bankmachine7_state <= 4'd0;
+ litedramcore_multiplexer_state <= 4'd0;
+ litedramcore_new_master_wdata_ready0 <= 1'd0;
+ litedramcore_new_master_wdata_ready1 <= 1'd0;
+ litedramcore_new_master_rdata_valid0 <= 1'd0;
+ litedramcore_new_master_rdata_valid1 <= 1'd0;
+ litedramcore_new_master_rdata_valid2 <= 1'd0;
+ litedramcore_new_master_rdata_valid3 <= 1'd0;
+ litedramcore_new_master_rdata_valid4 <= 1'd0;
+ litedramcore_new_master_rdata_valid5 <= 1'd0;
+ litedramcore_new_master_rdata_valid6 <= 1'd0;
+ litedramcore_new_master_rdata_valid7 <= 1'd0;
+ litedramcore_new_master_rdata_valid8 <= 1'd0;
+ litedramcore_state <= 2'd0;
+ end
end
reg [23:0] storage[0:15];
reg [23:0] storage_dat0;
always @(posedge sys_clk) begin
- if (soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we)
- storage[soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
- storage_dat0 <= storage[soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr];
+ if (soc_litedramcore_bankmachine0_wrport_we)
+ storage[soc_litedramcore_bankmachine0_wrport_adr] <= soc_litedramcore_bankmachine0_wrport_dat_w;
+ storage_dat0 <= storage[soc_litedramcore_bankmachine0_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = storage_dat0;
-assign soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[soc_litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr];
+assign soc_litedramcore_bankmachine0_wrport_dat_r = storage_dat0;
+assign soc_litedramcore_bankmachine0_rdport_dat_r = storage[soc_litedramcore_bankmachine0_rdport_adr];
//------------------------------------------------------------------------------
reg [23:0] storage_1[0:15];
reg [23:0] storage_1_dat0;
always @(posedge sys_clk) begin
- if (soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we)
- storage_1[soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
- storage_1_dat0 <= storage_1[soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr];
+ if (soc_litedramcore_bankmachine1_wrport_we)
+ storage_1[soc_litedramcore_bankmachine1_wrport_adr] <= soc_litedramcore_bankmachine1_wrport_dat_w;
+ storage_1_dat0 <= storage_1[soc_litedramcore_bankmachine1_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = storage_1_dat0;
-assign soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[soc_litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr];
+assign soc_litedramcore_bankmachine1_wrport_dat_r = storage_1_dat0;
+assign soc_litedramcore_bankmachine1_rdport_dat_r = storage_1[soc_litedramcore_bankmachine1_rdport_adr];
//------------------------------------------------------------------------------
reg [23:0] storage_2[0:15];
reg [23:0] storage_2_dat0;
always @(posedge sys_clk) begin
- if (soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we)
- storage_2[soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
- storage_2_dat0 <= storage_2[soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr];
+ if (soc_litedramcore_bankmachine2_wrport_we)
+ storage_2[soc_litedramcore_bankmachine2_wrport_adr] <= soc_litedramcore_bankmachine2_wrport_dat_w;
+ storage_2_dat0 <= storage_2[soc_litedramcore_bankmachine2_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = storage_2_dat0;
-assign soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[soc_litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr];
+assign soc_litedramcore_bankmachine2_wrport_dat_r = storage_2_dat0;
+assign soc_litedramcore_bankmachine2_rdport_dat_r = storage_2[soc_litedramcore_bankmachine2_rdport_adr];
//------------------------------------------------------------------------------
reg [23:0] storage_3[0:15];
reg [23:0] storage_3_dat0;
always @(posedge sys_clk) begin
- if (soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we)
- storage_3[soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
- storage_3_dat0 <= storage_3[soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr];
+ if (soc_litedramcore_bankmachine3_wrport_we)
+ storage_3[soc_litedramcore_bankmachine3_wrport_adr] <= soc_litedramcore_bankmachine3_wrport_dat_w;
+ storage_3_dat0 <= storage_3[soc_litedramcore_bankmachine3_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = storage_3_dat0;
-assign soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[soc_litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr];
+assign soc_litedramcore_bankmachine3_wrport_dat_r = storage_3_dat0;
+assign soc_litedramcore_bankmachine3_rdport_dat_r = storage_3[soc_litedramcore_bankmachine3_rdport_adr];
//------------------------------------------------------------------------------
reg [23:0] storage_4[0:15];
reg [23:0] storage_4_dat0;
always @(posedge sys_clk) begin
- if (soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we)
- storage_4[soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
- storage_4_dat0 <= storage_4[soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr];
+ if (soc_litedramcore_bankmachine4_wrport_we)
+ storage_4[soc_litedramcore_bankmachine4_wrport_adr] <= soc_litedramcore_bankmachine4_wrport_dat_w;
+ storage_4_dat0 <= storage_4[soc_litedramcore_bankmachine4_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = storage_4_dat0;
-assign soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[soc_litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr];
+assign soc_litedramcore_bankmachine4_wrport_dat_r = storage_4_dat0;
+assign soc_litedramcore_bankmachine4_rdport_dat_r = storage_4[soc_litedramcore_bankmachine4_rdport_adr];
//------------------------------------------------------------------------------
reg [23:0] storage_5[0:15];
reg [23:0] storage_5_dat0;
always @(posedge sys_clk) begin
- if (soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we)
- storage_5[soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
- storage_5_dat0 <= storage_5[soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr];
+ if (soc_litedramcore_bankmachine5_wrport_we)
+ storage_5[soc_litedramcore_bankmachine5_wrport_adr] <= soc_litedramcore_bankmachine5_wrport_dat_w;
+ storage_5_dat0 <= storage_5[soc_litedramcore_bankmachine5_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = storage_5_dat0;
-assign soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[soc_litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr];
+assign soc_litedramcore_bankmachine5_wrport_dat_r = storage_5_dat0;
+assign soc_litedramcore_bankmachine5_rdport_dat_r = storage_5[soc_litedramcore_bankmachine5_rdport_adr];
//------------------------------------------------------------------------------
reg [23:0] storage_6[0:15];
reg [23:0] storage_6_dat0;
always @(posedge sys_clk) begin
- if (soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we)
- storage_6[soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
- storage_6_dat0 <= storage_6[soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr];
+ if (soc_litedramcore_bankmachine6_wrport_we)
+ storage_6[soc_litedramcore_bankmachine6_wrport_adr] <= soc_litedramcore_bankmachine6_wrport_dat_w;
+ storage_6_dat0 <= storage_6[soc_litedramcore_bankmachine6_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = storage_6_dat0;
-assign soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[soc_litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr];
+assign soc_litedramcore_bankmachine6_wrport_dat_r = storage_6_dat0;
+assign soc_litedramcore_bankmachine6_rdport_dat_r = storage_6[soc_litedramcore_bankmachine6_rdport_adr];
//------------------------------------------------------------------------------
reg [23:0] storage_7[0:15];
reg [23:0] storage_7_dat0;
always @(posedge sys_clk) begin
- if (soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we)
- storage_7[soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
- storage_7_dat0 <= storage_7[soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr];
+ if (soc_litedramcore_bankmachine7_wrport_we)
+ storage_7[soc_litedramcore_bankmachine7_wrport_adr] <= soc_litedramcore_bankmachine7_wrport_dat_w;
+ storage_7_dat0 <= storage_7[soc_litedramcore_bankmachine7_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = storage_7_dat0;
-assign soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[soc_litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr];
+assign soc_litedramcore_bankmachine7_wrport_dat_r = storage_7_dat0;
+assign soc_litedramcore_bankmachine7_rdport_dat_r = storage_7[soc_litedramcore_bankmachine7_rdport_adr];
endmodule
// -----------------------------------------------------------------------------
-// Auto-Generated by LiteX on 2022-08-04 21:07:04.
+// Auto-Generated by LiteX on 2022-10-28 19:01:27.
//------------------------------------------------------------------------------
6421ff00782107c6
3d80000060215f00
798c07c6618c0000
-618c10d8658cff00
+618c10e0658cff00
4e8004217d8903a6
4e8004207c6903a6
0000000000000000
0000000000000000
3c4c000100000000
7c0802a63842adc4
-f8010010fbe1fff8
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//
// Filename : litedram_core.v
// Device :
-// LiteX sha1 : 6932fc51
-// Date : 2022-08-04 21:07:01
+// LiteX sha1 : --------
+// Date : 2022-10-28 19:01:24
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
module litedram_core (
- input wire clk,
- input wire rst,
- output wire pll_locked,
- output wire [13:0] ddram_a,
- output wire [2:0] ddram_ba,
- output wire ddram_ras_n,
- output wire ddram_cas_n,
- output wire ddram_we_n,
- output wire ddram_cs_n,
- output wire [1:0] ddram_dm,
- inout wire [15:0] ddram_dq,
- inout wire [1:0] ddram_dqs_p,
- inout wire [1:0] ddram_dqs_n,
- output wire ddram_clk_p,
- output wire ddram_clk_n,
- output wire ddram_cke,
- output wire ddram_odt,
- output wire ddram_reset_n,
- output wire init_done,
- output wire init_error,
- input wire [29:0] wb_ctrl_adr,
- input wire [31:0] wb_ctrl_dat_w,
- output wire [31:0] wb_ctrl_dat_r,
- input wire [3:0] wb_ctrl_sel,
- input wire wb_ctrl_cyc,
- input wire wb_ctrl_stb,
- output wire wb_ctrl_ack,
- input wire wb_ctrl_we,
- input wire [2:0] wb_ctrl_cti,
- input wire [1:0] wb_ctrl_bte,
- output wire wb_ctrl_err,
- output wire user_clk,
- output wire user_rst,
- input wire user_port_native_0_cmd_valid,
- output wire user_port_native_0_cmd_ready,
- input wire user_port_native_0_cmd_we,
- input wire [23:0] user_port_native_0_cmd_addr,
- input wire user_port_native_0_wdata_valid,
- output wire user_port_native_0_wdata_ready,
- input wire [15:0] user_port_native_0_wdata_we,
- input wire [127:0] user_port_native_0_wdata_data,
- output wire user_port_native_0_rdata_valid,
- input wire user_port_native_0_rdata_ready,
- output wire [127:0] user_port_native_0_rdata_data
+ input wire clk,
+ input wire rst,
+ output wire pll_locked,
+ output wire [13:0] ddram_a,
+ output wire [2:0] ddram_ba,
+ output wire ddram_ras_n,
+ output wire ddram_cas_n,
+ output wire ddram_we_n,
+ output wire ddram_cs_n,
+ output wire [1:0] ddram_dm,
+ inout wire [15:0] ddram_dq,
+ inout wire [1:0] ddram_dqs_p,
+ inout wire [1:0] ddram_dqs_n,
+ output wire ddram_clk_p,
+ output wire ddram_clk_n,
+ output wire ddram_cke,
+ output wire ddram_odt,
+ output wire ddram_reset_n,
+ output wire init_done,
+ output wire init_error,
+ input wire [29:0] wb_ctrl_adr,
+ input wire [31:0] wb_ctrl_dat_w,
+ output wire [31:0] wb_ctrl_dat_r,
+ input wire [3:0] wb_ctrl_sel,
+ input wire wb_ctrl_cyc,
+ input wire wb_ctrl_stb,
+ output wire wb_ctrl_ack,
+ input wire wb_ctrl_we,
+ input wire [2:0] wb_ctrl_cti,
+ input wire [1:0] wb_ctrl_bte,
+ output wire wb_ctrl_err,
+ output wire user_clk,
+ output wire user_rst,
+ input wire user_port_native_0_cmd_valid,
+ output wire user_port_native_0_cmd_ready,
+ input wire user_port_native_0_cmd_we,
+ input wire [23:0] user_port_native_0_cmd_addr,
+ input wire user_port_native_0_wdata_valid,
+ output wire user_port_native_0_wdata_ready,
+ input wire [15:0] user_port_native_0_wdata_we,
+ input wire [127:0] user_port_native_0_wdata_data,
+ output wire user_port_native_0_rdata_valid,
+ input wire user_port_native_0_rdata_ready,
+ output wire [127:0] user_port_native_0_rdata_data
);
// Signals
//------------------------------------------------------------------------------
-reg rst_1 = 1'd0;
-wire sys_clk;
-wire sys_rst;
-wire sys4x_clk;
-wire sys4x_dqs_clk;
-wire iodelay_clk;
-wire iodelay_rst;
-wire reset;
-reg power_down = 1'd0;
-wire locked;
-wire clkin;
-wire clkout0;
-wire clkout_buf0;
-wire clkout1;
-wire clkout_buf1;
-wire clkout2;
-wire clkout_buf2;
-wire clkout3;
-wire clkout_buf3;
-reg [3:0] reset_counter = 4'd15;
-reg ic_reset = 1'd1;
-reg a7ddrphy_rst_storage = 1'd0;
-reg a7ddrphy_rst_re = 1'd0;
-reg [1:0] a7ddrphy_dly_sel_storage = 2'd0;
-reg a7ddrphy_dly_sel_re = 1'd0;
-reg [4:0] a7ddrphy_half_sys8x_taps_storage = 5'd8;
-reg a7ddrphy_half_sys8x_taps_re = 1'd0;
-reg a7ddrphy_wlevel_en_storage = 1'd0;
-reg a7ddrphy_wlevel_en_re = 1'd0;
-reg a7ddrphy_wlevel_strobe_re = 1'd0;
-wire a7ddrphy_wlevel_strobe_r;
-reg a7ddrphy_wlevel_strobe_we = 1'd0;
-reg a7ddrphy_wlevel_strobe_w = 1'd0;
-reg a7ddrphy_rdly_dq_rst_re = 1'd0;
-wire a7ddrphy_rdly_dq_rst_r;
-reg a7ddrphy_rdly_dq_rst_we = 1'd0;
-reg a7ddrphy_rdly_dq_rst_w = 1'd0;
-reg a7ddrphy_rdly_dq_inc_re = 1'd0;
-wire a7ddrphy_rdly_dq_inc_r;
-reg a7ddrphy_rdly_dq_inc_we = 1'd0;
-reg a7ddrphy_rdly_dq_inc_w = 1'd0;
-reg a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
-wire a7ddrphy_rdly_dq_bitslip_rst_r;
-reg a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
-reg a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
-reg a7ddrphy_rdly_dq_bitslip_re = 1'd0;
-wire a7ddrphy_rdly_dq_bitslip_r;
-reg a7ddrphy_rdly_dq_bitslip_we = 1'd0;
-reg a7ddrphy_rdly_dq_bitslip_w = 1'd0;
-reg a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0;
-wire a7ddrphy_wdly_dq_bitslip_rst_r;
-reg a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0;
-reg a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0;
-reg a7ddrphy_wdly_dq_bitslip_re = 1'd0;
-wire a7ddrphy_wdly_dq_bitslip_r;
-reg a7ddrphy_wdly_dq_bitslip_we = 1'd0;
-reg a7ddrphy_wdly_dq_bitslip_w = 1'd0;
-reg [1:0] a7ddrphy_rdphase_storage = 2'd2;
-reg a7ddrphy_rdphase_re = 1'd0;
-reg [1:0] a7ddrphy_wrphase_storage = 2'd3;
-reg a7ddrphy_wrphase_re = 1'd0;
-wire [13:0] a7ddrphy_dfi_p0_address;
-wire [2:0] a7ddrphy_dfi_p0_bank;
-wire a7ddrphy_dfi_p0_cas_n;
-wire a7ddrphy_dfi_p0_cs_n;
-wire a7ddrphy_dfi_p0_ras_n;
-wire a7ddrphy_dfi_p0_we_n;
-wire a7ddrphy_dfi_p0_cke;
-wire a7ddrphy_dfi_p0_odt;
-wire a7ddrphy_dfi_p0_reset_n;
-wire a7ddrphy_dfi_p0_act_n;
-wire [31:0] a7ddrphy_dfi_p0_wrdata;
-wire a7ddrphy_dfi_p0_wrdata_en;
-wire [3:0] a7ddrphy_dfi_p0_wrdata_mask;
-wire a7ddrphy_dfi_p0_rddata_en;
-reg [31:0] a7ddrphy_dfi_p0_rddata = 32'd0;
-wire a7ddrphy_dfi_p0_rddata_valid;
-wire [13:0] a7ddrphy_dfi_p1_address;
-wire [2:0] a7ddrphy_dfi_p1_bank;
-wire a7ddrphy_dfi_p1_cas_n;
-wire a7ddrphy_dfi_p1_cs_n;
-wire a7ddrphy_dfi_p1_ras_n;
-wire a7ddrphy_dfi_p1_we_n;
-wire a7ddrphy_dfi_p1_cke;
-wire a7ddrphy_dfi_p1_odt;
-wire a7ddrphy_dfi_p1_reset_n;
-wire a7ddrphy_dfi_p1_act_n;
-wire [31:0] a7ddrphy_dfi_p1_wrdata;
-wire a7ddrphy_dfi_p1_wrdata_en;
-wire [3:0] a7ddrphy_dfi_p1_wrdata_mask;
-wire a7ddrphy_dfi_p1_rddata_en;
-reg [31:0] a7ddrphy_dfi_p1_rddata = 32'd0;
-wire a7ddrphy_dfi_p1_rddata_valid;
-wire [13:0] a7ddrphy_dfi_p2_address;
-wire [2:0] a7ddrphy_dfi_p2_bank;
-wire a7ddrphy_dfi_p2_cas_n;
-wire a7ddrphy_dfi_p2_cs_n;
-wire a7ddrphy_dfi_p2_ras_n;
-wire a7ddrphy_dfi_p2_we_n;
-wire a7ddrphy_dfi_p2_cke;
-wire a7ddrphy_dfi_p2_odt;
-wire a7ddrphy_dfi_p2_reset_n;
-wire a7ddrphy_dfi_p2_act_n;
-wire [31:0] a7ddrphy_dfi_p2_wrdata;
-wire a7ddrphy_dfi_p2_wrdata_en;
-wire [3:0] a7ddrphy_dfi_p2_wrdata_mask;
-wire a7ddrphy_dfi_p2_rddata_en;
-reg [31:0] a7ddrphy_dfi_p2_rddata = 32'd0;
-wire a7ddrphy_dfi_p2_rddata_valid;
-wire [13:0] a7ddrphy_dfi_p3_address;
-wire [2:0] a7ddrphy_dfi_p3_bank;
-wire a7ddrphy_dfi_p3_cas_n;
-wire a7ddrphy_dfi_p3_cs_n;
-wire a7ddrphy_dfi_p3_ras_n;
-wire a7ddrphy_dfi_p3_we_n;
-wire a7ddrphy_dfi_p3_cke;
-wire a7ddrphy_dfi_p3_odt;
-wire a7ddrphy_dfi_p3_reset_n;
-wire a7ddrphy_dfi_p3_act_n;
-wire [31:0] a7ddrphy_dfi_p3_wrdata;
-wire a7ddrphy_dfi_p3_wrdata_en;
-wire [3:0] a7ddrphy_dfi_p3_wrdata_mask;
-wire a7ddrphy_dfi_p3_rddata_en;
-reg [31:0] a7ddrphy_dfi_p3_rddata = 32'd0;
-wire a7ddrphy_dfi_p3_rddata_valid;
-wire a7ddrphy_sd_clk_se_nodelay;
-wire [2:0] a7ddrphy_pads_ba;
-reg a7ddrphy_dqs_oe = 1'd0;
-wire a7ddrphy_dqs_preamble;
-wire a7ddrphy_dqs_postamble;
-wire a7ddrphy_dqs_oe_delay_tappeddelayline;
-reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
-reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
-reg a7ddrphy_dqspattern0 = 1'd0;
-reg a7ddrphy_dqspattern1 = 1'd0;
-reg [7:0] a7ddrphy_dqspattern_o0 = 8'd0;
-reg [7:0] a7ddrphy_dqspattern_o1 = 8'd0;
-wire a7ddrphy_dqs_o_no_delay0;
-wire a7ddrphy_dqs_t0;
-reg [7:0] a7ddrphy_bitslip00 = 8'd0;
-reg [2:0] a7ddrphy_bitslip0_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip0_r0 = 16'd0;
-wire a7ddrphy0;
-wire a7ddrphy_dqs_o_no_delay1;
-wire a7ddrphy_dqs_t1;
-reg [7:0] a7ddrphy_bitslip10 = 8'd0;
-reg [2:0] a7ddrphy_bitslip1_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip1_r0 = 16'd0;
-wire a7ddrphy1;
-reg [7:0] a7ddrphy_bitslip01 = 8'd0;
-reg [2:0] a7ddrphy_bitslip0_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip0_r1 = 16'd0;
-reg [7:0] a7ddrphy_bitslip11 = 8'd0;
-reg [2:0] a7ddrphy_bitslip1_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip1_r1 = 16'd0;
-wire a7ddrphy_dq_oe;
-wire a7ddrphy_dq_oe_delay_tappeddelayline;
-reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
-reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
-wire a7ddrphy_dq_o_nodelay0;
-wire a7ddrphy_dq_i_nodelay0;
-wire a7ddrphy_dq_i_delayed0;
-wire a7ddrphy_dq_t0;
-reg [7:0] a7ddrphy_bitslip02 = 8'd0;
-reg [2:0] a7ddrphy_bitslip0_value2 = 3'd7;
-reg [15:0] a7ddrphy_bitslip0_r2 = 16'd0;
-wire [7:0] a7ddrphy_bitslip03;
-reg [7:0] a7ddrphy_bitslip04 = 8'd0;
-reg [2:0] a7ddrphy_bitslip0_value3 = 3'd7;
-reg [15:0] a7ddrphy_bitslip0_r3 = 16'd0;
-wire a7ddrphy_dq_o_nodelay1;
-wire a7ddrphy_dq_i_nodelay1;
-wire a7ddrphy_dq_i_delayed1;
-wire a7ddrphy_dq_t1;
-reg [7:0] a7ddrphy_bitslip12 = 8'd0;
-reg [2:0] a7ddrphy_bitslip1_value2 = 3'd7;
-reg [15:0] a7ddrphy_bitslip1_r2 = 16'd0;
-wire [7:0] a7ddrphy_bitslip13;
-reg [7:0] a7ddrphy_bitslip14 = 8'd0;
-reg [2:0] a7ddrphy_bitslip1_value3 = 3'd7;
-reg [15:0] a7ddrphy_bitslip1_r3 = 16'd0;
-wire a7ddrphy_dq_o_nodelay2;
-wire a7ddrphy_dq_i_nodelay2;
-wire a7ddrphy_dq_i_delayed2;
-wire a7ddrphy_dq_t2;
-reg [7:0] a7ddrphy_bitslip20 = 8'd0;
-reg [2:0] a7ddrphy_bitslip2_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip2_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip21;
-reg [7:0] a7ddrphy_bitslip22 = 8'd0;
-reg [2:0] a7ddrphy_bitslip2_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip2_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay3;
-wire a7ddrphy_dq_i_nodelay3;
-wire a7ddrphy_dq_i_delayed3;
-wire a7ddrphy_dq_t3;
-reg [7:0] a7ddrphy_bitslip30 = 8'd0;
-reg [2:0] a7ddrphy_bitslip3_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip3_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip31;
-reg [7:0] a7ddrphy_bitslip32 = 8'd0;
-reg [2:0] a7ddrphy_bitslip3_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip3_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay4;
-wire a7ddrphy_dq_i_nodelay4;
-wire a7ddrphy_dq_i_delayed4;
-wire a7ddrphy_dq_t4;
-reg [7:0] a7ddrphy_bitslip40 = 8'd0;
-reg [2:0] a7ddrphy_bitslip4_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip4_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip41;
-reg [7:0] a7ddrphy_bitslip42 = 8'd0;
-reg [2:0] a7ddrphy_bitslip4_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip4_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay5;
-wire a7ddrphy_dq_i_nodelay5;
-wire a7ddrphy_dq_i_delayed5;
-wire a7ddrphy_dq_t5;
-reg [7:0] a7ddrphy_bitslip50 = 8'd0;
-reg [2:0] a7ddrphy_bitslip5_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip5_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip51;
-reg [7:0] a7ddrphy_bitslip52 = 8'd0;
-reg [2:0] a7ddrphy_bitslip5_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip5_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay6;
-wire a7ddrphy_dq_i_nodelay6;
-wire a7ddrphy_dq_i_delayed6;
-wire a7ddrphy_dq_t6;
-reg [7:0] a7ddrphy_bitslip60 = 8'd0;
-reg [2:0] a7ddrphy_bitslip6_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip6_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip61;
-reg [7:0] a7ddrphy_bitslip62 = 8'd0;
-reg [2:0] a7ddrphy_bitslip6_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip6_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay7;
-wire a7ddrphy_dq_i_nodelay7;
-wire a7ddrphy_dq_i_delayed7;
-wire a7ddrphy_dq_t7;
-reg [7:0] a7ddrphy_bitslip70 = 8'd0;
-reg [2:0] a7ddrphy_bitslip7_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip7_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip71;
-reg [7:0] a7ddrphy_bitslip72 = 8'd0;
-reg [2:0] a7ddrphy_bitslip7_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip7_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay8;
-wire a7ddrphy_dq_i_nodelay8;
-wire a7ddrphy_dq_i_delayed8;
-wire a7ddrphy_dq_t8;
-reg [7:0] a7ddrphy_bitslip80 = 8'd0;
-reg [2:0] a7ddrphy_bitslip8_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip8_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip81;
-reg [7:0] a7ddrphy_bitslip82 = 8'd0;
-reg [2:0] a7ddrphy_bitslip8_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip8_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay9;
-wire a7ddrphy_dq_i_nodelay9;
-wire a7ddrphy_dq_i_delayed9;
-wire a7ddrphy_dq_t9;
-reg [7:0] a7ddrphy_bitslip90 = 8'd0;
-reg [2:0] a7ddrphy_bitslip9_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip9_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip91;
-reg [7:0] a7ddrphy_bitslip92 = 8'd0;
-reg [2:0] a7ddrphy_bitslip9_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip9_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay10;
-wire a7ddrphy_dq_i_nodelay10;
-wire a7ddrphy_dq_i_delayed10;
-wire a7ddrphy_dq_t10;
-reg [7:0] a7ddrphy_bitslip100 = 8'd0;
-reg [2:0] a7ddrphy_bitslip10_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip10_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip101;
-reg [7:0] a7ddrphy_bitslip102 = 8'd0;
-reg [2:0] a7ddrphy_bitslip10_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip10_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay11;
-wire a7ddrphy_dq_i_nodelay11;
-wire a7ddrphy_dq_i_delayed11;
-wire a7ddrphy_dq_t11;
-reg [7:0] a7ddrphy_bitslip110 = 8'd0;
-reg [2:0] a7ddrphy_bitslip11_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip11_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip111;
-reg [7:0] a7ddrphy_bitslip112 = 8'd0;
-reg [2:0] a7ddrphy_bitslip11_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip11_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay12;
-wire a7ddrphy_dq_i_nodelay12;
-wire a7ddrphy_dq_i_delayed12;
-wire a7ddrphy_dq_t12;
-reg [7:0] a7ddrphy_bitslip120 = 8'd0;
-reg [2:0] a7ddrphy_bitslip12_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip12_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip121;
-reg [7:0] a7ddrphy_bitslip122 = 8'd0;
-reg [2:0] a7ddrphy_bitslip12_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip12_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay13;
-wire a7ddrphy_dq_i_nodelay13;
-wire a7ddrphy_dq_i_delayed13;
-wire a7ddrphy_dq_t13;
-reg [7:0] a7ddrphy_bitslip130 = 8'd0;
-reg [2:0] a7ddrphy_bitslip13_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip13_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip131;
-reg [7:0] a7ddrphy_bitslip132 = 8'd0;
-reg [2:0] a7ddrphy_bitslip13_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip13_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay14;
-wire a7ddrphy_dq_i_nodelay14;
-wire a7ddrphy_dq_i_delayed14;
-wire a7ddrphy_dq_t14;
-reg [7:0] a7ddrphy_bitslip140 = 8'd0;
-reg [2:0] a7ddrphy_bitslip14_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip14_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip141;
-reg [7:0] a7ddrphy_bitslip142 = 8'd0;
-reg [2:0] a7ddrphy_bitslip14_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip14_r1 = 16'd0;
-wire a7ddrphy_dq_o_nodelay15;
-wire a7ddrphy_dq_i_nodelay15;
-wire a7ddrphy_dq_i_delayed15;
-wire a7ddrphy_dq_t15;
-reg [7:0] a7ddrphy_bitslip150 = 8'd0;
-reg [2:0] a7ddrphy_bitslip15_value0 = 3'd7;
-reg [15:0] a7ddrphy_bitslip15_r0 = 16'd0;
-wire [7:0] a7ddrphy_bitslip151;
-reg [7:0] a7ddrphy_bitslip152 = 8'd0;
-reg [2:0] a7ddrphy_bitslip15_value1 = 3'd7;
-reg [15:0] a7ddrphy_bitslip15_r1 = 16'd0;
-reg a7ddrphy_rddata_en_tappeddelayline0 = 1'd0;
-reg a7ddrphy_rddata_en_tappeddelayline1 = 1'd0;
-reg a7ddrphy_rddata_en_tappeddelayline2 = 1'd0;
-reg a7ddrphy_rddata_en_tappeddelayline3 = 1'd0;
-reg a7ddrphy_rddata_en_tappeddelayline4 = 1'd0;
-reg a7ddrphy_rddata_en_tappeddelayline5 = 1'd0;
-reg a7ddrphy_rddata_en_tappeddelayline6 = 1'd0;
-reg a7ddrphy_rddata_en_tappeddelayline7 = 1'd0;
-reg a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
-reg a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
-reg a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
-wire [13:0] litedramcore_slave_p0_address;
-wire [2:0] litedramcore_slave_p0_bank;
-wire litedramcore_slave_p0_cas_n;
-wire litedramcore_slave_p0_cs_n;
-wire litedramcore_slave_p0_ras_n;
-wire litedramcore_slave_p0_we_n;
-wire litedramcore_slave_p0_cke;
-wire litedramcore_slave_p0_odt;
-wire litedramcore_slave_p0_reset_n;
-wire litedramcore_slave_p0_act_n;
-wire [31:0] litedramcore_slave_p0_wrdata;
-wire litedramcore_slave_p0_wrdata_en;
-wire [3:0] litedramcore_slave_p0_wrdata_mask;
-wire litedramcore_slave_p0_rddata_en;
-reg [31:0] litedramcore_slave_p0_rddata = 32'd0;
-reg litedramcore_slave_p0_rddata_valid = 1'd0;
-wire [13:0] litedramcore_slave_p1_address;
-wire [2:0] litedramcore_slave_p1_bank;
-wire litedramcore_slave_p1_cas_n;
-wire litedramcore_slave_p1_cs_n;
-wire litedramcore_slave_p1_ras_n;
-wire litedramcore_slave_p1_we_n;
-wire litedramcore_slave_p1_cke;
-wire litedramcore_slave_p1_odt;
-wire litedramcore_slave_p1_reset_n;
-wire litedramcore_slave_p1_act_n;
-wire [31:0] litedramcore_slave_p1_wrdata;
-wire litedramcore_slave_p1_wrdata_en;
-wire [3:0] litedramcore_slave_p1_wrdata_mask;
-wire litedramcore_slave_p1_rddata_en;
-reg [31:0] litedramcore_slave_p1_rddata = 32'd0;
-reg litedramcore_slave_p1_rddata_valid = 1'd0;
-wire [13:0] litedramcore_slave_p2_address;
-wire [2:0] litedramcore_slave_p2_bank;
-wire litedramcore_slave_p2_cas_n;
-wire litedramcore_slave_p2_cs_n;
-wire litedramcore_slave_p2_ras_n;
-wire litedramcore_slave_p2_we_n;
-wire litedramcore_slave_p2_cke;
-wire litedramcore_slave_p2_odt;
-wire litedramcore_slave_p2_reset_n;
-wire litedramcore_slave_p2_act_n;
-wire [31:0] litedramcore_slave_p2_wrdata;
-wire litedramcore_slave_p2_wrdata_en;
-wire [3:0] litedramcore_slave_p2_wrdata_mask;
-wire litedramcore_slave_p2_rddata_en;
-reg [31:0] litedramcore_slave_p2_rddata = 32'd0;
-reg litedramcore_slave_p2_rddata_valid = 1'd0;
-wire [13:0] litedramcore_slave_p3_address;
-wire [2:0] litedramcore_slave_p3_bank;
-wire litedramcore_slave_p3_cas_n;
-wire litedramcore_slave_p3_cs_n;
-wire litedramcore_slave_p3_ras_n;
-wire litedramcore_slave_p3_we_n;
-wire litedramcore_slave_p3_cke;
-wire litedramcore_slave_p3_odt;
-wire litedramcore_slave_p3_reset_n;
-wire litedramcore_slave_p3_act_n;
-wire [31:0] litedramcore_slave_p3_wrdata;
-wire litedramcore_slave_p3_wrdata_en;
-wire [3:0] litedramcore_slave_p3_wrdata_mask;
-wire litedramcore_slave_p3_rddata_en;
-reg [31:0] litedramcore_slave_p3_rddata = 32'd0;
-reg litedramcore_slave_p3_rddata_valid = 1'd0;
-reg [13:0] litedramcore_master_p0_address = 14'd0;
-reg [2:0] litedramcore_master_p0_bank = 3'd0;
-reg litedramcore_master_p0_cas_n = 1'd1;
-reg litedramcore_master_p0_cs_n = 1'd1;
-reg litedramcore_master_p0_ras_n = 1'd1;
-reg litedramcore_master_p0_we_n = 1'd1;
-reg litedramcore_master_p0_cke = 1'd0;
-reg litedramcore_master_p0_odt = 1'd0;
-reg litedramcore_master_p0_reset_n = 1'd0;
-reg litedramcore_master_p0_act_n = 1'd1;
-reg [31:0] litedramcore_master_p0_wrdata = 32'd0;
-reg litedramcore_master_p0_wrdata_en = 1'd0;
-reg [3:0] litedramcore_master_p0_wrdata_mask = 4'd0;
-reg litedramcore_master_p0_rddata_en = 1'd0;
-wire [31:0] litedramcore_master_p0_rddata;
-wire litedramcore_master_p0_rddata_valid;
-reg [13:0] litedramcore_master_p1_address = 14'd0;
-reg [2:0] litedramcore_master_p1_bank = 3'd0;
-reg litedramcore_master_p1_cas_n = 1'd1;
-reg litedramcore_master_p1_cs_n = 1'd1;
-reg litedramcore_master_p1_ras_n = 1'd1;
-reg litedramcore_master_p1_we_n = 1'd1;
-reg litedramcore_master_p1_cke = 1'd0;
-reg litedramcore_master_p1_odt = 1'd0;
-reg litedramcore_master_p1_reset_n = 1'd0;
-reg litedramcore_master_p1_act_n = 1'd1;
-reg [31:0] litedramcore_master_p1_wrdata = 32'd0;
-reg litedramcore_master_p1_wrdata_en = 1'd0;
-reg [3:0] litedramcore_master_p1_wrdata_mask = 4'd0;
-reg litedramcore_master_p1_rddata_en = 1'd0;
-wire [31:0] litedramcore_master_p1_rddata;
-wire litedramcore_master_p1_rddata_valid;
-reg [13:0] litedramcore_master_p2_address = 14'd0;
-reg [2:0] litedramcore_master_p2_bank = 3'd0;
-reg litedramcore_master_p2_cas_n = 1'd1;
-reg litedramcore_master_p2_cs_n = 1'd1;
-reg litedramcore_master_p2_ras_n = 1'd1;
-reg litedramcore_master_p2_we_n = 1'd1;
-reg litedramcore_master_p2_cke = 1'd0;
-reg litedramcore_master_p2_odt = 1'd0;
-reg litedramcore_master_p2_reset_n = 1'd0;
-reg litedramcore_master_p2_act_n = 1'd1;
-reg [31:0] litedramcore_master_p2_wrdata = 32'd0;
-reg litedramcore_master_p2_wrdata_en = 1'd0;
-reg [3:0] litedramcore_master_p2_wrdata_mask = 4'd0;
-reg litedramcore_master_p2_rddata_en = 1'd0;
-wire [31:0] litedramcore_master_p2_rddata;
-wire litedramcore_master_p2_rddata_valid;
-reg [13:0] litedramcore_master_p3_address = 14'd0;
-reg [2:0] litedramcore_master_p3_bank = 3'd0;
-reg litedramcore_master_p3_cas_n = 1'd1;
-reg litedramcore_master_p3_cs_n = 1'd1;
-reg litedramcore_master_p3_ras_n = 1'd1;
-reg litedramcore_master_p3_we_n = 1'd1;
-reg litedramcore_master_p3_cke = 1'd0;
-reg litedramcore_master_p3_odt = 1'd0;
-reg litedramcore_master_p3_reset_n = 1'd0;
-reg litedramcore_master_p3_act_n = 1'd1;
-reg [31:0] litedramcore_master_p3_wrdata = 32'd0;
-reg litedramcore_master_p3_wrdata_en = 1'd0;
-reg [3:0] litedramcore_master_p3_wrdata_mask = 4'd0;
-reg litedramcore_master_p3_rddata_en = 1'd0;
-wire [31:0] litedramcore_master_p3_rddata;
-wire litedramcore_master_p3_rddata_valid;
-wire [13:0] litedramcore_csr_dfi_p0_address;
-wire [2:0] litedramcore_csr_dfi_p0_bank;
-reg litedramcore_csr_dfi_p0_cas_n = 1'd1;
-reg litedramcore_csr_dfi_p0_cs_n = 1'd1;
-reg litedramcore_csr_dfi_p0_ras_n = 1'd1;
-reg litedramcore_csr_dfi_p0_we_n = 1'd1;
-wire litedramcore_csr_dfi_p0_cke;
-wire litedramcore_csr_dfi_p0_odt;
-wire litedramcore_csr_dfi_p0_reset_n;
-reg litedramcore_csr_dfi_p0_act_n = 1'd1;
-wire [31:0] litedramcore_csr_dfi_p0_wrdata;
-wire litedramcore_csr_dfi_p0_wrdata_en;
-wire [3:0] litedramcore_csr_dfi_p0_wrdata_mask;
-wire litedramcore_csr_dfi_p0_rddata_en;
-reg [31:0] litedramcore_csr_dfi_p0_rddata = 32'd0;
-reg litedramcore_csr_dfi_p0_rddata_valid = 1'd0;
-wire [13:0] litedramcore_csr_dfi_p1_address;
-wire [2:0] litedramcore_csr_dfi_p1_bank;
-reg litedramcore_csr_dfi_p1_cas_n = 1'd1;
-reg litedramcore_csr_dfi_p1_cs_n = 1'd1;
-reg litedramcore_csr_dfi_p1_ras_n = 1'd1;
-reg litedramcore_csr_dfi_p1_we_n = 1'd1;
-wire litedramcore_csr_dfi_p1_cke;
-wire litedramcore_csr_dfi_p1_odt;
-wire litedramcore_csr_dfi_p1_reset_n;
-reg litedramcore_csr_dfi_p1_act_n = 1'd1;
-wire [31:0] litedramcore_csr_dfi_p1_wrdata;
-wire litedramcore_csr_dfi_p1_wrdata_en;
-wire [3:0] litedramcore_csr_dfi_p1_wrdata_mask;
-wire litedramcore_csr_dfi_p1_rddata_en;
-reg [31:0] litedramcore_csr_dfi_p1_rddata = 32'd0;
-reg litedramcore_csr_dfi_p1_rddata_valid = 1'd0;
-wire [13:0] litedramcore_csr_dfi_p2_address;
-wire [2:0] litedramcore_csr_dfi_p2_bank;
-reg litedramcore_csr_dfi_p2_cas_n = 1'd1;
-reg litedramcore_csr_dfi_p2_cs_n = 1'd1;
-reg litedramcore_csr_dfi_p2_ras_n = 1'd1;
-reg litedramcore_csr_dfi_p2_we_n = 1'd1;
-wire litedramcore_csr_dfi_p2_cke;
-wire litedramcore_csr_dfi_p2_odt;
-wire litedramcore_csr_dfi_p2_reset_n;
-reg litedramcore_csr_dfi_p2_act_n = 1'd1;
-wire [31:0] litedramcore_csr_dfi_p2_wrdata;
-wire litedramcore_csr_dfi_p2_wrdata_en;
-wire [3:0] litedramcore_csr_dfi_p2_wrdata_mask;
-wire litedramcore_csr_dfi_p2_rddata_en;
-reg [31:0] litedramcore_csr_dfi_p2_rddata = 32'd0;
-reg litedramcore_csr_dfi_p2_rddata_valid = 1'd0;
-wire [13:0] litedramcore_csr_dfi_p3_address;
-wire [2:0] litedramcore_csr_dfi_p3_bank;
-reg litedramcore_csr_dfi_p3_cas_n = 1'd1;
-reg litedramcore_csr_dfi_p3_cs_n = 1'd1;
-reg litedramcore_csr_dfi_p3_ras_n = 1'd1;
-reg litedramcore_csr_dfi_p3_we_n = 1'd1;
-wire litedramcore_csr_dfi_p3_cke;
-wire litedramcore_csr_dfi_p3_odt;
-wire litedramcore_csr_dfi_p3_reset_n;
-reg litedramcore_csr_dfi_p3_act_n = 1'd1;
-wire [31:0] litedramcore_csr_dfi_p3_wrdata;
-wire litedramcore_csr_dfi_p3_wrdata_en;
-wire [3:0] litedramcore_csr_dfi_p3_wrdata_mask;
-wire litedramcore_csr_dfi_p3_rddata_en;
-reg [31:0] litedramcore_csr_dfi_p3_rddata = 32'd0;
-reg litedramcore_csr_dfi_p3_rddata_valid = 1'd0;
-reg [13:0] litedramcore_ext_dfi_p0_address = 14'd0;
-reg [2:0] litedramcore_ext_dfi_p0_bank = 3'd0;
-reg litedramcore_ext_dfi_p0_cas_n = 1'd1;
-reg litedramcore_ext_dfi_p0_cs_n = 1'd1;
-reg litedramcore_ext_dfi_p0_ras_n = 1'd1;
-reg litedramcore_ext_dfi_p0_we_n = 1'd1;
-reg litedramcore_ext_dfi_p0_cke = 1'd0;
-reg litedramcore_ext_dfi_p0_odt = 1'd0;
-reg litedramcore_ext_dfi_p0_reset_n = 1'd0;
-reg litedramcore_ext_dfi_p0_act_n = 1'd1;
-reg [31:0] litedramcore_ext_dfi_p0_wrdata = 32'd0;
-reg litedramcore_ext_dfi_p0_wrdata_en = 1'd0;
-reg [3:0] litedramcore_ext_dfi_p0_wrdata_mask = 4'd0;
-reg litedramcore_ext_dfi_p0_rddata_en = 1'd0;
-reg [31:0] litedramcore_ext_dfi_p0_rddata = 32'd0;
-reg litedramcore_ext_dfi_p0_rddata_valid = 1'd0;
-reg [13:0] litedramcore_ext_dfi_p1_address = 14'd0;
-reg [2:0] litedramcore_ext_dfi_p1_bank = 3'd0;
-reg litedramcore_ext_dfi_p1_cas_n = 1'd1;
-reg litedramcore_ext_dfi_p1_cs_n = 1'd1;
-reg litedramcore_ext_dfi_p1_ras_n = 1'd1;
-reg litedramcore_ext_dfi_p1_we_n = 1'd1;
-reg litedramcore_ext_dfi_p1_cke = 1'd0;
-reg litedramcore_ext_dfi_p1_odt = 1'd0;
-reg litedramcore_ext_dfi_p1_reset_n = 1'd0;
-reg litedramcore_ext_dfi_p1_act_n = 1'd1;
-reg [31:0] litedramcore_ext_dfi_p1_wrdata = 32'd0;
-reg litedramcore_ext_dfi_p1_wrdata_en = 1'd0;
-reg [3:0] litedramcore_ext_dfi_p1_wrdata_mask = 4'd0;
-reg litedramcore_ext_dfi_p1_rddata_en = 1'd0;
-reg [31:0] litedramcore_ext_dfi_p1_rddata = 32'd0;
-reg litedramcore_ext_dfi_p1_rddata_valid = 1'd0;
-reg [13:0] litedramcore_ext_dfi_p2_address = 14'd0;
-reg [2:0] litedramcore_ext_dfi_p2_bank = 3'd0;
-reg litedramcore_ext_dfi_p2_cas_n = 1'd1;
-reg litedramcore_ext_dfi_p2_cs_n = 1'd1;
-reg litedramcore_ext_dfi_p2_ras_n = 1'd1;
-reg litedramcore_ext_dfi_p2_we_n = 1'd1;
-reg litedramcore_ext_dfi_p2_cke = 1'd0;
-reg litedramcore_ext_dfi_p2_odt = 1'd0;
-reg litedramcore_ext_dfi_p2_reset_n = 1'd0;
-reg litedramcore_ext_dfi_p2_act_n = 1'd1;
-reg [31:0] litedramcore_ext_dfi_p2_wrdata = 32'd0;
-reg litedramcore_ext_dfi_p2_wrdata_en = 1'd0;
-reg [3:0] litedramcore_ext_dfi_p2_wrdata_mask = 4'd0;
-reg litedramcore_ext_dfi_p2_rddata_en = 1'd0;
-reg [31:0] litedramcore_ext_dfi_p2_rddata = 32'd0;
-reg litedramcore_ext_dfi_p2_rddata_valid = 1'd0;
-reg [13:0] litedramcore_ext_dfi_p3_address = 14'd0;
-reg [2:0] litedramcore_ext_dfi_p3_bank = 3'd0;
-reg litedramcore_ext_dfi_p3_cas_n = 1'd1;
-reg litedramcore_ext_dfi_p3_cs_n = 1'd1;
-reg litedramcore_ext_dfi_p3_ras_n = 1'd1;
-reg litedramcore_ext_dfi_p3_we_n = 1'd1;
-reg litedramcore_ext_dfi_p3_cke = 1'd0;
-reg litedramcore_ext_dfi_p3_odt = 1'd0;
-reg litedramcore_ext_dfi_p3_reset_n = 1'd0;
-reg litedramcore_ext_dfi_p3_act_n = 1'd1;
-reg [31:0] litedramcore_ext_dfi_p3_wrdata = 32'd0;
-reg litedramcore_ext_dfi_p3_wrdata_en = 1'd0;
-reg [3:0] litedramcore_ext_dfi_p3_wrdata_mask = 4'd0;
-reg litedramcore_ext_dfi_p3_rddata_en = 1'd0;
-reg [31:0] litedramcore_ext_dfi_p3_rddata = 32'd0;
-reg litedramcore_ext_dfi_p3_rddata_valid = 1'd0;
-reg litedramcore_ext_dfi_sel = 1'd0;
-wire litedramcore_sel;
-wire litedramcore_cke;
-wire litedramcore_odt;
-wire litedramcore_reset_n;
-reg [3:0] litedramcore_storage = 4'd1;
-reg litedramcore_re = 1'd0;
-wire litedramcore_phaseinjector0_csrfield_cs;
-wire litedramcore_phaseinjector0_csrfield_we;
-wire litedramcore_phaseinjector0_csrfield_cas;
-wire litedramcore_phaseinjector0_csrfield_ras;
-wire litedramcore_phaseinjector0_csrfield_wren;
-wire litedramcore_phaseinjector0_csrfield_rden;
-reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0;
-reg litedramcore_phaseinjector0_command_re = 1'd0;
-reg litedramcore_phaseinjector0_command_issue_re = 1'd0;
-wire litedramcore_phaseinjector0_command_issue_r;
-reg litedramcore_phaseinjector0_command_issue_we = 1'd0;
-reg litedramcore_phaseinjector0_command_issue_w = 1'd0;
-reg [13:0] litedramcore_phaseinjector0_address_storage = 14'd0;
-reg litedramcore_phaseinjector0_address_re = 1'd0;
-reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0;
-reg litedramcore_phaseinjector0_baddress_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector0_wrdata_storage = 32'd0;
-reg litedramcore_phaseinjector0_wrdata_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector0_rddata_status = 32'd0;
-wire litedramcore_phaseinjector0_rddata_we;
-reg litedramcore_phaseinjector0_rddata_re = 1'd0;
-wire litedramcore_phaseinjector1_csrfield_cs;
-wire litedramcore_phaseinjector1_csrfield_we;
-wire litedramcore_phaseinjector1_csrfield_cas;
-wire litedramcore_phaseinjector1_csrfield_ras;
-wire litedramcore_phaseinjector1_csrfield_wren;
-wire litedramcore_phaseinjector1_csrfield_rden;
-reg [5:0] litedramcore_phaseinjector1_command_storage = 6'd0;
-reg litedramcore_phaseinjector1_command_re = 1'd0;
-reg litedramcore_phaseinjector1_command_issue_re = 1'd0;
-wire litedramcore_phaseinjector1_command_issue_r;
-reg litedramcore_phaseinjector1_command_issue_we = 1'd0;
-reg litedramcore_phaseinjector1_command_issue_w = 1'd0;
-reg [13:0] litedramcore_phaseinjector1_address_storage = 14'd0;
-reg litedramcore_phaseinjector1_address_re = 1'd0;
-reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0;
-reg litedramcore_phaseinjector1_baddress_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector1_wrdata_storage = 32'd0;
-reg litedramcore_phaseinjector1_wrdata_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector1_rddata_status = 32'd0;
-wire litedramcore_phaseinjector1_rddata_we;
-reg litedramcore_phaseinjector1_rddata_re = 1'd0;
-wire litedramcore_phaseinjector2_csrfield_cs;
-wire litedramcore_phaseinjector2_csrfield_we;
-wire litedramcore_phaseinjector2_csrfield_cas;
-wire litedramcore_phaseinjector2_csrfield_ras;
-wire litedramcore_phaseinjector2_csrfield_wren;
-wire litedramcore_phaseinjector2_csrfield_rden;
-reg [5:0] litedramcore_phaseinjector2_command_storage = 6'd0;
-reg litedramcore_phaseinjector2_command_re = 1'd0;
-reg litedramcore_phaseinjector2_command_issue_re = 1'd0;
-wire litedramcore_phaseinjector2_command_issue_r;
-reg litedramcore_phaseinjector2_command_issue_we = 1'd0;
-reg litedramcore_phaseinjector2_command_issue_w = 1'd0;
-reg [13:0] litedramcore_phaseinjector2_address_storage = 14'd0;
-reg litedramcore_phaseinjector2_address_re = 1'd0;
-reg [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0;
-reg litedramcore_phaseinjector2_baddress_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector2_wrdata_storage = 32'd0;
-reg litedramcore_phaseinjector2_wrdata_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector2_rddata_status = 32'd0;
-wire litedramcore_phaseinjector2_rddata_we;
-reg litedramcore_phaseinjector2_rddata_re = 1'd0;
-wire litedramcore_phaseinjector3_csrfield_cs;
-wire litedramcore_phaseinjector3_csrfield_we;
-wire litedramcore_phaseinjector3_csrfield_cas;
-wire litedramcore_phaseinjector3_csrfield_ras;
-wire litedramcore_phaseinjector3_csrfield_wren;
-wire litedramcore_phaseinjector3_csrfield_rden;
-reg [5:0] litedramcore_phaseinjector3_command_storage = 6'd0;
-reg litedramcore_phaseinjector3_command_re = 1'd0;
-reg litedramcore_phaseinjector3_command_issue_re = 1'd0;
-wire litedramcore_phaseinjector3_command_issue_r;
-reg litedramcore_phaseinjector3_command_issue_we = 1'd0;
-reg litedramcore_phaseinjector3_command_issue_w = 1'd0;
-reg [13:0] litedramcore_phaseinjector3_address_storage = 14'd0;
-reg litedramcore_phaseinjector3_address_re = 1'd0;
-reg [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0;
-reg litedramcore_phaseinjector3_baddress_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector3_wrdata_storage = 32'd0;
-reg litedramcore_phaseinjector3_wrdata_re = 1'd0;
-reg [31:0] litedramcore_phaseinjector3_rddata_status = 32'd0;
-wire litedramcore_phaseinjector3_rddata_we;
-reg litedramcore_phaseinjector3_rddata_re = 1'd0;
-wire litedramcore_interface_bank0_valid;
-wire litedramcore_interface_bank0_ready;
-wire litedramcore_interface_bank0_we;
-wire [20:0] litedramcore_interface_bank0_addr;
-wire litedramcore_interface_bank0_lock;
-wire litedramcore_interface_bank0_wdata_ready;
-wire litedramcore_interface_bank0_rdata_valid;
-wire litedramcore_interface_bank1_valid;
-wire litedramcore_interface_bank1_ready;
-wire litedramcore_interface_bank1_we;
-wire [20:0] litedramcore_interface_bank1_addr;
-wire litedramcore_interface_bank1_lock;
-wire litedramcore_interface_bank1_wdata_ready;
-wire litedramcore_interface_bank1_rdata_valid;
-wire litedramcore_interface_bank2_valid;
-wire litedramcore_interface_bank2_ready;
-wire litedramcore_interface_bank2_we;
-wire [20:0] litedramcore_interface_bank2_addr;
-wire litedramcore_interface_bank2_lock;
-wire litedramcore_interface_bank2_wdata_ready;
-wire litedramcore_interface_bank2_rdata_valid;
-wire litedramcore_interface_bank3_valid;
-wire litedramcore_interface_bank3_ready;
-wire litedramcore_interface_bank3_we;
-wire [20:0] litedramcore_interface_bank3_addr;
-wire litedramcore_interface_bank3_lock;
-wire litedramcore_interface_bank3_wdata_ready;
-wire litedramcore_interface_bank3_rdata_valid;
-wire litedramcore_interface_bank4_valid;
-wire litedramcore_interface_bank4_ready;
-wire litedramcore_interface_bank4_we;
-wire [20:0] litedramcore_interface_bank4_addr;
-wire litedramcore_interface_bank4_lock;
-wire litedramcore_interface_bank4_wdata_ready;
-wire litedramcore_interface_bank4_rdata_valid;
-wire litedramcore_interface_bank5_valid;
-wire litedramcore_interface_bank5_ready;
-wire litedramcore_interface_bank5_we;
-wire [20:0] litedramcore_interface_bank5_addr;
-wire litedramcore_interface_bank5_lock;
-wire litedramcore_interface_bank5_wdata_ready;
-wire litedramcore_interface_bank5_rdata_valid;
-wire litedramcore_interface_bank6_valid;
-wire litedramcore_interface_bank6_ready;
-wire litedramcore_interface_bank6_we;
-wire [20:0] litedramcore_interface_bank6_addr;
-wire litedramcore_interface_bank6_lock;
-wire litedramcore_interface_bank6_wdata_ready;
-wire litedramcore_interface_bank6_rdata_valid;
-wire litedramcore_interface_bank7_valid;
-wire litedramcore_interface_bank7_ready;
-wire litedramcore_interface_bank7_we;
-wire [20:0] litedramcore_interface_bank7_addr;
-wire litedramcore_interface_bank7_lock;
-wire litedramcore_interface_bank7_wdata_ready;
-wire litedramcore_interface_bank7_rdata_valid;
-reg [127:0] litedramcore_interface_wdata = 128'd0;
-reg [15:0] litedramcore_interface_wdata_we = 16'd0;
-wire [127:0] litedramcore_interface_rdata;
-reg [13:0] litedramcore_dfi_p0_address = 14'd0;
-reg [2:0] litedramcore_dfi_p0_bank = 3'd0;
-reg litedramcore_dfi_p0_cas_n = 1'd1;
-reg litedramcore_dfi_p0_cs_n = 1'd1;
-reg litedramcore_dfi_p0_ras_n = 1'd1;
-reg litedramcore_dfi_p0_we_n = 1'd1;
-wire litedramcore_dfi_p0_cke;
-wire litedramcore_dfi_p0_odt;
-wire litedramcore_dfi_p0_reset_n;
-reg litedramcore_dfi_p0_act_n = 1'd1;
-wire [31:0] litedramcore_dfi_p0_wrdata;
-reg litedramcore_dfi_p0_wrdata_en = 1'd0;
-wire [3:0] litedramcore_dfi_p0_wrdata_mask;
-reg litedramcore_dfi_p0_rddata_en = 1'd0;
-wire [31:0] litedramcore_dfi_p0_rddata;
-wire litedramcore_dfi_p0_rddata_valid;
-reg [13:0] litedramcore_dfi_p1_address = 14'd0;
-reg [2:0] litedramcore_dfi_p1_bank = 3'd0;
-reg litedramcore_dfi_p1_cas_n = 1'd1;
-reg litedramcore_dfi_p1_cs_n = 1'd1;
-reg litedramcore_dfi_p1_ras_n = 1'd1;
-reg litedramcore_dfi_p1_we_n = 1'd1;
-wire litedramcore_dfi_p1_cke;
-wire litedramcore_dfi_p1_odt;
-wire litedramcore_dfi_p1_reset_n;
-reg litedramcore_dfi_p1_act_n = 1'd1;
-wire [31:0] litedramcore_dfi_p1_wrdata;
-reg litedramcore_dfi_p1_wrdata_en = 1'd0;
-wire [3:0] litedramcore_dfi_p1_wrdata_mask;
-reg litedramcore_dfi_p1_rddata_en = 1'd0;
-wire [31:0] litedramcore_dfi_p1_rddata;
-wire litedramcore_dfi_p1_rddata_valid;
-reg [13:0] litedramcore_dfi_p2_address = 14'd0;
-reg [2:0] litedramcore_dfi_p2_bank = 3'd0;
-reg litedramcore_dfi_p2_cas_n = 1'd1;
-reg litedramcore_dfi_p2_cs_n = 1'd1;
-reg litedramcore_dfi_p2_ras_n = 1'd1;
-reg litedramcore_dfi_p2_we_n = 1'd1;
-wire litedramcore_dfi_p2_cke;
-wire litedramcore_dfi_p2_odt;
-wire litedramcore_dfi_p2_reset_n;
-reg litedramcore_dfi_p2_act_n = 1'd1;
-wire [31:0] litedramcore_dfi_p2_wrdata;
-reg litedramcore_dfi_p2_wrdata_en = 1'd0;
-wire [3:0] litedramcore_dfi_p2_wrdata_mask;
-reg litedramcore_dfi_p2_rddata_en = 1'd0;
-wire [31:0] litedramcore_dfi_p2_rddata;
-wire litedramcore_dfi_p2_rddata_valid;
-reg [13:0] litedramcore_dfi_p3_address = 14'd0;
-reg [2:0] litedramcore_dfi_p3_bank = 3'd0;
-reg litedramcore_dfi_p3_cas_n = 1'd1;
-reg litedramcore_dfi_p3_cs_n = 1'd1;
-reg litedramcore_dfi_p3_ras_n = 1'd1;
-reg litedramcore_dfi_p3_we_n = 1'd1;
-wire litedramcore_dfi_p3_cke;
-wire litedramcore_dfi_p3_odt;
-wire litedramcore_dfi_p3_reset_n;
-reg litedramcore_dfi_p3_act_n = 1'd1;
-wire [31:0] litedramcore_dfi_p3_wrdata;
-reg litedramcore_dfi_p3_wrdata_en = 1'd0;
-wire [3:0] litedramcore_dfi_p3_wrdata_mask;
-reg litedramcore_dfi_p3_rddata_en = 1'd0;
-wire [31:0] litedramcore_dfi_p3_rddata;
-wire litedramcore_dfi_p3_rddata_valid;
-reg litedramcore_cmd_valid = 1'd0;
-reg litedramcore_cmd_ready = 1'd0;
-reg litedramcore_cmd_last = 1'd0;
-reg [13:0] litedramcore_cmd_payload_a = 14'd0;
-reg [2:0] litedramcore_cmd_payload_ba = 3'd0;
-reg litedramcore_cmd_payload_cas = 1'd0;
-reg litedramcore_cmd_payload_ras = 1'd0;
-reg litedramcore_cmd_payload_we = 1'd0;
-reg litedramcore_cmd_payload_is_read = 1'd0;
-reg litedramcore_cmd_payload_is_write = 1'd0;
-wire litedramcore_wants_refresh;
-wire litedramcore_wants_zqcs;
-wire litedramcore_timer_wait;
-wire litedramcore_timer_done0;
-wire [9:0] litedramcore_timer_count0;
-wire litedramcore_timer_done1;
-reg [9:0] litedramcore_timer_count1 = 10'd781;
-wire litedramcore_postponer_req_i;
-reg litedramcore_postponer_req_o = 1'd0;
-reg litedramcore_postponer_count = 1'd0;
-reg litedramcore_sequencer_start0 = 1'd0;
-wire litedramcore_sequencer_done0;
-wire litedramcore_sequencer_start1;
-reg litedramcore_sequencer_done1 = 1'd0;
-reg [5:0] litedramcore_sequencer_counter = 6'd0;
-reg litedramcore_sequencer_count = 1'd0;
-wire litedramcore_zqcs_timer_wait;
-wire litedramcore_zqcs_timer_done0;
-wire [26:0] litedramcore_zqcs_timer_count0;
-wire litedramcore_zqcs_timer_done1;
-reg [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999;
-reg litedramcore_zqcs_executer_start = 1'd0;
-reg litedramcore_zqcs_executer_done = 1'd0;
-reg [4:0] litedramcore_zqcs_executer_counter = 5'd0;
-wire litedramcore_bankmachine0_req_valid;
-wire litedramcore_bankmachine0_req_ready;
-wire litedramcore_bankmachine0_req_we;
-wire [20:0] litedramcore_bankmachine0_req_addr;
-wire litedramcore_bankmachine0_req_lock;
-reg litedramcore_bankmachine0_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine0_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine0_refresh_req;
-reg litedramcore_bankmachine0_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine0_cmd_valid = 1'd0;
-reg litedramcore_bankmachine0_cmd_ready = 1'd0;
-reg [13:0] litedramcore_bankmachine0_cmd_payload_a = 14'd0;
-wire [2:0] litedramcore_bankmachine0_cmd_payload_ba;
-reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine0_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine0_auto_precharge = 1'd0;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
-wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
-wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-reg [4:0] litedramcore_bankmachine0_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine0_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we;
-wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine0_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine0_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine0_cmd_buffer_sink_first;
-wire litedramcore_bankmachine0_cmd_buffer_sink_last;
-wire litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
-wire [20:0] litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine0_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine0_cmd_buffer_source_ready;
-reg litedramcore_bankmachine0_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine0_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine0_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] litedramcore_bankmachine0_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] litedramcore_bankmachine0_row = 14'd0;
-reg litedramcore_bankmachine0_row_opened = 1'd0;
-wire litedramcore_bankmachine0_row_hit;
-reg litedramcore_bankmachine0_row_open = 1'd0;
-reg litedramcore_bankmachine0_row_close = 1'd0;
-reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine0_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine0_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine0_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine0_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine0_trccon_count = 3'd0;
-wire litedramcore_bankmachine0_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine0_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine0_trascon_count = 3'd0;
-wire litedramcore_bankmachine1_req_valid;
-wire litedramcore_bankmachine1_req_ready;
-wire litedramcore_bankmachine1_req_we;
-wire [20:0] litedramcore_bankmachine1_req_addr;
-wire litedramcore_bankmachine1_req_lock;
-reg litedramcore_bankmachine1_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine1_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine1_refresh_req;
-reg litedramcore_bankmachine1_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine1_cmd_valid = 1'd0;
-reg litedramcore_bankmachine1_cmd_ready = 1'd0;
-reg [13:0] litedramcore_bankmachine1_cmd_payload_a = 14'd0;
-wire [2:0] litedramcore_bankmachine1_cmd_payload_ba;
-reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine1_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine1_auto_precharge = 1'd0;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
-wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
-wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-reg [4:0] litedramcore_bankmachine1_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine1_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we;
-wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine1_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine1_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine1_cmd_buffer_sink_first;
-wire litedramcore_bankmachine1_cmd_buffer_sink_last;
-wire litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
-wire [20:0] litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine1_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine1_cmd_buffer_source_ready;
-reg litedramcore_bankmachine1_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine1_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine1_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] litedramcore_bankmachine1_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] litedramcore_bankmachine1_row = 14'd0;
-reg litedramcore_bankmachine1_row_opened = 1'd0;
-wire litedramcore_bankmachine1_row_hit;
-reg litedramcore_bankmachine1_row_open = 1'd0;
-reg litedramcore_bankmachine1_row_close = 1'd0;
-reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine1_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine1_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine1_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine1_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine1_trccon_count = 3'd0;
-wire litedramcore_bankmachine1_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine1_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine1_trascon_count = 3'd0;
-wire litedramcore_bankmachine2_req_valid;
-wire litedramcore_bankmachine2_req_ready;
-wire litedramcore_bankmachine2_req_we;
-wire [20:0] litedramcore_bankmachine2_req_addr;
-wire litedramcore_bankmachine2_req_lock;
-reg litedramcore_bankmachine2_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine2_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine2_refresh_req;
-reg litedramcore_bankmachine2_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine2_cmd_valid = 1'd0;
-reg litedramcore_bankmachine2_cmd_ready = 1'd0;
-reg [13:0] litedramcore_bankmachine2_cmd_payload_a = 14'd0;
-wire [2:0] litedramcore_bankmachine2_cmd_payload_ba;
-reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine2_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine2_auto_precharge = 1'd0;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
-wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
-wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-reg [4:0] litedramcore_bankmachine2_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine2_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we;
-wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine2_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine2_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine2_cmd_buffer_sink_first;
-wire litedramcore_bankmachine2_cmd_buffer_sink_last;
-wire litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
-wire [20:0] litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine2_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine2_cmd_buffer_source_ready;
-reg litedramcore_bankmachine2_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine2_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine2_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] litedramcore_bankmachine2_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] litedramcore_bankmachine2_row = 14'd0;
-reg litedramcore_bankmachine2_row_opened = 1'd0;
-wire litedramcore_bankmachine2_row_hit;
-reg litedramcore_bankmachine2_row_open = 1'd0;
-reg litedramcore_bankmachine2_row_close = 1'd0;
-reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine2_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine2_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine2_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine2_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine2_trccon_count = 3'd0;
-wire litedramcore_bankmachine2_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine2_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine2_trascon_count = 3'd0;
-wire litedramcore_bankmachine3_req_valid;
-wire litedramcore_bankmachine3_req_ready;
-wire litedramcore_bankmachine3_req_we;
-wire [20:0] litedramcore_bankmachine3_req_addr;
-wire litedramcore_bankmachine3_req_lock;
-reg litedramcore_bankmachine3_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine3_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine3_refresh_req;
-reg litedramcore_bankmachine3_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine3_cmd_valid = 1'd0;
-reg litedramcore_bankmachine3_cmd_ready = 1'd0;
-reg [13:0] litedramcore_bankmachine3_cmd_payload_a = 14'd0;
-wire [2:0] litedramcore_bankmachine3_cmd_payload_ba;
-reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine3_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine3_auto_precharge = 1'd0;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
-wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
-wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-reg [4:0] litedramcore_bankmachine3_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine3_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we;
-wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine3_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine3_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine3_cmd_buffer_sink_first;
-wire litedramcore_bankmachine3_cmd_buffer_sink_last;
-wire litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
-wire [20:0] litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine3_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine3_cmd_buffer_source_ready;
-reg litedramcore_bankmachine3_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine3_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine3_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] litedramcore_bankmachine3_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] litedramcore_bankmachine3_row = 14'd0;
-reg litedramcore_bankmachine3_row_opened = 1'd0;
-wire litedramcore_bankmachine3_row_hit;
-reg litedramcore_bankmachine3_row_open = 1'd0;
-reg litedramcore_bankmachine3_row_close = 1'd0;
-reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine3_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine3_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine3_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine3_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine3_trccon_count = 3'd0;
-wire litedramcore_bankmachine3_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine3_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine3_trascon_count = 3'd0;
-wire litedramcore_bankmachine4_req_valid;
-wire litedramcore_bankmachine4_req_ready;
-wire litedramcore_bankmachine4_req_we;
-wire [20:0] litedramcore_bankmachine4_req_addr;
-wire litedramcore_bankmachine4_req_lock;
-reg litedramcore_bankmachine4_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine4_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine4_refresh_req;
-reg litedramcore_bankmachine4_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine4_cmd_valid = 1'd0;
-reg litedramcore_bankmachine4_cmd_ready = 1'd0;
-reg [13:0] litedramcore_bankmachine4_cmd_payload_a = 14'd0;
-wire [2:0] litedramcore_bankmachine4_cmd_payload_ba;
-reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine4_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine4_auto_precharge = 1'd0;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
-wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
-wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-reg [4:0] litedramcore_bankmachine4_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine4_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we;
-wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine4_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine4_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine4_cmd_buffer_sink_first;
-wire litedramcore_bankmachine4_cmd_buffer_sink_last;
-wire litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
-wire [20:0] litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine4_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine4_cmd_buffer_source_ready;
-reg litedramcore_bankmachine4_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine4_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine4_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] litedramcore_bankmachine4_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] litedramcore_bankmachine4_row = 14'd0;
-reg litedramcore_bankmachine4_row_opened = 1'd0;
-wire litedramcore_bankmachine4_row_hit;
-reg litedramcore_bankmachine4_row_open = 1'd0;
-reg litedramcore_bankmachine4_row_close = 1'd0;
-reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine4_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine4_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine4_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine4_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine4_trccon_count = 3'd0;
-wire litedramcore_bankmachine4_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine4_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine4_trascon_count = 3'd0;
-wire litedramcore_bankmachine5_req_valid;
-wire litedramcore_bankmachine5_req_ready;
-wire litedramcore_bankmachine5_req_we;
-wire [20:0] litedramcore_bankmachine5_req_addr;
-wire litedramcore_bankmachine5_req_lock;
-reg litedramcore_bankmachine5_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine5_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine5_refresh_req;
-reg litedramcore_bankmachine5_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine5_cmd_valid = 1'd0;
-reg litedramcore_bankmachine5_cmd_ready = 1'd0;
-reg [13:0] litedramcore_bankmachine5_cmd_payload_a = 14'd0;
-wire [2:0] litedramcore_bankmachine5_cmd_payload_ba;
-reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine5_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine5_auto_precharge = 1'd0;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
-wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
-wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-reg [4:0] litedramcore_bankmachine5_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine5_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we;
-wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine5_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine5_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine5_cmd_buffer_sink_first;
-wire litedramcore_bankmachine5_cmd_buffer_sink_last;
-wire litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
-wire [20:0] litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine5_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine5_cmd_buffer_source_ready;
-reg litedramcore_bankmachine5_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine5_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine5_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] litedramcore_bankmachine5_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] litedramcore_bankmachine5_row = 14'd0;
-reg litedramcore_bankmachine5_row_opened = 1'd0;
-wire litedramcore_bankmachine5_row_hit;
-reg litedramcore_bankmachine5_row_open = 1'd0;
-reg litedramcore_bankmachine5_row_close = 1'd0;
-reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine5_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine5_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine5_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine5_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine5_trccon_count = 3'd0;
-wire litedramcore_bankmachine5_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine5_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine5_trascon_count = 3'd0;
-wire litedramcore_bankmachine6_req_valid;
-wire litedramcore_bankmachine6_req_ready;
-wire litedramcore_bankmachine6_req_we;
-wire [20:0] litedramcore_bankmachine6_req_addr;
-wire litedramcore_bankmachine6_req_lock;
-reg litedramcore_bankmachine6_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine6_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine6_refresh_req;
-reg litedramcore_bankmachine6_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine6_cmd_valid = 1'd0;
-reg litedramcore_bankmachine6_cmd_ready = 1'd0;
-reg [13:0] litedramcore_bankmachine6_cmd_payload_a = 14'd0;
-wire [2:0] litedramcore_bankmachine6_cmd_payload_ba;
-reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine6_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine6_auto_precharge = 1'd0;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
-wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
-wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-reg [4:0] litedramcore_bankmachine6_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine6_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we;
-wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine6_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine6_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine6_cmd_buffer_sink_first;
-wire litedramcore_bankmachine6_cmd_buffer_sink_last;
-wire litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
-wire [20:0] litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine6_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine6_cmd_buffer_source_ready;
-reg litedramcore_bankmachine6_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine6_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine6_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] litedramcore_bankmachine6_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] litedramcore_bankmachine6_row = 14'd0;
-reg litedramcore_bankmachine6_row_opened = 1'd0;
-wire litedramcore_bankmachine6_row_hit;
-reg litedramcore_bankmachine6_row_open = 1'd0;
-reg litedramcore_bankmachine6_row_close = 1'd0;
-reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine6_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine6_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine6_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine6_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine6_trccon_count = 3'd0;
-wire litedramcore_bankmachine6_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine6_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine6_trascon_count = 3'd0;
-wire litedramcore_bankmachine7_req_valid;
-wire litedramcore_bankmachine7_req_ready;
-wire litedramcore_bankmachine7_req_we;
-wire [20:0] litedramcore_bankmachine7_req_addr;
-wire litedramcore_bankmachine7_req_lock;
-reg litedramcore_bankmachine7_req_wdata_ready = 1'd0;
-reg litedramcore_bankmachine7_req_rdata_valid = 1'd0;
-wire litedramcore_bankmachine7_refresh_req;
-reg litedramcore_bankmachine7_refresh_gnt = 1'd0;
-reg litedramcore_bankmachine7_cmd_valid = 1'd0;
-reg litedramcore_bankmachine7_cmd_ready = 1'd0;
-reg [13:0] litedramcore_bankmachine7_cmd_payload_a = 14'd0;
-wire [2:0] litedramcore_bankmachine7_cmd_payload_ba;
-reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
-reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
-reg litedramcore_bankmachine7_cmd_payload_we = 1'd0;
-reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
-reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
-reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
-reg litedramcore_bankmachine7_auto_precharge = 1'd0;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
-reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first = 1'd0;
-reg litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last = 1'd0;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
-wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
-wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
-wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
-wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-reg [4:0] litedramcore_bankmachine7_cmd_buffer_lookahead_level = 5'd0;
-reg litedramcore_bankmachine7_cmd_buffer_lookahead_replace = 1'd0;
-reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_produce = 4'd0;
-reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_consume = 4'd0;
-reg [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr = 4'd0;
-wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we;
-wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_do_read;
-wire [3:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr;
-wire [23:0] litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we;
-wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
-wire [20:0] litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
-wire litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
-wire litedramcore_bankmachine7_cmd_buffer_sink_valid;
-wire litedramcore_bankmachine7_cmd_buffer_sink_ready;
-wire litedramcore_bankmachine7_cmd_buffer_sink_first;
-wire litedramcore_bankmachine7_cmd_buffer_sink_last;
-wire litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
-wire [20:0] litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
-reg litedramcore_bankmachine7_cmd_buffer_source_valid = 1'd0;
-wire litedramcore_bankmachine7_cmd_buffer_source_ready;
-reg litedramcore_bankmachine7_cmd_buffer_source_first = 1'd0;
-reg litedramcore_bankmachine7_cmd_buffer_source_last = 1'd0;
-reg litedramcore_bankmachine7_cmd_buffer_source_payload_we = 1'd0;
-reg [20:0] litedramcore_bankmachine7_cmd_buffer_source_payload_addr = 21'd0;
-reg [13:0] litedramcore_bankmachine7_row = 14'd0;
-reg litedramcore_bankmachine7_row_opened = 1'd0;
-wire litedramcore_bankmachine7_row_hit;
-reg litedramcore_bankmachine7_row_open = 1'd0;
-reg litedramcore_bankmachine7_row_close = 1'd0;
-reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
-wire litedramcore_bankmachine7_twtpcon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine7_twtpcon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0;
-wire litedramcore_bankmachine7_trccon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine7_trccon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine7_trccon_count = 3'd0;
-wire litedramcore_bankmachine7_trascon_valid;
-(* dont_touch = "true" *) reg litedramcore_bankmachine7_trascon_ready = 1'd0;
-reg [2:0] litedramcore_bankmachine7_trascon_count = 3'd0;
-wire litedramcore_ras_allowed;
-wire litedramcore_cas_allowed;
-wire [1:0] litedramcore_rdcmdphase;
-wire [1:0] litedramcore_wrcmdphase;
-reg litedramcore_choose_cmd_want_reads = 1'd0;
-reg litedramcore_choose_cmd_want_writes = 1'd0;
-reg litedramcore_choose_cmd_want_cmds = 1'd0;
-reg litedramcore_choose_cmd_want_activates = 1'd0;
-wire litedramcore_choose_cmd_cmd_valid;
-reg litedramcore_choose_cmd_cmd_ready = 1'd0;
-wire [13:0] litedramcore_choose_cmd_cmd_payload_a;
-wire [2:0] litedramcore_choose_cmd_cmd_payload_ba;
-reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
-reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
-reg litedramcore_choose_cmd_cmd_payload_we = 1'd0;
-wire litedramcore_choose_cmd_cmd_payload_is_cmd;
-wire litedramcore_choose_cmd_cmd_payload_is_read;
-wire litedramcore_choose_cmd_cmd_payload_is_write;
-reg [7:0] litedramcore_choose_cmd_valids = 8'd0;
-wire [7:0] litedramcore_choose_cmd_request;
-reg [2:0] litedramcore_choose_cmd_grant = 3'd0;
-wire litedramcore_choose_cmd_ce;
-reg litedramcore_choose_req_want_reads = 1'd0;
-reg litedramcore_choose_req_want_writes = 1'd0;
-reg litedramcore_choose_req_want_cmds = 1'd0;
-reg litedramcore_choose_req_want_activates = 1'd0;
-wire litedramcore_choose_req_cmd_valid;
-reg litedramcore_choose_req_cmd_ready = 1'd0;
-wire [13:0] litedramcore_choose_req_cmd_payload_a;
-wire [2:0] litedramcore_choose_req_cmd_payload_ba;
-reg litedramcore_choose_req_cmd_payload_cas = 1'd0;
-reg litedramcore_choose_req_cmd_payload_ras = 1'd0;
-reg litedramcore_choose_req_cmd_payload_we = 1'd0;
-wire litedramcore_choose_req_cmd_payload_is_cmd;
-wire litedramcore_choose_req_cmd_payload_is_read;
-wire litedramcore_choose_req_cmd_payload_is_write;
-reg [7:0] litedramcore_choose_req_valids = 8'd0;
-wire [7:0] litedramcore_choose_req_request;
-reg [2:0] litedramcore_choose_req_grant = 3'd0;
-wire litedramcore_choose_req_ce;
-reg [13:0] litedramcore_nop_a = 14'd0;
-reg [2:0] litedramcore_nop_ba = 3'd0;
-reg [1:0] litedramcore_steerer_sel0 = 2'd0;
-reg [1:0] litedramcore_steerer_sel1 = 2'd0;
-reg [1:0] litedramcore_steerer_sel2 = 2'd0;
-reg [1:0] litedramcore_steerer_sel3 = 2'd0;
-reg litedramcore_steerer0 = 1'd1;
-reg litedramcore_steerer1 = 1'd1;
-reg litedramcore_steerer2 = 1'd1;
-reg litedramcore_steerer3 = 1'd1;
-reg litedramcore_steerer4 = 1'd1;
-reg litedramcore_steerer5 = 1'd1;
-reg litedramcore_steerer6 = 1'd1;
-reg litedramcore_steerer7 = 1'd1;
-wire litedramcore_trrdcon_valid;
-(* dont_touch = "true" *) reg litedramcore_trrdcon_ready = 1'd0;
-reg litedramcore_trrdcon_count = 1'd0;
-wire litedramcore_tfawcon_valid;
-(* dont_touch = "true" *) reg litedramcore_tfawcon_ready = 1'd1;
-wire [2:0] litedramcore_tfawcon_count;
-reg [4:0] litedramcore_tfawcon_window = 5'd0;
-wire litedramcore_tccdcon_valid;
-(* dont_touch = "true" *) reg litedramcore_tccdcon_ready = 1'd0;
-reg litedramcore_tccdcon_count = 1'd0;
-wire litedramcore_twtrcon_valid;
-(* dont_touch = "true" *) reg litedramcore_twtrcon_ready = 1'd0;
-reg [2:0] litedramcore_twtrcon_count = 3'd0;
-wire litedramcore_read_available;
-wire litedramcore_write_available;
-reg litedramcore_en0 = 1'd0;
-wire litedramcore_max_time0;
-reg [4:0] litedramcore_time0 = 5'd0;
-reg litedramcore_en1 = 1'd0;
-wire litedramcore_max_time1;
-reg [3:0] litedramcore_time1 = 4'd0;
-wire litedramcore_go_to_refresh;
-reg init_done_storage = 1'd0;
-reg init_done_re = 1'd0;
-reg init_error_storage = 1'd0;
-reg init_error_re = 1'd0;
-wire [29:0] wb_bus_adr;
-wire [31:0] wb_bus_dat_w;
-wire [31:0] wb_bus_dat_r;
-wire [3:0] wb_bus_sel;
-wire wb_bus_cyc;
-wire wb_bus_stb;
-wire wb_bus_ack;
-wire wb_bus_we;
-wire [2:0] wb_bus_cti;
-wire [1:0] wb_bus_bte;
-wire wb_bus_err;
-wire user_enable;
-wire user_port_cmd_valid;
-wire user_port_cmd_ready;
-wire user_port_cmd_payload_we;
-wire [23:0] user_port_cmd_payload_addr;
-wire user_port_wdata_valid;
-wire user_port_wdata_ready;
-wire [127:0] user_port_wdata_payload_data;
-wire [15:0] user_port_wdata_payload_we;
-wire user_port_rdata_valid;
-wire user_port_rdata_ready;
-wire [127:0] user_port_rdata_payload_data;
-reg [13:0] litedramcore_adr = 14'd0;
-reg litedramcore_we = 1'd0;
-reg [31:0] litedramcore_dat_w = 32'd0;
-wire [31:0] litedramcore_dat_r;
-wire [29:0] litedramcore_wishbone_adr;
-wire [31:0] litedramcore_wishbone_dat_w;
-reg [31:0] litedramcore_wishbone_dat_r = 32'd0;
-wire [3:0] litedramcore_wishbone_sel;
-wire litedramcore_wishbone_cyc;
-wire litedramcore_wishbone_stb;
-reg litedramcore_wishbone_ack = 1'd0;
-wire litedramcore_wishbone_we;
-wire [2:0] litedramcore_wishbone_cti;
-wire [1:0] litedramcore_wishbone_bte;
-reg litedramcore_wishbone_err = 1'd0;
-wire [13:0] interface0_bank_bus_adr;
-wire interface0_bank_bus_we;
-wire [31:0] interface0_bank_bus_dat_w;
-reg [31:0] interface0_bank_bus_dat_r = 32'd0;
-reg csrbank0_init_done0_re = 1'd0;
-wire csrbank0_init_done0_r;
-reg csrbank0_init_done0_we = 1'd0;
-wire csrbank0_init_done0_w;
-reg csrbank0_init_error0_re = 1'd0;
-wire csrbank0_init_error0_r;
-reg csrbank0_init_error0_we = 1'd0;
-wire csrbank0_init_error0_w;
-wire csrbank0_sel;
-wire [13:0] interface1_bank_bus_adr;
-wire interface1_bank_bus_we;
-wire [31:0] interface1_bank_bus_dat_w;
-reg [31:0] interface1_bank_bus_dat_r = 32'd0;
-reg csrbank1_rst0_re = 1'd0;
-wire csrbank1_rst0_r;
-reg csrbank1_rst0_we = 1'd0;
-wire csrbank1_rst0_w;
-reg csrbank1_dly_sel0_re = 1'd0;
-wire [1:0] csrbank1_dly_sel0_r;
-reg csrbank1_dly_sel0_we = 1'd0;
-wire [1:0] csrbank1_dly_sel0_w;
-reg csrbank1_half_sys8x_taps0_re = 1'd0;
-wire [4:0] csrbank1_half_sys8x_taps0_r;
-reg csrbank1_half_sys8x_taps0_we = 1'd0;
-wire [4:0] csrbank1_half_sys8x_taps0_w;
-reg csrbank1_wlevel_en0_re = 1'd0;
-wire csrbank1_wlevel_en0_r;
-reg csrbank1_wlevel_en0_we = 1'd0;
-wire csrbank1_wlevel_en0_w;
-reg csrbank1_rdphase0_re = 1'd0;
-wire [1:0] csrbank1_rdphase0_r;
-reg csrbank1_rdphase0_we = 1'd0;
-wire [1:0] csrbank1_rdphase0_w;
-reg csrbank1_wrphase0_re = 1'd0;
-wire [1:0] csrbank1_wrphase0_r;
-reg csrbank1_wrphase0_we = 1'd0;
-wire [1:0] csrbank1_wrphase0_w;
-wire csrbank1_sel;
-wire [13:0] interface2_bank_bus_adr;
-wire interface2_bank_bus_we;
-wire [31:0] interface2_bank_bus_dat_w;
-reg [31:0] interface2_bank_bus_dat_r = 32'd0;
-reg csrbank2_dfii_control0_re = 1'd0;
-wire [3:0] csrbank2_dfii_control0_r;
-reg csrbank2_dfii_control0_we = 1'd0;
-wire [3:0] csrbank2_dfii_control0_w;
-reg csrbank2_dfii_pi0_command0_re = 1'd0;
-wire [5:0] csrbank2_dfii_pi0_command0_r;
-reg csrbank2_dfii_pi0_command0_we = 1'd0;
-wire [5:0] csrbank2_dfii_pi0_command0_w;
-reg csrbank2_dfii_pi0_address0_re = 1'd0;
-wire [13:0] csrbank2_dfii_pi0_address0_r;
-reg csrbank2_dfii_pi0_address0_we = 1'd0;
-wire [13:0] csrbank2_dfii_pi0_address0_w;
-reg csrbank2_dfii_pi0_baddress0_re = 1'd0;
-wire [2:0] csrbank2_dfii_pi0_baddress0_r;
-reg csrbank2_dfii_pi0_baddress0_we = 1'd0;
-wire [2:0] csrbank2_dfii_pi0_baddress0_w;
-reg csrbank2_dfii_pi0_wrdata0_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi0_wrdata0_r;
-reg csrbank2_dfii_pi0_wrdata0_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi0_wrdata0_w;
-reg csrbank2_dfii_pi0_rddata_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi0_rddata_r;
-reg csrbank2_dfii_pi0_rddata_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi0_rddata_w;
-reg csrbank2_dfii_pi1_command0_re = 1'd0;
-wire [5:0] csrbank2_dfii_pi1_command0_r;
-reg csrbank2_dfii_pi1_command0_we = 1'd0;
-wire [5:0] csrbank2_dfii_pi1_command0_w;
-reg csrbank2_dfii_pi1_address0_re = 1'd0;
-wire [13:0] csrbank2_dfii_pi1_address0_r;
-reg csrbank2_dfii_pi1_address0_we = 1'd0;
-wire [13:0] csrbank2_dfii_pi1_address0_w;
-reg csrbank2_dfii_pi1_baddress0_re = 1'd0;
-wire [2:0] csrbank2_dfii_pi1_baddress0_r;
-reg csrbank2_dfii_pi1_baddress0_we = 1'd0;
-wire [2:0] csrbank2_dfii_pi1_baddress0_w;
-reg csrbank2_dfii_pi1_wrdata0_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi1_wrdata0_r;
-reg csrbank2_dfii_pi1_wrdata0_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi1_wrdata0_w;
-reg csrbank2_dfii_pi1_rddata_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi1_rddata_r;
-reg csrbank2_dfii_pi1_rddata_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi1_rddata_w;
-reg csrbank2_dfii_pi2_command0_re = 1'd0;
-wire [5:0] csrbank2_dfii_pi2_command0_r;
-reg csrbank2_dfii_pi2_command0_we = 1'd0;
-wire [5:0] csrbank2_dfii_pi2_command0_w;
-reg csrbank2_dfii_pi2_address0_re = 1'd0;
-wire [13:0] csrbank2_dfii_pi2_address0_r;
-reg csrbank2_dfii_pi2_address0_we = 1'd0;
-wire [13:0] csrbank2_dfii_pi2_address0_w;
-reg csrbank2_dfii_pi2_baddress0_re = 1'd0;
-wire [2:0] csrbank2_dfii_pi2_baddress0_r;
-reg csrbank2_dfii_pi2_baddress0_we = 1'd0;
-wire [2:0] csrbank2_dfii_pi2_baddress0_w;
-reg csrbank2_dfii_pi2_wrdata0_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi2_wrdata0_r;
-reg csrbank2_dfii_pi2_wrdata0_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi2_wrdata0_w;
-reg csrbank2_dfii_pi2_rddata_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi2_rddata_r;
-reg csrbank2_dfii_pi2_rddata_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi2_rddata_w;
-reg csrbank2_dfii_pi3_command0_re = 1'd0;
-wire [5:0] csrbank2_dfii_pi3_command0_r;
-reg csrbank2_dfii_pi3_command0_we = 1'd0;
-wire [5:0] csrbank2_dfii_pi3_command0_w;
-reg csrbank2_dfii_pi3_address0_re = 1'd0;
-wire [13:0] csrbank2_dfii_pi3_address0_r;
-reg csrbank2_dfii_pi3_address0_we = 1'd0;
-wire [13:0] csrbank2_dfii_pi3_address0_w;
-reg csrbank2_dfii_pi3_baddress0_re = 1'd0;
-wire [2:0] csrbank2_dfii_pi3_baddress0_r;
-reg csrbank2_dfii_pi3_baddress0_we = 1'd0;
-wire [2:0] csrbank2_dfii_pi3_baddress0_w;
-reg csrbank2_dfii_pi3_wrdata0_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi3_wrdata0_r;
-reg csrbank2_dfii_pi3_wrdata0_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi3_wrdata0_w;
-reg csrbank2_dfii_pi3_rddata_re = 1'd0;
-wire [31:0] csrbank2_dfii_pi3_rddata_r;
-reg csrbank2_dfii_pi3_rddata_we = 1'd0;
-wire [31:0] csrbank2_dfii_pi3_rddata_w;
-wire csrbank2_sel;
-wire [13:0] csr_interconnect_adr;
-wire csr_interconnect_we;
-wire [31:0] csr_interconnect_dat_w;
-wire [31:0] csr_interconnect_dat_r;
-wire litedramcore_reset0;
-wire litedramcore_reset1;
-wire litedramcore_reset2;
-wire litedramcore_reset3;
-wire litedramcore_reset4;
-wire litedramcore_reset5;
-wire litedramcore_reset6;
-wire litedramcore_reset7;
-wire litedramcore_pll_fb;
-reg [1:0] litedramcore_refresher_state = 2'd0;
-reg [1:0] litedramcore_refresher_next_state = 2'd0;
-reg [3:0] litedramcore_bankmachine0_state = 4'd0;
-reg [3:0] litedramcore_bankmachine0_next_state = 4'd0;
-reg [3:0] litedramcore_bankmachine1_state = 4'd0;
-reg [3:0] litedramcore_bankmachine1_next_state = 4'd0;
-reg [3:0] litedramcore_bankmachine2_state = 4'd0;
-reg [3:0] litedramcore_bankmachine2_next_state = 4'd0;
-reg [3:0] litedramcore_bankmachine3_state = 4'd0;
-reg [3:0] litedramcore_bankmachine3_next_state = 4'd0;
-reg [3:0] litedramcore_bankmachine4_state = 4'd0;
-reg [3:0] litedramcore_bankmachine4_next_state = 4'd0;
-reg [3:0] litedramcore_bankmachine5_state = 4'd0;
-reg [3:0] litedramcore_bankmachine5_next_state = 4'd0;
-reg [3:0] litedramcore_bankmachine6_state = 4'd0;
-reg [3:0] litedramcore_bankmachine6_next_state = 4'd0;
-reg [3:0] litedramcore_bankmachine7_state = 4'd0;
-reg [3:0] litedramcore_bankmachine7_next_state = 4'd0;
-reg [3:0] litedramcore_multiplexer_state = 4'd0;
-reg [3:0] litedramcore_multiplexer_next_state = 4'd0;
-wire litedramcore_roundrobin0_request;
-wire litedramcore_roundrobin0_grant;
-wire litedramcore_roundrobin0_ce;
-wire litedramcore_roundrobin1_request;
-wire litedramcore_roundrobin1_grant;
-wire litedramcore_roundrobin1_ce;
-wire litedramcore_roundrobin2_request;
-wire litedramcore_roundrobin2_grant;
-wire litedramcore_roundrobin2_ce;
-wire litedramcore_roundrobin3_request;
-wire litedramcore_roundrobin3_grant;
-wire litedramcore_roundrobin3_ce;
-wire litedramcore_roundrobin4_request;
-wire litedramcore_roundrobin4_grant;
-wire litedramcore_roundrobin4_ce;
-wire litedramcore_roundrobin5_request;
-wire litedramcore_roundrobin5_grant;
-wire litedramcore_roundrobin5_ce;
-wire litedramcore_roundrobin6_request;
-wire litedramcore_roundrobin6_grant;
-wire litedramcore_roundrobin6_ce;
-wire litedramcore_roundrobin7_request;
-wire litedramcore_roundrobin7_grant;
-wire litedramcore_roundrobin7_ce;
-reg litedramcore_locked0 = 1'd0;
-reg litedramcore_locked1 = 1'd0;
-reg litedramcore_locked2 = 1'd0;
-reg litedramcore_locked3 = 1'd0;
-reg litedramcore_locked4 = 1'd0;
-reg litedramcore_locked5 = 1'd0;
-reg litedramcore_locked6 = 1'd0;
-reg litedramcore_locked7 = 1'd0;
-reg litedramcore_new_master_wdata_ready0 = 1'd0;
-reg litedramcore_new_master_wdata_ready1 = 1'd0;
-reg litedramcore_new_master_rdata_valid0 = 1'd0;
-reg litedramcore_new_master_rdata_valid1 = 1'd0;
-reg litedramcore_new_master_rdata_valid2 = 1'd0;
-reg litedramcore_new_master_rdata_valid3 = 1'd0;
-reg litedramcore_new_master_rdata_valid4 = 1'd0;
-reg litedramcore_new_master_rdata_valid5 = 1'd0;
-reg litedramcore_new_master_rdata_valid6 = 1'd0;
-reg litedramcore_new_master_rdata_valid7 = 1'd0;
-reg litedramcore_new_master_rdata_valid8 = 1'd0;
-reg [1:0] litedramcore_state = 2'd0;
-reg [1:0] litedramcore_next_state = 2'd0;
-reg [31:0] litedramcore_dat_w_next_value0 = 32'd0;
-reg litedramcore_dat_w_next_value_ce0 = 1'd0;
-reg [13:0] litedramcore_adr_next_value1 = 14'd0;
-reg litedramcore_adr_next_value_ce1 = 1'd0;
-reg litedramcore_we_next_value2 = 1'd0;
-reg litedramcore_we_next_value_ce2 = 1'd0;
-reg rhs_array_muxed0 = 1'd0;
-reg [13:0] rhs_array_muxed1 = 14'd0;
-reg [2:0] rhs_array_muxed2 = 3'd0;
-reg rhs_array_muxed3 = 1'd0;
-reg rhs_array_muxed4 = 1'd0;
-reg rhs_array_muxed5 = 1'd0;
-reg t_array_muxed0 = 1'd0;
-reg t_array_muxed1 = 1'd0;
-reg t_array_muxed2 = 1'd0;
-reg rhs_array_muxed6 = 1'd0;
-reg [13:0] rhs_array_muxed7 = 14'd0;
-reg [2:0] rhs_array_muxed8 = 3'd0;
-reg rhs_array_muxed9 = 1'd0;
-reg rhs_array_muxed10 = 1'd0;
-reg rhs_array_muxed11 = 1'd0;
-reg t_array_muxed3 = 1'd0;
-reg t_array_muxed4 = 1'd0;
-reg t_array_muxed5 = 1'd0;
-reg [20:0] rhs_array_muxed12 = 21'd0;
-reg rhs_array_muxed13 = 1'd0;
-reg rhs_array_muxed14 = 1'd0;
-reg [20:0] rhs_array_muxed15 = 21'd0;
-reg rhs_array_muxed16 = 1'd0;
-reg rhs_array_muxed17 = 1'd0;
-reg [20:0] rhs_array_muxed18 = 21'd0;
-reg rhs_array_muxed19 = 1'd0;
-reg rhs_array_muxed20 = 1'd0;
-reg [20:0] rhs_array_muxed21 = 21'd0;
-reg rhs_array_muxed22 = 1'd0;
-reg rhs_array_muxed23 = 1'd0;
-reg [20:0] rhs_array_muxed24 = 21'd0;
-reg rhs_array_muxed25 = 1'd0;
-reg rhs_array_muxed26 = 1'd0;
-reg [20:0] rhs_array_muxed27 = 21'd0;
-reg rhs_array_muxed28 = 1'd0;
-reg rhs_array_muxed29 = 1'd0;
-reg [20:0] rhs_array_muxed30 = 21'd0;
-reg rhs_array_muxed31 = 1'd0;
-reg rhs_array_muxed32 = 1'd0;
-reg [20:0] rhs_array_muxed33 = 21'd0;
-reg rhs_array_muxed34 = 1'd0;
-reg rhs_array_muxed35 = 1'd0;
-reg [2:0] array_muxed0 = 3'd0;
-reg [13:0] array_muxed1 = 14'd0;
-reg array_muxed2 = 1'd0;
-reg array_muxed3 = 1'd0;
-reg array_muxed4 = 1'd0;
-reg array_muxed5 = 1'd0;
-reg array_muxed6 = 1'd0;
-reg [2:0] array_muxed7 = 3'd0;
-reg [13:0] array_muxed8 = 14'd0;
-reg array_muxed9 = 1'd0;
-reg array_muxed10 = 1'd0;
-reg array_muxed11 = 1'd0;
-reg array_muxed12 = 1'd0;
-reg array_muxed13 = 1'd0;
-reg [2:0] array_muxed14 = 3'd0;
-reg [13:0] array_muxed15 = 14'd0;
-reg array_muxed16 = 1'd0;
-reg array_muxed17 = 1'd0;
-reg array_muxed18 = 1'd0;
-reg array_muxed19 = 1'd0;
-reg array_muxed20 = 1'd0;
-reg [2:0] array_muxed21 = 3'd0;
-reg [13:0] array_muxed22 = 14'd0;
-reg array_muxed23 = 1'd0;
-reg array_muxed24 = 1'd0;
-reg array_muxed25 = 1'd0;
-reg array_muxed26 = 1'd0;
-reg array_muxed27 = 1'd0;
-wire xilinxasyncresetsynchronizerimpl0;
-wire xilinxasyncresetsynchronizerimpl0_rst_meta;
-wire xilinxasyncresetsynchronizerimpl1;
-wire xilinxasyncresetsynchronizerimpl1_rst_meta;
-wire xilinxasyncresetsynchronizerimpl2;
-wire xilinxasyncresetsynchronizerimpl2_rst_meta;
-wire xilinxasyncresetsynchronizerimpl2_expr;
-wire xilinxasyncresetsynchronizerimpl3;
-wire xilinxasyncresetsynchronizerimpl3_rst_meta;
-wire xilinxasyncresetsynchronizerimpl3_expr;
+reg rst_1 = 1'd0;
+wire sys_clk;
+wire sys_rst;
+wire sys4x_clk;
+wire sys4x_dqs_clk;
+wire iodelay_clk;
+wire iodelay_rst;
+wire reset;
+reg power_down = 1'd0;
+wire locked;
+wire clkin;
+wire clkout0;
+wire clkout_buf0;
+wire clkout1;
+wire clkout_buf1;
+wire clkout2;
+wire clkout_buf2;
+wire clkout3;
+wire clkout_buf3;
+reg [3:0] reset_counter = 4'd15;
+reg ic_reset = 1'd1;
+reg a7ddrphy_rst_storage = 1'd0;
+reg a7ddrphy_rst_re = 1'd0;
+reg [1:0] a7ddrphy_dly_sel_storage = 2'd0;
+reg a7ddrphy_dly_sel_re = 1'd0;
+reg [4:0] a7ddrphy_half_sys8x_taps_storage = 5'd8;
+reg a7ddrphy_half_sys8x_taps_re = 1'd0;
+reg a7ddrphy_wlevel_en_storage = 1'd0;
+reg a7ddrphy_wlevel_en_re = 1'd0;
+reg a7ddrphy_wlevel_strobe_re = 1'd0;
+wire a7ddrphy_wlevel_strobe_r;
+reg a7ddrphy_wlevel_strobe_we = 1'd0;
+reg a7ddrphy_wlevel_strobe_w = 1'd0;
+reg a7ddrphy_rdly_dq_rst_re = 1'd0;
+wire a7ddrphy_rdly_dq_rst_r;
+reg a7ddrphy_rdly_dq_rst_we = 1'd0;
+reg a7ddrphy_rdly_dq_rst_w = 1'd0;
+reg a7ddrphy_rdly_dq_inc_re = 1'd0;
+wire a7ddrphy_rdly_dq_inc_r;
+reg a7ddrphy_rdly_dq_inc_we = 1'd0;
+reg a7ddrphy_rdly_dq_inc_w = 1'd0;
+reg a7ddrphy_rdly_dq_bitslip_rst_re = 1'd0;
+wire a7ddrphy_rdly_dq_bitslip_rst_r;
+reg a7ddrphy_rdly_dq_bitslip_rst_we = 1'd0;
+reg a7ddrphy_rdly_dq_bitslip_rst_w = 1'd0;
+reg a7ddrphy_rdly_dq_bitslip_re = 1'd0;
+wire a7ddrphy_rdly_dq_bitslip_r;
+reg a7ddrphy_rdly_dq_bitslip_we = 1'd0;
+reg a7ddrphy_rdly_dq_bitslip_w = 1'd0;
+reg a7ddrphy_wdly_dq_bitslip_rst_re = 1'd0;
+wire a7ddrphy_wdly_dq_bitslip_rst_r;
+reg a7ddrphy_wdly_dq_bitslip_rst_we = 1'd0;
+reg a7ddrphy_wdly_dq_bitslip_rst_w = 1'd0;
+reg a7ddrphy_wdly_dq_bitslip_re = 1'd0;
+wire a7ddrphy_wdly_dq_bitslip_r;
+reg a7ddrphy_wdly_dq_bitslip_we = 1'd0;
+reg a7ddrphy_wdly_dq_bitslip_w = 1'd0;
+reg [1:0] a7ddrphy_rdphase_storage = 2'd2;
+reg a7ddrphy_rdphase_re = 1'd0;
+reg [1:0] a7ddrphy_wrphase_storage = 2'd3;
+reg a7ddrphy_wrphase_re = 1'd0;
+wire [13:0] a7ddrphy_dfi_p0_address;
+wire [2:0] a7ddrphy_dfi_p0_bank;
+wire a7ddrphy_dfi_p0_cas_n;
+wire a7ddrphy_dfi_p0_cs_n;
+wire a7ddrphy_dfi_p0_ras_n;
+wire a7ddrphy_dfi_p0_we_n;
+wire a7ddrphy_dfi_p0_cke;
+wire a7ddrphy_dfi_p0_odt;
+wire a7ddrphy_dfi_p0_reset_n;
+wire a7ddrphy_dfi_p0_act_n;
+wire [31:0] a7ddrphy_dfi_p0_wrdata;
+wire a7ddrphy_dfi_p0_wrdata_en;
+wire [3:0] a7ddrphy_dfi_p0_wrdata_mask;
+wire a7ddrphy_dfi_p0_rddata_en;
+reg [31:0] a7ddrphy_dfi_p0_rddata = 32'd0;
+wire a7ddrphy_dfi_p0_rddata_valid;
+wire [13:0] a7ddrphy_dfi_p1_address;
+wire [2:0] a7ddrphy_dfi_p1_bank;
+wire a7ddrphy_dfi_p1_cas_n;
+wire a7ddrphy_dfi_p1_cs_n;
+wire a7ddrphy_dfi_p1_ras_n;
+wire a7ddrphy_dfi_p1_we_n;
+wire a7ddrphy_dfi_p1_cke;
+wire a7ddrphy_dfi_p1_odt;
+wire a7ddrphy_dfi_p1_reset_n;
+wire a7ddrphy_dfi_p1_act_n;
+wire [31:0] a7ddrphy_dfi_p1_wrdata;
+wire a7ddrphy_dfi_p1_wrdata_en;
+wire [3:0] a7ddrphy_dfi_p1_wrdata_mask;
+wire a7ddrphy_dfi_p1_rddata_en;
+reg [31:0] a7ddrphy_dfi_p1_rddata = 32'd0;
+wire a7ddrphy_dfi_p1_rddata_valid;
+wire [13:0] a7ddrphy_dfi_p2_address;
+wire [2:0] a7ddrphy_dfi_p2_bank;
+wire a7ddrphy_dfi_p2_cas_n;
+wire a7ddrphy_dfi_p2_cs_n;
+wire a7ddrphy_dfi_p2_ras_n;
+wire a7ddrphy_dfi_p2_we_n;
+wire a7ddrphy_dfi_p2_cke;
+wire a7ddrphy_dfi_p2_odt;
+wire a7ddrphy_dfi_p2_reset_n;
+wire a7ddrphy_dfi_p2_act_n;
+wire [31:0] a7ddrphy_dfi_p2_wrdata;
+wire a7ddrphy_dfi_p2_wrdata_en;
+wire [3:0] a7ddrphy_dfi_p2_wrdata_mask;
+wire a7ddrphy_dfi_p2_rddata_en;
+reg [31:0] a7ddrphy_dfi_p2_rddata = 32'd0;
+wire a7ddrphy_dfi_p2_rddata_valid;
+wire [13:0] a7ddrphy_dfi_p3_address;
+wire [2:0] a7ddrphy_dfi_p3_bank;
+wire a7ddrphy_dfi_p3_cas_n;
+wire a7ddrphy_dfi_p3_cs_n;
+wire a7ddrphy_dfi_p3_ras_n;
+wire a7ddrphy_dfi_p3_we_n;
+wire a7ddrphy_dfi_p3_cke;
+wire a7ddrphy_dfi_p3_odt;
+wire a7ddrphy_dfi_p3_reset_n;
+wire a7ddrphy_dfi_p3_act_n;
+wire [31:0] a7ddrphy_dfi_p3_wrdata;
+wire a7ddrphy_dfi_p3_wrdata_en;
+wire [3:0] a7ddrphy_dfi_p3_wrdata_mask;
+wire a7ddrphy_dfi_p3_rddata_en;
+reg [31:0] a7ddrphy_dfi_p3_rddata = 32'd0;
+wire a7ddrphy_dfi_p3_rddata_valid;
+wire a7ddrphy_sd_clk_se_nodelay;
+wire [2:0] a7ddrphy_pads_ba;
+reg a7ddrphy_dqs_oe = 1'd0;
+wire a7ddrphy_dqs_preamble;
+wire a7ddrphy_dqs_postamble;
+wire a7ddrphy_dqs_oe_delay_tappeddelayline;
+reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
+reg a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
+reg a7ddrphy_dqspattern0 = 1'd0;
+reg a7ddrphy_dqspattern1 = 1'd0;
+reg [7:0] a7ddrphy_dqspattern_o0 = 8'd0;
+reg [7:0] a7ddrphy_dqspattern_o1 = 8'd0;
+wire a7ddrphy_dqs_o_no_delay0;
+wire a7ddrphy_dqs_t0;
+reg [7:0] a7ddrphy_bitslip00 = 8'd0;
+reg [2:0] a7ddrphy_bitslip0_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip0_r0 = 16'd0;
+wire a7ddrphy0;
+wire a7ddrphy_dqs_o_no_delay1;
+wire a7ddrphy_dqs_t1;
+reg [7:0] a7ddrphy_bitslip10 = 8'd0;
+reg [2:0] a7ddrphy_bitslip1_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip1_r0 = 16'd0;
+wire a7ddrphy1;
+reg [7:0] a7ddrphy_bitslip01 = 8'd0;
+reg [2:0] a7ddrphy_bitslip0_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip0_r1 = 16'd0;
+reg [7:0] a7ddrphy_bitslip11 = 8'd0;
+reg [2:0] a7ddrphy_bitslip1_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip1_r1 = 16'd0;
+wire a7ddrphy_dq_oe;
+wire a7ddrphy_dq_oe_delay_tappeddelayline;
+reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 = 1'd0;
+reg a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 = 1'd0;
+wire a7ddrphy_dq_o_nodelay0;
+wire a7ddrphy_dq_i_nodelay0;
+wire a7ddrphy_dq_i_delayed0;
+wire a7ddrphy_dq_t0;
+reg [7:0] a7ddrphy_bitslip02 = 8'd0;
+reg [2:0] a7ddrphy_bitslip0_value2 = 3'd7;
+reg [15:0] a7ddrphy_bitslip0_r2 = 16'd0;
+wire [7:0] a7ddrphy_bitslip03;
+reg [7:0] a7ddrphy_bitslip04 = 8'd0;
+reg [2:0] a7ddrphy_bitslip0_value3 = 3'd7;
+reg [15:0] a7ddrphy_bitslip0_r3 = 16'd0;
+wire a7ddrphy_dq_o_nodelay1;
+wire a7ddrphy_dq_i_nodelay1;
+wire a7ddrphy_dq_i_delayed1;
+wire a7ddrphy_dq_t1;
+reg [7:0] a7ddrphy_bitslip12 = 8'd0;
+reg [2:0] a7ddrphy_bitslip1_value2 = 3'd7;
+reg [15:0] a7ddrphy_bitslip1_r2 = 16'd0;
+wire [7:0] a7ddrphy_bitslip13;
+reg [7:0] a7ddrphy_bitslip14 = 8'd0;
+reg [2:0] a7ddrphy_bitslip1_value3 = 3'd7;
+reg [15:0] a7ddrphy_bitslip1_r3 = 16'd0;
+wire a7ddrphy_dq_o_nodelay2;
+wire a7ddrphy_dq_i_nodelay2;
+wire a7ddrphy_dq_i_delayed2;
+wire a7ddrphy_dq_t2;
+reg [7:0] a7ddrphy_bitslip20 = 8'd0;
+reg [2:0] a7ddrphy_bitslip2_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip2_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip21;
+reg [7:0] a7ddrphy_bitslip22 = 8'd0;
+reg [2:0] a7ddrphy_bitslip2_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip2_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay3;
+wire a7ddrphy_dq_i_nodelay3;
+wire a7ddrphy_dq_i_delayed3;
+wire a7ddrphy_dq_t3;
+reg [7:0] a7ddrphy_bitslip30 = 8'd0;
+reg [2:0] a7ddrphy_bitslip3_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip3_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip31;
+reg [7:0] a7ddrphy_bitslip32 = 8'd0;
+reg [2:0] a7ddrphy_bitslip3_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip3_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay4;
+wire a7ddrphy_dq_i_nodelay4;
+wire a7ddrphy_dq_i_delayed4;
+wire a7ddrphy_dq_t4;
+reg [7:0] a7ddrphy_bitslip40 = 8'd0;
+reg [2:0] a7ddrphy_bitslip4_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip4_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip41;
+reg [7:0] a7ddrphy_bitslip42 = 8'd0;
+reg [2:0] a7ddrphy_bitslip4_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip4_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay5;
+wire a7ddrphy_dq_i_nodelay5;
+wire a7ddrphy_dq_i_delayed5;
+wire a7ddrphy_dq_t5;
+reg [7:0] a7ddrphy_bitslip50 = 8'd0;
+reg [2:0] a7ddrphy_bitslip5_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip5_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip51;
+reg [7:0] a7ddrphy_bitslip52 = 8'd0;
+reg [2:0] a7ddrphy_bitslip5_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip5_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay6;
+wire a7ddrphy_dq_i_nodelay6;
+wire a7ddrphy_dq_i_delayed6;
+wire a7ddrphy_dq_t6;
+reg [7:0] a7ddrphy_bitslip60 = 8'd0;
+reg [2:0] a7ddrphy_bitslip6_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip6_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip61;
+reg [7:0] a7ddrphy_bitslip62 = 8'd0;
+reg [2:0] a7ddrphy_bitslip6_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip6_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay7;
+wire a7ddrphy_dq_i_nodelay7;
+wire a7ddrphy_dq_i_delayed7;
+wire a7ddrphy_dq_t7;
+reg [7:0] a7ddrphy_bitslip70 = 8'd0;
+reg [2:0] a7ddrphy_bitslip7_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip7_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip71;
+reg [7:0] a7ddrphy_bitslip72 = 8'd0;
+reg [2:0] a7ddrphy_bitslip7_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip7_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay8;
+wire a7ddrphy_dq_i_nodelay8;
+wire a7ddrphy_dq_i_delayed8;
+wire a7ddrphy_dq_t8;
+reg [7:0] a7ddrphy_bitslip80 = 8'd0;
+reg [2:0] a7ddrphy_bitslip8_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip8_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip81;
+reg [7:0] a7ddrphy_bitslip82 = 8'd0;
+reg [2:0] a7ddrphy_bitslip8_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip8_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay9;
+wire a7ddrphy_dq_i_nodelay9;
+wire a7ddrphy_dq_i_delayed9;
+wire a7ddrphy_dq_t9;
+reg [7:0] a7ddrphy_bitslip90 = 8'd0;
+reg [2:0] a7ddrphy_bitslip9_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip9_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip91;
+reg [7:0] a7ddrphy_bitslip92 = 8'd0;
+reg [2:0] a7ddrphy_bitslip9_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip9_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay10;
+wire a7ddrphy_dq_i_nodelay10;
+wire a7ddrphy_dq_i_delayed10;
+wire a7ddrphy_dq_t10;
+reg [7:0] a7ddrphy_bitslip100 = 8'd0;
+reg [2:0] a7ddrphy_bitslip10_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip10_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip101;
+reg [7:0] a7ddrphy_bitslip102 = 8'd0;
+reg [2:0] a7ddrphy_bitslip10_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip10_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay11;
+wire a7ddrphy_dq_i_nodelay11;
+wire a7ddrphy_dq_i_delayed11;
+wire a7ddrphy_dq_t11;
+reg [7:0] a7ddrphy_bitslip110 = 8'd0;
+reg [2:0] a7ddrphy_bitslip11_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip11_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip111;
+reg [7:0] a7ddrphy_bitslip112 = 8'd0;
+reg [2:0] a7ddrphy_bitslip11_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip11_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay12;
+wire a7ddrphy_dq_i_nodelay12;
+wire a7ddrphy_dq_i_delayed12;
+wire a7ddrphy_dq_t12;
+reg [7:0] a7ddrphy_bitslip120 = 8'd0;
+reg [2:0] a7ddrphy_bitslip12_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip12_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip121;
+reg [7:0] a7ddrphy_bitslip122 = 8'd0;
+reg [2:0] a7ddrphy_bitslip12_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip12_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay13;
+wire a7ddrphy_dq_i_nodelay13;
+wire a7ddrphy_dq_i_delayed13;
+wire a7ddrphy_dq_t13;
+reg [7:0] a7ddrphy_bitslip130 = 8'd0;
+reg [2:0] a7ddrphy_bitslip13_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip13_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip131;
+reg [7:0] a7ddrphy_bitslip132 = 8'd0;
+reg [2:0] a7ddrphy_bitslip13_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip13_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay14;
+wire a7ddrphy_dq_i_nodelay14;
+wire a7ddrphy_dq_i_delayed14;
+wire a7ddrphy_dq_t14;
+reg [7:0] a7ddrphy_bitslip140 = 8'd0;
+reg [2:0] a7ddrphy_bitslip14_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip14_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip141;
+reg [7:0] a7ddrphy_bitslip142 = 8'd0;
+reg [2:0] a7ddrphy_bitslip14_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip14_r1 = 16'd0;
+wire a7ddrphy_dq_o_nodelay15;
+wire a7ddrphy_dq_i_nodelay15;
+wire a7ddrphy_dq_i_delayed15;
+wire a7ddrphy_dq_t15;
+reg [7:0] a7ddrphy_bitslip150 = 8'd0;
+reg [2:0] a7ddrphy_bitslip15_value0 = 3'd7;
+reg [15:0] a7ddrphy_bitslip15_r0 = 16'd0;
+wire [7:0] a7ddrphy_bitslip151;
+reg [7:0] a7ddrphy_bitslip152 = 8'd0;
+reg [2:0] a7ddrphy_bitslip15_value1 = 3'd7;
+reg [15:0] a7ddrphy_bitslip15_r1 = 16'd0;
+reg a7ddrphy_rddata_en_tappeddelayline0 = 1'd0;
+reg a7ddrphy_rddata_en_tappeddelayline1 = 1'd0;
+reg a7ddrphy_rddata_en_tappeddelayline2 = 1'd0;
+reg a7ddrphy_rddata_en_tappeddelayline3 = 1'd0;
+reg a7ddrphy_rddata_en_tappeddelayline4 = 1'd0;
+reg a7ddrphy_rddata_en_tappeddelayline5 = 1'd0;
+reg a7ddrphy_rddata_en_tappeddelayline6 = 1'd0;
+reg a7ddrphy_rddata_en_tappeddelayline7 = 1'd0;
+reg a7ddrphy_wrdata_en_tappeddelayline0 = 1'd0;
+reg a7ddrphy_wrdata_en_tappeddelayline1 = 1'd0;
+reg a7ddrphy_wrdata_en_tappeddelayline2 = 1'd0;
+wire [13:0] litedramcore_slave_p0_address;
+wire [2:0] litedramcore_slave_p0_bank;
+wire litedramcore_slave_p0_cas_n;
+wire litedramcore_slave_p0_cs_n;
+wire litedramcore_slave_p0_ras_n;
+wire litedramcore_slave_p0_we_n;
+wire litedramcore_slave_p0_cke;
+wire litedramcore_slave_p0_odt;
+wire litedramcore_slave_p0_reset_n;
+wire litedramcore_slave_p0_act_n;
+wire [31:0] litedramcore_slave_p0_wrdata;
+wire litedramcore_slave_p0_wrdata_en;
+wire [3:0] litedramcore_slave_p0_wrdata_mask;
+wire litedramcore_slave_p0_rddata_en;
+reg [31:0] litedramcore_slave_p0_rddata = 32'd0;
+reg litedramcore_slave_p0_rddata_valid = 1'd0;
+wire [13:0] litedramcore_slave_p1_address;
+wire [2:0] litedramcore_slave_p1_bank;
+wire litedramcore_slave_p1_cas_n;
+wire litedramcore_slave_p1_cs_n;
+wire litedramcore_slave_p1_ras_n;
+wire litedramcore_slave_p1_we_n;
+wire litedramcore_slave_p1_cke;
+wire litedramcore_slave_p1_odt;
+wire litedramcore_slave_p1_reset_n;
+wire litedramcore_slave_p1_act_n;
+wire [31:0] litedramcore_slave_p1_wrdata;
+wire litedramcore_slave_p1_wrdata_en;
+wire [3:0] litedramcore_slave_p1_wrdata_mask;
+wire litedramcore_slave_p1_rddata_en;
+reg [31:0] litedramcore_slave_p1_rddata = 32'd0;
+reg litedramcore_slave_p1_rddata_valid = 1'd0;
+wire [13:0] litedramcore_slave_p2_address;
+wire [2:0] litedramcore_slave_p2_bank;
+wire litedramcore_slave_p2_cas_n;
+wire litedramcore_slave_p2_cs_n;
+wire litedramcore_slave_p2_ras_n;
+wire litedramcore_slave_p2_we_n;
+wire litedramcore_slave_p2_cke;
+wire litedramcore_slave_p2_odt;
+wire litedramcore_slave_p2_reset_n;
+wire litedramcore_slave_p2_act_n;
+wire [31:0] litedramcore_slave_p2_wrdata;
+wire litedramcore_slave_p2_wrdata_en;
+wire [3:0] litedramcore_slave_p2_wrdata_mask;
+wire litedramcore_slave_p2_rddata_en;
+reg [31:0] litedramcore_slave_p2_rddata = 32'd0;
+reg litedramcore_slave_p2_rddata_valid = 1'd0;
+wire [13:0] litedramcore_slave_p3_address;
+wire [2:0] litedramcore_slave_p3_bank;
+wire litedramcore_slave_p3_cas_n;
+wire litedramcore_slave_p3_cs_n;
+wire litedramcore_slave_p3_ras_n;
+wire litedramcore_slave_p3_we_n;
+wire litedramcore_slave_p3_cke;
+wire litedramcore_slave_p3_odt;
+wire litedramcore_slave_p3_reset_n;
+wire litedramcore_slave_p3_act_n;
+wire [31:0] litedramcore_slave_p3_wrdata;
+wire litedramcore_slave_p3_wrdata_en;
+wire [3:0] litedramcore_slave_p3_wrdata_mask;
+wire litedramcore_slave_p3_rddata_en;
+reg [31:0] litedramcore_slave_p3_rddata = 32'd0;
+reg litedramcore_slave_p3_rddata_valid = 1'd0;
+reg [13:0] litedramcore_master_p0_address = 14'd0;
+reg [2:0] litedramcore_master_p0_bank = 3'd0;
+reg litedramcore_master_p0_cas_n = 1'd1;
+reg litedramcore_master_p0_cs_n = 1'd1;
+reg litedramcore_master_p0_ras_n = 1'd1;
+reg litedramcore_master_p0_we_n = 1'd1;
+reg litedramcore_master_p0_cke = 1'd0;
+reg litedramcore_master_p0_odt = 1'd0;
+reg litedramcore_master_p0_reset_n = 1'd0;
+reg litedramcore_master_p0_act_n = 1'd1;
+reg [31:0] litedramcore_master_p0_wrdata = 32'd0;
+reg litedramcore_master_p0_wrdata_en = 1'd0;
+reg [3:0] litedramcore_master_p0_wrdata_mask = 4'd0;
+reg litedramcore_master_p0_rddata_en = 1'd0;
+wire [31:0] litedramcore_master_p0_rddata;
+wire litedramcore_master_p0_rddata_valid;
+reg [13:0] litedramcore_master_p1_address = 14'd0;
+reg [2:0] litedramcore_master_p1_bank = 3'd0;
+reg litedramcore_master_p1_cas_n = 1'd1;
+reg litedramcore_master_p1_cs_n = 1'd1;
+reg litedramcore_master_p1_ras_n = 1'd1;
+reg litedramcore_master_p1_we_n = 1'd1;
+reg litedramcore_master_p1_cke = 1'd0;
+reg litedramcore_master_p1_odt = 1'd0;
+reg litedramcore_master_p1_reset_n = 1'd0;
+reg litedramcore_master_p1_act_n = 1'd1;
+reg [31:0] litedramcore_master_p1_wrdata = 32'd0;
+reg litedramcore_master_p1_wrdata_en = 1'd0;
+reg [3:0] litedramcore_master_p1_wrdata_mask = 4'd0;
+reg litedramcore_master_p1_rddata_en = 1'd0;
+wire [31:0] litedramcore_master_p1_rddata;
+wire litedramcore_master_p1_rddata_valid;
+reg [13:0] litedramcore_master_p2_address = 14'd0;
+reg [2:0] litedramcore_master_p2_bank = 3'd0;
+reg litedramcore_master_p2_cas_n = 1'd1;
+reg litedramcore_master_p2_cs_n = 1'd1;
+reg litedramcore_master_p2_ras_n = 1'd1;
+reg litedramcore_master_p2_we_n = 1'd1;
+reg litedramcore_master_p2_cke = 1'd0;
+reg litedramcore_master_p2_odt = 1'd0;
+reg litedramcore_master_p2_reset_n = 1'd0;
+reg litedramcore_master_p2_act_n = 1'd1;
+reg [31:0] litedramcore_master_p2_wrdata = 32'd0;
+reg litedramcore_master_p2_wrdata_en = 1'd0;
+reg [3:0] litedramcore_master_p2_wrdata_mask = 4'd0;
+reg litedramcore_master_p2_rddata_en = 1'd0;
+wire [31:0] litedramcore_master_p2_rddata;
+wire litedramcore_master_p2_rddata_valid;
+reg [13:0] litedramcore_master_p3_address = 14'd0;
+reg [2:0] litedramcore_master_p3_bank = 3'd0;
+reg litedramcore_master_p3_cas_n = 1'd1;
+reg litedramcore_master_p3_cs_n = 1'd1;
+reg litedramcore_master_p3_ras_n = 1'd1;
+reg litedramcore_master_p3_we_n = 1'd1;
+reg litedramcore_master_p3_cke = 1'd0;
+reg litedramcore_master_p3_odt = 1'd0;
+reg litedramcore_master_p3_reset_n = 1'd0;
+reg litedramcore_master_p3_act_n = 1'd1;
+reg [31:0] litedramcore_master_p3_wrdata = 32'd0;
+reg litedramcore_master_p3_wrdata_en = 1'd0;
+reg [3:0] litedramcore_master_p3_wrdata_mask = 4'd0;
+reg litedramcore_master_p3_rddata_en = 1'd0;
+wire [31:0] litedramcore_master_p3_rddata;
+wire litedramcore_master_p3_rddata_valid;
+wire [13:0] litedramcore_csr_dfi_p0_address;
+wire [2:0] litedramcore_csr_dfi_p0_bank;
+reg litedramcore_csr_dfi_p0_cas_n = 1'd1;
+reg litedramcore_csr_dfi_p0_cs_n = 1'd1;
+reg litedramcore_csr_dfi_p0_ras_n = 1'd1;
+reg litedramcore_csr_dfi_p0_we_n = 1'd1;
+wire litedramcore_csr_dfi_p0_cke;
+wire litedramcore_csr_dfi_p0_odt;
+wire litedramcore_csr_dfi_p0_reset_n;
+reg litedramcore_csr_dfi_p0_act_n = 1'd1;
+wire [31:0] litedramcore_csr_dfi_p0_wrdata;
+wire litedramcore_csr_dfi_p0_wrdata_en;
+wire [3:0] litedramcore_csr_dfi_p0_wrdata_mask;
+wire litedramcore_csr_dfi_p0_rddata_en;
+reg [31:0] litedramcore_csr_dfi_p0_rddata = 32'd0;
+reg litedramcore_csr_dfi_p0_rddata_valid = 1'd0;
+wire [13:0] litedramcore_csr_dfi_p1_address;
+wire [2:0] litedramcore_csr_dfi_p1_bank;
+reg litedramcore_csr_dfi_p1_cas_n = 1'd1;
+reg litedramcore_csr_dfi_p1_cs_n = 1'd1;
+reg litedramcore_csr_dfi_p1_ras_n = 1'd1;
+reg litedramcore_csr_dfi_p1_we_n = 1'd1;
+wire litedramcore_csr_dfi_p1_cke;
+wire litedramcore_csr_dfi_p1_odt;
+wire litedramcore_csr_dfi_p1_reset_n;
+reg litedramcore_csr_dfi_p1_act_n = 1'd1;
+wire [31:0] litedramcore_csr_dfi_p1_wrdata;
+wire litedramcore_csr_dfi_p1_wrdata_en;
+wire [3:0] litedramcore_csr_dfi_p1_wrdata_mask;
+wire litedramcore_csr_dfi_p1_rddata_en;
+reg [31:0] litedramcore_csr_dfi_p1_rddata = 32'd0;
+reg litedramcore_csr_dfi_p1_rddata_valid = 1'd0;
+wire [13:0] litedramcore_csr_dfi_p2_address;
+wire [2:0] litedramcore_csr_dfi_p2_bank;
+reg litedramcore_csr_dfi_p2_cas_n = 1'd1;
+reg litedramcore_csr_dfi_p2_cs_n = 1'd1;
+reg litedramcore_csr_dfi_p2_ras_n = 1'd1;
+reg litedramcore_csr_dfi_p2_we_n = 1'd1;
+wire litedramcore_csr_dfi_p2_cke;
+wire litedramcore_csr_dfi_p2_odt;
+wire litedramcore_csr_dfi_p2_reset_n;
+reg litedramcore_csr_dfi_p2_act_n = 1'd1;
+wire [31:0] litedramcore_csr_dfi_p2_wrdata;
+wire litedramcore_csr_dfi_p2_wrdata_en;
+wire [3:0] litedramcore_csr_dfi_p2_wrdata_mask;
+wire litedramcore_csr_dfi_p2_rddata_en;
+reg [31:0] litedramcore_csr_dfi_p2_rddata = 32'd0;
+reg litedramcore_csr_dfi_p2_rddata_valid = 1'd0;
+wire [13:0] litedramcore_csr_dfi_p3_address;
+wire [2:0] litedramcore_csr_dfi_p3_bank;
+reg litedramcore_csr_dfi_p3_cas_n = 1'd1;
+reg litedramcore_csr_dfi_p3_cs_n = 1'd1;
+reg litedramcore_csr_dfi_p3_ras_n = 1'd1;
+reg litedramcore_csr_dfi_p3_we_n = 1'd1;
+wire litedramcore_csr_dfi_p3_cke;
+wire litedramcore_csr_dfi_p3_odt;
+wire litedramcore_csr_dfi_p3_reset_n;
+reg litedramcore_csr_dfi_p3_act_n = 1'd1;
+wire [31:0] litedramcore_csr_dfi_p3_wrdata;
+wire litedramcore_csr_dfi_p3_wrdata_en;
+wire [3:0] litedramcore_csr_dfi_p3_wrdata_mask;
+wire litedramcore_csr_dfi_p3_rddata_en;
+reg [31:0] litedramcore_csr_dfi_p3_rddata = 32'd0;
+reg litedramcore_csr_dfi_p3_rddata_valid = 1'd0;
+reg [13:0] litedramcore_ext_dfi_p0_address = 14'd0;
+reg [2:0] litedramcore_ext_dfi_p0_bank = 3'd0;
+reg litedramcore_ext_dfi_p0_cas_n = 1'd1;
+reg litedramcore_ext_dfi_p0_cs_n = 1'd1;
+reg litedramcore_ext_dfi_p0_ras_n = 1'd1;
+reg litedramcore_ext_dfi_p0_we_n = 1'd1;
+reg litedramcore_ext_dfi_p0_cke = 1'd0;
+reg litedramcore_ext_dfi_p0_odt = 1'd0;
+reg litedramcore_ext_dfi_p0_reset_n = 1'd0;
+reg litedramcore_ext_dfi_p0_act_n = 1'd1;
+reg [31:0] litedramcore_ext_dfi_p0_wrdata = 32'd0;
+reg litedramcore_ext_dfi_p0_wrdata_en = 1'd0;
+reg [3:0] litedramcore_ext_dfi_p0_wrdata_mask = 4'd0;
+reg litedramcore_ext_dfi_p0_rddata_en = 1'd0;
+reg [31:0] litedramcore_ext_dfi_p0_rddata = 32'd0;
+reg litedramcore_ext_dfi_p0_rddata_valid = 1'd0;
+reg [13:0] litedramcore_ext_dfi_p1_address = 14'd0;
+reg [2:0] litedramcore_ext_dfi_p1_bank = 3'd0;
+reg litedramcore_ext_dfi_p1_cas_n = 1'd1;
+reg litedramcore_ext_dfi_p1_cs_n = 1'd1;
+reg litedramcore_ext_dfi_p1_ras_n = 1'd1;
+reg litedramcore_ext_dfi_p1_we_n = 1'd1;
+reg litedramcore_ext_dfi_p1_cke = 1'd0;
+reg litedramcore_ext_dfi_p1_odt = 1'd0;
+reg litedramcore_ext_dfi_p1_reset_n = 1'd0;
+reg litedramcore_ext_dfi_p1_act_n = 1'd1;
+reg [31:0] litedramcore_ext_dfi_p1_wrdata = 32'd0;
+reg litedramcore_ext_dfi_p1_wrdata_en = 1'd0;
+reg [3:0] litedramcore_ext_dfi_p1_wrdata_mask = 4'd0;
+reg litedramcore_ext_dfi_p1_rddata_en = 1'd0;
+reg [31:0] litedramcore_ext_dfi_p1_rddata = 32'd0;
+reg litedramcore_ext_dfi_p1_rddata_valid = 1'd0;
+reg [13:0] litedramcore_ext_dfi_p2_address = 14'd0;
+reg [2:0] litedramcore_ext_dfi_p2_bank = 3'd0;
+reg litedramcore_ext_dfi_p2_cas_n = 1'd1;
+reg litedramcore_ext_dfi_p2_cs_n = 1'd1;
+reg litedramcore_ext_dfi_p2_ras_n = 1'd1;
+reg litedramcore_ext_dfi_p2_we_n = 1'd1;
+reg litedramcore_ext_dfi_p2_cke = 1'd0;
+reg litedramcore_ext_dfi_p2_odt = 1'd0;
+reg litedramcore_ext_dfi_p2_reset_n = 1'd0;
+reg litedramcore_ext_dfi_p2_act_n = 1'd1;
+reg [31:0] litedramcore_ext_dfi_p2_wrdata = 32'd0;
+reg litedramcore_ext_dfi_p2_wrdata_en = 1'd0;
+reg [3:0] litedramcore_ext_dfi_p2_wrdata_mask = 4'd0;
+reg litedramcore_ext_dfi_p2_rddata_en = 1'd0;
+reg [31:0] litedramcore_ext_dfi_p2_rddata = 32'd0;
+reg litedramcore_ext_dfi_p2_rddata_valid = 1'd0;
+reg [13:0] litedramcore_ext_dfi_p3_address = 14'd0;
+reg [2:0] litedramcore_ext_dfi_p3_bank = 3'd0;
+reg litedramcore_ext_dfi_p3_cas_n = 1'd1;
+reg litedramcore_ext_dfi_p3_cs_n = 1'd1;
+reg litedramcore_ext_dfi_p3_ras_n = 1'd1;
+reg litedramcore_ext_dfi_p3_we_n = 1'd1;
+reg litedramcore_ext_dfi_p3_cke = 1'd0;
+reg litedramcore_ext_dfi_p3_odt = 1'd0;
+reg litedramcore_ext_dfi_p3_reset_n = 1'd0;
+reg litedramcore_ext_dfi_p3_act_n = 1'd1;
+reg [31:0] litedramcore_ext_dfi_p3_wrdata = 32'd0;
+reg litedramcore_ext_dfi_p3_wrdata_en = 1'd0;
+reg [3:0] litedramcore_ext_dfi_p3_wrdata_mask = 4'd0;
+reg litedramcore_ext_dfi_p3_rddata_en = 1'd0;
+reg [31:0] litedramcore_ext_dfi_p3_rddata = 32'd0;
+reg litedramcore_ext_dfi_p3_rddata_valid = 1'd0;
+reg litedramcore_ext_dfi_sel = 1'd0;
+wire litedramcore_sel;
+wire litedramcore_cke;
+wire litedramcore_odt;
+wire litedramcore_reset_n;
+reg [3:0] litedramcore_storage = 4'd1;
+reg litedramcore_re = 1'd0;
+wire litedramcore_phaseinjector0_csrfield_cs;
+wire litedramcore_phaseinjector0_csrfield_we;
+wire litedramcore_phaseinjector0_csrfield_cas;
+wire litedramcore_phaseinjector0_csrfield_ras;
+wire litedramcore_phaseinjector0_csrfield_wren;
+wire litedramcore_phaseinjector0_csrfield_rden;
+reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0;
+reg litedramcore_phaseinjector0_command_re = 1'd0;
+reg litedramcore_phaseinjector0_command_issue_re = 1'd0;
+wire litedramcore_phaseinjector0_command_issue_r;
+reg litedramcore_phaseinjector0_command_issue_we = 1'd0;
+reg litedramcore_phaseinjector0_command_issue_w = 1'd0;
+reg [13:0] litedramcore_phaseinjector0_address_storage = 14'd0;
+reg litedramcore_phaseinjector0_address_re = 1'd0;
+reg [2:0] litedramcore_phaseinjector0_baddress_storage = 3'd0;
+reg litedramcore_phaseinjector0_baddress_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector0_wrdata_storage = 32'd0;
+reg litedramcore_phaseinjector0_wrdata_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector0_rddata_status = 32'd0;
+wire litedramcore_phaseinjector0_rddata_we;
+reg litedramcore_phaseinjector0_rddata_re = 1'd0;
+wire litedramcore_phaseinjector1_csrfield_cs;
+wire litedramcore_phaseinjector1_csrfield_we;
+wire litedramcore_phaseinjector1_csrfield_cas;
+wire litedramcore_phaseinjector1_csrfield_ras;
+wire litedramcore_phaseinjector1_csrfield_wren;
+wire litedramcore_phaseinjector1_csrfield_rden;
+reg [5:0] litedramcore_phaseinjector1_command_storage = 6'd0;
+reg litedramcore_phaseinjector1_command_re = 1'd0;
+reg litedramcore_phaseinjector1_command_issue_re = 1'd0;
+wire litedramcore_phaseinjector1_command_issue_r;
+reg litedramcore_phaseinjector1_command_issue_we = 1'd0;
+reg litedramcore_phaseinjector1_command_issue_w = 1'd0;
+reg [13:0] litedramcore_phaseinjector1_address_storage = 14'd0;
+reg litedramcore_phaseinjector1_address_re = 1'd0;
+reg [2:0] litedramcore_phaseinjector1_baddress_storage = 3'd0;
+reg litedramcore_phaseinjector1_baddress_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector1_wrdata_storage = 32'd0;
+reg litedramcore_phaseinjector1_wrdata_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector1_rddata_status = 32'd0;
+wire litedramcore_phaseinjector1_rddata_we;
+reg litedramcore_phaseinjector1_rddata_re = 1'd0;
+wire litedramcore_phaseinjector2_csrfield_cs;
+wire litedramcore_phaseinjector2_csrfield_we;
+wire litedramcore_phaseinjector2_csrfield_cas;
+wire litedramcore_phaseinjector2_csrfield_ras;
+wire litedramcore_phaseinjector2_csrfield_wren;
+wire litedramcore_phaseinjector2_csrfield_rden;
+reg [5:0] litedramcore_phaseinjector2_command_storage = 6'd0;
+reg litedramcore_phaseinjector2_command_re = 1'd0;
+reg litedramcore_phaseinjector2_command_issue_re = 1'd0;
+wire litedramcore_phaseinjector2_command_issue_r;
+reg litedramcore_phaseinjector2_command_issue_we = 1'd0;
+reg litedramcore_phaseinjector2_command_issue_w = 1'd0;
+reg [13:0] litedramcore_phaseinjector2_address_storage = 14'd0;
+reg litedramcore_phaseinjector2_address_re = 1'd0;
+reg [2:0] litedramcore_phaseinjector2_baddress_storage = 3'd0;
+reg litedramcore_phaseinjector2_baddress_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector2_wrdata_storage = 32'd0;
+reg litedramcore_phaseinjector2_wrdata_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector2_rddata_status = 32'd0;
+wire litedramcore_phaseinjector2_rddata_we;
+reg litedramcore_phaseinjector2_rddata_re = 1'd0;
+wire litedramcore_phaseinjector3_csrfield_cs;
+wire litedramcore_phaseinjector3_csrfield_we;
+wire litedramcore_phaseinjector3_csrfield_cas;
+wire litedramcore_phaseinjector3_csrfield_ras;
+wire litedramcore_phaseinjector3_csrfield_wren;
+wire litedramcore_phaseinjector3_csrfield_rden;
+reg [5:0] litedramcore_phaseinjector3_command_storage = 6'd0;
+reg litedramcore_phaseinjector3_command_re = 1'd0;
+reg litedramcore_phaseinjector3_command_issue_re = 1'd0;
+wire litedramcore_phaseinjector3_command_issue_r;
+reg litedramcore_phaseinjector3_command_issue_we = 1'd0;
+reg litedramcore_phaseinjector3_command_issue_w = 1'd0;
+reg [13:0] litedramcore_phaseinjector3_address_storage = 14'd0;
+reg litedramcore_phaseinjector3_address_re = 1'd0;
+reg [2:0] litedramcore_phaseinjector3_baddress_storage = 3'd0;
+reg litedramcore_phaseinjector3_baddress_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector3_wrdata_storage = 32'd0;
+reg litedramcore_phaseinjector3_wrdata_re = 1'd0;
+reg [31:0] litedramcore_phaseinjector3_rddata_status = 32'd0;
+wire litedramcore_phaseinjector3_rddata_we;
+reg litedramcore_phaseinjector3_rddata_re = 1'd0;
+wire litedramcore_interface_bank0_valid;
+wire litedramcore_interface_bank0_ready;
+wire litedramcore_interface_bank0_we;
+wire [20:0] litedramcore_interface_bank0_addr;
+wire litedramcore_interface_bank0_lock;
+wire litedramcore_interface_bank0_wdata_ready;
+wire litedramcore_interface_bank0_rdata_valid;
+wire litedramcore_interface_bank1_valid;
+wire litedramcore_interface_bank1_ready;
+wire litedramcore_interface_bank1_we;
+wire [20:0] litedramcore_interface_bank1_addr;
+wire litedramcore_interface_bank1_lock;
+wire litedramcore_interface_bank1_wdata_ready;
+wire litedramcore_interface_bank1_rdata_valid;
+wire litedramcore_interface_bank2_valid;
+wire litedramcore_interface_bank2_ready;
+wire litedramcore_interface_bank2_we;
+wire [20:0] litedramcore_interface_bank2_addr;
+wire litedramcore_interface_bank2_lock;
+wire litedramcore_interface_bank2_wdata_ready;
+wire litedramcore_interface_bank2_rdata_valid;
+wire litedramcore_interface_bank3_valid;
+wire litedramcore_interface_bank3_ready;
+wire litedramcore_interface_bank3_we;
+wire [20:0] litedramcore_interface_bank3_addr;
+wire litedramcore_interface_bank3_lock;
+wire litedramcore_interface_bank3_wdata_ready;
+wire litedramcore_interface_bank3_rdata_valid;
+wire litedramcore_interface_bank4_valid;
+wire litedramcore_interface_bank4_ready;
+wire litedramcore_interface_bank4_we;
+wire [20:0] litedramcore_interface_bank4_addr;
+wire litedramcore_interface_bank4_lock;
+wire litedramcore_interface_bank4_wdata_ready;
+wire litedramcore_interface_bank4_rdata_valid;
+wire litedramcore_interface_bank5_valid;
+wire litedramcore_interface_bank5_ready;
+wire litedramcore_interface_bank5_we;
+wire [20:0] litedramcore_interface_bank5_addr;
+wire litedramcore_interface_bank5_lock;
+wire litedramcore_interface_bank5_wdata_ready;
+wire litedramcore_interface_bank5_rdata_valid;
+wire litedramcore_interface_bank6_valid;
+wire litedramcore_interface_bank6_ready;
+wire litedramcore_interface_bank6_we;
+wire [20:0] litedramcore_interface_bank6_addr;
+wire litedramcore_interface_bank6_lock;
+wire litedramcore_interface_bank6_wdata_ready;
+wire litedramcore_interface_bank6_rdata_valid;
+wire litedramcore_interface_bank7_valid;
+wire litedramcore_interface_bank7_ready;
+wire litedramcore_interface_bank7_we;
+wire [20:0] litedramcore_interface_bank7_addr;
+wire litedramcore_interface_bank7_lock;
+wire litedramcore_interface_bank7_wdata_ready;
+wire litedramcore_interface_bank7_rdata_valid;
+reg [127:0] litedramcore_interface_wdata = 128'd0;
+reg [15:0] litedramcore_interface_wdata_we = 16'd0;
+wire [127:0] litedramcore_interface_rdata;
+reg [13:0] litedramcore_dfi_p0_address = 14'd0;
+reg [2:0] litedramcore_dfi_p0_bank = 3'd0;
+reg litedramcore_dfi_p0_cas_n = 1'd1;
+reg litedramcore_dfi_p0_cs_n = 1'd1;
+reg litedramcore_dfi_p0_ras_n = 1'd1;
+reg litedramcore_dfi_p0_we_n = 1'd1;
+wire litedramcore_dfi_p0_cke;
+wire litedramcore_dfi_p0_odt;
+wire litedramcore_dfi_p0_reset_n;
+reg litedramcore_dfi_p0_act_n = 1'd1;
+wire [31:0] litedramcore_dfi_p0_wrdata;
+reg litedramcore_dfi_p0_wrdata_en = 1'd0;
+wire [3:0] litedramcore_dfi_p0_wrdata_mask;
+reg litedramcore_dfi_p0_rddata_en = 1'd0;
+wire [31:0] litedramcore_dfi_p0_rddata;
+wire litedramcore_dfi_p0_rddata_valid;
+reg [13:0] litedramcore_dfi_p1_address = 14'd0;
+reg [2:0] litedramcore_dfi_p1_bank = 3'd0;
+reg litedramcore_dfi_p1_cas_n = 1'd1;
+reg litedramcore_dfi_p1_cs_n = 1'd1;
+reg litedramcore_dfi_p1_ras_n = 1'd1;
+reg litedramcore_dfi_p1_we_n = 1'd1;
+wire litedramcore_dfi_p1_cke;
+wire litedramcore_dfi_p1_odt;
+wire litedramcore_dfi_p1_reset_n;
+reg litedramcore_dfi_p1_act_n = 1'd1;
+wire [31:0] litedramcore_dfi_p1_wrdata;
+reg litedramcore_dfi_p1_wrdata_en = 1'd0;
+wire [3:0] litedramcore_dfi_p1_wrdata_mask;
+reg litedramcore_dfi_p1_rddata_en = 1'd0;
+wire [31:0] litedramcore_dfi_p1_rddata;
+wire litedramcore_dfi_p1_rddata_valid;
+reg [13:0] litedramcore_dfi_p2_address = 14'd0;
+reg [2:0] litedramcore_dfi_p2_bank = 3'd0;
+reg litedramcore_dfi_p2_cas_n = 1'd1;
+reg litedramcore_dfi_p2_cs_n = 1'd1;
+reg litedramcore_dfi_p2_ras_n = 1'd1;
+reg litedramcore_dfi_p2_we_n = 1'd1;
+wire litedramcore_dfi_p2_cke;
+wire litedramcore_dfi_p2_odt;
+wire litedramcore_dfi_p2_reset_n;
+reg litedramcore_dfi_p2_act_n = 1'd1;
+wire [31:0] litedramcore_dfi_p2_wrdata;
+reg litedramcore_dfi_p2_wrdata_en = 1'd0;
+wire [3:0] litedramcore_dfi_p2_wrdata_mask;
+reg litedramcore_dfi_p2_rddata_en = 1'd0;
+wire [31:0] litedramcore_dfi_p2_rddata;
+wire litedramcore_dfi_p2_rddata_valid;
+reg [13:0] litedramcore_dfi_p3_address = 14'd0;
+reg [2:0] litedramcore_dfi_p3_bank = 3'd0;
+reg litedramcore_dfi_p3_cas_n = 1'd1;
+reg litedramcore_dfi_p3_cs_n = 1'd1;
+reg litedramcore_dfi_p3_ras_n = 1'd1;
+reg litedramcore_dfi_p3_we_n = 1'd1;
+wire litedramcore_dfi_p3_cke;
+wire litedramcore_dfi_p3_odt;
+wire litedramcore_dfi_p3_reset_n;
+reg litedramcore_dfi_p3_act_n = 1'd1;
+wire [31:0] litedramcore_dfi_p3_wrdata;
+reg litedramcore_dfi_p3_wrdata_en = 1'd0;
+wire [3:0] litedramcore_dfi_p3_wrdata_mask;
+reg litedramcore_dfi_p3_rddata_en = 1'd0;
+wire [31:0] litedramcore_dfi_p3_rddata;
+wire litedramcore_dfi_p3_rddata_valid;
+reg litedramcore_cmd_valid = 1'd0;
+reg litedramcore_cmd_ready = 1'd0;
+reg litedramcore_cmd_last = 1'd0;
+reg [13:0] litedramcore_cmd_payload_a = 14'd0;
+reg [2:0] litedramcore_cmd_payload_ba = 3'd0;
+reg litedramcore_cmd_payload_cas = 1'd0;
+reg litedramcore_cmd_payload_ras = 1'd0;
+reg litedramcore_cmd_payload_we = 1'd0;
+reg litedramcore_cmd_payload_is_read = 1'd0;
+reg litedramcore_cmd_payload_is_write = 1'd0;
+wire litedramcore_wants_refresh;
+wire litedramcore_wants_zqcs;
+wire litedramcore_timer_wait;
+wire litedramcore_timer_done0;
+wire [9:0] litedramcore_timer_count0;
+wire litedramcore_timer_done1;
+reg [9:0] litedramcore_timer_count1 = 10'd781;
+wire litedramcore_postponer_req_i;
+reg litedramcore_postponer_req_o = 1'd0;
+reg litedramcore_postponer_count = 1'd0;
+reg litedramcore_sequencer_start0 = 1'd0;
+wire litedramcore_sequencer_done0;
+wire litedramcore_sequencer_start1;
+reg litedramcore_sequencer_done1 = 1'd0;
+reg [5:0] litedramcore_sequencer_counter = 6'd0;
+reg litedramcore_sequencer_count = 1'd0;
+wire litedramcore_zqcs_timer_wait;
+wire litedramcore_zqcs_timer_done0;
+wire [26:0] litedramcore_zqcs_timer_count0;
+wire litedramcore_zqcs_timer_done1;
+reg [26:0] litedramcore_zqcs_timer_count1 = 27'd99999999;
+reg litedramcore_zqcs_executer_start = 1'd0;
+reg litedramcore_zqcs_executer_done = 1'd0;
+reg [4:0] litedramcore_zqcs_executer_counter = 5'd0;
+wire litedramcore_bankmachine0_req_valid;
+wire litedramcore_bankmachine0_req_ready;
+wire litedramcore_bankmachine0_req_we;
+wire [20:0] litedramcore_bankmachine0_req_addr;
+wire litedramcore_bankmachine0_req_lock;
+reg litedramcore_bankmachine0_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine0_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine0_refresh_req;
+reg litedramcore_bankmachine0_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine0_cmd_valid = 1'd0;
+reg litedramcore_bankmachine0_cmd_ready = 1'd0;
+reg [13:0] litedramcore_bankmachine0_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine0_cmd_payload_ba;
+reg litedramcore_bankmachine0_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine0_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine0_auto_precharge = 1'd0;
+wire litedramcore_bankmachine0_sink_valid;
+wire litedramcore_bankmachine0_sink_ready;
+reg litedramcore_bankmachine0_sink_first = 1'd0;
+reg litedramcore_bankmachine0_sink_last = 1'd0;
+wire litedramcore_bankmachine0_sink_payload_we;
+wire [20:0] litedramcore_bankmachine0_sink_payload_addr;
+wire litedramcore_bankmachine0_source_valid;
+wire litedramcore_bankmachine0_source_ready;
+wire litedramcore_bankmachine0_source_first;
+wire litedramcore_bankmachine0_source_last;
+wire litedramcore_bankmachine0_source_payload_we;
+wire [20:0] litedramcore_bankmachine0_source_payload_addr;
+wire litedramcore_bankmachine0_syncfifo0_we;
+wire litedramcore_bankmachine0_syncfifo0_writable;
+wire litedramcore_bankmachine0_syncfifo0_re;
+wire litedramcore_bankmachine0_syncfifo0_readable;
+wire [23:0] litedramcore_bankmachine0_syncfifo0_din;
+wire [23:0] litedramcore_bankmachine0_syncfifo0_dout;
+reg [4:0] litedramcore_bankmachine0_level = 5'd0;
+reg litedramcore_bankmachine0_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine0_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine0_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine0_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine0_wrport_dat_r;
+wire litedramcore_bankmachine0_wrport_we;
+wire [23:0] litedramcore_bankmachine0_wrport_dat_w;
+wire litedramcore_bankmachine0_do_read;
+wire [3:0] litedramcore_bankmachine0_rdport_adr;
+wire [23:0] litedramcore_bankmachine0_rdport_dat_r;
+wire litedramcore_bankmachine0_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine0_fifo_in_payload_addr;
+wire litedramcore_bankmachine0_fifo_in_first;
+wire litedramcore_bankmachine0_fifo_in_last;
+wire litedramcore_bankmachine0_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine0_fifo_out_payload_addr;
+wire litedramcore_bankmachine0_fifo_out_first;
+wire litedramcore_bankmachine0_fifo_out_last;
+wire litedramcore_bankmachine0_sink_sink_valid;
+wire litedramcore_bankmachine0_sink_sink_ready;
+wire litedramcore_bankmachine0_sink_sink_first;
+wire litedramcore_bankmachine0_sink_sink_last;
+wire litedramcore_bankmachine0_sink_sink_payload_we;
+wire [20:0] litedramcore_bankmachine0_sink_sink_payload_addr;
+wire litedramcore_bankmachine0_source_source_valid;
+wire litedramcore_bankmachine0_source_source_ready;
+wire litedramcore_bankmachine0_source_source_first;
+wire litedramcore_bankmachine0_source_source_last;
+wire litedramcore_bankmachine0_source_source_payload_we;
+wire [20:0] litedramcore_bankmachine0_source_source_payload_addr;
+wire litedramcore_bankmachine0_pipe_valid_sink_valid;
+wire litedramcore_bankmachine0_pipe_valid_sink_ready;
+wire litedramcore_bankmachine0_pipe_valid_sink_first;
+wire litedramcore_bankmachine0_pipe_valid_sink_last;
+wire litedramcore_bankmachine0_pipe_valid_sink_payload_we;
+wire [20:0] litedramcore_bankmachine0_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine0_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine0_pipe_valid_source_ready;
+reg litedramcore_bankmachine0_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine0_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine0_pipe_valid_source_payload_we = 1'd0;
+reg [20:0] litedramcore_bankmachine0_pipe_valid_source_payload_addr = 21'd0;
+reg [13:0] litedramcore_bankmachine0_row = 14'd0;
+reg litedramcore_bankmachine0_row_opened = 1'd0;
+wire litedramcore_bankmachine0_row_hit;
+reg litedramcore_bankmachine0_row_open = 1'd0;
+reg litedramcore_bankmachine0_row_close = 1'd0;
+reg litedramcore_bankmachine0_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine0_twtpcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine0_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine0_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine0_trccon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine0_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine0_trccon_count = 3'd0;
+wire litedramcore_bankmachine0_trascon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine0_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine0_trascon_count = 3'd0;
+wire litedramcore_bankmachine1_req_valid;
+wire litedramcore_bankmachine1_req_ready;
+wire litedramcore_bankmachine1_req_we;
+wire [20:0] litedramcore_bankmachine1_req_addr;
+wire litedramcore_bankmachine1_req_lock;
+reg litedramcore_bankmachine1_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine1_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine1_refresh_req;
+reg litedramcore_bankmachine1_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine1_cmd_valid = 1'd0;
+reg litedramcore_bankmachine1_cmd_ready = 1'd0;
+reg [13:0] litedramcore_bankmachine1_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine1_cmd_payload_ba;
+reg litedramcore_bankmachine1_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine1_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine1_auto_precharge = 1'd0;
+wire litedramcore_bankmachine1_sink_valid;
+wire litedramcore_bankmachine1_sink_ready;
+reg litedramcore_bankmachine1_sink_first = 1'd0;
+reg litedramcore_bankmachine1_sink_last = 1'd0;
+wire litedramcore_bankmachine1_sink_payload_we;
+wire [20:0] litedramcore_bankmachine1_sink_payload_addr;
+wire litedramcore_bankmachine1_source_valid;
+wire litedramcore_bankmachine1_source_ready;
+wire litedramcore_bankmachine1_source_first;
+wire litedramcore_bankmachine1_source_last;
+wire litedramcore_bankmachine1_source_payload_we;
+wire [20:0] litedramcore_bankmachine1_source_payload_addr;
+wire litedramcore_bankmachine1_syncfifo1_we;
+wire litedramcore_bankmachine1_syncfifo1_writable;
+wire litedramcore_bankmachine1_syncfifo1_re;
+wire litedramcore_bankmachine1_syncfifo1_readable;
+wire [23:0] litedramcore_bankmachine1_syncfifo1_din;
+wire [23:0] litedramcore_bankmachine1_syncfifo1_dout;
+reg [4:0] litedramcore_bankmachine1_level = 5'd0;
+reg litedramcore_bankmachine1_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine1_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine1_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine1_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine1_wrport_dat_r;
+wire litedramcore_bankmachine1_wrport_we;
+wire [23:0] litedramcore_bankmachine1_wrport_dat_w;
+wire litedramcore_bankmachine1_do_read;
+wire [3:0] litedramcore_bankmachine1_rdport_adr;
+wire [23:0] litedramcore_bankmachine1_rdport_dat_r;
+wire litedramcore_bankmachine1_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine1_fifo_in_payload_addr;
+wire litedramcore_bankmachine1_fifo_in_first;
+wire litedramcore_bankmachine1_fifo_in_last;
+wire litedramcore_bankmachine1_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine1_fifo_out_payload_addr;
+wire litedramcore_bankmachine1_fifo_out_first;
+wire litedramcore_bankmachine1_fifo_out_last;
+wire litedramcore_bankmachine1_sink_sink_valid;
+wire litedramcore_bankmachine1_sink_sink_ready;
+wire litedramcore_bankmachine1_sink_sink_first;
+wire litedramcore_bankmachine1_sink_sink_last;
+wire litedramcore_bankmachine1_sink_sink_payload_we;
+wire [20:0] litedramcore_bankmachine1_sink_sink_payload_addr;
+wire litedramcore_bankmachine1_source_source_valid;
+wire litedramcore_bankmachine1_source_source_ready;
+wire litedramcore_bankmachine1_source_source_first;
+wire litedramcore_bankmachine1_source_source_last;
+wire litedramcore_bankmachine1_source_source_payload_we;
+wire [20:0] litedramcore_bankmachine1_source_source_payload_addr;
+wire litedramcore_bankmachine1_pipe_valid_sink_valid;
+wire litedramcore_bankmachine1_pipe_valid_sink_ready;
+wire litedramcore_bankmachine1_pipe_valid_sink_first;
+wire litedramcore_bankmachine1_pipe_valid_sink_last;
+wire litedramcore_bankmachine1_pipe_valid_sink_payload_we;
+wire [20:0] litedramcore_bankmachine1_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine1_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine1_pipe_valid_source_ready;
+reg litedramcore_bankmachine1_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine1_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine1_pipe_valid_source_payload_we = 1'd0;
+reg [20:0] litedramcore_bankmachine1_pipe_valid_source_payload_addr = 21'd0;
+reg [13:0] litedramcore_bankmachine1_row = 14'd0;
+reg litedramcore_bankmachine1_row_opened = 1'd0;
+wire litedramcore_bankmachine1_row_hit;
+reg litedramcore_bankmachine1_row_open = 1'd0;
+reg litedramcore_bankmachine1_row_close = 1'd0;
+reg litedramcore_bankmachine1_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine1_twtpcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine1_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine1_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine1_trccon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine1_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine1_trccon_count = 3'd0;
+wire litedramcore_bankmachine1_trascon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine1_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine1_trascon_count = 3'd0;
+wire litedramcore_bankmachine2_req_valid;
+wire litedramcore_bankmachine2_req_ready;
+wire litedramcore_bankmachine2_req_we;
+wire [20:0] litedramcore_bankmachine2_req_addr;
+wire litedramcore_bankmachine2_req_lock;
+reg litedramcore_bankmachine2_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine2_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine2_refresh_req;
+reg litedramcore_bankmachine2_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine2_cmd_valid = 1'd0;
+reg litedramcore_bankmachine2_cmd_ready = 1'd0;
+reg [13:0] litedramcore_bankmachine2_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine2_cmd_payload_ba;
+reg litedramcore_bankmachine2_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine2_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine2_auto_precharge = 1'd0;
+wire litedramcore_bankmachine2_sink_valid;
+wire litedramcore_bankmachine2_sink_ready;
+reg litedramcore_bankmachine2_sink_first = 1'd0;
+reg litedramcore_bankmachine2_sink_last = 1'd0;
+wire litedramcore_bankmachine2_sink_payload_we;
+wire [20:0] litedramcore_bankmachine2_sink_payload_addr;
+wire litedramcore_bankmachine2_source_valid;
+wire litedramcore_bankmachine2_source_ready;
+wire litedramcore_bankmachine2_source_first;
+wire litedramcore_bankmachine2_source_last;
+wire litedramcore_bankmachine2_source_payload_we;
+wire [20:0] litedramcore_bankmachine2_source_payload_addr;
+wire litedramcore_bankmachine2_syncfifo2_we;
+wire litedramcore_bankmachine2_syncfifo2_writable;
+wire litedramcore_bankmachine2_syncfifo2_re;
+wire litedramcore_bankmachine2_syncfifo2_readable;
+wire [23:0] litedramcore_bankmachine2_syncfifo2_din;
+wire [23:0] litedramcore_bankmachine2_syncfifo2_dout;
+reg [4:0] litedramcore_bankmachine2_level = 5'd0;
+reg litedramcore_bankmachine2_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine2_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine2_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine2_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine2_wrport_dat_r;
+wire litedramcore_bankmachine2_wrport_we;
+wire [23:0] litedramcore_bankmachine2_wrport_dat_w;
+wire litedramcore_bankmachine2_do_read;
+wire [3:0] litedramcore_bankmachine2_rdport_adr;
+wire [23:0] litedramcore_bankmachine2_rdport_dat_r;
+wire litedramcore_bankmachine2_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine2_fifo_in_payload_addr;
+wire litedramcore_bankmachine2_fifo_in_first;
+wire litedramcore_bankmachine2_fifo_in_last;
+wire litedramcore_bankmachine2_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine2_fifo_out_payload_addr;
+wire litedramcore_bankmachine2_fifo_out_first;
+wire litedramcore_bankmachine2_fifo_out_last;
+wire litedramcore_bankmachine2_sink_sink_valid;
+wire litedramcore_bankmachine2_sink_sink_ready;
+wire litedramcore_bankmachine2_sink_sink_first;
+wire litedramcore_bankmachine2_sink_sink_last;
+wire litedramcore_bankmachine2_sink_sink_payload_we;
+wire [20:0] litedramcore_bankmachine2_sink_sink_payload_addr;
+wire litedramcore_bankmachine2_source_source_valid;
+wire litedramcore_bankmachine2_source_source_ready;
+wire litedramcore_bankmachine2_source_source_first;
+wire litedramcore_bankmachine2_source_source_last;
+wire litedramcore_bankmachine2_source_source_payload_we;
+wire [20:0] litedramcore_bankmachine2_source_source_payload_addr;
+wire litedramcore_bankmachine2_pipe_valid_sink_valid;
+wire litedramcore_bankmachine2_pipe_valid_sink_ready;
+wire litedramcore_bankmachine2_pipe_valid_sink_first;
+wire litedramcore_bankmachine2_pipe_valid_sink_last;
+wire litedramcore_bankmachine2_pipe_valid_sink_payload_we;
+wire [20:0] litedramcore_bankmachine2_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine2_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine2_pipe_valid_source_ready;
+reg litedramcore_bankmachine2_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine2_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine2_pipe_valid_source_payload_we = 1'd0;
+reg [20:0] litedramcore_bankmachine2_pipe_valid_source_payload_addr = 21'd0;
+reg [13:0] litedramcore_bankmachine2_row = 14'd0;
+reg litedramcore_bankmachine2_row_opened = 1'd0;
+wire litedramcore_bankmachine2_row_hit;
+reg litedramcore_bankmachine2_row_open = 1'd0;
+reg litedramcore_bankmachine2_row_close = 1'd0;
+reg litedramcore_bankmachine2_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine2_twtpcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine2_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine2_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine2_trccon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine2_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine2_trccon_count = 3'd0;
+wire litedramcore_bankmachine2_trascon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine2_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine2_trascon_count = 3'd0;
+wire litedramcore_bankmachine3_req_valid;
+wire litedramcore_bankmachine3_req_ready;
+wire litedramcore_bankmachine3_req_we;
+wire [20:0] litedramcore_bankmachine3_req_addr;
+wire litedramcore_bankmachine3_req_lock;
+reg litedramcore_bankmachine3_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine3_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine3_refresh_req;
+reg litedramcore_bankmachine3_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine3_cmd_valid = 1'd0;
+reg litedramcore_bankmachine3_cmd_ready = 1'd0;
+reg [13:0] litedramcore_bankmachine3_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine3_cmd_payload_ba;
+reg litedramcore_bankmachine3_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine3_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine3_auto_precharge = 1'd0;
+wire litedramcore_bankmachine3_sink_valid;
+wire litedramcore_bankmachine3_sink_ready;
+reg litedramcore_bankmachine3_sink_first = 1'd0;
+reg litedramcore_bankmachine3_sink_last = 1'd0;
+wire litedramcore_bankmachine3_sink_payload_we;
+wire [20:0] litedramcore_bankmachine3_sink_payload_addr;
+wire litedramcore_bankmachine3_source_valid;
+wire litedramcore_bankmachine3_source_ready;
+wire litedramcore_bankmachine3_source_first;
+wire litedramcore_bankmachine3_source_last;
+wire litedramcore_bankmachine3_source_payload_we;
+wire [20:0] litedramcore_bankmachine3_source_payload_addr;
+wire litedramcore_bankmachine3_syncfifo3_we;
+wire litedramcore_bankmachine3_syncfifo3_writable;
+wire litedramcore_bankmachine3_syncfifo3_re;
+wire litedramcore_bankmachine3_syncfifo3_readable;
+wire [23:0] litedramcore_bankmachine3_syncfifo3_din;
+wire [23:0] litedramcore_bankmachine3_syncfifo3_dout;
+reg [4:0] litedramcore_bankmachine3_level = 5'd0;
+reg litedramcore_bankmachine3_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine3_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine3_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine3_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine3_wrport_dat_r;
+wire litedramcore_bankmachine3_wrport_we;
+wire [23:0] litedramcore_bankmachine3_wrport_dat_w;
+wire litedramcore_bankmachine3_do_read;
+wire [3:0] litedramcore_bankmachine3_rdport_adr;
+wire [23:0] litedramcore_bankmachine3_rdport_dat_r;
+wire litedramcore_bankmachine3_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine3_fifo_in_payload_addr;
+wire litedramcore_bankmachine3_fifo_in_first;
+wire litedramcore_bankmachine3_fifo_in_last;
+wire litedramcore_bankmachine3_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine3_fifo_out_payload_addr;
+wire litedramcore_bankmachine3_fifo_out_first;
+wire litedramcore_bankmachine3_fifo_out_last;
+wire litedramcore_bankmachine3_sink_sink_valid;
+wire litedramcore_bankmachine3_sink_sink_ready;
+wire litedramcore_bankmachine3_sink_sink_first;
+wire litedramcore_bankmachine3_sink_sink_last;
+wire litedramcore_bankmachine3_sink_sink_payload_we;
+wire [20:0] litedramcore_bankmachine3_sink_sink_payload_addr;
+wire litedramcore_bankmachine3_source_source_valid;
+wire litedramcore_bankmachine3_source_source_ready;
+wire litedramcore_bankmachine3_source_source_first;
+wire litedramcore_bankmachine3_source_source_last;
+wire litedramcore_bankmachine3_source_source_payload_we;
+wire [20:0] litedramcore_bankmachine3_source_source_payload_addr;
+wire litedramcore_bankmachine3_pipe_valid_sink_valid;
+wire litedramcore_bankmachine3_pipe_valid_sink_ready;
+wire litedramcore_bankmachine3_pipe_valid_sink_first;
+wire litedramcore_bankmachine3_pipe_valid_sink_last;
+wire litedramcore_bankmachine3_pipe_valid_sink_payload_we;
+wire [20:0] litedramcore_bankmachine3_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine3_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine3_pipe_valid_source_ready;
+reg litedramcore_bankmachine3_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine3_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine3_pipe_valid_source_payload_we = 1'd0;
+reg [20:0] litedramcore_bankmachine3_pipe_valid_source_payload_addr = 21'd0;
+reg [13:0] litedramcore_bankmachine3_row = 14'd0;
+reg litedramcore_bankmachine3_row_opened = 1'd0;
+wire litedramcore_bankmachine3_row_hit;
+reg litedramcore_bankmachine3_row_open = 1'd0;
+reg litedramcore_bankmachine3_row_close = 1'd0;
+reg litedramcore_bankmachine3_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine3_twtpcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine3_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine3_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine3_trccon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine3_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine3_trccon_count = 3'd0;
+wire litedramcore_bankmachine3_trascon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine3_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine3_trascon_count = 3'd0;
+wire litedramcore_bankmachine4_req_valid;
+wire litedramcore_bankmachine4_req_ready;
+wire litedramcore_bankmachine4_req_we;
+wire [20:0] litedramcore_bankmachine4_req_addr;
+wire litedramcore_bankmachine4_req_lock;
+reg litedramcore_bankmachine4_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine4_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine4_refresh_req;
+reg litedramcore_bankmachine4_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine4_cmd_valid = 1'd0;
+reg litedramcore_bankmachine4_cmd_ready = 1'd0;
+reg [13:0] litedramcore_bankmachine4_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine4_cmd_payload_ba;
+reg litedramcore_bankmachine4_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine4_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine4_auto_precharge = 1'd0;
+wire litedramcore_bankmachine4_sink_valid;
+wire litedramcore_bankmachine4_sink_ready;
+reg litedramcore_bankmachine4_sink_first = 1'd0;
+reg litedramcore_bankmachine4_sink_last = 1'd0;
+wire litedramcore_bankmachine4_sink_payload_we;
+wire [20:0] litedramcore_bankmachine4_sink_payload_addr;
+wire litedramcore_bankmachine4_source_valid;
+wire litedramcore_bankmachine4_source_ready;
+wire litedramcore_bankmachine4_source_first;
+wire litedramcore_bankmachine4_source_last;
+wire litedramcore_bankmachine4_source_payload_we;
+wire [20:0] litedramcore_bankmachine4_source_payload_addr;
+wire litedramcore_bankmachine4_syncfifo4_we;
+wire litedramcore_bankmachine4_syncfifo4_writable;
+wire litedramcore_bankmachine4_syncfifo4_re;
+wire litedramcore_bankmachine4_syncfifo4_readable;
+wire [23:0] litedramcore_bankmachine4_syncfifo4_din;
+wire [23:0] litedramcore_bankmachine4_syncfifo4_dout;
+reg [4:0] litedramcore_bankmachine4_level = 5'd0;
+reg litedramcore_bankmachine4_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine4_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine4_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine4_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine4_wrport_dat_r;
+wire litedramcore_bankmachine4_wrport_we;
+wire [23:0] litedramcore_bankmachine4_wrport_dat_w;
+wire litedramcore_bankmachine4_do_read;
+wire [3:0] litedramcore_bankmachine4_rdport_adr;
+wire [23:0] litedramcore_bankmachine4_rdport_dat_r;
+wire litedramcore_bankmachine4_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine4_fifo_in_payload_addr;
+wire litedramcore_bankmachine4_fifo_in_first;
+wire litedramcore_bankmachine4_fifo_in_last;
+wire litedramcore_bankmachine4_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine4_fifo_out_payload_addr;
+wire litedramcore_bankmachine4_fifo_out_first;
+wire litedramcore_bankmachine4_fifo_out_last;
+wire litedramcore_bankmachine4_sink_sink_valid;
+wire litedramcore_bankmachine4_sink_sink_ready;
+wire litedramcore_bankmachine4_sink_sink_first;
+wire litedramcore_bankmachine4_sink_sink_last;
+wire litedramcore_bankmachine4_sink_sink_payload_we;
+wire [20:0] litedramcore_bankmachine4_sink_sink_payload_addr;
+wire litedramcore_bankmachine4_source_source_valid;
+wire litedramcore_bankmachine4_source_source_ready;
+wire litedramcore_bankmachine4_source_source_first;
+wire litedramcore_bankmachine4_source_source_last;
+wire litedramcore_bankmachine4_source_source_payload_we;
+wire [20:0] litedramcore_bankmachine4_source_source_payload_addr;
+wire litedramcore_bankmachine4_pipe_valid_sink_valid;
+wire litedramcore_bankmachine4_pipe_valid_sink_ready;
+wire litedramcore_bankmachine4_pipe_valid_sink_first;
+wire litedramcore_bankmachine4_pipe_valid_sink_last;
+wire litedramcore_bankmachine4_pipe_valid_sink_payload_we;
+wire [20:0] litedramcore_bankmachine4_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine4_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine4_pipe_valid_source_ready;
+reg litedramcore_bankmachine4_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine4_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine4_pipe_valid_source_payload_we = 1'd0;
+reg [20:0] litedramcore_bankmachine4_pipe_valid_source_payload_addr = 21'd0;
+reg [13:0] litedramcore_bankmachine4_row = 14'd0;
+reg litedramcore_bankmachine4_row_opened = 1'd0;
+wire litedramcore_bankmachine4_row_hit;
+reg litedramcore_bankmachine4_row_open = 1'd0;
+reg litedramcore_bankmachine4_row_close = 1'd0;
+reg litedramcore_bankmachine4_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine4_twtpcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine4_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine4_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine4_trccon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine4_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine4_trccon_count = 3'd0;
+wire litedramcore_bankmachine4_trascon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine4_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine4_trascon_count = 3'd0;
+wire litedramcore_bankmachine5_req_valid;
+wire litedramcore_bankmachine5_req_ready;
+wire litedramcore_bankmachine5_req_we;
+wire [20:0] litedramcore_bankmachine5_req_addr;
+wire litedramcore_bankmachine5_req_lock;
+reg litedramcore_bankmachine5_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine5_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine5_refresh_req;
+reg litedramcore_bankmachine5_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine5_cmd_valid = 1'd0;
+reg litedramcore_bankmachine5_cmd_ready = 1'd0;
+reg [13:0] litedramcore_bankmachine5_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine5_cmd_payload_ba;
+reg litedramcore_bankmachine5_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine5_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine5_auto_precharge = 1'd0;
+wire litedramcore_bankmachine5_sink_valid;
+wire litedramcore_bankmachine5_sink_ready;
+reg litedramcore_bankmachine5_sink_first = 1'd0;
+reg litedramcore_bankmachine5_sink_last = 1'd0;
+wire litedramcore_bankmachine5_sink_payload_we;
+wire [20:0] litedramcore_bankmachine5_sink_payload_addr;
+wire litedramcore_bankmachine5_source_valid;
+wire litedramcore_bankmachine5_source_ready;
+wire litedramcore_bankmachine5_source_first;
+wire litedramcore_bankmachine5_source_last;
+wire litedramcore_bankmachine5_source_payload_we;
+wire [20:0] litedramcore_bankmachine5_source_payload_addr;
+wire litedramcore_bankmachine5_syncfifo5_we;
+wire litedramcore_bankmachine5_syncfifo5_writable;
+wire litedramcore_bankmachine5_syncfifo5_re;
+wire litedramcore_bankmachine5_syncfifo5_readable;
+wire [23:0] litedramcore_bankmachine5_syncfifo5_din;
+wire [23:0] litedramcore_bankmachine5_syncfifo5_dout;
+reg [4:0] litedramcore_bankmachine5_level = 5'd0;
+reg litedramcore_bankmachine5_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine5_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine5_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine5_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine5_wrport_dat_r;
+wire litedramcore_bankmachine5_wrport_we;
+wire [23:0] litedramcore_bankmachine5_wrport_dat_w;
+wire litedramcore_bankmachine5_do_read;
+wire [3:0] litedramcore_bankmachine5_rdport_adr;
+wire [23:0] litedramcore_bankmachine5_rdport_dat_r;
+wire litedramcore_bankmachine5_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine5_fifo_in_payload_addr;
+wire litedramcore_bankmachine5_fifo_in_first;
+wire litedramcore_bankmachine5_fifo_in_last;
+wire litedramcore_bankmachine5_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine5_fifo_out_payload_addr;
+wire litedramcore_bankmachine5_fifo_out_first;
+wire litedramcore_bankmachine5_fifo_out_last;
+wire litedramcore_bankmachine5_sink_sink_valid;
+wire litedramcore_bankmachine5_sink_sink_ready;
+wire litedramcore_bankmachine5_sink_sink_first;
+wire litedramcore_bankmachine5_sink_sink_last;
+wire litedramcore_bankmachine5_sink_sink_payload_we;
+wire [20:0] litedramcore_bankmachine5_sink_sink_payload_addr;
+wire litedramcore_bankmachine5_source_source_valid;
+wire litedramcore_bankmachine5_source_source_ready;
+wire litedramcore_bankmachine5_source_source_first;
+wire litedramcore_bankmachine5_source_source_last;
+wire litedramcore_bankmachine5_source_source_payload_we;
+wire [20:0] litedramcore_bankmachine5_source_source_payload_addr;
+wire litedramcore_bankmachine5_pipe_valid_sink_valid;
+wire litedramcore_bankmachine5_pipe_valid_sink_ready;
+wire litedramcore_bankmachine5_pipe_valid_sink_first;
+wire litedramcore_bankmachine5_pipe_valid_sink_last;
+wire litedramcore_bankmachine5_pipe_valid_sink_payload_we;
+wire [20:0] litedramcore_bankmachine5_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine5_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine5_pipe_valid_source_ready;
+reg litedramcore_bankmachine5_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine5_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine5_pipe_valid_source_payload_we = 1'd0;
+reg [20:0] litedramcore_bankmachine5_pipe_valid_source_payload_addr = 21'd0;
+reg [13:0] litedramcore_bankmachine5_row = 14'd0;
+reg litedramcore_bankmachine5_row_opened = 1'd0;
+wire litedramcore_bankmachine5_row_hit;
+reg litedramcore_bankmachine5_row_open = 1'd0;
+reg litedramcore_bankmachine5_row_close = 1'd0;
+reg litedramcore_bankmachine5_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine5_twtpcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine5_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine5_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine5_trccon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine5_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine5_trccon_count = 3'd0;
+wire litedramcore_bankmachine5_trascon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine5_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine5_trascon_count = 3'd0;
+wire litedramcore_bankmachine6_req_valid;
+wire litedramcore_bankmachine6_req_ready;
+wire litedramcore_bankmachine6_req_we;
+wire [20:0] litedramcore_bankmachine6_req_addr;
+wire litedramcore_bankmachine6_req_lock;
+reg litedramcore_bankmachine6_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine6_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine6_refresh_req;
+reg litedramcore_bankmachine6_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine6_cmd_valid = 1'd0;
+reg litedramcore_bankmachine6_cmd_ready = 1'd0;
+reg [13:0] litedramcore_bankmachine6_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine6_cmd_payload_ba;
+reg litedramcore_bankmachine6_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine6_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine6_auto_precharge = 1'd0;
+wire litedramcore_bankmachine6_sink_valid;
+wire litedramcore_bankmachine6_sink_ready;
+reg litedramcore_bankmachine6_sink_first = 1'd0;
+reg litedramcore_bankmachine6_sink_last = 1'd0;
+wire litedramcore_bankmachine6_sink_payload_we;
+wire [20:0] litedramcore_bankmachine6_sink_payload_addr;
+wire litedramcore_bankmachine6_source_valid;
+wire litedramcore_bankmachine6_source_ready;
+wire litedramcore_bankmachine6_source_first;
+wire litedramcore_bankmachine6_source_last;
+wire litedramcore_bankmachine6_source_payload_we;
+wire [20:0] litedramcore_bankmachine6_source_payload_addr;
+wire litedramcore_bankmachine6_syncfifo6_we;
+wire litedramcore_bankmachine6_syncfifo6_writable;
+wire litedramcore_bankmachine6_syncfifo6_re;
+wire litedramcore_bankmachine6_syncfifo6_readable;
+wire [23:0] litedramcore_bankmachine6_syncfifo6_din;
+wire [23:0] litedramcore_bankmachine6_syncfifo6_dout;
+reg [4:0] litedramcore_bankmachine6_level = 5'd0;
+reg litedramcore_bankmachine6_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine6_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine6_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine6_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine6_wrport_dat_r;
+wire litedramcore_bankmachine6_wrport_we;
+wire [23:0] litedramcore_bankmachine6_wrport_dat_w;
+wire litedramcore_bankmachine6_do_read;
+wire [3:0] litedramcore_bankmachine6_rdport_adr;
+wire [23:0] litedramcore_bankmachine6_rdport_dat_r;
+wire litedramcore_bankmachine6_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine6_fifo_in_payload_addr;
+wire litedramcore_bankmachine6_fifo_in_first;
+wire litedramcore_bankmachine6_fifo_in_last;
+wire litedramcore_bankmachine6_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine6_fifo_out_payload_addr;
+wire litedramcore_bankmachine6_fifo_out_first;
+wire litedramcore_bankmachine6_fifo_out_last;
+wire litedramcore_bankmachine6_sink_sink_valid;
+wire litedramcore_bankmachine6_sink_sink_ready;
+wire litedramcore_bankmachine6_sink_sink_first;
+wire litedramcore_bankmachine6_sink_sink_last;
+wire litedramcore_bankmachine6_sink_sink_payload_we;
+wire [20:0] litedramcore_bankmachine6_sink_sink_payload_addr;
+wire litedramcore_bankmachine6_source_source_valid;
+wire litedramcore_bankmachine6_source_source_ready;
+wire litedramcore_bankmachine6_source_source_first;
+wire litedramcore_bankmachine6_source_source_last;
+wire litedramcore_bankmachine6_source_source_payload_we;
+wire [20:0] litedramcore_bankmachine6_source_source_payload_addr;
+wire litedramcore_bankmachine6_pipe_valid_sink_valid;
+wire litedramcore_bankmachine6_pipe_valid_sink_ready;
+wire litedramcore_bankmachine6_pipe_valid_sink_first;
+wire litedramcore_bankmachine6_pipe_valid_sink_last;
+wire litedramcore_bankmachine6_pipe_valid_sink_payload_we;
+wire [20:0] litedramcore_bankmachine6_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine6_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine6_pipe_valid_source_ready;
+reg litedramcore_bankmachine6_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine6_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine6_pipe_valid_source_payload_we = 1'd0;
+reg [20:0] litedramcore_bankmachine6_pipe_valid_source_payload_addr = 21'd0;
+reg [13:0] litedramcore_bankmachine6_row = 14'd0;
+reg litedramcore_bankmachine6_row_opened = 1'd0;
+wire litedramcore_bankmachine6_row_hit;
+reg litedramcore_bankmachine6_row_open = 1'd0;
+reg litedramcore_bankmachine6_row_close = 1'd0;
+reg litedramcore_bankmachine6_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine6_twtpcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine6_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine6_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine6_trccon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine6_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine6_trccon_count = 3'd0;
+wire litedramcore_bankmachine6_trascon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine6_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine6_trascon_count = 3'd0;
+wire litedramcore_bankmachine7_req_valid;
+wire litedramcore_bankmachine7_req_ready;
+wire litedramcore_bankmachine7_req_we;
+wire [20:0] litedramcore_bankmachine7_req_addr;
+wire litedramcore_bankmachine7_req_lock;
+reg litedramcore_bankmachine7_req_wdata_ready = 1'd0;
+reg litedramcore_bankmachine7_req_rdata_valid = 1'd0;
+wire litedramcore_bankmachine7_refresh_req;
+reg litedramcore_bankmachine7_refresh_gnt = 1'd0;
+reg litedramcore_bankmachine7_cmd_valid = 1'd0;
+reg litedramcore_bankmachine7_cmd_ready = 1'd0;
+reg [13:0] litedramcore_bankmachine7_cmd_payload_a = 14'd0;
+wire [2:0] litedramcore_bankmachine7_cmd_payload_ba;
+reg litedramcore_bankmachine7_cmd_payload_cas = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_ras = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_we = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_is_cmd = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_is_read = 1'd0;
+reg litedramcore_bankmachine7_cmd_payload_is_write = 1'd0;
+reg litedramcore_bankmachine7_auto_precharge = 1'd0;
+wire litedramcore_bankmachine7_sink_valid;
+wire litedramcore_bankmachine7_sink_ready;
+reg litedramcore_bankmachine7_sink_first = 1'd0;
+reg litedramcore_bankmachine7_sink_last = 1'd0;
+wire litedramcore_bankmachine7_sink_payload_we;
+wire [20:0] litedramcore_bankmachine7_sink_payload_addr;
+wire litedramcore_bankmachine7_source_valid;
+wire litedramcore_bankmachine7_source_ready;
+wire litedramcore_bankmachine7_source_first;
+wire litedramcore_bankmachine7_source_last;
+wire litedramcore_bankmachine7_source_payload_we;
+wire [20:0] litedramcore_bankmachine7_source_payload_addr;
+wire litedramcore_bankmachine7_syncfifo7_we;
+wire litedramcore_bankmachine7_syncfifo7_writable;
+wire litedramcore_bankmachine7_syncfifo7_re;
+wire litedramcore_bankmachine7_syncfifo7_readable;
+wire [23:0] litedramcore_bankmachine7_syncfifo7_din;
+wire [23:0] litedramcore_bankmachine7_syncfifo7_dout;
+reg [4:0] litedramcore_bankmachine7_level = 5'd0;
+reg litedramcore_bankmachine7_replace = 1'd0;
+reg [3:0] litedramcore_bankmachine7_produce = 4'd0;
+reg [3:0] litedramcore_bankmachine7_consume = 4'd0;
+reg [3:0] litedramcore_bankmachine7_wrport_adr = 4'd0;
+wire [23:0] litedramcore_bankmachine7_wrport_dat_r;
+wire litedramcore_bankmachine7_wrport_we;
+wire [23:0] litedramcore_bankmachine7_wrport_dat_w;
+wire litedramcore_bankmachine7_do_read;
+wire [3:0] litedramcore_bankmachine7_rdport_adr;
+wire [23:0] litedramcore_bankmachine7_rdport_dat_r;
+wire litedramcore_bankmachine7_fifo_in_payload_we;
+wire [20:0] litedramcore_bankmachine7_fifo_in_payload_addr;
+wire litedramcore_bankmachine7_fifo_in_first;
+wire litedramcore_bankmachine7_fifo_in_last;
+wire litedramcore_bankmachine7_fifo_out_payload_we;
+wire [20:0] litedramcore_bankmachine7_fifo_out_payload_addr;
+wire litedramcore_bankmachine7_fifo_out_first;
+wire litedramcore_bankmachine7_fifo_out_last;
+wire litedramcore_bankmachine7_sink_sink_valid;
+wire litedramcore_bankmachine7_sink_sink_ready;
+wire litedramcore_bankmachine7_sink_sink_first;
+wire litedramcore_bankmachine7_sink_sink_last;
+wire litedramcore_bankmachine7_sink_sink_payload_we;
+wire [20:0] litedramcore_bankmachine7_sink_sink_payload_addr;
+wire litedramcore_bankmachine7_source_source_valid;
+wire litedramcore_bankmachine7_source_source_ready;
+wire litedramcore_bankmachine7_source_source_first;
+wire litedramcore_bankmachine7_source_source_last;
+wire litedramcore_bankmachine7_source_source_payload_we;
+wire [20:0] litedramcore_bankmachine7_source_source_payload_addr;
+wire litedramcore_bankmachine7_pipe_valid_sink_valid;
+wire litedramcore_bankmachine7_pipe_valid_sink_ready;
+wire litedramcore_bankmachine7_pipe_valid_sink_first;
+wire litedramcore_bankmachine7_pipe_valid_sink_last;
+wire litedramcore_bankmachine7_pipe_valid_sink_payload_we;
+wire [20:0] litedramcore_bankmachine7_pipe_valid_sink_payload_addr;
+reg litedramcore_bankmachine7_pipe_valid_source_valid = 1'd0;
+wire litedramcore_bankmachine7_pipe_valid_source_ready;
+reg litedramcore_bankmachine7_pipe_valid_source_first = 1'd0;
+reg litedramcore_bankmachine7_pipe_valid_source_last = 1'd0;
+reg litedramcore_bankmachine7_pipe_valid_source_payload_we = 1'd0;
+reg [20:0] litedramcore_bankmachine7_pipe_valid_source_payload_addr = 21'd0;
+reg [13:0] litedramcore_bankmachine7_row = 14'd0;
+reg litedramcore_bankmachine7_row_opened = 1'd0;
+wire litedramcore_bankmachine7_row_hit;
+reg litedramcore_bankmachine7_row_open = 1'd0;
+reg litedramcore_bankmachine7_row_close = 1'd0;
+reg litedramcore_bankmachine7_row_col_n_addr_sel = 1'd0;
+wire litedramcore_bankmachine7_twtpcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine7_twtpcon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine7_twtpcon_count = 3'd0;
+wire litedramcore_bankmachine7_trccon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine7_trccon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine7_trccon_count = 3'd0;
+wire litedramcore_bankmachine7_trascon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_bankmachine7_trascon_ready = 1'd0;
+reg [2:0] litedramcore_bankmachine7_trascon_count = 3'd0;
+wire litedramcore_ras_allowed;
+wire litedramcore_cas_allowed;
+wire [1:0] litedramcore_rdcmdphase;
+wire [1:0] litedramcore_wrcmdphase;
+reg litedramcore_choose_cmd_want_reads = 1'd0;
+reg litedramcore_choose_cmd_want_writes = 1'd0;
+reg litedramcore_choose_cmd_want_cmds = 1'd0;
+reg litedramcore_choose_cmd_want_activates = 1'd0;
+wire litedramcore_choose_cmd_cmd_valid;
+reg litedramcore_choose_cmd_cmd_ready = 1'd0;
+wire [13:0] litedramcore_choose_cmd_cmd_payload_a;
+wire [2:0] litedramcore_choose_cmd_cmd_payload_ba;
+reg litedramcore_choose_cmd_cmd_payload_cas = 1'd0;
+reg litedramcore_choose_cmd_cmd_payload_ras = 1'd0;
+reg litedramcore_choose_cmd_cmd_payload_we = 1'd0;
+wire litedramcore_choose_cmd_cmd_payload_is_cmd;
+wire litedramcore_choose_cmd_cmd_payload_is_read;
+wire litedramcore_choose_cmd_cmd_payload_is_write;
+reg [7:0] litedramcore_choose_cmd_valids = 8'd0;
+wire [7:0] litedramcore_choose_cmd_request;
+reg [2:0] litedramcore_choose_cmd_grant = 3'd0;
+wire litedramcore_choose_cmd_ce;
+reg litedramcore_choose_req_want_reads = 1'd0;
+reg litedramcore_choose_req_want_writes = 1'd0;
+reg litedramcore_choose_req_want_cmds = 1'd0;
+reg litedramcore_choose_req_want_activates = 1'd0;
+wire litedramcore_choose_req_cmd_valid;
+reg litedramcore_choose_req_cmd_ready = 1'd0;
+wire [13:0] litedramcore_choose_req_cmd_payload_a;
+wire [2:0] litedramcore_choose_req_cmd_payload_ba;
+reg litedramcore_choose_req_cmd_payload_cas = 1'd0;
+reg litedramcore_choose_req_cmd_payload_ras = 1'd0;
+reg litedramcore_choose_req_cmd_payload_we = 1'd0;
+wire litedramcore_choose_req_cmd_payload_is_cmd;
+wire litedramcore_choose_req_cmd_payload_is_read;
+wire litedramcore_choose_req_cmd_payload_is_write;
+reg [7:0] litedramcore_choose_req_valids = 8'd0;
+wire [7:0] litedramcore_choose_req_request;
+reg [2:0] litedramcore_choose_req_grant = 3'd0;
+wire litedramcore_choose_req_ce;
+reg [13:0] litedramcore_nop_a = 14'd0;
+reg [2:0] litedramcore_nop_ba = 3'd0;
+reg [1:0] litedramcore_steerer_sel0 = 2'd0;
+reg [1:0] litedramcore_steerer_sel1 = 2'd0;
+reg [1:0] litedramcore_steerer_sel2 = 2'd0;
+reg [1:0] litedramcore_steerer_sel3 = 2'd0;
+reg litedramcore_steerer0 = 1'd1;
+reg litedramcore_steerer1 = 1'd1;
+reg litedramcore_steerer2 = 1'd1;
+reg litedramcore_steerer3 = 1'd1;
+reg litedramcore_steerer4 = 1'd1;
+reg litedramcore_steerer5 = 1'd1;
+reg litedramcore_steerer6 = 1'd1;
+reg litedramcore_steerer7 = 1'd1;
+wire litedramcore_trrdcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_trrdcon_ready = 1'd0;
+reg litedramcore_trrdcon_count = 1'd0;
+wire litedramcore_tfawcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_tfawcon_ready = 1'd1;
+wire [2:0] litedramcore_tfawcon_count;
+reg [4:0] litedramcore_tfawcon_window = 5'd0;
+wire litedramcore_tccdcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_tccdcon_ready = 1'd0;
+reg litedramcore_tccdcon_count = 1'd0;
+wire litedramcore_twtrcon_valid;
+(* dont_touch = "true" *)
+reg litedramcore_twtrcon_ready = 1'd0;
+reg [2:0] litedramcore_twtrcon_count = 3'd0;
+wire litedramcore_read_available;
+wire litedramcore_write_available;
+reg litedramcore_en0 = 1'd0;
+wire litedramcore_max_time0;
+reg [4:0] litedramcore_time0 = 5'd0;
+reg litedramcore_en1 = 1'd0;
+wire litedramcore_max_time1;
+reg [3:0] litedramcore_time1 = 4'd0;
+wire litedramcore_go_to_refresh;
+reg init_done_storage = 1'd0;
+reg init_done_re = 1'd0;
+reg init_error_storage = 1'd0;
+reg init_error_re = 1'd0;
+wire [29:0] wb_bus_adr;
+wire [31:0] wb_bus_dat_w;
+wire [31:0] wb_bus_dat_r;
+wire [3:0] wb_bus_sel;
+wire wb_bus_cyc;
+wire wb_bus_stb;
+wire wb_bus_ack;
+wire wb_bus_we;
+wire [2:0] wb_bus_cti;
+wire [1:0] wb_bus_bte;
+wire wb_bus_err;
+wire user_enable;
+wire user_port_cmd_valid;
+wire user_port_cmd_ready;
+wire user_port_cmd_payload_we;
+wire [23:0] user_port_cmd_payload_addr;
+wire user_port_wdata_valid;
+wire user_port_wdata_ready;
+wire [127:0] user_port_wdata_payload_data;
+wire [15:0] user_port_wdata_payload_we;
+wire user_port_rdata_valid;
+wire user_port_rdata_ready;
+wire [127:0] user_port_rdata_payload_data;
+reg [13:0] litedramcore_adr = 14'd0;
+reg litedramcore_we = 1'd0;
+reg [31:0] litedramcore_dat_w = 32'd0;
+wire [31:0] litedramcore_dat_r;
+wire [29:0] litedramcore_wishbone_adr;
+wire [31:0] litedramcore_wishbone_dat_w;
+reg [31:0] litedramcore_wishbone_dat_r = 32'd0;
+wire [3:0] litedramcore_wishbone_sel;
+wire litedramcore_wishbone_cyc;
+wire litedramcore_wishbone_stb;
+reg litedramcore_wishbone_ack = 1'd0;
+wire litedramcore_wishbone_we;
+wire [2:0] litedramcore_wishbone_cti;
+wire [1:0] litedramcore_wishbone_bte;
+reg litedramcore_wishbone_err = 1'd0;
+wire [13:0] interface0_bank_bus_adr;
+wire interface0_bank_bus_we;
+wire [31:0] interface0_bank_bus_dat_w;
+reg [31:0] interface0_bank_bus_dat_r = 32'd0;
+reg csrbank0_init_done0_re = 1'd0;
+wire csrbank0_init_done0_r;
+reg csrbank0_init_done0_we = 1'd0;
+wire csrbank0_init_done0_w;
+reg csrbank0_init_error0_re = 1'd0;
+wire csrbank0_init_error0_r;
+reg csrbank0_init_error0_we = 1'd0;
+wire csrbank0_init_error0_w;
+wire csrbank0_sel;
+wire [13:0] interface1_bank_bus_adr;
+wire interface1_bank_bus_we;
+wire [31:0] interface1_bank_bus_dat_w;
+reg [31:0] interface1_bank_bus_dat_r = 32'd0;
+reg csrbank1_rst0_re = 1'd0;
+wire csrbank1_rst0_r;
+reg csrbank1_rst0_we = 1'd0;
+wire csrbank1_rst0_w;
+reg csrbank1_dly_sel0_re = 1'd0;
+wire [1:0] csrbank1_dly_sel0_r;
+reg csrbank1_dly_sel0_we = 1'd0;
+wire [1:0] csrbank1_dly_sel0_w;
+reg csrbank1_half_sys8x_taps0_re = 1'd0;
+wire [4:0] csrbank1_half_sys8x_taps0_r;
+reg csrbank1_half_sys8x_taps0_we = 1'd0;
+wire [4:0] csrbank1_half_sys8x_taps0_w;
+reg csrbank1_wlevel_en0_re = 1'd0;
+wire csrbank1_wlevel_en0_r;
+reg csrbank1_wlevel_en0_we = 1'd0;
+wire csrbank1_wlevel_en0_w;
+reg csrbank1_rdphase0_re = 1'd0;
+wire [1:0] csrbank1_rdphase0_r;
+reg csrbank1_rdphase0_we = 1'd0;
+wire [1:0] csrbank1_rdphase0_w;
+reg csrbank1_wrphase0_re = 1'd0;
+wire [1:0] csrbank1_wrphase0_r;
+reg csrbank1_wrphase0_we = 1'd0;
+wire [1:0] csrbank1_wrphase0_w;
+wire csrbank1_sel;
+wire [13:0] interface2_bank_bus_adr;
+wire interface2_bank_bus_we;
+wire [31:0] interface2_bank_bus_dat_w;
+reg [31:0] interface2_bank_bus_dat_r = 32'd0;
+reg csrbank2_dfii_control0_re = 1'd0;
+wire [3:0] csrbank2_dfii_control0_r;
+reg csrbank2_dfii_control0_we = 1'd0;
+wire [3:0] csrbank2_dfii_control0_w;
+reg csrbank2_dfii_pi0_command0_re = 1'd0;
+wire [5:0] csrbank2_dfii_pi0_command0_r;
+reg csrbank2_dfii_pi0_command0_we = 1'd0;
+wire [5:0] csrbank2_dfii_pi0_command0_w;
+reg csrbank2_dfii_pi0_address0_re = 1'd0;
+wire [13:0] csrbank2_dfii_pi0_address0_r;
+reg csrbank2_dfii_pi0_address0_we = 1'd0;
+wire [13:0] csrbank2_dfii_pi0_address0_w;
+reg csrbank2_dfii_pi0_baddress0_re = 1'd0;
+wire [2:0] csrbank2_dfii_pi0_baddress0_r;
+reg csrbank2_dfii_pi0_baddress0_we = 1'd0;
+wire [2:0] csrbank2_dfii_pi0_baddress0_w;
+reg csrbank2_dfii_pi0_wrdata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_wrdata0_r;
+reg csrbank2_dfii_pi0_wrdata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_wrdata0_w;
+reg csrbank2_dfii_pi0_rddata_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_rddata_r;
+reg csrbank2_dfii_pi0_rddata_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi0_rddata_w;
+reg csrbank2_dfii_pi1_command0_re = 1'd0;
+wire [5:0] csrbank2_dfii_pi1_command0_r;
+reg csrbank2_dfii_pi1_command0_we = 1'd0;
+wire [5:0] csrbank2_dfii_pi1_command0_w;
+reg csrbank2_dfii_pi1_address0_re = 1'd0;
+wire [13:0] csrbank2_dfii_pi1_address0_r;
+reg csrbank2_dfii_pi1_address0_we = 1'd0;
+wire [13:0] csrbank2_dfii_pi1_address0_w;
+reg csrbank2_dfii_pi1_baddress0_re = 1'd0;
+wire [2:0] csrbank2_dfii_pi1_baddress0_r;
+reg csrbank2_dfii_pi1_baddress0_we = 1'd0;
+wire [2:0] csrbank2_dfii_pi1_baddress0_w;
+reg csrbank2_dfii_pi1_wrdata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_wrdata0_r;
+reg csrbank2_dfii_pi1_wrdata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_wrdata0_w;
+reg csrbank2_dfii_pi1_rddata_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_rddata_r;
+reg csrbank2_dfii_pi1_rddata_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi1_rddata_w;
+reg csrbank2_dfii_pi2_command0_re = 1'd0;
+wire [5:0] csrbank2_dfii_pi2_command0_r;
+reg csrbank2_dfii_pi2_command0_we = 1'd0;
+wire [5:0] csrbank2_dfii_pi2_command0_w;
+reg csrbank2_dfii_pi2_address0_re = 1'd0;
+wire [13:0] csrbank2_dfii_pi2_address0_r;
+reg csrbank2_dfii_pi2_address0_we = 1'd0;
+wire [13:0] csrbank2_dfii_pi2_address0_w;
+reg csrbank2_dfii_pi2_baddress0_re = 1'd0;
+wire [2:0] csrbank2_dfii_pi2_baddress0_r;
+reg csrbank2_dfii_pi2_baddress0_we = 1'd0;
+wire [2:0] csrbank2_dfii_pi2_baddress0_w;
+reg csrbank2_dfii_pi2_wrdata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_wrdata0_r;
+reg csrbank2_dfii_pi2_wrdata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_wrdata0_w;
+reg csrbank2_dfii_pi2_rddata_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_rddata_r;
+reg csrbank2_dfii_pi2_rddata_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi2_rddata_w;
+reg csrbank2_dfii_pi3_command0_re = 1'd0;
+wire [5:0] csrbank2_dfii_pi3_command0_r;
+reg csrbank2_dfii_pi3_command0_we = 1'd0;
+wire [5:0] csrbank2_dfii_pi3_command0_w;
+reg csrbank2_dfii_pi3_address0_re = 1'd0;
+wire [13:0] csrbank2_dfii_pi3_address0_r;
+reg csrbank2_dfii_pi3_address0_we = 1'd0;
+wire [13:0] csrbank2_dfii_pi3_address0_w;
+reg csrbank2_dfii_pi3_baddress0_re = 1'd0;
+wire [2:0] csrbank2_dfii_pi3_baddress0_r;
+reg csrbank2_dfii_pi3_baddress0_we = 1'd0;
+wire [2:0] csrbank2_dfii_pi3_baddress0_w;
+reg csrbank2_dfii_pi3_wrdata0_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_wrdata0_r;
+reg csrbank2_dfii_pi3_wrdata0_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_wrdata0_w;
+reg csrbank2_dfii_pi3_rddata_re = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_rddata_r;
+reg csrbank2_dfii_pi3_rddata_we = 1'd0;
+wire [31:0] csrbank2_dfii_pi3_rddata_w;
+wire csrbank2_sel;
+wire [13:0] csr_interconnect_adr;
+wire csr_interconnect_we;
+wire [31:0] csr_interconnect_dat_w;
+wire [31:0] csr_interconnect_dat_r;
+wire litedramcore_reset0;
+wire litedramcore_reset1;
+wire litedramcore_reset2;
+wire litedramcore_reset3;
+wire litedramcore_reset4;
+wire litedramcore_reset5;
+wire litedramcore_reset6;
+wire litedramcore_reset7;
+wire litedramcore_pll_fb;
+reg [1:0] litedramcore_refresher_state = 2'd0;
+reg [1:0] litedramcore_refresher_next_state = 2'd0;
+reg [3:0] litedramcore_bankmachine0_state = 4'd0;
+reg [3:0] litedramcore_bankmachine0_next_state = 4'd0;
+reg [3:0] litedramcore_bankmachine1_state = 4'd0;
+reg [3:0] litedramcore_bankmachine1_next_state = 4'd0;
+reg [3:0] litedramcore_bankmachine2_state = 4'd0;
+reg [3:0] litedramcore_bankmachine2_next_state = 4'd0;
+reg [3:0] litedramcore_bankmachine3_state = 4'd0;
+reg [3:0] litedramcore_bankmachine3_next_state = 4'd0;
+reg [3:0] litedramcore_bankmachine4_state = 4'd0;
+reg [3:0] litedramcore_bankmachine4_next_state = 4'd0;
+reg [3:0] litedramcore_bankmachine5_state = 4'd0;
+reg [3:0] litedramcore_bankmachine5_next_state = 4'd0;
+reg [3:0] litedramcore_bankmachine6_state = 4'd0;
+reg [3:0] litedramcore_bankmachine6_next_state = 4'd0;
+reg [3:0] litedramcore_bankmachine7_state = 4'd0;
+reg [3:0] litedramcore_bankmachine7_next_state = 4'd0;
+reg [3:0] litedramcore_multiplexer_state = 4'd0;
+reg [3:0] litedramcore_multiplexer_next_state = 4'd0;
+wire litedramcore_roundrobin0_request;
+wire litedramcore_roundrobin0_grant;
+wire litedramcore_roundrobin0_ce;
+wire litedramcore_roundrobin1_request;
+wire litedramcore_roundrobin1_grant;
+wire litedramcore_roundrobin1_ce;
+wire litedramcore_roundrobin2_request;
+wire litedramcore_roundrobin2_grant;
+wire litedramcore_roundrobin2_ce;
+wire litedramcore_roundrobin3_request;
+wire litedramcore_roundrobin3_grant;
+wire litedramcore_roundrobin3_ce;
+wire litedramcore_roundrobin4_request;
+wire litedramcore_roundrobin4_grant;
+wire litedramcore_roundrobin4_ce;
+wire litedramcore_roundrobin5_request;
+wire litedramcore_roundrobin5_grant;
+wire litedramcore_roundrobin5_ce;
+wire litedramcore_roundrobin6_request;
+wire litedramcore_roundrobin6_grant;
+wire litedramcore_roundrobin6_ce;
+wire litedramcore_roundrobin7_request;
+wire litedramcore_roundrobin7_grant;
+wire litedramcore_roundrobin7_ce;
+reg litedramcore_locked0 = 1'd0;
+reg litedramcore_locked1 = 1'd0;
+reg litedramcore_locked2 = 1'd0;
+reg litedramcore_locked3 = 1'd0;
+reg litedramcore_locked4 = 1'd0;
+reg litedramcore_locked5 = 1'd0;
+reg litedramcore_locked6 = 1'd0;
+reg litedramcore_locked7 = 1'd0;
+reg litedramcore_new_master_wdata_ready0 = 1'd0;
+reg litedramcore_new_master_wdata_ready1 = 1'd0;
+reg litedramcore_new_master_rdata_valid0 = 1'd0;
+reg litedramcore_new_master_rdata_valid1 = 1'd0;
+reg litedramcore_new_master_rdata_valid2 = 1'd0;
+reg litedramcore_new_master_rdata_valid3 = 1'd0;
+reg litedramcore_new_master_rdata_valid4 = 1'd0;
+reg litedramcore_new_master_rdata_valid5 = 1'd0;
+reg litedramcore_new_master_rdata_valid6 = 1'd0;
+reg litedramcore_new_master_rdata_valid7 = 1'd0;
+reg litedramcore_new_master_rdata_valid8 = 1'd0;
+reg [1:0] litedramcore_state = 2'd0;
+reg [1:0] litedramcore_next_state = 2'd0;
+reg [31:0] litedramcore_dat_w_next_value0 = 32'd0;
+reg litedramcore_dat_w_next_value_ce0 = 1'd0;
+reg [13:0] litedramcore_adr_next_value1 = 14'd0;
+reg litedramcore_adr_next_value_ce1 = 1'd0;
+reg litedramcore_we_next_value2 = 1'd0;
+reg litedramcore_we_next_value_ce2 = 1'd0;
+reg rhs_array_muxed0 = 1'd0;
+reg [13:0] rhs_array_muxed1 = 14'd0;
+reg [2:0] rhs_array_muxed2 = 3'd0;
+reg rhs_array_muxed3 = 1'd0;
+reg rhs_array_muxed4 = 1'd0;
+reg rhs_array_muxed5 = 1'd0;
+reg t_array_muxed0 = 1'd0;
+reg t_array_muxed1 = 1'd0;
+reg t_array_muxed2 = 1'd0;
+reg rhs_array_muxed6 = 1'd0;
+reg [13:0] rhs_array_muxed7 = 14'd0;
+reg [2:0] rhs_array_muxed8 = 3'd0;
+reg rhs_array_muxed9 = 1'd0;
+reg rhs_array_muxed10 = 1'd0;
+reg rhs_array_muxed11 = 1'd0;
+reg t_array_muxed3 = 1'd0;
+reg t_array_muxed4 = 1'd0;
+reg t_array_muxed5 = 1'd0;
+reg [20:0] rhs_array_muxed12 = 21'd0;
+reg rhs_array_muxed13 = 1'd0;
+reg rhs_array_muxed14 = 1'd0;
+reg [20:0] rhs_array_muxed15 = 21'd0;
+reg rhs_array_muxed16 = 1'd0;
+reg rhs_array_muxed17 = 1'd0;
+reg [20:0] rhs_array_muxed18 = 21'd0;
+reg rhs_array_muxed19 = 1'd0;
+reg rhs_array_muxed20 = 1'd0;
+reg [20:0] rhs_array_muxed21 = 21'd0;
+reg rhs_array_muxed22 = 1'd0;
+reg rhs_array_muxed23 = 1'd0;
+reg [20:0] rhs_array_muxed24 = 21'd0;
+reg rhs_array_muxed25 = 1'd0;
+reg rhs_array_muxed26 = 1'd0;
+reg [20:0] rhs_array_muxed27 = 21'd0;
+reg rhs_array_muxed28 = 1'd0;
+reg rhs_array_muxed29 = 1'd0;
+reg [20:0] rhs_array_muxed30 = 21'd0;
+reg rhs_array_muxed31 = 1'd0;
+reg rhs_array_muxed32 = 1'd0;
+reg [20:0] rhs_array_muxed33 = 21'd0;
+reg rhs_array_muxed34 = 1'd0;
+reg rhs_array_muxed35 = 1'd0;
+reg [2:0] array_muxed0 = 3'd0;
+reg [13:0] array_muxed1 = 14'd0;
+reg array_muxed2 = 1'd0;
+reg array_muxed3 = 1'd0;
+reg array_muxed4 = 1'd0;
+reg array_muxed5 = 1'd0;
+reg array_muxed6 = 1'd0;
+reg [2:0] array_muxed7 = 3'd0;
+reg [13:0] array_muxed8 = 14'd0;
+reg array_muxed9 = 1'd0;
+reg array_muxed10 = 1'd0;
+reg array_muxed11 = 1'd0;
+reg array_muxed12 = 1'd0;
+reg array_muxed13 = 1'd0;
+reg [2:0] array_muxed14 = 3'd0;
+reg [13:0] array_muxed15 = 14'd0;
+reg array_muxed16 = 1'd0;
+reg array_muxed17 = 1'd0;
+reg array_muxed18 = 1'd0;
+reg array_muxed19 = 1'd0;
+reg array_muxed20 = 1'd0;
+reg [2:0] array_muxed21 = 3'd0;
+reg [13:0] array_muxed22 = 14'd0;
+reg array_muxed23 = 1'd0;
+reg array_muxed24 = 1'd0;
+reg array_muxed25 = 1'd0;
+reg array_muxed26 = 1'd0;
+reg array_muxed27 = 1'd0;
+wire xilinxasyncresetsynchronizerimpl0;
+wire xilinxasyncresetsynchronizerimpl0_rst_meta;
+wire xilinxasyncresetsynchronizerimpl1;
+wire xilinxasyncresetsynchronizerimpl1_rst_meta;
+wire xilinxasyncresetsynchronizerimpl2;
+wire xilinxasyncresetsynchronizerimpl2_rst_meta;
+wire xilinxasyncresetsynchronizerimpl2_expr;
+wire xilinxasyncresetsynchronizerimpl3;
+wire xilinxasyncresetsynchronizerimpl3_rst_meta;
+wire xilinxasyncresetsynchronizerimpl3_expr;
//------------------------------------------------------------------------------
// Combinatorial Logic
assign a7ddrphy_dqs_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dqs_oe) | a7ddrphy_dqs_postamble);
assign a7ddrphy_dq_oe_delay_tappeddelayline = ((a7ddrphy_dqs_preamble | a7ddrphy_dq_oe) | a7ddrphy_dqs_postamble);
always @(*) begin
- a7ddrphy_dfi_p0_rddata <= 32'd0;
- a7ddrphy_dfi_p0_rddata[0] <= a7ddrphy_bitslip04[0];
- a7ddrphy_dfi_p0_rddata[16] <= a7ddrphy_bitslip04[1];
- a7ddrphy_dfi_p0_rddata[1] <= a7ddrphy_bitslip14[0];
- a7ddrphy_dfi_p0_rddata[17] <= a7ddrphy_bitslip14[1];
- a7ddrphy_dfi_p0_rddata[2] <= a7ddrphy_bitslip22[0];
- a7ddrphy_dfi_p0_rddata[18] <= a7ddrphy_bitslip22[1];
- a7ddrphy_dfi_p0_rddata[3] <= a7ddrphy_bitslip32[0];
- a7ddrphy_dfi_p0_rddata[19] <= a7ddrphy_bitslip32[1];
- a7ddrphy_dfi_p0_rddata[4] <= a7ddrphy_bitslip42[0];
- a7ddrphy_dfi_p0_rddata[20] <= a7ddrphy_bitslip42[1];
- a7ddrphy_dfi_p0_rddata[5] <= a7ddrphy_bitslip52[0];
- a7ddrphy_dfi_p0_rddata[21] <= a7ddrphy_bitslip52[1];
- a7ddrphy_dfi_p0_rddata[6] <= a7ddrphy_bitslip62[0];
- a7ddrphy_dfi_p0_rddata[22] <= a7ddrphy_bitslip62[1];
- a7ddrphy_dfi_p0_rddata[7] <= a7ddrphy_bitslip72[0];
- a7ddrphy_dfi_p0_rddata[23] <= a7ddrphy_bitslip72[1];
- a7ddrphy_dfi_p0_rddata[8] <= a7ddrphy_bitslip82[0];
- a7ddrphy_dfi_p0_rddata[24] <= a7ddrphy_bitslip82[1];
- a7ddrphy_dfi_p0_rddata[9] <= a7ddrphy_bitslip92[0];
- a7ddrphy_dfi_p0_rddata[25] <= a7ddrphy_bitslip92[1];
- a7ddrphy_dfi_p0_rddata[10] <= a7ddrphy_bitslip102[0];
- a7ddrphy_dfi_p0_rddata[26] <= a7ddrphy_bitslip102[1];
- a7ddrphy_dfi_p0_rddata[11] <= a7ddrphy_bitslip112[0];
- a7ddrphy_dfi_p0_rddata[27] <= a7ddrphy_bitslip112[1];
- a7ddrphy_dfi_p0_rddata[12] <= a7ddrphy_bitslip122[0];
- a7ddrphy_dfi_p0_rddata[28] <= a7ddrphy_bitslip122[1];
- a7ddrphy_dfi_p0_rddata[13] <= a7ddrphy_bitslip132[0];
- a7ddrphy_dfi_p0_rddata[29] <= a7ddrphy_bitslip132[1];
- a7ddrphy_dfi_p0_rddata[14] <= a7ddrphy_bitslip142[0];
- a7ddrphy_dfi_p0_rddata[30] <= a7ddrphy_bitslip142[1];
- a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip152[0];
- a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip152[1];
-end
-always @(*) begin
- a7ddrphy_dfi_p1_rddata <= 32'd0;
- a7ddrphy_dfi_p1_rddata[0] <= a7ddrphy_bitslip04[2];
- a7ddrphy_dfi_p1_rddata[16] <= a7ddrphy_bitslip04[3];
- a7ddrphy_dfi_p1_rddata[1] <= a7ddrphy_bitslip14[2];
- a7ddrphy_dfi_p1_rddata[17] <= a7ddrphy_bitslip14[3];
- a7ddrphy_dfi_p1_rddata[2] <= a7ddrphy_bitslip22[2];
- a7ddrphy_dfi_p1_rddata[18] <= a7ddrphy_bitslip22[3];
- a7ddrphy_dfi_p1_rddata[3] <= a7ddrphy_bitslip32[2];
- a7ddrphy_dfi_p1_rddata[19] <= a7ddrphy_bitslip32[3];
- a7ddrphy_dfi_p1_rddata[4] <= a7ddrphy_bitslip42[2];
- a7ddrphy_dfi_p1_rddata[20] <= a7ddrphy_bitslip42[3];
- a7ddrphy_dfi_p1_rddata[5] <= a7ddrphy_bitslip52[2];
- a7ddrphy_dfi_p1_rddata[21] <= a7ddrphy_bitslip52[3];
- a7ddrphy_dfi_p1_rddata[6] <= a7ddrphy_bitslip62[2];
- a7ddrphy_dfi_p1_rddata[22] <= a7ddrphy_bitslip62[3];
- a7ddrphy_dfi_p1_rddata[7] <= a7ddrphy_bitslip72[2];
- a7ddrphy_dfi_p1_rddata[23] <= a7ddrphy_bitslip72[3];
- a7ddrphy_dfi_p1_rddata[8] <= a7ddrphy_bitslip82[2];
- a7ddrphy_dfi_p1_rddata[24] <= a7ddrphy_bitslip82[3];
- a7ddrphy_dfi_p1_rddata[9] <= a7ddrphy_bitslip92[2];
- a7ddrphy_dfi_p1_rddata[25] <= a7ddrphy_bitslip92[3];
- a7ddrphy_dfi_p1_rddata[10] <= a7ddrphy_bitslip102[2];
- a7ddrphy_dfi_p1_rddata[26] <= a7ddrphy_bitslip102[3];
- a7ddrphy_dfi_p1_rddata[11] <= a7ddrphy_bitslip112[2];
- a7ddrphy_dfi_p1_rddata[27] <= a7ddrphy_bitslip112[3];
- a7ddrphy_dfi_p1_rddata[12] <= a7ddrphy_bitslip122[2];
- a7ddrphy_dfi_p1_rddata[28] <= a7ddrphy_bitslip122[3];
- a7ddrphy_dfi_p1_rddata[13] <= a7ddrphy_bitslip132[2];
- a7ddrphy_dfi_p1_rddata[29] <= a7ddrphy_bitslip132[3];
- a7ddrphy_dfi_p1_rddata[14] <= a7ddrphy_bitslip142[2];
- a7ddrphy_dfi_p1_rddata[30] <= a7ddrphy_bitslip142[3];
- a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip152[2];
- a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip152[3];
-end
-always @(*) begin
- a7ddrphy_dfi_p2_rddata <= 32'd0;
- a7ddrphy_dfi_p2_rddata[0] <= a7ddrphy_bitslip04[4];
- a7ddrphy_dfi_p2_rddata[16] <= a7ddrphy_bitslip04[5];
- a7ddrphy_dfi_p2_rddata[1] <= a7ddrphy_bitslip14[4];
- a7ddrphy_dfi_p2_rddata[17] <= a7ddrphy_bitslip14[5];
- a7ddrphy_dfi_p2_rddata[2] <= a7ddrphy_bitslip22[4];
- a7ddrphy_dfi_p2_rddata[18] <= a7ddrphy_bitslip22[5];
- a7ddrphy_dfi_p2_rddata[3] <= a7ddrphy_bitslip32[4];
- a7ddrphy_dfi_p2_rddata[19] <= a7ddrphy_bitslip32[5];
- a7ddrphy_dfi_p2_rddata[4] <= a7ddrphy_bitslip42[4];
- a7ddrphy_dfi_p2_rddata[20] <= a7ddrphy_bitslip42[5];
- a7ddrphy_dfi_p2_rddata[5] <= a7ddrphy_bitslip52[4];
- a7ddrphy_dfi_p2_rddata[21] <= a7ddrphy_bitslip52[5];
- a7ddrphy_dfi_p2_rddata[6] <= a7ddrphy_bitslip62[4];
- a7ddrphy_dfi_p2_rddata[22] <= a7ddrphy_bitslip62[5];
- a7ddrphy_dfi_p2_rddata[7] <= a7ddrphy_bitslip72[4];
- a7ddrphy_dfi_p2_rddata[23] <= a7ddrphy_bitslip72[5];
- a7ddrphy_dfi_p2_rddata[8] <= a7ddrphy_bitslip82[4];
- a7ddrphy_dfi_p2_rddata[24] <= a7ddrphy_bitslip82[5];
- a7ddrphy_dfi_p2_rddata[9] <= a7ddrphy_bitslip92[4];
- a7ddrphy_dfi_p2_rddata[25] <= a7ddrphy_bitslip92[5];
- a7ddrphy_dfi_p2_rddata[10] <= a7ddrphy_bitslip102[4];
- a7ddrphy_dfi_p2_rddata[26] <= a7ddrphy_bitslip102[5];
- a7ddrphy_dfi_p2_rddata[11] <= a7ddrphy_bitslip112[4];
- a7ddrphy_dfi_p2_rddata[27] <= a7ddrphy_bitslip112[5];
- a7ddrphy_dfi_p2_rddata[12] <= a7ddrphy_bitslip122[4];
- a7ddrphy_dfi_p2_rddata[28] <= a7ddrphy_bitslip122[5];
- a7ddrphy_dfi_p2_rddata[13] <= a7ddrphy_bitslip132[4];
- a7ddrphy_dfi_p2_rddata[29] <= a7ddrphy_bitslip132[5];
- a7ddrphy_dfi_p2_rddata[14] <= a7ddrphy_bitslip142[4];
- a7ddrphy_dfi_p2_rddata[30] <= a7ddrphy_bitslip142[5];
- a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip152[4];
- a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip152[5];
-end
-always @(*) begin
- a7ddrphy_dfi_p3_rddata <= 32'd0;
- a7ddrphy_dfi_p3_rddata[0] <= a7ddrphy_bitslip04[6];
- a7ddrphy_dfi_p3_rddata[16] <= a7ddrphy_bitslip04[7];
- a7ddrphy_dfi_p3_rddata[1] <= a7ddrphy_bitslip14[6];
- a7ddrphy_dfi_p3_rddata[17] <= a7ddrphy_bitslip14[7];
- a7ddrphy_dfi_p3_rddata[2] <= a7ddrphy_bitslip22[6];
- a7ddrphy_dfi_p3_rddata[18] <= a7ddrphy_bitslip22[7];
- a7ddrphy_dfi_p3_rddata[3] <= a7ddrphy_bitslip32[6];
- a7ddrphy_dfi_p3_rddata[19] <= a7ddrphy_bitslip32[7];
- a7ddrphy_dfi_p3_rddata[4] <= a7ddrphy_bitslip42[6];
- a7ddrphy_dfi_p3_rddata[20] <= a7ddrphy_bitslip42[7];
- a7ddrphy_dfi_p3_rddata[5] <= a7ddrphy_bitslip52[6];
- a7ddrphy_dfi_p3_rddata[21] <= a7ddrphy_bitslip52[7];
- a7ddrphy_dfi_p3_rddata[6] <= a7ddrphy_bitslip62[6];
- a7ddrphy_dfi_p3_rddata[22] <= a7ddrphy_bitslip62[7];
- a7ddrphy_dfi_p3_rddata[7] <= a7ddrphy_bitslip72[6];
- a7ddrphy_dfi_p3_rddata[23] <= a7ddrphy_bitslip72[7];
- a7ddrphy_dfi_p3_rddata[8] <= a7ddrphy_bitslip82[6];
- a7ddrphy_dfi_p3_rddata[24] <= a7ddrphy_bitslip82[7];
- a7ddrphy_dfi_p3_rddata[9] <= a7ddrphy_bitslip92[6];
- a7ddrphy_dfi_p3_rddata[25] <= a7ddrphy_bitslip92[7];
- a7ddrphy_dfi_p3_rddata[10] <= a7ddrphy_bitslip102[6];
- a7ddrphy_dfi_p3_rddata[26] <= a7ddrphy_bitslip102[7];
- a7ddrphy_dfi_p3_rddata[11] <= a7ddrphy_bitslip112[6];
- a7ddrphy_dfi_p3_rddata[27] <= a7ddrphy_bitslip112[7];
- a7ddrphy_dfi_p3_rddata[12] <= a7ddrphy_bitslip122[6];
- a7ddrphy_dfi_p3_rddata[28] <= a7ddrphy_bitslip122[7];
- a7ddrphy_dfi_p3_rddata[13] <= a7ddrphy_bitslip132[6];
- a7ddrphy_dfi_p3_rddata[29] <= a7ddrphy_bitslip132[7];
- a7ddrphy_dfi_p3_rddata[14] <= a7ddrphy_bitslip142[6];
- a7ddrphy_dfi_p3_rddata[30] <= a7ddrphy_bitslip142[7];
- a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip152[6];
- a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip152[7];
+ a7ddrphy_dfi_p0_rddata <= 32'd0;
+ a7ddrphy_dfi_p0_rddata[0] <= a7ddrphy_bitslip04[0];
+ a7ddrphy_dfi_p0_rddata[16] <= a7ddrphy_bitslip04[1];
+ a7ddrphy_dfi_p0_rddata[1] <= a7ddrphy_bitslip14[0];
+ a7ddrphy_dfi_p0_rddata[17] <= a7ddrphy_bitslip14[1];
+ a7ddrphy_dfi_p0_rddata[2] <= a7ddrphy_bitslip22[0];
+ a7ddrphy_dfi_p0_rddata[18] <= a7ddrphy_bitslip22[1];
+ a7ddrphy_dfi_p0_rddata[3] <= a7ddrphy_bitslip32[0];
+ a7ddrphy_dfi_p0_rddata[19] <= a7ddrphy_bitslip32[1];
+ a7ddrphy_dfi_p0_rddata[4] <= a7ddrphy_bitslip42[0];
+ a7ddrphy_dfi_p0_rddata[20] <= a7ddrphy_bitslip42[1];
+ a7ddrphy_dfi_p0_rddata[5] <= a7ddrphy_bitslip52[0];
+ a7ddrphy_dfi_p0_rddata[21] <= a7ddrphy_bitslip52[1];
+ a7ddrphy_dfi_p0_rddata[6] <= a7ddrphy_bitslip62[0];
+ a7ddrphy_dfi_p0_rddata[22] <= a7ddrphy_bitslip62[1];
+ a7ddrphy_dfi_p0_rddata[7] <= a7ddrphy_bitslip72[0];
+ a7ddrphy_dfi_p0_rddata[23] <= a7ddrphy_bitslip72[1];
+ a7ddrphy_dfi_p0_rddata[8] <= a7ddrphy_bitslip82[0];
+ a7ddrphy_dfi_p0_rddata[24] <= a7ddrphy_bitslip82[1];
+ a7ddrphy_dfi_p0_rddata[9] <= a7ddrphy_bitslip92[0];
+ a7ddrphy_dfi_p0_rddata[25] <= a7ddrphy_bitslip92[1];
+ a7ddrphy_dfi_p0_rddata[10] <= a7ddrphy_bitslip102[0];
+ a7ddrphy_dfi_p0_rddata[26] <= a7ddrphy_bitslip102[1];
+ a7ddrphy_dfi_p0_rddata[11] <= a7ddrphy_bitslip112[0];
+ a7ddrphy_dfi_p0_rddata[27] <= a7ddrphy_bitslip112[1];
+ a7ddrphy_dfi_p0_rddata[12] <= a7ddrphy_bitslip122[0];
+ a7ddrphy_dfi_p0_rddata[28] <= a7ddrphy_bitslip122[1];
+ a7ddrphy_dfi_p0_rddata[13] <= a7ddrphy_bitslip132[0];
+ a7ddrphy_dfi_p0_rddata[29] <= a7ddrphy_bitslip132[1];
+ a7ddrphy_dfi_p0_rddata[14] <= a7ddrphy_bitslip142[0];
+ a7ddrphy_dfi_p0_rddata[30] <= a7ddrphy_bitslip142[1];
+ a7ddrphy_dfi_p0_rddata[15] <= a7ddrphy_bitslip152[0];
+ a7ddrphy_dfi_p0_rddata[31] <= a7ddrphy_bitslip152[1];
+end
+always @(*) begin
+ a7ddrphy_dfi_p1_rddata <= 32'd0;
+ a7ddrphy_dfi_p1_rddata[0] <= a7ddrphy_bitslip04[2];
+ a7ddrphy_dfi_p1_rddata[16] <= a7ddrphy_bitslip04[3];
+ a7ddrphy_dfi_p1_rddata[1] <= a7ddrphy_bitslip14[2];
+ a7ddrphy_dfi_p1_rddata[17] <= a7ddrphy_bitslip14[3];
+ a7ddrphy_dfi_p1_rddata[2] <= a7ddrphy_bitslip22[2];
+ a7ddrphy_dfi_p1_rddata[18] <= a7ddrphy_bitslip22[3];
+ a7ddrphy_dfi_p1_rddata[3] <= a7ddrphy_bitslip32[2];
+ a7ddrphy_dfi_p1_rddata[19] <= a7ddrphy_bitslip32[3];
+ a7ddrphy_dfi_p1_rddata[4] <= a7ddrphy_bitslip42[2];
+ a7ddrphy_dfi_p1_rddata[20] <= a7ddrphy_bitslip42[3];
+ a7ddrphy_dfi_p1_rddata[5] <= a7ddrphy_bitslip52[2];
+ a7ddrphy_dfi_p1_rddata[21] <= a7ddrphy_bitslip52[3];
+ a7ddrphy_dfi_p1_rddata[6] <= a7ddrphy_bitslip62[2];
+ a7ddrphy_dfi_p1_rddata[22] <= a7ddrphy_bitslip62[3];
+ a7ddrphy_dfi_p1_rddata[7] <= a7ddrphy_bitslip72[2];
+ a7ddrphy_dfi_p1_rddata[23] <= a7ddrphy_bitslip72[3];
+ a7ddrphy_dfi_p1_rddata[8] <= a7ddrphy_bitslip82[2];
+ a7ddrphy_dfi_p1_rddata[24] <= a7ddrphy_bitslip82[3];
+ a7ddrphy_dfi_p1_rddata[9] <= a7ddrphy_bitslip92[2];
+ a7ddrphy_dfi_p1_rddata[25] <= a7ddrphy_bitslip92[3];
+ a7ddrphy_dfi_p1_rddata[10] <= a7ddrphy_bitslip102[2];
+ a7ddrphy_dfi_p1_rddata[26] <= a7ddrphy_bitslip102[3];
+ a7ddrphy_dfi_p1_rddata[11] <= a7ddrphy_bitslip112[2];
+ a7ddrphy_dfi_p1_rddata[27] <= a7ddrphy_bitslip112[3];
+ a7ddrphy_dfi_p1_rddata[12] <= a7ddrphy_bitslip122[2];
+ a7ddrphy_dfi_p1_rddata[28] <= a7ddrphy_bitslip122[3];
+ a7ddrphy_dfi_p1_rddata[13] <= a7ddrphy_bitslip132[2];
+ a7ddrphy_dfi_p1_rddata[29] <= a7ddrphy_bitslip132[3];
+ a7ddrphy_dfi_p1_rddata[14] <= a7ddrphy_bitslip142[2];
+ a7ddrphy_dfi_p1_rddata[30] <= a7ddrphy_bitslip142[3];
+ a7ddrphy_dfi_p1_rddata[15] <= a7ddrphy_bitslip152[2];
+ a7ddrphy_dfi_p1_rddata[31] <= a7ddrphy_bitslip152[3];
+end
+always @(*) begin
+ a7ddrphy_dfi_p2_rddata <= 32'd0;
+ a7ddrphy_dfi_p2_rddata[0] <= a7ddrphy_bitslip04[4];
+ a7ddrphy_dfi_p2_rddata[16] <= a7ddrphy_bitslip04[5];
+ a7ddrphy_dfi_p2_rddata[1] <= a7ddrphy_bitslip14[4];
+ a7ddrphy_dfi_p2_rddata[17] <= a7ddrphy_bitslip14[5];
+ a7ddrphy_dfi_p2_rddata[2] <= a7ddrphy_bitslip22[4];
+ a7ddrphy_dfi_p2_rddata[18] <= a7ddrphy_bitslip22[5];
+ a7ddrphy_dfi_p2_rddata[3] <= a7ddrphy_bitslip32[4];
+ a7ddrphy_dfi_p2_rddata[19] <= a7ddrphy_bitslip32[5];
+ a7ddrphy_dfi_p2_rddata[4] <= a7ddrphy_bitslip42[4];
+ a7ddrphy_dfi_p2_rddata[20] <= a7ddrphy_bitslip42[5];
+ a7ddrphy_dfi_p2_rddata[5] <= a7ddrphy_bitslip52[4];
+ a7ddrphy_dfi_p2_rddata[21] <= a7ddrphy_bitslip52[5];
+ a7ddrphy_dfi_p2_rddata[6] <= a7ddrphy_bitslip62[4];
+ a7ddrphy_dfi_p2_rddata[22] <= a7ddrphy_bitslip62[5];
+ a7ddrphy_dfi_p2_rddata[7] <= a7ddrphy_bitslip72[4];
+ a7ddrphy_dfi_p2_rddata[23] <= a7ddrphy_bitslip72[5];
+ a7ddrphy_dfi_p2_rddata[8] <= a7ddrphy_bitslip82[4];
+ a7ddrphy_dfi_p2_rddata[24] <= a7ddrphy_bitslip82[5];
+ a7ddrphy_dfi_p2_rddata[9] <= a7ddrphy_bitslip92[4];
+ a7ddrphy_dfi_p2_rddata[25] <= a7ddrphy_bitslip92[5];
+ a7ddrphy_dfi_p2_rddata[10] <= a7ddrphy_bitslip102[4];
+ a7ddrphy_dfi_p2_rddata[26] <= a7ddrphy_bitslip102[5];
+ a7ddrphy_dfi_p2_rddata[11] <= a7ddrphy_bitslip112[4];
+ a7ddrphy_dfi_p2_rddata[27] <= a7ddrphy_bitslip112[5];
+ a7ddrphy_dfi_p2_rddata[12] <= a7ddrphy_bitslip122[4];
+ a7ddrphy_dfi_p2_rddata[28] <= a7ddrphy_bitslip122[5];
+ a7ddrphy_dfi_p2_rddata[13] <= a7ddrphy_bitslip132[4];
+ a7ddrphy_dfi_p2_rddata[29] <= a7ddrphy_bitslip132[5];
+ a7ddrphy_dfi_p2_rddata[14] <= a7ddrphy_bitslip142[4];
+ a7ddrphy_dfi_p2_rddata[30] <= a7ddrphy_bitslip142[5];
+ a7ddrphy_dfi_p2_rddata[15] <= a7ddrphy_bitslip152[4];
+ a7ddrphy_dfi_p2_rddata[31] <= a7ddrphy_bitslip152[5];
+end
+always @(*) begin
+ a7ddrphy_dfi_p3_rddata <= 32'd0;
+ a7ddrphy_dfi_p3_rddata[0] <= a7ddrphy_bitslip04[6];
+ a7ddrphy_dfi_p3_rddata[16] <= a7ddrphy_bitslip04[7];
+ a7ddrphy_dfi_p3_rddata[1] <= a7ddrphy_bitslip14[6];
+ a7ddrphy_dfi_p3_rddata[17] <= a7ddrphy_bitslip14[7];
+ a7ddrphy_dfi_p3_rddata[2] <= a7ddrphy_bitslip22[6];
+ a7ddrphy_dfi_p3_rddata[18] <= a7ddrphy_bitslip22[7];
+ a7ddrphy_dfi_p3_rddata[3] <= a7ddrphy_bitslip32[6];
+ a7ddrphy_dfi_p3_rddata[19] <= a7ddrphy_bitslip32[7];
+ a7ddrphy_dfi_p3_rddata[4] <= a7ddrphy_bitslip42[6];
+ a7ddrphy_dfi_p3_rddata[20] <= a7ddrphy_bitslip42[7];
+ a7ddrphy_dfi_p3_rddata[5] <= a7ddrphy_bitslip52[6];
+ a7ddrphy_dfi_p3_rddata[21] <= a7ddrphy_bitslip52[7];
+ a7ddrphy_dfi_p3_rddata[6] <= a7ddrphy_bitslip62[6];
+ a7ddrphy_dfi_p3_rddata[22] <= a7ddrphy_bitslip62[7];
+ a7ddrphy_dfi_p3_rddata[7] <= a7ddrphy_bitslip72[6];
+ a7ddrphy_dfi_p3_rddata[23] <= a7ddrphy_bitslip72[7];
+ a7ddrphy_dfi_p3_rddata[8] <= a7ddrphy_bitslip82[6];
+ a7ddrphy_dfi_p3_rddata[24] <= a7ddrphy_bitslip82[7];
+ a7ddrphy_dfi_p3_rddata[9] <= a7ddrphy_bitslip92[6];
+ a7ddrphy_dfi_p3_rddata[25] <= a7ddrphy_bitslip92[7];
+ a7ddrphy_dfi_p3_rddata[10] <= a7ddrphy_bitslip102[6];
+ a7ddrphy_dfi_p3_rddata[26] <= a7ddrphy_bitslip102[7];
+ a7ddrphy_dfi_p3_rddata[11] <= a7ddrphy_bitslip112[6];
+ a7ddrphy_dfi_p3_rddata[27] <= a7ddrphy_bitslip112[7];
+ a7ddrphy_dfi_p3_rddata[12] <= a7ddrphy_bitslip122[6];
+ a7ddrphy_dfi_p3_rddata[28] <= a7ddrphy_bitslip122[7];
+ a7ddrphy_dfi_p3_rddata[13] <= a7ddrphy_bitslip132[6];
+ a7ddrphy_dfi_p3_rddata[29] <= a7ddrphy_bitslip132[7];
+ a7ddrphy_dfi_p3_rddata[14] <= a7ddrphy_bitslip142[6];
+ a7ddrphy_dfi_p3_rddata[30] <= a7ddrphy_bitslip142[7];
+ a7ddrphy_dfi_p3_rddata[15] <= a7ddrphy_bitslip152[6];
+ a7ddrphy_dfi_p3_rddata[31] <= a7ddrphy_bitslip152[7];
end
assign a7ddrphy_dfi_p0_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage);
assign a7ddrphy_dfi_p1_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage);
assign a7ddrphy_dfi_p3_rddata_valid = (a7ddrphy_rddata_en_tappeddelayline7 | a7ddrphy_wlevel_en_storage);
assign a7ddrphy_dq_oe = a7ddrphy_wrdata_en_tappeddelayline1;
always @(*) begin
- a7ddrphy_dqs_oe <= 1'd0;
- if (a7ddrphy_wlevel_en_storage) begin
- a7ddrphy_dqs_oe <= 1'd1;
- end else begin
- a7ddrphy_dqs_oe <= a7ddrphy_dq_oe;
- end
+ a7ddrphy_dqs_oe <= 1'd0;
+ if (a7ddrphy_wlevel_en_storage) begin
+ a7ddrphy_dqs_oe <= 1'd1;
+ end else begin
+ a7ddrphy_dqs_oe <= a7ddrphy_dq_oe;
+ end
end
assign a7ddrphy_dqs_preamble = (a7ddrphy_wrdata_en_tappeddelayline0 & (~a7ddrphy_wrdata_en_tappeddelayline1));
assign a7ddrphy_dqs_postamble = (a7ddrphy_wrdata_en_tappeddelayline2 & (~a7ddrphy_wrdata_en_tappeddelayline1));
always @(*) begin
- a7ddrphy_dqspattern_o0 <= 8'd0;
- a7ddrphy_dqspattern_o0 <= 7'd85;
- if (a7ddrphy_dqspattern0) begin
- a7ddrphy_dqspattern_o0 <= 5'd21;
- end
- if (a7ddrphy_dqspattern1) begin
- a7ddrphy_dqspattern_o0 <= 7'd84;
- end
- if (a7ddrphy_wlevel_en_storage) begin
- a7ddrphy_dqspattern_o0 <= 1'd0;
- if (a7ddrphy_wlevel_strobe_re) begin
- a7ddrphy_dqspattern_o0 <= 1'd1;
- end
- end
-end
-always @(*) begin
- a7ddrphy_bitslip00 <= 8'd0;
- case (a7ddrphy_bitslip0_value0)
- 1'd0: begin
- a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip10 <= 8'd0;
- case (a7ddrphy_bitslip1_value0)
- 1'd0: begin
- a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip01 <= 8'd0;
- case (a7ddrphy_bitslip0_value1)
- 1'd0: begin
- a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip11 <= 8'd0;
- case (a7ddrphy_bitslip1_value1)
- 1'd0: begin
- a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip02 <= 8'd0;
- case (a7ddrphy_bitslip0_value2)
- 1'd0: begin
- a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip04 <= 8'd0;
- case (a7ddrphy_bitslip0_value3)
- 1'd0: begin
- a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip12 <= 8'd0;
- case (a7ddrphy_bitslip1_value2)
- 1'd0: begin
- a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip14 <= 8'd0;
- case (a7ddrphy_bitslip1_value3)
- 1'd0: begin
- a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip20 <= 8'd0;
- case (a7ddrphy_bitslip2_value0)
- 1'd0: begin
- a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip22 <= 8'd0;
- case (a7ddrphy_bitslip2_value1)
- 1'd0: begin
- a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip30 <= 8'd0;
- case (a7ddrphy_bitslip3_value0)
- 1'd0: begin
- a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip32 <= 8'd0;
- case (a7ddrphy_bitslip3_value1)
- 1'd0: begin
- a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip40 <= 8'd0;
- case (a7ddrphy_bitslip4_value0)
- 1'd0: begin
- a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip42 <= 8'd0;
- case (a7ddrphy_bitslip4_value1)
- 1'd0: begin
- a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip50 <= 8'd0;
- case (a7ddrphy_bitslip5_value0)
- 1'd0: begin
- a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip52 <= 8'd0;
- case (a7ddrphy_bitslip5_value1)
- 1'd0: begin
- a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip60 <= 8'd0;
- case (a7ddrphy_bitslip6_value0)
- 1'd0: begin
- a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip62 <= 8'd0;
- case (a7ddrphy_bitslip6_value1)
- 1'd0: begin
- a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip70 <= 8'd0;
- case (a7ddrphy_bitslip7_value0)
- 1'd0: begin
- a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip72 <= 8'd0;
- case (a7ddrphy_bitslip7_value1)
- 1'd0: begin
- a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip80 <= 8'd0;
- case (a7ddrphy_bitslip8_value0)
- 1'd0: begin
- a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip82 <= 8'd0;
- case (a7ddrphy_bitslip8_value1)
- 1'd0: begin
- a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip90 <= 8'd0;
- case (a7ddrphy_bitslip9_value0)
- 1'd0: begin
- a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip92 <= 8'd0;
- case (a7ddrphy_bitslip9_value1)
- 1'd0: begin
- a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip100 <= 8'd0;
- case (a7ddrphy_bitslip10_value0)
- 1'd0: begin
- a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip102 <= 8'd0;
- case (a7ddrphy_bitslip10_value1)
- 1'd0: begin
- a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip110 <= 8'd0;
- case (a7ddrphy_bitslip11_value0)
- 1'd0: begin
- a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip112 <= 8'd0;
- case (a7ddrphy_bitslip11_value1)
- 1'd0: begin
- a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip120 <= 8'd0;
- case (a7ddrphy_bitslip12_value0)
- 1'd0: begin
- a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip122 <= 8'd0;
- case (a7ddrphy_bitslip12_value1)
- 1'd0: begin
- a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip130 <= 8'd0;
- case (a7ddrphy_bitslip13_value0)
- 1'd0: begin
- a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip132 <= 8'd0;
- case (a7ddrphy_bitslip13_value1)
- 1'd0: begin
- a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip140 <= 8'd0;
- case (a7ddrphy_bitslip14_value0)
- 1'd0: begin
- a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip142 <= 8'd0;
- case (a7ddrphy_bitslip14_value1)
- 1'd0: begin
- a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip150 <= 8'd0;
- case (a7ddrphy_bitslip15_value0)
- 1'd0: begin
- a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[15:8];
- end
- endcase
-end
-always @(*) begin
- a7ddrphy_bitslip152 <= 8'd0;
- case (a7ddrphy_bitslip15_value1)
- 1'd0: begin
- a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[8:1];
- end
- 1'd1: begin
- a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[9:2];
- end
- 2'd2: begin
- a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[10:3];
- end
- 2'd3: begin
- a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[11:4];
- end
- 3'd4: begin
- a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[12:5];
- end
- 3'd5: begin
- a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[13:6];
- end
- 3'd6: begin
- a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[14:7];
- end
- 3'd7: begin
- a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[15:8];
- end
- endcase
+ a7ddrphy_dqspattern_o0 <= 8'd0;
+ a7ddrphy_dqspattern_o0 <= 7'd85;
+ if (a7ddrphy_dqspattern0) begin
+ a7ddrphy_dqspattern_o0 <= 5'd21;
+ end
+ if (a7ddrphy_dqspattern1) begin
+ a7ddrphy_dqspattern_o0 <= 7'd84;
+ end
+ if (a7ddrphy_wlevel_en_storage) begin
+ a7ddrphy_dqspattern_o0 <= 1'd0;
+ if (a7ddrphy_wlevel_strobe_re) begin
+ a7ddrphy_dqspattern_o0 <= 1'd1;
+ end
+ end
+end
+always @(*) begin
+ a7ddrphy_bitslip00 <= 8'd0;
+ case (a7ddrphy_bitslip0_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip00 <= a7ddrphy_bitslip0_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip10 <= 8'd0;
+ case (a7ddrphy_bitslip1_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip10 <= a7ddrphy_bitslip1_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip01 <= 8'd0;
+ case (a7ddrphy_bitslip0_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip01 <= a7ddrphy_bitslip0_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip11 <= 8'd0;
+ case (a7ddrphy_bitslip1_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip11 <= a7ddrphy_bitslip1_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip02 <= 8'd0;
+ case (a7ddrphy_bitslip0_value2)
+ 1'd0: begin
+ a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip02 <= a7ddrphy_bitslip0_r2[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip04 <= 8'd0;
+ case (a7ddrphy_bitslip0_value3)
+ 1'd0: begin
+ a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip04 <= a7ddrphy_bitslip0_r3[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip12 <= 8'd0;
+ case (a7ddrphy_bitslip1_value2)
+ 1'd0: begin
+ a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip12 <= a7ddrphy_bitslip1_r2[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip14 <= 8'd0;
+ case (a7ddrphy_bitslip1_value3)
+ 1'd0: begin
+ a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip14 <= a7ddrphy_bitslip1_r3[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip20 <= 8'd0;
+ case (a7ddrphy_bitslip2_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip20 <= a7ddrphy_bitslip2_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip22 <= 8'd0;
+ case (a7ddrphy_bitslip2_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip22 <= a7ddrphy_bitslip2_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip30 <= 8'd0;
+ case (a7ddrphy_bitslip3_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip30 <= a7ddrphy_bitslip3_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip32 <= 8'd0;
+ case (a7ddrphy_bitslip3_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip32 <= a7ddrphy_bitslip3_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip40 <= 8'd0;
+ case (a7ddrphy_bitslip4_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip40 <= a7ddrphy_bitslip4_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip42 <= 8'd0;
+ case (a7ddrphy_bitslip4_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip42 <= a7ddrphy_bitslip4_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip50 <= 8'd0;
+ case (a7ddrphy_bitslip5_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip50 <= a7ddrphy_bitslip5_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip52 <= 8'd0;
+ case (a7ddrphy_bitslip5_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip52 <= a7ddrphy_bitslip5_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip60 <= 8'd0;
+ case (a7ddrphy_bitslip6_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip60 <= a7ddrphy_bitslip6_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip62 <= 8'd0;
+ case (a7ddrphy_bitslip6_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip62 <= a7ddrphy_bitslip6_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip70 <= 8'd0;
+ case (a7ddrphy_bitslip7_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip70 <= a7ddrphy_bitslip7_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip72 <= 8'd0;
+ case (a7ddrphy_bitslip7_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip72 <= a7ddrphy_bitslip7_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip80 <= 8'd0;
+ case (a7ddrphy_bitslip8_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip80 <= a7ddrphy_bitslip8_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip82 <= 8'd0;
+ case (a7ddrphy_bitslip8_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip82 <= a7ddrphy_bitslip8_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip90 <= 8'd0;
+ case (a7ddrphy_bitslip9_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip90 <= a7ddrphy_bitslip9_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip92 <= 8'd0;
+ case (a7ddrphy_bitslip9_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip92 <= a7ddrphy_bitslip9_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip100 <= 8'd0;
+ case (a7ddrphy_bitslip10_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip100 <= a7ddrphy_bitslip10_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip102 <= 8'd0;
+ case (a7ddrphy_bitslip10_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip102 <= a7ddrphy_bitslip10_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip110 <= 8'd0;
+ case (a7ddrphy_bitslip11_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip110 <= a7ddrphy_bitslip11_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip112 <= 8'd0;
+ case (a7ddrphy_bitslip11_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip112 <= a7ddrphy_bitslip11_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip120 <= 8'd0;
+ case (a7ddrphy_bitslip12_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip120 <= a7ddrphy_bitslip12_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip122 <= 8'd0;
+ case (a7ddrphy_bitslip12_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip122 <= a7ddrphy_bitslip12_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip130 <= 8'd0;
+ case (a7ddrphy_bitslip13_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip130 <= a7ddrphy_bitslip13_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip132 <= 8'd0;
+ case (a7ddrphy_bitslip13_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip132 <= a7ddrphy_bitslip13_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip140 <= 8'd0;
+ case (a7ddrphy_bitslip14_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip140 <= a7ddrphy_bitslip14_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip142 <= 8'd0;
+ case (a7ddrphy_bitslip14_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip142 <= a7ddrphy_bitslip14_r1[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip150 <= 8'd0;
+ case (a7ddrphy_bitslip15_value0)
+ 1'd0: begin
+ a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip150 <= a7ddrphy_bitslip15_r0[15:8];
+ end
+ endcase
+end
+always @(*) begin
+ a7ddrphy_bitslip152 <= 8'd0;
+ case (a7ddrphy_bitslip15_value1)
+ 1'd0: begin
+ a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[8:1];
+ end
+ 1'd1: begin
+ a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[9:2];
+ end
+ 2'd2: begin
+ a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[10:3];
+ end
+ 2'd3: begin
+ a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[11:4];
+ end
+ 3'd4: begin
+ a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[12:5];
+ end
+ 3'd5: begin
+ a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[13:6];
+ end
+ 3'd6: begin
+ a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[14:7];
+ end
+ 3'd7: begin
+ a7ddrphy_bitslip152 <= a7ddrphy_bitslip15_r1[15:8];
+ end
+ endcase
end
assign a7ddrphy_dfi_p0_address = litedramcore_master_p0_address;
assign a7ddrphy_dfi_p0_bank = litedramcore_master_p0_bank;
assign litedramcore_dfi_p3_rddata = litedramcore_slave_p3_rddata;
assign litedramcore_dfi_p3_rddata_valid = litedramcore_slave_p3_rddata_valid;
always @(*) begin
- litedramcore_csr_dfi_p0_rddata <= 32'd0;
- if (litedramcore_sel) begin
- end else begin
- litedramcore_csr_dfi_p0_rddata <= litedramcore_master_p0_rddata;
- end
+ litedramcore_csr_dfi_p0_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_csr_dfi_p0_rddata <= litedramcore_master_p0_rddata;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p0_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- end else begin
- litedramcore_csr_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
- end
-end
-always @(*) begin
- litedramcore_csr_dfi_p1_rddata <= 32'd0;
- if (litedramcore_sel) begin
- end else begin
- litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata;
- end
-end
-always @(*) begin
- litedramcore_csr_dfi_p1_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- end else begin
- litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
- end
-end
-always @(*) begin
- litedramcore_csr_dfi_p2_rddata <= 32'd0;
- if (litedramcore_sel) begin
- end else begin
- litedramcore_csr_dfi_p2_rddata <= litedramcore_master_p2_rddata;
- end
-end
-always @(*) begin
- litedramcore_csr_dfi_p2_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- end else begin
- litedramcore_csr_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
- end
-end
-always @(*) begin
- litedramcore_csr_dfi_p3_rddata <= 32'd0;
- if (litedramcore_sel) begin
- end else begin
- litedramcore_csr_dfi_p3_rddata <= litedramcore_master_p3_rddata;
- end
-end
-always @(*) begin
- litedramcore_csr_dfi_p3_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- end else begin
- litedramcore_csr_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
- end
-end
-always @(*) begin
- litedramcore_ext_dfi_p0_rddata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_ext_dfi_p0_rddata <= litedramcore_master_p0_rddata;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_ext_dfi_p0_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_ext_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_ext_dfi_p1_rddata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_ext_dfi_p1_rddata <= litedramcore_master_p1_rddata;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_ext_dfi_p1_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_ext_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_ext_dfi_p2_rddata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_ext_dfi_p2_rddata <= litedramcore_master_p2_rddata;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_ext_dfi_p2_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_ext_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_slave_p0_rddata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- end else begin
- litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata;
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_slave_p0_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- end else begin
- litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_ext_dfi_p3_rddata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_ext_dfi_p3_rddata <= litedramcore_master_p3_rddata;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_ext_dfi_p3_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_ext_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
- end else begin
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_slave_p1_rddata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- end else begin
- litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata;
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_slave_p1_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- end else begin
- litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_slave_p2_rddata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- end else begin
- litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata;
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_slave_p2_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- end else begin
- litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_slave_p3_rddata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- end else begin
- litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata;
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_slave_p3_rddata_valid <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- end else begin
- litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
- end
- end else begin
- end
-end
-always @(*) begin
- litedramcore_master_p0_address <= 14'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_address <= litedramcore_ext_dfi_p0_address;
- end else begin
- litedramcore_master_p0_address <= litedramcore_slave_p0_address;
- end
- end else begin
- litedramcore_master_p0_address <= litedramcore_csr_dfi_p0_address;
- end
-end
-always @(*) begin
- litedramcore_master_p0_bank <= 3'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_bank <= litedramcore_ext_dfi_p0_bank;
- end else begin
- litedramcore_master_p0_bank <= litedramcore_slave_p0_bank;
- end
- end else begin
- litedramcore_master_p0_bank <= litedramcore_csr_dfi_p0_bank;
- end
-end
-always @(*) begin
- litedramcore_master_p0_cas_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_cas_n <= litedramcore_ext_dfi_p0_cas_n;
- end else begin
- litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n;
- end
- end else begin
- litedramcore_master_p0_cas_n <= litedramcore_csr_dfi_p0_cas_n;
- end
-end
-always @(*) begin
- litedramcore_master_p0_cs_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n;
- end else begin
- litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n;
- end
- end else begin
- litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n;
- end
-end
-always @(*) begin
- litedramcore_master_p0_ras_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n;
- end else begin
- litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n;
- end
- end else begin
- litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n;
- end
-end
-always @(*) begin
- litedramcore_master_p0_we_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n;
- end else begin
- litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n;
- end
- end else begin
- litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n;
- end
-end
-always @(*) begin
- litedramcore_master_p0_cke <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_cke <= litedramcore_ext_dfi_p0_cke;
- end else begin
- litedramcore_master_p0_cke <= litedramcore_slave_p0_cke;
- end
- end else begin
- litedramcore_master_p0_cke <= litedramcore_csr_dfi_p0_cke;
- end
-end
-always @(*) begin
- litedramcore_master_p0_odt <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_odt <= litedramcore_ext_dfi_p0_odt;
- end else begin
- litedramcore_master_p0_odt <= litedramcore_slave_p0_odt;
- end
- end else begin
- litedramcore_master_p0_odt <= litedramcore_csr_dfi_p0_odt;
- end
-end
-always @(*) begin
- litedramcore_master_p0_reset_n <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_reset_n <= litedramcore_ext_dfi_p0_reset_n;
- end else begin
- litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n;
- end
- end else begin
- litedramcore_master_p0_reset_n <= litedramcore_csr_dfi_p0_reset_n;
- end
-end
-always @(*) begin
- litedramcore_master_p0_act_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_act_n <= litedramcore_ext_dfi_p0_act_n;
- end else begin
- litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n;
- end
- end else begin
- litedramcore_master_p0_act_n <= litedramcore_csr_dfi_p0_act_n;
- end
-end
-always @(*) begin
- litedramcore_master_p0_wrdata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_wrdata <= litedramcore_ext_dfi_p0_wrdata;
- end else begin
- litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata;
- end
- end else begin
- litedramcore_master_p0_wrdata <= litedramcore_csr_dfi_p0_wrdata;
- end
-end
-always @(*) begin
- litedramcore_master_p0_wrdata_en <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_wrdata_en <= litedramcore_ext_dfi_p0_wrdata_en;
- end else begin
- litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en;
- end
- end else begin
- litedramcore_master_p0_wrdata_en <= litedramcore_csr_dfi_p0_wrdata_en;
- end
-end
-always @(*) begin
- litedramcore_master_p0_wrdata_mask <= 4'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_wrdata_mask <= litedramcore_ext_dfi_p0_wrdata_mask;
- end else begin
- litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask;
- end
- end else begin
- litedramcore_master_p0_wrdata_mask <= litedramcore_csr_dfi_p0_wrdata_mask;
- end
-end
-always @(*) begin
- litedramcore_master_p0_rddata_en <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p0_rddata_en <= litedramcore_ext_dfi_p0_rddata_en;
- end else begin
- litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en;
- end
- end else begin
- litedramcore_master_p0_rddata_en <= litedramcore_csr_dfi_p0_rddata_en;
- end
-end
-always @(*) begin
- litedramcore_master_p1_address <= 14'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_address <= litedramcore_ext_dfi_p1_address;
- end else begin
- litedramcore_master_p1_address <= litedramcore_slave_p1_address;
- end
- end else begin
- litedramcore_master_p1_address <= litedramcore_csr_dfi_p1_address;
- end
-end
-always @(*) begin
- litedramcore_master_p1_bank <= 3'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_bank <= litedramcore_ext_dfi_p1_bank;
- end else begin
- litedramcore_master_p1_bank <= litedramcore_slave_p1_bank;
- end
- end else begin
- litedramcore_master_p1_bank <= litedramcore_csr_dfi_p1_bank;
- end
-end
-always @(*) begin
- litedramcore_master_p1_cas_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_cas_n <= litedramcore_ext_dfi_p1_cas_n;
- end else begin
- litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n;
- end
- end else begin
- litedramcore_master_p1_cas_n <= litedramcore_csr_dfi_p1_cas_n;
- end
-end
-always @(*) begin
- litedramcore_master_p1_cs_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_cs_n <= litedramcore_ext_dfi_p1_cs_n;
- end else begin
- litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n;
- end
- end else begin
- litedramcore_master_p1_cs_n <= litedramcore_csr_dfi_p1_cs_n;
- end
-end
-always @(*) begin
- litedramcore_master_p1_ras_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_ras_n <= litedramcore_ext_dfi_p1_ras_n;
- end else begin
- litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n;
- end
- end else begin
- litedramcore_master_p1_ras_n <= litedramcore_csr_dfi_p1_ras_n;
- end
-end
-always @(*) begin
- litedramcore_master_p1_we_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_we_n <= litedramcore_ext_dfi_p1_we_n;
- end else begin
- litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n;
- end
- end else begin
- litedramcore_master_p1_we_n <= litedramcore_csr_dfi_p1_we_n;
- end
-end
-always @(*) begin
- litedramcore_master_p1_cke <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_cke <= litedramcore_ext_dfi_p1_cke;
- end else begin
- litedramcore_master_p1_cke <= litedramcore_slave_p1_cke;
- end
- end else begin
- litedramcore_master_p1_cke <= litedramcore_csr_dfi_p1_cke;
- end
-end
-always @(*) begin
- litedramcore_master_p1_odt <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_odt <= litedramcore_ext_dfi_p1_odt;
- end else begin
- litedramcore_master_p1_odt <= litedramcore_slave_p1_odt;
- end
- end else begin
- litedramcore_master_p1_odt <= litedramcore_csr_dfi_p1_odt;
- end
-end
-always @(*) begin
- litedramcore_master_p1_reset_n <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_reset_n <= litedramcore_ext_dfi_p1_reset_n;
- end else begin
- litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n;
- end
- end else begin
- litedramcore_master_p1_reset_n <= litedramcore_csr_dfi_p1_reset_n;
- end
-end
-always @(*) begin
- litedramcore_master_p1_act_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_act_n <= litedramcore_ext_dfi_p1_act_n;
- end else begin
- litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n;
- end
- end else begin
- litedramcore_master_p1_act_n <= litedramcore_csr_dfi_p1_act_n;
- end
-end
-always @(*) begin
- litedramcore_master_p1_wrdata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_wrdata <= litedramcore_ext_dfi_p1_wrdata;
- end else begin
- litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata;
- end
- end else begin
- litedramcore_master_p1_wrdata <= litedramcore_csr_dfi_p1_wrdata;
- end
-end
-always @(*) begin
- litedramcore_master_p1_wrdata_en <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_wrdata_en <= litedramcore_ext_dfi_p1_wrdata_en;
- end else begin
- litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en;
- end
- end else begin
- litedramcore_master_p1_wrdata_en <= litedramcore_csr_dfi_p1_wrdata_en;
- end
-end
-always @(*) begin
- litedramcore_master_p1_wrdata_mask <= 4'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_wrdata_mask <= litedramcore_ext_dfi_p1_wrdata_mask;
- end else begin
- litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask;
- end
- end else begin
- litedramcore_master_p1_wrdata_mask <= litedramcore_csr_dfi_p1_wrdata_mask;
- end
-end
-always @(*) begin
- litedramcore_master_p1_rddata_en <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p1_rddata_en <= litedramcore_ext_dfi_p1_rddata_en;
- end else begin
- litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en;
- end
- end else begin
- litedramcore_master_p1_rddata_en <= litedramcore_csr_dfi_p1_rddata_en;
- end
-end
-always @(*) begin
- litedramcore_master_p2_address <= 14'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_address <= litedramcore_ext_dfi_p2_address;
- end else begin
- litedramcore_master_p2_address <= litedramcore_slave_p2_address;
- end
- end else begin
- litedramcore_master_p2_address <= litedramcore_csr_dfi_p2_address;
- end
-end
-always @(*) begin
- litedramcore_master_p2_bank <= 3'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_bank <= litedramcore_ext_dfi_p2_bank;
- end else begin
- litedramcore_master_p2_bank <= litedramcore_slave_p2_bank;
- end
- end else begin
- litedramcore_master_p2_bank <= litedramcore_csr_dfi_p2_bank;
- end
-end
-always @(*) begin
- litedramcore_master_p2_cas_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_cas_n <= litedramcore_ext_dfi_p2_cas_n;
- end else begin
- litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n;
- end
- end else begin
- litedramcore_master_p2_cas_n <= litedramcore_csr_dfi_p2_cas_n;
- end
-end
-always @(*) begin
- litedramcore_master_p2_cs_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_cs_n <= litedramcore_ext_dfi_p2_cs_n;
- end else begin
- litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n;
- end
- end else begin
- litedramcore_master_p2_cs_n <= litedramcore_csr_dfi_p2_cs_n;
- end
-end
-always @(*) begin
- litedramcore_master_p2_ras_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_ras_n <= litedramcore_ext_dfi_p2_ras_n;
- end else begin
- litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n;
- end
- end else begin
- litedramcore_master_p2_ras_n <= litedramcore_csr_dfi_p2_ras_n;
- end
-end
-always @(*) begin
- litedramcore_master_p2_we_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_we_n <= litedramcore_ext_dfi_p2_we_n;
- end else begin
- litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n;
- end
- end else begin
- litedramcore_master_p2_we_n <= litedramcore_csr_dfi_p2_we_n;
- end
-end
-always @(*) begin
- litedramcore_master_p2_cke <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_cke <= litedramcore_ext_dfi_p2_cke;
- end else begin
- litedramcore_master_p2_cke <= litedramcore_slave_p2_cke;
- end
- end else begin
- litedramcore_master_p2_cke <= litedramcore_csr_dfi_p2_cke;
- end
-end
-always @(*) begin
- litedramcore_master_p2_odt <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_odt <= litedramcore_ext_dfi_p2_odt;
- end else begin
- litedramcore_master_p2_odt <= litedramcore_slave_p2_odt;
- end
- end else begin
- litedramcore_master_p2_odt <= litedramcore_csr_dfi_p2_odt;
- end
-end
-always @(*) begin
- litedramcore_master_p2_reset_n <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_reset_n <= litedramcore_ext_dfi_p2_reset_n;
- end else begin
- litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n;
- end
- end else begin
- litedramcore_master_p2_reset_n <= litedramcore_csr_dfi_p2_reset_n;
- end
-end
-always @(*) begin
- litedramcore_master_p2_act_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_act_n <= litedramcore_ext_dfi_p2_act_n;
- end else begin
- litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n;
- end
- end else begin
- litedramcore_master_p2_act_n <= litedramcore_csr_dfi_p2_act_n;
- end
-end
-always @(*) begin
- litedramcore_master_p2_wrdata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_wrdata <= litedramcore_ext_dfi_p2_wrdata;
- end else begin
- litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata;
- end
- end else begin
- litedramcore_master_p2_wrdata <= litedramcore_csr_dfi_p2_wrdata;
- end
-end
-always @(*) begin
- litedramcore_master_p2_wrdata_en <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_wrdata_en <= litedramcore_ext_dfi_p2_wrdata_en;
- end else begin
- litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en;
- end
- end else begin
- litedramcore_master_p2_wrdata_en <= litedramcore_csr_dfi_p2_wrdata_en;
- end
-end
-always @(*) begin
- litedramcore_master_p2_wrdata_mask <= 4'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_wrdata_mask <= litedramcore_ext_dfi_p2_wrdata_mask;
- end else begin
- litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask;
- end
- end else begin
- litedramcore_master_p2_wrdata_mask <= litedramcore_csr_dfi_p2_wrdata_mask;
- end
-end
-always @(*) begin
- litedramcore_master_p2_rddata_en <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p2_rddata_en <= litedramcore_ext_dfi_p2_rddata_en;
- end else begin
- litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en;
- end
- end else begin
- litedramcore_master_p2_rddata_en <= litedramcore_csr_dfi_p2_rddata_en;
- end
-end
-always @(*) begin
- litedramcore_master_p3_address <= 14'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_address <= litedramcore_ext_dfi_p3_address;
- end else begin
- litedramcore_master_p3_address <= litedramcore_slave_p3_address;
- end
- end else begin
- litedramcore_master_p3_address <= litedramcore_csr_dfi_p3_address;
- end
-end
-always @(*) begin
- litedramcore_master_p3_bank <= 3'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_bank <= litedramcore_ext_dfi_p3_bank;
- end else begin
- litedramcore_master_p3_bank <= litedramcore_slave_p3_bank;
- end
- end else begin
- litedramcore_master_p3_bank <= litedramcore_csr_dfi_p3_bank;
- end
-end
-always @(*) begin
- litedramcore_master_p3_cas_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_cas_n <= litedramcore_ext_dfi_p3_cas_n;
- end else begin
- litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n;
- end
- end else begin
- litedramcore_master_p3_cas_n <= litedramcore_csr_dfi_p3_cas_n;
- end
-end
-always @(*) begin
- litedramcore_master_p3_cs_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_cs_n <= litedramcore_ext_dfi_p3_cs_n;
- end else begin
- litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n;
- end
- end else begin
- litedramcore_master_p3_cs_n <= litedramcore_csr_dfi_p3_cs_n;
- end
-end
-always @(*) begin
- litedramcore_master_p3_ras_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_ras_n <= litedramcore_ext_dfi_p3_ras_n;
- end else begin
- litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n;
- end
- end else begin
- litedramcore_master_p3_ras_n <= litedramcore_csr_dfi_p3_ras_n;
- end
-end
-always @(*) begin
- litedramcore_master_p3_we_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_we_n <= litedramcore_ext_dfi_p3_we_n;
- end else begin
- litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n;
- end
- end else begin
- litedramcore_master_p3_we_n <= litedramcore_csr_dfi_p3_we_n;
- end
-end
-always @(*) begin
- litedramcore_master_p3_cke <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_cke <= litedramcore_ext_dfi_p3_cke;
- end else begin
- litedramcore_master_p3_cke <= litedramcore_slave_p3_cke;
- end
- end else begin
- litedramcore_master_p3_cke <= litedramcore_csr_dfi_p3_cke;
- end
-end
-always @(*) begin
- litedramcore_master_p3_odt <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_odt <= litedramcore_ext_dfi_p3_odt;
- end else begin
- litedramcore_master_p3_odt <= litedramcore_slave_p3_odt;
- end
- end else begin
- litedramcore_master_p3_odt <= litedramcore_csr_dfi_p3_odt;
- end
-end
-always @(*) begin
- litedramcore_master_p3_reset_n <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_reset_n <= litedramcore_ext_dfi_p3_reset_n;
- end else begin
- litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n;
- end
- end else begin
- litedramcore_master_p3_reset_n <= litedramcore_csr_dfi_p3_reset_n;
- end
-end
-always @(*) begin
- litedramcore_master_p3_act_n <= 1'd1;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_act_n <= litedramcore_ext_dfi_p3_act_n;
- end else begin
- litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n;
- end
- end else begin
- litedramcore_master_p3_act_n <= litedramcore_csr_dfi_p3_act_n;
- end
-end
-always @(*) begin
- litedramcore_master_p3_wrdata <= 32'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_wrdata <= litedramcore_ext_dfi_p3_wrdata;
- end else begin
- litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata;
- end
- end else begin
- litedramcore_master_p3_wrdata <= litedramcore_csr_dfi_p3_wrdata;
- end
-end
-always @(*) begin
- litedramcore_master_p3_wrdata_en <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_wrdata_en <= litedramcore_ext_dfi_p3_wrdata_en;
- end else begin
- litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en;
- end
- end else begin
- litedramcore_master_p3_wrdata_en <= litedramcore_csr_dfi_p3_wrdata_en;
- end
-end
-always @(*) begin
- litedramcore_master_p3_wrdata_mask <= 4'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_wrdata_mask <= litedramcore_ext_dfi_p3_wrdata_mask;
- end else begin
- litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask;
- end
- end else begin
- litedramcore_master_p3_wrdata_mask <= litedramcore_csr_dfi_p3_wrdata_mask;
- end
-end
-always @(*) begin
- litedramcore_master_p3_rddata_en <= 1'd0;
- if (litedramcore_sel) begin
- if (litedramcore_ext_dfi_sel) begin
- litedramcore_master_p3_rddata_en <= litedramcore_ext_dfi_p3_rddata_en;
- end else begin
- litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en;
- end
- end else begin
- litedramcore_master_p3_rddata_en <= litedramcore_csr_dfi_p3_rddata_en;
- end
+ litedramcore_csr_dfi_p0_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_csr_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+ end
+end
+always @(*) begin
+ litedramcore_csr_dfi_p1_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_csr_dfi_p1_rddata <= litedramcore_master_p1_rddata;
+ end
+end
+always @(*) begin
+ litedramcore_csr_dfi_p1_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_csr_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+ end
+end
+always @(*) begin
+ litedramcore_csr_dfi_p2_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_csr_dfi_p2_rddata <= litedramcore_master_p2_rddata;
+ end
+end
+always @(*) begin
+ litedramcore_csr_dfi_p2_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_csr_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+ end
+end
+always @(*) begin
+ litedramcore_csr_dfi_p3_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_csr_dfi_p3_rddata <= litedramcore_master_p3_rddata;
+ end
+end
+always @(*) begin
+ litedramcore_csr_dfi_p3_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ end else begin
+ litedramcore_csr_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+ end
+end
+always @(*) begin
+ litedramcore_ext_dfi_p0_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_ext_dfi_p0_rddata <= litedramcore_master_p0_rddata;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_ext_dfi_p0_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_ext_dfi_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_ext_dfi_p1_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_ext_dfi_p1_rddata <= litedramcore_master_p1_rddata;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_ext_dfi_p1_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_ext_dfi_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_ext_dfi_p2_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_ext_dfi_p2_rddata <= litedramcore_master_p2_rddata;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_ext_dfi_p2_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_ext_dfi_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p0_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ end else begin
+ litedramcore_slave_p0_rddata <= litedramcore_master_p0_rddata;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p0_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ end else begin
+ litedramcore_slave_p0_rddata_valid <= litedramcore_master_p0_rddata_valid;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_ext_dfi_p3_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_ext_dfi_p3_rddata <= litedramcore_master_p3_rddata;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_ext_dfi_p3_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_ext_dfi_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+ end else begin
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p1_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ end else begin
+ litedramcore_slave_p1_rddata <= litedramcore_master_p1_rddata;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p1_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ end else begin
+ litedramcore_slave_p1_rddata_valid <= litedramcore_master_p1_rddata_valid;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p2_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ end else begin
+ litedramcore_slave_p2_rddata <= litedramcore_master_p2_rddata;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p2_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ end else begin
+ litedramcore_slave_p2_rddata_valid <= litedramcore_master_p2_rddata_valid;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p3_rddata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ end else begin
+ litedramcore_slave_p3_rddata <= litedramcore_master_p3_rddata;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_slave_p3_rddata_valid <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ end else begin
+ litedramcore_slave_p3_rddata_valid <= litedramcore_master_p3_rddata_valid;
+ end
+ end else begin
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_address <= 14'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_address <= litedramcore_ext_dfi_p0_address;
+ end else begin
+ litedramcore_master_p0_address <= litedramcore_slave_p0_address;
+ end
+ end else begin
+ litedramcore_master_p0_address <= litedramcore_csr_dfi_p0_address;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_bank <= 3'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_bank <= litedramcore_ext_dfi_p0_bank;
+ end else begin
+ litedramcore_master_p0_bank <= litedramcore_slave_p0_bank;
+ end
+ end else begin
+ litedramcore_master_p0_bank <= litedramcore_csr_dfi_p0_bank;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_cas_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_cas_n <= litedramcore_ext_dfi_p0_cas_n;
+ end else begin
+ litedramcore_master_p0_cas_n <= litedramcore_slave_p0_cas_n;
+ end
+ end else begin
+ litedramcore_master_p0_cas_n <= litedramcore_csr_dfi_p0_cas_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_cs_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_cs_n <= litedramcore_ext_dfi_p0_cs_n;
+ end else begin
+ litedramcore_master_p0_cs_n <= litedramcore_slave_p0_cs_n;
+ end
+ end else begin
+ litedramcore_master_p0_cs_n <= litedramcore_csr_dfi_p0_cs_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_ras_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_ras_n <= litedramcore_ext_dfi_p0_ras_n;
+ end else begin
+ litedramcore_master_p0_ras_n <= litedramcore_slave_p0_ras_n;
+ end
+ end else begin
+ litedramcore_master_p0_ras_n <= litedramcore_csr_dfi_p0_ras_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_we_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_we_n <= litedramcore_ext_dfi_p0_we_n;
+ end else begin
+ litedramcore_master_p0_we_n <= litedramcore_slave_p0_we_n;
+ end
+ end else begin
+ litedramcore_master_p0_we_n <= litedramcore_csr_dfi_p0_we_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_cke <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_cke <= litedramcore_ext_dfi_p0_cke;
+ end else begin
+ litedramcore_master_p0_cke <= litedramcore_slave_p0_cke;
+ end
+ end else begin
+ litedramcore_master_p0_cke <= litedramcore_csr_dfi_p0_cke;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_odt <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_odt <= litedramcore_ext_dfi_p0_odt;
+ end else begin
+ litedramcore_master_p0_odt <= litedramcore_slave_p0_odt;
+ end
+ end else begin
+ litedramcore_master_p0_odt <= litedramcore_csr_dfi_p0_odt;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_reset_n <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_reset_n <= litedramcore_ext_dfi_p0_reset_n;
+ end else begin
+ litedramcore_master_p0_reset_n <= litedramcore_slave_p0_reset_n;
+ end
+ end else begin
+ litedramcore_master_p0_reset_n <= litedramcore_csr_dfi_p0_reset_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_act_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_act_n <= litedramcore_ext_dfi_p0_act_n;
+ end else begin
+ litedramcore_master_p0_act_n <= litedramcore_slave_p0_act_n;
+ end
+ end else begin
+ litedramcore_master_p0_act_n <= litedramcore_csr_dfi_p0_act_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_wrdata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_wrdata <= litedramcore_ext_dfi_p0_wrdata;
+ end else begin
+ litedramcore_master_p0_wrdata <= litedramcore_slave_p0_wrdata;
+ end
+ end else begin
+ litedramcore_master_p0_wrdata <= litedramcore_csr_dfi_p0_wrdata;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_wrdata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_wrdata_en <= litedramcore_ext_dfi_p0_wrdata_en;
+ end else begin
+ litedramcore_master_p0_wrdata_en <= litedramcore_slave_p0_wrdata_en;
+ end
+ end else begin
+ litedramcore_master_p0_wrdata_en <= litedramcore_csr_dfi_p0_wrdata_en;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_wrdata_mask <= 4'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_wrdata_mask <= litedramcore_ext_dfi_p0_wrdata_mask;
+ end else begin
+ litedramcore_master_p0_wrdata_mask <= litedramcore_slave_p0_wrdata_mask;
+ end
+ end else begin
+ litedramcore_master_p0_wrdata_mask <= litedramcore_csr_dfi_p0_wrdata_mask;
+ end
+end
+always @(*) begin
+ litedramcore_master_p0_rddata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p0_rddata_en <= litedramcore_ext_dfi_p0_rddata_en;
+ end else begin
+ litedramcore_master_p0_rddata_en <= litedramcore_slave_p0_rddata_en;
+ end
+ end else begin
+ litedramcore_master_p0_rddata_en <= litedramcore_csr_dfi_p0_rddata_en;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_address <= 14'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_address <= litedramcore_ext_dfi_p1_address;
+ end else begin
+ litedramcore_master_p1_address <= litedramcore_slave_p1_address;
+ end
+ end else begin
+ litedramcore_master_p1_address <= litedramcore_csr_dfi_p1_address;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_bank <= 3'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_bank <= litedramcore_ext_dfi_p1_bank;
+ end else begin
+ litedramcore_master_p1_bank <= litedramcore_slave_p1_bank;
+ end
+ end else begin
+ litedramcore_master_p1_bank <= litedramcore_csr_dfi_p1_bank;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_cas_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_cas_n <= litedramcore_ext_dfi_p1_cas_n;
+ end else begin
+ litedramcore_master_p1_cas_n <= litedramcore_slave_p1_cas_n;
+ end
+ end else begin
+ litedramcore_master_p1_cas_n <= litedramcore_csr_dfi_p1_cas_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_cs_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_cs_n <= litedramcore_ext_dfi_p1_cs_n;
+ end else begin
+ litedramcore_master_p1_cs_n <= litedramcore_slave_p1_cs_n;
+ end
+ end else begin
+ litedramcore_master_p1_cs_n <= litedramcore_csr_dfi_p1_cs_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_ras_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_ras_n <= litedramcore_ext_dfi_p1_ras_n;
+ end else begin
+ litedramcore_master_p1_ras_n <= litedramcore_slave_p1_ras_n;
+ end
+ end else begin
+ litedramcore_master_p1_ras_n <= litedramcore_csr_dfi_p1_ras_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_we_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_we_n <= litedramcore_ext_dfi_p1_we_n;
+ end else begin
+ litedramcore_master_p1_we_n <= litedramcore_slave_p1_we_n;
+ end
+ end else begin
+ litedramcore_master_p1_we_n <= litedramcore_csr_dfi_p1_we_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_cke <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_cke <= litedramcore_ext_dfi_p1_cke;
+ end else begin
+ litedramcore_master_p1_cke <= litedramcore_slave_p1_cke;
+ end
+ end else begin
+ litedramcore_master_p1_cke <= litedramcore_csr_dfi_p1_cke;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_odt <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_odt <= litedramcore_ext_dfi_p1_odt;
+ end else begin
+ litedramcore_master_p1_odt <= litedramcore_slave_p1_odt;
+ end
+ end else begin
+ litedramcore_master_p1_odt <= litedramcore_csr_dfi_p1_odt;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_reset_n <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_reset_n <= litedramcore_ext_dfi_p1_reset_n;
+ end else begin
+ litedramcore_master_p1_reset_n <= litedramcore_slave_p1_reset_n;
+ end
+ end else begin
+ litedramcore_master_p1_reset_n <= litedramcore_csr_dfi_p1_reset_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_act_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_act_n <= litedramcore_ext_dfi_p1_act_n;
+ end else begin
+ litedramcore_master_p1_act_n <= litedramcore_slave_p1_act_n;
+ end
+ end else begin
+ litedramcore_master_p1_act_n <= litedramcore_csr_dfi_p1_act_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_wrdata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_wrdata <= litedramcore_ext_dfi_p1_wrdata;
+ end else begin
+ litedramcore_master_p1_wrdata <= litedramcore_slave_p1_wrdata;
+ end
+ end else begin
+ litedramcore_master_p1_wrdata <= litedramcore_csr_dfi_p1_wrdata;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_wrdata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_wrdata_en <= litedramcore_ext_dfi_p1_wrdata_en;
+ end else begin
+ litedramcore_master_p1_wrdata_en <= litedramcore_slave_p1_wrdata_en;
+ end
+ end else begin
+ litedramcore_master_p1_wrdata_en <= litedramcore_csr_dfi_p1_wrdata_en;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_wrdata_mask <= 4'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_wrdata_mask <= litedramcore_ext_dfi_p1_wrdata_mask;
+ end else begin
+ litedramcore_master_p1_wrdata_mask <= litedramcore_slave_p1_wrdata_mask;
+ end
+ end else begin
+ litedramcore_master_p1_wrdata_mask <= litedramcore_csr_dfi_p1_wrdata_mask;
+ end
+end
+always @(*) begin
+ litedramcore_master_p1_rddata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p1_rddata_en <= litedramcore_ext_dfi_p1_rddata_en;
+ end else begin
+ litedramcore_master_p1_rddata_en <= litedramcore_slave_p1_rddata_en;
+ end
+ end else begin
+ litedramcore_master_p1_rddata_en <= litedramcore_csr_dfi_p1_rddata_en;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_address <= 14'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_address <= litedramcore_ext_dfi_p2_address;
+ end else begin
+ litedramcore_master_p2_address <= litedramcore_slave_p2_address;
+ end
+ end else begin
+ litedramcore_master_p2_address <= litedramcore_csr_dfi_p2_address;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_bank <= 3'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_bank <= litedramcore_ext_dfi_p2_bank;
+ end else begin
+ litedramcore_master_p2_bank <= litedramcore_slave_p2_bank;
+ end
+ end else begin
+ litedramcore_master_p2_bank <= litedramcore_csr_dfi_p2_bank;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_cas_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_cas_n <= litedramcore_ext_dfi_p2_cas_n;
+ end else begin
+ litedramcore_master_p2_cas_n <= litedramcore_slave_p2_cas_n;
+ end
+ end else begin
+ litedramcore_master_p2_cas_n <= litedramcore_csr_dfi_p2_cas_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_cs_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_cs_n <= litedramcore_ext_dfi_p2_cs_n;
+ end else begin
+ litedramcore_master_p2_cs_n <= litedramcore_slave_p2_cs_n;
+ end
+ end else begin
+ litedramcore_master_p2_cs_n <= litedramcore_csr_dfi_p2_cs_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_ras_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_ras_n <= litedramcore_ext_dfi_p2_ras_n;
+ end else begin
+ litedramcore_master_p2_ras_n <= litedramcore_slave_p2_ras_n;
+ end
+ end else begin
+ litedramcore_master_p2_ras_n <= litedramcore_csr_dfi_p2_ras_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_we_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_we_n <= litedramcore_ext_dfi_p2_we_n;
+ end else begin
+ litedramcore_master_p2_we_n <= litedramcore_slave_p2_we_n;
+ end
+ end else begin
+ litedramcore_master_p2_we_n <= litedramcore_csr_dfi_p2_we_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_cke <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_cke <= litedramcore_ext_dfi_p2_cke;
+ end else begin
+ litedramcore_master_p2_cke <= litedramcore_slave_p2_cke;
+ end
+ end else begin
+ litedramcore_master_p2_cke <= litedramcore_csr_dfi_p2_cke;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_odt <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_odt <= litedramcore_ext_dfi_p2_odt;
+ end else begin
+ litedramcore_master_p2_odt <= litedramcore_slave_p2_odt;
+ end
+ end else begin
+ litedramcore_master_p2_odt <= litedramcore_csr_dfi_p2_odt;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_reset_n <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_reset_n <= litedramcore_ext_dfi_p2_reset_n;
+ end else begin
+ litedramcore_master_p2_reset_n <= litedramcore_slave_p2_reset_n;
+ end
+ end else begin
+ litedramcore_master_p2_reset_n <= litedramcore_csr_dfi_p2_reset_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_act_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_act_n <= litedramcore_ext_dfi_p2_act_n;
+ end else begin
+ litedramcore_master_p2_act_n <= litedramcore_slave_p2_act_n;
+ end
+ end else begin
+ litedramcore_master_p2_act_n <= litedramcore_csr_dfi_p2_act_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_wrdata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_wrdata <= litedramcore_ext_dfi_p2_wrdata;
+ end else begin
+ litedramcore_master_p2_wrdata <= litedramcore_slave_p2_wrdata;
+ end
+ end else begin
+ litedramcore_master_p2_wrdata <= litedramcore_csr_dfi_p2_wrdata;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_wrdata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_wrdata_en <= litedramcore_ext_dfi_p2_wrdata_en;
+ end else begin
+ litedramcore_master_p2_wrdata_en <= litedramcore_slave_p2_wrdata_en;
+ end
+ end else begin
+ litedramcore_master_p2_wrdata_en <= litedramcore_csr_dfi_p2_wrdata_en;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_wrdata_mask <= 4'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_wrdata_mask <= litedramcore_ext_dfi_p2_wrdata_mask;
+ end else begin
+ litedramcore_master_p2_wrdata_mask <= litedramcore_slave_p2_wrdata_mask;
+ end
+ end else begin
+ litedramcore_master_p2_wrdata_mask <= litedramcore_csr_dfi_p2_wrdata_mask;
+ end
+end
+always @(*) begin
+ litedramcore_master_p2_rddata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p2_rddata_en <= litedramcore_ext_dfi_p2_rddata_en;
+ end else begin
+ litedramcore_master_p2_rddata_en <= litedramcore_slave_p2_rddata_en;
+ end
+ end else begin
+ litedramcore_master_p2_rddata_en <= litedramcore_csr_dfi_p2_rddata_en;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_address <= 14'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_address <= litedramcore_ext_dfi_p3_address;
+ end else begin
+ litedramcore_master_p3_address <= litedramcore_slave_p3_address;
+ end
+ end else begin
+ litedramcore_master_p3_address <= litedramcore_csr_dfi_p3_address;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_bank <= 3'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_bank <= litedramcore_ext_dfi_p3_bank;
+ end else begin
+ litedramcore_master_p3_bank <= litedramcore_slave_p3_bank;
+ end
+ end else begin
+ litedramcore_master_p3_bank <= litedramcore_csr_dfi_p3_bank;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_cas_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_cas_n <= litedramcore_ext_dfi_p3_cas_n;
+ end else begin
+ litedramcore_master_p3_cas_n <= litedramcore_slave_p3_cas_n;
+ end
+ end else begin
+ litedramcore_master_p3_cas_n <= litedramcore_csr_dfi_p3_cas_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_cs_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_cs_n <= litedramcore_ext_dfi_p3_cs_n;
+ end else begin
+ litedramcore_master_p3_cs_n <= litedramcore_slave_p3_cs_n;
+ end
+ end else begin
+ litedramcore_master_p3_cs_n <= litedramcore_csr_dfi_p3_cs_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_ras_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_ras_n <= litedramcore_ext_dfi_p3_ras_n;
+ end else begin
+ litedramcore_master_p3_ras_n <= litedramcore_slave_p3_ras_n;
+ end
+ end else begin
+ litedramcore_master_p3_ras_n <= litedramcore_csr_dfi_p3_ras_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_we_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_we_n <= litedramcore_ext_dfi_p3_we_n;
+ end else begin
+ litedramcore_master_p3_we_n <= litedramcore_slave_p3_we_n;
+ end
+ end else begin
+ litedramcore_master_p3_we_n <= litedramcore_csr_dfi_p3_we_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_cke <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_cke <= litedramcore_ext_dfi_p3_cke;
+ end else begin
+ litedramcore_master_p3_cke <= litedramcore_slave_p3_cke;
+ end
+ end else begin
+ litedramcore_master_p3_cke <= litedramcore_csr_dfi_p3_cke;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_odt <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_odt <= litedramcore_ext_dfi_p3_odt;
+ end else begin
+ litedramcore_master_p3_odt <= litedramcore_slave_p3_odt;
+ end
+ end else begin
+ litedramcore_master_p3_odt <= litedramcore_csr_dfi_p3_odt;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_reset_n <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_reset_n <= litedramcore_ext_dfi_p3_reset_n;
+ end else begin
+ litedramcore_master_p3_reset_n <= litedramcore_slave_p3_reset_n;
+ end
+ end else begin
+ litedramcore_master_p3_reset_n <= litedramcore_csr_dfi_p3_reset_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_act_n <= 1'd1;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_act_n <= litedramcore_ext_dfi_p3_act_n;
+ end else begin
+ litedramcore_master_p3_act_n <= litedramcore_slave_p3_act_n;
+ end
+ end else begin
+ litedramcore_master_p3_act_n <= litedramcore_csr_dfi_p3_act_n;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_wrdata <= 32'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_wrdata <= litedramcore_ext_dfi_p3_wrdata;
+ end else begin
+ litedramcore_master_p3_wrdata <= litedramcore_slave_p3_wrdata;
+ end
+ end else begin
+ litedramcore_master_p3_wrdata <= litedramcore_csr_dfi_p3_wrdata;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_wrdata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_wrdata_en <= litedramcore_ext_dfi_p3_wrdata_en;
+ end else begin
+ litedramcore_master_p3_wrdata_en <= litedramcore_slave_p3_wrdata_en;
+ end
+ end else begin
+ litedramcore_master_p3_wrdata_en <= litedramcore_csr_dfi_p3_wrdata_en;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_wrdata_mask <= 4'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_wrdata_mask <= litedramcore_ext_dfi_p3_wrdata_mask;
+ end else begin
+ litedramcore_master_p3_wrdata_mask <= litedramcore_slave_p3_wrdata_mask;
+ end
+ end else begin
+ litedramcore_master_p3_wrdata_mask <= litedramcore_csr_dfi_p3_wrdata_mask;
+ end
+end
+always @(*) begin
+ litedramcore_master_p3_rddata_en <= 1'd0;
+ if (litedramcore_sel) begin
+ if (litedramcore_ext_dfi_sel) begin
+ litedramcore_master_p3_rddata_en <= litedramcore_ext_dfi_p3_rddata_en;
+ end else begin
+ litedramcore_master_p3_rddata_en <= litedramcore_slave_p3_rddata_en;
+ end
+ end else begin
+ litedramcore_master_p3_rddata_en <= litedramcore_csr_dfi_p3_rddata_en;
+ end
end
assign litedramcore_csr_dfi_p0_cke = litedramcore_cke;
assign litedramcore_csr_dfi_p1_cke = litedramcore_cke;
assign litedramcore_csr_dfi_p2_reset_n = litedramcore_reset_n;
assign litedramcore_csr_dfi_p3_reset_n = litedramcore_reset_n;
always @(*) begin
- litedramcore_csr_dfi_p0_we_n <= 1'd1;
- if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we);
- end else begin
- litedramcore_csr_dfi_p0_we_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p0_we_n <= 1'd1;
+ if (litedramcore_phaseinjector0_command_issue_re) begin
+ litedramcore_csr_dfi_p0_we_n <= (~litedramcore_phaseinjector0_csrfield_we);
+ end else begin
+ litedramcore_csr_dfi_p0_we_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p0_cas_n <= 1'd1;
- if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_csr_dfi_p0_cas_n <= (~litedramcore_phaseinjector0_csrfield_cas);
- end else begin
- litedramcore_csr_dfi_p0_cas_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p0_cas_n <= 1'd1;
+ if (litedramcore_phaseinjector0_command_issue_re) begin
+ litedramcore_csr_dfi_p0_cas_n <= (~litedramcore_phaseinjector0_csrfield_cas);
+ end else begin
+ litedramcore_csr_dfi_p0_cas_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p0_cs_n <= 1'd1;
- if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}};
- end else begin
- litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}};
- end
+ litedramcore_csr_dfi_p0_cs_n <= 1'd1;
+ if (litedramcore_phaseinjector0_command_issue_re) begin
+ litedramcore_csr_dfi_p0_cs_n <= {1{(~litedramcore_phaseinjector0_csrfield_cs)}};
+ end else begin
+ litedramcore_csr_dfi_p0_cs_n <= {1{1'd1}};
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p0_ras_n <= 1'd1;
- if (litedramcore_phaseinjector0_command_issue_re) begin
- litedramcore_csr_dfi_p0_ras_n <= (~litedramcore_phaseinjector0_csrfield_ras);
- end else begin
- litedramcore_csr_dfi_p0_ras_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p0_ras_n <= 1'd1;
+ if (litedramcore_phaseinjector0_command_issue_re) begin
+ litedramcore_csr_dfi_p0_ras_n <= (~litedramcore_phaseinjector0_csrfield_ras);
+ end else begin
+ litedramcore_csr_dfi_p0_ras_n <= 1'd1;
+ end
end
assign litedramcore_csr_dfi_p0_address = litedramcore_phaseinjector0_address_storage;
assign litedramcore_csr_dfi_p0_bank = litedramcore_phaseinjector0_baddress_storage;
assign litedramcore_csr_dfi_p0_wrdata = litedramcore_phaseinjector0_wrdata_storage;
assign litedramcore_csr_dfi_p0_wrdata_mask = 1'd0;
always @(*) begin
- litedramcore_csr_dfi_p1_we_n <= 1'd1;
- if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we);
- end else begin
- litedramcore_csr_dfi_p1_we_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p1_we_n <= 1'd1;
+ if (litedramcore_phaseinjector1_command_issue_re) begin
+ litedramcore_csr_dfi_p1_we_n <= (~litedramcore_phaseinjector1_csrfield_we);
+ end else begin
+ litedramcore_csr_dfi_p1_we_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p1_cas_n <= 1'd1;
- if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_csr_dfi_p1_cas_n <= (~litedramcore_phaseinjector1_csrfield_cas);
- end else begin
- litedramcore_csr_dfi_p1_cas_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p1_cas_n <= 1'd1;
+ if (litedramcore_phaseinjector1_command_issue_re) begin
+ litedramcore_csr_dfi_p1_cas_n <= (~litedramcore_phaseinjector1_csrfield_cas);
+ end else begin
+ litedramcore_csr_dfi_p1_cas_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p1_cs_n <= 1'd1;
- if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}};
- end else begin
- litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}};
- end
+ litedramcore_csr_dfi_p1_cs_n <= 1'd1;
+ if (litedramcore_phaseinjector1_command_issue_re) begin
+ litedramcore_csr_dfi_p1_cs_n <= {1{(~litedramcore_phaseinjector1_csrfield_cs)}};
+ end else begin
+ litedramcore_csr_dfi_p1_cs_n <= {1{1'd1}};
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p1_ras_n <= 1'd1;
- if (litedramcore_phaseinjector1_command_issue_re) begin
- litedramcore_csr_dfi_p1_ras_n <= (~litedramcore_phaseinjector1_csrfield_ras);
- end else begin
- litedramcore_csr_dfi_p1_ras_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p1_ras_n <= 1'd1;
+ if (litedramcore_phaseinjector1_command_issue_re) begin
+ litedramcore_csr_dfi_p1_ras_n <= (~litedramcore_phaseinjector1_csrfield_ras);
+ end else begin
+ litedramcore_csr_dfi_p1_ras_n <= 1'd1;
+ end
end
assign litedramcore_csr_dfi_p1_address = litedramcore_phaseinjector1_address_storage;
assign litedramcore_csr_dfi_p1_bank = litedramcore_phaseinjector1_baddress_storage;
assign litedramcore_csr_dfi_p1_wrdata = litedramcore_phaseinjector1_wrdata_storage;
assign litedramcore_csr_dfi_p1_wrdata_mask = 1'd0;
always @(*) begin
- litedramcore_csr_dfi_p2_we_n <= 1'd1;
- if (litedramcore_phaseinjector2_command_issue_re) begin
- litedramcore_csr_dfi_p2_we_n <= (~litedramcore_phaseinjector2_csrfield_we);
- end else begin
- litedramcore_csr_dfi_p2_we_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p2_we_n <= 1'd1;
+ if (litedramcore_phaseinjector2_command_issue_re) begin
+ litedramcore_csr_dfi_p2_we_n <= (~litedramcore_phaseinjector2_csrfield_we);
+ end else begin
+ litedramcore_csr_dfi_p2_we_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p2_cas_n <= 1'd1;
- if (litedramcore_phaseinjector2_command_issue_re) begin
- litedramcore_csr_dfi_p2_cas_n <= (~litedramcore_phaseinjector2_csrfield_cas);
- end else begin
- litedramcore_csr_dfi_p2_cas_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p2_cas_n <= 1'd1;
+ if (litedramcore_phaseinjector2_command_issue_re) begin
+ litedramcore_csr_dfi_p2_cas_n <= (~litedramcore_phaseinjector2_csrfield_cas);
+ end else begin
+ litedramcore_csr_dfi_p2_cas_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p2_cs_n <= 1'd1;
- if (litedramcore_phaseinjector2_command_issue_re) begin
- litedramcore_csr_dfi_p2_cs_n <= {1{(~litedramcore_phaseinjector2_csrfield_cs)}};
- end else begin
- litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}};
- end
+ litedramcore_csr_dfi_p2_cs_n <= 1'd1;
+ if (litedramcore_phaseinjector2_command_issue_re) begin
+ litedramcore_csr_dfi_p2_cs_n <= {1{(~litedramcore_phaseinjector2_csrfield_cs)}};
+ end else begin
+ litedramcore_csr_dfi_p2_cs_n <= {1{1'd1}};
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p2_ras_n <= 1'd1;
- if (litedramcore_phaseinjector2_command_issue_re) begin
- litedramcore_csr_dfi_p2_ras_n <= (~litedramcore_phaseinjector2_csrfield_ras);
- end else begin
- litedramcore_csr_dfi_p2_ras_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p2_ras_n <= 1'd1;
+ if (litedramcore_phaseinjector2_command_issue_re) begin
+ litedramcore_csr_dfi_p2_ras_n <= (~litedramcore_phaseinjector2_csrfield_ras);
+ end else begin
+ litedramcore_csr_dfi_p2_ras_n <= 1'd1;
+ end
end
assign litedramcore_csr_dfi_p2_address = litedramcore_phaseinjector2_address_storage;
assign litedramcore_csr_dfi_p2_bank = litedramcore_phaseinjector2_baddress_storage;
assign litedramcore_csr_dfi_p2_wrdata = litedramcore_phaseinjector2_wrdata_storage;
assign litedramcore_csr_dfi_p2_wrdata_mask = 1'd0;
always @(*) begin
- litedramcore_csr_dfi_p3_we_n <= 1'd1;
- if (litedramcore_phaseinjector3_command_issue_re) begin
- litedramcore_csr_dfi_p3_we_n <= (~litedramcore_phaseinjector3_csrfield_we);
- end else begin
- litedramcore_csr_dfi_p3_we_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p3_we_n <= 1'd1;
+ if (litedramcore_phaseinjector3_command_issue_re) begin
+ litedramcore_csr_dfi_p3_we_n <= (~litedramcore_phaseinjector3_csrfield_we);
+ end else begin
+ litedramcore_csr_dfi_p3_we_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p3_cas_n <= 1'd1;
- if (litedramcore_phaseinjector3_command_issue_re) begin
- litedramcore_csr_dfi_p3_cas_n <= (~litedramcore_phaseinjector3_csrfield_cas);
- end else begin
- litedramcore_csr_dfi_p3_cas_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p3_cas_n <= 1'd1;
+ if (litedramcore_phaseinjector3_command_issue_re) begin
+ litedramcore_csr_dfi_p3_cas_n <= (~litedramcore_phaseinjector3_csrfield_cas);
+ end else begin
+ litedramcore_csr_dfi_p3_cas_n <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p3_cs_n <= 1'd1;
- if (litedramcore_phaseinjector3_command_issue_re) begin
- litedramcore_csr_dfi_p3_cs_n <= {1{(~litedramcore_phaseinjector3_csrfield_cs)}};
- end else begin
- litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}};
- end
+ litedramcore_csr_dfi_p3_cs_n <= 1'd1;
+ if (litedramcore_phaseinjector3_command_issue_re) begin
+ litedramcore_csr_dfi_p3_cs_n <= {1{(~litedramcore_phaseinjector3_csrfield_cs)}};
+ end else begin
+ litedramcore_csr_dfi_p3_cs_n <= {1{1'd1}};
+ end
end
always @(*) begin
- litedramcore_csr_dfi_p3_ras_n <= 1'd1;
- if (litedramcore_phaseinjector3_command_issue_re) begin
- litedramcore_csr_dfi_p3_ras_n <= (~litedramcore_phaseinjector3_csrfield_ras);
- end else begin
- litedramcore_csr_dfi_p3_ras_n <= 1'd1;
- end
+ litedramcore_csr_dfi_p3_ras_n <= 1'd1;
+ if (litedramcore_phaseinjector3_command_issue_re) begin
+ litedramcore_csr_dfi_p3_ras_n <= (~litedramcore_phaseinjector3_csrfield_ras);
+ end else begin
+ litedramcore_csr_dfi_p3_ras_n <= 1'd1;
+ end
end
assign litedramcore_csr_dfi_p3_address = litedramcore_phaseinjector3_address_storage;
assign litedramcore_csr_dfi_p3_bank = litedramcore_phaseinjector3_baddress_storage;
assign litedramcore_zqcs_timer_done0 = litedramcore_zqcs_timer_done1;
assign litedramcore_zqcs_timer_count0 = litedramcore_zqcs_timer_count1;
always @(*) begin
- litedramcore_refresher_next_state <= 2'd0;
- litedramcore_refresher_next_state <= litedramcore_refresher_state;
- case (litedramcore_refresher_state)
- 1'd1: begin
- if (litedramcore_cmd_ready) begin
- litedramcore_refresher_next_state <= 2'd2;
- end
- end
- 2'd2: begin
- if (litedramcore_sequencer_done0) begin
- if (litedramcore_wants_zqcs) begin
- litedramcore_refresher_next_state <= 2'd3;
- end else begin
- litedramcore_refresher_next_state <= 1'd0;
- end
- end
- end
- 2'd3: begin
- if (litedramcore_zqcs_executer_done) begin
- litedramcore_refresher_next_state <= 1'd0;
- end
- end
- default: begin
- if (1'd1) begin
- if (litedramcore_wants_refresh) begin
- litedramcore_refresher_next_state <= 1'd1;
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_zqcs_executer_start <= 1'd0;
- case (litedramcore_refresher_state)
- 1'd1: begin
- end
- 2'd2: begin
- if (litedramcore_sequencer_done0) begin
- if (litedramcore_wants_zqcs) begin
- litedramcore_zqcs_executer_start <= 1'd1;
- end else begin
- end
- end
- end
- 2'd3: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_cmd_last <= 1'd0;
- case (litedramcore_refresher_state)
- 1'd1: begin
- end
- 2'd2: begin
- if (litedramcore_sequencer_done0) begin
- if (litedramcore_wants_zqcs) begin
- end else begin
- litedramcore_cmd_last <= 1'd1;
- end
- end
- end
- 2'd3: begin
- if (litedramcore_zqcs_executer_done) begin
- litedramcore_cmd_last <= 1'd1;
- end
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_sequencer_start0 <= 1'd0;
- case (litedramcore_refresher_state)
- 1'd1: begin
- if (litedramcore_cmd_ready) begin
- litedramcore_sequencer_start0 <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_cmd_valid <= 1'd0;
- case (litedramcore_refresher_state)
- 1'd1: begin
- litedramcore_cmd_valid <= 1'd1;
- end
- 2'd2: begin
- litedramcore_cmd_valid <= 1'd1;
- if (litedramcore_sequencer_done0) begin
- if (litedramcore_wants_zqcs) begin
- end else begin
- litedramcore_cmd_valid <= 1'd0;
- end
- end
- end
- 2'd3: begin
- litedramcore_cmd_valid <= 1'd1;
- if (litedramcore_zqcs_executer_done) begin
- litedramcore_cmd_valid <= 1'd0;
- end
- end
- default: begin
- end
- endcase
-end
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine0_req_valid;
-assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine0_req_we;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine0_req_addr;
-assign litedramcore_bankmachine0_cmd_buffer_sink_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine0_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine0_cmd_buffer_sink_first = litedramcore_bankmachine0_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine0_cmd_buffer_sink_last = litedramcore_bankmachine0_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine0_cmd_buffer_sink_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine0_cmd_buffer_sink_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine0_cmd_buffer_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid);
-assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine0_cmd_buffer_source_valid);
-assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7]);
+ litedramcore_refresher_next_state <= 2'd0;
+ litedramcore_refresher_next_state <= litedramcore_refresher_state;
+ case (litedramcore_refresher_state)
+ 1'd1: begin
+ if (litedramcore_cmd_ready) begin
+ litedramcore_refresher_next_state <= 2'd2;
+ end
+ end
+ 2'd2: begin
+ if (litedramcore_sequencer_done0) begin
+ if (litedramcore_wants_zqcs) begin
+ litedramcore_refresher_next_state <= 2'd3;
+ end else begin
+ litedramcore_refresher_next_state <= 1'd0;
+ end
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_zqcs_executer_done) begin
+ litedramcore_refresher_next_state <= 1'd0;
+ end
+ end
+ default: begin
+ if (1'd1) begin
+ if (litedramcore_wants_refresh) begin
+ litedramcore_refresher_next_state <= 1'd1;
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_zqcs_executer_start <= 1'd0;
+ case (litedramcore_refresher_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ if (litedramcore_sequencer_done0) begin
+ if (litedramcore_wants_zqcs) begin
+ litedramcore_zqcs_executer_start <= 1'd1;
+ end else begin
+ end
+ end
+ end
+ 2'd3: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_cmd_last <= 1'd0;
+ case (litedramcore_refresher_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ if (litedramcore_sequencer_done0) begin
+ if (litedramcore_wants_zqcs) begin
+ end else begin
+ litedramcore_cmd_last <= 1'd1;
+ end
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_zqcs_executer_done) begin
+ litedramcore_cmd_last <= 1'd1;
+ end
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_sequencer_start0 <= 1'd0;
+ case (litedramcore_refresher_state)
+ 1'd1: begin
+ if (litedramcore_cmd_ready) begin
+ litedramcore_sequencer_start0 <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_cmd_valid <= 1'd0;
+ case (litedramcore_refresher_state)
+ 1'd1: begin
+ litedramcore_cmd_valid <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_cmd_valid <= 1'd1;
+ if (litedramcore_sequencer_done0) begin
+ if (litedramcore_wants_zqcs) begin
+ end else begin
+ litedramcore_cmd_valid <= 1'd0;
+ end
+ end
+ end
+ 2'd3: begin
+ litedramcore_cmd_valid <= 1'd1;
+ if (litedramcore_zqcs_executer_done) begin
+ litedramcore_cmd_valid <= 1'd0;
+ end
+ end
+ default: begin
+ end
+ endcase
+end
+assign litedramcore_bankmachine0_sink_valid = litedramcore_bankmachine0_req_valid;
+assign litedramcore_bankmachine0_req_ready = litedramcore_bankmachine0_sink_ready;
+assign litedramcore_bankmachine0_sink_payload_we = litedramcore_bankmachine0_req_we;
+assign litedramcore_bankmachine0_sink_payload_addr = litedramcore_bankmachine0_req_addr;
+assign litedramcore_bankmachine0_sink_sink_valid = litedramcore_bankmachine0_source_valid;
+assign litedramcore_bankmachine0_source_ready = litedramcore_bankmachine0_sink_sink_ready;
+assign litedramcore_bankmachine0_sink_sink_first = litedramcore_bankmachine0_source_first;
+assign litedramcore_bankmachine0_sink_sink_last = litedramcore_bankmachine0_source_last;
+assign litedramcore_bankmachine0_sink_sink_payload_we = litedramcore_bankmachine0_source_payload_we;
+assign litedramcore_bankmachine0_sink_sink_payload_addr = litedramcore_bankmachine0_source_payload_addr;
+assign litedramcore_bankmachine0_source_source_ready = (litedramcore_bankmachine0_req_wdata_ready | litedramcore_bankmachine0_req_rdata_valid);
+assign litedramcore_bankmachine0_req_lock = (litedramcore_bankmachine0_source_valid | litedramcore_bankmachine0_source_source_valid);
+assign litedramcore_bankmachine0_row_hit = (litedramcore_bankmachine0_row == litedramcore_bankmachine0_source_source_payload_addr[20:7]);
assign litedramcore_bankmachine0_cmd_payload_ba = 1'd0;
always @(*) begin
- litedramcore_bankmachine0_cmd_payload_a <= 14'd0;
- if (litedramcore_bankmachine0_row_col_n_addr_sel) begin
- litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7];
- end else begin
- litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine0_cmd_payload_a <= 14'd0;
+ if (litedramcore_bankmachine0_row_col_n_addr_sel) begin
+ litedramcore_bankmachine0_cmd_payload_a <= litedramcore_bankmachine0_source_source_payload_addr[20:7];
+ end else begin
+ litedramcore_bankmachine0_cmd_payload_a <= ((litedramcore_bankmachine0_auto_precharge <<< 4'd10) | {litedramcore_bankmachine0_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine0_twtpcon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_cmd_payload_is_write);
assign litedramcore_bankmachine0_trccon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
assign litedramcore_bankmachine0_trascon_valid = ((litedramcore_bankmachine0_cmd_valid & litedramcore_bankmachine0_cmd_ready) & litedramcore_bankmachine0_row_open);
always @(*) begin
- litedramcore_bankmachine0_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine0_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7])) begin
- litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din = {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign {litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_first = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_last = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re = litedramcore_bankmachine0_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine0_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine0_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_din;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable | litedramcore_bankmachine0_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_re);
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine0_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout = litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable = (litedramcore_bankmachine0_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine0_cmd_buffer_sink_ready = ((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine0_next_state <= 4'd0;
- litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- if (litedramcore_bankmachine0_cmd_ready) begin
- litedramcore_bankmachine0_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- if (litedramcore_bankmachine0_cmd_ready) begin
- litedramcore_bankmachine0_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine0_refresh_req)) begin
- litedramcore_bankmachine0_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine0_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine0_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine0_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine0_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- litedramcore_bankmachine0_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin
- litedramcore_bankmachine0_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine0_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine0_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine0_twtpcon_ready) begin
- litedramcore_bankmachine0_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- litedramcore_bankmachine0_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_row_open <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_row_close <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- litedramcore_bankmachine0_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine0_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine0_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine0_trccon_ready) begin
- litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine0_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine0_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine0_row_opened) begin
- if (litedramcore_bankmachine0_row_hit) begin
- if (litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine1_req_valid;
-assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine1_req_we;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine1_req_addr;
-assign litedramcore_bankmachine1_cmd_buffer_sink_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine1_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine1_cmd_buffer_sink_first = litedramcore_bankmachine1_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine1_cmd_buffer_sink_last = litedramcore_bankmachine1_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine1_cmd_buffer_sink_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine1_cmd_buffer_sink_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine1_cmd_buffer_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid);
-assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine1_cmd_buffer_source_valid);
-assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7]);
+ litedramcore_bankmachine0_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine0_source_valid & litedramcore_bankmachine0_source_source_valid)) begin
+ if ((litedramcore_bankmachine0_source_payload_addr[20:7] != litedramcore_bankmachine0_source_source_payload_addr[20:7])) begin
+ litedramcore_bankmachine0_auto_precharge <= (litedramcore_bankmachine0_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine0_syncfifo0_din = {litedramcore_bankmachine0_fifo_in_last, litedramcore_bankmachine0_fifo_in_first, litedramcore_bankmachine0_fifo_in_payload_addr, litedramcore_bankmachine0_fifo_in_payload_we};
+assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout;
+assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout;
+assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout;
+assign {litedramcore_bankmachine0_fifo_out_last, litedramcore_bankmachine0_fifo_out_first, litedramcore_bankmachine0_fifo_out_payload_addr, litedramcore_bankmachine0_fifo_out_payload_we} = litedramcore_bankmachine0_syncfifo0_dout;
+assign litedramcore_bankmachine0_sink_ready = litedramcore_bankmachine0_syncfifo0_writable;
+assign litedramcore_bankmachine0_syncfifo0_we = litedramcore_bankmachine0_sink_valid;
+assign litedramcore_bankmachine0_fifo_in_first = litedramcore_bankmachine0_sink_first;
+assign litedramcore_bankmachine0_fifo_in_last = litedramcore_bankmachine0_sink_last;
+assign litedramcore_bankmachine0_fifo_in_payload_we = litedramcore_bankmachine0_sink_payload_we;
+assign litedramcore_bankmachine0_fifo_in_payload_addr = litedramcore_bankmachine0_sink_payload_addr;
+assign litedramcore_bankmachine0_source_valid = litedramcore_bankmachine0_syncfifo0_readable;
+assign litedramcore_bankmachine0_source_first = litedramcore_bankmachine0_fifo_out_first;
+assign litedramcore_bankmachine0_source_last = litedramcore_bankmachine0_fifo_out_last;
+assign litedramcore_bankmachine0_source_payload_we = litedramcore_bankmachine0_fifo_out_payload_we;
+assign litedramcore_bankmachine0_source_payload_addr = litedramcore_bankmachine0_fifo_out_payload_addr;
+assign litedramcore_bankmachine0_syncfifo0_re = litedramcore_bankmachine0_source_ready;
+always @(*) begin
+ litedramcore_bankmachine0_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine0_replace) begin
+ litedramcore_bankmachine0_wrport_adr <= (litedramcore_bankmachine0_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine0_wrport_adr <= litedramcore_bankmachine0_produce;
+ end
+end
+assign litedramcore_bankmachine0_wrport_dat_w = litedramcore_bankmachine0_syncfifo0_din;
+assign litedramcore_bankmachine0_wrport_we = (litedramcore_bankmachine0_syncfifo0_we & (litedramcore_bankmachine0_syncfifo0_writable | litedramcore_bankmachine0_replace));
+assign litedramcore_bankmachine0_do_read = (litedramcore_bankmachine0_syncfifo0_readable & litedramcore_bankmachine0_syncfifo0_re);
+assign litedramcore_bankmachine0_rdport_adr = litedramcore_bankmachine0_consume;
+assign litedramcore_bankmachine0_syncfifo0_dout = litedramcore_bankmachine0_rdport_dat_r;
+assign litedramcore_bankmachine0_syncfifo0_writable = (litedramcore_bankmachine0_level != 5'd16);
+assign litedramcore_bankmachine0_syncfifo0_readable = (litedramcore_bankmachine0_level != 1'd0);
+assign litedramcore_bankmachine0_pipe_valid_sink_ready = ((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready);
+assign litedramcore_bankmachine0_pipe_valid_sink_valid = litedramcore_bankmachine0_sink_sink_valid;
+assign litedramcore_bankmachine0_sink_sink_ready = litedramcore_bankmachine0_pipe_valid_sink_ready;
+assign litedramcore_bankmachine0_pipe_valid_sink_first = litedramcore_bankmachine0_sink_sink_first;
+assign litedramcore_bankmachine0_pipe_valid_sink_last = litedramcore_bankmachine0_sink_sink_last;
+assign litedramcore_bankmachine0_pipe_valid_sink_payload_we = litedramcore_bankmachine0_sink_sink_payload_we;
+assign litedramcore_bankmachine0_pipe_valid_sink_payload_addr = litedramcore_bankmachine0_sink_sink_payload_addr;
+assign litedramcore_bankmachine0_source_source_valid = litedramcore_bankmachine0_pipe_valid_source_valid;
+assign litedramcore_bankmachine0_pipe_valid_source_ready = litedramcore_bankmachine0_source_source_ready;
+assign litedramcore_bankmachine0_source_source_first = litedramcore_bankmachine0_pipe_valid_source_first;
+assign litedramcore_bankmachine0_source_source_last = litedramcore_bankmachine0_pipe_valid_source_last;
+assign litedramcore_bankmachine0_source_source_payload_we = litedramcore_bankmachine0_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine0_source_source_payload_addr = litedramcore_bankmachine0_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine0_next_state <= 4'd0;
+ litedramcore_bankmachine0_next_state <= litedramcore_bankmachine0_state;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ if (litedramcore_bankmachine0_cmd_ready) begin
+ litedramcore_bankmachine0_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ if (litedramcore_bankmachine0_cmd_ready) begin
+ litedramcore_bankmachine0_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine0_refresh_req)) begin
+ litedramcore_bankmachine0_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine0_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine0_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine0_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine0_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ litedramcore_bankmachine0_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if ((litedramcore_bankmachine0_cmd_ready & litedramcore_bankmachine0_auto_precharge)) begin
+ litedramcore_bankmachine0_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine0_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine0_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if (litedramcore_bankmachine0_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine0_req_rdata_valid <= litedramcore_bankmachine0_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine0_twtpcon_ready) begin
+ litedramcore_bankmachine0_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_row_open <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ litedramcore_bankmachine0_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_row_close <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ litedramcore_bankmachine0_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine0_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine0_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if (litedramcore_bankmachine0_source_source_payload_we) begin
+ litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine0_twtpcon_ready & litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine0_trccon_ready) begin
+ litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if (litedramcore_bankmachine0_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if (litedramcore_bankmachine0_source_source_payload_we) begin
+ litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine0_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine0_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine0_source_source_valid) begin
+ if (litedramcore_bankmachine0_row_opened) begin
+ if (litedramcore_bankmachine0_row_hit) begin
+ if (litedramcore_bankmachine0_source_source_payload_we) begin
+ litedramcore_bankmachine0_req_wdata_ready <= litedramcore_bankmachine0_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+assign litedramcore_bankmachine1_sink_valid = litedramcore_bankmachine1_req_valid;
+assign litedramcore_bankmachine1_req_ready = litedramcore_bankmachine1_sink_ready;
+assign litedramcore_bankmachine1_sink_payload_we = litedramcore_bankmachine1_req_we;
+assign litedramcore_bankmachine1_sink_payload_addr = litedramcore_bankmachine1_req_addr;
+assign litedramcore_bankmachine1_sink_sink_valid = litedramcore_bankmachine1_source_valid;
+assign litedramcore_bankmachine1_source_ready = litedramcore_bankmachine1_sink_sink_ready;
+assign litedramcore_bankmachine1_sink_sink_first = litedramcore_bankmachine1_source_first;
+assign litedramcore_bankmachine1_sink_sink_last = litedramcore_bankmachine1_source_last;
+assign litedramcore_bankmachine1_sink_sink_payload_we = litedramcore_bankmachine1_source_payload_we;
+assign litedramcore_bankmachine1_sink_sink_payload_addr = litedramcore_bankmachine1_source_payload_addr;
+assign litedramcore_bankmachine1_source_source_ready = (litedramcore_bankmachine1_req_wdata_ready | litedramcore_bankmachine1_req_rdata_valid);
+assign litedramcore_bankmachine1_req_lock = (litedramcore_bankmachine1_source_valid | litedramcore_bankmachine1_source_source_valid);
+assign litedramcore_bankmachine1_row_hit = (litedramcore_bankmachine1_row == litedramcore_bankmachine1_source_source_payload_addr[20:7]);
assign litedramcore_bankmachine1_cmd_payload_ba = 1'd1;
always @(*) begin
- litedramcore_bankmachine1_cmd_payload_a <= 14'd0;
- if (litedramcore_bankmachine1_row_col_n_addr_sel) begin
- litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7];
- end else begin
- litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine1_cmd_payload_a <= 14'd0;
+ if (litedramcore_bankmachine1_row_col_n_addr_sel) begin
+ litedramcore_bankmachine1_cmd_payload_a <= litedramcore_bankmachine1_source_source_payload_addr[20:7];
+ end else begin
+ litedramcore_bankmachine1_cmd_payload_a <= ((litedramcore_bankmachine1_auto_precharge <<< 4'd10) | {litedramcore_bankmachine1_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine1_twtpcon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_cmd_payload_is_write);
assign litedramcore_bankmachine1_trccon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
assign litedramcore_bankmachine1_trascon_valid = ((litedramcore_bankmachine1_cmd_valid & litedramcore_bankmachine1_cmd_ready) & litedramcore_bankmachine1_row_open);
always @(*) begin
- litedramcore_bankmachine1_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine1_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7])) begin
- litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din = {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign {litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_first = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_last = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re = litedramcore_bankmachine1_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine1_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine1_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_din;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable | litedramcore_bankmachine1_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_re);
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine1_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout = litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable = (litedramcore_bankmachine1_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine1_cmd_buffer_sink_ready = ((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine1_next_state <= 4'd0;
- litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- if (litedramcore_bankmachine1_cmd_ready) begin
- litedramcore_bankmachine1_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- if (litedramcore_bankmachine1_cmd_ready) begin
- litedramcore_bankmachine1_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine1_refresh_req)) begin
- litedramcore_bankmachine1_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine1_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine1_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine1_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine1_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- litedramcore_bankmachine1_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin
- litedramcore_bankmachine1_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine1_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine1_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine1_twtpcon_ready) begin
- litedramcore_bankmachine1_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- litedramcore_bankmachine1_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_row_open <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_row_close <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- litedramcore_bankmachine1_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine1_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine1_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine1_trccon_ready) begin
- litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine1_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine1_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine1_row_opened) begin
- if (litedramcore_bankmachine1_row_hit) begin
- if (litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine2_req_valid;
-assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine2_req_we;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine2_req_addr;
-assign litedramcore_bankmachine2_cmd_buffer_sink_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine2_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine2_cmd_buffer_sink_first = litedramcore_bankmachine2_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine2_cmd_buffer_sink_last = litedramcore_bankmachine2_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine2_cmd_buffer_sink_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine2_cmd_buffer_sink_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine2_cmd_buffer_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid);
-assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine2_cmd_buffer_source_valid);
-assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7]);
+ litedramcore_bankmachine1_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine1_source_valid & litedramcore_bankmachine1_source_source_valid)) begin
+ if ((litedramcore_bankmachine1_source_payload_addr[20:7] != litedramcore_bankmachine1_source_source_payload_addr[20:7])) begin
+ litedramcore_bankmachine1_auto_precharge <= (litedramcore_bankmachine1_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine1_syncfifo1_din = {litedramcore_bankmachine1_fifo_in_last, litedramcore_bankmachine1_fifo_in_first, litedramcore_bankmachine1_fifo_in_payload_addr, litedramcore_bankmachine1_fifo_in_payload_we};
+assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout;
+assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout;
+assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout;
+assign {litedramcore_bankmachine1_fifo_out_last, litedramcore_bankmachine1_fifo_out_first, litedramcore_bankmachine1_fifo_out_payload_addr, litedramcore_bankmachine1_fifo_out_payload_we} = litedramcore_bankmachine1_syncfifo1_dout;
+assign litedramcore_bankmachine1_sink_ready = litedramcore_bankmachine1_syncfifo1_writable;
+assign litedramcore_bankmachine1_syncfifo1_we = litedramcore_bankmachine1_sink_valid;
+assign litedramcore_bankmachine1_fifo_in_first = litedramcore_bankmachine1_sink_first;
+assign litedramcore_bankmachine1_fifo_in_last = litedramcore_bankmachine1_sink_last;
+assign litedramcore_bankmachine1_fifo_in_payload_we = litedramcore_bankmachine1_sink_payload_we;
+assign litedramcore_bankmachine1_fifo_in_payload_addr = litedramcore_bankmachine1_sink_payload_addr;
+assign litedramcore_bankmachine1_source_valid = litedramcore_bankmachine1_syncfifo1_readable;
+assign litedramcore_bankmachine1_source_first = litedramcore_bankmachine1_fifo_out_first;
+assign litedramcore_bankmachine1_source_last = litedramcore_bankmachine1_fifo_out_last;
+assign litedramcore_bankmachine1_source_payload_we = litedramcore_bankmachine1_fifo_out_payload_we;
+assign litedramcore_bankmachine1_source_payload_addr = litedramcore_bankmachine1_fifo_out_payload_addr;
+assign litedramcore_bankmachine1_syncfifo1_re = litedramcore_bankmachine1_source_ready;
+always @(*) begin
+ litedramcore_bankmachine1_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine1_replace) begin
+ litedramcore_bankmachine1_wrport_adr <= (litedramcore_bankmachine1_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine1_wrport_adr <= litedramcore_bankmachine1_produce;
+ end
+end
+assign litedramcore_bankmachine1_wrport_dat_w = litedramcore_bankmachine1_syncfifo1_din;
+assign litedramcore_bankmachine1_wrport_we = (litedramcore_bankmachine1_syncfifo1_we & (litedramcore_bankmachine1_syncfifo1_writable | litedramcore_bankmachine1_replace));
+assign litedramcore_bankmachine1_do_read = (litedramcore_bankmachine1_syncfifo1_readable & litedramcore_bankmachine1_syncfifo1_re);
+assign litedramcore_bankmachine1_rdport_adr = litedramcore_bankmachine1_consume;
+assign litedramcore_bankmachine1_syncfifo1_dout = litedramcore_bankmachine1_rdport_dat_r;
+assign litedramcore_bankmachine1_syncfifo1_writable = (litedramcore_bankmachine1_level != 5'd16);
+assign litedramcore_bankmachine1_syncfifo1_readable = (litedramcore_bankmachine1_level != 1'd0);
+assign litedramcore_bankmachine1_pipe_valid_sink_ready = ((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready);
+assign litedramcore_bankmachine1_pipe_valid_sink_valid = litedramcore_bankmachine1_sink_sink_valid;
+assign litedramcore_bankmachine1_sink_sink_ready = litedramcore_bankmachine1_pipe_valid_sink_ready;
+assign litedramcore_bankmachine1_pipe_valid_sink_first = litedramcore_bankmachine1_sink_sink_first;
+assign litedramcore_bankmachine1_pipe_valid_sink_last = litedramcore_bankmachine1_sink_sink_last;
+assign litedramcore_bankmachine1_pipe_valid_sink_payload_we = litedramcore_bankmachine1_sink_sink_payload_we;
+assign litedramcore_bankmachine1_pipe_valid_sink_payload_addr = litedramcore_bankmachine1_sink_sink_payload_addr;
+assign litedramcore_bankmachine1_source_source_valid = litedramcore_bankmachine1_pipe_valid_source_valid;
+assign litedramcore_bankmachine1_pipe_valid_source_ready = litedramcore_bankmachine1_source_source_ready;
+assign litedramcore_bankmachine1_source_source_first = litedramcore_bankmachine1_pipe_valid_source_first;
+assign litedramcore_bankmachine1_source_source_last = litedramcore_bankmachine1_pipe_valid_source_last;
+assign litedramcore_bankmachine1_source_source_payload_we = litedramcore_bankmachine1_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine1_source_source_payload_addr = litedramcore_bankmachine1_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine1_next_state <= 4'd0;
+ litedramcore_bankmachine1_next_state <= litedramcore_bankmachine1_state;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ if (litedramcore_bankmachine1_cmd_ready) begin
+ litedramcore_bankmachine1_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ if (litedramcore_bankmachine1_cmd_ready) begin
+ litedramcore_bankmachine1_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine1_refresh_req)) begin
+ litedramcore_bankmachine1_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine1_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine1_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine1_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine1_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ litedramcore_bankmachine1_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if ((litedramcore_bankmachine1_cmd_ready & litedramcore_bankmachine1_auto_precharge)) begin
+ litedramcore_bankmachine1_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine1_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine1_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if (litedramcore_bankmachine1_source_source_payload_we) begin
+ litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if (litedramcore_bankmachine1_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if (litedramcore_bankmachine1_source_source_payload_we) begin
+ litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if (litedramcore_bankmachine1_source_source_payload_we) begin
+ litedramcore_bankmachine1_req_wdata_ready <= litedramcore_bankmachine1_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ if (litedramcore_bankmachine1_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine1_req_rdata_valid <= litedramcore_bankmachine1_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine1_twtpcon_ready) begin
+ litedramcore_bankmachine1_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_row_open <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine1_twtpcon_ready & litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine1_trccon_ready) begin
+ litedramcore_bankmachine1_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine1_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine1_source_source_valid) begin
+ if (litedramcore_bankmachine1_row_opened) begin
+ if (litedramcore_bankmachine1_row_hit) begin
+ litedramcore_bankmachine1_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine1_row_close <= 1'd0;
+ case (litedramcore_bankmachine1_state)
+ 1'd1: begin
+ litedramcore_bankmachine1_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine1_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine1_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+assign litedramcore_bankmachine2_sink_valid = litedramcore_bankmachine2_req_valid;
+assign litedramcore_bankmachine2_req_ready = litedramcore_bankmachine2_sink_ready;
+assign litedramcore_bankmachine2_sink_payload_we = litedramcore_bankmachine2_req_we;
+assign litedramcore_bankmachine2_sink_payload_addr = litedramcore_bankmachine2_req_addr;
+assign litedramcore_bankmachine2_sink_sink_valid = litedramcore_bankmachine2_source_valid;
+assign litedramcore_bankmachine2_source_ready = litedramcore_bankmachine2_sink_sink_ready;
+assign litedramcore_bankmachine2_sink_sink_first = litedramcore_bankmachine2_source_first;
+assign litedramcore_bankmachine2_sink_sink_last = litedramcore_bankmachine2_source_last;
+assign litedramcore_bankmachine2_sink_sink_payload_we = litedramcore_bankmachine2_source_payload_we;
+assign litedramcore_bankmachine2_sink_sink_payload_addr = litedramcore_bankmachine2_source_payload_addr;
+assign litedramcore_bankmachine2_source_source_ready = (litedramcore_bankmachine2_req_wdata_ready | litedramcore_bankmachine2_req_rdata_valid);
+assign litedramcore_bankmachine2_req_lock = (litedramcore_bankmachine2_source_valid | litedramcore_bankmachine2_source_source_valid);
+assign litedramcore_bankmachine2_row_hit = (litedramcore_bankmachine2_row == litedramcore_bankmachine2_source_source_payload_addr[20:7]);
assign litedramcore_bankmachine2_cmd_payload_ba = 2'd2;
always @(*) begin
- litedramcore_bankmachine2_cmd_payload_a <= 14'd0;
- if (litedramcore_bankmachine2_row_col_n_addr_sel) begin
- litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7];
- end else begin
- litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine2_cmd_payload_a <= 14'd0;
+ if (litedramcore_bankmachine2_row_col_n_addr_sel) begin
+ litedramcore_bankmachine2_cmd_payload_a <= litedramcore_bankmachine2_source_source_payload_addr[20:7];
+ end else begin
+ litedramcore_bankmachine2_cmd_payload_a <= ((litedramcore_bankmachine2_auto_precharge <<< 4'd10) | {litedramcore_bankmachine2_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine2_twtpcon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_cmd_payload_is_write);
assign litedramcore_bankmachine2_trccon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
assign litedramcore_bankmachine2_trascon_valid = ((litedramcore_bankmachine2_cmd_valid & litedramcore_bankmachine2_cmd_ready) & litedramcore_bankmachine2_row_open);
always @(*) begin
- litedramcore_bankmachine2_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine2_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7])) begin
- litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din = {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign {litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_first = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_last = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re = litedramcore_bankmachine2_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine2_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine2_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_din;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable | litedramcore_bankmachine2_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_re);
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine2_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout = litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable = (litedramcore_bankmachine2_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine2_cmd_buffer_sink_ready = ((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine2_next_state <= 4'd0;
- litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- if (litedramcore_bankmachine2_cmd_ready) begin
- litedramcore_bankmachine2_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- if (litedramcore_bankmachine2_cmd_ready) begin
- litedramcore_bankmachine2_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine2_refresh_req)) begin
- litedramcore_bankmachine2_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine2_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine2_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine2_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine2_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- litedramcore_bankmachine2_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin
- litedramcore_bankmachine2_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine2_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine2_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine2_twtpcon_ready) begin
- litedramcore_bankmachine2_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- litedramcore_bankmachine2_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_row_open <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_row_close <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- litedramcore_bankmachine2_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine2_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine2_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine2_trccon_ready) begin
- litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine2_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine2_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine2_row_opened) begin
- if (litedramcore_bankmachine2_row_hit) begin
- if (litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine3_req_valid;
-assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine3_req_we;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine3_req_addr;
-assign litedramcore_bankmachine3_cmd_buffer_sink_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine3_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine3_cmd_buffer_sink_first = litedramcore_bankmachine3_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine3_cmd_buffer_sink_last = litedramcore_bankmachine3_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine3_cmd_buffer_sink_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine3_cmd_buffer_sink_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine3_cmd_buffer_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid);
-assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine3_cmd_buffer_source_valid);
-assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7]);
+ litedramcore_bankmachine2_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine2_source_valid & litedramcore_bankmachine2_source_source_valid)) begin
+ if ((litedramcore_bankmachine2_source_payload_addr[20:7] != litedramcore_bankmachine2_source_source_payload_addr[20:7])) begin
+ litedramcore_bankmachine2_auto_precharge <= (litedramcore_bankmachine2_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine2_syncfifo2_din = {litedramcore_bankmachine2_fifo_in_last, litedramcore_bankmachine2_fifo_in_first, litedramcore_bankmachine2_fifo_in_payload_addr, litedramcore_bankmachine2_fifo_in_payload_we};
+assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout;
+assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout;
+assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout;
+assign {litedramcore_bankmachine2_fifo_out_last, litedramcore_bankmachine2_fifo_out_first, litedramcore_bankmachine2_fifo_out_payload_addr, litedramcore_bankmachine2_fifo_out_payload_we} = litedramcore_bankmachine2_syncfifo2_dout;
+assign litedramcore_bankmachine2_sink_ready = litedramcore_bankmachine2_syncfifo2_writable;
+assign litedramcore_bankmachine2_syncfifo2_we = litedramcore_bankmachine2_sink_valid;
+assign litedramcore_bankmachine2_fifo_in_first = litedramcore_bankmachine2_sink_first;
+assign litedramcore_bankmachine2_fifo_in_last = litedramcore_bankmachine2_sink_last;
+assign litedramcore_bankmachine2_fifo_in_payload_we = litedramcore_bankmachine2_sink_payload_we;
+assign litedramcore_bankmachine2_fifo_in_payload_addr = litedramcore_bankmachine2_sink_payload_addr;
+assign litedramcore_bankmachine2_source_valid = litedramcore_bankmachine2_syncfifo2_readable;
+assign litedramcore_bankmachine2_source_first = litedramcore_bankmachine2_fifo_out_first;
+assign litedramcore_bankmachine2_source_last = litedramcore_bankmachine2_fifo_out_last;
+assign litedramcore_bankmachine2_source_payload_we = litedramcore_bankmachine2_fifo_out_payload_we;
+assign litedramcore_bankmachine2_source_payload_addr = litedramcore_bankmachine2_fifo_out_payload_addr;
+assign litedramcore_bankmachine2_syncfifo2_re = litedramcore_bankmachine2_source_ready;
+always @(*) begin
+ litedramcore_bankmachine2_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine2_replace) begin
+ litedramcore_bankmachine2_wrport_adr <= (litedramcore_bankmachine2_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine2_wrport_adr <= litedramcore_bankmachine2_produce;
+ end
+end
+assign litedramcore_bankmachine2_wrport_dat_w = litedramcore_bankmachine2_syncfifo2_din;
+assign litedramcore_bankmachine2_wrport_we = (litedramcore_bankmachine2_syncfifo2_we & (litedramcore_bankmachine2_syncfifo2_writable | litedramcore_bankmachine2_replace));
+assign litedramcore_bankmachine2_do_read = (litedramcore_bankmachine2_syncfifo2_readable & litedramcore_bankmachine2_syncfifo2_re);
+assign litedramcore_bankmachine2_rdport_adr = litedramcore_bankmachine2_consume;
+assign litedramcore_bankmachine2_syncfifo2_dout = litedramcore_bankmachine2_rdport_dat_r;
+assign litedramcore_bankmachine2_syncfifo2_writable = (litedramcore_bankmachine2_level != 5'd16);
+assign litedramcore_bankmachine2_syncfifo2_readable = (litedramcore_bankmachine2_level != 1'd0);
+assign litedramcore_bankmachine2_pipe_valid_sink_ready = ((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready);
+assign litedramcore_bankmachine2_pipe_valid_sink_valid = litedramcore_bankmachine2_sink_sink_valid;
+assign litedramcore_bankmachine2_sink_sink_ready = litedramcore_bankmachine2_pipe_valid_sink_ready;
+assign litedramcore_bankmachine2_pipe_valid_sink_first = litedramcore_bankmachine2_sink_sink_first;
+assign litedramcore_bankmachine2_pipe_valid_sink_last = litedramcore_bankmachine2_sink_sink_last;
+assign litedramcore_bankmachine2_pipe_valid_sink_payload_we = litedramcore_bankmachine2_sink_sink_payload_we;
+assign litedramcore_bankmachine2_pipe_valid_sink_payload_addr = litedramcore_bankmachine2_sink_sink_payload_addr;
+assign litedramcore_bankmachine2_source_source_valid = litedramcore_bankmachine2_pipe_valid_source_valid;
+assign litedramcore_bankmachine2_pipe_valid_source_ready = litedramcore_bankmachine2_source_source_ready;
+assign litedramcore_bankmachine2_source_source_first = litedramcore_bankmachine2_pipe_valid_source_first;
+assign litedramcore_bankmachine2_source_source_last = litedramcore_bankmachine2_pipe_valid_source_last;
+assign litedramcore_bankmachine2_source_source_payload_we = litedramcore_bankmachine2_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine2_source_source_payload_addr = litedramcore_bankmachine2_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine2_next_state <= 4'd0;
+ litedramcore_bankmachine2_next_state <= litedramcore_bankmachine2_state;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ if (litedramcore_bankmachine2_cmd_ready) begin
+ litedramcore_bankmachine2_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ if (litedramcore_bankmachine2_cmd_ready) begin
+ litedramcore_bankmachine2_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine2_refresh_req)) begin
+ litedramcore_bankmachine2_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine2_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine2_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine2_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine2_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ litedramcore_bankmachine2_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if ((litedramcore_bankmachine2_cmd_ready & litedramcore_bankmachine2_auto_precharge)) begin
+ litedramcore_bankmachine2_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine2_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine2_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if (litedramcore_bankmachine2_source_source_payload_we) begin
+ litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if (litedramcore_bankmachine2_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if (litedramcore_bankmachine2_source_source_payload_we) begin
+ litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if (litedramcore_bankmachine2_source_source_payload_we) begin
+ litedramcore_bankmachine2_req_wdata_ready <= litedramcore_bankmachine2_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ if (litedramcore_bankmachine2_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine2_req_rdata_valid <= litedramcore_bankmachine2_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine2_twtpcon_ready) begin
+ litedramcore_bankmachine2_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_row_open <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine2_twtpcon_ready & litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine2_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine2_source_source_valid) begin
+ if (litedramcore_bankmachine2_row_opened) begin
+ if (litedramcore_bankmachine2_row_hit) begin
+ litedramcore_bankmachine2_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_row_close <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ litedramcore_bankmachine2_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine2_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine2_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine2_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine2_trccon_ready) begin
+ litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+assign litedramcore_bankmachine3_sink_valid = litedramcore_bankmachine3_req_valid;
+assign litedramcore_bankmachine3_req_ready = litedramcore_bankmachine3_sink_ready;
+assign litedramcore_bankmachine3_sink_payload_we = litedramcore_bankmachine3_req_we;
+assign litedramcore_bankmachine3_sink_payload_addr = litedramcore_bankmachine3_req_addr;
+assign litedramcore_bankmachine3_sink_sink_valid = litedramcore_bankmachine3_source_valid;
+assign litedramcore_bankmachine3_source_ready = litedramcore_bankmachine3_sink_sink_ready;
+assign litedramcore_bankmachine3_sink_sink_first = litedramcore_bankmachine3_source_first;
+assign litedramcore_bankmachine3_sink_sink_last = litedramcore_bankmachine3_source_last;
+assign litedramcore_bankmachine3_sink_sink_payload_we = litedramcore_bankmachine3_source_payload_we;
+assign litedramcore_bankmachine3_sink_sink_payload_addr = litedramcore_bankmachine3_source_payload_addr;
+assign litedramcore_bankmachine3_source_source_ready = (litedramcore_bankmachine3_req_wdata_ready | litedramcore_bankmachine3_req_rdata_valid);
+assign litedramcore_bankmachine3_req_lock = (litedramcore_bankmachine3_source_valid | litedramcore_bankmachine3_source_source_valid);
+assign litedramcore_bankmachine3_row_hit = (litedramcore_bankmachine3_row == litedramcore_bankmachine3_source_source_payload_addr[20:7]);
assign litedramcore_bankmachine3_cmd_payload_ba = 2'd3;
always @(*) begin
- litedramcore_bankmachine3_cmd_payload_a <= 14'd0;
- if (litedramcore_bankmachine3_row_col_n_addr_sel) begin
- litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7];
- end else begin
- litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine3_cmd_payload_a <= 14'd0;
+ if (litedramcore_bankmachine3_row_col_n_addr_sel) begin
+ litedramcore_bankmachine3_cmd_payload_a <= litedramcore_bankmachine3_source_source_payload_addr[20:7];
+ end else begin
+ litedramcore_bankmachine3_cmd_payload_a <= ((litedramcore_bankmachine3_auto_precharge <<< 4'd10) | {litedramcore_bankmachine3_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine3_twtpcon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_cmd_payload_is_write);
assign litedramcore_bankmachine3_trccon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
assign litedramcore_bankmachine3_trascon_valid = ((litedramcore_bankmachine3_cmd_valid & litedramcore_bankmachine3_cmd_ready) & litedramcore_bankmachine3_row_open);
always @(*) begin
- litedramcore_bankmachine3_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine3_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7])) begin
- litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din = {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign {litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_first = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_last = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re = litedramcore_bankmachine3_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine3_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine3_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_din;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable | litedramcore_bankmachine3_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_re);
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine3_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout = litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable = (litedramcore_bankmachine3_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine3_cmd_buffer_sink_ready = ((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine3_next_state <= 4'd0;
- litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- if (litedramcore_bankmachine3_cmd_ready) begin
- litedramcore_bankmachine3_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- if (litedramcore_bankmachine3_cmd_ready) begin
- litedramcore_bankmachine3_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine3_refresh_req)) begin
- litedramcore_bankmachine3_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine3_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine3_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine3_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine3_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- litedramcore_bankmachine3_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin
- litedramcore_bankmachine3_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine3_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine3_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine3_twtpcon_ready) begin
- litedramcore_bankmachine3_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- litedramcore_bankmachine3_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_row_open <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_row_close <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- litedramcore_bankmachine3_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine3_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine3_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine3_trccon_ready) begin
- litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine3_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine3_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine3_row_opened) begin
- if (litedramcore_bankmachine3_row_hit) begin
- if (litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine4_req_valid;
-assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine4_req_we;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine4_req_addr;
-assign litedramcore_bankmachine4_cmd_buffer_sink_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine4_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine4_cmd_buffer_sink_first = litedramcore_bankmachine4_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine4_cmd_buffer_sink_last = litedramcore_bankmachine4_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine4_cmd_buffer_sink_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine4_cmd_buffer_sink_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine4_cmd_buffer_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid);
-assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine4_cmd_buffer_source_valid);
-assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7]);
+ litedramcore_bankmachine3_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine3_source_valid & litedramcore_bankmachine3_source_source_valid)) begin
+ if ((litedramcore_bankmachine3_source_payload_addr[20:7] != litedramcore_bankmachine3_source_source_payload_addr[20:7])) begin
+ litedramcore_bankmachine3_auto_precharge <= (litedramcore_bankmachine3_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine3_syncfifo3_din = {litedramcore_bankmachine3_fifo_in_last, litedramcore_bankmachine3_fifo_in_first, litedramcore_bankmachine3_fifo_in_payload_addr, litedramcore_bankmachine3_fifo_in_payload_we};
+assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout;
+assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout;
+assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout;
+assign {litedramcore_bankmachine3_fifo_out_last, litedramcore_bankmachine3_fifo_out_first, litedramcore_bankmachine3_fifo_out_payload_addr, litedramcore_bankmachine3_fifo_out_payload_we} = litedramcore_bankmachine3_syncfifo3_dout;
+assign litedramcore_bankmachine3_sink_ready = litedramcore_bankmachine3_syncfifo3_writable;
+assign litedramcore_bankmachine3_syncfifo3_we = litedramcore_bankmachine3_sink_valid;
+assign litedramcore_bankmachine3_fifo_in_first = litedramcore_bankmachine3_sink_first;
+assign litedramcore_bankmachine3_fifo_in_last = litedramcore_bankmachine3_sink_last;
+assign litedramcore_bankmachine3_fifo_in_payload_we = litedramcore_bankmachine3_sink_payload_we;
+assign litedramcore_bankmachine3_fifo_in_payload_addr = litedramcore_bankmachine3_sink_payload_addr;
+assign litedramcore_bankmachine3_source_valid = litedramcore_bankmachine3_syncfifo3_readable;
+assign litedramcore_bankmachine3_source_first = litedramcore_bankmachine3_fifo_out_first;
+assign litedramcore_bankmachine3_source_last = litedramcore_bankmachine3_fifo_out_last;
+assign litedramcore_bankmachine3_source_payload_we = litedramcore_bankmachine3_fifo_out_payload_we;
+assign litedramcore_bankmachine3_source_payload_addr = litedramcore_bankmachine3_fifo_out_payload_addr;
+assign litedramcore_bankmachine3_syncfifo3_re = litedramcore_bankmachine3_source_ready;
+always @(*) begin
+ litedramcore_bankmachine3_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine3_replace) begin
+ litedramcore_bankmachine3_wrport_adr <= (litedramcore_bankmachine3_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine3_wrport_adr <= litedramcore_bankmachine3_produce;
+ end
+end
+assign litedramcore_bankmachine3_wrport_dat_w = litedramcore_bankmachine3_syncfifo3_din;
+assign litedramcore_bankmachine3_wrport_we = (litedramcore_bankmachine3_syncfifo3_we & (litedramcore_bankmachine3_syncfifo3_writable | litedramcore_bankmachine3_replace));
+assign litedramcore_bankmachine3_do_read = (litedramcore_bankmachine3_syncfifo3_readable & litedramcore_bankmachine3_syncfifo3_re);
+assign litedramcore_bankmachine3_rdport_adr = litedramcore_bankmachine3_consume;
+assign litedramcore_bankmachine3_syncfifo3_dout = litedramcore_bankmachine3_rdport_dat_r;
+assign litedramcore_bankmachine3_syncfifo3_writable = (litedramcore_bankmachine3_level != 5'd16);
+assign litedramcore_bankmachine3_syncfifo3_readable = (litedramcore_bankmachine3_level != 1'd0);
+assign litedramcore_bankmachine3_pipe_valid_sink_ready = ((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready);
+assign litedramcore_bankmachine3_pipe_valid_sink_valid = litedramcore_bankmachine3_sink_sink_valid;
+assign litedramcore_bankmachine3_sink_sink_ready = litedramcore_bankmachine3_pipe_valid_sink_ready;
+assign litedramcore_bankmachine3_pipe_valid_sink_first = litedramcore_bankmachine3_sink_sink_first;
+assign litedramcore_bankmachine3_pipe_valid_sink_last = litedramcore_bankmachine3_sink_sink_last;
+assign litedramcore_bankmachine3_pipe_valid_sink_payload_we = litedramcore_bankmachine3_sink_sink_payload_we;
+assign litedramcore_bankmachine3_pipe_valid_sink_payload_addr = litedramcore_bankmachine3_sink_sink_payload_addr;
+assign litedramcore_bankmachine3_source_source_valid = litedramcore_bankmachine3_pipe_valid_source_valid;
+assign litedramcore_bankmachine3_pipe_valid_source_ready = litedramcore_bankmachine3_source_source_ready;
+assign litedramcore_bankmachine3_source_source_first = litedramcore_bankmachine3_pipe_valid_source_first;
+assign litedramcore_bankmachine3_source_source_last = litedramcore_bankmachine3_pipe_valid_source_last;
+assign litedramcore_bankmachine3_source_source_payload_we = litedramcore_bankmachine3_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine3_source_source_payload_addr = litedramcore_bankmachine3_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine3_next_state <= 4'd0;
+ litedramcore_bankmachine3_next_state <= litedramcore_bankmachine3_state;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ if (litedramcore_bankmachine3_cmd_ready) begin
+ litedramcore_bankmachine3_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ if (litedramcore_bankmachine3_cmd_ready) begin
+ litedramcore_bankmachine3_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine3_refresh_req)) begin
+ litedramcore_bankmachine3_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine3_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine3_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine3_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine3_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ litedramcore_bankmachine3_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if ((litedramcore_bankmachine3_cmd_ready & litedramcore_bankmachine3_auto_precharge)) begin
+ litedramcore_bankmachine3_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine3_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine3_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if (litedramcore_bankmachine3_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if (litedramcore_bankmachine3_source_source_payload_we) begin
+ litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if (litedramcore_bankmachine3_source_source_payload_we) begin
+ litedramcore_bankmachine3_req_wdata_ready <= litedramcore_bankmachine3_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if (litedramcore_bankmachine3_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine3_req_rdata_valid <= litedramcore_bankmachine3_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine3_twtpcon_ready) begin
+ litedramcore_bankmachine3_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_row_open <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ litedramcore_bankmachine3_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_row_close <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ litedramcore_bankmachine3_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine3_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine3_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine3_trccon_ready) begin
+ litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine3_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine3_twtpcon_ready & litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine3_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine3_source_source_valid) begin
+ if (litedramcore_bankmachine3_row_opened) begin
+ if (litedramcore_bankmachine3_row_hit) begin
+ if (litedramcore_bankmachine3_source_source_payload_we) begin
+ litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+assign litedramcore_bankmachine4_sink_valid = litedramcore_bankmachine4_req_valid;
+assign litedramcore_bankmachine4_req_ready = litedramcore_bankmachine4_sink_ready;
+assign litedramcore_bankmachine4_sink_payload_we = litedramcore_bankmachine4_req_we;
+assign litedramcore_bankmachine4_sink_payload_addr = litedramcore_bankmachine4_req_addr;
+assign litedramcore_bankmachine4_sink_sink_valid = litedramcore_bankmachine4_source_valid;
+assign litedramcore_bankmachine4_source_ready = litedramcore_bankmachine4_sink_sink_ready;
+assign litedramcore_bankmachine4_sink_sink_first = litedramcore_bankmachine4_source_first;
+assign litedramcore_bankmachine4_sink_sink_last = litedramcore_bankmachine4_source_last;
+assign litedramcore_bankmachine4_sink_sink_payload_we = litedramcore_bankmachine4_source_payload_we;
+assign litedramcore_bankmachine4_sink_sink_payload_addr = litedramcore_bankmachine4_source_payload_addr;
+assign litedramcore_bankmachine4_source_source_ready = (litedramcore_bankmachine4_req_wdata_ready | litedramcore_bankmachine4_req_rdata_valid);
+assign litedramcore_bankmachine4_req_lock = (litedramcore_bankmachine4_source_valid | litedramcore_bankmachine4_source_source_valid);
+assign litedramcore_bankmachine4_row_hit = (litedramcore_bankmachine4_row == litedramcore_bankmachine4_source_source_payload_addr[20:7]);
assign litedramcore_bankmachine4_cmd_payload_ba = 3'd4;
always @(*) begin
- litedramcore_bankmachine4_cmd_payload_a <= 14'd0;
- if (litedramcore_bankmachine4_row_col_n_addr_sel) begin
- litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7];
- end else begin
- litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine4_cmd_payload_a <= 14'd0;
+ if (litedramcore_bankmachine4_row_col_n_addr_sel) begin
+ litedramcore_bankmachine4_cmd_payload_a <= litedramcore_bankmachine4_source_source_payload_addr[20:7];
+ end else begin
+ litedramcore_bankmachine4_cmd_payload_a <= ((litedramcore_bankmachine4_auto_precharge <<< 4'd10) | {litedramcore_bankmachine4_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine4_twtpcon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_cmd_payload_is_write);
assign litedramcore_bankmachine4_trccon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
assign litedramcore_bankmachine4_trascon_valid = ((litedramcore_bankmachine4_cmd_valid & litedramcore_bankmachine4_cmd_ready) & litedramcore_bankmachine4_row_open);
always @(*) begin
- litedramcore_bankmachine4_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine4_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7])) begin
- litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din = {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign {litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_first = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_last = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine4_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re = litedramcore_bankmachine4_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine4_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine4_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_din;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable | litedramcore_bankmachine4_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_re);
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine4_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_dout = litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_readable = (litedramcore_bankmachine4_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine4_cmd_buffer_sink_ready = ((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine4_next_state <= 4'd0;
- litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- if (litedramcore_bankmachine4_cmd_ready) begin
- litedramcore_bankmachine4_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- if (litedramcore_bankmachine4_cmd_ready) begin
- litedramcore_bankmachine4_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine4_refresh_req)) begin
- litedramcore_bankmachine4_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine4_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine4_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine4_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine4_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- litedramcore_bankmachine4_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin
- litedramcore_bankmachine4_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine4_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine4_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine4_twtpcon_ready) begin
- litedramcore_bankmachine4_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- litedramcore_bankmachine4_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_row_open <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_row_close <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- litedramcore_bankmachine4_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine4_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine4_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine4_trccon_ready) begin
- litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine4_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine4_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine4_row_opened) begin
- if (litedramcore_bankmachine4_row_hit) begin
- if (litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine5_req_valid;
-assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine5_req_we;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine5_req_addr;
-assign litedramcore_bankmachine5_cmd_buffer_sink_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine5_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine5_cmd_buffer_sink_first = litedramcore_bankmachine5_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine5_cmd_buffer_sink_last = litedramcore_bankmachine5_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine5_cmd_buffer_sink_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine5_cmd_buffer_sink_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine5_cmd_buffer_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid);
-assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine5_cmd_buffer_source_valid);
-assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7]);
+ litedramcore_bankmachine4_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine4_source_valid & litedramcore_bankmachine4_source_source_valid)) begin
+ if ((litedramcore_bankmachine4_source_payload_addr[20:7] != litedramcore_bankmachine4_source_source_payload_addr[20:7])) begin
+ litedramcore_bankmachine4_auto_precharge <= (litedramcore_bankmachine4_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine4_syncfifo4_din = {litedramcore_bankmachine4_fifo_in_last, litedramcore_bankmachine4_fifo_in_first, litedramcore_bankmachine4_fifo_in_payload_addr, litedramcore_bankmachine4_fifo_in_payload_we};
+assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout;
+assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout;
+assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout;
+assign {litedramcore_bankmachine4_fifo_out_last, litedramcore_bankmachine4_fifo_out_first, litedramcore_bankmachine4_fifo_out_payload_addr, litedramcore_bankmachine4_fifo_out_payload_we} = litedramcore_bankmachine4_syncfifo4_dout;
+assign litedramcore_bankmachine4_sink_ready = litedramcore_bankmachine4_syncfifo4_writable;
+assign litedramcore_bankmachine4_syncfifo4_we = litedramcore_bankmachine4_sink_valid;
+assign litedramcore_bankmachine4_fifo_in_first = litedramcore_bankmachine4_sink_first;
+assign litedramcore_bankmachine4_fifo_in_last = litedramcore_bankmachine4_sink_last;
+assign litedramcore_bankmachine4_fifo_in_payload_we = litedramcore_bankmachine4_sink_payload_we;
+assign litedramcore_bankmachine4_fifo_in_payload_addr = litedramcore_bankmachine4_sink_payload_addr;
+assign litedramcore_bankmachine4_source_valid = litedramcore_bankmachine4_syncfifo4_readable;
+assign litedramcore_bankmachine4_source_first = litedramcore_bankmachine4_fifo_out_first;
+assign litedramcore_bankmachine4_source_last = litedramcore_bankmachine4_fifo_out_last;
+assign litedramcore_bankmachine4_source_payload_we = litedramcore_bankmachine4_fifo_out_payload_we;
+assign litedramcore_bankmachine4_source_payload_addr = litedramcore_bankmachine4_fifo_out_payload_addr;
+assign litedramcore_bankmachine4_syncfifo4_re = litedramcore_bankmachine4_source_ready;
+always @(*) begin
+ litedramcore_bankmachine4_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine4_replace) begin
+ litedramcore_bankmachine4_wrport_adr <= (litedramcore_bankmachine4_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine4_wrport_adr <= litedramcore_bankmachine4_produce;
+ end
+end
+assign litedramcore_bankmachine4_wrport_dat_w = litedramcore_bankmachine4_syncfifo4_din;
+assign litedramcore_bankmachine4_wrport_we = (litedramcore_bankmachine4_syncfifo4_we & (litedramcore_bankmachine4_syncfifo4_writable | litedramcore_bankmachine4_replace));
+assign litedramcore_bankmachine4_do_read = (litedramcore_bankmachine4_syncfifo4_readable & litedramcore_bankmachine4_syncfifo4_re);
+assign litedramcore_bankmachine4_rdport_adr = litedramcore_bankmachine4_consume;
+assign litedramcore_bankmachine4_syncfifo4_dout = litedramcore_bankmachine4_rdport_dat_r;
+assign litedramcore_bankmachine4_syncfifo4_writable = (litedramcore_bankmachine4_level != 5'd16);
+assign litedramcore_bankmachine4_syncfifo4_readable = (litedramcore_bankmachine4_level != 1'd0);
+assign litedramcore_bankmachine4_pipe_valid_sink_ready = ((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready);
+assign litedramcore_bankmachine4_pipe_valid_sink_valid = litedramcore_bankmachine4_sink_sink_valid;
+assign litedramcore_bankmachine4_sink_sink_ready = litedramcore_bankmachine4_pipe_valid_sink_ready;
+assign litedramcore_bankmachine4_pipe_valid_sink_first = litedramcore_bankmachine4_sink_sink_first;
+assign litedramcore_bankmachine4_pipe_valid_sink_last = litedramcore_bankmachine4_sink_sink_last;
+assign litedramcore_bankmachine4_pipe_valid_sink_payload_we = litedramcore_bankmachine4_sink_sink_payload_we;
+assign litedramcore_bankmachine4_pipe_valid_sink_payload_addr = litedramcore_bankmachine4_sink_sink_payload_addr;
+assign litedramcore_bankmachine4_source_source_valid = litedramcore_bankmachine4_pipe_valid_source_valid;
+assign litedramcore_bankmachine4_pipe_valid_source_ready = litedramcore_bankmachine4_source_source_ready;
+assign litedramcore_bankmachine4_source_source_first = litedramcore_bankmachine4_pipe_valid_source_first;
+assign litedramcore_bankmachine4_source_source_last = litedramcore_bankmachine4_pipe_valid_source_last;
+assign litedramcore_bankmachine4_source_source_payload_we = litedramcore_bankmachine4_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine4_source_source_payload_addr = litedramcore_bankmachine4_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine4_next_state <= 4'd0;
+ litedramcore_bankmachine4_next_state <= litedramcore_bankmachine4_state;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ if (litedramcore_bankmachine4_cmd_ready) begin
+ litedramcore_bankmachine4_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ if (litedramcore_bankmachine4_cmd_ready) begin
+ litedramcore_bankmachine4_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine4_refresh_req)) begin
+ litedramcore_bankmachine4_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine4_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine4_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine4_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine4_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ litedramcore_bankmachine4_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if ((litedramcore_bankmachine4_cmd_ready & litedramcore_bankmachine4_auto_precharge)) begin
+ litedramcore_bankmachine4_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine4_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine4_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if (litedramcore_bankmachine4_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine4_req_rdata_valid <= litedramcore_bankmachine4_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine4_twtpcon_ready) begin
+ litedramcore_bankmachine4_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_row_open <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ litedramcore_bankmachine4_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ litedramcore_bankmachine4_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ litedramcore_bankmachine4_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_row_close <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ litedramcore_bankmachine4_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine4_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine4_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if (litedramcore_bankmachine4_source_source_payload_we) begin
+ litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine4_twtpcon_ready & litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine4_trccon_ready) begin
+ litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if (litedramcore_bankmachine4_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if (litedramcore_bankmachine4_source_source_payload_we) begin
+ litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine4_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine4_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine4_source_source_valid) begin
+ if (litedramcore_bankmachine4_row_opened) begin
+ if (litedramcore_bankmachine4_row_hit) begin
+ if (litedramcore_bankmachine4_source_source_payload_we) begin
+ litedramcore_bankmachine4_req_wdata_ready <= litedramcore_bankmachine4_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+assign litedramcore_bankmachine5_sink_valid = litedramcore_bankmachine5_req_valid;
+assign litedramcore_bankmachine5_req_ready = litedramcore_bankmachine5_sink_ready;
+assign litedramcore_bankmachine5_sink_payload_we = litedramcore_bankmachine5_req_we;
+assign litedramcore_bankmachine5_sink_payload_addr = litedramcore_bankmachine5_req_addr;
+assign litedramcore_bankmachine5_sink_sink_valid = litedramcore_bankmachine5_source_valid;
+assign litedramcore_bankmachine5_source_ready = litedramcore_bankmachine5_sink_sink_ready;
+assign litedramcore_bankmachine5_sink_sink_first = litedramcore_bankmachine5_source_first;
+assign litedramcore_bankmachine5_sink_sink_last = litedramcore_bankmachine5_source_last;
+assign litedramcore_bankmachine5_sink_sink_payload_we = litedramcore_bankmachine5_source_payload_we;
+assign litedramcore_bankmachine5_sink_sink_payload_addr = litedramcore_bankmachine5_source_payload_addr;
+assign litedramcore_bankmachine5_source_source_ready = (litedramcore_bankmachine5_req_wdata_ready | litedramcore_bankmachine5_req_rdata_valid);
+assign litedramcore_bankmachine5_req_lock = (litedramcore_bankmachine5_source_valid | litedramcore_bankmachine5_source_source_valid);
+assign litedramcore_bankmachine5_row_hit = (litedramcore_bankmachine5_row == litedramcore_bankmachine5_source_source_payload_addr[20:7]);
assign litedramcore_bankmachine5_cmd_payload_ba = 3'd5;
always @(*) begin
- litedramcore_bankmachine5_cmd_payload_a <= 14'd0;
- if (litedramcore_bankmachine5_row_col_n_addr_sel) begin
- litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7];
- end else begin
- litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine5_cmd_payload_a <= 14'd0;
+ if (litedramcore_bankmachine5_row_col_n_addr_sel) begin
+ litedramcore_bankmachine5_cmd_payload_a <= litedramcore_bankmachine5_source_source_payload_addr[20:7];
+ end else begin
+ litedramcore_bankmachine5_cmd_payload_a <= ((litedramcore_bankmachine5_auto_precharge <<< 4'd10) | {litedramcore_bankmachine5_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine5_twtpcon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_cmd_payload_is_write);
assign litedramcore_bankmachine5_trccon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
assign litedramcore_bankmachine5_trascon_valid = ((litedramcore_bankmachine5_cmd_valid & litedramcore_bankmachine5_cmd_ready) & litedramcore_bankmachine5_row_open);
always @(*) begin
- litedramcore_bankmachine5_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine5_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7])) begin
- litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din = {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign {litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_first = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_last = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine5_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re = litedramcore_bankmachine5_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine5_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine5_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_din;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable | litedramcore_bankmachine5_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_re);
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine5_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_dout = litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_readable = (litedramcore_bankmachine5_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine5_cmd_buffer_sink_ready = ((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine5_next_state <= 4'd0;
- litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- if (litedramcore_bankmachine5_cmd_ready) begin
- litedramcore_bankmachine5_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- if (litedramcore_bankmachine5_cmd_ready) begin
- litedramcore_bankmachine5_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine5_refresh_req)) begin
- litedramcore_bankmachine5_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine5_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine5_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine5_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine5_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- litedramcore_bankmachine5_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin
- litedramcore_bankmachine5_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine5_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine5_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine5_twtpcon_ready) begin
- litedramcore_bankmachine5_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- litedramcore_bankmachine5_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_row_open <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_row_close <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- litedramcore_bankmachine5_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine5_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine5_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine5_trccon_ready) begin
- litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine5_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine5_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine5_row_opened) begin
- if (litedramcore_bankmachine5_row_hit) begin
- if (litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine6_req_valid;
-assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine6_req_we;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine6_req_addr;
-assign litedramcore_bankmachine6_cmd_buffer_sink_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine6_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine6_cmd_buffer_sink_first = litedramcore_bankmachine6_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine6_cmd_buffer_sink_last = litedramcore_bankmachine6_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine6_cmd_buffer_sink_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine6_cmd_buffer_sink_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine6_cmd_buffer_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid);
-assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine6_cmd_buffer_source_valid);
-assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7]);
+ litedramcore_bankmachine5_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine5_source_valid & litedramcore_bankmachine5_source_source_valid)) begin
+ if ((litedramcore_bankmachine5_source_payload_addr[20:7] != litedramcore_bankmachine5_source_source_payload_addr[20:7])) begin
+ litedramcore_bankmachine5_auto_precharge <= (litedramcore_bankmachine5_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine5_syncfifo5_din = {litedramcore_bankmachine5_fifo_in_last, litedramcore_bankmachine5_fifo_in_first, litedramcore_bankmachine5_fifo_in_payload_addr, litedramcore_bankmachine5_fifo_in_payload_we};
+assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout;
+assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout;
+assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout;
+assign {litedramcore_bankmachine5_fifo_out_last, litedramcore_bankmachine5_fifo_out_first, litedramcore_bankmachine5_fifo_out_payload_addr, litedramcore_bankmachine5_fifo_out_payload_we} = litedramcore_bankmachine5_syncfifo5_dout;
+assign litedramcore_bankmachine5_sink_ready = litedramcore_bankmachine5_syncfifo5_writable;
+assign litedramcore_bankmachine5_syncfifo5_we = litedramcore_bankmachine5_sink_valid;
+assign litedramcore_bankmachine5_fifo_in_first = litedramcore_bankmachine5_sink_first;
+assign litedramcore_bankmachine5_fifo_in_last = litedramcore_bankmachine5_sink_last;
+assign litedramcore_bankmachine5_fifo_in_payload_we = litedramcore_bankmachine5_sink_payload_we;
+assign litedramcore_bankmachine5_fifo_in_payload_addr = litedramcore_bankmachine5_sink_payload_addr;
+assign litedramcore_bankmachine5_source_valid = litedramcore_bankmachine5_syncfifo5_readable;
+assign litedramcore_bankmachine5_source_first = litedramcore_bankmachine5_fifo_out_first;
+assign litedramcore_bankmachine5_source_last = litedramcore_bankmachine5_fifo_out_last;
+assign litedramcore_bankmachine5_source_payload_we = litedramcore_bankmachine5_fifo_out_payload_we;
+assign litedramcore_bankmachine5_source_payload_addr = litedramcore_bankmachine5_fifo_out_payload_addr;
+assign litedramcore_bankmachine5_syncfifo5_re = litedramcore_bankmachine5_source_ready;
+always @(*) begin
+ litedramcore_bankmachine5_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine5_replace) begin
+ litedramcore_bankmachine5_wrport_adr <= (litedramcore_bankmachine5_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine5_wrport_adr <= litedramcore_bankmachine5_produce;
+ end
+end
+assign litedramcore_bankmachine5_wrport_dat_w = litedramcore_bankmachine5_syncfifo5_din;
+assign litedramcore_bankmachine5_wrport_we = (litedramcore_bankmachine5_syncfifo5_we & (litedramcore_bankmachine5_syncfifo5_writable | litedramcore_bankmachine5_replace));
+assign litedramcore_bankmachine5_do_read = (litedramcore_bankmachine5_syncfifo5_readable & litedramcore_bankmachine5_syncfifo5_re);
+assign litedramcore_bankmachine5_rdport_adr = litedramcore_bankmachine5_consume;
+assign litedramcore_bankmachine5_syncfifo5_dout = litedramcore_bankmachine5_rdport_dat_r;
+assign litedramcore_bankmachine5_syncfifo5_writable = (litedramcore_bankmachine5_level != 5'd16);
+assign litedramcore_bankmachine5_syncfifo5_readable = (litedramcore_bankmachine5_level != 1'd0);
+assign litedramcore_bankmachine5_pipe_valid_sink_ready = ((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready);
+assign litedramcore_bankmachine5_pipe_valid_sink_valid = litedramcore_bankmachine5_sink_sink_valid;
+assign litedramcore_bankmachine5_sink_sink_ready = litedramcore_bankmachine5_pipe_valid_sink_ready;
+assign litedramcore_bankmachine5_pipe_valid_sink_first = litedramcore_bankmachine5_sink_sink_first;
+assign litedramcore_bankmachine5_pipe_valid_sink_last = litedramcore_bankmachine5_sink_sink_last;
+assign litedramcore_bankmachine5_pipe_valid_sink_payload_we = litedramcore_bankmachine5_sink_sink_payload_we;
+assign litedramcore_bankmachine5_pipe_valid_sink_payload_addr = litedramcore_bankmachine5_sink_sink_payload_addr;
+assign litedramcore_bankmachine5_source_source_valid = litedramcore_bankmachine5_pipe_valid_source_valid;
+assign litedramcore_bankmachine5_pipe_valid_source_ready = litedramcore_bankmachine5_source_source_ready;
+assign litedramcore_bankmachine5_source_source_first = litedramcore_bankmachine5_pipe_valid_source_first;
+assign litedramcore_bankmachine5_source_source_last = litedramcore_bankmachine5_pipe_valid_source_last;
+assign litedramcore_bankmachine5_source_source_payload_we = litedramcore_bankmachine5_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine5_source_source_payload_addr = litedramcore_bankmachine5_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine5_next_state <= 4'd0;
+ litedramcore_bankmachine5_next_state <= litedramcore_bankmachine5_state;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ if (litedramcore_bankmachine5_cmd_ready) begin
+ litedramcore_bankmachine5_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ if (litedramcore_bankmachine5_cmd_ready) begin
+ litedramcore_bankmachine5_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine5_refresh_req)) begin
+ litedramcore_bankmachine5_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine5_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine5_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine5_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine5_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ litedramcore_bankmachine5_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if ((litedramcore_bankmachine5_cmd_ready & litedramcore_bankmachine5_auto_precharge)) begin
+ litedramcore_bankmachine5_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine5_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine5_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if (litedramcore_bankmachine5_source_source_payload_we) begin
+ litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if (litedramcore_bankmachine5_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if (litedramcore_bankmachine5_source_source_payload_we) begin
+ litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if (litedramcore_bankmachine5_source_source_payload_we) begin
+ litedramcore_bankmachine5_req_wdata_ready <= litedramcore_bankmachine5_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ if (litedramcore_bankmachine5_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine5_req_rdata_valid <= litedramcore_bankmachine5_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine5_twtpcon_ready) begin
+ litedramcore_bankmachine5_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_row_open <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine5_twtpcon_ready & litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine5_trccon_ready) begin
+ litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine5_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine5_source_source_valid) begin
+ if (litedramcore_bankmachine5_row_opened) begin
+ if (litedramcore_bankmachine5_row_hit) begin
+ litedramcore_bankmachine5_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine5_row_close <= 1'd0;
+ case (litedramcore_bankmachine5_state)
+ 1'd1: begin
+ litedramcore_bankmachine5_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine5_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine5_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+assign litedramcore_bankmachine6_sink_valid = litedramcore_bankmachine6_req_valid;
+assign litedramcore_bankmachine6_req_ready = litedramcore_bankmachine6_sink_ready;
+assign litedramcore_bankmachine6_sink_payload_we = litedramcore_bankmachine6_req_we;
+assign litedramcore_bankmachine6_sink_payload_addr = litedramcore_bankmachine6_req_addr;
+assign litedramcore_bankmachine6_sink_sink_valid = litedramcore_bankmachine6_source_valid;
+assign litedramcore_bankmachine6_source_ready = litedramcore_bankmachine6_sink_sink_ready;
+assign litedramcore_bankmachine6_sink_sink_first = litedramcore_bankmachine6_source_first;
+assign litedramcore_bankmachine6_sink_sink_last = litedramcore_bankmachine6_source_last;
+assign litedramcore_bankmachine6_sink_sink_payload_we = litedramcore_bankmachine6_source_payload_we;
+assign litedramcore_bankmachine6_sink_sink_payload_addr = litedramcore_bankmachine6_source_payload_addr;
+assign litedramcore_bankmachine6_source_source_ready = (litedramcore_bankmachine6_req_wdata_ready | litedramcore_bankmachine6_req_rdata_valid);
+assign litedramcore_bankmachine6_req_lock = (litedramcore_bankmachine6_source_valid | litedramcore_bankmachine6_source_source_valid);
+assign litedramcore_bankmachine6_row_hit = (litedramcore_bankmachine6_row == litedramcore_bankmachine6_source_source_payload_addr[20:7]);
assign litedramcore_bankmachine6_cmd_payload_ba = 3'd6;
always @(*) begin
- litedramcore_bankmachine6_cmd_payload_a <= 14'd0;
- if (litedramcore_bankmachine6_row_col_n_addr_sel) begin
- litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7];
- end else begin
- litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine6_cmd_payload_a <= 14'd0;
+ if (litedramcore_bankmachine6_row_col_n_addr_sel) begin
+ litedramcore_bankmachine6_cmd_payload_a <= litedramcore_bankmachine6_source_source_payload_addr[20:7];
+ end else begin
+ litedramcore_bankmachine6_cmd_payload_a <= ((litedramcore_bankmachine6_auto_precharge <<< 4'd10) | {litedramcore_bankmachine6_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine6_twtpcon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_cmd_payload_is_write);
assign litedramcore_bankmachine6_trccon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
assign litedramcore_bankmachine6_trascon_valid = ((litedramcore_bankmachine6_cmd_valid & litedramcore_bankmachine6_cmd_ready) & litedramcore_bankmachine6_row_open);
always @(*) begin
- litedramcore_bankmachine6_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine6_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7])) begin
- litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din = {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign {litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_first = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_last = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine6_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re = litedramcore_bankmachine6_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine6_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine6_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_din;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable | litedramcore_bankmachine6_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_re);
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine6_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_dout = litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_readable = (litedramcore_bankmachine6_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine6_cmd_buffer_sink_ready = ((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine6_next_state <= 4'd0;
- litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- if (litedramcore_bankmachine6_cmd_ready) begin
- litedramcore_bankmachine6_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- if (litedramcore_bankmachine6_cmd_ready) begin
- litedramcore_bankmachine6_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine6_refresh_req)) begin
- litedramcore_bankmachine6_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine6_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine6_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine6_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine6_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- litedramcore_bankmachine6_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin
- litedramcore_bankmachine6_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine6_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine6_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine6_twtpcon_ready) begin
- litedramcore_bankmachine6_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- litedramcore_bankmachine6_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_row_open <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_row_close <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- litedramcore_bankmachine6_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine6_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine6_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine6_trccon_ready) begin
- litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine6_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine6_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine6_row_opened) begin
- if (litedramcore_bankmachine6_row_hit) begin
- if (litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid = litedramcore_bankmachine7_req_valid;
-assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we = litedramcore_bankmachine7_req_we;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr = litedramcore_bankmachine7_req_addr;
-assign litedramcore_bankmachine7_cmd_buffer_sink_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready = litedramcore_bankmachine7_cmd_buffer_sink_ready;
-assign litedramcore_bankmachine7_cmd_buffer_sink_first = litedramcore_bankmachine7_cmd_buffer_lookahead_source_first;
-assign litedramcore_bankmachine7_cmd_buffer_sink_last = litedramcore_bankmachine7_cmd_buffer_lookahead_source_last;
-assign litedramcore_bankmachine7_cmd_buffer_sink_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we;
-assign litedramcore_bankmachine7_cmd_buffer_sink_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr;
-assign litedramcore_bankmachine7_cmd_buffer_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid);
-assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid | litedramcore_bankmachine7_cmd_buffer_source_valid);
-assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7]);
+ litedramcore_bankmachine6_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine6_source_valid & litedramcore_bankmachine6_source_source_valid)) begin
+ if ((litedramcore_bankmachine6_source_payload_addr[20:7] != litedramcore_bankmachine6_source_source_payload_addr[20:7])) begin
+ litedramcore_bankmachine6_auto_precharge <= (litedramcore_bankmachine6_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine6_syncfifo6_din = {litedramcore_bankmachine6_fifo_in_last, litedramcore_bankmachine6_fifo_in_first, litedramcore_bankmachine6_fifo_in_payload_addr, litedramcore_bankmachine6_fifo_in_payload_we};
+assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout;
+assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout;
+assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout;
+assign {litedramcore_bankmachine6_fifo_out_last, litedramcore_bankmachine6_fifo_out_first, litedramcore_bankmachine6_fifo_out_payload_addr, litedramcore_bankmachine6_fifo_out_payload_we} = litedramcore_bankmachine6_syncfifo6_dout;
+assign litedramcore_bankmachine6_sink_ready = litedramcore_bankmachine6_syncfifo6_writable;
+assign litedramcore_bankmachine6_syncfifo6_we = litedramcore_bankmachine6_sink_valid;
+assign litedramcore_bankmachine6_fifo_in_first = litedramcore_bankmachine6_sink_first;
+assign litedramcore_bankmachine6_fifo_in_last = litedramcore_bankmachine6_sink_last;
+assign litedramcore_bankmachine6_fifo_in_payload_we = litedramcore_bankmachine6_sink_payload_we;
+assign litedramcore_bankmachine6_fifo_in_payload_addr = litedramcore_bankmachine6_sink_payload_addr;
+assign litedramcore_bankmachine6_source_valid = litedramcore_bankmachine6_syncfifo6_readable;
+assign litedramcore_bankmachine6_source_first = litedramcore_bankmachine6_fifo_out_first;
+assign litedramcore_bankmachine6_source_last = litedramcore_bankmachine6_fifo_out_last;
+assign litedramcore_bankmachine6_source_payload_we = litedramcore_bankmachine6_fifo_out_payload_we;
+assign litedramcore_bankmachine6_source_payload_addr = litedramcore_bankmachine6_fifo_out_payload_addr;
+assign litedramcore_bankmachine6_syncfifo6_re = litedramcore_bankmachine6_source_ready;
+always @(*) begin
+ litedramcore_bankmachine6_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine6_replace) begin
+ litedramcore_bankmachine6_wrport_adr <= (litedramcore_bankmachine6_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine6_wrport_adr <= litedramcore_bankmachine6_produce;
+ end
+end
+assign litedramcore_bankmachine6_wrport_dat_w = litedramcore_bankmachine6_syncfifo6_din;
+assign litedramcore_bankmachine6_wrport_we = (litedramcore_bankmachine6_syncfifo6_we & (litedramcore_bankmachine6_syncfifo6_writable | litedramcore_bankmachine6_replace));
+assign litedramcore_bankmachine6_do_read = (litedramcore_bankmachine6_syncfifo6_readable & litedramcore_bankmachine6_syncfifo6_re);
+assign litedramcore_bankmachine6_rdport_adr = litedramcore_bankmachine6_consume;
+assign litedramcore_bankmachine6_syncfifo6_dout = litedramcore_bankmachine6_rdport_dat_r;
+assign litedramcore_bankmachine6_syncfifo6_writable = (litedramcore_bankmachine6_level != 5'd16);
+assign litedramcore_bankmachine6_syncfifo6_readable = (litedramcore_bankmachine6_level != 1'd0);
+assign litedramcore_bankmachine6_pipe_valid_sink_ready = ((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready);
+assign litedramcore_bankmachine6_pipe_valid_sink_valid = litedramcore_bankmachine6_sink_sink_valid;
+assign litedramcore_bankmachine6_sink_sink_ready = litedramcore_bankmachine6_pipe_valid_sink_ready;
+assign litedramcore_bankmachine6_pipe_valid_sink_first = litedramcore_bankmachine6_sink_sink_first;
+assign litedramcore_bankmachine6_pipe_valid_sink_last = litedramcore_bankmachine6_sink_sink_last;
+assign litedramcore_bankmachine6_pipe_valid_sink_payload_we = litedramcore_bankmachine6_sink_sink_payload_we;
+assign litedramcore_bankmachine6_pipe_valid_sink_payload_addr = litedramcore_bankmachine6_sink_sink_payload_addr;
+assign litedramcore_bankmachine6_source_source_valid = litedramcore_bankmachine6_pipe_valid_source_valid;
+assign litedramcore_bankmachine6_pipe_valid_source_ready = litedramcore_bankmachine6_source_source_ready;
+assign litedramcore_bankmachine6_source_source_first = litedramcore_bankmachine6_pipe_valid_source_first;
+assign litedramcore_bankmachine6_source_source_last = litedramcore_bankmachine6_pipe_valid_source_last;
+assign litedramcore_bankmachine6_source_source_payload_we = litedramcore_bankmachine6_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine6_source_source_payload_addr = litedramcore_bankmachine6_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine6_next_state <= 4'd0;
+ litedramcore_bankmachine6_next_state <= litedramcore_bankmachine6_state;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ if (litedramcore_bankmachine6_cmd_ready) begin
+ litedramcore_bankmachine6_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ if (litedramcore_bankmachine6_cmd_ready) begin
+ litedramcore_bankmachine6_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine6_refresh_req)) begin
+ litedramcore_bankmachine6_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine6_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine6_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine6_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine6_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ litedramcore_bankmachine6_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if ((litedramcore_bankmachine6_cmd_ready & litedramcore_bankmachine6_auto_precharge)) begin
+ litedramcore_bankmachine6_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine6_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine6_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if (litedramcore_bankmachine6_source_source_payload_we) begin
+ litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if (litedramcore_bankmachine6_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if (litedramcore_bankmachine6_source_source_payload_we) begin
+ litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if (litedramcore_bankmachine6_source_source_payload_we) begin
+ litedramcore_bankmachine6_req_wdata_ready <= litedramcore_bankmachine6_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ if (litedramcore_bankmachine6_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine6_req_rdata_valid <= litedramcore_bankmachine6_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine6_twtpcon_ready) begin
+ litedramcore_bankmachine6_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_row_open <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine6_twtpcon_ready & litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine6_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine6_source_source_valid) begin
+ if (litedramcore_bankmachine6_row_opened) begin
+ if (litedramcore_bankmachine6_row_hit) begin
+ litedramcore_bankmachine6_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_row_close <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ litedramcore_bankmachine6_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine6_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine6_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine6_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine6_trccon_ready) begin
+ litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+assign litedramcore_bankmachine7_sink_valid = litedramcore_bankmachine7_req_valid;
+assign litedramcore_bankmachine7_req_ready = litedramcore_bankmachine7_sink_ready;
+assign litedramcore_bankmachine7_sink_payload_we = litedramcore_bankmachine7_req_we;
+assign litedramcore_bankmachine7_sink_payload_addr = litedramcore_bankmachine7_req_addr;
+assign litedramcore_bankmachine7_sink_sink_valid = litedramcore_bankmachine7_source_valid;
+assign litedramcore_bankmachine7_source_ready = litedramcore_bankmachine7_sink_sink_ready;
+assign litedramcore_bankmachine7_sink_sink_first = litedramcore_bankmachine7_source_first;
+assign litedramcore_bankmachine7_sink_sink_last = litedramcore_bankmachine7_source_last;
+assign litedramcore_bankmachine7_sink_sink_payload_we = litedramcore_bankmachine7_source_payload_we;
+assign litedramcore_bankmachine7_sink_sink_payload_addr = litedramcore_bankmachine7_source_payload_addr;
+assign litedramcore_bankmachine7_source_source_ready = (litedramcore_bankmachine7_req_wdata_ready | litedramcore_bankmachine7_req_rdata_valid);
+assign litedramcore_bankmachine7_req_lock = (litedramcore_bankmachine7_source_valid | litedramcore_bankmachine7_source_source_valid);
+assign litedramcore_bankmachine7_row_hit = (litedramcore_bankmachine7_row == litedramcore_bankmachine7_source_source_payload_addr[20:7]);
assign litedramcore_bankmachine7_cmd_payload_ba = 3'd7;
always @(*) begin
- litedramcore_bankmachine7_cmd_payload_a <= 14'd0;
- if (litedramcore_bankmachine7_row_col_n_addr_sel) begin
- litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7];
- end else begin
- litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_cmd_buffer_source_payload_addr[6:0], {3{1'd0}}});
- end
+ litedramcore_bankmachine7_cmd_payload_a <= 14'd0;
+ if (litedramcore_bankmachine7_row_col_n_addr_sel) begin
+ litedramcore_bankmachine7_cmd_payload_a <= litedramcore_bankmachine7_source_source_payload_addr[20:7];
+ end else begin
+ litedramcore_bankmachine7_cmd_payload_a <= ((litedramcore_bankmachine7_auto_precharge <<< 4'd10) | {litedramcore_bankmachine7_source_source_payload_addr[6:0], {3{1'd0}}});
+ end
end
assign litedramcore_bankmachine7_twtpcon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_cmd_payload_is_write);
assign litedramcore_bankmachine7_trccon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
assign litedramcore_bankmachine7_trascon_valid = ((litedramcore_bankmachine7_cmd_valid & litedramcore_bankmachine7_cmd_ready) & litedramcore_bankmachine7_row_open);
always @(*) begin
- litedramcore_bankmachine7_auto_precharge <= 1'd0;
- if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid & litedramcore_bankmachine7_cmd_buffer_source_valid)) begin
- if ((litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr[20:7] != litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7])) begin
- litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0);
- end
- end
-end
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din = {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we};
-assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign {litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr, litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we} = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_sink_ready = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_valid;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_first = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_first;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_last = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_last;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_we;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_in_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_sink_payload_addr;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_valid = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_first = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_first;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_last = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_last;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_we = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_we;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_source_payload_addr = litedramcore_bankmachine7_cmd_buffer_lookahead_fifo_out_payload_addr;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re = litedramcore_bankmachine7_cmd_buffer_lookahead_source_ready;
-always @(*) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= 4'd0;
- if (litedramcore_bankmachine7_cmd_buffer_lookahead_replace) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce - 1'd1);
- end else begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr <= litedramcore_bankmachine7_cmd_buffer_lookahead_produce;
- end
-end
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w = litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_din;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable | litedramcore_bankmachine7_cmd_buffer_lookahead_replace));
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_do_read = (litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_re);
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr = litedramcore_bankmachine7_cmd_buffer_lookahead_consume;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_dout = litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 5'd16);
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_readable = (litedramcore_bankmachine7_cmd_buffer_lookahead_level != 1'd0);
-assign litedramcore_bankmachine7_cmd_buffer_sink_ready = ((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready);
-always @(*) begin
- litedramcore_bankmachine7_next_state <= 4'd0;
- litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- if (litedramcore_bankmachine7_cmd_ready) begin
- litedramcore_bankmachine7_next_state <= 3'd5;
- end
- end
- end
- 2'd2: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_next_state <= 3'd5;
- end
- end
- 2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- if (litedramcore_bankmachine7_cmd_ready) begin
- litedramcore_bankmachine7_next_state <= 3'd7;
- end
- end
- end
- 3'd4: begin
- if ((~litedramcore_bankmachine7_refresh_req)) begin
- litedramcore_bankmachine7_next_state <= 1'd0;
- end
- end
- 3'd5: begin
- litedramcore_bankmachine7_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_bankmachine7_next_state <= 2'd3;
- end
- 3'd7: begin
- litedramcore_bankmachine7_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_bankmachine7_next_state <= 1'd0;
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- litedramcore_bankmachine7_next_state <= 3'd4;
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin
- litedramcore_bankmachine7_next_state <= 2'd2;
- end
- end else begin
- litedramcore_bankmachine7_next_state <= 1'd1;
- end
- end else begin
- litedramcore_bankmachine7_next_state <= 2'd3;
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_refresh_gnt <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- if (litedramcore_bankmachine7_twtpcon_ready) begin
- litedramcore_bankmachine7_refresh_gnt <= 1'd1;
- end
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_cmd_valid <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_valid <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_cmd_valid <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- litedramcore_bankmachine7_cmd_valid <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_row_open <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_row_open <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_row_close <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- litedramcore_bankmachine7_row_close <= 1'd1;
- end
- 2'd2: begin
- litedramcore_bankmachine7_row_close <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- litedramcore_bankmachine7_row_close <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
- end
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- if (litedramcore_bankmachine7_trccon_ready) begin
- litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
- end
- end
- 3'd4: begin
- litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- end else begin
- litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
- case (litedramcore_bankmachine7_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- default: begin
- if (litedramcore_bankmachine7_refresh_req) begin
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_source_valid) begin
- if (litedramcore_bankmachine7_row_opened) begin
- if (litedramcore_bankmachine7_row_hit) begin
- if (litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
- litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready;
- end else begin
- end
- end else begin
- end
- end else begin
- end
- end
- end
- end
- endcase
+ litedramcore_bankmachine7_auto_precharge <= 1'd0;
+ if ((litedramcore_bankmachine7_source_valid & litedramcore_bankmachine7_source_source_valid)) begin
+ if ((litedramcore_bankmachine7_source_payload_addr[20:7] != litedramcore_bankmachine7_source_source_payload_addr[20:7])) begin
+ litedramcore_bankmachine7_auto_precharge <= (litedramcore_bankmachine7_row_close == 1'd0);
+ end
+ end
+end
+assign litedramcore_bankmachine7_syncfifo7_din = {litedramcore_bankmachine7_fifo_in_last, litedramcore_bankmachine7_fifo_in_first, litedramcore_bankmachine7_fifo_in_payload_addr, litedramcore_bankmachine7_fifo_in_payload_we};
+assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout;
+assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout;
+assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout;
+assign {litedramcore_bankmachine7_fifo_out_last, litedramcore_bankmachine7_fifo_out_first, litedramcore_bankmachine7_fifo_out_payload_addr, litedramcore_bankmachine7_fifo_out_payload_we} = litedramcore_bankmachine7_syncfifo7_dout;
+assign litedramcore_bankmachine7_sink_ready = litedramcore_bankmachine7_syncfifo7_writable;
+assign litedramcore_bankmachine7_syncfifo7_we = litedramcore_bankmachine7_sink_valid;
+assign litedramcore_bankmachine7_fifo_in_first = litedramcore_bankmachine7_sink_first;
+assign litedramcore_bankmachine7_fifo_in_last = litedramcore_bankmachine7_sink_last;
+assign litedramcore_bankmachine7_fifo_in_payload_we = litedramcore_bankmachine7_sink_payload_we;
+assign litedramcore_bankmachine7_fifo_in_payload_addr = litedramcore_bankmachine7_sink_payload_addr;
+assign litedramcore_bankmachine7_source_valid = litedramcore_bankmachine7_syncfifo7_readable;
+assign litedramcore_bankmachine7_source_first = litedramcore_bankmachine7_fifo_out_first;
+assign litedramcore_bankmachine7_source_last = litedramcore_bankmachine7_fifo_out_last;
+assign litedramcore_bankmachine7_source_payload_we = litedramcore_bankmachine7_fifo_out_payload_we;
+assign litedramcore_bankmachine7_source_payload_addr = litedramcore_bankmachine7_fifo_out_payload_addr;
+assign litedramcore_bankmachine7_syncfifo7_re = litedramcore_bankmachine7_source_ready;
+always @(*) begin
+ litedramcore_bankmachine7_wrport_adr <= 4'd0;
+ if (litedramcore_bankmachine7_replace) begin
+ litedramcore_bankmachine7_wrport_adr <= (litedramcore_bankmachine7_produce - 1'd1);
+ end else begin
+ litedramcore_bankmachine7_wrport_adr <= litedramcore_bankmachine7_produce;
+ end
+end
+assign litedramcore_bankmachine7_wrport_dat_w = litedramcore_bankmachine7_syncfifo7_din;
+assign litedramcore_bankmachine7_wrport_we = (litedramcore_bankmachine7_syncfifo7_we & (litedramcore_bankmachine7_syncfifo7_writable | litedramcore_bankmachine7_replace));
+assign litedramcore_bankmachine7_do_read = (litedramcore_bankmachine7_syncfifo7_readable & litedramcore_bankmachine7_syncfifo7_re);
+assign litedramcore_bankmachine7_rdport_adr = litedramcore_bankmachine7_consume;
+assign litedramcore_bankmachine7_syncfifo7_dout = litedramcore_bankmachine7_rdport_dat_r;
+assign litedramcore_bankmachine7_syncfifo7_writable = (litedramcore_bankmachine7_level != 5'd16);
+assign litedramcore_bankmachine7_syncfifo7_readable = (litedramcore_bankmachine7_level != 1'd0);
+assign litedramcore_bankmachine7_pipe_valid_sink_ready = ((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready);
+assign litedramcore_bankmachine7_pipe_valid_sink_valid = litedramcore_bankmachine7_sink_sink_valid;
+assign litedramcore_bankmachine7_sink_sink_ready = litedramcore_bankmachine7_pipe_valid_sink_ready;
+assign litedramcore_bankmachine7_pipe_valid_sink_first = litedramcore_bankmachine7_sink_sink_first;
+assign litedramcore_bankmachine7_pipe_valid_sink_last = litedramcore_bankmachine7_sink_sink_last;
+assign litedramcore_bankmachine7_pipe_valid_sink_payload_we = litedramcore_bankmachine7_sink_sink_payload_we;
+assign litedramcore_bankmachine7_pipe_valid_sink_payload_addr = litedramcore_bankmachine7_sink_sink_payload_addr;
+assign litedramcore_bankmachine7_source_source_valid = litedramcore_bankmachine7_pipe_valid_source_valid;
+assign litedramcore_bankmachine7_pipe_valid_source_ready = litedramcore_bankmachine7_source_source_ready;
+assign litedramcore_bankmachine7_source_source_first = litedramcore_bankmachine7_pipe_valid_source_first;
+assign litedramcore_bankmachine7_source_source_last = litedramcore_bankmachine7_pipe_valid_source_last;
+assign litedramcore_bankmachine7_source_source_payload_we = litedramcore_bankmachine7_pipe_valid_source_payload_we;
+assign litedramcore_bankmachine7_source_source_payload_addr = litedramcore_bankmachine7_pipe_valid_source_payload_addr;
+always @(*) begin
+ litedramcore_bankmachine7_next_state <= 4'd0;
+ litedramcore_bankmachine7_next_state <= litedramcore_bankmachine7_state;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ if (litedramcore_bankmachine7_cmd_ready) begin
+ litedramcore_bankmachine7_next_state <= 3'd5;
+ end
+ end
+ end
+ 2'd2: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_next_state <= 3'd5;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ if (litedramcore_bankmachine7_cmd_ready) begin
+ litedramcore_bankmachine7_next_state <= 3'd7;
+ end
+ end
+ end
+ 3'd4: begin
+ if ((~litedramcore_bankmachine7_refresh_req)) begin
+ litedramcore_bankmachine7_next_state <= 1'd0;
+ end
+ end
+ 3'd5: begin
+ litedramcore_bankmachine7_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_bankmachine7_next_state <= 2'd3;
+ end
+ 3'd7: begin
+ litedramcore_bankmachine7_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_bankmachine7_next_state <= 1'd0;
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ litedramcore_bankmachine7_next_state <= 3'd4;
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if ((litedramcore_bankmachine7_cmd_ready & litedramcore_bankmachine7_auto_precharge)) begin
+ litedramcore_bankmachine7_next_state <= 2'd2;
+ end
+ end else begin
+ litedramcore_bankmachine7_next_state <= 1'd1;
+ end
+ end else begin
+ litedramcore_bankmachine7_next_state <= 2'd3;
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if (litedramcore_bankmachine7_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if (litedramcore_bankmachine7_source_source_payload_we) begin
+ litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if (litedramcore_bankmachine7_source_source_payload_we) begin
+ litedramcore_bankmachine7_req_wdata_ready <= litedramcore_bankmachine7_cmd_ready;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if (litedramcore_bankmachine7_source_source_payload_we) begin
+ end else begin
+ litedramcore_bankmachine7_req_rdata_valid <= litedramcore_bankmachine7_cmd_ready;
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_refresh_gnt <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ if (litedramcore_bankmachine7_twtpcon_ready) begin
+ litedramcore_bankmachine7_refresh_gnt <= 1'd1;
+ end
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_row_open <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_row_open <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_valid <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_cmd_valid <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_cmd_valid <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ litedramcore_bankmachine7_cmd_valid <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_row_close <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ litedramcore_bankmachine7_row_close <= 1'd1;
+ end
+ 2'd2: begin
+ litedramcore_bankmachine7_row_close <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ litedramcore_bankmachine7_row_close <= 1'd1;
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ if (litedramcore_bankmachine7_trccon_ready) begin
+ litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+ end
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
+ case (litedramcore_bankmachine7_state)
+ 1'd1: begin
+ if ((litedramcore_bankmachine7_twtpcon_ready & litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ default: begin
+ if (litedramcore_bankmachine7_refresh_req) begin
+ end else begin
+ if (litedramcore_bankmachine7_source_source_valid) begin
+ if (litedramcore_bankmachine7_row_opened) begin
+ if (litedramcore_bankmachine7_row_hit) begin
+ if (litedramcore_bankmachine7_source_source_payload_we) begin
+ litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+ end else begin
+ end
+ end else begin
+ end
+ end else begin
+ end
+ end
+ end
+ end
+ endcase
end
assign litedramcore_rdcmdphase = (a7ddrphy_rdphase_storage - 1'd1);
assign litedramcore_wrcmdphase = (a7ddrphy_wrphase_storage - 1'd1);
assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
assign {litedramcore_dfi_p3_wrdata_mask, litedramcore_dfi_p2_wrdata_mask, litedramcore_dfi_p1_wrdata_mask, litedramcore_dfi_p0_wrdata_mask} = (~litedramcore_interface_wdata_we);
always @(*) begin
- litedramcore_choose_cmd_valids <= 8'd0;
- litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
- litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids <= 8'd0;
+ litedramcore_choose_cmd_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
+ litedramcore_choose_cmd_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_cmd_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_cmd_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_cmd_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_cmd_want_writes))));
end
assign litedramcore_choose_cmd_request = litedramcore_choose_cmd_valids;
assign litedramcore_choose_cmd_cmd_valid = rhs_array_muxed0;
assign litedramcore_choose_cmd_cmd_payload_is_write = rhs_array_muxed4;
assign litedramcore_choose_cmd_cmd_payload_is_cmd = rhs_array_muxed5;
always @(*) begin
- litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
- if (litedramcore_choose_cmd_cmd_valid) begin
- litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0;
- end
+ litedramcore_choose_cmd_cmd_payload_cas <= 1'd0;
+ if (litedramcore_choose_cmd_cmd_valid) begin
+ litedramcore_choose_cmd_cmd_payload_cas <= t_array_muxed0;
+ end
end
always @(*) begin
- litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
- if (litedramcore_choose_cmd_cmd_valid) begin
- litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1;
- end
+ litedramcore_choose_cmd_cmd_payload_ras <= 1'd0;
+ if (litedramcore_choose_cmd_cmd_valid) begin
+ litedramcore_choose_cmd_cmd_payload_ras <= t_array_muxed1;
+ end
end
always @(*) begin
- litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
- if (litedramcore_choose_cmd_cmd_valid) begin
- litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2;
- end
+ litedramcore_choose_cmd_cmd_payload_we <= 1'd0;
+ if (litedramcore_choose_cmd_cmd_valid) begin
+ litedramcore_choose_cmd_cmd_payload_we <= t_array_muxed2;
+ end
end
always @(*) begin
- litedramcore_bankmachine0_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin
- litedramcore_bankmachine0_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin
- litedramcore_bankmachine0_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine0_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd0))) begin
+ litedramcore_bankmachine0_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd0))) begin
+ litedramcore_bankmachine0_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_bankmachine1_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin
- litedramcore_bankmachine1_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin
- litedramcore_bankmachine1_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine1_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 1'd1))) begin
+ litedramcore_bankmachine1_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 1'd1))) begin
+ litedramcore_bankmachine1_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_bankmachine2_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin
- litedramcore_bankmachine2_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin
- litedramcore_bankmachine2_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine2_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd2))) begin
+ litedramcore_bankmachine2_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd2))) begin
+ litedramcore_bankmachine2_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_bankmachine3_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin
- litedramcore_bankmachine3_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin
- litedramcore_bankmachine3_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine3_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 2'd3))) begin
+ litedramcore_bankmachine3_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 2'd3))) begin
+ litedramcore_bankmachine3_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_bankmachine4_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin
- litedramcore_bankmachine4_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin
- litedramcore_bankmachine4_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine4_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd4))) begin
+ litedramcore_bankmachine4_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd4))) begin
+ litedramcore_bankmachine4_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_bankmachine5_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin
- litedramcore_bankmachine5_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin
- litedramcore_bankmachine5_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine5_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd5))) begin
+ litedramcore_bankmachine5_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd5))) begin
+ litedramcore_bankmachine5_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_bankmachine6_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin
- litedramcore_bankmachine6_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin
- litedramcore_bankmachine6_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine6_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd6))) begin
+ litedramcore_bankmachine6_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd6))) begin
+ litedramcore_bankmachine6_cmd_ready <= 1'd1;
+ end
end
always @(*) begin
- litedramcore_bankmachine7_cmd_ready <= 1'd0;
- if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin
- litedramcore_bankmachine7_cmd_ready <= 1'd1;
- end
- if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin
- litedramcore_bankmachine7_cmd_ready <= 1'd1;
- end
+ litedramcore_bankmachine7_cmd_ready <= 1'd0;
+ if (((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & (litedramcore_choose_cmd_grant == 3'd7))) begin
+ litedramcore_bankmachine7_cmd_ready <= 1'd1;
+ end
+ if (((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & (litedramcore_choose_req_grant == 3'd7))) begin
+ litedramcore_bankmachine7_cmd_ready <= 1'd1;
+ end
end
assign litedramcore_choose_cmd_ce = (litedramcore_choose_cmd_cmd_ready | (~litedramcore_choose_cmd_cmd_valid));
always @(*) begin
- litedramcore_choose_req_valids <= 8'd0;
- litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
- litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids <= 8'd0;
+ litedramcore_choose_req_valids[0] <= (litedramcore_bankmachine0_cmd_valid & (((litedramcore_bankmachine0_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine0_cmd_payload_ras & (~litedramcore_bankmachine0_cmd_payload_cas)) & (~litedramcore_bankmachine0_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine0_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine0_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[1] <= (litedramcore_bankmachine1_cmd_valid & (((litedramcore_bankmachine1_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine1_cmd_payload_ras & (~litedramcore_bankmachine1_cmd_payload_cas)) & (~litedramcore_bankmachine1_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine1_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine1_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[2] <= (litedramcore_bankmachine2_cmd_valid & (((litedramcore_bankmachine2_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine2_cmd_payload_ras & (~litedramcore_bankmachine2_cmd_payload_cas)) & (~litedramcore_bankmachine2_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine2_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine2_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[3] <= (litedramcore_bankmachine3_cmd_valid & (((litedramcore_bankmachine3_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine3_cmd_payload_ras & (~litedramcore_bankmachine3_cmd_payload_cas)) & (~litedramcore_bankmachine3_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine3_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine3_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[4] <= (litedramcore_bankmachine4_cmd_valid & (((litedramcore_bankmachine4_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine4_cmd_payload_ras & (~litedramcore_bankmachine4_cmd_payload_cas)) & (~litedramcore_bankmachine4_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine4_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine4_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[5] <= (litedramcore_bankmachine5_cmd_valid & (((litedramcore_bankmachine5_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine5_cmd_payload_ras & (~litedramcore_bankmachine5_cmd_payload_cas)) & (~litedramcore_bankmachine5_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine5_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine5_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[6] <= (litedramcore_bankmachine6_cmd_valid & (((litedramcore_bankmachine6_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine6_cmd_payload_ras & (~litedramcore_bankmachine6_cmd_payload_cas)) & (~litedramcore_bankmachine6_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine6_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine6_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
+ litedramcore_choose_req_valids[7] <= (litedramcore_bankmachine7_cmd_valid & (((litedramcore_bankmachine7_cmd_payload_is_cmd & litedramcore_choose_req_want_cmds) & ((~((litedramcore_bankmachine7_cmd_payload_ras & (~litedramcore_bankmachine7_cmd_payload_cas)) & (~litedramcore_bankmachine7_cmd_payload_we))) | litedramcore_choose_req_want_activates)) | ((litedramcore_bankmachine7_cmd_payload_is_read == litedramcore_choose_req_want_reads) & (litedramcore_bankmachine7_cmd_payload_is_write == litedramcore_choose_req_want_writes))));
end
assign litedramcore_choose_req_request = litedramcore_choose_req_valids;
assign litedramcore_choose_req_cmd_valid = rhs_array_muxed6;
assign litedramcore_choose_req_cmd_payload_is_write = rhs_array_muxed10;
assign litedramcore_choose_req_cmd_payload_is_cmd = rhs_array_muxed11;
always @(*) begin
- litedramcore_choose_req_cmd_payload_cas <= 1'd0;
- if (litedramcore_choose_req_cmd_valid) begin
- litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3;
- end
+ litedramcore_choose_req_cmd_payload_cas <= 1'd0;
+ if (litedramcore_choose_req_cmd_valid) begin
+ litedramcore_choose_req_cmd_payload_cas <= t_array_muxed3;
+ end
end
always @(*) begin
- litedramcore_choose_req_cmd_payload_ras <= 1'd0;
- if (litedramcore_choose_req_cmd_valid) begin
- litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4;
- end
+ litedramcore_choose_req_cmd_payload_ras <= 1'd0;
+ if (litedramcore_choose_req_cmd_valid) begin
+ litedramcore_choose_req_cmd_payload_ras <= t_array_muxed4;
+ end
end
always @(*) begin
- litedramcore_choose_req_cmd_payload_we <= 1'd0;
- if (litedramcore_choose_req_cmd_valid) begin
- litedramcore_choose_req_cmd_payload_we <= t_array_muxed5;
- end
+ litedramcore_choose_req_cmd_payload_we <= 1'd0;
+ if (litedramcore_choose_req_cmd_valid) begin
+ litedramcore_choose_req_cmd_payload_we <= t_array_muxed5;
+ end
end
assign litedramcore_choose_req_ce = (litedramcore_choose_req_cmd_ready | (~litedramcore_choose_req_cmd_valid));
assign litedramcore_dfi_p0_reset_n = 1'd1;
assign litedramcore_dfi_p3_odt = {1{litedramcore_steerer7}};
assign litedramcore_tfawcon_count = ((((litedramcore_tfawcon_window[0] + litedramcore_tfawcon_window[1]) + litedramcore_tfawcon_window[2]) + litedramcore_tfawcon_window[3]) + litedramcore_tfawcon_window[4]);
always @(*) begin
- litedramcore_multiplexer_next_state <= 4'd0;
- litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- if (litedramcore_read_available) begin
- if (((~litedramcore_write_available) | litedramcore_max_time1)) begin
- litedramcore_multiplexer_next_state <= 2'd3;
- end
- end
- if (litedramcore_go_to_refresh) begin
- litedramcore_multiplexer_next_state <= 2'd2;
- end
- end
- 2'd2: begin
- if (litedramcore_cmd_last) begin
- litedramcore_multiplexer_next_state <= 1'd0;
- end
- end
- 2'd3: begin
- if (litedramcore_twtrcon_ready) begin
- litedramcore_multiplexer_next_state <= 1'd0;
- end
- end
- 3'd4: begin
- litedramcore_multiplexer_next_state <= 3'd5;
- end
- 3'd5: begin
- litedramcore_multiplexer_next_state <= 3'd6;
- end
- 3'd6: begin
- litedramcore_multiplexer_next_state <= 3'd7;
- end
- 3'd7: begin
- litedramcore_multiplexer_next_state <= 4'd8;
- end
- 4'd8: begin
- litedramcore_multiplexer_next_state <= 4'd9;
- end
- 4'd9: begin
- litedramcore_multiplexer_next_state <= 4'd10;
- end
- 4'd10: begin
- litedramcore_multiplexer_next_state <= 1'd1;
- end
- default: begin
- if (litedramcore_write_available) begin
- if (((~litedramcore_read_available) | litedramcore_max_time0)) begin
- litedramcore_multiplexer_next_state <= 3'd4;
- end
- end
- if (litedramcore_go_to_refresh) begin
- litedramcore_multiplexer_next_state <= 2'd2;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_steerer_sel0 <= 2'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- litedramcore_steerer_sel0 <= 1'd0;
- if ((a7ddrphy_wrphase_storage == 1'd0)) begin
- litedramcore_steerer_sel0 <= 2'd2;
- end
- if ((litedramcore_wrcmdphase == 1'd0)) begin
- litedramcore_steerer_sel0 <= 1'd1;
- end
- end
- 2'd2: begin
- litedramcore_steerer_sel0 <= 2'd3;
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- litedramcore_steerer_sel0 <= 1'd0;
- if ((a7ddrphy_rdphase_storage == 1'd0)) begin
- litedramcore_steerer_sel0 <= 2'd2;
- end
- if ((litedramcore_rdcmdphase == 1'd0)) begin
- litedramcore_steerer_sel0 <= 1'd1;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_cmd_ready <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- end
- 2'd2: begin
- litedramcore_cmd_ready <= 1'd1;
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_steerer_sel1 <= 2'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- litedramcore_steerer_sel1 <= 1'd0;
- if ((a7ddrphy_wrphase_storage == 1'd1)) begin
- litedramcore_steerer_sel1 <= 2'd2;
- end
- if ((litedramcore_wrcmdphase == 1'd1)) begin
- litedramcore_steerer_sel1 <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- litedramcore_steerer_sel1 <= 1'd0;
- if ((a7ddrphy_rdphase_storage == 1'd1)) begin
- litedramcore_steerer_sel1 <= 2'd2;
- end
- if ((litedramcore_rdcmdphase == 1'd1)) begin
- litedramcore_steerer_sel1 <= 1'd1;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_steerer_sel2 <= 2'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- litedramcore_steerer_sel2 <= 1'd0;
- if ((a7ddrphy_wrphase_storage == 2'd2)) begin
- litedramcore_steerer_sel2 <= 2'd2;
- end
- if ((litedramcore_wrcmdphase == 2'd2)) begin
- litedramcore_steerer_sel2 <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- litedramcore_steerer_sel2 <= 1'd0;
- if ((a7ddrphy_rdphase_storage == 2'd2)) begin
- litedramcore_steerer_sel2 <= 2'd2;
- end
- if ((litedramcore_rdcmdphase == 2'd2)) begin
- litedramcore_steerer_sel2 <= 1'd1;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_choose_cmd_want_activates <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_steerer_sel3 <= 2'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- litedramcore_steerer_sel3 <= 1'd0;
- if ((a7ddrphy_wrphase_storage == 2'd3)) begin
- litedramcore_steerer_sel3 <= 2'd2;
- end
- if ((litedramcore_wrcmdphase == 2'd3)) begin
- litedramcore_steerer_sel3 <= 1'd1;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- litedramcore_steerer_sel3 <= 1'd0;
- if ((a7ddrphy_rdphase_storage == 2'd3)) begin
- litedramcore_steerer_sel3 <= 2'd2;
- end
- if ((litedramcore_rdcmdphase == 2'd3)) begin
- litedramcore_steerer_sel3 <= 1'd1;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_en0 <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- litedramcore_en0 <= 1'd1;
- end
- endcase
-end
-always @(*) begin
- litedramcore_choose_cmd_cmd_ready <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- if (1'd0) begin
- end else begin
- litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_choose_req_want_reads <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- litedramcore_choose_req_want_reads <= 1'd1;
- end
- endcase
-end
-always @(*) begin
- litedramcore_choose_req_want_writes <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- litedramcore_choose_req_want_writes <= 1'd1;
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_choose_req_cmd_ready <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- if (1'd0) begin
- litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
- end else begin
- litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
- end
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- if (1'd0) begin
- litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
- end else begin
- litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_en1 <= 1'd0;
- case (litedramcore_multiplexer_state)
- 1'd1: begin
- litedramcore_en1 <= 1'd1;
- end
- 2'd2: begin
- end
- 2'd3: begin
- end
- 3'd4: begin
- end
- 3'd5: begin
- end
- 3'd6: begin
- end
- 3'd7: begin
- end
- 4'd8: begin
- end
- 4'd9: begin
- end
- 4'd10: begin
- end
- default: begin
- end
- endcase
+ litedramcore_multiplexer_next_state <= 4'd0;
+ litedramcore_multiplexer_next_state <= litedramcore_multiplexer_state;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ if (litedramcore_read_available) begin
+ if (((~litedramcore_write_available) | litedramcore_max_time1)) begin
+ litedramcore_multiplexer_next_state <= 2'd3;
+ end
+ end
+ if (litedramcore_go_to_refresh) begin
+ litedramcore_multiplexer_next_state <= 2'd2;
+ end
+ end
+ 2'd2: begin
+ if (litedramcore_cmd_last) begin
+ litedramcore_multiplexer_next_state <= 1'd0;
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_twtrcon_ready) begin
+ litedramcore_multiplexer_next_state <= 1'd0;
+ end
+ end
+ 3'd4: begin
+ litedramcore_multiplexer_next_state <= 3'd5;
+ end
+ 3'd5: begin
+ litedramcore_multiplexer_next_state <= 3'd6;
+ end
+ 3'd6: begin
+ litedramcore_multiplexer_next_state <= 3'd7;
+ end
+ 3'd7: begin
+ litedramcore_multiplexer_next_state <= 4'd8;
+ end
+ 4'd8: begin
+ litedramcore_multiplexer_next_state <= 4'd9;
+ end
+ 4'd9: begin
+ litedramcore_multiplexer_next_state <= 4'd10;
+ end
+ 4'd10: begin
+ litedramcore_multiplexer_next_state <= 1'd1;
+ end
+ default: begin
+ if (litedramcore_write_available) begin
+ if (((~litedramcore_read_available) | litedramcore_max_time0)) begin
+ litedramcore_multiplexer_next_state <= 3'd4;
+ end
+ end
+ if (litedramcore_go_to_refresh) begin
+ litedramcore_multiplexer_next_state <= 2'd2;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_steerer_sel0 <= 2'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ litedramcore_steerer_sel0 <= 1'd0;
+ if ((a7ddrphy_wrphase_storage == 1'd0)) begin
+ litedramcore_steerer_sel0 <= 2'd2;
+ end
+ if ((litedramcore_wrcmdphase == 1'd0)) begin
+ litedramcore_steerer_sel0 <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ litedramcore_steerer_sel0 <= 2'd3;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ litedramcore_steerer_sel0 <= 1'd0;
+ if ((a7ddrphy_rdphase_storage == 1'd0)) begin
+ litedramcore_steerer_sel0 <= 2'd2;
+ end
+ if ((litedramcore_rdcmdphase == 1'd0)) begin
+ litedramcore_steerer_sel0 <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_cmd_ready <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ litedramcore_cmd_ready <= 1'd1;
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_steerer_sel1 <= 2'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ litedramcore_steerer_sel1 <= 1'd0;
+ if ((a7ddrphy_wrphase_storage == 1'd1)) begin
+ litedramcore_steerer_sel1 <= 2'd2;
+ end
+ if ((litedramcore_wrcmdphase == 1'd1)) begin
+ litedramcore_steerer_sel1 <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ litedramcore_steerer_sel1 <= 1'd0;
+ if ((a7ddrphy_rdphase_storage == 1'd1)) begin
+ litedramcore_steerer_sel1 <= 2'd2;
+ end
+ if ((litedramcore_rdcmdphase == 1'd1)) begin
+ litedramcore_steerer_sel1 <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_steerer_sel2 <= 2'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ litedramcore_steerer_sel2 <= 1'd0;
+ if ((a7ddrphy_wrphase_storage == 2'd2)) begin
+ litedramcore_steerer_sel2 <= 2'd2;
+ end
+ if ((litedramcore_wrcmdphase == 2'd2)) begin
+ litedramcore_steerer_sel2 <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ litedramcore_steerer_sel2 <= 1'd0;
+ if ((a7ddrphy_rdphase_storage == 2'd2)) begin
+ litedramcore_steerer_sel2 <= 2'd2;
+ end
+ if ((litedramcore_rdcmdphase == 2'd2)) begin
+ litedramcore_steerer_sel2 <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_choose_cmd_want_activates <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ if (1'd0) begin
+ end else begin
+ litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ if (1'd0) begin
+ end else begin
+ litedramcore_choose_cmd_want_activates <= litedramcore_ras_allowed;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_steerer_sel3 <= 2'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ litedramcore_steerer_sel3 <= 1'd0;
+ if ((a7ddrphy_wrphase_storage == 2'd3)) begin
+ litedramcore_steerer_sel3 <= 2'd2;
+ end
+ if ((litedramcore_wrcmdphase == 2'd3)) begin
+ litedramcore_steerer_sel3 <= 1'd1;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ litedramcore_steerer_sel3 <= 1'd0;
+ if ((a7ddrphy_rdphase_storage == 2'd3)) begin
+ litedramcore_steerer_sel3 <= 2'd2;
+ end
+ if ((litedramcore_rdcmdphase == 2'd3)) begin
+ litedramcore_steerer_sel3 <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_en0 <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ litedramcore_en0 <= 1'd1;
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_choose_cmd_cmd_ready <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ if (1'd0) begin
+ end else begin
+ litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ if (1'd0) begin
+ end else begin
+ litedramcore_choose_cmd_cmd_ready <= ((~((litedramcore_choose_cmd_cmd_payload_ras & (~litedramcore_choose_cmd_cmd_payload_cas)) & (~litedramcore_choose_cmd_cmd_payload_we))) | litedramcore_ras_allowed);
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_choose_req_want_reads <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ litedramcore_choose_req_want_reads <= 1'd1;
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_choose_req_want_writes <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ litedramcore_choose_req_want_writes <= 1'd1;
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_choose_req_cmd_ready <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ if (1'd0) begin
+ litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+ end else begin
+ litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+ end
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ if (1'd0) begin
+ litedramcore_choose_req_cmd_ready <= (litedramcore_cas_allowed & ((~((litedramcore_choose_req_cmd_payload_ras & (~litedramcore_choose_req_cmd_payload_cas)) & (~litedramcore_choose_req_cmd_payload_we))) | litedramcore_ras_allowed));
+ end else begin
+ litedramcore_choose_req_cmd_ready <= litedramcore_cas_allowed;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_en1 <= 1'd0;
+ case (litedramcore_multiplexer_state)
+ 1'd1: begin
+ litedramcore_en1 <= 1'd1;
+ end
+ 2'd2: begin
+ end
+ 2'd3: begin
+ end
+ 3'd4: begin
+ end
+ 3'd5: begin
+ end
+ 3'd6: begin
+ end
+ 3'd7: begin
+ end
+ 4'd8: begin
+ end
+ 4'd9: begin
+ end
+ 4'd10: begin
+ end
+ default: begin
+ end
+ endcase
end
assign litedramcore_roundrobin0_request = {(((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid)};
assign litedramcore_roundrobin0_ce = ((~litedramcore_interface_bank0_valid) & (~litedramcore_interface_bank0_lock));
assign user_port_wdata_ready = litedramcore_new_master_wdata_ready1;
assign user_port_rdata_valid = litedramcore_new_master_rdata_valid8;
always @(*) begin
- litedramcore_interface_wdata <= 128'd0;
- case ({litedramcore_new_master_wdata_ready1})
- 1'd1: begin
- litedramcore_interface_wdata <= user_port_wdata_payload_data;
- end
- default: begin
- litedramcore_interface_wdata <= 1'd0;
- end
- endcase
-end
-always @(*) begin
- litedramcore_interface_wdata_we <= 16'd0;
- case ({litedramcore_new_master_wdata_ready1})
- 1'd1: begin
- litedramcore_interface_wdata_we <= user_port_wdata_payload_we;
- end
- default: begin
- litedramcore_interface_wdata_we <= 1'd0;
- end
- endcase
+ litedramcore_interface_wdata <= 128'd0;
+ case ({litedramcore_new_master_wdata_ready1})
+ 1'd1: begin
+ litedramcore_interface_wdata <= user_port_wdata_payload_data;
+ end
+ default: begin
+ litedramcore_interface_wdata <= 1'd0;
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_interface_wdata_we <= 16'd0;
+ case ({litedramcore_new_master_wdata_ready1})
+ 1'd1: begin
+ litedramcore_interface_wdata_we <= user_port_wdata_payload_we;
+ end
+ default: begin
+ litedramcore_interface_wdata_we <= 1'd0;
+ end
+ endcase
end
assign user_port_rdata_payload_data = litedramcore_interface_rdata;
assign litedramcore_roundrobin0_grant = 1'd0;
assign litedramcore_roundrobin6_grant = 1'd0;
assign litedramcore_roundrobin7_grant = 1'd0;
always @(*) begin
- litedramcore_next_state <= 2'd0;
- litedramcore_next_state <= litedramcore_state;
- case (litedramcore_state)
- 1'd1: begin
- litedramcore_next_state <= 2'd2;
- end
- 2'd2: begin
- litedramcore_next_state <= 1'd0;
- end
- default: begin
- if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_next_state <= 1'd1;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_we_next_value2 <= 1'd0;
- case (litedramcore_state)
- 1'd1: begin
- litedramcore_we_next_value2 <= 1'd0;
- end
- 2'd2: begin
- end
- default: begin
- if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_we_next_value_ce2 <= 1'd0;
- case (litedramcore_state)
- 1'd1: begin
- litedramcore_we_next_value_ce2 <= 1'd1;
- end
- 2'd2: begin
- end
- default: begin
- if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_we_next_value_ce2 <= 1'd1;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_wishbone_ack <= 1'd0;
- case (litedramcore_state)
- 1'd1: begin
- end
- 2'd2: begin
- litedramcore_wishbone_ack <= 1'd1;
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_wishbone_dat_r <= 32'd0;
- case (litedramcore_state)
- 1'd1: begin
- end
- 2'd2: begin
- litedramcore_wishbone_dat_r <= litedramcore_dat_r;
- end
- default: begin
- end
- endcase
-end
-always @(*) begin
- litedramcore_dat_w_next_value0 <= 32'd0;
- case (litedramcore_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- default: begin
- litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w;
- end
- endcase
-end
-always @(*) begin
- litedramcore_dat_w_next_value_ce0 <= 1'd0;
- case (litedramcore_state)
- 1'd1: begin
- end
- 2'd2: begin
- end
- default: begin
- litedramcore_dat_w_next_value_ce0 <= 1'd1;
- end
- endcase
-end
-always @(*) begin
- litedramcore_adr_next_value1 <= 14'd0;
- case (litedramcore_state)
- 1'd1: begin
- litedramcore_adr_next_value1 <= 1'd0;
- end
- 2'd2: begin
- end
- default: begin
- if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_adr_next_value1 <= litedramcore_wishbone_adr;
- end
- end
- endcase
-end
-always @(*) begin
- litedramcore_adr_next_value_ce1 <= 1'd0;
- case (litedramcore_state)
- 1'd1: begin
- litedramcore_adr_next_value_ce1 <= 1'd1;
- end
- 2'd2: begin
- end
- default: begin
- if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
- litedramcore_adr_next_value_ce1 <= 1'd1;
- end
- end
- endcase
+ litedramcore_next_state <= 2'd0;
+ litedramcore_next_state <= litedramcore_state;
+ case (litedramcore_state)
+ 1'd1: begin
+ litedramcore_next_state <= 2'd2;
+ end
+ 2'd2: begin
+ litedramcore_next_state <= 1'd0;
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_next_state <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_we_next_value2 <= 1'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ litedramcore_we_next_value2 <= 1'd0;
+ end
+ 2'd2: begin
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_we_next_value2 <= (litedramcore_wishbone_we & (litedramcore_wishbone_sel != 1'd0));
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_we_next_value_ce2 <= 1'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ litedramcore_we_next_value_ce2 <= 1'd1;
+ end
+ 2'd2: begin
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_we_next_value_ce2 <= 1'd1;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_wishbone_ack <= 1'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ litedramcore_wishbone_ack <= 1'd1;
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_wishbone_dat_r <= 32'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ litedramcore_wishbone_dat_r <= litedramcore_dat_r;
+ end
+ default: begin
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_dat_w_next_value0 <= 32'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ default: begin
+ litedramcore_dat_w_next_value0 <= litedramcore_wishbone_dat_w;
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_dat_w_next_value_ce0 <= 1'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ end
+ 2'd2: begin
+ end
+ default: begin
+ litedramcore_dat_w_next_value_ce0 <= 1'd1;
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_adr_next_value1 <= 14'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ litedramcore_adr_next_value1 <= 1'd0;
+ end
+ 2'd2: begin
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_adr_next_value1 <= litedramcore_wishbone_adr;
+ end
+ end
+ endcase
+end
+always @(*) begin
+ litedramcore_adr_next_value_ce1 <= 1'd0;
+ case (litedramcore_state)
+ 1'd1: begin
+ litedramcore_adr_next_value_ce1 <= 1'd1;
+ end
+ 2'd2: begin
+ end
+ default: begin
+ if ((litedramcore_wishbone_cyc & litedramcore_wishbone_stb)) begin
+ litedramcore_adr_next_value_ce1 <= 1'd1;
+ end
+ end
+ endcase
end
assign litedramcore_wishbone_adr = wb_bus_adr;
assign litedramcore_wishbone_dat_w = wb_bus_dat_w;
assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0);
assign csrbank0_init_done0_r = interface0_bank_bus_dat_w[0];
always @(*) begin
- csrbank0_init_done0_we <= 1'd0;
- if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
- csrbank0_init_done0_we <= (~interface0_bank_bus_we);
- end
+ csrbank0_init_done0_we <= 1'd0;
+ if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank0_init_done0_we <= (~interface0_bank_bus_we);
+ end
end
always @(*) begin
- csrbank0_init_done0_re <= 1'd0;
- if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
- csrbank0_init_done0_re <= interface0_bank_bus_we;
- end
+ csrbank0_init_done0_re <= 1'd0;
+ if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank0_init_done0_re <= interface0_bank_bus_we;
+ end
end
assign csrbank0_init_error0_r = interface0_bank_bus_dat_w[0];
always @(*) begin
- csrbank0_init_error0_re <= 1'd0;
- if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
- csrbank0_init_error0_re <= interface0_bank_bus_we;
- end
+ csrbank0_init_error0_re <= 1'd0;
+ if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
+ csrbank0_init_error0_re <= interface0_bank_bus_we;
+ end
end
always @(*) begin
- csrbank0_init_error0_we <= 1'd0;
- if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
- csrbank0_init_error0_we <= (~interface0_bank_bus_we);
- end
+ csrbank0_init_error0_we <= 1'd0;
+ if ((csrbank0_sel & (interface0_bank_bus_adr[8:0] == 1'd1))) begin
+ csrbank0_init_error0_we <= (~interface0_bank_bus_we);
+ end
end
assign csrbank0_init_done0_w = init_done_storage;
assign csrbank0_init_error0_w = init_error_storage;
assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 1'd1);
assign csrbank1_rst0_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- csrbank1_rst0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
- csrbank1_rst0_re <= interface1_bank_bus_we;
- end
+ csrbank1_rst0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank1_rst0_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- csrbank1_rst0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
- csrbank1_rst0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_rst0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank1_rst0_we <= (~interface1_bank_bus_we);
+ end
end
assign csrbank1_dly_sel0_r = interface1_bank_bus_dat_w[1:0];
always @(*) begin
- csrbank1_dly_sel0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
- csrbank1_dly_sel0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_dly_sel0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
+ csrbank1_dly_sel0_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- csrbank1_dly_sel0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
- csrbank1_dly_sel0_re <= interface1_bank_bus_we;
- end
+ csrbank1_dly_sel0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 1'd1))) begin
+ csrbank1_dly_sel0_re <= interface1_bank_bus_we;
+ end
end
assign csrbank1_half_sys8x_taps0_r = interface1_bank_bus_dat_w[4:0];
always @(*) begin
- csrbank1_half_sys8x_taps0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
- csrbank1_half_sys8x_taps0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_half_sys8x_taps0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
+ csrbank1_half_sys8x_taps0_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- csrbank1_half_sys8x_taps0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
- csrbank1_half_sys8x_taps0_re <= interface1_bank_bus_we;
- end
+ csrbank1_half_sys8x_taps0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd2))) begin
+ csrbank1_half_sys8x_taps0_re <= interface1_bank_bus_we;
+ end
end
assign csrbank1_wlevel_en0_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- csrbank1_wlevel_en0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
- csrbank1_wlevel_en0_re <= interface1_bank_bus_we;
- end
+ csrbank1_wlevel_en0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
+ csrbank1_wlevel_en0_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- csrbank1_wlevel_en0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
- csrbank1_wlevel_en0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_wlevel_en0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 2'd3))) begin
+ csrbank1_wlevel_en0_we <= (~interface1_bank_bus_we);
+ end
end
assign a7ddrphy_wlevel_strobe_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- a7ddrphy_wlevel_strobe_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
- a7ddrphy_wlevel_strobe_re <= interface1_bank_bus_we;
- end
+ a7ddrphy_wlevel_strobe_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
+ a7ddrphy_wlevel_strobe_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- a7ddrphy_wlevel_strobe_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
- a7ddrphy_wlevel_strobe_we <= (~interface1_bank_bus_we);
- end
+ a7ddrphy_wlevel_strobe_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd4))) begin
+ a7ddrphy_wlevel_strobe_we <= (~interface1_bank_bus_we);
+ end
end
assign a7ddrphy_rdly_dq_rst_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- a7ddrphy_rdly_dq_rst_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
- a7ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we;
- end
+ a7ddrphy_rdly_dq_rst_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
+ a7ddrphy_rdly_dq_rst_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- a7ddrphy_rdly_dq_rst_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
- a7ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we);
- end
+ a7ddrphy_rdly_dq_rst_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd5))) begin
+ a7ddrphy_rdly_dq_rst_we <= (~interface1_bank_bus_we);
+ end
end
assign a7ddrphy_rdly_dq_inc_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- a7ddrphy_rdly_dq_inc_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
- a7ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we;
- end
+ a7ddrphy_rdly_dq_inc_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
+ a7ddrphy_rdly_dq_inc_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- a7ddrphy_rdly_dq_inc_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
- a7ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we);
- end
+ a7ddrphy_rdly_dq_inc_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd6))) begin
+ a7ddrphy_rdly_dq_inc_we <= (~interface1_bank_bus_we);
+ end
end
assign a7ddrphy_rdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
- a7ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
- end
+ a7ddrphy_rdly_dq_bitslip_rst_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
+ a7ddrphy_rdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
- a7ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
- end
+ a7ddrphy_rdly_dq_bitslip_rst_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 3'd7))) begin
+ a7ddrphy_rdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
+ end
end
assign a7ddrphy_rdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- a7ddrphy_rdly_dq_bitslip_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
- a7ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we);
- end
+ a7ddrphy_rdly_dq_bitslip_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
+ a7ddrphy_rdly_dq_bitslip_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- a7ddrphy_rdly_dq_bitslip_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
- a7ddrphy_rdly_dq_bitslip_re <= interface1_bank_bus_we;
- end
+ a7ddrphy_rdly_dq_bitslip_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd8))) begin
+ a7ddrphy_rdly_dq_bitslip_re <= interface1_bank_bus_we;
+ end
end
assign a7ddrphy_wdly_dq_bitslip_rst_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
- a7ddrphy_wdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
- end
+ a7ddrphy_wdly_dq_bitslip_rst_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
+ a7ddrphy_wdly_dq_bitslip_rst_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
- a7ddrphy_wdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
- end
+ a7ddrphy_wdly_dq_bitslip_rst_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd9))) begin
+ a7ddrphy_wdly_dq_bitslip_rst_re <= interface1_bank_bus_we;
+ end
end
assign a7ddrphy_wdly_dq_bitslip_r = interface1_bank_bus_dat_w[0];
always @(*) begin
- a7ddrphy_wdly_dq_bitslip_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
- a7ddrphy_wdly_dq_bitslip_we <= (~interface1_bank_bus_we);
- end
+ a7ddrphy_wdly_dq_bitslip_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
+ a7ddrphy_wdly_dq_bitslip_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- a7ddrphy_wdly_dq_bitslip_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
- a7ddrphy_wdly_dq_bitslip_re <= interface1_bank_bus_we;
- end
+ a7ddrphy_wdly_dq_bitslip_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd10))) begin
+ a7ddrphy_wdly_dq_bitslip_re <= interface1_bank_bus_we;
+ end
end
assign csrbank1_rdphase0_r = interface1_bank_bus_dat_w[1:0];
always @(*) begin
- csrbank1_rdphase0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
- csrbank1_rdphase0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_rdphase0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
+ csrbank1_rdphase0_we <= (~interface1_bank_bus_we);
+ end
end
always @(*) begin
- csrbank1_rdphase0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
- csrbank1_rdphase0_re <= interface1_bank_bus_we;
- end
+ csrbank1_rdphase0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd11))) begin
+ csrbank1_rdphase0_re <= interface1_bank_bus_we;
+ end
end
assign csrbank1_wrphase0_r = interface1_bank_bus_dat_w[1:0];
always @(*) begin
- csrbank1_wrphase0_re <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
- csrbank1_wrphase0_re <= interface1_bank_bus_we;
- end
+ csrbank1_wrphase0_re <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
+ csrbank1_wrphase0_re <= interface1_bank_bus_we;
+ end
end
always @(*) begin
- csrbank1_wrphase0_we <= 1'd0;
- if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
- csrbank1_wrphase0_we <= (~interface1_bank_bus_we);
- end
+ csrbank1_wrphase0_we <= 1'd0;
+ if ((csrbank1_sel & (interface1_bank_bus_adr[8:0] == 4'd12))) begin
+ csrbank1_wrphase0_we <= (~interface1_bank_bus_we);
+ end
end
assign csrbank1_rst0_w = a7ddrphy_rst_storage;
assign csrbank1_dly_sel0_w = a7ddrphy_dly_sel_storage[1:0];
assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd2);
assign csrbank2_dfii_control0_r = interface2_bank_bus_dat_w[3:0];
always @(*) begin
- csrbank2_dfii_control0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
- csrbank2_dfii_control0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_control0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank2_dfii_control0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_control0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
- csrbank2_dfii_control0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_control0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd0))) begin
+ csrbank2_dfii_control0_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi0_command0_r = interface2_bank_bus_dat_w[5:0];
always @(*) begin
- csrbank2_dfii_pi0_command0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
- csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi0_command0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
+ csrbank2_dfii_pi0_command0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi0_command0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
- csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi0_command0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 1'd1))) begin
+ csrbank2_dfii_pi0_command0_we <= (~interface2_bank_bus_we);
+ end
end
assign litedramcore_phaseinjector0_command_issue_r = interface2_bank_bus_dat_w[0];
always @(*) begin
- litedramcore_phaseinjector0_command_issue_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
- litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we;
- end
+ litedramcore_phaseinjector0_command_issue_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
+ litedramcore_phaseinjector0_command_issue_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- litedramcore_phaseinjector0_command_issue_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
- litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we);
- end
+ litedramcore_phaseinjector0_command_issue_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd2))) begin
+ litedramcore_phaseinjector0_command_issue_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi0_address0_r = interface2_bank_bus_dat_w[13:0];
always @(*) begin
- csrbank2_dfii_pi0_address0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
- csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi0_address0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
+ csrbank2_dfii_pi0_address0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi0_address0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
- csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi0_address0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 2'd3))) begin
+ csrbank2_dfii_pi0_address0_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi0_baddress0_r = interface2_bank_bus_dat_w[2:0];
always @(*) begin
- csrbank2_dfii_pi0_baddress0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
- csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi0_baddress0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
+ csrbank2_dfii_pi0_baddress0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi0_baddress0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
- csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi0_baddress0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd4))) begin
+ csrbank2_dfii_pi0_baddress0_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi0_wrdata0_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
- csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi0_wrdata0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
+ csrbank2_dfii_pi0_wrdata0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
- csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi0_wrdata0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd5))) begin
+ csrbank2_dfii_pi0_wrdata0_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi0_rddata_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi0_rddata_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
- csrbank2_dfii_pi0_rddata_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi0_rddata_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
+ csrbank2_dfii_pi0_rddata_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi0_rddata_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
- csrbank2_dfii_pi0_rddata_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi0_rddata_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd6))) begin
+ csrbank2_dfii_pi0_rddata_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi1_command0_r = interface2_bank_bus_dat_w[5:0];
always @(*) begin
- csrbank2_dfii_pi1_command0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
- csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi1_command0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
+ csrbank2_dfii_pi1_command0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi1_command0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
- csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi1_command0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 3'd7))) begin
+ csrbank2_dfii_pi1_command0_re <= interface2_bank_bus_we;
+ end
end
assign litedramcore_phaseinjector1_command_issue_r = interface2_bank_bus_dat_w[0];
always @(*) begin
- litedramcore_phaseinjector1_command_issue_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
- litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we);
- end
+ litedramcore_phaseinjector1_command_issue_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
+ litedramcore_phaseinjector1_command_issue_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- litedramcore_phaseinjector1_command_issue_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
- litedramcore_phaseinjector1_command_issue_re <= interface2_bank_bus_we;
- end
+ litedramcore_phaseinjector1_command_issue_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd8))) begin
+ litedramcore_phaseinjector1_command_issue_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi1_address0_r = interface2_bank_bus_dat_w[13:0];
always @(*) begin
- csrbank2_dfii_pi1_address0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
- csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi1_address0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
+ csrbank2_dfii_pi1_address0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi1_address0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
- csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi1_address0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd9))) begin
+ csrbank2_dfii_pi1_address0_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi1_baddress0_r = interface2_bank_bus_dat_w[2:0];
always @(*) begin
- csrbank2_dfii_pi1_baddress0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
- csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi1_baddress0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
+ csrbank2_dfii_pi1_baddress0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi1_baddress0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
- csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi1_baddress0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd10))) begin
+ csrbank2_dfii_pi1_baddress0_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi1_wrdata0_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
- csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi1_wrdata0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
+ csrbank2_dfii_pi1_wrdata0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
- csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi1_wrdata0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd11))) begin
+ csrbank2_dfii_pi1_wrdata0_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi1_rddata_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi1_rddata_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
- csrbank2_dfii_pi1_rddata_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi1_rddata_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
+ csrbank2_dfii_pi1_rddata_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi1_rddata_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
- csrbank2_dfii_pi1_rddata_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi1_rddata_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd12))) begin
+ csrbank2_dfii_pi1_rddata_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi2_command0_r = interface2_bank_bus_dat_w[5:0];
always @(*) begin
- csrbank2_dfii_pi2_command0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
- csrbank2_dfii_pi2_command0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi2_command0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
+ csrbank2_dfii_pi2_command0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi2_command0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
- csrbank2_dfii_pi2_command0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi2_command0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd13))) begin
+ csrbank2_dfii_pi2_command0_re <= interface2_bank_bus_we;
+ end
end
assign litedramcore_phaseinjector2_command_issue_r = interface2_bank_bus_dat_w[0];
always @(*) begin
- litedramcore_phaseinjector2_command_issue_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
- litedramcore_phaseinjector2_command_issue_we <= (~interface2_bank_bus_we);
- end
+ litedramcore_phaseinjector2_command_issue_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
+ litedramcore_phaseinjector2_command_issue_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- litedramcore_phaseinjector2_command_issue_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
- litedramcore_phaseinjector2_command_issue_re <= interface2_bank_bus_we;
- end
+ litedramcore_phaseinjector2_command_issue_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd14))) begin
+ litedramcore_phaseinjector2_command_issue_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi2_address0_r = interface2_bank_bus_dat_w[13:0];
always @(*) begin
- csrbank2_dfii_pi2_address0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
- csrbank2_dfii_pi2_address0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi2_address0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
+ csrbank2_dfii_pi2_address0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi2_address0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
- csrbank2_dfii_pi2_address0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi2_address0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 4'd15))) begin
+ csrbank2_dfii_pi2_address0_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi2_baddress0_r = interface2_bank_bus_dat_w[2:0];
always @(*) begin
- csrbank2_dfii_pi2_baddress0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
- csrbank2_dfii_pi2_baddress0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi2_baddress0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
+ csrbank2_dfii_pi2_baddress0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi2_baddress0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
- csrbank2_dfii_pi2_baddress0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi2_baddress0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd16))) begin
+ csrbank2_dfii_pi2_baddress0_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi2_wrdata0_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
- csrbank2_dfii_pi2_wrdata0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi2_wrdata0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
+ csrbank2_dfii_pi2_wrdata0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
- csrbank2_dfii_pi2_wrdata0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi2_wrdata0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd17))) begin
+ csrbank2_dfii_pi2_wrdata0_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi2_rddata_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi2_rddata_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
- csrbank2_dfii_pi2_rddata_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi2_rddata_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
+ csrbank2_dfii_pi2_rddata_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi2_rddata_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
- csrbank2_dfii_pi2_rddata_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi2_rddata_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd18))) begin
+ csrbank2_dfii_pi2_rddata_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi3_command0_r = interface2_bank_bus_dat_w[5:0];
always @(*) begin
- csrbank2_dfii_pi3_command0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin
- csrbank2_dfii_pi3_command0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi3_command0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin
+ csrbank2_dfii_pi3_command0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi3_command0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin
- csrbank2_dfii_pi3_command0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi3_command0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd19))) begin
+ csrbank2_dfii_pi3_command0_we <= (~interface2_bank_bus_we);
+ end
end
assign litedramcore_phaseinjector3_command_issue_r = interface2_bank_bus_dat_w[0];
always @(*) begin
- litedramcore_phaseinjector3_command_issue_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin
- litedramcore_phaseinjector3_command_issue_re <= interface2_bank_bus_we;
- end
+ litedramcore_phaseinjector3_command_issue_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin
+ litedramcore_phaseinjector3_command_issue_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- litedramcore_phaseinjector3_command_issue_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin
- litedramcore_phaseinjector3_command_issue_we <= (~interface2_bank_bus_we);
- end
+ litedramcore_phaseinjector3_command_issue_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd20))) begin
+ litedramcore_phaseinjector3_command_issue_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi3_address0_r = interface2_bank_bus_dat_w[13:0];
always @(*) begin
- csrbank2_dfii_pi3_address0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin
- csrbank2_dfii_pi3_address0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi3_address0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin
+ csrbank2_dfii_pi3_address0_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi3_address0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin
- csrbank2_dfii_pi3_address0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi3_address0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd21))) begin
+ csrbank2_dfii_pi3_address0_re <= interface2_bank_bus_we;
+ end
end
assign csrbank2_dfii_pi3_baddress0_r = interface2_bank_bus_dat_w[2:0];
always @(*) begin
- csrbank2_dfii_pi3_baddress0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin
- csrbank2_dfii_pi3_baddress0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi3_baddress0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin
+ csrbank2_dfii_pi3_baddress0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi3_baddress0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin
- csrbank2_dfii_pi3_baddress0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi3_baddress0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd22))) begin
+ csrbank2_dfii_pi3_baddress0_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi3_wrdata0_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi3_wrdata0_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin
- csrbank2_dfii_pi3_wrdata0_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi3_wrdata0_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin
+ csrbank2_dfii_pi3_wrdata0_re <= interface2_bank_bus_we;
+ end
end
always @(*) begin
- csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin
- csrbank2_dfii_pi3_wrdata0_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi3_wrdata0_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd23))) begin
+ csrbank2_dfii_pi3_wrdata0_we <= (~interface2_bank_bus_we);
+ end
end
assign csrbank2_dfii_pi3_rddata_r = interface2_bank_bus_dat_w[31:0];
always @(*) begin
- csrbank2_dfii_pi3_rddata_we <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin
- csrbank2_dfii_pi3_rddata_we <= (~interface2_bank_bus_we);
- end
+ csrbank2_dfii_pi3_rddata_we <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin
+ csrbank2_dfii_pi3_rddata_we <= (~interface2_bank_bus_we);
+ end
end
always @(*) begin
- csrbank2_dfii_pi3_rddata_re <= 1'd0;
- if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin
- csrbank2_dfii_pi3_rddata_re <= interface2_bank_bus_we;
- end
+ csrbank2_dfii_pi3_rddata_re <= 1'd0;
+ if ((csrbank2_sel & (interface2_bank_bus_adr[8:0] == 5'd24))) begin
+ csrbank2_dfii_pi3_rddata_re <= interface2_bank_bus_we;
+ end
end
assign litedramcore_sel = litedramcore_storage[0];
assign litedramcore_cke = litedramcore_storage[1];
assign interface2_bank_bus_dat_w = csr_interconnect_dat_w;
assign csr_interconnect_dat_r = ((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r);
always @(*) begin
- rhs_array_muxed0 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0];
- end
- 1'd1: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1];
- end
- 2'd2: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2];
- end
- 2'd3: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3];
- end
- 3'd4: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4];
- end
- 3'd5: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5];
- end
- 3'd6: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6];
- end
- default: begin
- rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7];
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed1 <= 14'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a;
- end
- 1'd1: begin
- rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a;
- end
- 2'd2: begin
- rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a;
- end
- 2'd3: begin
- rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a;
- end
- 3'd4: begin
- rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a;
- end
- 3'd5: begin
- rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a;
- end
- 3'd6: begin
- rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a;
- end
- default: begin
- rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed2 <= 3'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba;
- end
- 1'd1: begin
- rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba;
- end
- 2'd2: begin
- rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba;
- end
- 2'd3: begin
- rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba;
- end
- 3'd4: begin
- rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba;
- end
- 3'd5: begin
- rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba;
- end
- 3'd6: begin
- rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba;
- end
- default: begin
- rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed3 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read;
- end
- 1'd1: begin
- rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read;
- end
- 2'd2: begin
- rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read;
- end
- 2'd3: begin
- rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read;
- end
- 3'd4: begin
- rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read;
- end
- 3'd5: begin
- rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read;
- end
- 3'd6: begin
- rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read;
- end
- default: begin
- rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed4 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write;
- end
- 1'd1: begin
- rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write;
- end
- 2'd2: begin
- rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write;
- end
- 2'd3: begin
- rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write;
- end
- 3'd4: begin
- rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write;
- end
- 3'd5: begin
- rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write;
- end
- 3'd6: begin
- rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write;
- end
- default: begin
- rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed5 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
- end
- 1'd1: begin
- rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
- end
- 2'd2: begin
- rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
- end
- 2'd3: begin
- rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
- end
- 3'd4: begin
- rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
- end
- 3'd5: begin
- rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
- end
- 3'd6: begin
- rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
- end
- default: begin
- rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
- end
- endcase
-end
-always @(*) begin
- t_array_muxed0 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas;
- end
- 1'd1: begin
- t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas;
- end
- 2'd2: begin
- t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas;
- end
- 2'd3: begin
- t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas;
- end
- 3'd4: begin
- t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas;
- end
- 3'd5: begin
- t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas;
- end
- 3'd6: begin
- t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas;
- end
- default: begin
- t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas;
- end
- endcase
-end
-always @(*) begin
- t_array_muxed1 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras;
- end
- 1'd1: begin
- t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras;
- end
- 2'd2: begin
- t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras;
- end
- 2'd3: begin
- t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras;
- end
- 3'd4: begin
- t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras;
- end
- 3'd5: begin
- t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras;
- end
- 3'd6: begin
- t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras;
- end
- default: begin
- t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras;
- end
- endcase
-end
-always @(*) begin
- t_array_muxed2 <= 1'd0;
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we;
- end
- 1'd1: begin
- t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we;
- end
- 2'd2: begin
- t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we;
- end
- 2'd3: begin
- t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we;
- end
- 3'd4: begin
- t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we;
- end
- 3'd5: begin
- t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we;
- end
- 3'd6: begin
- t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we;
- end
- default: begin
- t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed6 <= 1'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[0];
- end
- 1'd1: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[1];
- end
- 2'd2: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[2];
- end
- 2'd3: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[3];
- end
- 3'd4: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[4];
- end
- 3'd5: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[5];
- end
- 3'd6: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[6];
- end
- default: begin
- rhs_array_muxed6 <= litedramcore_choose_req_valids[7];
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed7 <= 14'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a;
- end
- 1'd1: begin
- rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a;
- end
- 2'd2: begin
- rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a;
- end
- 2'd3: begin
- rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a;
- end
- 3'd4: begin
- rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a;
- end
- 3'd5: begin
- rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a;
- end
- 3'd6: begin
- rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a;
- end
- default: begin
- rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed8 <= 3'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba;
- end
- 1'd1: begin
- rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba;
- end
- 2'd2: begin
- rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba;
- end
- 2'd3: begin
- rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba;
- end
- 3'd4: begin
- rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba;
- end
- 3'd5: begin
- rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba;
- end
- 3'd6: begin
- rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba;
- end
- default: begin
- rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed9 <= 1'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read;
- end
- 1'd1: begin
- rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read;
- end
- 2'd2: begin
- rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read;
- end
- 2'd3: begin
- rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read;
- end
- 3'd4: begin
- rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read;
- end
- 3'd5: begin
- rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read;
- end
- 3'd6: begin
- rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read;
- end
- default: begin
- rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed10 <= 1'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write;
- end
- 1'd1: begin
- rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write;
- end
- 2'd2: begin
- rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write;
- end
- 2'd3: begin
- rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write;
- end
- 3'd4: begin
- rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write;
- end
- 3'd5: begin
- rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write;
- end
- 3'd6: begin
- rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write;
- end
- default: begin
- rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed11 <= 1'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
- end
- 1'd1: begin
- rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
- end
- 2'd2: begin
- rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
- end
- 2'd3: begin
- rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
- end
- 3'd4: begin
- rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
- end
- 3'd5: begin
- rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
- end
- 3'd6: begin
- rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
- end
- default: begin
- rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
- end
- endcase
-end
-always @(*) begin
- t_array_muxed3 <= 1'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas;
- end
- 1'd1: begin
- t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas;
- end
- 2'd2: begin
- t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas;
- end
- 2'd3: begin
- t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas;
- end
- 3'd4: begin
- t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas;
- end
- 3'd5: begin
- t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas;
- end
- 3'd6: begin
- t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas;
- end
- default: begin
- t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas;
- end
- endcase
-end
-always @(*) begin
- t_array_muxed4 <= 1'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras;
- end
- 1'd1: begin
- t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras;
- end
- 2'd2: begin
- t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras;
- end
- 2'd3: begin
- t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras;
- end
- 3'd4: begin
- t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras;
- end
- 3'd5: begin
- t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras;
- end
- 3'd6: begin
- t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras;
- end
- default: begin
- t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras;
- end
- endcase
-end
-always @(*) begin
- t_array_muxed5 <= 1'd0;
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we;
- end
- 1'd1: begin
- t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we;
- end
- 2'd2: begin
- t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we;
- end
- 2'd3: begin
- t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we;
- end
- 3'd4: begin
- t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we;
- end
- 3'd5: begin
- t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we;
- end
- 3'd6: begin
- t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we;
- end
- default: begin
- t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed12 <= 21'd0;
- case (litedramcore_roundrobin0_grant)
- default: begin
- rhs_array_muxed12 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed13 <= 1'd0;
- case (litedramcore_roundrobin0_grant)
- default: begin
- rhs_array_muxed13 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed14 <= 1'd0;
- case (litedramcore_roundrobin0_grant)
- default: begin
- rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed15 <= 21'd0;
- case (litedramcore_roundrobin1_grant)
- default: begin
- rhs_array_muxed15 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed16 <= 1'd0;
- case (litedramcore_roundrobin1_grant)
- default: begin
- rhs_array_muxed16 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed17 <= 1'd0;
- case (litedramcore_roundrobin1_grant)
- default: begin
- rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed18 <= 21'd0;
- case (litedramcore_roundrobin2_grant)
- default: begin
- rhs_array_muxed18 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed19 <= 1'd0;
- case (litedramcore_roundrobin2_grant)
- default: begin
- rhs_array_muxed19 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed20 <= 1'd0;
- case (litedramcore_roundrobin2_grant)
- default: begin
- rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed21 <= 21'd0;
- case (litedramcore_roundrobin3_grant)
- default: begin
- rhs_array_muxed21 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed22 <= 1'd0;
- case (litedramcore_roundrobin3_grant)
- default: begin
- rhs_array_muxed22 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed23 <= 1'd0;
- case (litedramcore_roundrobin3_grant)
- default: begin
- rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
+ rhs_array_muxed0 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[0];
+ end
+ 1'd1: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[1];
+ end
+ 2'd2: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[2];
+ end
+ 2'd3: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[3];
+ end
+ 3'd4: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[4];
+ end
+ 3'd5: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[5];
+ end
+ 3'd6: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[6];
+ end
+ default: begin
+ rhs_array_muxed0 <= litedramcore_choose_cmd_valids[7];
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed1 <= 14'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_a;
+ end
+ 1'd1: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_a;
+ end
+ 2'd2: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_a;
+ end
+ 2'd3: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_a;
+ end
+ 3'd4: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_a;
+ end
+ 3'd5: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_a;
+ end
+ 3'd6: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_a;
+ end
+ default: begin
+ rhs_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed2 <= 3'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_ba;
+ end
+ 1'd1: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_ba;
+ end
+ 2'd2: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_ba;
+ end
+ 2'd3: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_ba;
+ end
+ 3'd4: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_ba;
+ end
+ 3'd5: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_ba;
+ end
+ 3'd6: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_ba;
+ end
+ default: begin
+ rhs_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_ba;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed3 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_is_read;
+ end
+ 1'd1: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_is_read;
+ end
+ 2'd2: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_is_read;
+ end
+ 2'd3: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_is_read;
+ end
+ 3'd4: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_is_read;
+ end
+ 3'd5: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_is_read;
+ end
+ 3'd6: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_is_read;
+ end
+ default: begin
+ rhs_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_is_read;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed4 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_is_write;
+ end
+ 1'd1: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_is_write;
+ end
+ 2'd2: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_is_write;
+ end
+ 2'd3: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_is_write;
+ end
+ 3'd4: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_is_write;
+ end
+ 3'd5: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_is_write;
+ end
+ 3'd6: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_is_write;
+ end
+ default: begin
+ rhs_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_is_write;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed5 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
+ end
+ 1'd1: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
+ end
+ 2'd2: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
+ end
+ 2'd3: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
+ end
+ 3'd4: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
+ end
+ 3'd5: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
+ end
+ 3'd6: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
+ end
+ default: begin
+ rhs_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed0 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ t_array_muxed0 <= litedramcore_bankmachine0_cmd_payload_cas;
+ end
+ 1'd1: begin
+ t_array_muxed0 <= litedramcore_bankmachine1_cmd_payload_cas;
+ end
+ 2'd2: begin
+ t_array_muxed0 <= litedramcore_bankmachine2_cmd_payload_cas;
+ end
+ 2'd3: begin
+ t_array_muxed0 <= litedramcore_bankmachine3_cmd_payload_cas;
+ end
+ 3'd4: begin
+ t_array_muxed0 <= litedramcore_bankmachine4_cmd_payload_cas;
+ end
+ 3'd5: begin
+ t_array_muxed0 <= litedramcore_bankmachine5_cmd_payload_cas;
+ end
+ 3'd6: begin
+ t_array_muxed0 <= litedramcore_bankmachine6_cmd_payload_cas;
+ end
+ default: begin
+ t_array_muxed0 <= litedramcore_bankmachine7_cmd_payload_cas;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed1 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ t_array_muxed1 <= litedramcore_bankmachine0_cmd_payload_ras;
+ end
+ 1'd1: begin
+ t_array_muxed1 <= litedramcore_bankmachine1_cmd_payload_ras;
+ end
+ 2'd2: begin
+ t_array_muxed1 <= litedramcore_bankmachine2_cmd_payload_ras;
+ end
+ 2'd3: begin
+ t_array_muxed1 <= litedramcore_bankmachine3_cmd_payload_ras;
+ end
+ 3'd4: begin
+ t_array_muxed1 <= litedramcore_bankmachine4_cmd_payload_ras;
+ end
+ 3'd5: begin
+ t_array_muxed1 <= litedramcore_bankmachine5_cmd_payload_ras;
+ end
+ 3'd6: begin
+ t_array_muxed1 <= litedramcore_bankmachine6_cmd_payload_ras;
+ end
+ default: begin
+ t_array_muxed1 <= litedramcore_bankmachine7_cmd_payload_ras;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed2 <= 1'd0;
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ t_array_muxed2 <= litedramcore_bankmachine0_cmd_payload_we;
+ end
+ 1'd1: begin
+ t_array_muxed2 <= litedramcore_bankmachine1_cmd_payload_we;
+ end
+ 2'd2: begin
+ t_array_muxed2 <= litedramcore_bankmachine2_cmd_payload_we;
+ end
+ 2'd3: begin
+ t_array_muxed2 <= litedramcore_bankmachine3_cmd_payload_we;
+ end
+ 3'd4: begin
+ t_array_muxed2 <= litedramcore_bankmachine4_cmd_payload_we;
+ end
+ 3'd5: begin
+ t_array_muxed2 <= litedramcore_bankmachine5_cmd_payload_we;
+ end
+ 3'd6: begin
+ t_array_muxed2 <= litedramcore_bankmachine6_cmd_payload_we;
+ end
+ default: begin
+ t_array_muxed2 <= litedramcore_bankmachine7_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed6 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[0];
+ end
+ 1'd1: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[1];
+ end
+ 2'd2: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[2];
+ end
+ 2'd3: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[3];
+ end
+ 3'd4: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[4];
+ end
+ 3'd5: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[5];
+ end
+ 3'd6: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[6];
+ end
+ default: begin
+ rhs_array_muxed6 <= litedramcore_choose_req_valids[7];
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed7 <= 14'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine0_cmd_payload_a;
+ end
+ 1'd1: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine1_cmd_payload_a;
+ end
+ 2'd2: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine2_cmd_payload_a;
+ end
+ 2'd3: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine3_cmd_payload_a;
+ end
+ 3'd4: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine4_cmd_payload_a;
+ end
+ 3'd5: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine5_cmd_payload_a;
+ end
+ 3'd6: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine6_cmd_payload_a;
+ end
+ default: begin
+ rhs_array_muxed7 <= litedramcore_bankmachine7_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed8 <= 3'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine0_cmd_payload_ba;
+ end
+ 1'd1: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine1_cmd_payload_ba;
+ end
+ 2'd2: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine2_cmd_payload_ba;
+ end
+ 2'd3: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine3_cmd_payload_ba;
+ end
+ 3'd4: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine4_cmd_payload_ba;
+ end
+ 3'd5: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine5_cmd_payload_ba;
+ end
+ 3'd6: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine6_cmd_payload_ba;
+ end
+ default: begin
+ rhs_array_muxed8 <= litedramcore_bankmachine7_cmd_payload_ba;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed9 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine0_cmd_payload_is_read;
+ end
+ 1'd1: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine1_cmd_payload_is_read;
+ end
+ 2'd2: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine2_cmd_payload_is_read;
+ end
+ 2'd3: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine3_cmd_payload_is_read;
+ end
+ 3'd4: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine4_cmd_payload_is_read;
+ end
+ 3'd5: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine5_cmd_payload_is_read;
+ end
+ 3'd6: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine6_cmd_payload_is_read;
+ end
+ default: begin
+ rhs_array_muxed9 <= litedramcore_bankmachine7_cmd_payload_is_read;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed10 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine0_cmd_payload_is_write;
+ end
+ 1'd1: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine1_cmd_payload_is_write;
+ end
+ 2'd2: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine2_cmd_payload_is_write;
+ end
+ 2'd3: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine3_cmd_payload_is_write;
+ end
+ 3'd4: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine4_cmd_payload_is_write;
+ end
+ 3'd5: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine5_cmd_payload_is_write;
+ end
+ 3'd6: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine6_cmd_payload_is_write;
+ end
+ default: begin
+ rhs_array_muxed10 <= litedramcore_bankmachine7_cmd_payload_is_write;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed11 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine0_cmd_payload_is_cmd;
+ end
+ 1'd1: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine1_cmd_payload_is_cmd;
+ end
+ 2'd2: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine2_cmd_payload_is_cmd;
+ end
+ 2'd3: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine3_cmd_payload_is_cmd;
+ end
+ 3'd4: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine4_cmd_payload_is_cmd;
+ end
+ 3'd5: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine5_cmd_payload_is_cmd;
+ end
+ 3'd6: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine6_cmd_payload_is_cmd;
+ end
+ default: begin
+ rhs_array_muxed11 <= litedramcore_bankmachine7_cmd_payload_is_cmd;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed3 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ t_array_muxed3 <= litedramcore_bankmachine0_cmd_payload_cas;
+ end
+ 1'd1: begin
+ t_array_muxed3 <= litedramcore_bankmachine1_cmd_payload_cas;
+ end
+ 2'd2: begin
+ t_array_muxed3 <= litedramcore_bankmachine2_cmd_payload_cas;
+ end
+ 2'd3: begin
+ t_array_muxed3 <= litedramcore_bankmachine3_cmd_payload_cas;
+ end
+ 3'd4: begin
+ t_array_muxed3 <= litedramcore_bankmachine4_cmd_payload_cas;
+ end
+ 3'd5: begin
+ t_array_muxed3 <= litedramcore_bankmachine5_cmd_payload_cas;
+ end
+ 3'd6: begin
+ t_array_muxed3 <= litedramcore_bankmachine6_cmd_payload_cas;
+ end
+ default: begin
+ t_array_muxed3 <= litedramcore_bankmachine7_cmd_payload_cas;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed4 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ t_array_muxed4 <= litedramcore_bankmachine0_cmd_payload_ras;
+ end
+ 1'd1: begin
+ t_array_muxed4 <= litedramcore_bankmachine1_cmd_payload_ras;
+ end
+ 2'd2: begin
+ t_array_muxed4 <= litedramcore_bankmachine2_cmd_payload_ras;
+ end
+ 2'd3: begin
+ t_array_muxed4 <= litedramcore_bankmachine3_cmd_payload_ras;
+ end
+ 3'd4: begin
+ t_array_muxed4 <= litedramcore_bankmachine4_cmd_payload_ras;
+ end
+ 3'd5: begin
+ t_array_muxed4 <= litedramcore_bankmachine5_cmd_payload_ras;
+ end
+ 3'd6: begin
+ t_array_muxed4 <= litedramcore_bankmachine6_cmd_payload_ras;
+ end
+ default: begin
+ t_array_muxed4 <= litedramcore_bankmachine7_cmd_payload_ras;
+ end
+ endcase
+end
+always @(*) begin
+ t_array_muxed5 <= 1'd0;
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ t_array_muxed5 <= litedramcore_bankmachine0_cmd_payload_we;
+ end
+ 1'd1: begin
+ t_array_muxed5 <= litedramcore_bankmachine1_cmd_payload_we;
+ end
+ 2'd2: begin
+ t_array_muxed5 <= litedramcore_bankmachine2_cmd_payload_we;
+ end
+ 2'd3: begin
+ t_array_muxed5 <= litedramcore_bankmachine3_cmd_payload_we;
+ end
+ 3'd4: begin
+ t_array_muxed5 <= litedramcore_bankmachine4_cmd_payload_we;
+ end
+ 3'd5: begin
+ t_array_muxed5 <= litedramcore_bankmachine5_cmd_payload_we;
+ end
+ 3'd6: begin
+ t_array_muxed5 <= litedramcore_bankmachine6_cmd_payload_we;
+ end
+ default: begin
+ t_array_muxed5 <= litedramcore_bankmachine7_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed12 <= 21'd0;
+ case (litedramcore_roundrobin0_grant)
+ default: begin
+ rhs_array_muxed12 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed13 <= 1'd0;
+ case (litedramcore_roundrobin0_grant)
+ default: begin
+ rhs_array_muxed13 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed14 <= 1'd0;
+ case (litedramcore_roundrobin0_grant)
+ default: begin
+ rhs_array_muxed14 <= (((user_port_cmd_payload_addr[9:7] == 1'd0) & (~(((((((litedramcore_locked0 | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed15 <= 21'd0;
+ case (litedramcore_roundrobin1_grant)
+ default: begin
+ rhs_array_muxed15 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed16 <= 1'd0;
+ case (litedramcore_roundrobin1_grant)
+ default: begin
+ rhs_array_muxed16 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed17 <= 1'd0;
+ case (litedramcore_roundrobin1_grant)
+ default: begin
+ rhs_array_muxed17 <= (((user_port_cmd_payload_addr[9:7] == 1'd1) & (~(((((((litedramcore_locked1 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed18 <= 21'd0;
+ case (litedramcore_roundrobin2_grant)
+ default: begin
+ rhs_array_muxed18 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed19 <= 1'd0;
+ case (litedramcore_roundrobin2_grant)
+ default: begin
+ rhs_array_muxed19 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed20 <= 1'd0;
+ case (litedramcore_roundrobin2_grant)
+ default: begin
+ rhs_array_muxed20 <= (((user_port_cmd_payload_addr[9:7] == 2'd2) & (~(((((((litedramcore_locked2 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed21 <= 21'd0;
+ case (litedramcore_roundrobin3_grant)
+ default: begin
+ rhs_array_muxed21 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed22 <= 1'd0;
+ case (litedramcore_roundrobin3_grant)
+ default: begin
+ rhs_array_muxed22 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed23 <= 1'd0;
+ case (litedramcore_roundrobin3_grant)
+ default: begin
+ rhs_array_muxed23 <= (((user_port_cmd_payload_addr[9:7] == 2'd3) & (~(((((((litedramcore_locked3 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
end
always @(*) begin
- rhs_array_muxed24 <= 21'd0;
- case (litedramcore_roundrobin4_grant)
- default: begin
- rhs_array_muxed24 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed25 <= 1'd0;
- case (litedramcore_roundrobin4_grant)
- default: begin
- rhs_array_muxed25 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed26 <= 1'd0;
- case (litedramcore_roundrobin4_grant)
- default: begin
- rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed27 <= 21'd0;
- case (litedramcore_roundrobin5_grant)
- default: begin
- rhs_array_muxed27 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed28 <= 1'd0;
- case (litedramcore_roundrobin5_grant)
- default: begin
- rhs_array_muxed28 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed29 <= 1'd0;
- case (litedramcore_roundrobin5_grant)
- default: begin
- rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed30 <= 21'd0;
- case (litedramcore_roundrobin6_grant)
- default: begin
- rhs_array_muxed30 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed31 <= 1'd0;
- case (litedramcore_roundrobin6_grant)
- default: begin
- rhs_array_muxed31 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed32 <= 1'd0;
- case (litedramcore_roundrobin6_grant)
- default: begin
- rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed33 <= 21'd0;
- case (litedramcore_roundrobin7_grant)
- default: begin
- rhs_array_muxed33 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed34 <= 1'd0;
- case (litedramcore_roundrobin7_grant)
- default: begin
- rhs_array_muxed34 <= user_port_cmd_payload_we;
- end
- endcase
-end
-always @(*) begin
- rhs_array_muxed35 <= 1'd0;
- case (litedramcore_roundrobin7_grant)
- default: begin
- rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid);
- end
- endcase
-end
-always @(*) begin
- array_muxed0 <= 3'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed0 <= litedramcore_nop_ba[2:0];
- end
- 1'd1: begin
- array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
- end
- 2'd2: begin
- array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0];
- end
- default: begin
- array_muxed0 <= litedramcore_cmd_payload_ba[2:0];
- end
- endcase
-end
-always @(*) begin
- array_muxed1 <= 14'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed1 <= litedramcore_nop_a;
- end
- 1'd1: begin
- array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a;
- end
- 2'd2: begin
- array_muxed1 <= litedramcore_choose_req_cmd_payload_a;
- end
- default: begin
- array_muxed1 <= litedramcore_cmd_payload_a;
- end
- endcase
-end
-always @(*) begin
- array_muxed2 <= 1'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed2 <= 1'd0;
- end
- 1'd1: begin
- array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
- end
- 2'd2: begin
- array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
- end
- default: begin
- array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
- end
- endcase
-end
-always @(*) begin
- array_muxed3 <= 1'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed3 <= 1'd0;
- end
- 1'd1: begin
- array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
- end
- 2'd2: begin
- array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
- end
- default: begin
- array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
- end
- endcase
-end
-always @(*) begin
- array_muxed4 <= 1'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed4 <= 1'd0;
- end
- 1'd1: begin
- array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
- end
- 2'd2: begin
- array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
- end
- default: begin
- array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
- end
- endcase
-end
-always @(*) begin
- array_muxed5 <= 1'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed5 <= 1'd0;
- end
- 1'd1: begin
- array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
- end
- 2'd2: begin
- array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
- end
- default: begin
- array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
- end
- endcase
-end
-always @(*) begin
- array_muxed6 <= 1'd0;
- case (litedramcore_steerer_sel0)
- 1'd0: begin
- array_muxed6 <= 1'd0;
- end
- 1'd1: begin
- array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
- end
- 2'd2: begin
- array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
- end
- default: begin
- array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
- end
- endcase
-end
-always @(*) begin
- array_muxed7 <= 3'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed7 <= litedramcore_nop_ba[2:0];
- end
- 1'd1: begin
- array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
- end
- 2'd2: begin
- array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0];
- end
- default: begin
- array_muxed7 <= litedramcore_cmd_payload_ba[2:0];
- end
- endcase
-end
-always @(*) begin
- array_muxed8 <= 14'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed8 <= litedramcore_nop_a;
- end
- 1'd1: begin
- array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a;
- end
- 2'd2: begin
- array_muxed8 <= litedramcore_choose_req_cmd_payload_a;
- end
- default: begin
- array_muxed8 <= litedramcore_cmd_payload_a;
- end
- endcase
-end
-always @(*) begin
- array_muxed9 <= 1'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed9 <= 1'd0;
- end
- 1'd1: begin
- array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
- end
- 2'd2: begin
- array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
- end
- default: begin
- array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
- end
- endcase
-end
-always @(*) begin
- array_muxed10 <= 1'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed10 <= 1'd0;
- end
- 1'd1: begin
- array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
- end
- 2'd2: begin
- array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
- end
- default: begin
- array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
- end
- endcase
-end
-always @(*) begin
- array_muxed11 <= 1'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed11 <= 1'd0;
- end
- 1'd1: begin
- array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
- end
- 2'd2: begin
- array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
- end
- default: begin
- array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
- end
- endcase
-end
-always @(*) begin
- array_muxed12 <= 1'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed12 <= 1'd0;
- end
- 1'd1: begin
- array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
- end
- 2'd2: begin
- array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
- end
- default: begin
- array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
- end
- endcase
-end
-always @(*) begin
- array_muxed13 <= 1'd0;
- case (litedramcore_steerer_sel1)
- 1'd0: begin
- array_muxed13 <= 1'd0;
- end
- 1'd1: begin
- array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
- end
- 2'd2: begin
- array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
- end
- default: begin
- array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
- end
- endcase
-end
-always @(*) begin
- array_muxed14 <= 3'd0;
- case (litedramcore_steerer_sel2)
- 1'd0: begin
- array_muxed14 <= litedramcore_nop_ba[2:0];
- end
- 1'd1: begin
- array_muxed14 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
- end
- 2'd2: begin
- array_muxed14 <= litedramcore_choose_req_cmd_payload_ba[2:0];
- end
- default: begin
- array_muxed14 <= litedramcore_cmd_payload_ba[2:0];
- end
- endcase
-end
-always @(*) begin
- array_muxed15 <= 14'd0;
- case (litedramcore_steerer_sel2)
- 1'd0: begin
- array_muxed15 <= litedramcore_nop_a;
- end
- 1'd1: begin
- array_muxed15 <= litedramcore_choose_cmd_cmd_payload_a;
- end
- 2'd2: begin
- array_muxed15 <= litedramcore_choose_req_cmd_payload_a;
- end
- default: begin
- array_muxed15 <= litedramcore_cmd_payload_a;
- end
- endcase
-end
-always @(*) begin
- array_muxed16 <= 1'd0;
- case (litedramcore_steerer_sel2)
- 1'd0: begin
- array_muxed16 <= 1'd0;
- end
- 1'd1: begin
- array_muxed16 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
- end
- 2'd2: begin
- array_muxed16 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
- end
- default: begin
- array_muxed16 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
- end
- endcase
-end
-always @(*) begin
- array_muxed17 <= 1'd0;
- case (litedramcore_steerer_sel2)
- 1'd0: begin
- array_muxed17 <= 1'd0;
- end
- 1'd1: begin
- array_muxed17 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
- end
- 2'd2: begin
- array_muxed17 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
- end
- default: begin
- array_muxed17 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
- end
- endcase
-end
-always @(*) begin
- array_muxed18 <= 1'd0;
- case (litedramcore_steerer_sel2)
- 1'd0: begin
- array_muxed18 <= 1'd0;
- end
- 1'd1: begin
- array_muxed18 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
- end
- 2'd2: begin
- array_muxed18 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
- end
- default: begin
- array_muxed18 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
- end
- endcase
-end
-always @(*) begin
- array_muxed19 <= 1'd0;
- case (litedramcore_steerer_sel2)
- 1'd0: begin
- array_muxed19 <= 1'd0;
- end
- 1'd1: begin
- array_muxed19 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
- end
- 2'd2: begin
- array_muxed19 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
- end
- default: begin
- array_muxed19 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
- end
- endcase
-end
-always @(*) begin
- array_muxed20 <= 1'd0;
- case (litedramcore_steerer_sel2)
- 1'd0: begin
- array_muxed20 <= 1'd0;
- end
- 1'd1: begin
- array_muxed20 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
- end
- 2'd2: begin
- array_muxed20 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
- end
- default: begin
- array_muxed20 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
- end
- endcase
-end
-always @(*) begin
- array_muxed21 <= 3'd0;
- case (litedramcore_steerer_sel3)
- 1'd0: begin
- array_muxed21 <= litedramcore_nop_ba[2:0];
- end
- 1'd1: begin
- array_muxed21 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
- end
- 2'd2: begin
- array_muxed21 <= litedramcore_choose_req_cmd_payload_ba[2:0];
- end
- default: begin
- array_muxed21 <= litedramcore_cmd_payload_ba[2:0];
- end
- endcase
-end
-always @(*) begin
- array_muxed22 <= 14'd0;
- case (litedramcore_steerer_sel3)
- 1'd0: begin
- array_muxed22 <= litedramcore_nop_a;
- end
- 1'd1: begin
- array_muxed22 <= litedramcore_choose_cmd_cmd_payload_a;
- end
- 2'd2: begin
- array_muxed22 <= litedramcore_choose_req_cmd_payload_a;
- end
- default: begin
- array_muxed22 <= litedramcore_cmd_payload_a;
- end
- endcase
-end
-always @(*) begin
- array_muxed23 <= 1'd0;
- case (litedramcore_steerer_sel3)
- 1'd0: begin
- array_muxed23 <= 1'd0;
- end
- 1'd1: begin
- array_muxed23 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
- end
- 2'd2: begin
- array_muxed23 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
- end
- default: begin
- array_muxed23 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
- end
- endcase
-end
-always @(*) begin
- array_muxed24 <= 1'd0;
- case (litedramcore_steerer_sel3)
- 1'd0: begin
- array_muxed24 <= 1'd0;
- end
- 1'd1: begin
- array_muxed24 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
- end
- 2'd2: begin
- array_muxed24 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
- end
- default: begin
- array_muxed24 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
- end
- endcase
-end
-always @(*) begin
- array_muxed25 <= 1'd0;
- case (litedramcore_steerer_sel3)
- 1'd0: begin
- array_muxed25 <= 1'd0;
- end
- 1'd1: begin
- array_muxed25 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
- end
- 2'd2: begin
- array_muxed25 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
- end
- default: begin
- array_muxed25 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
- end
- endcase
-end
-always @(*) begin
- array_muxed26 <= 1'd0;
- case (litedramcore_steerer_sel3)
- 1'd0: begin
- array_muxed26 <= 1'd0;
- end
- 1'd1: begin
- array_muxed26 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
- end
- 2'd2: begin
- array_muxed26 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
- end
- default: begin
- array_muxed26 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
- end
- endcase
-end
-always @(*) begin
- array_muxed27 <= 1'd0;
- case (litedramcore_steerer_sel3)
- 1'd0: begin
- array_muxed27 <= 1'd0;
- end
- 1'd1: begin
- array_muxed27 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
- end
- 2'd2: begin
- array_muxed27 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
- end
- default: begin
- array_muxed27 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
- end
- endcase
+ rhs_array_muxed24 <= 21'd0;
+ case (litedramcore_roundrobin4_grant)
+ default: begin
+ rhs_array_muxed24 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed25 <= 1'd0;
+ case (litedramcore_roundrobin4_grant)
+ default: begin
+ rhs_array_muxed25 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed26 <= 1'd0;
+ case (litedramcore_roundrobin4_grant)
+ default: begin
+ rhs_array_muxed26 <= (((user_port_cmd_payload_addr[9:7] == 3'd4) & (~(((((((litedramcore_locked4 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed27 <= 21'd0;
+ case (litedramcore_roundrobin5_grant)
+ default: begin
+ rhs_array_muxed27 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed28 <= 1'd0;
+ case (litedramcore_roundrobin5_grant)
+ default: begin
+ rhs_array_muxed28 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed29 <= 1'd0;
+ case (litedramcore_roundrobin5_grant)
+ default: begin
+ rhs_array_muxed29 <= (((user_port_cmd_payload_addr[9:7] == 3'd5) & (~(((((((litedramcore_locked5 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed30 <= 21'd0;
+ case (litedramcore_roundrobin6_grant)
+ default: begin
+ rhs_array_muxed30 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed31 <= 1'd0;
+ case (litedramcore_roundrobin6_grant)
+ default: begin
+ rhs_array_muxed31 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed32 <= 1'd0;
+ case (litedramcore_roundrobin6_grant)
+ default: begin
+ rhs_array_muxed32 <= (((user_port_cmd_payload_addr[9:7] == 3'd6) & (~(((((((litedramcore_locked6 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank7_lock & (litedramcore_roundrobin7_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed33 <= 21'd0;
+ case (litedramcore_roundrobin7_grant)
+ default: begin
+ rhs_array_muxed33 <= {user_port_cmd_payload_addr[23:10], user_port_cmd_payload_addr[6:0]};
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed34 <= 1'd0;
+ case (litedramcore_roundrobin7_grant)
+ default: begin
+ rhs_array_muxed34 <= user_port_cmd_payload_we;
+ end
+ endcase
+end
+always @(*) begin
+ rhs_array_muxed35 <= 1'd0;
+ case (litedramcore_roundrobin7_grant)
+ default: begin
+ rhs_array_muxed35 <= (((user_port_cmd_payload_addr[9:7] == 3'd7) & (~(((((((litedramcore_locked7 | (litedramcore_interface_bank0_lock & (litedramcore_roundrobin0_grant == 1'd0))) | (litedramcore_interface_bank1_lock & (litedramcore_roundrobin1_grant == 1'd0))) | (litedramcore_interface_bank2_lock & (litedramcore_roundrobin2_grant == 1'd0))) | (litedramcore_interface_bank3_lock & (litedramcore_roundrobin3_grant == 1'd0))) | (litedramcore_interface_bank4_lock & (litedramcore_roundrobin4_grant == 1'd0))) | (litedramcore_interface_bank5_lock & (litedramcore_roundrobin5_grant == 1'd0))) | (litedramcore_interface_bank6_lock & (litedramcore_roundrobin6_grant == 1'd0))))) & user_port_cmd_valid);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed0 <= 3'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed0 <= litedramcore_nop_ba[2:0];
+ end
+ 1'd1: begin
+ array_muxed0 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+ end
+ 2'd2: begin
+ array_muxed0 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+ end
+ default: begin
+ array_muxed0 <= litedramcore_cmd_payload_ba[2:0];
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed1 <= 14'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed1 <= litedramcore_nop_a;
+ end
+ 1'd1: begin
+ array_muxed1 <= litedramcore_choose_cmd_cmd_payload_a;
+ end
+ 2'd2: begin
+ array_muxed1 <= litedramcore_choose_req_cmd_payload_a;
+ end
+ default: begin
+ array_muxed1 <= litedramcore_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed2 <= 1'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed2 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed2 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+ end
+ 2'd2: begin
+ array_muxed2 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+ end
+ default: begin
+ array_muxed2 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed3 <= 1'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed3 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed3 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+ end
+ 2'd2: begin
+ array_muxed3 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+ end
+ default: begin
+ array_muxed3 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed4 <= 1'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed4 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed4 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+ end
+ 2'd2: begin
+ array_muxed4 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+ end
+ default: begin
+ array_muxed4 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed5 <= 1'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed5 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed5 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+ end
+ 2'd2: begin
+ array_muxed5 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+ end
+ default: begin
+ array_muxed5 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed6 <= 1'd0;
+ case (litedramcore_steerer_sel0)
+ 1'd0: begin
+ array_muxed6 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed6 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+ end
+ 2'd2: begin
+ array_muxed6 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+ end
+ default: begin
+ array_muxed6 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed7 <= 3'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed7 <= litedramcore_nop_ba[2:0];
+ end
+ 1'd1: begin
+ array_muxed7 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+ end
+ 2'd2: begin
+ array_muxed7 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+ end
+ default: begin
+ array_muxed7 <= litedramcore_cmd_payload_ba[2:0];
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed8 <= 14'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed8 <= litedramcore_nop_a;
+ end
+ 1'd1: begin
+ array_muxed8 <= litedramcore_choose_cmd_cmd_payload_a;
+ end
+ 2'd2: begin
+ array_muxed8 <= litedramcore_choose_req_cmd_payload_a;
+ end
+ default: begin
+ array_muxed8 <= litedramcore_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed9 <= 1'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed9 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed9 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+ end
+ 2'd2: begin
+ array_muxed9 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+ end
+ default: begin
+ array_muxed9 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed10 <= 1'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed10 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed10 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+ end
+ 2'd2: begin
+ array_muxed10 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+ end
+ default: begin
+ array_muxed10 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed11 <= 1'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed11 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed11 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+ end
+ 2'd2: begin
+ array_muxed11 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+ end
+ default: begin
+ array_muxed11 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed12 <= 1'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed12 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed12 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+ end
+ 2'd2: begin
+ array_muxed12 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+ end
+ default: begin
+ array_muxed12 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed13 <= 1'd0;
+ case (litedramcore_steerer_sel1)
+ 1'd0: begin
+ array_muxed13 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed13 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+ end
+ 2'd2: begin
+ array_muxed13 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+ end
+ default: begin
+ array_muxed13 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed14 <= 3'd0;
+ case (litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed14 <= litedramcore_nop_ba[2:0];
+ end
+ 1'd1: begin
+ array_muxed14 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+ end
+ 2'd2: begin
+ array_muxed14 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+ end
+ default: begin
+ array_muxed14 <= litedramcore_cmd_payload_ba[2:0];
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed15 <= 14'd0;
+ case (litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed15 <= litedramcore_nop_a;
+ end
+ 1'd1: begin
+ array_muxed15 <= litedramcore_choose_cmd_cmd_payload_a;
+ end
+ 2'd2: begin
+ array_muxed15 <= litedramcore_choose_req_cmd_payload_a;
+ end
+ default: begin
+ array_muxed15 <= litedramcore_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed16 <= 1'd0;
+ case (litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed16 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed16 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+ end
+ 2'd2: begin
+ array_muxed16 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+ end
+ default: begin
+ array_muxed16 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed17 <= 1'd0;
+ case (litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed17 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed17 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+ end
+ 2'd2: begin
+ array_muxed17 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+ end
+ default: begin
+ array_muxed17 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed18 <= 1'd0;
+ case (litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed18 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed18 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+ end
+ 2'd2: begin
+ array_muxed18 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+ end
+ default: begin
+ array_muxed18 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed19 <= 1'd0;
+ case (litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed19 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed19 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+ end
+ 2'd2: begin
+ array_muxed19 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+ end
+ default: begin
+ array_muxed19 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed20 <= 1'd0;
+ case (litedramcore_steerer_sel2)
+ 1'd0: begin
+ array_muxed20 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed20 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+ end
+ 2'd2: begin
+ array_muxed20 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+ end
+ default: begin
+ array_muxed20 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed21 <= 3'd0;
+ case (litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed21 <= litedramcore_nop_ba[2:0];
+ end
+ 1'd1: begin
+ array_muxed21 <= litedramcore_choose_cmd_cmd_payload_ba[2:0];
+ end
+ 2'd2: begin
+ array_muxed21 <= litedramcore_choose_req_cmd_payload_ba[2:0];
+ end
+ default: begin
+ array_muxed21 <= litedramcore_cmd_payload_ba[2:0];
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed22 <= 14'd0;
+ case (litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed22 <= litedramcore_nop_a;
+ end
+ 1'd1: begin
+ array_muxed22 <= litedramcore_choose_cmd_cmd_payload_a;
+ end
+ 2'd2: begin
+ array_muxed22 <= litedramcore_choose_req_cmd_payload_a;
+ end
+ default: begin
+ array_muxed22 <= litedramcore_cmd_payload_a;
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed23 <= 1'd0;
+ case (litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed23 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed23 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_cas);
+ end
+ 2'd2: begin
+ array_muxed23 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_cas);
+ end
+ default: begin
+ array_muxed23 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_cas);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed24 <= 1'd0;
+ case (litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed24 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed24 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_ras);
+ end
+ 2'd2: begin
+ array_muxed24 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_ras);
+ end
+ default: begin
+ array_muxed24 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_ras);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed25 <= 1'd0;
+ case (litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed25 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed25 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_we);
+ end
+ 2'd2: begin
+ array_muxed25 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_we);
+ end
+ default: begin
+ array_muxed25 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_we);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed26 <= 1'd0;
+ case (litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed26 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed26 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_read);
+ end
+ 2'd2: begin
+ array_muxed26 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_read);
+ end
+ default: begin
+ array_muxed26 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_read);
+ end
+ endcase
+end
+always @(*) begin
+ array_muxed27 <= 1'd0;
+ case (litedramcore_steerer_sel3)
+ 1'd0: begin
+ array_muxed27 <= 1'd0;
+ end
+ 1'd1: begin
+ array_muxed27 <= ((litedramcore_choose_cmd_cmd_valid & litedramcore_choose_cmd_cmd_ready) & litedramcore_choose_cmd_cmd_payload_is_write);
+ end
+ 2'd2: begin
+ array_muxed27 <= ((litedramcore_choose_req_cmd_valid & litedramcore_choose_req_cmd_ready) & litedramcore_choose_req_cmd_payload_is_write);
+ end
+ default: begin
+ array_muxed27 <= ((litedramcore_cmd_valid & litedramcore_cmd_ready) & litedramcore_cmd_payload_is_write);
+ end
+ endcase
end
assign xilinxasyncresetsynchronizerimpl0 = (~locked);
assign xilinxasyncresetsynchronizerimpl1 = (~locked);
//------------------------------------------------------------------------------
always @(posedge iodelay_clk) begin
- if ((reset_counter != 1'd0)) begin
- reset_counter <= (reset_counter - 1'd1);
- end else begin
- ic_reset <= 1'd0;
- end
- if (iodelay_rst) begin
- reset_counter <= 4'd15;
- ic_reset <= 1'd1;
- end
+ if ((reset_counter != 1'd0)) begin
+ reset_counter <= (reset_counter - 1'd1);
+ end else begin
+ ic_reset <= 1'd0;
+ end
+ if (iodelay_rst) begin
+ reset_counter <= 4'd15;
+ ic_reset <= 1'd1;
+ end
end
always @(posedge sys_clk) begin
- a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dqs_oe_delay_tappeddelayline;
- a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0;
- a7ddrphy_dqspattern_o1 <= a7ddrphy_dqspattern_o0;
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip0_value0 <= (a7ddrphy_bitslip0_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip0_value0 <= 3'd7;
- end
- a7ddrphy_bitslip0_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip0_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip1_value0 <= (a7ddrphy_bitslip1_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip1_value0 <= 3'd7;
- end
- a7ddrphy_bitslip1_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip1_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip0_value1 <= (a7ddrphy_bitslip0_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip0_value1 <= 3'd7;
- end
- a7ddrphy_bitslip0_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[2], a7ddrphy_dfi_p3_wrdata_mask[0], a7ddrphy_dfi_p2_wrdata_mask[2], a7ddrphy_dfi_p2_wrdata_mask[0], a7ddrphy_dfi_p1_wrdata_mask[2], a7ddrphy_dfi_p1_wrdata_mask[0], a7ddrphy_dfi_p0_wrdata_mask[2], a7ddrphy_dfi_p0_wrdata_mask[0]}, a7ddrphy_bitslip0_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip1_value1 <= (a7ddrphy_bitslip1_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip1_value1 <= 3'd7;
- end
- a7ddrphy_bitslip1_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[3], a7ddrphy_dfi_p3_wrdata_mask[1], a7ddrphy_dfi_p2_wrdata_mask[3], a7ddrphy_dfi_p2_wrdata_mask[1], a7ddrphy_dfi_p1_wrdata_mask[3], a7ddrphy_dfi_p1_wrdata_mask[1], a7ddrphy_dfi_p0_wrdata_mask[3], a7ddrphy_dfi_p0_wrdata_mask[1]}, a7ddrphy_bitslip1_r1[15:8]};
- a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dq_oe_delay_tappeddelayline;
- a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0;
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip0_value2 <= (a7ddrphy_bitslip0_value2 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip0_value2 <= 3'd7;
- end
- a7ddrphy_bitslip0_r2 <= {{a7ddrphy_dfi_p3_wrdata[16], a7ddrphy_dfi_p3_wrdata[0], a7ddrphy_dfi_p2_wrdata[16], a7ddrphy_dfi_p2_wrdata[0], a7ddrphy_dfi_p1_wrdata[16], a7ddrphy_dfi_p1_wrdata[0], a7ddrphy_dfi_p0_wrdata[16], a7ddrphy_dfi_p0_wrdata[0]}, a7ddrphy_bitslip0_r2[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip0_value3 <= (a7ddrphy_bitslip0_value3 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip0_value3 <= 3'd7;
- end
- a7ddrphy_bitslip0_r3 <= {a7ddrphy_bitslip03, a7ddrphy_bitslip0_r3[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip1_value2 <= (a7ddrphy_bitslip1_value2 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip1_value2 <= 3'd7;
- end
- a7ddrphy_bitslip1_r2 <= {{a7ddrphy_dfi_p3_wrdata[17], a7ddrphy_dfi_p3_wrdata[1], a7ddrphy_dfi_p2_wrdata[17], a7ddrphy_dfi_p2_wrdata[1], a7ddrphy_dfi_p1_wrdata[17], a7ddrphy_dfi_p1_wrdata[1], a7ddrphy_dfi_p0_wrdata[17], a7ddrphy_dfi_p0_wrdata[1]}, a7ddrphy_bitslip1_r2[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip1_value3 <= (a7ddrphy_bitslip1_value3 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip1_value3 <= 3'd7;
- end
- a7ddrphy_bitslip1_r3 <= {a7ddrphy_bitslip13, a7ddrphy_bitslip1_r3[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip2_value0 <= (a7ddrphy_bitslip2_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip2_value0 <= 3'd7;
- end
- a7ddrphy_bitslip2_r0 <= {{a7ddrphy_dfi_p3_wrdata[18], a7ddrphy_dfi_p3_wrdata[2], a7ddrphy_dfi_p2_wrdata[18], a7ddrphy_dfi_p2_wrdata[2], a7ddrphy_dfi_p1_wrdata[18], a7ddrphy_dfi_p1_wrdata[2], a7ddrphy_dfi_p0_wrdata[18], a7ddrphy_dfi_p0_wrdata[2]}, a7ddrphy_bitslip2_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip2_value1 <= (a7ddrphy_bitslip2_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip2_value1 <= 3'd7;
- end
- a7ddrphy_bitslip2_r1 <= {a7ddrphy_bitslip21, a7ddrphy_bitslip2_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip3_value0 <= (a7ddrphy_bitslip3_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip3_value0 <= 3'd7;
- end
- a7ddrphy_bitslip3_r0 <= {{a7ddrphy_dfi_p3_wrdata[19], a7ddrphy_dfi_p3_wrdata[3], a7ddrphy_dfi_p2_wrdata[19], a7ddrphy_dfi_p2_wrdata[3], a7ddrphy_dfi_p1_wrdata[19], a7ddrphy_dfi_p1_wrdata[3], a7ddrphy_dfi_p0_wrdata[19], a7ddrphy_dfi_p0_wrdata[3]}, a7ddrphy_bitslip3_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip3_value1 <= (a7ddrphy_bitslip3_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip3_value1 <= 3'd7;
- end
- a7ddrphy_bitslip3_r1 <= {a7ddrphy_bitslip31, a7ddrphy_bitslip3_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip4_value0 <= (a7ddrphy_bitslip4_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip4_value0 <= 3'd7;
- end
- a7ddrphy_bitslip4_r0 <= {{a7ddrphy_dfi_p3_wrdata[20], a7ddrphy_dfi_p3_wrdata[4], a7ddrphy_dfi_p2_wrdata[20], a7ddrphy_dfi_p2_wrdata[4], a7ddrphy_dfi_p1_wrdata[20], a7ddrphy_dfi_p1_wrdata[4], a7ddrphy_dfi_p0_wrdata[20], a7ddrphy_dfi_p0_wrdata[4]}, a7ddrphy_bitslip4_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip4_value1 <= (a7ddrphy_bitslip4_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip4_value1 <= 3'd7;
- end
- a7ddrphy_bitslip4_r1 <= {a7ddrphy_bitslip41, a7ddrphy_bitslip4_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip5_value0 <= (a7ddrphy_bitslip5_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip5_value0 <= 3'd7;
- end
- a7ddrphy_bitslip5_r0 <= {{a7ddrphy_dfi_p3_wrdata[21], a7ddrphy_dfi_p3_wrdata[5], a7ddrphy_dfi_p2_wrdata[21], a7ddrphy_dfi_p2_wrdata[5], a7ddrphy_dfi_p1_wrdata[21], a7ddrphy_dfi_p1_wrdata[5], a7ddrphy_dfi_p0_wrdata[21], a7ddrphy_dfi_p0_wrdata[5]}, a7ddrphy_bitslip5_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip5_value1 <= (a7ddrphy_bitslip5_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip5_value1 <= 3'd7;
- end
- a7ddrphy_bitslip5_r1 <= {a7ddrphy_bitslip51, a7ddrphy_bitslip5_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip6_value0 <= (a7ddrphy_bitslip6_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip6_value0 <= 3'd7;
- end
- a7ddrphy_bitslip6_r0 <= {{a7ddrphy_dfi_p3_wrdata[22], a7ddrphy_dfi_p3_wrdata[6], a7ddrphy_dfi_p2_wrdata[22], a7ddrphy_dfi_p2_wrdata[6], a7ddrphy_dfi_p1_wrdata[22], a7ddrphy_dfi_p1_wrdata[6], a7ddrphy_dfi_p0_wrdata[22], a7ddrphy_dfi_p0_wrdata[6]}, a7ddrphy_bitslip6_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip6_value1 <= (a7ddrphy_bitslip6_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip6_value1 <= 3'd7;
- end
- a7ddrphy_bitslip6_r1 <= {a7ddrphy_bitslip61, a7ddrphy_bitslip6_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip7_value0 <= (a7ddrphy_bitslip7_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip7_value0 <= 3'd7;
- end
- a7ddrphy_bitslip7_r0 <= {{a7ddrphy_dfi_p3_wrdata[23], a7ddrphy_dfi_p3_wrdata[7], a7ddrphy_dfi_p2_wrdata[23], a7ddrphy_dfi_p2_wrdata[7], a7ddrphy_dfi_p1_wrdata[23], a7ddrphy_dfi_p1_wrdata[7], a7ddrphy_dfi_p0_wrdata[23], a7ddrphy_dfi_p0_wrdata[7]}, a7ddrphy_bitslip7_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip7_value1 <= (a7ddrphy_bitslip7_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip7_value1 <= 3'd7;
- end
- a7ddrphy_bitslip7_r1 <= {a7ddrphy_bitslip71, a7ddrphy_bitslip7_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip8_value0 <= (a7ddrphy_bitslip8_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip8_value0 <= 3'd7;
- end
- a7ddrphy_bitslip8_r0 <= {{a7ddrphy_dfi_p3_wrdata[24], a7ddrphy_dfi_p3_wrdata[8], a7ddrphy_dfi_p2_wrdata[24], a7ddrphy_dfi_p2_wrdata[8], a7ddrphy_dfi_p1_wrdata[24], a7ddrphy_dfi_p1_wrdata[8], a7ddrphy_dfi_p0_wrdata[24], a7ddrphy_dfi_p0_wrdata[8]}, a7ddrphy_bitslip8_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip8_value1 <= (a7ddrphy_bitslip8_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip8_value1 <= 3'd7;
- end
- a7ddrphy_bitslip8_r1 <= {a7ddrphy_bitslip81, a7ddrphy_bitslip8_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip9_value0 <= (a7ddrphy_bitslip9_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip9_value0 <= 3'd7;
- end
- a7ddrphy_bitslip9_r0 <= {{a7ddrphy_dfi_p3_wrdata[25], a7ddrphy_dfi_p3_wrdata[9], a7ddrphy_dfi_p2_wrdata[25], a7ddrphy_dfi_p2_wrdata[9], a7ddrphy_dfi_p1_wrdata[25], a7ddrphy_dfi_p1_wrdata[9], a7ddrphy_dfi_p0_wrdata[25], a7ddrphy_dfi_p0_wrdata[9]}, a7ddrphy_bitslip9_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip9_value1 <= (a7ddrphy_bitslip9_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip9_value1 <= 3'd7;
- end
- a7ddrphy_bitslip9_r1 <= {a7ddrphy_bitslip91, a7ddrphy_bitslip9_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip10_value0 <= (a7ddrphy_bitslip10_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip10_value0 <= 3'd7;
- end
- a7ddrphy_bitslip10_r0 <= {{a7ddrphy_dfi_p3_wrdata[26], a7ddrphy_dfi_p3_wrdata[10], a7ddrphy_dfi_p2_wrdata[26], a7ddrphy_dfi_p2_wrdata[10], a7ddrphy_dfi_p1_wrdata[26], a7ddrphy_dfi_p1_wrdata[10], a7ddrphy_dfi_p0_wrdata[26], a7ddrphy_dfi_p0_wrdata[10]}, a7ddrphy_bitslip10_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip10_value1 <= (a7ddrphy_bitslip10_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip10_value1 <= 3'd7;
- end
- a7ddrphy_bitslip10_r1 <= {a7ddrphy_bitslip101, a7ddrphy_bitslip10_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip11_value0 <= (a7ddrphy_bitslip11_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip11_value0 <= 3'd7;
- end
- a7ddrphy_bitslip11_r0 <= {{a7ddrphy_dfi_p3_wrdata[27], a7ddrphy_dfi_p3_wrdata[11], a7ddrphy_dfi_p2_wrdata[27], a7ddrphy_dfi_p2_wrdata[11], a7ddrphy_dfi_p1_wrdata[27], a7ddrphy_dfi_p1_wrdata[11], a7ddrphy_dfi_p0_wrdata[27], a7ddrphy_dfi_p0_wrdata[11]}, a7ddrphy_bitslip11_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip11_value1 <= (a7ddrphy_bitslip11_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip11_value1 <= 3'd7;
- end
- a7ddrphy_bitslip11_r1 <= {a7ddrphy_bitslip111, a7ddrphy_bitslip11_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip12_value0 <= (a7ddrphy_bitslip12_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip12_value0 <= 3'd7;
- end
- a7ddrphy_bitslip12_r0 <= {{a7ddrphy_dfi_p3_wrdata[28], a7ddrphy_dfi_p3_wrdata[12], a7ddrphy_dfi_p2_wrdata[28], a7ddrphy_dfi_p2_wrdata[12], a7ddrphy_dfi_p1_wrdata[28], a7ddrphy_dfi_p1_wrdata[12], a7ddrphy_dfi_p0_wrdata[28], a7ddrphy_dfi_p0_wrdata[12]}, a7ddrphy_bitslip12_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip12_value1 <= (a7ddrphy_bitslip12_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip12_value1 <= 3'd7;
- end
- a7ddrphy_bitslip12_r1 <= {a7ddrphy_bitslip121, a7ddrphy_bitslip12_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip13_value0 <= (a7ddrphy_bitslip13_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip13_value0 <= 3'd7;
- end
- a7ddrphy_bitslip13_r0 <= {{a7ddrphy_dfi_p3_wrdata[29], a7ddrphy_dfi_p3_wrdata[13], a7ddrphy_dfi_p2_wrdata[29], a7ddrphy_dfi_p2_wrdata[13], a7ddrphy_dfi_p1_wrdata[29], a7ddrphy_dfi_p1_wrdata[13], a7ddrphy_dfi_p0_wrdata[29], a7ddrphy_dfi_p0_wrdata[13]}, a7ddrphy_bitslip13_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip13_value1 <= (a7ddrphy_bitslip13_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip13_value1 <= 3'd7;
- end
- a7ddrphy_bitslip13_r1 <= {a7ddrphy_bitslip131, a7ddrphy_bitslip13_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip14_value0 <= (a7ddrphy_bitslip14_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip14_value0 <= 3'd7;
- end
- a7ddrphy_bitslip14_r0 <= {{a7ddrphy_dfi_p3_wrdata[30], a7ddrphy_dfi_p3_wrdata[14], a7ddrphy_dfi_p2_wrdata[30], a7ddrphy_dfi_p2_wrdata[14], a7ddrphy_dfi_p1_wrdata[30], a7ddrphy_dfi_p1_wrdata[14], a7ddrphy_dfi_p0_wrdata[30], a7ddrphy_dfi_p0_wrdata[14]}, a7ddrphy_bitslip14_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip14_value1 <= (a7ddrphy_bitslip14_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip14_value1 <= 3'd7;
- end
- a7ddrphy_bitslip14_r1 <= {a7ddrphy_bitslip141, a7ddrphy_bitslip14_r1[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip15_value0 <= (a7ddrphy_bitslip15_value0 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip15_value0 <= 3'd7;
- end
- a7ddrphy_bitslip15_r0 <= {{a7ddrphy_dfi_p3_wrdata[31], a7ddrphy_dfi_p3_wrdata[15], a7ddrphy_dfi_p2_wrdata[31], a7ddrphy_dfi_p2_wrdata[15], a7ddrphy_dfi_p1_wrdata[31], a7ddrphy_dfi_p1_wrdata[15], a7ddrphy_dfi_p0_wrdata[31], a7ddrphy_dfi_p0_wrdata[15]}, a7ddrphy_bitslip15_r0[15:8]};
- if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
- a7ddrphy_bitslip15_value1 <= (a7ddrphy_bitslip15_value1 + 1'd1);
- end
- if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
- a7ddrphy_bitslip15_value1 <= 3'd7;
- end
- a7ddrphy_bitslip15_r1 <= {a7ddrphy_bitslip151, a7ddrphy_bitslip15_r1[15:8]};
- a7ddrphy_rddata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_rddata_en | a7ddrphy_dfi_p1_rddata_en) | a7ddrphy_dfi_p2_rddata_en) | a7ddrphy_dfi_p3_rddata_en);
- a7ddrphy_rddata_en_tappeddelayline1 <= a7ddrphy_rddata_en_tappeddelayline0;
- a7ddrphy_rddata_en_tappeddelayline2 <= a7ddrphy_rddata_en_tappeddelayline1;
- a7ddrphy_rddata_en_tappeddelayline3 <= a7ddrphy_rddata_en_tappeddelayline2;
- a7ddrphy_rddata_en_tappeddelayline4 <= a7ddrphy_rddata_en_tappeddelayline3;
- a7ddrphy_rddata_en_tappeddelayline5 <= a7ddrphy_rddata_en_tappeddelayline4;
- a7ddrphy_rddata_en_tappeddelayline6 <= a7ddrphy_rddata_en_tappeddelayline5;
- a7ddrphy_rddata_en_tappeddelayline7 <= a7ddrphy_rddata_en_tappeddelayline6;
- a7ddrphy_wrdata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_wrdata_en | a7ddrphy_dfi_p1_wrdata_en) | a7ddrphy_dfi_p2_wrdata_en) | a7ddrphy_dfi_p3_wrdata_en);
- a7ddrphy_wrdata_en_tappeddelayline1 <= a7ddrphy_wrdata_en_tappeddelayline0;
- a7ddrphy_wrdata_en_tappeddelayline2 <= a7ddrphy_wrdata_en_tappeddelayline1;
- if (litedramcore_csr_dfi_p0_rddata_valid) begin
- litedramcore_phaseinjector0_rddata_status <= litedramcore_csr_dfi_p0_rddata;
- end
- if (litedramcore_csr_dfi_p1_rddata_valid) begin
- litedramcore_phaseinjector1_rddata_status <= litedramcore_csr_dfi_p1_rddata;
- end
- if (litedramcore_csr_dfi_p2_rddata_valid) begin
- litedramcore_phaseinjector2_rddata_status <= litedramcore_csr_dfi_p2_rddata;
- end
- if (litedramcore_csr_dfi_p3_rddata_valid) begin
- litedramcore_phaseinjector3_rddata_status <= litedramcore_csr_dfi_p3_rddata;
- end
- if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin
- litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1);
- end else begin
- litedramcore_timer_count1 <= 10'd781;
- end
- litedramcore_postponer_req_o <= 1'd0;
- if (litedramcore_postponer_req_i) begin
- litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1);
- if ((litedramcore_postponer_count == 1'd0)) begin
- litedramcore_postponer_count <= 1'd0;
- litedramcore_postponer_req_o <= 1'd1;
- end
- end
- if (litedramcore_sequencer_start0) begin
- litedramcore_sequencer_count <= 1'd0;
- end else begin
- if (litedramcore_sequencer_done1) begin
- if ((litedramcore_sequencer_count != 1'd0)) begin
- litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1);
- end
- end
- end
- litedramcore_cmd_payload_a <= 1'd0;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd0;
- litedramcore_cmd_payload_we <= 1'd0;
- litedramcore_sequencer_done1 <= 1'd0;
- if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin
- litedramcore_cmd_payload_a <= 11'd1024;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd1;
- litedramcore_cmd_payload_we <= 1'd1;
- end
- if ((litedramcore_sequencer_counter == 2'd3)) begin
- litedramcore_cmd_payload_a <= 11'd1024;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd1;
- litedramcore_cmd_payload_ras <= 1'd1;
- litedramcore_cmd_payload_we <= 1'd0;
- end
- if ((litedramcore_sequencer_counter == 6'd35)) begin
- litedramcore_cmd_payload_a <= 1'd0;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd0;
- litedramcore_cmd_payload_we <= 1'd0;
- litedramcore_sequencer_done1 <= 1'd1;
- end
- if ((litedramcore_sequencer_counter == 6'd35)) begin
- litedramcore_sequencer_counter <= 1'd0;
- end else begin
- if ((litedramcore_sequencer_counter != 1'd0)) begin
- litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1);
- end else begin
- if (litedramcore_sequencer_start1) begin
- litedramcore_sequencer_counter <= 1'd1;
- end
- end
- end
- if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin
- litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1);
- end else begin
- litedramcore_zqcs_timer_count1 <= 27'd99999999;
- end
- litedramcore_zqcs_executer_done <= 1'd0;
- if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin
- litedramcore_cmd_payload_a <= 11'd1024;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd1;
- litedramcore_cmd_payload_we <= 1'd1;
- end
- if ((litedramcore_zqcs_executer_counter == 2'd3)) begin
- litedramcore_cmd_payload_a <= 1'd0;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd0;
- litedramcore_cmd_payload_we <= 1'd1;
- end
- if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
- litedramcore_cmd_payload_a <= 1'd0;
- litedramcore_cmd_payload_ba <= 1'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd0;
- litedramcore_cmd_payload_we <= 1'd0;
- litedramcore_zqcs_executer_done <= 1'd1;
- end
- if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
- litedramcore_zqcs_executer_counter <= 1'd0;
- end else begin
- if ((litedramcore_zqcs_executer_counter != 1'd0)) begin
- litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1);
- end else begin
- if (litedramcore_zqcs_executer_start) begin
- litedramcore_zqcs_executer_counter <= 1'd1;
- end
- end
- end
- litedramcore_refresher_state <= litedramcore_refresher_next_state;
- if (litedramcore_bankmachine0_row_close) begin
- litedramcore_bankmachine0_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine0_row_open) begin
- litedramcore_bankmachine0_row_opened <= 1'd1;
- litedramcore_bankmachine0_row <= litedramcore_bankmachine0_cmd_buffer_source_payload_addr[20:7];
- end
- end
- if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine0_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine0_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_we & litedramcore_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable) & (~litedramcore_bankmachine0_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine0_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine0_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine0_cmd_buffer_lookahead_level <= (litedramcore_bankmachine0_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine0_cmd_buffer_source_valid) | litedramcore_bankmachine0_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine0_cmd_buffer_source_valid <= litedramcore_bankmachine0_cmd_buffer_sink_valid;
- litedramcore_bankmachine0_cmd_buffer_source_first <= litedramcore_bankmachine0_cmd_buffer_sink_first;
- litedramcore_bankmachine0_cmd_buffer_source_last <= litedramcore_bankmachine0_cmd_buffer_sink_last;
- litedramcore_bankmachine0_cmd_buffer_source_payload_we <= litedramcore_bankmachine0_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= litedramcore_bankmachine0_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine0_twtpcon_valid) begin
- litedramcore_bankmachine0_twtpcon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine0_twtpcon_ready)) begin
- litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine0_trccon_valid) begin
- litedramcore_bankmachine0_trccon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine0_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine0_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine0_trccon_ready)) begin
- litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1);
- if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin
- litedramcore_bankmachine0_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine0_trascon_valid) begin
- litedramcore_bankmachine0_trascon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_bankmachine0_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine0_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine0_trascon_ready)) begin
- litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1);
- if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin
- litedramcore_bankmachine0_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state;
- if (litedramcore_bankmachine1_row_close) begin
- litedramcore_bankmachine1_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine1_row_open) begin
- litedramcore_bankmachine1_row_opened <= 1'd1;
- litedramcore_bankmachine1_row <= litedramcore_bankmachine1_cmd_buffer_source_payload_addr[20:7];
- end
- end
- if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine1_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine1_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_we & litedramcore_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable) & (~litedramcore_bankmachine1_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine1_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine1_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine1_cmd_buffer_lookahead_level <= (litedramcore_bankmachine1_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine1_cmd_buffer_source_valid) | litedramcore_bankmachine1_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine1_cmd_buffer_source_valid <= litedramcore_bankmachine1_cmd_buffer_sink_valid;
- litedramcore_bankmachine1_cmd_buffer_source_first <= litedramcore_bankmachine1_cmd_buffer_sink_first;
- litedramcore_bankmachine1_cmd_buffer_source_last <= litedramcore_bankmachine1_cmd_buffer_sink_last;
- litedramcore_bankmachine1_cmd_buffer_source_payload_we <= litedramcore_bankmachine1_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= litedramcore_bankmachine1_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine1_twtpcon_valid) begin
- litedramcore_bankmachine1_twtpcon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine1_twtpcon_ready)) begin
- litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine1_trccon_valid) begin
- litedramcore_bankmachine1_trccon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine1_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine1_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine1_trccon_ready)) begin
- litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1);
- if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin
- litedramcore_bankmachine1_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine1_trascon_valid) begin
- litedramcore_bankmachine1_trascon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_bankmachine1_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine1_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine1_trascon_ready)) begin
- litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1);
- if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin
- litedramcore_bankmachine1_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state;
- if (litedramcore_bankmachine2_row_close) begin
- litedramcore_bankmachine2_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine2_row_open) begin
- litedramcore_bankmachine2_row_opened <= 1'd1;
- litedramcore_bankmachine2_row <= litedramcore_bankmachine2_cmd_buffer_source_payload_addr[20:7];
- end
- end
- if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine2_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine2_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_we & litedramcore_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable) & (~litedramcore_bankmachine2_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine2_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine2_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine2_cmd_buffer_lookahead_level <= (litedramcore_bankmachine2_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine2_cmd_buffer_source_valid) | litedramcore_bankmachine2_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine2_cmd_buffer_source_valid <= litedramcore_bankmachine2_cmd_buffer_sink_valid;
- litedramcore_bankmachine2_cmd_buffer_source_first <= litedramcore_bankmachine2_cmd_buffer_sink_first;
- litedramcore_bankmachine2_cmd_buffer_source_last <= litedramcore_bankmachine2_cmd_buffer_sink_last;
- litedramcore_bankmachine2_cmd_buffer_source_payload_we <= litedramcore_bankmachine2_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= litedramcore_bankmachine2_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine2_twtpcon_valid) begin
- litedramcore_bankmachine2_twtpcon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine2_twtpcon_ready)) begin
- litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine2_trccon_valid) begin
- litedramcore_bankmachine2_trccon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine2_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine2_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine2_trccon_ready)) begin
- litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1);
- if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin
- litedramcore_bankmachine2_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine2_trascon_valid) begin
- litedramcore_bankmachine2_trascon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_bankmachine2_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine2_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine2_trascon_ready)) begin
- litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1);
- if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin
- litedramcore_bankmachine2_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state;
- if (litedramcore_bankmachine3_row_close) begin
- litedramcore_bankmachine3_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine3_row_open) begin
- litedramcore_bankmachine3_row_opened <= 1'd1;
- litedramcore_bankmachine3_row <= litedramcore_bankmachine3_cmd_buffer_source_payload_addr[20:7];
- end
- end
- if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine3_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine3_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_we & litedramcore_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable) & (~litedramcore_bankmachine3_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine3_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine3_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine3_cmd_buffer_lookahead_level <= (litedramcore_bankmachine3_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine3_cmd_buffer_source_valid) | litedramcore_bankmachine3_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine3_cmd_buffer_source_valid <= litedramcore_bankmachine3_cmd_buffer_sink_valid;
- litedramcore_bankmachine3_cmd_buffer_source_first <= litedramcore_bankmachine3_cmd_buffer_sink_first;
- litedramcore_bankmachine3_cmd_buffer_source_last <= litedramcore_bankmachine3_cmd_buffer_sink_last;
- litedramcore_bankmachine3_cmd_buffer_source_payload_we <= litedramcore_bankmachine3_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= litedramcore_bankmachine3_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine3_twtpcon_valid) begin
- litedramcore_bankmachine3_twtpcon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine3_twtpcon_ready)) begin
- litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine3_trccon_valid) begin
- litedramcore_bankmachine3_trccon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine3_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine3_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine3_trccon_ready)) begin
- litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1);
- if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin
- litedramcore_bankmachine3_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine3_trascon_valid) begin
- litedramcore_bankmachine3_trascon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_bankmachine3_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine3_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine3_trascon_ready)) begin
- litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1);
- if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin
- litedramcore_bankmachine3_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state;
- if (litedramcore_bankmachine4_row_close) begin
- litedramcore_bankmachine4_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine4_row_open) begin
- litedramcore_bankmachine4_row_opened <= 1'd1;
- litedramcore_bankmachine4_row <= litedramcore_bankmachine4_cmd_buffer_source_payload_addr[20:7];
- end
- end
- if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine4_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine4_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_we & litedramcore_bankmachine4_cmd_buffer_lookahead_syncfifo4_writable) & (~litedramcore_bankmachine4_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine4_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine4_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine4_cmd_buffer_lookahead_level <= (litedramcore_bankmachine4_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine4_cmd_buffer_source_valid) | litedramcore_bankmachine4_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine4_cmd_buffer_source_valid <= litedramcore_bankmachine4_cmd_buffer_sink_valid;
- litedramcore_bankmachine4_cmd_buffer_source_first <= litedramcore_bankmachine4_cmd_buffer_sink_first;
- litedramcore_bankmachine4_cmd_buffer_source_last <= litedramcore_bankmachine4_cmd_buffer_sink_last;
- litedramcore_bankmachine4_cmd_buffer_source_payload_we <= litedramcore_bankmachine4_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= litedramcore_bankmachine4_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine4_twtpcon_valid) begin
- litedramcore_bankmachine4_twtpcon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine4_twtpcon_ready)) begin
- litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine4_trccon_valid) begin
- litedramcore_bankmachine4_trccon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine4_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine4_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine4_trccon_ready)) begin
- litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1);
- if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin
- litedramcore_bankmachine4_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine4_trascon_valid) begin
- litedramcore_bankmachine4_trascon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_bankmachine4_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine4_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine4_trascon_ready)) begin
- litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1);
- if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin
- litedramcore_bankmachine4_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state;
- if (litedramcore_bankmachine5_row_close) begin
- litedramcore_bankmachine5_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine5_row_open) begin
- litedramcore_bankmachine5_row_opened <= 1'd1;
- litedramcore_bankmachine5_row <= litedramcore_bankmachine5_cmd_buffer_source_payload_addr[20:7];
- end
- end
- if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine5_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine5_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_we & litedramcore_bankmachine5_cmd_buffer_lookahead_syncfifo5_writable) & (~litedramcore_bankmachine5_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine5_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine5_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine5_cmd_buffer_lookahead_level <= (litedramcore_bankmachine5_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine5_cmd_buffer_source_valid) | litedramcore_bankmachine5_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine5_cmd_buffer_source_valid <= litedramcore_bankmachine5_cmd_buffer_sink_valid;
- litedramcore_bankmachine5_cmd_buffer_source_first <= litedramcore_bankmachine5_cmd_buffer_sink_first;
- litedramcore_bankmachine5_cmd_buffer_source_last <= litedramcore_bankmachine5_cmd_buffer_sink_last;
- litedramcore_bankmachine5_cmd_buffer_source_payload_we <= litedramcore_bankmachine5_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= litedramcore_bankmachine5_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine5_twtpcon_valid) begin
- litedramcore_bankmachine5_twtpcon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine5_twtpcon_ready)) begin
- litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine5_trccon_valid) begin
- litedramcore_bankmachine5_trccon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine5_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine5_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine5_trccon_ready)) begin
- litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1);
- if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin
- litedramcore_bankmachine5_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine5_trascon_valid) begin
- litedramcore_bankmachine5_trascon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_bankmachine5_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine5_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine5_trascon_ready)) begin
- litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1);
- if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin
- litedramcore_bankmachine5_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state;
- if (litedramcore_bankmachine6_row_close) begin
- litedramcore_bankmachine6_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine6_row_open) begin
- litedramcore_bankmachine6_row_opened <= 1'd1;
- litedramcore_bankmachine6_row <= litedramcore_bankmachine6_cmd_buffer_source_payload_addr[20:7];
- end
- end
- if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine6_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine6_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_we & litedramcore_bankmachine6_cmd_buffer_lookahead_syncfifo6_writable) & (~litedramcore_bankmachine6_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine6_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine6_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine6_cmd_buffer_lookahead_level <= (litedramcore_bankmachine6_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine6_cmd_buffer_source_valid) | litedramcore_bankmachine6_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine6_cmd_buffer_source_valid <= litedramcore_bankmachine6_cmd_buffer_sink_valid;
- litedramcore_bankmachine6_cmd_buffer_source_first <= litedramcore_bankmachine6_cmd_buffer_sink_first;
- litedramcore_bankmachine6_cmd_buffer_source_last <= litedramcore_bankmachine6_cmd_buffer_sink_last;
- litedramcore_bankmachine6_cmd_buffer_source_payload_we <= litedramcore_bankmachine6_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= litedramcore_bankmachine6_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine6_twtpcon_valid) begin
- litedramcore_bankmachine6_twtpcon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine6_twtpcon_ready)) begin
- litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine6_trccon_valid) begin
- litedramcore_bankmachine6_trccon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine6_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine6_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine6_trccon_ready)) begin
- litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1);
- if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin
- litedramcore_bankmachine6_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine6_trascon_valid) begin
- litedramcore_bankmachine6_trascon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_bankmachine6_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine6_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine6_trascon_ready)) begin
- litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1);
- if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin
- litedramcore_bankmachine6_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state;
- if (litedramcore_bankmachine7_row_close) begin
- litedramcore_bankmachine7_row_opened <= 1'd0;
- end else begin
- if (litedramcore_bankmachine7_row_open) begin
- litedramcore_bankmachine7_row_opened <= 1'd1;
- litedramcore_bankmachine7_row <= litedramcore_bankmachine7_cmd_buffer_source_payload_addr[20:7];
- end
- end
- if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= (litedramcore_bankmachine7_cmd_buffer_lookahead_produce + 1'd1);
- end
- if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= (litedramcore_bankmachine7_cmd_buffer_lookahead_consume + 1'd1);
- end
- if (((litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_we & litedramcore_bankmachine7_cmd_buffer_lookahead_syncfifo7_writable) & (~litedramcore_bankmachine7_cmd_buffer_lookahead_replace))) begin
- if ((~litedramcore_bankmachine7_cmd_buffer_lookahead_do_read)) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level + 1'd1);
- end
- end else begin
- if (litedramcore_bankmachine7_cmd_buffer_lookahead_do_read) begin
- litedramcore_bankmachine7_cmd_buffer_lookahead_level <= (litedramcore_bankmachine7_cmd_buffer_lookahead_level - 1'd1);
- end
- end
- if (((~litedramcore_bankmachine7_cmd_buffer_source_valid) | litedramcore_bankmachine7_cmd_buffer_source_ready)) begin
- litedramcore_bankmachine7_cmd_buffer_source_valid <= litedramcore_bankmachine7_cmd_buffer_sink_valid;
- litedramcore_bankmachine7_cmd_buffer_source_first <= litedramcore_bankmachine7_cmd_buffer_sink_first;
- litedramcore_bankmachine7_cmd_buffer_source_last <= litedramcore_bankmachine7_cmd_buffer_sink_last;
- litedramcore_bankmachine7_cmd_buffer_source_payload_we <= litedramcore_bankmachine7_cmd_buffer_sink_payload_we;
- litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= litedramcore_bankmachine7_cmd_buffer_sink_payload_addr;
- end
- if (litedramcore_bankmachine7_twtpcon_valid) begin
- litedramcore_bankmachine7_twtpcon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine7_twtpcon_ready)) begin
- litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1);
- if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
- litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine7_trccon_valid) begin
- litedramcore_bankmachine7_trccon_count <= 3'd5;
- if (1'd0) begin
- litedramcore_bankmachine7_trccon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine7_trccon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine7_trccon_ready)) begin
- litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1);
- if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin
- litedramcore_bankmachine7_trccon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_bankmachine7_trascon_valid) begin
- litedramcore_bankmachine7_trascon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_bankmachine7_trascon_ready <= 1'd1;
- end else begin
- litedramcore_bankmachine7_trascon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_bankmachine7_trascon_ready)) begin
- litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1);
- if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin
- litedramcore_bankmachine7_trascon_ready <= 1'd1;
- end
- end
- end
- litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state;
- if ((~litedramcore_en0)) begin
- litedramcore_time0 <= 5'd31;
- end else begin
- if ((~litedramcore_max_time0)) begin
- litedramcore_time0 <= (litedramcore_time0 - 1'd1);
- end
- end
- if ((~litedramcore_en1)) begin
- litedramcore_time1 <= 4'd15;
- end else begin
- if ((~litedramcore_max_time1)) begin
- litedramcore_time1 <= (litedramcore_time1 - 1'd1);
- end
- end
- if (litedramcore_choose_cmd_ce) begin
- case (litedramcore_choose_cmd_grant)
- 1'd0: begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
- end
- end
- end
- end
- end
- end
- end
- end
- 1'd1: begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
- end
- end
- end
- end
- end
- end
- end
- end
- 2'd2: begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
- end
- end
- end
- end
- end
- end
- end
- end
- 2'd3: begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd4: begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd5: begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd6: begin
- if (litedramcore_choose_cmd_request[7]) begin
- litedramcore_choose_cmd_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd7: begin
- if (litedramcore_choose_cmd_request[0]) begin
- litedramcore_choose_cmd_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_cmd_request[1]) begin
- litedramcore_choose_cmd_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_cmd_request[2]) begin
- litedramcore_choose_cmd_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_cmd_request[3]) begin
- litedramcore_choose_cmd_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_cmd_request[4]) begin
- litedramcore_choose_cmd_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_cmd_request[5]) begin
- litedramcore_choose_cmd_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_cmd_request[6]) begin
- litedramcore_choose_cmd_grant <= 3'd6;
- end
- end
- end
- end
- end
- end
- end
- end
- endcase
- end
- if (litedramcore_choose_req_ce) begin
- case (litedramcore_choose_req_grant)
- 1'd0: begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
- end
- end
- end
- end
- end
- end
- end
- end
- 1'd1: begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
- end
- end
- end
- end
- end
- end
- end
- end
- 2'd2: begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
- end
- end
- end
- end
- end
- end
- end
- end
- 2'd3: begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd4: begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd5: begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
- end else begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd6: begin
- if (litedramcore_choose_req_request[7]) begin
- litedramcore_choose_req_grant <= 3'd7;
- end else begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
- end
- end
- end
- end
- end
- end
- end
- end
- 3'd7: begin
- if (litedramcore_choose_req_request[0]) begin
- litedramcore_choose_req_grant <= 1'd0;
- end else begin
- if (litedramcore_choose_req_request[1]) begin
- litedramcore_choose_req_grant <= 1'd1;
- end else begin
- if (litedramcore_choose_req_request[2]) begin
- litedramcore_choose_req_grant <= 2'd2;
- end else begin
- if (litedramcore_choose_req_request[3]) begin
- litedramcore_choose_req_grant <= 2'd3;
- end else begin
- if (litedramcore_choose_req_request[4]) begin
- litedramcore_choose_req_grant <= 3'd4;
- end else begin
- if (litedramcore_choose_req_request[5]) begin
- litedramcore_choose_req_grant <= 3'd5;
- end else begin
- if (litedramcore_choose_req_request[6]) begin
- litedramcore_choose_req_grant <= 3'd6;
- end
- end
- end
- end
- end
- end
- end
- end
- endcase
- end
- litedramcore_dfi_p0_cs_n <= 1'd0;
- litedramcore_dfi_p0_bank <= array_muxed0;
- litedramcore_dfi_p0_address <= array_muxed1;
- litedramcore_dfi_p0_cas_n <= (~array_muxed2);
- litedramcore_dfi_p0_ras_n <= (~array_muxed3);
- litedramcore_dfi_p0_we_n <= (~array_muxed4);
- litedramcore_dfi_p0_rddata_en <= array_muxed5;
- litedramcore_dfi_p0_wrdata_en <= array_muxed6;
- litedramcore_dfi_p1_cs_n <= 1'd0;
- litedramcore_dfi_p1_bank <= array_muxed7;
- litedramcore_dfi_p1_address <= array_muxed8;
- litedramcore_dfi_p1_cas_n <= (~array_muxed9);
- litedramcore_dfi_p1_ras_n <= (~array_muxed10);
- litedramcore_dfi_p1_we_n <= (~array_muxed11);
- litedramcore_dfi_p1_rddata_en <= array_muxed12;
- litedramcore_dfi_p1_wrdata_en <= array_muxed13;
- litedramcore_dfi_p2_cs_n <= 1'd0;
- litedramcore_dfi_p2_bank <= array_muxed14;
- litedramcore_dfi_p2_address <= array_muxed15;
- litedramcore_dfi_p2_cas_n <= (~array_muxed16);
- litedramcore_dfi_p2_ras_n <= (~array_muxed17);
- litedramcore_dfi_p2_we_n <= (~array_muxed18);
- litedramcore_dfi_p2_rddata_en <= array_muxed19;
- litedramcore_dfi_p2_wrdata_en <= array_muxed20;
- litedramcore_dfi_p3_cs_n <= 1'd0;
- litedramcore_dfi_p3_bank <= array_muxed21;
- litedramcore_dfi_p3_address <= array_muxed22;
- litedramcore_dfi_p3_cas_n <= (~array_muxed23);
- litedramcore_dfi_p3_ras_n <= (~array_muxed24);
- litedramcore_dfi_p3_we_n <= (~array_muxed25);
- litedramcore_dfi_p3_rddata_en <= array_muxed26;
- litedramcore_dfi_p3_wrdata_en <= array_muxed27;
- if (litedramcore_trrdcon_valid) begin
- litedramcore_trrdcon_count <= 1'd1;
- if (1'd0) begin
- litedramcore_trrdcon_ready <= 1'd1;
- end else begin
- litedramcore_trrdcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_trrdcon_ready)) begin
- litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1);
- if ((litedramcore_trrdcon_count == 1'd1)) begin
- litedramcore_trrdcon_ready <= 1'd1;
- end
- end
- end
- litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid};
- if ((litedramcore_tfawcon_count < 3'd4)) begin
- if ((litedramcore_tfawcon_count == 2'd3)) begin
- litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid);
- end else begin
- litedramcore_tfawcon_ready <= 1'd1;
- end
- end
- if (litedramcore_tccdcon_valid) begin
- litedramcore_tccdcon_count <= 1'd0;
- if (1'd1) begin
- litedramcore_tccdcon_ready <= 1'd1;
- end else begin
- litedramcore_tccdcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_tccdcon_ready)) begin
- litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1);
- if ((litedramcore_tccdcon_count == 1'd1)) begin
- litedramcore_tccdcon_ready <= 1'd1;
- end
- end
- end
- if (litedramcore_twtrcon_valid) begin
- litedramcore_twtrcon_count <= 3'd4;
- if (1'd0) begin
- litedramcore_twtrcon_ready <= 1'd1;
- end else begin
- litedramcore_twtrcon_ready <= 1'd0;
- end
- end else begin
- if ((~litedramcore_twtrcon_ready)) begin
- litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1);
- if ((litedramcore_twtrcon_count == 1'd1)) begin
- litedramcore_twtrcon_ready <= 1'd1;
- end
- end
- end
- litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state;
- litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready));
- litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0;
- litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid));
- litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0;
- litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1;
- litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2;
- litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3;
- litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4;
- litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5;
- litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6;
- litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7;
- litedramcore_state <= litedramcore_next_state;
- if (litedramcore_dat_w_next_value_ce0) begin
- litedramcore_dat_w <= litedramcore_dat_w_next_value0;
- end
- if (litedramcore_adr_next_value_ce1) begin
- litedramcore_adr <= litedramcore_adr_next_value1;
- end
- if (litedramcore_we_next_value_ce2) begin
- litedramcore_we <= litedramcore_we_next_value2;
- end
- interface0_bank_bus_dat_r <= 1'd0;
- if (csrbank0_sel) begin
- case (interface0_bank_bus_adr[8:0])
- 1'd0: begin
- interface0_bank_bus_dat_r <= csrbank0_init_done0_w;
- end
- 1'd1: begin
- interface0_bank_bus_dat_r <= csrbank0_init_error0_w;
- end
- endcase
- end
- if (csrbank0_init_done0_re) begin
- init_done_storage <= csrbank0_init_done0_r;
- end
- init_done_re <= csrbank0_init_done0_re;
- if (csrbank0_init_error0_re) begin
- init_error_storage <= csrbank0_init_error0_r;
- end
- init_error_re <= csrbank0_init_error0_re;
- interface1_bank_bus_dat_r <= 1'd0;
- if (csrbank1_sel) begin
- case (interface1_bank_bus_adr[8:0])
- 1'd0: begin
- interface1_bank_bus_dat_r <= csrbank1_rst0_w;
- end
- 1'd1: begin
- interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w;
- end
- 2'd2: begin
- interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w;
- end
- 2'd3: begin
- interface1_bank_bus_dat_r <= csrbank1_wlevel_en0_w;
- end
- 3'd4: begin
- interface1_bank_bus_dat_r <= a7ddrphy_wlevel_strobe_w;
- end
- 3'd5: begin
- interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_rst_w;
- end
- 3'd6: begin
- interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_inc_w;
- end
- 3'd7: begin
- interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_rst_w;
- end
- 4'd8: begin
- interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_w;
- end
- 4'd9: begin
- interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_rst_w;
- end
- 4'd10: begin
- interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_w;
- end
- 4'd11: begin
- interface1_bank_bus_dat_r <= csrbank1_rdphase0_w;
- end
- 4'd12: begin
- interface1_bank_bus_dat_r <= csrbank1_wrphase0_w;
- end
- endcase
- end
- if (csrbank1_rst0_re) begin
- a7ddrphy_rst_storage <= csrbank1_rst0_r;
- end
- a7ddrphy_rst_re <= csrbank1_rst0_re;
- if (csrbank1_dly_sel0_re) begin
- a7ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r;
- end
- a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re;
- if (csrbank1_half_sys8x_taps0_re) begin
- a7ddrphy_half_sys8x_taps_storage[4:0] <= csrbank1_half_sys8x_taps0_r;
- end
- a7ddrphy_half_sys8x_taps_re <= csrbank1_half_sys8x_taps0_re;
- if (csrbank1_wlevel_en0_re) begin
- a7ddrphy_wlevel_en_storage <= csrbank1_wlevel_en0_r;
- end
- a7ddrphy_wlevel_en_re <= csrbank1_wlevel_en0_re;
- if (csrbank1_rdphase0_re) begin
- a7ddrphy_rdphase_storage[1:0] <= csrbank1_rdphase0_r;
- end
- a7ddrphy_rdphase_re <= csrbank1_rdphase0_re;
- if (csrbank1_wrphase0_re) begin
- a7ddrphy_wrphase_storage[1:0] <= csrbank1_wrphase0_r;
- end
- a7ddrphy_wrphase_re <= csrbank1_wrphase0_re;
- interface2_bank_bus_dat_r <= 1'd0;
- if (csrbank2_sel) begin
- case (interface2_bank_bus_adr[8:0])
- 1'd0: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w;
- end
- 1'd1: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w;
- end
- 2'd2: begin
- interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w;
- end
- 2'd3: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w;
- end
- 3'd4: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w;
- end
- 3'd5: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w;
- end
- 3'd6: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata_w;
- end
- 3'd7: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w;
- end
- 4'd8: begin
- interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w;
- end
- 4'd9: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w;
- end
- 4'd10: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w;
- end
- 4'd11: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w;
- end
- 4'd12: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata_w;
- end
- 4'd13: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w;
- end
- 4'd14: begin
- interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w;
- end
- 4'd15: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w;
- end
- 5'd16: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w;
- end
- 5'd17: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w;
- end
- 5'd18: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata_w;
- end
- 5'd19: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w;
- end
- 5'd20: begin
- interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w;
- end
- 5'd21: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w;
- end
- 5'd22: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w;
- end
- 5'd23: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w;
- end
- 5'd24: begin
- interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata_w;
- end
- endcase
- end
- if (csrbank2_dfii_control0_re) begin
- litedramcore_storage[3:0] <= csrbank2_dfii_control0_r;
- end
- litedramcore_re <= csrbank2_dfii_control0_re;
- if (csrbank2_dfii_pi0_command0_re) begin
- litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r;
- end
- litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re;
- if (csrbank2_dfii_pi0_address0_re) begin
- litedramcore_phaseinjector0_address_storage[13:0] <= csrbank2_dfii_pi0_address0_r;
- end
- litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re;
- if (csrbank2_dfii_pi0_baddress0_re) begin
- litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r;
- end
- litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re;
- if (csrbank2_dfii_pi0_wrdata0_re) begin
- litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r;
- end
- litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re;
- litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata_re;
- if (csrbank2_dfii_pi1_command0_re) begin
- litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r;
- end
- litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re;
- if (csrbank2_dfii_pi1_address0_re) begin
- litedramcore_phaseinjector1_address_storage[13:0] <= csrbank2_dfii_pi1_address0_r;
- end
- litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re;
- if (csrbank2_dfii_pi1_baddress0_re) begin
- litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r;
- end
- litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re;
- if (csrbank2_dfii_pi1_wrdata0_re) begin
- litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r;
- end
- litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re;
- litedramcore_phaseinjector1_rddata_re <= csrbank2_dfii_pi1_rddata_re;
- if (csrbank2_dfii_pi2_command0_re) begin
- litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r;
- end
- litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re;
- if (csrbank2_dfii_pi2_address0_re) begin
- litedramcore_phaseinjector2_address_storage[13:0] <= csrbank2_dfii_pi2_address0_r;
- end
- litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re;
- if (csrbank2_dfii_pi2_baddress0_re) begin
- litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r;
- end
- litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re;
- if (csrbank2_dfii_pi2_wrdata0_re) begin
- litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r;
- end
- litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re;
- litedramcore_phaseinjector2_rddata_re <= csrbank2_dfii_pi2_rddata_re;
- if (csrbank2_dfii_pi3_command0_re) begin
- litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r;
- end
- litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re;
- if (csrbank2_dfii_pi3_address0_re) begin
- litedramcore_phaseinjector3_address_storage[13:0] <= csrbank2_dfii_pi3_address0_r;
- end
- litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re;
- if (csrbank2_dfii_pi3_baddress0_re) begin
- litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r;
- end
- litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re;
- if (csrbank2_dfii_pi3_wrdata0_re) begin
- litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r;
- end
- litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re;
- litedramcore_phaseinjector3_rddata_re <= csrbank2_dfii_pi3_rddata_re;
- if (sys_rst) begin
- a7ddrphy_rst_storage <= 1'd0;
- a7ddrphy_rst_re <= 1'd0;
- a7ddrphy_dly_sel_storage <= 2'd0;
- a7ddrphy_dly_sel_re <= 1'd0;
- a7ddrphy_half_sys8x_taps_storage <= 5'd8;
- a7ddrphy_half_sys8x_taps_re <= 1'd0;
- a7ddrphy_wlevel_en_storage <= 1'd0;
- a7ddrphy_wlevel_en_re <= 1'd0;
- a7ddrphy_rdphase_storage <= 2'd2;
- a7ddrphy_rdphase_re <= 1'd0;
- a7ddrphy_wrphase_storage <= 2'd3;
- a7ddrphy_wrphase_re <= 1'd0;
- a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
- a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
- a7ddrphy_dqspattern_o1 <= 8'd0;
- a7ddrphy_bitslip0_value0 <= 3'd7;
- a7ddrphy_bitslip1_value0 <= 3'd7;
- a7ddrphy_bitslip0_value1 <= 3'd7;
- a7ddrphy_bitslip1_value1 <= 3'd7;
- a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
- a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
- a7ddrphy_bitslip0_value2 <= 3'd7;
- a7ddrphy_bitslip0_value3 <= 3'd7;
- a7ddrphy_bitslip1_value2 <= 3'd7;
- a7ddrphy_bitslip1_value3 <= 3'd7;
- a7ddrphy_bitslip2_value0 <= 3'd7;
- a7ddrphy_bitslip2_value1 <= 3'd7;
- a7ddrphy_bitslip3_value0 <= 3'd7;
- a7ddrphy_bitslip3_value1 <= 3'd7;
- a7ddrphy_bitslip4_value0 <= 3'd7;
- a7ddrphy_bitslip4_value1 <= 3'd7;
- a7ddrphy_bitslip5_value0 <= 3'd7;
- a7ddrphy_bitslip5_value1 <= 3'd7;
- a7ddrphy_bitslip6_value0 <= 3'd7;
- a7ddrphy_bitslip6_value1 <= 3'd7;
- a7ddrphy_bitslip7_value0 <= 3'd7;
- a7ddrphy_bitslip7_value1 <= 3'd7;
- a7ddrphy_bitslip8_value0 <= 3'd7;
- a7ddrphy_bitslip8_value1 <= 3'd7;
- a7ddrphy_bitslip9_value0 <= 3'd7;
- a7ddrphy_bitslip9_value1 <= 3'd7;
- a7ddrphy_bitslip10_value0 <= 3'd7;
- a7ddrphy_bitslip10_value1 <= 3'd7;
- a7ddrphy_bitslip11_value0 <= 3'd7;
- a7ddrphy_bitslip11_value1 <= 3'd7;
- a7ddrphy_bitslip12_value0 <= 3'd7;
- a7ddrphy_bitslip12_value1 <= 3'd7;
- a7ddrphy_bitslip13_value0 <= 3'd7;
- a7ddrphy_bitslip13_value1 <= 3'd7;
- a7ddrphy_bitslip14_value0 <= 3'd7;
- a7ddrphy_bitslip14_value1 <= 3'd7;
- a7ddrphy_bitslip15_value0 <= 3'd7;
- a7ddrphy_bitslip15_value1 <= 3'd7;
- a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0;
- a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0;
- a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0;
- a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0;
- a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0;
- a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0;
- a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0;
- a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0;
- a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0;
- a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0;
- a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0;
- litedramcore_storage <= 4'd1;
- litedramcore_re <= 1'd0;
- litedramcore_phaseinjector0_command_storage <= 6'd0;
- litedramcore_phaseinjector0_command_re <= 1'd0;
- litedramcore_phaseinjector0_address_re <= 1'd0;
- litedramcore_phaseinjector0_baddress_re <= 1'd0;
- litedramcore_phaseinjector0_wrdata_re <= 1'd0;
- litedramcore_phaseinjector0_rddata_status <= 32'd0;
- litedramcore_phaseinjector0_rddata_re <= 1'd0;
- litedramcore_phaseinjector1_command_storage <= 6'd0;
- litedramcore_phaseinjector1_command_re <= 1'd0;
- litedramcore_phaseinjector1_address_re <= 1'd0;
- litedramcore_phaseinjector1_baddress_re <= 1'd0;
- litedramcore_phaseinjector1_wrdata_re <= 1'd0;
- litedramcore_phaseinjector1_rddata_status <= 32'd0;
- litedramcore_phaseinjector1_rddata_re <= 1'd0;
- litedramcore_phaseinjector2_command_storage <= 6'd0;
- litedramcore_phaseinjector2_command_re <= 1'd0;
- litedramcore_phaseinjector2_address_re <= 1'd0;
- litedramcore_phaseinjector2_baddress_re <= 1'd0;
- litedramcore_phaseinjector2_wrdata_re <= 1'd0;
- litedramcore_phaseinjector2_rddata_status <= 32'd0;
- litedramcore_phaseinjector2_rddata_re <= 1'd0;
- litedramcore_phaseinjector3_command_storage <= 6'd0;
- litedramcore_phaseinjector3_command_re <= 1'd0;
- litedramcore_phaseinjector3_address_re <= 1'd0;
- litedramcore_phaseinjector3_baddress_re <= 1'd0;
- litedramcore_phaseinjector3_wrdata_re <= 1'd0;
- litedramcore_phaseinjector3_rddata_status <= 32'd0;
- litedramcore_phaseinjector3_rddata_re <= 1'd0;
- litedramcore_dfi_p0_address <= 14'd0;
- litedramcore_dfi_p0_bank <= 3'd0;
- litedramcore_dfi_p0_cas_n <= 1'd1;
- litedramcore_dfi_p0_cs_n <= 1'd1;
- litedramcore_dfi_p0_ras_n <= 1'd1;
- litedramcore_dfi_p0_we_n <= 1'd1;
- litedramcore_dfi_p0_wrdata_en <= 1'd0;
- litedramcore_dfi_p0_rddata_en <= 1'd0;
- litedramcore_dfi_p1_address <= 14'd0;
- litedramcore_dfi_p1_bank <= 3'd0;
- litedramcore_dfi_p1_cas_n <= 1'd1;
- litedramcore_dfi_p1_cs_n <= 1'd1;
- litedramcore_dfi_p1_ras_n <= 1'd1;
- litedramcore_dfi_p1_we_n <= 1'd1;
- litedramcore_dfi_p1_wrdata_en <= 1'd0;
- litedramcore_dfi_p1_rddata_en <= 1'd0;
- litedramcore_dfi_p2_address <= 14'd0;
- litedramcore_dfi_p2_bank <= 3'd0;
- litedramcore_dfi_p2_cas_n <= 1'd1;
- litedramcore_dfi_p2_cs_n <= 1'd1;
- litedramcore_dfi_p2_ras_n <= 1'd1;
- litedramcore_dfi_p2_we_n <= 1'd1;
- litedramcore_dfi_p2_wrdata_en <= 1'd0;
- litedramcore_dfi_p2_rddata_en <= 1'd0;
- litedramcore_dfi_p3_address <= 14'd0;
- litedramcore_dfi_p3_bank <= 3'd0;
- litedramcore_dfi_p3_cas_n <= 1'd1;
- litedramcore_dfi_p3_cs_n <= 1'd1;
- litedramcore_dfi_p3_ras_n <= 1'd1;
- litedramcore_dfi_p3_we_n <= 1'd1;
- litedramcore_dfi_p3_wrdata_en <= 1'd0;
- litedramcore_dfi_p3_rddata_en <= 1'd0;
- litedramcore_cmd_payload_a <= 14'd0;
- litedramcore_cmd_payload_ba <= 3'd0;
- litedramcore_cmd_payload_cas <= 1'd0;
- litedramcore_cmd_payload_ras <= 1'd0;
- litedramcore_cmd_payload_we <= 1'd0;
- litedramcore_timer_count1 <= 10'd781;
- litedramcore_postponer_req_o <= 1'd0;
- litedramcore_postponer_count <= 1'd0;
- litedramcore_sequencer_done1 <= 1'd0;
- litedramcore_sequencer_counter <= 6'd0;
- litedramcore_sequencer_count <= 1'd0;
- litedramcore_zqcs_timer_count1 <= 27'd99999999;
- litedramcore_zqcs_executer_done <= 1'd0;
- litedramcore_zqcs_executer_counter <= 5'd0;
- litedramcore_bankmachine0_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine0_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine0_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine0_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine0_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine0_cmd_buffer_source_payload_addr <= 21'd0;
- litedramcore_bankmachine0_row <= 14'd0;
- litedramcore_bankmachine0_row_opened <= 1'd0;
- litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine0_twtpcon_count <= 3'd0;
- litedramcore_bankmachine0_trccon_ready <= 1'd0;
- litedramcore_bankmachine0_trccon_count <= 3'd0;
- litedramcore_bankmachine0_trascon_ready <= 1'd0;
- litedramcore_bankmachine0_trascon_count <= 3'd0;
- litedramcore_bankmachine1_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine1_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine1_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine1_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine1_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine1_cmd_buffer_source_payload_addr <= 21'd0;
- litedramcore_bankmachine1_row <= 14'd0;
- litedramcore_bankmachine1_row_opened <= 1'd0;
- litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine1_twtpcon_count <= 3'd0;
- litedramcore_bankmachine1_trccon_ready <= 1'd0;
- litedramcore_bankmachine1_trccon_count <= 3'd0;
- litedramcore_bankmachine1_trascon_ready <= 1'd0;
- litedramcore_bankmachine1_trascon_count <= 3'd0;
- litedramcore_bankmachine2_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine2_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine2_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine2_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine2_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine2_cmd_buffer_source_payload_addr <= 21'd0;
- litedramcore_bankmachine2_row <= 14'd0;
- litedramcore_bankmachine2_row_opened <= 1'd0;
- litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine2_twtpcon_count <= 3'd0;
- litedramcore_bankmachine2_trccon_ready <= 1'd0;
- litedramcore_bankmachine2_trccon_count <= 3'd0;
- litedramcore_bankmachine2_trascon_ready <= 1'd0;
- litedramcore_bankmachine2_trascon_count <= 3'd0;
- litedramcore_bankmachine3_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine3_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine3_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine3_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine3_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine3_cmd_buffer_source_payload_addr <= 21'd0;
- litedramcore_bankmachine3_row <= 14'd0;
- litedramcore_bankmachine3_row_opened <= 1'd0;
- litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine3_twtpcon_count <= 3'd0;
- litedramcore_bankmachine3_trccon_ready <= 1'd0;
- litedramcore_bankmachine3_trccon_count <= 3'd0;
- litedramcore_bankmachine3_trascon_ready <= 1'd0;
- litedramcore_bankmachine3_trascon_count <= 3'd0;
- litedramcore_bankmachine4_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine4_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine4_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine4_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine4_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine4_cmd_buffer_source_payload_addr <= 21'd0;
- litedramcore_bankmachine4_row <= 14'd0;
- litedramcore_bankmachine4_row_opened <= 1'd0;
- litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine4_twtpcon_count <= 3'd0;
- litedramcore_bankmachine4_trccon_ready <= 1'd0;
- litedramcore_bankmachine4_trccon_count <= 3'd0;
- litedramcore_bankmachine4_trascon_ready <= 1'd0;
- litedramcore_bankmachine4_trascon_count <= 3'd0;
- litedramcore_bankmachine5_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine5_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine5_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine5_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine5_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine5_cmd_buffer_source_payload_addr <= 21'd0;
- litedramcore_bankmachine5_row <= 14'd0;
- litedramcore_bankmachine5_row_opened <= 1'd0;
- litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine5_twtpcon_count <= 3'd0;
- litedramcore_bankmachine5_trccon_ready <= 1'd0;
- litedramcore_bankmachine5_trccon_count <= 3'd0;
- litedramcore_bankmachine5_trascon_ready <= 1'd0;
- litedramcore_bankmachine5_trascon_count <= 3'd0;
- litedramcore_bankmachine6_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine6_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine6_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine6_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine6_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine6_cmd_buffer_source_payload_addr <= 21'd0;
- litedramcore_bankmachine6_row <= 14'd0;
- litedramcore_bankmachine6_row_opened <= 1'd0;
- litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine6_twtpcon_count <= 3'd0;
- litedramcore_bankmachine6_trccon_ready <= 1'd0;
- litedramcore_bankmachine6_trccon_count <= 3'd0;
- litedramcore_bankmachine6_trascon_ready <= 1'd0;
- litedramcore_bankmachine6_trascon_count <= 3'd0;
- litedramcore_bankmachine7_cmd_buffer_lookahead_level <= 5'd0;
- litedramcore_bankmachine7_cmd_buffer_lookahead_produce <= 4'd0;
- litedramcore_bankmachine7_cmd_buffer_lookahead_consume <= 4'd0;
- litedramcore_bankmachine7_cmd_buffer_source_valid <= 1'd0;
- litedramcore_bankmachine7_cmd_buffer_source_payload_we <= 1'd0;
- litedramcore_bankmachine7_cmd_buffer_source_payload_addr <= 21'd0;
- litedramcore_bankmachine7_row <= 14'd0;
- litedramcore_bankmachine7_row_opened <= 1'd0;
- litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
- litedramcore_bankmachine7_twtpcon_count <= 3'd0;
- litedramcore_bankmachine7_trccon_ready <= 1'd0;
- litedramcore_bankmachine7_trccon_count <= 3'd0;
- litedramcore_bankmachine7_trascon_ready <= 1'd0;
- litedramcore_bankmachine7_trascon_count <= 3'd0;
- litedramcore_choose_cmd_grant <= 3'd0;
- litedramcore_choose_req_grant <= 3'd0;
- litedramcore_trrdcon_ready <= 1'd0;
- litedramcore_trrdcon_count <= 1'd0;
- litedramcore_tfawcon_ready <= 1'd1;
- litedramcore_tfawcon_window <= 5'd0;
- litedramcore_tccdcon_ready <= 1'd0;
- litedramcore_tccdcon_count <= 1'd0;
- litedramcore_twtrcon_ready <= 1'd0;
- litedramcore_twtrcon_count <= 3'd0;
- litedramcore_time0 <= 5'd0;
- litedramcore_time1 <= 4'd0;
- init_done_storage <= 1'd0;
- init_done_re <= 1'd0;
- init_error_storage <= 1'd0;
- init_error_re <= 1'd0;
- litedramcore_we <= 1'd0;
- litedramcore_refresher_state <= 2'd0;
- litedramcore_bankmachine0_state <= 4'd0;
- litedramcore_bankmachine1_state <= 4'd0;
- litedramcore_bankmachine2_state <= 4'd0;
- litedramcore_bankmachine3_state <= 4'd0;
- litedramcore_bankmachine4_state <= 4'd0;
- litedramcore_bankmachine5_state <= 4'd0;
- litedramcore_bankmachine6_state <= 4'd0;
- litedramcore_bankmachine7_state <= 4'd0;
- litedramcore_multiplexer_state <= 4'd0;
- litedramcore_new_master_wdata_ready0 <= 1'd0;
- litedramcore_new_master_wdata_ready1 <= 1'd0;
- litedramcore_new_master_rdata_valid0 <= 1'd0;
- litedramcore_new_master_rdata_valid1 <= 1'd0;
- litedramcore_new_master_rdata_valid2 <= 1'd0;
- litedramcore_new_master_rdata_valid3 <= 1'd0;
- litedramcore_new_master_rdata_valid4 <= 1'd0;
- litedramcore_new_master_rdata_valid5 <= 1'd0;
- litedramcore_new_master_rdata_valid6 <= 1'd0;
- litedramcore_new_master_rdata_valid7 <= 1'd0;
- litedramcore_new_master_rdata_valid8 <= 1'd0;
- litedramcore_state <= 2'd0;
- end
+ a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dqs_oe_delay_tappeddelayline;
+ a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0;
+ a7ddrphy_dqspattern_o1 <= a7ddrphy_dqspattern_o0;
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip0_value0 <= (a7ddrphy_bitslip0_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip0_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip0_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip0_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip1_value0 <= (a7ddrphy_bitslip1_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip1_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip1_r0 <= {a7ddrphy_dqspattern_o1, a7ddrphy_bitslip1_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip0_value1 <= (a7ddrphy_bitslip0_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip0_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip0_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[2], a7ddrphy_dfi_p3_wrdata_mask[0], a7ddrphy_dfi_p2_wrdata_mask[2], a7ddrphy_dfi_p2_wrdata_mask[0], a7ddrphy_dfi_p1_wrdata_mask[2], a7ddrphy_dfi_p1_wrdata_mask[0], a7ddrphy_dfi_p0_wrdata_mask[2], a7ddrphy_dfi_p0_wrdata_mask[0]}, a7ddrphy_bitslip0_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip1_value1 <= (a7ddrphy_bitslip1_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip1_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip1_r1 <= {{a7ddrphy_dfi_p3_wrdata_mask[3], a7ddrphy_dfi_p3_wrdata_mask[1], a7ddrphy_dfi_p2_wrdata_mask[3], a7ddrphy_dfi_p2_wrdata_mask[1], a7ddrphy_dfi_p1_wrdata_mask[3], a7ddrphy_dfi_p1_wrdata_mask[1], a7ddrphy_dfi_p0_wrdata_mask[3], a7ddrphy_dfi_p0_wrdata_mask[1]}, a7ddrphy_bitslip1_r1[15:8]};
+ a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= a7ddrphy_dq_oe_delay_tappeddelayline;
+ a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0;
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip0_value2 <= (a7ddrphy_bitslip0_value2 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip0_value2 <= 3'd7;
+ end
+ a7ddrphy_bitslip0_r2 <= {{a7ddrphy_dfi_p3_wrdata[16], a7ddrphy_dfi_p3_wrdata[0], a7ddrphy_dfi_p2_wrdata[16], a7ddrphy_dfi_p2_wrdata[0], a7ddrphy_dfi_p1_wrdata[16], a7ddrphy_dfi_p1_wrdata[0], a7ddrphy_dfi_p0_wrdata[16], a7ddrphy_dfi_p0_wrdata[0]}, a7ddrphy_bitslip0_r2[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip0_value3 <= (a7ddrphy_bitslip0_value3 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip0_value3 <= 3'd7;
+ end
+ a7ddrphy_bitslip0_r3 <= {a7ddrphy_bitslip03, a7ddrphy_bitslip0_r3[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip1_value2 <= (a7ddrphy_bitslip1_value2 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip1_value2 <= 3'd7;
+ end
+ a7ddrphy_bitslip1_r2 <= {{a7ddrphy_dfi_p3_wrdata[17], a7ddrphy_dfi_p3_wrdata[1], a7ddrphy_dfi_p2_wrdata[17], a7ddrphy_dfi_p2_wrdata[1], a7ddrphy_dfi_p1_wrdata[17], a7ddrphy_dfi_p1_wrdata[1], a7ddrphy_dfi_p0_wrdata[17], a7ddrphy_dfi_p0_wrdata[1]}, a7ddrphy_bitslip1_r2[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip1_value3 <= (a7ddrphy_bitslip1_value3 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip1_value3 <= 3'd7;
+ end
+ a7ddrphy_bitslip1_r3 <= {a7ddrphy_bitslip13, a7ddrphy_bitslip1_r3[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip2_value0 <= (a7ddrphy_bitslip2_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip2_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip2_r0 <= {{a7ddrphy_dfi_p3_wrdata[18], a7ddrphy_dfi_p3_wrdata[2], a7ddrphy_dfi_p2_wrdata[18], a7ddrphy_dfi_p2_wrdata[2], a7ddrphy_dfi_p1_wrdata[18], a7ddrphy_dfi_p1_wrdata[2], a7ddrphy_dfi_p0_wrdata[18], a7ddrphy_dfi_p0_wrdata[2]}, a7ddrphy_bitslip2_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip2_value1 <= (a7ddrphy_bitslip2_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip2_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip2_r1 <= {a7ddrphy_bitslip21, a7ddrphy_bitslip2_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip3_value0 <= (a7ddrphy_bitslip3_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip3_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip3_r0 <= {{a7ddrphy_dfi_p3_wrdata[19], a7ddrphy_dfi_p3_wrdata[3], a7ddrphy_dfi_p2_wrdata[19], a7ddrphy_dfi_p2_wrdata[3], a7ddrphy_dfi_p1_wrdata[19], a7ddrphy_dfi_p1_wrdata[3], a7ddrphy_dfi_p0_wrdata[19], a7ddrphy_dfi_p0_wrdata[3]}, a7ddrphy_bitslip3_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip3_value1 <= (a7ddrphy_bitslip3_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip3_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip3_r1 <= {a7ddrphy_bitslip31, a7ddrphy_bitslip3_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip4_value0 <= (a7ddrphy_bitslip4_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip4_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip4_r0 <= {{a7ddrphy_dfi_p3_wrdata[20], a7ddrphy_dfi_p3_wrdata[4], a7ddrphy_dfi_p2_wrdata[20], a7ddrphy_dfi_p2_wrdata[4], a7ddrphy_dfi_p1_wrdata[20], a7ddrphy_dfi_p1_wrdata[4], a7ddrphy_dfi_p0_wrdata[20], a7ddrphy_dfi_p0_wrdata[4]}, a7ddrphy_bitslip4_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip4_value1 <= (a7ddrphy_bitslip4_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip4_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip4_r1 <= {a7ddrphy_bitslip41, a7ddrphy_bitslip4_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip5_value0 <= (a7ddrphy_bitslip5_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip5_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip5_r0 <= {{a7ddrphy_dfi_p3_wrdata[21], a7ddrphy_dfi_p3_wrdata[5], a7ddrphy_dfi_p2_wrdata[21], a7ddrphy_dfi_p2_wrdata[5], a7ddrphy_dfi_p1_wrdata[21], a7ddrphy_dfi_p1_wrdata[5], a7ddrphy_dfi_p0_wrdata[21], a7ddrphy_dfi_p0_wrdata[5]}, a7ddrphy_bitslip5_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip5_value1 <= (a7ddrphy_bitslip5_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip5_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip5_r1 <= {a7ddrphy_bitslip51, a7ddrphy_bitslip5_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip6_value0 <= (a7ddrphy_bitslip6_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip6_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip6_r0 <= {{a7ddrphy_dfi_p3_wrdata[22], a7ddrphy_dfi_p3_wrdata[6], a7ddrphy_dfi_p2_wrdata[22], a7ddrphy_dfi_p2_wrdata[6], a7ddrphy_dfi_p1_wrdata[22], a7ddrphy_dfi_p1_wrdata[6], a7ddrphy_dfi_p0_wrdata[22], a7ddrphy_dfi_p0_wrdata[6]}, a7ddrphy_bitslip6_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip6_value1 <= (a7ddrphy_bitslip6_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip6_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip6_r1 <= {a7ddrphy_bitslip61, a7ddrphy_bitslip6_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip7_value0 <= (a7ddrphy_bitslip7_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip7_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip7_r0 <= {{a7ddrphy_dfi_p3_wrdata[23], a7ddrphy_dfi_p3_wrdata[7], a7ddrphy_dfi_p2_wrdata[23], a7ddrphy_dfi_p2_wrdata[7], a7ddrphy_dfi_p1_wrdata[23], a7ddrphy_dfi_p1_wrdata[7], a7ddrphy_dfi_p0_wrdata[23], a7ddrphy_dfi_p0_wrdata[7]}, a7ddrphy_bitslip7_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip7_value1 <= (a7ddrphy_bitslip7_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[0] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip7_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip7_r1 <= {a7ddrphy_bitslip71, a7ddrphy_bitslip7_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip8_value0 <= (a7ddrphy_bitslip8_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip8_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip8_r0 <= {{a7ddrphy_dfi_p3_wrdata[24], a7ddrphy_dfi_p3_wrdata[8], a7ddrphy_dfi_p2_wrdata[24], a7ddrphy_dfi_p2_wrdata[8], a7ddrphy_dfi_p1_wrdata[24], a7ddrphy_dfi_p1_wrdata[8], a7ddrphy_dfi_p0_wrdata[24], a7ddrphy_dfi_p0_wrdata[8]}, a7ddrphy_bitslip8_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip8_value1 <= (a7ddrphy_bitslip8_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip8_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip8_r1 <= {a7ddrphy_bitslip81, a7ddrphy_bitslip8_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip9_value0 <= (a7ddrphy_bitslip9_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip9_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip9_r0 <= {{a7ddrphy_dfi_p3_wrdata[25], a7ddrphy_dfi_p3_wrdata[9], a7ddrphy_dfi_p2_wrdata[25], a7ddrphy_dfi_p2_wrdata[9], a7ddrphy_dfi_p1_wrdata[25], a7ddrphy_dfi_p1_wrdata[9], a7ddrphy_dfi_p0_wrdata[25], a7ddrphy_dfi_p0_wrdata[9]}, a7ddrphy_bitslip9_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip9_value1 <= (a7ddrphy_bitslip9_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip9_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip9_r1 <= {a7ddrphy_bitslip91, a7ddrphy_bitslip9_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip10_value0 <= (a7ddrphy_bitslip10_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip10_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip10_r0 <= {{a7ddrphy_dfi_p3_wrdata[26], a7ddrphy_dfi_p3_wrdata[10], a7ddrphy_dfi_p2_wrdata[26], a7ddrphy_dfi_p2_wrdata[10], a7ddrphy_dfi_p1_wrdata[26], a7ddrphy_dfi_p1_wrdata[10], a7ddrphy_dfi_p0_wrdata[26], a7ddrphy_dfi_p0_wrdata[10]}, a7ddrphy_bitslip10_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip10_value1 <= (a7ddrphy_bitslip10_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip10_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip10_r1 <= {a7ddrphy_bitslip101, a7ddrphy_bitslip10_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip11_value0 <= (a7ddrphy_bitslip11_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip11_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip11_r0 <= {{a7ddrphy_dfi_p3_wrdata[27], a7ddrphy_dfi_p3_wrdata[11], a7ddrphy_dfi_p2_wrdata[27], a7ddrphy_dfi_p2_wrdata[11], a7ddrphy_dfi_p1_wrdata[27], a7ddrphy_dfi_p1_wrdata[11], a7ddrphy_dfi_p0_wrdata[27], a7ddrphy_dfi_p0_wrdata[11]}, a7ddrphy_bitslip11_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip11_value1 <= (a7ddrphy_bitslip11_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip11_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip11_r1 <= {a7ddrphy_bitslip111, a7ddrphy_bitslip11_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip12_value0 <= (a7ddrphy_bitslip12_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip12_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip12_r0 <= {{a7ddrphy_dfi_p3_wrdata[28], a7ddrphy_dfi_p3_wrdata[12], a7ddrphy_dfi_p2_wrdata[28], a7ddrphy_dfi_p2_wrdata[12], a7ddrphy_dfi_p1_wrdata[28], a7ddrphy_dfi_p1_wrdata[12], a7ddrphy_dfi_p0_wrdata[28], a7ddrphy_dfi_p0_wrdata[12]}, a7ddrphy_bitslip12_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip12_value1 <= (a7ddrphy_bitslip12_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip12_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip12_r1 <= {a7ddrphy_bitslip121, a7ddrphy_bitslip12_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip13_value0 <= (a7ddrphy_bitslip13_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip13_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip13_r0 <= {{a7ddrphy_dfi_p3_wrdata[29], a7ddrphy_dfi_p3_wrdata[13], a7ddrphy_dfi_p2_wrdata[29], a7ddrphy_dfi_p2_wrdata[13], a7ddrphy_dfi_p1_wrdata[29], a7ddrphy_dfi_p1_wrdata[13], a7ddrphy_dfi_p0_wrdata[29], a7ddrphy_dfi_p0_wrdata[13]}, a7ddrphy_bitslip13_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip13_value1 <= (a7ddrphy_bitslip13_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip13_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip13_r1 <= {a7ddrphy_bitslip131, a7ddrphy_bitslip13_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip14_value0 <= (a7ddrphy_bitslip14_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip14_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip14_r0 <= {{a7ddrphy_dfi_p3_wrdata[30], a7ddrphy_dfi_p3_wrdata[14], a7ddrphy_dfi_p2_wrdata[30], a7ddrphy_dfi_p2_wrdata[14], a7ddrphy_dfi_p1_wrdata[30], a7ddrphy_dfi_p1_wrdata[14], a7ddrphy_dfi_p0_wrdata[30], a7ddrphy_dfi_p0_wrdata[14]}, a7ddrphy_bitslip14_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip14_value1 <= (a7ddrphy_bitslip14_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip14_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip14_r1 <= {a7ddrphy_bitslip141, a7ddrphy_bitslip14_r1[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip15_value0 <= (a7ddrphy_bitslip15_value0 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_wdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip15_value0 <= 3'd7;
+ end
+ a7ddrphy_bitslip15_r0 <= {{a7ddrphy_dfi_p3_wrdata[31], a7ddrphy_dfi_p3_wrdata[15], a7ddrphy_dfi_p2_wrdata[31], a7ddrphy_dfi_p2_wrdata[15], a7ddrphy_dfi_p1_wrdata[31], a7ddrphy_dfi_p1_wrdata[15], a7ddrphy_dfi_p0_wrdata[31], a7ddrphy_dfi_p0_wrdata[15]}, a7ddrphy_bitslip15_r0[15:8]};
+ if ((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_re)) begin
+ a7ddrphy_bitslip15_value1 <= (a7ddrphy_bitslip15_value1 + 1'd1);
+ end
+ if (((a7ddrphy_dly_sel_storage[1] & a7ddrphy_rdly_dq_bitslip_rst_re) | a7ddrphy_rst_storage)) begin
+ a7ddrphy_bitslip15_value1 <= 3'd7;
+ end
+ a7ddrphy_bitslip15_r1 <= {a7ddrphy_bitslip151, a7ddrphy_bitslip15_r1[15:8]};
+ a7ddrphy_rddata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_rddata_en | a7ddrphy_dfi_p1_rddata_en) | a7ddrphy_dfi_p2_rddata_en) | a7ddrphy_dfi_p3_rddata_en);
+ a7ddrphy_rddata_en_tappeddelayline1 <= a7ddrphy_rddata_en_tappeddelayline0;
+ a7ddrphy_rddata_en_tappeddelayline2 <= a7ddrphy_rddata_en_tappeddelayline1;
+ a7ddrphy_rddata_en_tappeddelayline3 <= a7ddrphy_rddata_en_tappeddelayline2;
+ a7ddrphy_rddata_en_tappeddelayline4 <= a7ddrphy_rddata_en_tappeddelayline3;
+ a7ddrphy_rddata_en_tappeddelayline5 <= a7ddrphy_rddata_en_tappeddelayline4;
+ a7ddrphy_rddata_en_tappeddelayline6 <= a7ddrphy_rddata_en_tappeddelayline5;
+ a7ddrphy_rddata_en_tappeddelayline7 <= a7ddrphy_rddata_en_tappeddelayline6;
+ a7ddrphy_wrdata_en_tappeddelayline0 <= (((a7ddrphy_dfi_p0_wrdata_en | a7ddrphy_dfi_p1_wrdata_en) | a7ddrphy_dfi_p2_wrdata_en) | a7ddrphy_dfi_p3_wrdata_en);
+ a7ddrphy_wrdata_en_tappeddelayline1 <= a7ddrphy_wrdata_en_tappeddelayline0;
+ a7ddrphy_wrdata_en_tappeddelayline2 <= a7ddrphy_wrdata_en_tappeddelayline1;
+ if (litedramcore_csr_dfi_p0_rddata_valid) begin
+ litedramcore_phaseinjector0_rddata_status <= litedramcore_csr_dfi_p0_rddata;
+ end
+ if (litedramcore_csr_dfi_p1_rddata_valid) begin
+ litedramcore_phaseinjector1_rddata_status <= litedramcore_csr_dfi_p1_rddata;
+ end
+ if (litedramcore_csr_dfi_p2_rddata_valid) begin
+ litedramcore_phaseinjector2_rddata_status <= litedramcore_csr_dfi_p2_rddata;
+ end
+ if (litedramcore_csr_dfi_p3_rddata_valid) begin
+ litedramcore_phaseinjector3_rddata_status <= litedramcore_csr_dfi_p3_rddata;
+ end
+ if ((litedramcore_timer_wait & (~litedramcore_timer_done0))) begin
+ litedramcore_timer_count1 <= (litedramcore_timer_count1 - 1'd1);
+ end else begin
+ litedramcore_timer_count1 <= 10'd781;
+ end
+ litedramcore_postponer_req_o <= 1'd0;
+ if (litedramcore_postponer_req_i) begin
+ litedramcore_postponer_count <= (litedramcore_postponer_count - 1'd1);
+ if ((litedramcore_postponer_count == 1'd0)) begin
+ litedramcore_postponer_count <= 1'd0;
+ litedramcore_postponer_req_o <= 1'd1;
+ end
+ end
+ if (litedramcore_sequencer_start0) begin
+ litedramcore_sequencer_count <= 1'd0;
+ end else begin
+ if (litedramcore_sequencer_done1) begin
+ if ((litedramcore_sequencer_count != 1'd0)) begin
+ litedramcore_sequencer_count <= (litedramcore_sequencer_count - 1'd1);
+ end
+ end
+ end
+ litedramcore_cmd_payload_a <= 1'd0;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd0;
+ litedramcore_cmd_payload_we <= 1'd0;
+ litedramcore_sequencer_done1 <= 1'd0;
+ if ((litedramcore_sequencer_start1 & (litedramcore_sequencer_counter == 1'd0))) begin
+ litedramcore_cmd_payload_a <= 11'd1024;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd1;
+ litedramcore_cmd_payload_we <= 1'd1;
+ end
+ if ((litedramcore_sequencer_counter == 2'd3)) begin
+ litedramcore_cmd_payload_a <= 11'd1024;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd1;
+ litedramcore_cmd_payload_ras <= 1'd1;
+ litedramcore_cmd_payload_we <= 1'd0;
+ end
+ if ((litedramcore_sequencer_counter == 6'd35)) begin
+ litedramcore_cmd_payload_a <= 1'd0;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd0;
+ litedramcore_cmd_payload_we <= 1'd0;
+ litedramcore_sequencer_done1 <= 1'd1;
+ end
+ if ((litedramcore_sequencer_counter == 6'd35)) begin
+ litedramcore_sequencer_counter <= 1'd0;
+ end else begin
+ if ((litedramcore_sequencer_counter != 1'd0)) begin
+ litedramcore_sequencer_counter <= (litedramcore_sequencer_counter + 1'd1);
+ end else begin
+ if (litedramcore_sequencer_start1) begin
+ litedramcore_sequencer_counter <= 1'd1;
+ end
+ end
+ end
+ if ((litedramcore_zqcs_timer_wait & (~litedramcore_zqcs_timer_done0))) begin
+ litedramcore_zqcs_timer_count1 <= (litedramcore_zqcs_timer_count1 - 1'd1);
+ end else begin
+ litedramcore_zqcs_timer_count1 <= 27'd99999999;
+ end
+ litedramcore_zqcs_executer_done <= 1'd0;
+ if ((litedramcore_zqcs_executer_start & (litedramcore_zqcs_executer_counter == 1'd0))) begin
+ litedramcore_cmd_payload_a <= 11'd1024;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd1;
+ litedramcore_cmd_payload_we <= 1'd1;
+ end
+ if ((litedramcore_zqcs_executer_counter == 2'd3)) begin
+ litedramcore_cmd_payload_a <= 1'd0;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd0;
+ litedramcore_cmd_payload_we <= 1'd1;
+ end
+ if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
+ litedramcore_cmd_payload_a <= 1'd0;
+ litedramcore_cmd_payload_ba <= 1'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd0;
+ litedramcore_cmd_payload_we <= 1'd0;
+ litedramcore_zqcs_executer_done <= 1'd1;
+ end
+ if ((litedramcore_zqcs_executer_counter == 5'd19)) begin
+ litedramcore_zqcs_executer_counter <= 1'd0;
+ end else begin
+ if ((litedramcore_zqcs_executer_counter != 1'd0)) begin
+ litedramcore_zqcs_executer_counter <= (litedramcore_zqcs_executer_counter + 1'd1);
+ end else begin
+ if (litedramcore_zqcs_executer_start) begin
+ litedramcore_zqcs_executer_counter <= 1'd1;
+ end
+ end
+ end
+ litedramcore_refresher_state <= litedramcore_refresher_next_state;
+ if (litedramcore_bankmachine0_row_close) begin
+ litedramcore_bankmachine0_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine0_row_open) begin
+ litedramcore_bankmachine0_row_opened <= 1'd1;
+ litedramcore_bankmachine0_row <= litedramcore_bankmachine0_source_source_payload_addr[20:7];
+ end
+ end
+ if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin
+ litedramcore_bankmachine0_produce <= (litedramcore_bankmachine0_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine0_do_read) begin
+ litedramcore_bankmachine0_consume <= (litedramcore_bankmachine0_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine0_syncfifo0_we & litedramcore_bankmachine0_syncfifo0_writable) & (~litedramcore_bankmachine0_replace))) begin
+ if ((~litedramcore_bankmachine0_do_read)) begin
+ litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine0_do_read) begin
+ litedramcore_bankmachine0_level <= (litedramcore_bankmachine0_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine0_pipe_valid_source_valid) | litedramcore_bankmachine0_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine0_pipe_valid_source_valid <= litedramcore_bankmachine0_pipe_valid_sink_valid;
+ litedramcore_bankmachine0_pipe_valid_source_first <= litedramcore_bankmachine0_pipe_valid_sink_first;
+ litedramcore_bankmachine0_pipe_valid_source_last <= litedramcore_bankmachine0_pipe_valid_sink_last;
+ litedramcore_bankmachine0_pipe_valid_source_payload_we <= litedramcore_bankmachine0_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine0_pipe_valid_source_payload_addr <= litedramcore_bankmachine0_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine0_twtpcon_valid) begin
+ litedramcore_bankmachine0_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine0_twtpcon_ready)) begin
+ litedramcore_bankmachine0_twtpcon_count <= (litedramcore_bankmachine0_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine0_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine0_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine0_trccon_valid) begin
+ litedramcore_bankmachine0_trccon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine0_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine0_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine0_trccon_ready)) begin
+ litedramcore_bankmachine0_trccon_count <= (litedramcore_bankmachine0_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine0_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine0_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine0_trascon_valid) begin
+ litedramcore_bankmachine0_trascon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_bankmachine0_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine0_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine0_trascon_ready)) begin
+ litedramcore_bankmachine0_trascon_count <= (litedramcore_bankmachine0_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine0_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine0_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine0_state <= litedramcore_bankmachine0_next_state;
+ if (litedramcore_bankmachine1_row_close) begin
+ litedramcore_bankmachine1_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine1_row_open) begin
+ litedramcore_bankmachine1_row_opened <= 1'd1;
+ litedramcore_bankmachine1_row <= litedramcore_bankmachine1_source_source_payload_addr[20:7];
+ end
+ end
+ if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin
+ litedramcore_bankmachine1_produce <= (litedramcore_bankmachine1_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine1_do_read) begin
+ litedramcore_bankmachine1_consume <= (litedramcore_bankmachine1_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine1_syncfifo1_we & litedramcore_bankmachine1_syncfifo1_writable) & (~litedramcore_bankmachine1_replace))) begin
+ if ((~litedramcore_bankmachine1_do_read)) begin
+ litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine1_do_read) begin
+ litedramcore_bankmachine1_level <= (litedramcore_bankmachine1_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine1_pipe_valid_source_valid) | litedramcore_bankmachine1_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine1_pipe_valid_source_valid <= litedramcore_bankmachine1_pipe_valid_sink_valid;
+ litedramcore_bankmachine1_pipe_valid_source_first <= litedramcore_bankmachine1_pipe_valid_sink_first;
+ litedramcore_bankmachine1_pipe_valid_source_last <= litedramcore_bankmachine1_pipe_valid_sink_last;
+ litedramcore_bankmachine1_pipe_valid_source_payload_we <= litedramcore_bankmachine1_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine1_pipe_valid_source_payload_addr <= litedramcore_bankmachine1_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine1_twtpcon_valid) begin
+ litedramcore_bankmachine1_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine1_twtpcon_ready)) begin
+ litedramcore_bankmachine1_twtpcon_count <= (litedramcore_bankmachine1_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine1_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine1_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine1_trccon_valid) begin
+ litedramcore_bankmachine1_trccon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine1_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine1_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine1_trccon_ready)) begin
+ litedramcore_bankmachine1_trccon_count <= (litedramcore_bankmachine1_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine1_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine1_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine1_trascon_valid) begin
+ litedramcore_bankmachine1_trascon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_bankmachine1_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine1_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine1_trascon_ready)) begin
+ litedramcore_bankmachine1_trascon_count <= (litedramcore_bankmachine1_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine1_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine1_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine1_state <= litedramcore_bankmachine1_next_state;
+ if (litedramcore_bankmachine2_row_close) begin
+ litedramcore_bankmachine2_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine2_row_open) begin
+ litedramcore_bankmachine2_row_opened <= 1'd1;
+ litedramcore_bankmachine2_row <= litedramcore_bankmachine2_source_source_payload_addr[20:7];
+ end
+ end
+ if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin
+ litedramcore_bankmachine2_produce <= (litedramcore_bankmachine2_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine2_do_read) begin
+ litedramcore_bankmachine2_consume <= (litedramcore_bankmachine2_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine2_syncfifo2_we & litedramcore_bankmachine2_syncfifo2_writable) & (~litedramcore_bankmachine2_replace))) begin
+ if ((~litedramcore_bankmachine2_do_read)) begin
+ litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine2_do_read) begin
+ litedramcore_bankmachine2_level <= (litedramcore_bankmachine2_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine2_pipe_valid_source_valid) | litedramcore_bankmachine2_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine2_pipe_valid_source_valid <= litedramcore_bankmachine2_pipe_valid_sink_valid;
+ litedramcore_bankmachine2_pipe_valid_source_first <= litedramcore_bankmachine2_pipe_valid_sink_first;
+ litedramcore_bankmachine2_pipe_valid_source_last <= litedramcore_bankmachine2_pipe_valid_sink_last;
+ litedramcore_bankmachine2_pipe_valid_source_payload_we <= litedramcore_bankmachine2_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine2_pipe_valid_source_payload_addr <= litedramcore_bankmachine2_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine2_twtpcon_valid) begin
+ litedramcore_bankmachine2_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine2_twtpcon_ready)) begin
+ litedramcore_bankmachine2_twtpcon_count <= (litedramcore_bankmachine2_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine2_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine2_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine2_trccon_valid) begin
+ litedramcore_bankmachine2_trccon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine2_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine2_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine2_trccon_ready)) begin
+ litedramcore_bankmachine2_trccon_count <= (litedramcore_bankmachine2_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine2_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine2_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine2_trascon_valid) begin
+ litedramcore_bankmachine2_trascon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_bankmachine2_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine2_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine2_trascon_ready)) begin
+ litedramcore_bankmachine2_trascon_count <= (litedramcore_bankmachine2_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine2_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine2_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine2_state <= litedramcore_bankmachine2_next_state;
+ if (litedramcore_bankmachine3_row_close) begin
+ litedramcore_bankmachine3_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine3_row_open) begin
+ litedramcore_bankmachine3_row_opened <= 1'd1;
+ litedramcore_bankmachine3_row <= litedramcore_bankmachine3_source_source_payload_addr[20:7];
+ end
+ end
+ if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin
+ litedramcore_bankmachine3_produce <= (litedramcore_bankmachine3_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine3_do_read) begin
+ litedramcore_bankmachine3_consume <= (litedramcore_bankmachine3_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine3_syncfifo3_we & litedramcore_bankmachine3_syncfifo3_writable) & (~litedramcore_bankmachine3_replace))) begin
+ if ((~litedramcore_bankmachine3_do_read)) begin
+ litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine3_do_read) begin
+ litedramcore_bankmachine3_level <= (litedramcore_bankmachine3_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine3_pipe_valid_source_valid) | litedramcore_bankmachine3_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine3_pipe_valid_source_valid <= litedramcore_bankmachine3_pipe_valid_sink_valid;
+ litedramcore_bankmachine3_pipe_valid_source_first <= litedramcore_bankmachine3_pipe_valid_sink_first;
+ litedramcore_bankmachine3_pipe_valid_source_last <= litedramcore_bankmachine3_pipe_valid_sink_last;
+ litedramcore_bankmachine3_pipe_valid_source_payload_we <= litedramcore_bankmachine3_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine3_pipe_valid_source_payload_addr <= litedramcore_bankmachine3_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine3_twtpcon_valid) begin
+ litedramcore_bankmachine3_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine3_twtpcon_ready)) begin
+ litedramcore_bankmachine3_twtpcon_count <= (litedramcore_bankmachine3_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine3_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine3_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine3_trccon_valid) begin
+ litedramcore_bankmachine3_trccon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine3_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine3_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine3_trccon_ready)) begin
+ litedramcore_bankmachine3_trccon_count <= (litedramcore_bankmachine3_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine3_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine3_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine3_trascon_valid) begin
+ litedramcore_bankmachine3_trascon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_bankmachine3_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine3_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine3_trascon_ready)) begin
+ litedramcore_bankmachine3_trascon_count <= (litedramcore_bankmachine3_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine3_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine3_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine3_state <= litedramcore_bankmachine3_next_state;
+ if (litedramcore_bankmachine4_row_close) begin
+ litedramcore_bankmachine4_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine4_row_open) begin
+ litedramcore_bankmachine4_row_opened <= 1'd1;
+ litedramcore_bankmachine4_row <= litedramcore_bankmachine4_source_source_payload_addr[20:7];
+ end
+ end
+ if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin
+ litedramcore_bankmachine4_produce <= (litedramcore_bankmachine4_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine4_do_read) begin
+ litedramcore_bankmachine4_consume <= (litedramcore_bankmachine4_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine4_syncfifo4_we & litedramcore_bankmachine4_syncfifo4_writable) & (~litedramcore_bankmachine4_replace))) begin
+ if ((~litedramcore_bankmachine4_do_read)) begin
+ litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine4_do_read) begin
+ litedramcore_bankmachine4_level <= (litedramcore_bankmachine4_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine4_pipe_valid_source_valid) | litedramcore_bankmachine4_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine4_pipe_valid_source_valid <= litedramcore_bankmachine4_pipe_valid_sink_valid;
+ litedramcore_bankmachine4_pipe_valid_source_first <= litedramcore_bankmachine4_pipe_valid_sink_first;
+ litedramcore_bankmachine4_pipe_valid_source_last <= litedramcore_bankmachine4_pipe_valid_sink_last;
+ litedramcore_bankmachine4_pipe_valid_source_payload_we <= litedramcore_bankmachine4_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine4_pipe_valid_source_payload_addr <= litedramcore_bankmachine4_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine4_twtpcon_valid) begin
+ litedramcore_bankmachine4_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine4_twtpcon_ready)) begin
+ litedramcore_bankmachine4_twtpcon_count <= (litedramcore_bankmachine4_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine4_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine4_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine4_trccon_valid) begin
+ litedramcore_bankmachine4_trccon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine4_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine4_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine4_trccon_ready)) begin
+ litedramcore_bankmachine4_trccon_count <= (litedramcore_bankmachine4_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine4_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine4_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine4_trascon_valid) begin
+ litedramcore_bankmachine4_trascon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_bankmachine4_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine4_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine4_trascon_ready)) begin
+ litedramcore_bankmachine4_trascon_count <= (litedramcore_bankmachine4_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine4_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine4_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine4_state <= litedramcore_bankmachine4_next_state;
+ if (litedramcore_bankmachine5_row_close) begin
+ litedramcore_bankmachine5_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine5_row_open) begin
+ litedramcore_bankmachine5_row_opened <= 1'd1;
+ litedramcore_bankmachine5_row <= litedramcore_bankmachine5_source_source_payload_addr[20:7];
+ end
+ end
+ if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin
+ litedramcore_bankmachine5_produce <= (litedramcore_bankmachine5_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine5_do_read) begin
+ litedramcore_bankmachine5_consume <= (litedramcore_bankmachine5_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine5_syncfifo5_we & litedramcore_bankmachine5_syncfifo5_writable) & (~litedramcore_bankmachine5_replace))) begin
+ if ((~litedramcore_bankmachine5_do_read)) begin
+ litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine5_do_read) begin
+ litedramcore_bankmachine5_level <= (litedramcore_bankmachine5_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine5_pipe_valid_source_valid) | litedramcore_bankmachine5_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine5_pipe_valid_source_valid <= litedramcore_bankmachine5_pipe_valid_sink_valid;
+ litedramcore_bankmachine5_pipe_valid_source_first <= litedramcore_bankmachine5_pipe_valid_sink_first;
+ litedramcore_bankmachine5_pipe_valid_source_last <= litedramcore_bankmachine5_pipe_valid_sink_last;
+ litedramcore_bankmachine5_pipe_valid_source_payload_we <= litedramcore_bankmachine5_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine5_pipe_valid_source_payload_addr <= litedramcore_bankmachine5_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine5_twtpcon_valid) begin
+ litedramcore_bankmachine5_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine5_twtpcon_ready)) begin
+ litedramcore_bankmachine5_twtpcon_count <= (litedramcore_bankmachine5_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine5_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine5_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine5_trccon_valid) begin
+ litedramcore_bankmachine5_trccon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine5_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine5_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine5_trccon_ready)) begin
+ litedramcore_bankmachine5_trccon_count <= (litedramcore_bankmachine5_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine5_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine5_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine5_trascon_valid) begin
+ litedramcore_bankmachine5_trascon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_bankmachine5_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine5_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine5_trascon_ready)) begin
+ litedramcore_bankmachine5_trascon_count <= (litedramcore_bankmachine5_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine5_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine5_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine5_state <= litedramcore_bankmachine5_next_state;
+ if (litedramcore_bankmachine6_row_close) begin
+ litedramcore_bankmachine6_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine6_row_open) begin
+ litedramcore_bankmachine6_row_opened <= 1'd1;
+ litedramcore_bankmachine6_row <= litedramcore_bankmachine6_source_source_payload_addr[20:7];
+ end
+ end
+ if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin
+ litedramcore_bankmachine6_produce <= (litedramcore_bankmachine6_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine6_do_read) begin
+ litedramcore_bankmachine6_consume <= (litedramcore_bankmachine6_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine6_syncfifo6_we & litedramcore_bankmachine6_syncfifo6_writable) & (~litedramcore_bankmachine6_replace))) begin
+ if ((~litedramcore_bankmachine6_do_read)) begin
+ litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine6_do_read) begin
+ litedramcore_bankmachine6_level <= (litedramcore_bankmachine6_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine6_pipe_valid_source_valid) | litedramcore_bankmachine6_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine6_pipe_valid_source_valid <= litedramcore_bankmachine6_pipe_valid_sink_valid;
+ litedramcore_bankmachine6_pipe_valid_source_first <= litedramcore_bankmachine6_pipe_valid_sink_first;
+ litedramcore_bankmachine6_pipe_valid_source_last <= litedramcore_bankmachine6_pipe_valid_sink_last;
+ litedramcore_bankmachine6_pipe_valid_source_payload_we <= litedramcore_bankmachine6_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine6_pipe_valid_source_payload_addr <= litedramcore_bankmachine6_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine6_twtpcon_valid) begin
+ litedramcore_bankmachine6_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine6_twtpcon_ready)) begin
+ litedramcore_bankmachine6_twtpcon_count <= (litedramcore_bankmachine6_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine6_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine6_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine6_trccon_valid) begin
+ litedramcore_bankmachine6_trccon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine6_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine6_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine6_trccon_ready)) begin
+ litedramcore_bankmachine6_trccon_count <= (litedramcore_bankmachine6_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine6_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine6_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine6_trascon_valid) begin
+ litedramcore_bankmachine6_trascon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_bankmachine6_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine6_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine6_trascon_ready)) begin
+ litedramcore_bankmachine6_trascon_count <= (litedramcore_bankmachine6_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine6_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine6_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine6_state <= litedramcore_bankmachine6_next_state;
+ if (litedramcore_bankmachine7_row_close) begin
+ litedramcore_bankmachine7_row_opened <= 1'd0;
+ end else begin
+ if (litedramcore_bankmachine7_row_open) begin
+ litedramcore_bankmachine7_row_opened <= 1'd1;
+ litedramcore_bankmachine7_row <= litedramcore_bankmachine7_source_source_payload_addr[20:7];
+ end
+ end
+ if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin
+ litedramcore_bankmachine7_produce <= (litedramcore_bankmachine7_produce + 1'd1);
+ end
+ if (litedramcore_bankmachine7_do_read) begin
+ litedramcore_bankmachine7_consume <= (litedramcore_bankmachine7_consume + 1'd1);
+ end
+ if (((litedramcore_bankmachine7_syncfifo7_we & litedramcore_bankmachine7_syncfifo7_writable) & (~litedramcore_bankmachine7_replace))) begin
+ if ((~litedramcore_bankmachine7_do_read)) begin
+ litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level + 1'd1);
+ end
+ end else begin
+ if (litedramcore_bankmachine7_do_read) begin
+ litedramcore_bankmachine7_level <= (litedramcore_bankmachine7_level - 1'd1);
+ end
+ end
+ if (((~litedramcore_bankmachine7_pipe_valid_source_valid) | litedramcore_bankmachine7_pipe_valid_source_ready)) begin
+ litedramcore_bankmachine7_pipe_valid_source_valid <= litedramcore_bankmachine7_pipe_valid_sink_valid;
+ litedramcore_bankmachine7_pipe_valid_source_first <= litedramcore_bankmachine7_pipe_valid_sink_first;
+ litedramcore_bankmachine7_pipe_valid_source_last <= litedramcore_bankmachine7_pipe_valid_sink_last;
+ litedramcore_bankmachine7_pipe_valid_source_payload_we <= litedramcore_bankmachine7_pipe_valid_sink_payload_we;
+ litedramcore_bankmachine7_pipe_valid_source_payload_addr <= litedramcore_bankmachine7_pipe_valid_sink_payload_addr;
+ end
+ if (litedramcore_bankmachine7_twtpcon_valid) begin
+ litedramcore_bankmachine7_twtpcon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine7_twtpcon_ready)) begin
+ litedramcore_bankmachine7_twtpcon_count <= (litedramcore_bankmachine7_twtpcon_count - 1'd1);
+ if ((litedramcore_bankmachine7_twtpcon_count == 1'd1)) begin
+ litedramcore_bankmachine7_twtpcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine7_trccon_valid) begin
+ litedramcore_bankmachine7_trccon_count <= 3'd5;
+ if (1'd0) begin
+ litedramcore_bankmachine7_trccon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine7_trccon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine7_trccon_ready)) begin
+ litedramcore_bankmachine7_trccon_count <= (litedramcore_bankmachine7_trccon_count - 1'd1);
+ if ((litedramcore_bankmachine7_trccon_count == 1'd1)) begin
+ litedramcore_bankmachine7_trccon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_bankmachine7_trascon_valid) begin
+ litedramcore_bankmachine7_trascon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_bankmachine7_trascon_ready <= 1'd1;
+ end else begin
+ litedramcore_bankmachine7_trascon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_bankmachine7_trascon_ready)) begin
+ litedramcore_bankmachine7_trascon_count <= (litedramcore_bankmachine7_trascon_count - 1'd1);
+ if ((litedramcore_bankmachine7_trascon_count == 1'd1)) begin
+ litedramcore_bankmachine7_trascon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_bankmachine7_state <= litedramcore_bankmachine7_next_state;
+ if ((~litedramcore_en0)) begin
+ litedramcore_time0 <= 5'd31;
+ end else begin
+ if ((~litedramcore_max_time0)) begin
+ litedramcore_time0 <= (litedramcore_time0 - 1'd1);
+ end
+ end
+ if ((~litedramcore_en1)) begin
+ litedramcore_time1 <= 4'd15;
+ end else begin
+ if ((~litedramcore_max_time1)) begin
+ litedramcore_time1 <= (litedramcore_time1 - 1'd1);
+ end
+ end
+ if (litedramcore_choose_cmd_ce) begin
+ case (litedramcore_choose_cmd_grant)
+ 1'd0: begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 1'd1: begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 2'd2: begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd4: begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd5: begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd6: begin
+ if (litedramcore_choose_cmd_request[7]) begin
+ litedramcore_choose_cmd_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd7: begin
+ if (litedramcore_choose_cmd_request[0]) begin
+ litedramcore_choose_cmd_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_cmd_request[1]) begin
+ litedramcore_choose_cmd_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_cmd_request[2]) begin
+ litedramcore_choose_cmd_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_cmd_request[3]) begin
+ litedramcore_choose_cmd_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_cmd_request[4]) begin
+ litedramcore_choose_cmd_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_cmd_request[5]) begin
+ litedramcore_choose_cmd_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_cmd_request[6]) begin
+ litedramcore_choose_cmd_grant <= 3'd6;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ endcase
+ end
+ if (litedramcore_choose_req_ce) begin
+ case (litedramcore_choose_req_grant)
+ 1'd0: begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 1'd1: begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 2'd2: begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 2'd3: begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd4: begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd5: begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end else begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd6: begin
+ if (litedramcore_choose_req_request[7]) begin
+ litedramcore_choose_req_grant <= 3'd7;
+ end else begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ 3'd7: begin
+ if (litedramcore_choose_req_request[0]) begin
+ litedramcore_choose_req_grant <= 1'd0;
+ end else begin
+ if (litedramcore_choose_req_request[1]) begin
+ litedramcore_choose_req_grant <= 1'd1;
+ end else begin
+ if (litedramcore_choose_req_request[2]) begin
+ litedramcore_choose_req_grant <= 2'd2;
+ end else begin
+ if (litedramcore_choose_req_request[3]) begin
+ litedramcore_choose_req_grant <= 2'd3;
+ end else begin
+ if (litedramcore_choose_req_request[4]) begin
+ litedramcore_choose_req_grant <= 3'd4;
+ end else begin
+ if (litedramcore_choose_req_request[5]) begin
+ litedramcore_choose_req_grant <= 3'd5;
+ end else begin
+ if (litedramcore_choose_req_request[6]) begin
+ litedramcore_choose_req_grant <= 3'd6;
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ end
+ endcase
+ end
+ litedramcore_dfi_p0_cs_n <= 1'd0;
+ litedramcore_dfi_p0_bank <= array_muxed0;
+ litedramcore_dfi_p0_address <= array_muxed1;
+ litedramcore_dfi_p0_cas_n <= (~array_muxed2);
+ litedramcore_dfi_p0_ras_n <= (~array_muxed3);
+ litedramcore_dfi_p0_we_n <= (~array_muxed4);
+ litedramcore_dfi_p0_rddata_en <= array_muxed5;
+ litedramcore_dfi_p0_wrdata_en <= array_muxed6;
+ litedramcore_dfi_p1_cs_n <= 1'd0;
+ litedramcore_dfi_p1_bank <= array_muxed7;
+ litedramcore_dfi_p1_address <= array_muxed8;
+ litedramcore_dfi_p1_cas_n <= (~array_muxed9);
+ litedramcore_dfi_p1_ras_n <= (~array_muxed10);
+ litedramcore_dfi_p1_we_n <= (~array_muxed11);
+ litedramcore_dfi_p1_rddata_en <= array_muxed12;
+ litedramcore_dfi_p1_wrdata_en <= array_muxed13;
+ litedramcore_dfi_p2_cs_n <= 1'd0;
+ litedramcore_dfi_p2_bank <= array_muxed14;
+ litedramcore_dfi_p2_address <= array_muxed15;
+ litedramcore_dfi_p2_cas_n <= (~array_muxed16);
+ litedramcore_dfi_p2_ras_n <= (~array_muxed17);
+ litedramcore_dfi_p2_we_n <= (~array_muxed18);
+ litedramcore_dfi_p2_rddata_en <= array_muxed19;
+ litedramcore_dfi_p2_wrdata_en <= array_muxed20;
+ litedramcore_dfi_p3_cs_n <= 1'd0;
+ litedramcore_dfi_p3_bank <= array_muxed21;
+ litedramcore_dfi_p3_address <= array_muxed22;
+ litedramcore_dfi_p3_cas_n <= (~array_muxed23);
+ litedramcore_dfi_p3_ras_n <= (~array_muxed24);
+ litedramcore_dfi_p3_we_n <= (~array_muxed25);
+ litedramcore_dfi_p3_rddata_en <= array_muxed26;
+ litedramcore_dfi_p3_wrdata_en <= array_muxed27;
+ if (litedramcore_trrdcon_valid) begin
+ litedramcore_trrdcon_count <= 1'd1;
+ if (1'd0) begin
+ litedramcore_trrdcon_ready <= 1'd1;
+ end else begin
+ litedramcore_trrdcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_trrdcon_ready)) begin
+ litedramcore_trrdcon_count <= (litedramcore_trrdcon_count - 1'd1);
+ if ((litedramcore_trrdcon_count == 1'd1)) begin
+ litedramcore_trrdcon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_tfawcon_window <= {litedramcore_tfawcon_window, litedramcore_tfawcon_valid};
+ if ((litedramcore_tfawcon_count < 3'd4)) begin
+ if ((litedramcore_tfawcon_count == 2'd3)) begin
+ litedramcore_tfawcon_ready <= (~litedramcore_tfawcon_valid);
+ end else begin
+ litedramcore_tfawcon_ready <= 1'd1;
+ end
+ end
+ if (litedramcore_tccdcon_valid) begin
+ litedramcore_tccdcon_count <= 1'd0;
+ if (1'd1) begin
+ litedramcore_tccdcon_ready <= 1'd1;
+ end else begin
+ litedramcore_tccdcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_tccdcon_ready)) begin
+ litedramcore_tccdcon_count <= (litedramcore_tccdcon_count - 1'd1);
+ if ((litedramcore_tccdcon_count == 1'd1)) begin
+ litedramcore_tccdcon_ready <= 1'd1;
+ end
+ end
+ end
+ if (litedramcore_twtrcon_valid) begin
+ litedramcore_twtrcon_count <= 3'd4;
+ if (1'd0) begin
+ litedramcore_twtrcon_ready <= 1'd1;
+ end else begin
+ litedramcore_twtrcon_ready <= 1'd0;
+ end
+ end else begin
+ if ((~litedramcore_twtrcon_ready)) begin
+ litedramcore_twtrcon_count <= (litedramcore_twtrcon_count - 1'd1);
+ if ((litedramcore_twtrcon_count == 1'd1)) begin
+ litedramcore_twtrcon_ready <= 1'd1;
+ end
+ end
+ end
+ litedramcore_multiplexer_state <= litedramcore_multiplexer_next_state;
+ litedramcore_new_master_wdata_ready0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_wdata_ready)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_wdata_ready)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_wdata_ready)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_wdata_ready)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_wdata_ready)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_wdata_ready)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_wdata_ready)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_wdata_ready));
+ litedramcore_new_master_wdata_ready1 <= litedramcore_new_master_wdata_ready0;
+ litedramcore_new_master_rdata_valid0 <= ((((((((1'd0 | ((litedramcore_roundrobin0_grant == 1'd0) & litedramcore_interface_bank0_rdata_valid)) | ((litedramcore_roundrobin1_grant == 1'd0) & litedramcore_interface_bank1_rdata_valid)) | ((litedramcore_roundrobin2_grant == 1'd0) & litedramcore_interface_bank2_rdata_valid)) | ((litedramcore_roundrobin3_grant == 1'd0) & litedramcore_interface_bank3_rdata_valid)) | ((litedramcore_roundrobin4_grant == 1'd0) & litedramcore_interface_bank4_rdata_valid)) | ((litedramcore_roundrobin5_grant == 1'd0) & litedramcore_interface_bank5_rdata_valid)) | ((litedramcore_roundrobin6_grant == 1'd0) & litedramcore_interface_bank6_rdata_valid)) | ((litedramcore_roundrobin7_grant == 1'd0) & litedramcore_interface_bank7_rdata_valid));
+ litedramcore_new_master_rdata_valid1 <= litedramcore_new_master_rdata_valid0;
+ litedramcore_new_master_rdata_valid2 <= litedramcore_new_master_rdata_valid1;
+ litedramcore_new_master_rdata_valid3 <= litedramcore_new_master_rdata_valid2;
+ litedramcore_new_master_rdata_valid4 <= litedramcore_new_master_rdata_valid3;
+ litedramcore_new_master_rdata_valid5 <= litedramcore_new_master_rdata_valid4;
+ litedramcore_new_master_rdata_valid6 <= litedramcore_new_master_rdata_valid5;
+ litedramcore_new_master_rdata_valid7 <= litedramcore_new_master_rdata_valid6;
+ litedramcore_new_master_rdata_valid8 <= litedramcore_new_master_rdata_valid7;
+ litedramcore_state <= litedramcore_next_state;
+ if (litedramcore_dat_w_next_value_ce0) begin
+ litedramcore_dat_w <= litedramcore_dat_w_next_value0;
+ end
+ if (litedramcore_adr_next_value_ce1) begin
+ litedramcore_adr <= litedramcore_adr_next_value1;
+ end
+ if (litedramcore_we_next_value_ce2) begin
+ litedramcore_we <= litedramcore_we_next_value2;
+ end
+ interface0_bank_bus_dat_r <= 1'd0;
+ if (csrbank0_sel) begin
+ case (interface0_bank_bus_adr[8:0])
+ 1'd0: begin
+ interface0_bank_bus_dat_r <= csrbank0_init_done0_w;
+ end
+ 1'd1: begin
+ interface0_bank_bus_dat_r <= csrbank0_init_error0_w;
+ end
+ endcase
+ end
+ if (csrbank0_init_done0_re) begin
+ init_done_storage <= csrbank0_init_done0_r;
+ end
+ init_done_re <= csrbank0_init_done0_re;
+ if (csrbank0_init_error0_re) begin
+ init_error_storage <= csrbank0_init_error0_r;
+ end
+ init_error_re <= csrbank0_init_error0_re;
+ interface1_bank_bus_dat_r <= 1'd0;
+ if (csrbank1_sel) begin
+ case (interface1_bank_bus_adr[8:0])
+ 1'd0: begin
+ interface1_bank_bus_dat_r <= csrbank1_rst0_w;
+ end
+ 1'd1: begin
+ interface1_bank_bus_dat_r <= csrbank1_dly_sel0_w;
+ end
+ 2'd2: begin
+ interface1_bank_bus_dat_r <= csrbank1_half_sys8x_taps0_w;
+ end
+ 2'd3: begin
+ interface1_bank_bus_dat_r <= csrbank1_wlevel_en0_w;
+ end
+ 3'd4: begin
+ interface1_bank_bus_dat_r <= a7ddrphy_wlevel_strobe_w;
+ end
+ 3'd5: begin
+ interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_rst_w;
+ end
+ 3'd6: begin
+ interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_inc_w;
+ end
+ 3'd7: begin
+ interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_rst_w;
+ end
+ 4'd8: begin
+ interface1_bank_bus_dat_r <= a7ddrphy_rdly_dq_bitslip_w;
+ end
+ 4'd9: begin
+ interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_rst_w;
+ end
+ 4'd10: begin
+ interface1_bank_bus_dat_r <= a7ddrphy_wdly_dq_bitslip_w;
+ end
+ 4'd11: begin
+ interface1_bank_bus_dat_r <= csrbank1_rdphase0_w;
+ end
+ 4'd12: begin
+ interface1_bank_bus_dat_r <= csrbank1_wrphase0_w;
+ end
+ endcase
+ end
+ if (csrbank1_rst0_re) begin
+ a7ddrphy_rst_storage <= csrbank1_rst0_r;
+ end
+ a7ddrphy_rst_re <= csrbank1_rst0_re;
+ if (csrbank1_dly_sel0_re) begin
+ a7ddrphy_dly_sel_storage[1:0] <= csrbank1_dly_sel0_r;
+ end
+ a7ddrphy_dly_sel_re <= csrbank1_dly_sel0_re;
+ if (csrbank1_half_sys8x_taps0_re) begin
+ a7ddrphy_half_sys8x_taps_storage[4:0] <= csrbank1_half_sys8x_taps0_r;
+ end
+ a7ddrphy_half_sys8x_taps_re <= csrbank1_half_sys8x_taps0_re;
+ if (csrbank1_wlevel_en0_re) begin
+ a7ddrphy_wlevel_en_storage <= csrbank1_wlevel_en0_r;
+ end
+ a7ddrphy_wlevel_en_re <= csrbank1_wlevel_en0_re;
+ if (csrbank1_rdphase0_re) begin
+ a7ddrphy_rdphase_storage[1:0] <= csrbank1_rdphase0_r;
+ end
+ a7ddrphy_rdphase_re <= csrbank1_rdphase0_re;
+ if (csrbank1_wrphase0_re) begin
+ a7ddrphy_wrphase_storage[1:0] <= csrbank1_wrphase0_r;
+ end
+ a7ddrphy_wrphase_re <= csrbank1_wrphase0_re;
+ interface2_bank_bus_dat_r <= 1'd0;
+ if (csrbank2_sel) begin
+ case (interface2_bank_bus_adr[8:0])
+ 1'd0: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_control0_w;
+ end
+ 1'd1: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_command0_w;
+ end
+ 2'd2: begin
+ interface2_bank_bus_dat_r <= litedramcore_phaseinjector0_command_issue_w;
+ end
+ 2'd3: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_address0_w;
+ end
+ 3'd4: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_baddress0_w;
+ end
+ 3'd5: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_wrdata0_w;
+ end
+ 3'd6: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi0_rddata_w;
+ end
+ 3'd7: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_command0_w;
+ end
+ 4'd8: begin
+ interface2_bank_bus_dat_r <= litedramcore_phaseinjector1_command_issue_w;
+ end
+ 4'd9: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_address0_w;
+ end
+ 4'd10: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_baddress0_w;
+ end
+ 4'd11: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_wrdata0_w;
+ end
+ 4'd12: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi1_rddata_w;
+ end
+ 4'd13: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_command0_w;
+ end
+ 4'd14: begin
+ interface2_bank_bus_dat_r <= litedramcore_phaseinjector2_command_issue_w;
+ end
+ 4'd15: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_address0_w;
+ end
+ 5'd16: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_baddress0_w;
+ end
+ 5'd17: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_wrdata0_w;
+ end
+ 5'd18: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi2_rddata_w;
+ end
+ 5'd19: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_command0_w;
+ end
+ 5'd20: begin
+ interface2_bank_bus_dat_r <= litedramcore_phaseinjector3_command_issue_w;
+ end
+ 5'd21: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_address0_w;
+ end
+ 5'd22: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_baddress0_w;
+ end
+ 5'd23: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_wrdata0_w;
+ end
+ 5'd24: begin
+ interface2_bank_bus_dat_r <= csrbank2_dfii_pi3_rddata_w;
+ end
+ endcase
+ end
+ if (csrbank2_dfii_control0_re) begin
+ litedramcore_storage[3:0] <= csrbank2_dfii_control0_r;
+ end
+ litedramcore_re <= csrbank2_dfii_control0_re;
+ if (csrbank2_dfii_pi0_command0_re) begin
+ litedramcore_phaseinjector0_command_storage[5:0] <= csrbank2_dfii_pi0_command0_r;
+ end
+ litedramcore_phaseinjector0_command_re <= csrbank2_dfii_pi0_command0_re;
+ if (csrbank2_dfii_pi0_address0_re) begin
+ litedramcore_phaseinjector0_address_storage[13:0] <= csrbank2_dfii_pi0_address0_r;
+ end
+ litedramcore_phaseinjector0_address_re <= csrbank2_dfii_pi0_address0_re;
+ if (csrbank2_dfii_pi0_baddress0_re) begin
+ litedramcore_phaseinjector0_baddress_storage[2:0] <= csrbank2_dfii_pi0_baddress0_r;
+ end
+ litedramcore_phaseinjector0_baddress_re <= csrbank2_dfii_pi0_baddress0_re;
+ if (csrbank2_dfii_pi0_wrdata0_re) begin
+ litedramcore_phaseinjector0_wrdata_storage[31:0] <= csrbank2_dfii_pi0_wrdata0_r;
+ end
+ litedramcore_phaseinjector0_wrdata_re <= csrbank2_dfii_pi0_wrdata0_re;
+ litedramcore_phaseinjector0_rddata_re <= csrbank2_dfii_pi0_rddata_re;
+ if (csrbank2_dfii_pi1_command0_re) begin
+ litedramcore_phaseinjector1_command_storage[5:0] <= csrbank2_dfii_pi1_command0_r;
+ end
+ litedramcore_phaseinjector1_command_re <= csrbank2_dfii_pi1_command0_re;
+ if (csrbank2_dfii_pi1_address0_re) begin
+ litedramcore_phaseinjector1_address_storage[13:0] <= csrbank2_dfii_pi1_address0_r;
+ end
+ litedramcore_phaseinjector1_address_re <= csrbank2_dfii_pi1_address0_re;
+ if (csrbank2_dfii_pi1_baddress0_re) begin
+ litedramcore_phaseinjector1_baddress_storage[2:0] <= csrbank2_dfii_pi1_baddress0_r;
+ end
+ litedramcore_phaseinjector1_baddress_re <= csrbank2_dfii_pi1_baddress0_re;
+ if (csrbank2_dfii_pi1_wrdata0_re) begin
+ litedramcore_phaseinjector1_wrdata_storage[31:0] <= csrbank2_dfii_pi1_wrdata0_r;
+ end
+ litedramcore_phaseinjector1_wrdata_re <= csrbank2_dfii_pi1_wrdata0_re;
+ litedramcore_phaseinjector1_rddata_re <= csrbank2_dfii_pi1_rddata_re;
+ if (csrbank2_dfii_pi2_command0_re) begin
+ litedramcore_phaseinjector2_command_storage[5:0] <= csrbank2_dfii_pi2_command0_r;
+ end
+ litedramcore_phaseinjector2_command_re <= csrbank2_dfii_pi2_command0_re;
+ if (csrbank2_dfii_pi2_address0_re) begin
+ litedramcore_phaseinjector2_address_storage[13:0] <= csrbank2_dfii_pi2_address0_r;
+ end
+ litedramcore_phaseinjector2_address_re <= csrbank2_dfii_pi2_address0_re;
+ if (csrbank2_dfii_pi2_baddress0_re) begin
+ litedramcore_phaseinjector2_baddress_storage[2:0] <= csrbank2_dfii_pi2_baddress0_r;
+ end
+ litedramcore_phaseinjector2_baddress_re <= csrbank2_dfii_pi2_baddress0_re;
+ if (csrbank2_dfii_pi2_wrdata0_re) begin
+ litedramcore_phaseinjector2_wrdata_storage[31:0] <= csrbank2_dfii_pi2_wrdata0_r;
+ end
+ litedramcore_phaseinjector2_wrdata_re <= csrbank2_dfii_pi2_wrdata0_re;
+ litedramcore_phaseinjector2_rddata_re <= csrbank2_dfii_pi2_rddata_re;
+ if (csrbank2_dfii_pi3_command0_re) begin
+ litedramcore_phaseinjector3_command_storage[5:0] <= csrbank2_dfii_pi3_command0_r;
+ end
+ litedramcore_phaseinjector3_command_re <= csrbank2_dfii_pi3_command0_re;
+ if (csrbank2_dfii_pi3_address0_re) begin
+ litedramcore_phaseinjector3_address_storage[13:0] <= csrbank2_dfii_pi3_address0_r;
+ end
+ litedramcore_phaseinjector3_address_re <= csrbank2_dfii_pi3_address0_re;
+ if (csrbank2_dfii_pi3_baddress0_re) begin
+ litedramcore_phaseinjector3_baddress_storage[2:0] <= csrbank2_dfii_pi3_baddress0_r;
+ end
+ litedramcore_phaseinjector3_baddress_re <= csrbank2_dfii_pi3_baddress0_re;
+ if (csrbank2_dfii_pi3_wrdata0_re) begin
+ litedramcore_phaseinjector3_wrdata_storage[31:0] <= csrbank2_dfii_pi3_wrdata0_r;
+ end
+ litedramcore_phaseinjector3_wrdata_re <= csrbank2_dfii_pi3_wrdata0_re;
+ litedramcore_phaseinjector3_rddata_re <= csrbank2_dfii_pi3_rddata_re;
+ if (sys_rst) begin
+ a7ddrphy_rst_storage <= 1'd0;
+ a7ddrphy_rst_re <= 1'd0;
+ a7ddrphy_dly_sel_storage <= 2'd0;
+ a7ddrphy_dly_sel_re <= 1'd0;
+ a7ddrphy_half_sys8x_taps_storage <= 5'd8;
+ a7ddrphy_half_sys8x_taps_re <= 1'd0;
+ a7ddrphy_wlevel_en_storage <= 1'd0;
+ a7ddrphy_wlevel_en_re <= 1'd0;
+ a7ddrphy_rdphase_storage <= 2'd2;
+ a7ddrphy_rdphase_re <= 1'd0;
+ a7ddrphy_wrphase_storage <= 2'd3;
+ a7ddrphy_wrphase_re <= 1'd0;
+ a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
+ a7ddrphy_dqs_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
+ a7ddrphy_dqspattern_o1 <= 8'd0;
+ a7ddrphy_bitslip0_value0 <= 3'd7;
+ a7ddrphy_bitslip1_value0 <= 3'd7;
+ a7ddrphy_bitslip0_value1 <= 3'd7;
+ a7ddrphy_bitslip1_value1 <= 3'd7;
+ a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline0 <= 1'd0;
+ a7ddrphy_dq_oe_delay_tappeddelayline_tappeddelayline1 <= 1'd0;
+ a7ddrphy_bitslip0_value2 <= 3'd7;
+ a7ddrphy_bitslip0_value3 <= 3'd7;
+ a7ddrphy_bitslip1_value2 <= 3'd7;
+ a7ddrphy_bitslip1_value3 <= 3'd7;
+ a7ddrphy_bitslip2_value0 <= 3'd7;
+ a7ddrphy_bitslip2_value1 <= 3'd7;
+ a7ddrphy_bitslip3_value0 <= 3'd7;
+ a7ddrphy_bitslip3_value1 <= 3'd7;
+ a7ddrphy_bitslip4_value0 <= 3'd7;
+ a7ddrphy_bitslip4_value1 <= 3'd7;
+ a7ddrphy_bitslip5_value0 <= 3'd7;
+ a7ddrphy_bitslip5_value1 <= 3'd7;
+ a7ddrphy_bitslip6_value0 <= 3'd7;
+ a7ddrphy_bitslip6_value1 <= 3'd7;
+ a7ddrphy_bitslip7_value0 <= 3'd7;
+ a7ddrphy_bitslip7_value1 <= 3'd7;
+ a7ddrphy_bitslip8_value0 <= 3'd7;
+ a7ddrphy_bitslip8_value1 <= 3'd7;
+ a7ddrphy_bitslip9_value0 <= 3'd7;
+ a7ddrphy_bitslip9_value1 <= 3'd7;
+ a7ddrphy_bitslip10_value0 <= 3'd7;
+ a7ddrphy_bitslip10_value1 <= 3'd7;
+ a7ddrphy_bitslip11_value0 <= 3'd7;
+ a7ddrphy_bitslip11_value1 <= 3'd7;
+ a7ddrphy_bitslip12_value0 <= 3'd7;
+ a7ddrphy_bitslip12_value1 <= 3'd7;
+ a7ddrphy_bitslip13_value0 <= 3'd7;
+ a7ddrphy_bitslip13_value1 <= 3'd7;
+ a7ddrphy_bitslip14_value0 <= 3'd7;
+ a7ddrphy_bitslip14_value1 <= 3'd7;
+ a7ddrphy_bitslip15_value0 <= 3'd7;
+ a7ddrphy_bitslip15_value1 <= 3'd7;
+ a7ddrphy_rddata_en_tappeddelayline0 <= 1'd0;
+ a7ddrphy_rddata_en_tappeddelayline1 <= 1'd0;
+ a7ddrphy_rddata_en_tappeddelayline2 <= 1'd0;
+ a7ddrphy_rddata_en_tappeddelayline3 <= 1'd0;
+ a7ddrphy_rddata_en_tappeddelayline4 <= 1'd0;
+ a7ddrphy_rddata_en_tappeddelayline5 <= 1'd0;
+ a7ddrphy_rddata_en_tappeddelayline6 <= 1'd0;
+ a7ddrphy_rddata_en_tappeddelayline7 <= 1'd0;
+ a7ddrphy_wrdata_en_tappeddelayline0 <= 1'd0;
+ a7ddrphy_wrdata_en_tappeddelayline1 <= 1'd0;
+ a7ddrphy_wrdata_en_tappeddelayline2 <= 1'd0;
+ litedramcore_storage <= 4'd1;
+ litedramcore_re <= 1'd0;
+ litedramcore_phaseinjector0_command_storage <= 6'd0;
+ litedramcore_phaseinjector0_command_re <= 1'd0;
+ litedramcore_phaseinjector0_address_re <= 1'd0;
+ litedramcore_phaseinjector0_baddress_re <= 1'd0;
+ litedramcore_phaseinjector0_wrdata_re <= 1'd0;
+ litedramcore_phaseinjector0_rddata_status <= 32'd0;
+ litedramcore_phaseinjector0_rddata_re <= 1'd0;
+ litedramcore_phaseinjector1_command_storage <= 6'd0;
+ litedramcore_phaseinjector1_command_re <= 1'd0;
+ litedramcore_phaseinjector1_address_re <= 1'd0;
+ litedramcore_phaseinjector1_baddress_re <= 1'd0;
+ litedramcore_phaseinjector1_wrdata_re <= 1'd0;
+ litedramcore_phaseinjector1_rddata_status <= 32'd0;
+ litedramcore_phaseinjector1_rddata_re <= 1'd0;
+ litedramcore_phaseinjector2_command_storage <= 6'd0;
+ litedramcore_phaseinjector2_command_re <= 1'd0;
+ litedramcore_phaseinjector2_address_re <= 1'd0;
+ litedramcore_phaseinjector2_baddress_re <= 1'd0;
+ litedramcore_phaseinjector2_wrdata_re <= 1'd0;
+ litedramcore_phaseinjector2_rddata_status <= 32'd0;
+ litedramcore_phaseinjector2_rddata_re <= 1'd0;
+ litedramcore_phaseinjector3_command_storage <= 6'd0;
+ litedramcore_phaseinjector3_command_re <= 1'd0;
+ litedramcore_phaseinjector3_address_re <= 1'd0;
+ litedramcore_phaseinjector3_baddress_re <= 1'd0;
+ litedramcore_phaseinjector3_wrdata_re <= 1'd0;
+ litedramcore_phaseinjector3_rddata_status <= 32'd0;
+ litedramcore_phaseinjector3_rddata_re <= 1'd0;
+ litedramcore_dfi_p0_address <= 14'd0;
+ litedramcore_dfi_p0_bank <= 3'd0;
+ litedramcore_dfi_p0_cas_n <= 1'd1;
+ litedramcore_dfi_p0_cs_n <= 1'd1;
+ litedramcore_dfi_p0_ras_n <= 1'd1;
+ litedramcore_dfi_p0_we_n <= 1'd1;
+ litedramcore_dfi_p0_wrdata_en <= 1'd0;
+ litedramcore_dfi_p0_rddata_en <= 1'd0;
+ litedramcore_dfi_p1_address <= 14'd0;
+ litedramcore_dfi_p1_bank <= 3'd0;
+ litedramcore_dfi_p1_cas_n <= 1'd1;
+ litedramcore_dfi_p1_cs_n <= 1'd1;
+ litedramcore_dfi_p1_ras_n <= 1'd1;
+ litedramcore_dfi_p1_we_n <= 1'd1;
+ litedramcore_dfi_p1_wrdata_en <= 1'd0;
+ litedramcore_dfi_p1_rddata_en <= 1'd0;
+ litedramcore_dfi_p2_address <= 14'd0;
+ litedramcore_dfi_p2_bank <= 3'd0;
+ litedramcore_dfi_p2_cas_n <= 1'd1;
+ litedramcore_dfi_p2_cs_n <= 1'd1;
+ litedramcore_dfi_p2_ras_n <= 1'd1;
+ litedramcore_dfi_p2_we_n <= 1'd1;
+ litedramcore_dfi_p2_wrdata_en <= 1'd0;
+ litedramcore_dfi_p2_rddata_en <= 1'd0;
+ litedramcore_dfi_p3_address <= 14'd0;
+ litedramcore_dfi_p3_bank <= 3'd0;
+ litedramcore_dfi_p3_cas_n <= 1'd1;
+ litedramcore_dfi_p3_cs_n <= 1'd1;
+ litedramcore_dfi_p3_ras_n <= 1'd1;
+ litedramcore_dfi_p3_we_n <= 1'd1;
+ litedramcore_dfi_p3_wrdata_en <= 1'd0;
+ litedramcore_dfi_p3_rddata_en <= 1'd0;
+ litedramcore_cmd_payload_a <= 14'd0;
+ litedramcore_cmd_payload_ba <= 3'd0;
+ litedramcore_cmd_payload_cas <= 1'd0;
+ litedramcore_cmd_payload_ras <= 1'd0;
+ litedramcore_cmd_payload_we <= 1'd0;
+ litedramcore_timer_count1 <= 10'd781;
+ litedramcore_postponer_req_o <= 1'd0;
+ litedramcore_postponer_count <= 1'd0;
+ litedramcore_sequencer_done1 <= 1'd0;
+ litedramcore_sequencer_counter <= 6'd0;
+ litedramcore_sequencer_count <= 1'd0;
+ litedramcore_zqcs_timer_count1 <= 27'd99999999;
+ litedramcore_zqcs_executer_done <= 1'd0;
+ litedramcore_zqcs_executer_counter <= 5'd0;
+ litedramcore_bankmachine0_level <= 5'd0;
+ litedramcore_bankmachine0_produce <= 4'd0;
+ litedramcore_bankmachine0_consume <= 4'd0;
+ litedramcore_bankmachine0_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine0_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine0_pipe_valid_source_payload_addr <= 21'd0;
+ litedramcore_bankmachine0_row <= 14'd0;
+ litedramcore_bankmachine0_row_opened <= 1'd0;
+ litedramcore_bankmachine0_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine0_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine0_trccon_ready <= 1'd0;
+ litedramcore_bankmachine0_trccon_count <= 3'd0;
+ litedramcore_bankmachine0_trascon_ready <= 1'd0;
+ litedramcore_bankmachine0_trascon_count <= 3'd0;
+ litedramcore_bankmachine1_level <= 5'd0;
+ litedramcore_bankmachine1_produce <= 4'd0;
+ litedramcore_bankmachine1_consume <= 4'd0;
+ litedramcore_bankmachine1_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine1_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine1_pipe_valid_source_payload_addr <= 21'd0;
+ litedramcore_bankmachine1_row <= 14'd0;
+ litedramcore_bankmachine1_row_opened <= 1'd0;
+ litedramcore_bankmachine1_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine1_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine1_trccon_ready <= 1'd0;
+ litedramcore_bankmachine1_trccon_count <= 3'd0;
+ litedramcore_bankmachine1_trascon_ready <= 1'd0;
+ litedramcore_bankmachine1_trascon_count <= 3'd0;
+ litedramcore_bankmachine2_level <= 5'd0;
+ litedramcore_bankmachine2_produce <= 4'd0;
+ litedramcore_bankmachine2_consume <= 4'd0;
+ litedramcore_bankmachine2_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine2_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine2_pipe_valid_source_payload_addr <= 21'd0;
+ litedramcore_bankmachine2_row <= 14'd0;
+ litedramcore_bankmachine2_row_opened <= 1'd0;
+ litedramcore_bankmachine2_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine2_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine2_trccon_ready <= 1'd0;
+ litedramcore_bankmachine2_trccon_count <= 3'd0;
+ litedramcore_bankmachine2_trascon_ready <= 1'd0;
+ litedramcore_bankmachine2_trascon_count <= 3'd0;
+ litedramcore_bankmachine3_level <= 5'd0;
+ litedramcore_bankmachine3_produce <= 4'd0;
+ litedramcore_bankmachine3_consume <= 4'd0;
+ litedramcore_bankmachine3_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine3_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine3_pipe_valid_source_payload_addr <= 21'd0;
+ litedramcore_bankmachine3_row <= 14'd0;
+ litedramcore_bankmachine3_row_opened <= 1'd0;
+ litedramcore_bankmachine3_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine3_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine3_trccon_ready <= 1'd0;
+ litedramcore_bankmachine3_trccon_count <= 3'd0;
+ litedramcore_bankmachine3_trascon_ready <= 1'd0;
+ litedramcore_bankmachine3_trascon_count <= 3'd0;
+ litedramcore_bankmachine4_level <= 5'd0;
+ litedramcore_bankmachine4_produce <= 4'd0;
+ litedramcore_bankmachine4_consume <= 4'd0;
+ litedramcore_bankmachine4_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine4_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine4_pipe_valid_source_payload_addr <= 21'd0;
+ litedramcore_bankmachine4_row <= 14'd0;
+ litedramcore_bankmachine4_row_opened <= 1'd0;
+ litedramcore_bankmachine4_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine4_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine4_trccon_ready <= 1'd0;
+ litedramcore_bankmachine4_trccon_count <= 3'd0;
+ litedramcore_bankmachine4_trascon_ready <= 1'd0;
+ litedramcore_bankmachine4_trascon_count <= 3'd0;
+ litedramcore_bankmachine5_level <= 5'd0;
+ litedramcore_bankmachine5_produce <= 4'd0;
+ litedramcore_bankmachine5_consume <= 4'd0;
+ litedramcore_bankmachine5_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine5_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine5_pipe_valid_source_payload_addr <= 21'd0;
+ litedramcore_bankmachine5_row <= 14'd0;
+ litedramcore_bankmachine5_row_opened <= 1'd0;
+ litedramcore_bankmachine5_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine5_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine5_trccon_ready <= 1'd0;
+ litedramcore_bankmachine5_trccon_count <= 3'd0;
+ litedramcore_bankmachine5_trascon_ready <= 1'd0;
+ litedramcore_bankmachine5_trascon_count <= 3'd0;
+ litedramcore_bankmachine6_level <= 5'd0;
+ litedramcore_bankmachine6_produce <= 4'd0;
+ litedramcore_bankmachine6_consume <= 4'd0;
+ litedramcore_bankmachine6_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine6_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine6_pipe_valid_source_payload_addr <= 21'd0;
+ litedramcore_bankmachine6_row <= 14'd0;
+ litedramcore_bankmachine6_row_opened <= 1'd0;
+ litedramcore_bankmachine6_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine6_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine6_trccon_ready <= 1'd0;
+ litedramcore_bankmachine6_trccon_count <= 3'd0;
+ litedramcore_bankmachine6_trascon_ready <= 1'd0;
+ litedramcore_bankmachine6_trascon_count <= 3'd0;
+ litedramcore_bankmachine7_level <= 5'd0;
+ litedramcore_bankmachine7_produce <= 4'd0;
+ litedramcore_bankmachine7_consume <= 4'd0;
+ litedramcore_bankmachine7_pipe_valid_source_valid <= 1'd0;
+ litedramcore_bankmachine7_pipe_valid_source_payload_we <= 1'd0;
+ litedramcore_bankmachine7_pipe_valid_source_payload_addr <= 21'd0;
+ litedramcore_bankmachine7_row <= 14'd0;
+ litedramcore_bankmachine7_row_opened <= 1'd0;
+ litedramcore_bankmachine7_twtpcon_ready <= 1'd0;
+ litedramcore_bankmachine7_twtpcon_count <= 3'd0;
+ litedramcore_bankmachine7_trccon_ready <= 1'd0;
+ litedramcore_bankmachine7_trccon_count <= 3'd0;
+ litedramcore_bankmachine7_trascon_ready <= 1'd0;
+ litedramcore_bankmachine7_trascon_count <= 3'd0;
+ litedramcore_choose_cmd_grant <= 3'd0;
+ litedramcore_choose_req_grant <= 3'd0;
+ litedramcore_trrdcon_ready <= 1'd0;
+ litedramcore_trrdcon_count <= 1'd0;
+ litedramcore_tfawcon_ready <= 1'd1;
+ litedramcore_tfawcon_window <= 5'd0;
+ litedramcore_tccdcon_ready <= 1'd0;
+ litedramcore_tccdcon_count <= 1'd0;
+ litedramcore_twtrcon_ready <= 1'd0;
+ litedramcore_twtrcon_count <= 3'd0;
+ litedramcore_time0 <= 5'd0;
+ litedramcore_time1 <= 4'd0;
+ init_done_storage <= 1'd0;
+ init_done_re <= 1'd0;
+ init_error_storage <= 1'd0;
+ init_error_re <= 1'd0;
+ litedramcore_we <= 1'd0;
+ litedramcore_refresher_state <= 2'd0;
+ litedramcore_bankmachine0_state <= 4'd0;
+ litedramcore_bankmachine1_state <= 4'd0;
+ litedramcore_bankmachine2_state <= 4'd0;
+ litedramcore_bankmachine3_state <= 4'd0;
+ litedramcore_bankmachine4_state <= 4'd0;
+ litedramcore_bankmachine5_state <= 4'd0;
+ litedramcore_bankmachine6_state <= 4'd0;
+ litedramcore_bankmachine7_state <= 4'd0;
+ litedramcore_multiplexer_state <= 4'd0;
+ litedramcore_new_master_wdata_ready0 <= 1'd0;
+ litedramcore_new_master_wdata_ready1 <= 1'd0;
+ litedramcore_new_master_rdata_valid0 <= 1'd0;
+ litedramcore_new_master_rdata_valid1 <= 1'd0;
+ litedramcore_new_master_rdata_valid2 <= 1'd0;
+ litedramcore_new_master_rdata_valid3 <= 1'd0;
+ litedramcore_new_master_rdata_valid4 <= 1'd0;
+ litedramcore_new_master_rdata_valid5 <= 1'd0;
+ litedramcore_new_master_rdata_valid6 <= 1'd0;
+ litedramcore_new_master_rdata_valid7 <= 1'd0;
+ litedramcore_new_master_rdata_valid8 <= 1'd0;
+ litedramcore_state <= 2'd0;
+ end
end
reg [23:0] storage[0:15];
reg [23:0] storage_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_we)
- storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_w;
- storage_dat0 <= storage[litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine0_wrport_we)
+ storage[litedramcore_bankmachine0_wrport_adr] <= litedramcore_bankmachine0_wrport_dat_w;
+ storage_dat0 <= storage[litedramcore_bankmachine0_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_wrport_dat_r = storage_dat0;
-assign litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_dat_r = storage[litedramcore_bankmachine0_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine0_wrport_dat_r = storage_dat0;
+assign litedramcore_bankmachine0_rdport_dat_r = storage[litedramcore_bankmachine0_rdport_adr];
//------------------------------------------------------------------------------
reg [23:0] storage_1[0:15];
reg [23:0] storage_1_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_we)
- storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_w;
- storage_1_dat0 <= storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine1_wrport_we)
+ storage_1[litedramcore_bankmachine1_wrport_adr] <= litedramcore_bankmachine1_wrport_dat_w;
+ storage_1_dat0 <= storage_1[litedramcore_bankmachine1_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_wrport_dat_r = storage_1_dat0;
-assign litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_dat_r = storage_1[litedramcore_bankmachine1_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine1_wrport_dat_r = storage_1_dat0;
+assign litedramcore_bankmachine1_rdport_dat_r = storage_1[litedramcore_bankmachine1_rdport_adr];
//------------------------------------------------------------------------------
reg [23:0] storage_2[0:15];
reg [23:0] storage_2_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_we)
- storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_w;
- storage_2_dat0 <= storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine2_wrport_we)
+ storage_2[litedramcore_bankmachine2_wrport_adr] <= litedramcore_bankmachine2_wrport_dat_w;
+ storage_2_dat0 <= storage_2[litedramcore_bankmachine2_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_wrport_dat_r = storage_2_dat0;
-assign litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_dat_r = storage_2[litedramcore_bankmachine2_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine2_wrport_dat_r = storage_2_dat0;
+assign litedramcore_bankmachine2_rdport_dat_r = storage_2[litedramcore_bankmachine2_rdport_adr];
//------------------------------------------------------------------------------
reg [23:0] storage_3[0:15];
reg [23:0] storage_3_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_we)
- storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_w;
- storage_3_dat0 <= storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine3_wrport_we)
+ storage_3[litedramcore_bankmachine3_wrport_adr] <= litedramcore_bankmachine3_wrport_dat_w;
+ storage_3_dat0 <= storage_3[litedramcore_bankmachine3_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_wrport_dat_r = storage_3_dat0;
-assign litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_dat_r = storage_3[litedramcore_bankmachine3_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine3_wrport_dat_r = storage_3_dat0;
+assign litedramcore_bankmachine3_rdport_dat_r = storage_3[litedramcore_bankmachine3_rdport_adr];
//------------------------------------------------------------------------------
reg [23:0] storage_4[0:15];
reg [23:0] storage_4_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_we)
- storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_w;
- storage_4_dat0 <= storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine4_wrport_we)
+ storage_4[litedramcore_bankmachine4_wrport_adr] <= litedramcore_bankmachine4_wrport_dat_w;
+ storage_4_dat0 <= storage_4[litedramcore_bankmachine4_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_wrport_dat_r = storage_4_dat0;
-assign litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_dat_r = storage_4[litedramcore_bankmachine4_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine4_wrport_dat_r = storage_4_dat0;
+assign litedramcore_bankmachine4_rdport_dat_r = storage_4[litedramcore_bankmachine4_rdport_adr];
//------------------------------------------------------------------------------
reg [23:0] storage_5[0:15];
reg [23:0] storage_5_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_we)
- storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_w;
- storage_5_dat0 <= storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine5_wrport_we)
+ storage_5[litedramcore_bankmachine5_wrport_adr] <= litedramcore_bankmachine5_wrport_dat_w;
+ storage_5_dat0 <= storage_5[litedramcore_bankmachine5_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_wrport_dat_r = storage_5_dat0;
-assign litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_dat_r = storage_5[litedramcore_bankmachine5_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine5_wrport_dat_r = storage_5_dat0;
+assign litedramcore_bankmachine5_rdport_dat_r = storage_5[litedramcore_bankmachine5_rdport_adr];
//------------------------------------------------------------------------------
reg [23:0] storage_6[0:15];
reg [23:0] storage_6_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_we)
- storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_w;
- storage_6_dat0 <= storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine6_wrport_we)
+ storage_6[litedramcore_bankmachine6_wrport_adr] <= litedramcore_bankmachine6_wrport_dat_w;
+ storage_6_dat0 <= storage_6[litedramcore_bankmachine6_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_wrport_dat_r = storage_6_dat0;
-assign litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_dat_r = storage_6[litedramcore_bankmachine6_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine6_wrport_dat_r = storage_6_dat0;
+assign litedramcore_bankmachine6_rdport_dat_r = storage_6[litedramcore_bankmachine6_rdport_adr];
//------------------------------------------------------------------------------
reg [23:0] storage_7[0:15];
reg [23:0] storage_7_dat0;
always @(posedge sys_clk) begin
- if (litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_we)
- storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr] <= litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_w;
- storage_7_dat0 <= storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_adr];
+ if (litedramcore_bankmachine7_wrport_we)
+ storage_7[litedramcore_bankmachine7_wrport_adr] <= litedramcore_bankmachine7_wrport_dat_w;
+ storage_7_dat0 <= storage_7[litedramcore_bankmachine7_wrport_adr];
end
always @(posedge sys_clk) begin
end
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_wrport_dat_r = storage_7_dat0;
-assign litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_dat_r = storage_7[litedramcore_bankmachine7_cmd_buffer_lookahead_rdport_adr];
+assign litedramcore_bankmachine7_wrport_dat_r = storage_7_dat0;
+assign litedramcore_bankmachine7_rdport_dat_r = storage_7[litedramcore_bankmachine7_rdport_adr];
FDCE FDCE(
.LOCKED(locked)
);
-(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
+(* ars_ff1 = "true", async_reg = "true" *)
+FDPE #(
.INIT(1'd1)
) FDPE (
.C(iodelay_clk),
.Q(xilinxasyncresetsynchronizerimpl0_rst_meta)
);
-(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
+(* ars_ff2 = "true", async_reg = "true" *)
+FDPE #(
.INIT(1'd1)
) FDPE_1 (
.C(iodelay_clk),
.Q(iodelay_rst)
);
-(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
+(* ars_ff1 = "true", async_reg = "true" *)
+FDPE #(
.INIT(1'd1)
) FDPE_2 (
.C(sys_clk),
.Q(xilinxasyncresetsynchronizerimpl1_rst_meta)
);
-(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
+(* ars_ff2 = "true", async_reg = "true" *)
+FDPE #(
.INIT(1'd1)
) FDPE_3 (
.C(sys_clk),
.Q(sys_rst)
);
-(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
+(* ars_ff1 = "true", async_reg = "true" *)
+FDPE #(
.INIT(1'd1)
) FDPE_4 (
.C(sys4x_clk),
.Q(xilinxasyncresetsynchronizerimpl2_rst_meta)
);
-(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
+(* ars_ff2 = "true", async_reg = "true" *)
+FDPE #(
.INIT(1'd1)
) FDPE_5 (
.C(sys4x_clk),
.Q(xilinxasyncresetsynchronizerimpl2_expr)
);
-(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
+(* ars_ff1 = "true", async_reg = "true" *)
+FDPE #(
.INIT(1'd1)
) FDPE_6 (
.C(sys4x_dqs_clk),
.Q(xilinxasyncresetsynchronizerimpl3_rst_meta)
);
-(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
+(* ars_ff2 = "true", async_reg = "true" *)
+FDPE #(
.INIT(1'd1)
) FDPE_7 (
.C(sys4x_dqs_clk),
endmodule
// -----------------------------------------------------------------------------
-// Auto-Generated by LiteX on 2022-08-04 21:07:01.
+// Auto-Generated by LiteX on 2022-10-28 19:01:25.
//------------------------------------------------------------------------------
projects / microwatt.git / commitdiff