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diff --git a/openpower/sv/svp64/discussion.mdwn b/openpower/sv/svp64/discussion.mdwn
index c996d39306ef342c0abb0b6440e318f9b80dff1f..78e782c28355ee4f57ac043b57fe3fc5af780db8 100644 (file)
--- a/openpower/sv/svp64/discussion.mdwn
+++ b/openpower/sv/svp64/discussion.mdwn
@@ -4,7 +4,6 @@ the original assessment for SVP from 18 months ago concluded that it should be e
 
 question: has anything changed about the assessment that was done, which concluded that for scalar SVP regs they should overlap completely with scalar ISA regs?
 
-
 # Notes on requirements for bit allocations
 
 do not try to jam VL or MAXVL in.  go with the flow of 24 bits spare.
@@ -230,6 +229,14 @@ Summary so far:
   bit for auto-VL=1.  requires an extra reduction instruction.
 * sv.branches should not be touched. at all.
 
+## only 1 src/dest
+
+Instructions in this category are usually Unvectoriseable
+or they are Load-Immediates. `fmvis` for example, is 1-Write,
+whilst SV.Branch-Conditional is BI (CR field bit).
+
+TBD
+
 ## answers to 2, RM Modes
 
 **Normal Mode:**