(no commit message)

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index f1a06c5cb304d76a4da6ded73e1028a3b4b24841..74b26366a4000baf0a4d181421659222aa7521a0 100644 (file)
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -19,7 +19,6 @@ Scalar instructions, present and future, in the Scalar Power ISA.
 The Vectorisation System is called "Simple-V" and the Prefix Format is
 called "SVP64". **Simple-V is not a Traditional Vector ISA and therefore
 does not add Vector opcodes**.
-
 An ISA Concept similar to Simple-V was originally invented in 1994 by
 Peter Hsu (Architect of the MIPS R8000) but was dropped as MIPS did not
 have an Out-of-Order Microarchitecture on which to best exploit it.
@@ -111,14 +110,14 @@ such large numbers of registers, even for Multi-Issue microarchitectures.
   (**No modifications to existing Power ISA are required either**).
 * GPR FPR and CR Field Register numbers are extended to 128.
   A future version may extend to 256 or beyond [^extend]
-* (A future version or other Stakeholder *may* wish to drop Simple-V
-  onto VSX: extension of the number of VSX registers will be discussed at that
-  time)
+ (A future version or other Stakeholder *may* wish to drop Simple-V
+  onto VSX: this would be a separate RFC)
 * 24-bits are needed within the main SVP64 Prefix (equivalent to a 2-bit XO)
 * Another 24-bit (a second 2-bit XO) is needed for a planned future encoding,
   currently named "SVP64-Single" [^likeext001]
 * A third 24-bits (third 2-bit XO) is strongly recommended to be `RESERVED`
-  such that future unforeseen capability is needed.
+  such that future unforeseen capability is needed (although this may be
+  alternatively achieved with a mandatory PCR or MSR bit)
 * To hold all Vector Context, five SPRs are needed for userspace.
   If Supervisor and Hypervisor mode are to
   also support Simple-V they will correspondingly need five SPRs each.
@@ -134,7 +133,7 @@ such large numbers of registers, even for Multi-Issue microarchitectures.
 No further opcode space *for Simple-V* is envisaged to be required for
 at least the next decade (including if added on VSX)
 
-**SPRs**
+**Simple-V SPRs**
 
 * **SVSTATE** - Vectorisation State sufficient for Precise-Interrupt
   Context-switching and no adverse latency.