Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility

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+Subject: Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture
+ feasibility
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+Lauri Kasanen schreef op ma 16-03-2020 om 09:14 [+0200]:
+> On Sun, 15 Mar 2020 12:43:45 -0700Jacob Lifshay <programmerjake@gmail.com=
+> wrote:
+> > Later (for Libre-SOC v2 or v3), it might be a good idea to add support =
+forx86 and x86_64 user-mode since the patents for the base ISA will haveexp=
+ired by then. This would help give us an advantage since it would allowus t=
+o run legacy software.
+>=20
+> 486 and 586 patents had expired years ago, and we had Chinese 1 GHzimplem=
+entations of those (vortex86). Now they have 686 models, so Itake pentium p=
+ro patents are also up for use.
+
+I think these were because Via had cross-patent license agreement with Inte=
+l.
+
+greets,
+Staf.
+
+
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