i965/gen9: Enable rep clears on gen9

The (gen < 9) check in brw_clear() was too broad. It disabled all types
of fast color clears:
    a. singlesample rep clears
    b. singlesample MCS fast clears
    c. multisample MCS fast clears

The MCS clears are still buggy, but the rep clear works well. So let's
enable it.

Reviewed-by: Neil Roberts <neil@linux.intel.com>

diff --git a/src/mesa/drivers/dri/i965/brw_clear.c b/src/mesa/drivers/dri/i965/brw_clear.c
index 17a745d0373f9da3621b17330906f08cdd797ae4..b0119558c3a4016c83cd22ec5de88263161a3019 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -241,7 +241,7 @@ brw_clear(struct gl_context *ctx, GLbitfield mask)
    }
 
    /* Clear color buffers with fast clear or at least rep16 writes. */
-   if (brw->gen >= 6 && brw->gen < 9 && (mask & BUFFER_BITS_COLOR)) {
+   if (brw->gen >= 6 && (mask & BUFFER_BITS_COLOR)) {
       if (brw_meta_fast_clear(brw, fb, mask, partial_clear)) {
          debug_mask("blorp color", mask & BUFFER_BITS_COLOR);
          mask &= ~BUFFER_BITS_COLOR;

diff --git a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
index eb201736c6ec5ff60374f1be64e5d95344c605e3..fbde3f04204b6e91e27cad88513ffc16cd558e15 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_meta_fast_clear.c
@@ -451,6 +451,11 @@ brw_meta_fast_clear(struct brw_context *brw, struct gl_framebuffer *fb,
       if (irb->mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_NO_MCS)
          clear_type = REP_CLEAR;
 
+      if (brw->gen >= 9 && clear_type == FAST_CLEAR) {
+         perf_debug("fast MCS clears are disabled on gen9");
+         clear_type = REP_CLEAR;
+      }
+
       /* We can't do scissored fast clears because of the restrictions on the
        * fast clear rectangle size.
        */