Remove explicit bus names

diff --git a/milkymist/lm32/__init__.py b/milkymist/lm32/__init__.py
index 3245954195656eaba40b063c8c66446943324ac4..29be0f65e4bbd2a9fa2e8907c7098d3db530f7a8 100644 (file)
--- a/milkymist/lm32/__init__.py
+++ b/milkymist/lm32/__init__.py
@@ -3,8 +3,8 @@ from migen.bus import wishbone
 
 class LM32:
        def __init__(self):
-               self.ibus = i = wishbone.Master("lm32i")
-               self.dbus = d = wishbone.Master("lm32d")
+               self.ibus = i = wishbone.Master()
+               self.dbus = d = wishbone.Master()
                self.interrupt = Signal(BV(32))
                self.ext_break = Signal()
                self._inst = Instance("lm32_top",

diff --git a/milkymist/norflash/__init__.py b/milkymist/norflash/__init__.py
index 0ee19ec27894f7d3a08855d8578fbe628f2a3232..5b3ad788a82e923f35fc0d6151ac995e004e2afd 100644 (file)
--- a/milkymist/norflash/__init__.py
+++ b/milkymist/norflash/__init__.py
@@ -4,7 +4,7 @@ from migen.corelogic import timeline
 
 class NorFlash:
        def __init__(self, adr_width, rd_timing):
-               self.bus = wishbone.Slave("norflash")
+               self.bus = wishbone.Slave()
                self.adr = Signal(BV(adr_width-1))
                self.d = Signal(BV(16))
                self.oe_n = Signal()

diff --git a/milkymist/sram/__init__.py b/milkymist/sram/__init__.py
index 5071c423615276f3a9b3712c9c1413414d5f7eb0..756b2c51601fa1f53f8da723d03b1e5ec2889733 100644 (file)
--- a/milkymist/sram/__init__.py
+++ b/milkymist/sram/__init__.py
@@ -3,7 +3,7 @@ from migen.bus import wishbone
 
 class SRAM:
        def __init__(self, depth):
-               self.bus = wishbone.Slave("sram")
+               self.bus = wishbone.Slave()
                self.depth = depth
        
        def get_fragment(self):