add rvc_sp redirection/offset overload

also found weird bug where RVC_FRS1/2 were not being detected,
how it was not found earlier is a mystery, code should not
have compiled!

diff --git a/id_regs.py b/id_regs.py
index 3563f6061b37d74b1703d49090c8204fad3fe791..8a96032e71af71a790df2ccde351e588b4a47edb 100644 (file)
--- a/id_regs.py
+++ b/id_regs.py
@@ -39,9 +39,10 @@ def list_insns():
         res.append((os.path.join(insns_dir, fname), insn))
     return res
 
-cintpatterns = [ 'WRITE_RVC_RS1S', 'WRITE_RVC_RS2S',
-                 'RVC_RS1', 'RVC_RS2', 'RVC_RS1S', 'RVC_RS2S', ]
-cfloatpatterns = [ 'WRITE_RVC_FRS2S', 'RVC_FRS2 ', 'RVC_FRS2S ']
+cintpatterns = [ 'WRITE_RVC_RS1S', 'WRITE_RVC_RS2S', 'RVC_SP',
+                 'RVC_RS1', 'RVC_RS2', 'RVC_RS1S', 'RVC_RS2S',
+                 ]
+cfloatpatterns = [ 'WRITE_RVC_FRS2S', 'RVC_FRS2', 'RVC_FRS2S']
 intpatterns   = ['WRITE_RD' , 'RS1', 'RS2', 'RS3']
 floatpatterns = ['WRITE_FRD', 'FRS1', 'FRS2', 'FRS3']
 patterns = intpatterns + floatpatterns
@@ -50,16 +51,17 @@ patterns += cfloatpatterns
 
 allfloats = floatpatterns + cfloatpatterns
 floatmask = (1<<len(allfloats)-1)
-allints = intpatterns + cintpatterns[2:]
+allints = intpatterns + cintpatterns[3:]
 
 skip = '#define USING_NOREGS\n' \
        '#define REGS_PATTERN 0x0\n'
 
-# this matches the order of the 4 predication arguments to
+# this matches the order of the 5 predication arguments to
 drlookup = { 'rd': 0, 'frd': 0, 'rs1': 1, 'rs2': 2, 'rs3': 3,
              'rvc_rs1': 1, 'rvc_rs1s': 1,
              'rvc_rs2': 2, 'rvc_rs2s': 2,
              'rvc_frs2': 2, 'rvc_frs2s': 2,
+             'rvc_sp': 4,
              }
 
 def find_registers(fname, insn, twin_predication, immed_offset, is_branch):
@@ -92,7 +94,7 @@ def find_registers(fname, insn, twin_predication, immed_offset, is_branch):
                 # RS1 also matches against RVC_FRS1 (etc.)
                 # check letter before match: if "_", skip it.
                 continue
-            if 'RVC_' in pattern and f[x+len(pattern)] == 'S':
+            if 'RVC_' in pattern and f[x+len(pattern)-1] == 'S':
                 # RVC_RS2S also matches against RVC_RS2 (etc.)
                 # check letter at end of match: if "S", skip it.
                 continue
@@ -125,7 +127,7 @@ def find_registers(fname, insn, twin_predication, immed_offset, is_branch):
         return skip
     res.append('#define REGS_PATTERN 0x%x' % isintfloat)
 
-    predargs = ['dest_pred'] * 4
+    predargs = ['dest_pred'] * 5
     if immed_offset: # C.LWSP
         if immed_offset == 'LD':
             predargs.append('&src_pred')
@@ -158,7 +160,7 @@ def find_registers(fname, insn, twin_predication, immed_offset, is_branch):
             res.append('#define SRC_PREDINT %d' % (0 if fsrc else 1))
             res.append('#define SRC_REG %s' % found)
 
-    if len(predargs) == 4:
+    if len(predargs) == 5:
         predargs.append('NULL')
 
     res.append('#define PRED_ARGS %s' % ','.join(predargs))

diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc
index bbc0a62aab020c99668ef8bd71088ae05d46abbf..2f77612bf25e9c93a0b1bacf3f8b616b324dafef 100644 (file)
--- a/riscv/insn_template_sv.cc
+++ b/riscv/insn_template_sv.cc
@@ -27,8 +27,8 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc)
 // not going to make any difference...
 #define DEST_PREDINT 1
 #define SRC_PREDINT 1
-#define PRED_ARGS dest_pred,dest_pred,dest_pred,dest_pred,&dest_pred
-#define OFFS_ARGS dest_offs,dest_offs,dest_offs,dest_offs,dest_offs
+#define PRED_ARGS dest_pred,dest_pred,dest_pred,dest_pred,dest_pred,&dest_pred
+#define OFFS_ARGS dest_offs,dest_offs,dest_offs,dest_offs,dest_offs,dest_offs
 #else
 #define sv_enabled true
 #endif

diff --git a/riscv/sv_decode.h b/riscv/sv_decode.h
index b2b73a4a4c2b81ecfca0d555b70b514faf534fcf..c6b01dc177b7d63ba938ce9e34009017624479ce 100644 (file)
--- a/riscv/sv_decode.h
+++ b/riscv/sv_decode.h
@@ -25,13 +25,15 @@ class sv_insn_t: public insn_t
 public:
   sv_insn_t(processor_t *pr, bool _sv_enabled, insn_bits_t bits, unsigned int f,
             uint64_t &p_rd, uint64_t &p_rs1, uint64_t &p_rs2, uint64_t &p_rs3,
-            uint64_t *p_im,
-            int *o_rd, int *o_rs1, int *o_rs2, int *o_rs3, int *o_imm) :
+            uint64_t &p_sp, uint64_t *p_im,
+            int *o_rd, int *o_rs1, int *o_rs2, int *o_rs3, int *o_sp,
+            int *o_imm) :
             insn_t(bits), p(pr), sv_enabled(_sv_enabled), vloop_continue(false),
             at_least_one_reg_vectorised(false), fimap(f),
             offs_rd(o_rd), offs_rs1(o_rs1), offs_rs2(o_rs2), offs_rs3(o_rs3),
+            offs_sp(o_sp),
             offs_imm(o_imm),
-            prd(p_rd), prs1(p_rs1), prs2(p_rs2), prs3(p_rs3),
+            prd(p_rd), prs1(p_rs1), prs2(p_rs2), prs3(p_rs3), psp(p_sp),
             save_branch_addr(0) {}
 
   uint64_t rvc_imm() { return (insn_t::rvc_imm()); }
@@ -52,6 +54,7 @@ public:
   uint64_t rvc_rs1s() { return predicated(_rvc_rs1s(), *offs_rs1, prs1); }
   uint64_t rvc_rs2 () { return predicated(_rvc_rs2 (), *offs_rs2, prs2); }
   uint64_t rvc_rs2s() { return predicated(_rvc_rs2s(), *offs_rs2, prs2); }
+  uint64_t rvc_sp  () { return predicated(_rvc_sp  (), *offs_sp , psp ); }
 
   uint64_t _rd () { return _remap(insn_t::rd (), fimap & REG_RD , offs_rd); }
   uint64_t _rs1() { return _remap(insn_t::rs1(), fimap & REG_RS1, offs_rs1); }
@@ -65,6 +68,8 @@ public:
                                        offs_rs2); }
   uint64_t _rvc_rs2s() { return _remap(insn_t::rvc_rs2s(), fimap & REG_RVC_RS2S,
                                        offs_rs2); }
+  uint64_t _rvc_sp  () { return _remap(2, true, // sp always 2, always int
+                                       offs_sp); }
 
   void setpc(int xlen, int vlen, reg_t &npc, reg_t addr, uint64_t offs,
              reg_t *target_reg);
@@ -107,11 +112,14 @@ private:
   int *offs_rs1;
   int *offs_rs2;
   int *offs_rs3;
+  int *offs_sp;
   int *offs_imm;
   uint64_t &prd;
   uint64_t &prs1;
   uint64_t &prs2;
   uint64_t &prs3;
+  uint64_t &psp;
+
   uint64_t save_branch_addr;
   uint64_t save_branch_rd;