Trap superpage PTEs when PPN LSBs are set

diff --git a/riscv/mmu.cc b/riscv/mmu.cc
index f0adb2204c6867bd39e3fd4796dc33d3bc66a851..76a6ab1d4f685cf142a83d03a87f68847529e266 100644 (file)
--- a/riscv/mmu.cc
+++ b/riscv/mmu.cc
@@ -197,6 +197,8 @@ reg_t mmu_t::walk(reg_t addr, access_type type, reg_t mode)
                type == LOAD ?  !(pte & PTE_R) && !(mxr && (pte & PTE_X)) :
                                !((pte & PTE_R) && (pte & PTE_W))) {
       break;
+    } else if ((ppn & ((reg_t(1) << ptshift) - 1)) != 0) {
+      break;
     } else {
       reg_t ad = PTE_A | ((type == STORE) * PTE_D);
 #ifdef RISCV_ENABLE_DIRTY