Merge tag 'yosys-0.9'

diff --cc CHANGELOG
index dd94c76ed1818df87e0a0de323a0e7219838620a,afbcffa26dd6e2f80f429b8727e1be164da09624..c4882acaba6451612a96e5ba9873e2ada7915e19
--- 1/CHANGELOG
--- 2/CHANGELOG
+++ b/CHANGELOG
@@@ -3,42 -3,14 +3,44 @@@ List of major changes and improvements 
  =======================================================
  
  
 -Yosys 0.8 .. Yosys 0.9
 +Yosys 0.9 .. Yosys 0.9-dev
  --------------------------
  
- Yosys 0.8 .. Yosys 0.8-dev
- --------------------------
 + * Various
 +    - Added "write_xaiger" backend
 +    - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
 +    - Added "synth_xilinx -abc9" (experimental)
 +    - Added "synth_ice40 -abc9" (experimental)
 +    - Added "synth -abc9" (experimental)
 +    - Added "script -scriptwire
++    - Added "synth_xilinx -nocarry"
++    - Added "synth_xilinx -nowidelut"
++    - Added "synth_ecp5 -nowidelut"
++    - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
 +    - "synth_xilinx" to now infer wide multiplexers (-widemux <min> to enable)
 +    - Renamed labels/options in synth_ice40 (e.g. dram -> map_lutram; -nodram -> -nolutram)
 +    - Renamed labels/options in synth_ecp5 (e.g. dram -> map_lutram; -nodram -> -nolutram)
 +    - Renamed labels in synth_intel (e.g. bram -> map_bram)
 +    - Renamed labels/options in synth_xilinx (e.g. dram -> map_lutram; -nodram -> -nolutram)
 +    - Added automatic gzip decompression for frontends
 +    - Added $_NMUX_ cell type
 +    - Added automatic gzip compression (based on filename extension) for backends
 +    - Improve attribute and parameter encoding in JSON to avoid ambiguities between
 +      bit vectors and strings containing [01xz]*
 +    - Improvements in pmgen: subpattern and recursive matches
 +    - Added "opt_share" pass, run as part of "opt -full"
 +    - Added "ice40_wrapcarry" to encapsulate SB_LUT+SB_CARRY pairs for techmapping
 +    - Removed "ice40_unlut"
 +    - Improvements in pmgen: slices, choices, define, generate
 +
++Yosys 0.8 .. Yosys 0.9
++----------------------
 +
   * Various
-     - Added $changed support to read_verilog
+     - Many bugfixes and small improvements
+     - Added support for SystemVerilog interfaces and modports
      - Added "write_edif -attrprop"
-     - Added "ice40_unlut" pass
      - Added "opt_lut" pass
-     - Added "synth_ice40 -relut"
-     - Added "synth_ice40 -noabc"
      - Added "gate2lut.v" techmap rule
      - Added "rename -src"
      - Added "equiv_opt" pass
@@@ -49,12 -58,69 +88,69 @@@
      - Added "muxcover -nopartial"
      - Added "muxpack" pass
      - Added "pmux2shiftx -norange"
 - * Xilinx support 
+     - Added support for "~" in filename parsing
+     - Added "read_verilog -pwires" feature to turn parameters into wires
+     - Fixed sign extension of unsized constants with 'bx and 'bz MSB
+     - Fixed genvar to be a signed type
+     - Added support for attributes on case rules
+     - Added "upto" and "offset" to JSON frontend and backend
+     - Several liberty file parser improvements
+     - Fixed handling of more complex BRAM patterns
+     - Add "write_aiger -I -O -B"
+ 
+  * Formal Verification
+     - Added $changed support to read_verilog
+     - Added "read_verilog -noassert -noassume -assert-assumes"
+     - Added btor ops for $mul, $div, $mod and $concat
+     - Added yosys-smtbmc support for btor witnesses
+     - Added "supercover" pass
+     - Fixed $global_clock handling vs autowire
+     - Added $dffsr support to "async2sync"
+     - Added "fmcombine" pass
+     - Added memory init support in "write_btor"
+     - Added "cutpoint" pass
+     - Changed "ne" to "neq" in btor2 output
+     - Added support for SVA "final" keyword
+     - Added "fmcombine -initeq -anyeq"
+     - Added timescale and generated-by header to yosys-smtbmc vcd output
+     - Improved BTOR2 handling of undriven wires
+ 
+  * Verific support
+     - Enabled Verific flags vhdl_support_variable_slice and veri_elaborate_top_level_modules_having_interface_ports
+     - Improved support for asymmetric memories
+     - Added "verific -chparam"
+     - Fixed "verific -extnets" for more complex situations
+     - Added "read -verific" and "read -noverific"
+     - Added "hierarchy -chparam"
+ 
+  * New back-ends
+     - Added initial Anlogic support
+     - Added initial SmartFusion2 and IGLOO2 support
+ 
+  * ECP5 support
+     - Added "synth_ecp5 -nowidelut"
+     - Added BRAM inference support to "synth_ecp5"
+     - Added support for transforming Diamond IO and flipflop primitives
+ 
+  * iCE40 support
+     - Added "ice40_unlut" pass
+     - Added "synth_ice40 -relut"
+     - Added "synth_ice40 -noabc"
+     - Added "synth_ice40 -dffe_min_ce_use"
+     - Added DSP inference support using pmgen
+     - Added support for initialising BRAM primitives from a file
+     - Added iCE40 Ultra RGB LED driver cells
+ 
++ * Xilinx support
+     - Use "write_edif -pvector bra" for Xilinx EDIF files
+     - Fixes for VPR place and route support with "synth_xilinx"
+     - Added more cell simulation models
+     - Added "synth_xilinx -family"
+     - Added "stat -tech xilinx" to estimate logic cell usage
      - Added "synth_xilinx -nocarry"
      - Added "synth_xilinx -nowidelut"
-     - Added "synth_ecp5 -nowidelut"
      - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
-     - Fixed sign extension of unsized constants with 'bx and 'bz MSB
- 
+     - Added support for mapping RAM32X1D
  
  Yosys 0.7 .. Yosys 0.8
  ----------------------

diff --cc Makefile
index a742f2e50f34c503b9f5b6dc4ed11151537a54a3,a673154151bdb60ef6b92e439385adb4323fefbd..48a4f3a1ccb70f8f88864967179192b643726796
--- 1/Makefile
--- 2/Makefile
+++ b/Makefile
@@@ -115,7 -114,7 +115,7 @@@ LDFLAGS += -rdynami
  LDLIBS += -lrt
  endif
  
- YOSYS_VER := 0.8+$(shell cd $(YOSYS_SRC) && test -e .git && { git log --author=clifford@clifford.at --oneline 4d4665b.. 2> /dev/null | wc -l; })
 -YOSYS_VER := 0.9
++YOSYS_VER := 0.9+1
  GIT_REV := $(shell cd $(YOSYS_SRC) && git rev-parse --short HEAD 2> /dev/null || echo UNKNOWN)
  OBJS = kernel/version_$(GIT_REV).o