preparation for r200 hw vertex programs. Increase R200_CMD_BUF_SZ to 16k instead...

diff --git a/src/mesa/drivers/dri/r200/r200_context.h b/src/mesa/drivers/dri/r200/r200_context.h
index f6709d3d7fd7f788d00e88b4036b1beac9835210..0de131adc1dda4eaf5897eb333c908f8b2dd0c6d 100644 (file)
--- a/src/mesa/drivers/dri/r200/r200_context.h
+++ b/src/mesa/drivers/dri/r200/r200_context.h
@@ -637,7 +637,7 @@ struct r200_dri_mirror {
 };
 
 
-#define R200_CMD_BUF_SZ  (8*1024) 
+#define R200_CMD_BUF_SZ  (16*1024) 
 
 struct r200_store {
    GLuint statenr;

diff --git a/src/mesa/drivers/dri/r200/r200_reg.h b/src/mesa/drivers/dri/r200/r200_reg.h
index 6d1b84769a8d33d04c4fdb391e0a59ce938fd59f..dab08a9eb730198b18810f59a97f36f293a35c45 100644 (file)
--- a/src/mesa/drivers/dri/r200/r200_reg.h
+++ b/src/mesa/drivers/dri/r200/r200_reg.h
@@ -337,6 +337,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 /* gap */
 #define R200_SE_VAP_CNTL                           0x2080
 #define     R200_VAP_TCL_ENABLE                       0x00000001
+#define     R200_VAP_PROG_VTX_SHADER_ENABLE           0x00000004
 #define     R200_VAP_SINGLE_BUF_STATE_ENABLE          0x00000010
 #define     R200_VAP_FORCE_W_TO_ONE                   0x00010000
 #define     R200_VAP_D3D_TEX_DEFAULT                  0x00020000
@@ -660,6 +661,17 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define R200_SE_TCL_POINT_SPRITE_CNTL     0x22c4
 #define     R200_POINTSIZE_SEL_STATE            (1<<16)
 /* gap */
+/* taken from r300, see comments there */
+#define R200_VAP_PVS_CNTL_1                 0x22d0
+#       define R200_PVS_CNTL_1_PROGRAM_START_SHIFT   0
+#       define R200_PVS_CNTL_1_POS_END_SHIFT         10
+#       define R200_PVS_CNTL_1_PROGRAM_END_SHIFT     20
+/* Addresses are relative the the vertex program parameters area. */
+#define R200_VAP_PVS_CNTL_2                 0x22d4
+#       define R200_PVS_CNTL_2_PARAM_OFFSET_SHIFT 0
+#       define R200_PVS_CNTL_2_PARAM_COUNT_SHIFT  16
+/* gap */
+
 #define R200_SE_VTX_ST_POS_0_X_4                   0x2300
 #define R200_SE_VTX_ST_POS_0_Y_4                   0x2304
 #define R200_SE_VTX_ST_POS_0_Z_4                   0x2308
@@ -1473,6 +1485,10 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define R200_VS_PNT_SPRITE_CLAMP            0x000000BE
 #define R200_VS_MAX                         0x000001C0
 
+#define R200_PVS_PROG0                      0x00000080
+#define R200_PVS_PROG1                      0x00000180
+#define R200_PVS_PARAM0                     0x00000000
+#define R200_PVS_PARAM1                     0x00000100
 
 /*
  * Offsets in TCL scalar state

diff --git a/src/mesa/drivers/dri/r200/r200_sanity.c b/src/mesa/drivers/dri/r200/r200_sanity.c
index 4dc87cd945d5096db775dad19622032a21b65508..8c9319fe278ce1ac95bd78fa36adc144a3cd92af 100644 (file)
--- a/src/mesa/drivers/dri/r200/r200_sanity.c
+++ b/src/mesa/drivers/dri/r200/r200_sanity.c
@@ -160,6 +160,7 @@ static struct {
    { R200_PP_TXFILTER_3, 8, "R200_PP_TXCTLALL_3"},
    { R200_PP_TXFILTER_4, 8, "R200_PP_TXCTLALL_4"},
    { R200_PP_TXFILTER_5, 8, "R200_PP_TXCTLALL_5"},
+   { R200_VAP_PVS_CNTL_1, 2, "R200_VAP_PVS_CNTL"},
 };
 
 struct reg_names {
@@ -532,6 +533,8 @@ static struct reg_names reg_names[] = {
    { R200_PP_TXCBLEND2_15, "R200_PP_TXCBLEND2_15" },
    { R200_PP_TXABLEND_15, "R200_PP_TXABLEND_15" },
    { R200_PP_TXABLEND2_15, "R200_PP_TXABLEND2_15" },
+   { R200_VAP_PVS_CNTL_1, "R200_VAP_PVS_CNTL_1" },
+   { R200_VAP_PVS_CNTL_2, "R200_VAP_PVS_CNTL_2" },
 };
 
 static struct reg_names scalar_names[] = {
@@ -935,6 +938,62 @@ static int radeon_emit_vectors(
    return 0;
 }
 
+static int radeon_emit_veclinear( 
+   drm_radeon_cmd_header_t header,
+   drm_radeon_cmd_buffer_t *cmdbuf )
+{
+   int sz = header.veclinear.count * 4;
+   int *data = (int *)cmdbuf->buf;
+   float *fdata =(float *)cmdbuf->buf;
+   int start = header.veclinear.addr_lo | (header.veclinear.addr_hi << 8);
+   int i;
+
+   if (1||VERBOSE)
+      fprintf(stderr, "emit vectors linear, start %d nr %d (end %d) (0x%x)\n",
+             start, sz >> 2, start + (sz >> 2), header.i);
+
+
+   if (start < 0x60) {
+      for (i = 0 ; i < sz ;  i += 4) {
+        fprintf(stderr, "R200_VS_PARAM %d 0 %f\n", (i >> 2) + start , fdata[i]);
+        fprintf(stderr, "R200_VS_PARAM %d 1 %f\n", (i >> 2) + start, fdata[i+1]);
+        fprintf(stderr, "R200_VS_PARAM %d 2 %f\n", (i >> 2) + start, fdata[i+2]);
+        fprintf(stderr, "R200_VS_PARAM %d 3 %f\n", (i >> 2) + start, fdata[i+3]);
+      }
+   }
+   else if ((start >= 0x100) && (start < 0x160)) {
+      for (i = 0 ; i < sz ;  i += 4) {
+        fprintf(stderr, "R200_VS_PARAM %d 0 %f\n", (i >> 2) + start - 0x100 + 0x60, fdata[i]);
+        fprintf(stderr, "R200_VS_PARAM %d 1 %f\n", (i >> 2) + start - 0x100 + 0x60, fdata[i+1]);
+        fprintf(stderr, "R200_VS_PARAM %d 2 %f\n", (i >> 2) + start - 0x100 + 0x60, fdata[i+2]);
+        fprintf(stderr, "R200_VS_PARAM %d 3 %f\n", (i >> 2) + start - 0x100 + 0x60, fdata[i+3]);
+      }
+   }
+   else if ((start >= 0x80) && (start < 0xc0)) {
+      for (i = 0 ; i < sz ;  i += 4) {
+        fprintf(stderr, "R200_VS_PROG %d OPDST %08x\n", (i >> 2) + start - 0x80, data[i]);
+        fprintf(stderr, "R200_VS_PROG %d SRC1  %08x\n", (i >> 2) + start - 0x80, data[i+1]);
+        fprintf(stderr, "R200_VS_PROG %d SRC2  %08x\n", (i >> 2) + start - 0x80, data[i+2]);
+        fprintf(stderr, "R200_VS_PROG %d SRC3  %08x\n", (i >> 2)  + start - 0x80, data[i+3]);
+      }
+   }
+   else if ((start >= 0x180) && (start < 0x1c0)) {
+      for (i = start ; (i < start + sz) ;  i += 4) {
+        fprintf(stderr, "R200_VS_PROG %d OPDST %08x\n", (i >> 2) + start - 0x180 + 0x40, data[i]);
+        fprintf(stderr, "R200_VS_PROG %d SRC1  %08x\n", (i >> 2) + start - 0x180 + 0x40, data[i+1]);
+        fprintf(stderr, "R200_VS_PROG %d SRC2  %08x\n", (i >> 2) + start - 0x180 + 0x40, data[i+2]);
+        fprintf(stderr, "R200_VS_PROG %d SRC3  %08x\n", (i >> 2) + start - 0x180 + 0x40, data[i+3]);
+      }
+   }
+   else {
+      fprintf(stderr, "write to unknown vector area\n");
+   }
+
+   cmdbuf->buf += sz * sizeof(int);
+   cmdbuf->bufsz -= sz * sizeof(int);
+   return 0;
+}
+
 #if 0
 static int print_vertex_format( int vfmt )
 {
@@ -1360,6 +1419,13 @@ int r200SanityCmdBuffer( r200ContextPtr rmesa,
       case RADEON_CMD_WAIT:
         break;
 
+      case RADEON_CMD_VECLINEAR:
+        if (radeon_emit_veclinear( header, &cmdbuf )) {
+           fprintf(stderr,"radeon_emit_veclinear failed\n");
+           return -EINVAL;
+        }
+        break;
+
       default:
         fprintf(stderr,"bad cmd_type %d at %p\n", 
                   header.header.cmd_type,

diff --git a/src/mesa/drivers/dri/r200/r200_state.c b/src/mesa/drivers/dri/r200/r200_state.c
index 6ffb48c1505b9f28741ce305aab5298761f5e41d..41c7607b61d5abaaa631d7691badf95b5d92cae1 100644 (file)
--- a/src/mesa/drivers/dri/r200/r200_state.c
+++ b/src/mesa/drivers/dri/r200/r200_state.c
@@ -2110,18 +2110,18 @@ static void r200Enable( GLcontext *ctx, GLenum cap, GLboolean state )
            if they didn't change) and restore tex coord routing */
         GLuint unit;
         for (unit = 0; unit < R200_MAX_TEXTURE_UNITS; unit++) {
+           R200_STATECHANGE( rmesa, pix[unit] );
+           R200_STATECHANGE( rmesa, tex[unit] );
            rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT] &=
                ~(R200_TXFORMAT_ST_ROUTE_MASK | R200_TXFORMAT_LOOKUP_DISABLE);
            rmesa->hw.tex[unit].cmd[TEX_PP_TXFORMAT] |= unit << R200_TXFORMAT_ST_ROUTE_SHIFT;
            /* need to guard this with drmSupportsFragmentShader? Should never get here if
               we don't announce ATI_fs, right? */
            rmesa->hw.tex[unit].cmd[TEX_PP_TXMULTI_CTL] = 0;
-           R200_STATECHANGE( rmesa, pix[unit] );
-           R200_STATECHANGE( rmesa, tex[unit] );
          }
-        rmesa->hw.cst.cmd[CST_PP_CNTL_X] = 0;
         R200_STATECHANGE( rmesa, cst );
         R200_STATECHANGE( rmesa, tf );
+        rmesa->hw.cst.cmd[CST_PP_CNTL_X] = 0;
       }
       else {
         /* need to mark this dirty as pix/tf atoms have overwritten the data

diff --git a/src/mesa/drivers/dri/radeon/radeon_sanity.c b/src/mesa/drivers/dri/radeon/radeon_sanity.c
index 9ca9ebe84e0cf9efcc303d79fadfd2ef1be1333e..557057784c35d2decdc410c08fdc67129a7fbc1b 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_sanity.c
+++ b/src/mesa/drivers/dri/radeon/radeon_sanity.c
@@ -156,6 +156,7 @@ static struct {
    { 0, 8, "R200_PP_TXCTLALL_3"},
    { 0, 8, "R200_PP_TXCTLALL_4"},
    { 0, 8, "R200_PP_TXCTLALL_5"},
+   { 0, 2, "R200_VAP_PVS_CNTL"},
 };
 
 struct reg_names {

diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c
index 3a0a8d208b252aac96208491eaa7dec30388b2dc..0a1c0bbc38bc7d5753a0a8fcd272178f8640b29c 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_screen.c
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.c
@@ -372,6 +372,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv )
       screen->drmSupportsFragShader = (sPriv->drmMinor >= 18);
       screen->drmSupportsPointSprites = (sPriv->drmMinor >= 13);
       screen->drmSupportsCubeMapsR100 = (sPriv->drmMinor >= 15);
+      screen->drmSupportsVertexProgram = (sPriv->drmMinor >= 25);
    }
 
    screen->mmio.handle = dri_priv->registerHandle;

diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.h b/src/mesa/drivers/dri/radeon/radeon_screen.h
index 3e0f9454e7f5324805b0c86c3c09dbc0e5612200..25e6fcf399a0879b7a0956c02b9876f7a27bc607 100644 (file)
--- a/src/mesa/drivers/dri/radeon/radeon_screen.h
+++ b/src/mesa/drivers/dri/radeon/radeon_screen.h
@@ -98,6 +98,7 @@ typedef struct {
    GLboolean drmSupportsFragShader;     /* need radeon kernel module >= 1.18 */
    GLboolean drmSupportsPointSprites;   /* need radeon kernel module >= 1.13 */
    GLboolean drmSupportsCubeMapsR100;   /* need radeon kernel module >= 1.15 */
+   GLboolean drmSupportsVertexProgram;  /* need radeon kernel module >= 1.25 */
    GLboolean depthHasSurface;
 
    /* Configuration cache with default values for all contexts */

diff --git a/src/mesa/drivers/dri/radeon/server/radeon_reg.h b/src/mesa/drivers/dri/radeon/server/radeon_reg.h
index a1883f644d18c413c127cdbcba576c2753afcb13..4dcce638460ec5a0fb44ffc2c993ae44f9234f97 100644 (file)
--- a/src/mesa/drivers/dri/radeon/server/radeon_reg.h
+++ b/src/mesa/drivers/dri/radeon/server/radeon_reg.h
@@ -1883,6 +1883,8 @@
 #       define RADEON_LIGHT_6_SHIFT            0
 #       define RADEON_LIGHT_7_SHIFT            16
 
+#define RADEON_SE_TCL_STATE_FLUSH           0x2284
+
 #define RADEON_SE_TCL_SHININESS             0x2250
 
 #define RADEON_SE_TCL_TEXTURE_PROC_CTL      0x2268