bus/csr: Rename a->adr d->dat to be consistent with the other buses

diff --git a/migen/bank/csrgen.py b/migen/bank/csrgen.py
index 6007ab50701e7b8e84af42acc29053f5ce5cfcf6..d0188fa6d68034630c45ae79387b1e5e4a0c9720 100644 (file)
--- a/migen/bank/csrgen.py
+++ b/migen/bank/csrgen.py
@@ -13,7 +13,7 @@ class Bank:
                sync = []
                
                sel = Signal()
-               comb.append(sel.eq(self.interface.a_i[9:] == Constant(self.address, BV(5))))
+               comb.append(sel.eq(self.interface.adr_i[9:] == Constant(self.address, BV(5))))
                
                desc_exp = expand_description(self.description, 8)
                nbits = bits_for(len(desc_exp)-1)
@@ -22,29 +22,29 @@ class Bank:
                bwcases = []
                for i, reg in enumerate(desc_exp):
                        if isinstance(reg, RegisterRaw):
-                               comb.append(reg.r.eq(self.interface.d_i[:reg.size]))
+                               comb.append(reg.r.eq(self.interface.dat_i[:reg.size]))
                                comb.append(reg.re.eq(sel & \
                                        self.interface.we_i & \
-                                       (self.interface.a_i[:nbits] == Constant(i, BV(nbits)))))
+                                       (self.interface.adr_i[:nbits] == Constant(i, BV(nbits)))))
                        elif isinstance(reg, RegisterFields):
                                bwra = [Constant(i, BV(nbits))]
                                offset = 0
                                for field in reg.fields:
                                        if field.access_bus == WRITE_ONLY or field.access_bus == READ_WRITE:
-                                               bwra.append(field.storage.eq(self.interface.d_i[offset:offset+field.size]))
+                                               bwra.append(field.storage.eq(self.interface.dat_i[offset:offset+field.size]))
                                        offset += field.size
                                if len(bwra) > 1:
                                        bwcases.append(bwra)
                        else:
                                raise TypeError
                if bwcases:
-                       sync.append(If(sel & self.interface.we_i, Case(self.interface.a_i[:nbits], *bwcases)))
+                       sync.append(If(sel & self.interface.we_i, Case(self.interface.adr_i[:nbits], *bwcases)))
                
                # Bus reads
                brcases = []
                for i, reg in enumerate(desc_exp):
                        if isinstance(reg, RegisterRaw):
-                               brcases.append([Constant(i, BV(nbits)), self.interface.d_o.eq(reg.w)])
+                               brcases.append([Constant(i, BV(nbits)), self.interface.dat_o.eq(reg.w)])
                        elif isinstance(reg, RegisterFields):
                                brs = []
                                reg_readable = False
@@ -56,16 +56,16 @@ class Bank:
                                                brs.append(Constant(0, BV(field.size)))
                                if reg_readable:
                                        if len(brs) > 1:
-                                               brcases.append([Constant(i, BV(nbits)), self.interface.d_o.eq(Cat(*brs))])
+                                               brcases.append([Constant(i, BV(nbits)), self.interface.dat_o.eq(Cat(*brs))])
                                        else:
-                                               brcases.append([Constant(i, BV(nbits)), self.interface.d_o.eq(brs[0])])
+                                               brcases.append([Constant(i, BV(nbits)), self.interface.dat_o.eq(brs[0])])
                        else:
                                raise TypeError
                if brcases:
-                       sync.append(self.interface.d_o.eq(Constant(0, BV(8))))
-                       sync.append(If(sel, Case(self.interface.a_i[:nbits], *brcases)))
+                       sync.append(self.interface.dat_o.eq(Constant(0, BV(8))))
+                       sync.append(If(sel, Case(self.interface.adr_i[:nbits], *brcases)))
                else:
-                       comb.append(self.interface.d_o.eq(Constant(0, BV(8))))
+                       comb.append(self.interface.dat_o.eq(Constant(0, BV(8))))
                
                # Device access
                for reg in self.description:

diff --git a/migen/bus/csr.py b/migen/bus/csr.py
index 4443cda3e0651ddcf4c5e5d461275c2e669ebb50..9e00932209702e4edaec891e897741b6a34d11f5 100644 (file)
--- a/migen/bus/csr.py
+++ b/migen/bus/csr.py
@@ -3,10 +3,10 @@ from migen.corelogic.misc import optree
 from migen.bus.simple import Simple
 
 _desc = [
-       (True,  "a",    14),
+       (True,  "adr",  14),
        (True,  "we",   1),
-       (True,  "d",    8),
-       (False, "d",    8)
+       (True,  "dat",  8),
+       (False, "dat",  8)
 ]
 
 class Master(Simple):
@@ -25,9 +25,9 @@ class Interconnect:
        def get_fragment(self):
                comb = []
                for slave in self.slaves:
-                       comb.append(slave.a_i.eq(self.master.a_o))
+                       comb.append(slave.adr_i.eq(self.master.adr_o))
                        comb.append(slave.we_i.eq(self.master.we_o))
-                       comb.append(slave.d_i.eq(self.master.d_o))
-               rb = optree('|', [slave.d_o for slave in self.slaves])
-               comb.append(self.master.d_i.eq(rb))
+                       comb.append(slave.dat_i.eq(self.master.dat_o))
+               rb = optree("|", [slave.dat_o for slave in self.slaves])
+               comb.append(self.master.dat_i.eq(rb))
                return Fragment(comb)

diff --git a/migen/bus/wishbone2csr.py b/migen/bus/wishbone2csr.py
index 56568618106280a3fce4f37a00e057ae97c6bfa1..bd5406eec4cb194432fcdc4988b13b107f44d800 100644 (file)
--- a/migen/bus/wishbone2csr.py
+++ b/migen/bus/wishbone2csr.py
@@ -3,7 +3,7 @@ from migen.bus import csr
 from migen.fhdl.structure import *
 from migen.corelogic import timeline
 
-class WB2CSR():
+class WB2CSR:
        def __init__(self):
                self.wishbone = wishbone.Slave()
                self.csr = csr.Master()
@@ -15,8 +15,8 @@ class WB2CSR():
        def get_fragment(self):
                sync = [
                        self.csr.we_o.eq(0),
-                       self.csr.d_o.eq(self.wishbone.dat_i[:8]),
-                       self.csr.a_o.eq(self.wishbone.adr_i[:14]),
-                       self.wishbone.dat_o.eq(self.csr.d_i)
+                       self.csr.dat_o.eq(self.wishbone.dat_i[:8]),
+                       self.csr.adr_o.eq(self.wishbone.adr_i[:14]),
+                       self.wishbone.dat_o.eq(self.csr.dat_i)
                ]
                return Fragment(sync=sync) + self.timeline.get_fragment()