system.ruby = Ruby.create_system(options, system)
-assert(options.num_cpus == len(system.ruby.cpu_ruby_ports))
+assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
-for ruby_port in system.ruby.cpu_ruby_ports:
+for ruby_port in system.ruby._cpu_ruby_ports:
#
# Tie the ruby tester ports to the ruby cpu ports
#
#
# Tie the cpu ports to the correct ruby system ports
#
- cpu.icache_port = system.ruby.cpu_ruby_ports[i].port
- cpu.dcache_port = system.ruby.cpu_ruby_ports[i].port
+ cpu.icache_port = system.ruby._cpu_ruby_ports[i].port
+ cpu.dcache_port = system.ruby._cpu_ruby_ports[i].port
if buildEnv['TARGET_ISA'] == "x86":
- cpu.itb.walker.port = system.ruby.cpu_ruby_ports[i].port
- cpu.dtb.walker.port = system.ruby.cpu_ruby_ports[i].port
+ cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].port
+ cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].port
cpu.interrupts.pio = system.piobus.port
cpu.interrupts.int_port = system.piobus.port
#
system.ruby.randomization = True
-assert(len(cpus) == len(system.ruby.cpu_ruby_ports))
+assert(len(cpus) == len(system.ruby._cpu_ruby_ports))
for (i, cpu) in enumerate(cpus):
#
# Tie the cpu memtester ports to the correct system ports
#
- cpu.test = system.ruby.cpu_ruby_ports[i].port
+ cpu.test = system.ruby._cpu_ruby_ports[i].port
cpu.functional = system.funcmem.port
#
# Since the memtester is incredibly bursty, increase the deadlock
# threshold to 5 million cycles
#
- system.ruby.cpu_ruby_ports[i].deadlock_threshold = 5000000
+ system.ruby._cpu_ruby_ports[i].deadlock_threshold = 5000000
for (i, dma) in enumerate(dmas):
#
system.ruby = Ruby.create_system(options, system)
i = 0
-for ruby_port in system.ruby.cpu_ruby_ports:
+for ruby_port in system.ruby._cpu_ruby_ports:
#
# Tie the cpu test ports to the ruby cpu port
#
system.ruby = Ruby.create_system(options, system)
-assert(options.num_cpus == len(system.ruby.cpu_ruby_ports))
+assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
#
# The tester is most effective when randomization is turned on and
#
system.ruby.randomization = True
-for ruby_port in system.ruby.cpu_ruby_ports:
+for ruby_port in system.ruby._cpu_ruby_ports:
#
# Tie the ruby tester ports to the ruby cpu ports
#
if options.ruby:
options.use_map = True
system.ruby = Ruby.create_system(options, system)
- assert(options.num_cpus == len(system.ruby.cpu_ruby_ports))
+ assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
else:
system.physmem.port = system.membus.port
CacheConfig.config_cache(options, system)
system.cpu[i].workload = multiprocesses[i]
if options.ruby:
- system.cpu[i].icache_port = system.ruby.cpu_ruby_ports[i].port
- system.cpu[i].dcache_port = system.ruby.cpu_ruby_ports[i].port
+ system.cpu[i].icache_port = system.ruby._cpu_ruby_ports[i].port
+ system.cpu[i].dcache_port = system.ruby._cpu_ruby_ports[i].port
if options.fastmem:
system.cpu[0].physmem_port = system.physmem.port
assoc = options.l1d_assoc,
start_index_bit = block_size_bits)
+ l1_cntrl = L1Cache_Controller(version = i,
+ cntrl_id = cntrl_count,
+ L1IcacheMemory = l1i_cache,
+ L1DcacheMemory = l1d_cache,
+ l2_select_num_bits = l2_bits)
+
cpu_seq = RubySequencer(version = i,
icache = l1i_cache,
dcache = l1d_cache,
physMemPort = system.physmem.port,
physmem = system.physmem)
+ l1_cntrl.sequencer = cpu_seq
+
if piobus != None:
cpu_seq.pio_port = piobus.port
- l1_cntrl = L1Cache_Controller(version = i,
- cntrl_id = cntrl_count,
- sequencer = cpu_seq,
- L1IcacheMemory = l1i_cache,
- L1DcacheMemory = l1d_cache,
- l2_select_num_bits = l2_bits)
-
exec("system.l1_cntrl%d = l1_cntrl" % i)
#
#
# Only one unified L1 cache exists. Can cache instructions and data.
#
+ l1_cntrl = L1Cache_Controller(version = i,
+ cntrl_id = cntrl_count,
+ cacheMemory = cache)
+
cpu_seq = RubySequencer(version = i,
icache = cache,
dcache = cache,
physMemPort = system.physmem.port,
physmem = system.physmem)
+ l1_cntrl.sequencer = cpu_seq
+
if piobus != None:
cpu_seq.pio_port = piobus.port
- l1_cntrl = L1Cache_Controller(version = i,
- cntrl_id = cntrl_count,
- sequencer = cpu_seq,
- cacheMemory = cache)
-
exec("system.l1_cntrl%d = l1_cntrl" % i)
#
# Add controllers and sequencers to the appropriate lists
assoc = options.l1d_assoc,
start_index_bit = block_size_bits)
+ l1_cntrl = L1Cache_Controller(version = i,
+ cntrl_id = cntrl_count,
+ L1IcacheMemory = l1i_cache,
+ L1DcacheMemory = l1d_cache,
+ l2_select_num_bits = l2_bits)
+
cpu_seq = RubySequencer(version = i,
icache = l1i_cache,
dcache = l1d_cache,
physMemPort = system.physmem.port,
physmem = system.physmem)
+ l1_cntrl.sequencer = cpu_seq
+
if piobus != None:
cpu_seq.pio_port = piobus.port
- l1_cntrl = L1Cache_Controller(version = i,
- cntrl_id = cntrl_count,
- sequencer = cpu_seq,
- L1IcacheMemory = l1i_cache,
- L1DcacheMemory = l1d_cache,
- l2_select_num_bits = l2_bits)
-
exec("system.l1_cntrl%d = l1_cntrl" % i)
#
# Add controllers and sequencers to the appropriate lists
assoc = options.l1d_assoc,
start_index_bit = block_size_bits)
- cpu_seq = RubySequencer(version = i,
- icache = l1i_cache,
- dcache = l1d_cache,
- physMemPort = system.physmem.port,
- physmem = system.physmem)
-
- if piobus != None:
- cpu_seq.pio_port = piobus.port
-
l1_cntrl = L1Cache_Controller(version = i,
cntrl_id = cntrl_count,
- sequencer = cpu_seq,
L1IcacheMemory = l1i_cache,
L1DcacheMemory = l1d_cache,
l2_select_num_bits = l2_bits,
no_mig_atomic = not \
options.allow_atomic_migration)
+ cpu_seq = RubySequencer(version = i,
+ icache = l1i_cache,
+ dcache = l1d_cache,
+ physMemPort = system.physmem.port,
+ physmem = system.physmem)
+
+ l1_cntrl.sequencer = cpu_seq
+
+ if piobus != None:
+ cpu_seq.pio_port = piobus.port
+
exec("system.l1_cntrl%d = l1_cntrl" % i)
#
# Add controllers and sequencers to the appropriate lists
assoc = options.l2_assoc,
start_index_bit = block_size_bits)
+ l1_cntrl = L1Cache_Controller(version = i,
+ cntrl_id = cntrl_count,
+ L1IcacheMemory = l1i_cache,
+ L1DcacheMemory = l1d_cache,
+ L2cacheMemory = l2_cache,
+ no_mig_atomic = not \
+ options.allow_atomic_migration)
+
cpu_seq = RubySequencer(version = i,
icache = l1i_cache,
dcache = l1d_cache,
physMemPort = system.physmem.port,
physmem = system.physmem)
+ l1_cntrl.sequencer = cpu_seq
+
if piobus != None:
cpu_seq.pio_port = piobus.port
- l1_cntrl = L1Cache_Controller(version = i,
- cntrl_id = cntrl_count,
- sequencer = cpu_seq,
- L1IcacheMemory = l1i_cache,
- L1DcacheMemory = l1d_cache,
- L2cacheMemory = l2_cache,
- no_mig_atomic = not \
- options.allow_atomic_migration)
-
if options.recycle_latency:
l1_cntrl.recycle_latency = options.recycle_latency
#
# Only one unified L1 cache exists. Can cache instructions and data.
#
+ l1_cntrl = L1Cache_Controller(version = i,
+ cntrl_id = cntrl_count,
+ cacheMemory = cache)
+
cpu_seq = RubySequencer(icache = cache,
dcache = cache,
physMemPort = system.physmem.port,
physmem = system.physmem,
using_network_tester = True)
+ l1_cntrl.sequencer = cpu_seq
+
if piobus != None:
cpu_seq.pio_port = piobus.port
- l1_cntrl = L1Cache_Controller(version = i,
- cntrl_id = cntrl_count,
- sequencer = cpu_seq,
- cacheMemory = cache)
-
exec("system.l1_cntrl%d = l1_cntrl" % i)
#
# Add controllers and sequencers to the appropriate lists
tracer = RubyTracer(),
mem_size = total_mem_size)
- ruby.cpu_ruby_ports = cpu_sequencers
+ ruby._cpu_ruby_ports = cpu_sequencers
ruby.random_seed = options.random_seed
return ruby
# centralized crossbar. The large numbers of routers are needed because
# external links do not model outgoing bandwidth in the simple network, but
# internal links do.
- routers = [Router(router_id=i) for i in range(len(nodes)+1)]
- ext_links = [ExtLink(link_id=i, ext_node=n, int_node=routers[i])
- for (i, n) in enumerate(nodes)]
+ cb = Crossbar()
+ cb.routers = [Router(router_id=i) for i in range(len(nodes)+1)]
+ cb.ext_links = [ExtLink(link_id=i, ext_node=n, int_node=cb.routers[i])
+ for (i, n) in enumerate(nodes)]
link_count = len(nodes)
- xbar = routers[len(nodes)] # the crossbar router is the last router created
- int_links = [IntLink(link_id=(link_count+i), node_a=routers[i], node_b=xbar)
- for i in range(len(nodes))]
- return Crossbar(ext_links=ext_links, int_links=int_links,
- routers=routers)
+ xbar = cb.routers[len(nodes)] # the crossbar router is the last router created
+ cb.int_links = [IntLink(link_id=(link_count+i),
+ node_a=cb.routers[i], node_b=xbar)
+ for i in range(len(nodes))]
+ return cb
num_columns = int(num_routers / num_rows)
assert(num_columns * num_rows == num_routers)
+ # Create the mesh object
+ mesh = Mesh()
+
# Create the routers in the mesh
- routers = [Router(router_id=i) for i in range(num_routers)]
+ mesh.routers = [Router(router_id=i) for i in range(num_routers)]
# link counter to set unique link ids
link_count = 0
cntrl_level, router_id = divmod(i, num_routers)
assert(cntrl_level < cntrls_per_router)
ext_links.append(ExtLink(link_id=link_count, ext_node=n,
- int_node=routers[router_id]))
+ int_node=mesh.routers[router_id]))
link_count += 1
# Connect the remainding nodes to router 0. These should only be
assert(node.type == 'DMA_Controller')
assert(i < remainder)
ext_links.append(ExtLink(link_id=link_count, ext_node=node,
- int_node=routers[0]))
+ int_node=mesh.routers[0]))
link_count += 1
# Create the mesh links. First row (east-west) links then column
east_id = col + (row * num_columns)
west_id = (col + 1) + (row * num_columns)
int_links.append(IntLink(link_id=link_count,
- node_a=routers[east_id],
- node_b=routers[west_id],
+ node_a=mesh.routers[east_id],
+ node_b=mesh.routers[west_id],
weight=1))
link_count += 1
north_id = col + (row * num_columns)
south_id = col + ((row + 1) * num_columns)
int_links.append(IntLink(link_id=link_count,
- node_a=routers[north_id],
- node_b=routers[south_id],
+ node_a=mesh.routers[north_id],
+ node_b=mesh.routers[south_id],
weight=2))
link_count += 1
- return Mesh(ext_links=ext_links,
- int_links=int_links,
- routers=routers)
+
+ mesh.int_links = int_links
+ mesh.ext_links = ext_links
+
+ return mesh
assert(remainder == 0)
assert(len(dir_nodes) == 4)
+ mesh = MeshDirCorners()
+
# Create the routers in the mesh
- routers = [Router(router_id=i) for i in range(num_routers)]
+ mesh.routers = [Router(router_id=i) for i in range(num_routers)]
# link counter to set unique link ids
link_count = 0
cntrl_level, router_id = divmod(i, num_routers)
assert(cntrl_level < caches_per_router)
ext_links.append(ExtLink(link_id=link_count, ext_node=n,
- int_node=routers[router_id]))
+ int_node=mesh.routers[router_id]))
link_count += 1
# Connect the dir nodes to the corners.
ext_links.append(ExtLink(link_id=link_count, ext_node=dir_nodes[0],
- int_node=routers[0]))
+ int_node=mesh.routers[0]))
link_count += 1
ext_links.append(ExtLink(link_id=link_count, ext_node=dir_nodes[1],
- int_node=routers[num_columns - 1]))
+ int_node=mesh.routers[num_columns - 1]))
link_count += 1
ext_links.append(ExtLink(link_id=link_count, ext_node=dir_nodes[2],
- int_node=routers[num_routers - num_columns]))
+ int_node=mesh.routers[num_routers - num_columns]))
link_count += 1
ext_links.append(ExtLink(link_id=link_count, ext_node=dir_nodes[3],
- int_node=routers[num_routers - 1]))
+ int_node=mesh.routers[num_routers - 1]))
link_count += 1
# Connect the dma nodes to router 0. These should only be DMA nodes.
for (i, node) in enumerate(dma_nodes):
assert(node.type == 'DMA_Controller')
- ext_links.append(ExtLink(ext_node=node, int_node=routers[0]))
+ ext_links.append(ExtLink(ext_node=node, int_node=mesh.routers[0]))
# Create the mesh links. First row (east-west) links then column
# (north-south) links
east_id = col + (row * num_columns)
west_id = (col + 1) + (row * num_columns)
int_links.append(IntLink(link_id=link_count,
- node_a=routers[east_id],
- node_b=routers[west_id],
+ node_a=mesh.routers[east_id],
+ node_b=mesh.routers[west_id],
weight=1))
link_count += 1
north_id = col + (row * num_columns)
south_id = col + ((row + 1) * num_columns)
int_links.append(IntLink(link_id=link_count,
- node_a=routers[north_id],
- node_b=routers[south_id],
+ node_a=mesh.routers[north_id],
+ node_b=mesh.routers[south_id],
weight=2))
link_count += 1
- return MeshDirCorners(ext_links=ext_links,
- int_links=int_links,
- routers=routers)
+ mesh.ext_links = ext_links
+ mesh.int_links = int_links
+ return mesh
def makeTopology(nodes, options, IntLink, ExtLink, Router):
# Create an individual router for each controller, and connect all to all.
- routers = [Router(router_id=i) for i in range(len(nodes))]
- ext_links = [ExtLink(link_id=i, ext_node=n, int_node=routers[i])
+ pt2pt = Pt2Pt()
+ pt2pt.routers = [Router(router_id=i) for i in range(len(nodes))]
+ ext_links = [ExtLink(link_id=i, ext_node=n, int_node=pt2pt.routers[i])
for (i, n) in enumerate(nodes)]
link_count = len(nodes)
if (i != j):
link_count += 1
int_links.append(IntLink(link_id=link_count,
- node_a=routers[i],
- node_b=routers[j]))
+ node_a=pt2pt.routers[i],
+ node_b=pt2pt.routers[j]))
- return Pt2Pt(ext_links=ext_links,
- int_links=int_links,
- routers=routers)
+ pt2pt.ext_links = ext_links
+ pt2pt.int_links = int_links
+
+ return pt2pt
num_columns = int(num_routers / num_rows)
assert(num_columns * num_rows == num_routers)
+ # Create the torus object
+ torus = Torus()
+
# Create the routers in the torus
- routers = [Router(router_id=i) for i in range(num_routers)]
+ torus.routers = [Router(router_id=i) for i in range(num_routers)]
# link counter to set unique link ids
link_count = 0
cntrl_level, router_id = divmod(i, num_routers)
assert(cntrl_level < cntrls_per_router)
ext_links.append(ExtLink(link_id=link_count, ext_node=n,
- int_node=routers[router_id]))
+ int_node=torus.routers[router_id]))
link_count += 1
# Connect the remainding nodes to router 0. These should only be
assert(node.type == 'DMA_Controller')
assert(i < remainder)
ext_links.append(ExtLink(link_id=link_count, ext_node=node,
- int_node=routers[0]))
+ int_node=torus.routers[0]))
link_count += 1
# Create the torus links. First row (east-west) links then column
else:
east_id = (row * num_columns)
int_links.append(IntLink(link_id=link_count,
- node_a=routers[east_id],
- node_b=routers[west_id],
+ node_a=torus.routers[east_id],
+ node_b=torus.routers[west_id],
latency=2,
weight=1))
link_count += 1
else:
south_id = col
int_links.append(IntLink(link_id=link_count,
- node_a=routers[north_id],
- node_b=routers[south_id],
+ node_a=torus.routers[north_id],
+ node_b=torus.routers[south_id],
latency=2,
weight=2))
link_count += 1
- return Torus(ext_links=ext_links,
- int_links=int_links,
- routers=routers)
+ torus.ext_links = ext_links
+ torus.int_links = int_links
+
+ return torus
system.ruby = Ruby.create_system(options, system)
-assert(len(cpus) == len(system.ruby.cpu_ruby_ports))
+assert(len(cpus) == len(system.ruby._cpu_ruby_ports))
-for (i, ruby_port) in enumerate(system.ruby.cpu_ruby_ports):
+for (i, ruby_port) in enumerate(system.ruby._cpu_ruby_ports):
#
# Tie the cpu test and functional ports to the ruby cpu ports and
# physmem, respectively
system.ruby = Ruby.create_system(options, system)
-assert(options.num_cpus == len(system.ruby.cpu_ruby_ports))
+assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
#
# The tester is most effective when randomization is turned on and
#
system.ruby.randomization = True
-for ruby_port in system.ruby.cpu_ruby_ports:
+for ruby_port in system.ruby._cpu_ruby_ports:
#
# Tie the ruby tester ports to the ruby cpu ports
#
system.ruby = Ruby.create_system(options, system)
-assert(options.num_cpus == len(system.ruby.cpu_ruby_ports))
+assert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
for (i, cpu) in enumerate(system.cpu):
#
# Tie the cpu ports to the ruby cpu ports
#
- cpu.icache_port = system.ruby.cpu_ruby_ports[i].port
- cpu.dcache_port = system.ruby.cpu_ruby_ports[i].port
+ cpu.icache_port = system.ruby._cpu_ruby_ports[i].port
+ cpu.dcache_port = system.ruby._cpu_ruby_ports[i].port
# -----------------------
# run simulation
system.ruby = Ruby.create_system(options, system)
-assert(len(system.ruby.cpu_ruby_ports) == 1)
+assert(len(system.ruby._cpu_ruby_ports) == 1)
#
# Tie the cpu cache ports to the ruby cpu ports and
# physmem, respectively
#
-cpu.icache_port = system.ruby.cpu_ruby_ports[0].port
-cpu.dcache_port = system.ruby.cpu_ruby_ports[0].port
+cpu.icache_port = system.ruby._cpu_ruby_ports[0].port
+cpu.dcache_port = system.ruby._cpu_ruby_ports[0].port
# -----------------------
# run simulation
projects / gem5.git / commitdiff