Update more stuff to use get_src_attribute() and set_src_attribute()

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index faddcd9945e93a7ded28133c42fe5ee1ab772b86..9539861cda6d03d7cd2687aa91a98c196f5cda21 100644 (file)
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1643,7 +1643,7 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *oth
                cell->parameters["\\Y_WIDTH"] = sig_y.size();       \
                cell->setPort("\\A", sig_a);                        \
                cell->setPort("\\Y", sig_y);                        \
-               if (!src.empty()) cell->attributes["\\src"] = src;  \
+               cell->set_src_attribute(src);                       \
                return cell;                                        \
        } \
        RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, RTLIL::SigSpec sig_a, bool is_signed, std::string src) { \

diff --git a/passes/techmap/alumacc.cc b/passes/techmap/alumacc.cc
index 9204489157e46de00a2cc17302e87f72a5b6f762..95be7ab3b66555fd82115c2c33d36cc47e11e27c 100644 (file)
--- a/passes/techmap/alumacc.cc
+++ b/passes/techmap/alumacc.cc
@@ -55,19 +55,19 @@ struct AlumaccWorker
 
                RTLIL::SigSpec get_gt() {
                        if (GetSize(cached_gt) == 0)
-                               cached_gt = alu_cell->module->Not(NEW_ID, alu_cell->module->Or(NEW_ID, get_lt(), get_eq()), false, alu_cell->attributes["\\src"].decode_string());
+                               cached_gt = alu_cell->module->Not(NEW_ID, alu_cell->module->Or(NEW_ID, get_lt(), get_eq()), false, alu_cell->get_src_attribute());
                        return cached_gt;
                }
 
                RTLIL::SigSpec get_eq() {
                        if (GetSize(cached_eq) == 0)
-                               cached_eq = alu_cell->module->ReduceAnd(NEW_ID, alu_cell->getPort("\\X"), false, alu_cell->attributes["\\src"].decode_string());
+                               cached_eq = alu_cell->module->ReduceAnd(NEW_ID, alu_cell->getPort("\\X"), false, alu_cell->get_src_attribute());
                        return cached_eq;
                }
 
                RTLIL::SigSpec get_ne() {
                        if (GetSize(cached_ne) == 0)
-                               cached_ne = alu_cell->module->Not(NEW_ID, get_eq(), false, alu_cell->attributes["\\src"].decode_string());
+                               cached_ne = alu_cell->module->Not(NEW_ID, get_eq(), false, alu_cell->get_src_attribute());
                        return cached_ne;
                }
 
@@ -75,7 +75,7 @@ struct AlumaccWorker
                        if (GetSize(cached_cf) == 0) {
                                cached_cf = alu_cell->getPort("\\CO");
                                log_assert(GetSize(cached_cf) >= 1);
-                               cached_cf = alu_cell->module->Not(NEW_ID, cached_cf[GetSize(cached_cf)-1], false, alu_cell->attributes["\\src"].decode_string());
+                               cached_cf = alu_cell->module->Not(NEW_ID, cached_cf[GetSize(cached_cf)-1], false, alu_cell->get_src_attribute());
                        }
                        return cached_cf;
                }