platforms/kc705: fix speed grade

diff --git a/mibuild/platforms/kc705.py b/mibuild/platforms/kc705.py
index 66366c15214dfc0fa7564b77d09611eb033ed70b..8dc4f7f6e81a8c0252103c4af3a034d8cc08eaf4 100644 (file)
--- a/mibuild/platforms/kc705.py
+++ b/mibuild/platforms/kc705.py
@@ -128,7 +128,7 @@ def Platform(*args, toolchain="vivado", **kwargs):
 
        class RealPlatform(xilinx_platform):
                def __init__(self, crg_factory=lambda p: CRG_DS(p, "clk156", "cpu_reset")):
-                       xilinx_platform.__init__(self, "xc7k325t-ffg900-1", _io, crg_factory)
+                       xilinx_platform.__init__(self, "xc7k325t-ffg900-2", _io, crg_factory)
 
                def create_programmer(self):
                        return XC3SProg("jtaghs1", "bscan_spi_kc705.bit")