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diff --git a/openpower/sv/implementation.mdwn b/openpower/sv/implementation.mdwn
index 39cb7ff24bec7338cb43855b9d1f4732f9310b5f..b9d8e85a574821fb3c353f7c5d5766e845da323d 100644 (file)
--- a/openpower/sv/implementation.mdwn
+++ b/openpower/sv/implementation.mdwn
@@ -141,11 +141,13 @@ Links:
 
 SV's SVSTATE context is effectively a Sub-PC.  On exceptions the PC is saved into SRR0: it should come as no surprise that SVSTATE must be treated exactly the same.  SVSRR0 therefore is added to the list to be saved/restored in **exactly** the same way and time as SRR0 and SRR1.  This is fundamental and absolutely critical to view SVSTATE as a full peer of PC (CIA, NIA).
 
-* ISACaller: TODO
+* ISACaller: TODO unit test
 * power-gem5: TODO
 * TestIssuer: TODO
 * Microwatt: TODO
 
+* added ISACaller SVSRR0 save <https://git.libre-soc.org/?p=openpower-isa.git;a=commitdiff;h=25071d491dba94495657796eb6ff10eb6499257f>
+
 ## Illegal instruction exceptions
 
 Anything not listed as SVP64 extended must raise an illegal exception if prefixed. setvl, branch, mtmsr, mfmsr at the minimum.