(no commit message)

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 74d7b4efb4c72dca2e763b24b25b49c580cfd419..c6589b41a5828da3e7a6f32dbbc26d4fb53ad888 100644 (file)
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -294,7 +294,8 @@ of the problem-space:
   go as low as 8-bit arithmetic, even 8-bit Floating-Point for
   high-performance AI. Rather than waste opcode space adding all
   such operations at different bitwidths, let the prefix
-  *redefine* the element width.
+  *redefine* (override) the element width, without actually altering
+  the Scalar ISA at all.
 * "Reordering" of the assumption of linear sequential element
   access, for Matrices, rotations, transposition, Convolutions,
   DCT, FFT, Parallel Prefix-Sum and other common transformations