re PR target/55981 (std::atomic store is split in two smaller stores)

	PR target/55981
	* config/i386/sync.md (atomic_store<mode>): Always generate SWImode
	store through atomic_store<mode>_1.
	(atomic_store<mode>_1): Macroize insn using SWI mode iterator.

testsuite/ChangeLog:

	PR target/55981
	* gcc.target/pr55981.c: New test.

From-SVN: r195273

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 6475b3c081e697833e097839c2f204c1d5598a06..1bf9288ee9b8da37ec73dcf3b71a50735ac8c9ad 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2012-01-17  Uros Bizjak  <ubizjak@gmail.com>
+
+       PR target/55981
+       * config/i386/sync.md (atomic_store<mode>): Always generate SWImode
+       store through atomic_store<mode>_1.
+       (atomic_store<mode>_1): Macroize insn using SWI mode iterator.
+
 2013-01-17  Martin Jambor  <mjambor@suse.cz>
 
        PR tree-optimizations/55264
@@ -39,8 +46,7 @@
        * tree-loop-distribution.c (update_phis_for_loop_copy): Remove.
        (copy_loop_before): Adjust and delete update-ssa status.
        * tree-vect-loop-manip.c (rename_variables_in_bb): Make static.
-       (rename_variables_in_bb): Likewise.  Properly walk over
-       predecessors.
+       (rename_variables_in_bb): Likewise.  Properly walk over predecessors.
        (rename_variables_in_loop): Remove.
        (slpeel_update_phis_for_duplicate_loop): Likewise.
        (slpeel_tree_duplicate_loop_to_edge_cfg): Handle nested loops,

diff --git a/gcc/config/i386/sync.md b/gcc/config/i386/sync.md
index 2309c83b12271d173e00dd44e1fdef34c9bbe002..9e5835662e1c690e25bd6f7c0ff6a3077e280c9d 100644 (file)
--- a/gcc/config/i386/sync.md
+++ b/gcc/config/i386/sync.md
@@ -225,11 +225,8 @@
        }
 
       /* Otherwise use a store.  */
-      if (INTVAL (operands[2]) & IX86_HLE_RELEASE)
-       emit_insn (gen_atomic_store<mode>_1 (operands[0], operands[1],
-                                            operands[2]));
-      else
-       emit_move_insn (operands[0], operands[1]);
+      emit_insn (gen_atomic_store<mode>_1 (operands[0], operands[1],
+                                          operands[2]));
     }
   /* ... followed by an MFENCE, if required.  */
   if (model == MEMMODEL_SEQ_CST)
@@ -238,10 +235,10 @@
 })
 
 (define_insn "atomic_store<mode>_1"
-  [(set (match_operand:ATOMIC 0 "memory_operand" "=m")
-       (unspec:ATOMIC [(match_operand:ATOMIC 1 "<nonmemory_operand>" "<r><i>")
-                       (match_operand:SI 2 "const_int_operand")]
-                      UNSPEC_MOVA))]
+  [(set (match_operand:SWI 0 "memory_operand" "=m")
+       (unspec:SWI [(match_operand:SWI 1 "<nonmemory_operand>" "<r><i>")
+                    (match_operand:SI 2 "const_int_operand")]
+                   UNSPEC_MOVA))]
   ""
   "%K2mov{<imodesuffix>}\t{%1, %0|%0, %1}")
 

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 34cad904f7609986bbf6d10ec480e15ba8a69cfd..dc25943f8cdecc1fdc3851534fb16ae823b2b0af 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2012-01-17  Uros Bizjak  <ubizjak@gmail.com>
+
+       PR target/55981
+       * gcc.target/pr55981.c: New test.
+
 2013-01-17  Janis Johnson  <janisjo@codesourcery.com>
 
        * gcc.target/arm/pr40887.c: Require at least armv5.

diff --git a/gcc/testsuite/gcc.target/i386/pr55981.c b/gcc/testsuite/gcc.target/i386/pr55981.c
new file mode 100644 (file)
index 0000000..36498d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr55981.c
@@ -0,0 +1,54 @@
+/* { dg-do compile  { target { ! { ia32 } } } } */
+/* { dg-options "-O2" } */
+
+volatile int a, b, c, d, e, f, g, h, i, j, k, l, m, n, o, p;
+
+volatile long long y;
+
+void
+test ()
+{
+  int a_ = a;
+  int b_ = b;
+  int c_ = c;
+  int d_ = d;
+  int e_ = e;
+  int f_ = f;
+  int g_ = g;
+  int h_ = h;
+  int i_ = i;
+  int j_ = j;
+  int k_ = k;
+  int l_ = l;
+  int m_ = m;
+  int n_ = n;
+  int o_ = o;
+  int p_ = p;
+
+  int z;
+
+  for (z = 0; z < 1000; z++)
+    {
+      __atomic_store_n (&y, 0x100000002ll, __ATOMIC_SEQ_CST);
+      __atomic_store_n (&y, 0x300000004ll, __ATOMIC_SEQ_CST);
+    }
+
+  a = a_;
+  b = b_;
+  c = c_;
+  d = d_;
+  e = e_;
+  f = f_;
+  g = g_;
+  h = h_;
+  i = i_;
+  j = j_;
+  k = k_;
+  l = l_;
+  m = m_;
+  n = n_;
+  o = o_;
+  p = p_;
+}
+
+/* { dg-final { scan-assembler-times "movabs" 2 } } */