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diff --git a/openpower/sv/svp_rewrite/svp64/discussion.mdwn b/openpower/sv/svp_rewrite/svp64/discussion.mdwn
index 433e722d48e781ed043f255ee8de82e3aab68679..bf960b973728b6d3bd24d21ffe73a3046bff39d9 100644 (file)
--- a/openpower/sv/svp_rewrite/svp64/discussion.mdwn
+++ b/openpower/sv/svp_rewrite/svp64/discussion.mdwn
@@ -18,6 +18,13 @@ totals: 24 bits (dest elwidth shared)
 
 http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-December/001434.html
 
+## All zeros indicates "disable SVP"
+
+The defaults for all capabilities of SVP should be zero to indicate "no action".  SUBVL=1 encoded as 0b00.  register name prefixes, scalar=0b0, elwidth overrides DEFAULT=0b00, predication off=0b000 etc.
+
+this way SV may be entirely disabled, leaving an "all zeros" to indicate to v3.1B 64bit prefixing that the standard OpenPOWER v3.1B encodings are in full effect (and that SV is not). As all zeros meshes with current "reserved" encodings this should work well.
+
+
 ## twin predication
 
 twin predication and twin elwidth overrides is extremely important to have to be able to override both the src and dest elwidth yet keep the underlying scalar operation intact.  examples include mr with an elwidth=8, VL=8 on the src will take a byte at a time from one 64 bit reg and place it into 8x 64-bit regs, zero-extended.  more complex operations involve SUBVL and Audio/Video DSP operations, see [[av_opcodes]]