verilator: Specify top level module

While verilator finds the correct top level module with the current
setup, if we start adding simulation models it can get confused.

Explicitly specify the top level module.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>

diff --git a/Makefile b/Makefile
index 63c0c6f4c0f1c17a9bfde9b65097ffc457673b67..ca3ee5ffbe600e0bf7986bb0df90f56ccc0311de 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -205,7 +205,7 @@ microwatt.v: $(synth_files) $(RAM_INIT_FILE)
        $(YOSYS) -m $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; write_verilog $@"
 
 microwatt-verilator: microwatt.v verilator/microwatt-verilator.cpp verilator/uart-verilator.c
-       $(VERILATOR) $(VERILATOR_FLAGS) -CFLAGS "$(VERILATOR_CFLAGS) -DCLK_FREQUENCY=$(CLK_FREQUENCY)" -Iuart16550 --assert --cc --exe --build $^ -o $@
+       $(VERILATOR) $(VERILATOR_FLAGS) -CFLAGS "$(VERILATOR_CFLAGS) -DCLK_FREQUENCY=$(CLK_FREQUENCY)" -Iuart16550 --assert --cc --exe --build $^ -o $@ -top-module toplevel
        @cp -f obj_dir/microwatt-verilator microwatt-verilator
 
 microwatt_out.config: microwatt.json $(LPF)

diff --git a/verilator/microwatt-verilator.cpp b/verilator/microwatt-verilator.cpp
index 1e8282082296ebaf6ab94f22a18f60a77f572d1b..3c37f0a86e344da85fd6eaf76c840bd179d83ddf 100644 (file)
--- a/verilator/microwatt-verilator.cpp
+++ b/verilator/microwatt-verilator.cpp
@@ -1,5 +1,5 @@
 #include <stdlib.h>
-#include "Vmicrowatt.h"
+#include "Vtoplevel.h"
 #include "verilated.h"
 #include "verilated_vcd_c.h"
 
@@ -24,7 +24,7 @@ double sc_time_stamp(void)
 VerilatedVcdC *tfp;
 #endif
 
-void tick(Vmicrowatt *top)
+void tick(Vtoplevel *top)
 {
        top->ext_clk = 1;
        top->eval();
@@ -51,7 +51,7 @@ int main(int argc, char **argv)
        Verilated::commandArgs(argc, argv);
 
        // init top verilog instance
-       Vmicrowatt* top = new Vmicrowatt;
+       Vtoplevel* top = new Vtoplevel;
 
 #if VM_TRACE
        // init trace dump