Automerged

--HG--
extra : convert_revision : 7b56535ee32551f27db8d98172159f63e5099835

diff --cc arch/alpha/isa_desc
index a7665210fc88c6e48eac121bb1ee975146ffb95b,41f7388e08bab8006e1c8a0f2f009431c3691156..56e7cb31c9db8ce852a73a7365e73ac7f94a4f18
--- 1/arch/alpha/isa_desc
--- 2/arch/alpha/isa_desc
+++ b/arch/alpha/isa_desc
@@@ -5,7 -5,7 +5,7 @@@
  
  let {{
      global rcs_id
--    rcs_id = "$Id$"
++    rcs_id = "$Id: s.isa_desc 1.43 04/02/29 22:41:10-05:00 ehallnor@zazzer.eecs.umich.edu $"
  }};
  
  
@@@ -1854,9 -1854,9 +1854,10 @@@ decode OPCODE default Unknown::unknown(
        0x23: ldt({{ EA = Rb + disp; }}, {{ Fa = Mem.df; }});
        0x2a: ldl_l({{ EA = Rb + disp; }}, {{ Ra.sl = Mem.sl; }}, LOCKED);
        0x2b: ldq_l({{ EA = Rb + disp; }}, {{ Ra.uq = Mem.uq; }}, LOCKED);
 -      0x20: copy_load({{EA = Ra;}}, 
+                       {{fault = memAccessObj->copySrcTranslate(EA);}},
 -                      IsMemRef, IsLoad, IsCopy);
 +      //0x20: copy_load({{EA = Ra;}}, 
 +      //                {{memAccessObj->copySrcTranslate(EA);}},
 +      //              IsMemRef, IsLoad, IsCopy);
      }
  
      format LoadOrPrefetch {
@@@ -1876,9 -1876,9 +1877,10 @@@
        0x0f: stq_u({{ EA = (Rb + disp) & ~7; }}, {{ Mem.uq = Ra.uq; }});
        0x26: sts({{ EA = Rb + disp; }}, {{ Mem.ul = t_to_s(Fa.uq); }});
        0x27: stt({{ EA = Rb + disp; }}, {{ Mem.df = Fa; }});
 -      0x24: copy_store({{EA = Rb;}},
+                        {{fault =memAccessObj->copy(EA);}},
 -                       IsMemRef, IsStore, IsCopy);
 +      //0x24: copy_store({{EA = Rb;}},
 +      //                 {{memAccessObj->copy(EA);}},
 +      //               IsMemRef, IsStore, IsCopy);
      }
  
      format StoreCond {

diff --cc cpu/exec_context.hh
Simple merge

diff --cc cpu/simple_cpu/simple_cpu.cc
Simple merge