[AArch64] Remove redundant SVE FADDA pattern

*pred_fold_left_plus_<mode> could no longer match anything, since
UNSPEC_FADDA now takes three operands.  Predicated FADDAs should
now go through mask_fold_left_plus_<mode> instead.

2019-08-07  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64-sve.md (*pred_fold_left_plus_<mode>): Delete.

From-SVN: r274186

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index aa0ad4aff3e499ec3aef4fded641c655331ba4ad..c292eec60135ff45451dfd9e15cd7e7a74596309 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,7 @@
+2019-08-07  Richard Sandiford  <richard.sandiford@arm.com>
+
+       * config/aarch64/aarch64-sve.md (*pred_fold_left_plus_<mode>): Delete.
+
 2019-08-07  Richard Sandiford  <richard.sandiford@arm.com>
 
        * config/aarch64/iterators.md (UNSPEC_COND_ADD): Rename to...

diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md
index b66066becb6fe15600640af36fa7c4da0440d06c..6c40979cb6583c16e995d32fa007d02afbc906b1 100644 (file)
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -3468,21 +3468,6 @@
   "fadda\t%<Vetype>0, %3, %<Vetype>0, %2.<Vetype>"
 )
 
-;; Predicated form of the above in-order reduction.
-(define_insn "*pred_fold_left_plus_<mode>"
-  [(set (match_operand:<VEL> 0 "register_operand" "=w")
-       (unspec:<VEL>
-         [(match_operand:<VEL> 1 "register_operand" "0")
-          (unspec:SVE_F
-            [(match_operand:<VPRED> 2 "register_operand" "Upl")
-             (match_operand:SVE_F 3 "register_operand" "w")
-             (match_operand:SVE_F 4 "aarch64_simd_imm_zero")]
-            UNSPEC_SEL)]
-         UNSPEC_FADDA))]
-  "TARGET_SVE"
-  "fadda\t%<Vetype>0, %2, %<Vetype>0, %3.<Vetype>"
-)
-
 ;; =========================================================================
 ;; == Permutes
 ;; =========================================================================