X86: Turn on the page table walker in SE mode.

diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript
index 1b443cd839c4435cd5d62628de72fef29021a24f..5ac092185853ab739e3a1bd169fe1969431d8022 100644 (file)
--- a/src/arch/x86/SConscript
+++ b/src/arch/x86/SConscript
@@ -57,6 +57,7 @@ if env['TARGET_ISA'] == 'x86':
     Source('isa.cc')
     Source('nativetrace.cc')
     Source('pagetable.cc')
+    Source('pagetable_walker.cc')
     Source('predecoder.cc')
     Source('predecoder_tables.cc')
     Source('remote_gdb.cc')
@@ -70,18 +71,17 @@ if env['TARGET_ISA'] == 'x86':
 
     DebugFlag('Faults', "Trace all faults/exceptions/traps")
     DebugFlag('LocalApic', "Local APIC debugging")
+    DebugFlag('PageTableWalker', \
+              "Page table walker state machine debugging")
     DebugFlag('Predecoder', "Predecoder debug output")
     DebugFlag('X86', "Generic X86 ISA debugging")
 
     if env['FULL_SYSTEM']:
-        DebugFlag('PageTableWalker', \
-                  "Page table walker state machine debugging")
 
         SimObject('X86System.py')
 
         # Full-system sources
         Source('linux/system.cc')
-        Source('pagetable_walker.cc')
         Source('system.cc')
         Source('stacktrace.cc')
         Source('vtophys.cc')

diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py
index ae9bfd3533400c8556b582f3d78218778605136a..7f2fcd358caa867371772025c6035100fe5bb24e 100644 (file)
--- a/src/arch/x86/X86TLB.py
+++ b/src/arch/x86/X86TLB.py
@@ -35,24 +35,21 @@
 #
 # Authors: Gabe Black
 
-from m5.defines import buildEnv
 from m5.params import *
 from m5.proxy import *
 
 from BaseTLB import BaseTLB
 from MemObject import MemObject
 
-if buildEnv['FULL_SYSTEM']:
-    class X86PagetableWalker(MemObject):
-        type = 'X86PagetableWalker'
-        cxx_class = 'X86ISA::Walker'
-        port = Port("Port for the hardware table walker")
-        system = Param.System(Parent.any, "system object")
+class X86PagetableWalker(MemObject):
+    type = 'X86PagetableWalker'
+    cxx_class = 'X86ISA::Walker'
+    port = Port("Port for the hardware table walker")
+    system = Param.System(Parent.any, "system object")
 
 class X86TLB(BaseTLB):
     type = 'X86TLB'
     cxx_class = 'X86ISA::TLB'
     size = Param.Int(64, "TLB size")
-    if buildEnv['FULL_SYSTEM']:
-        walker = Param.X86PagetableWalker(\
-                X86PagetableWalker(), "page table walker")
+    walker = Param.X86PagetableWalker(\
+            X86PagetableWalker(), "page table walker")

diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 40c30637d4d8c9f02fbf048475913325b2a2cf3c..88eb19b541ff084eb054ffc6b175a6bfe246704f 100644 (file)
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -44,6 +44,7 @@
 #include "arch/x86/regs/msr.hh"
 #include "arch/x86/faults.hh"
 #include "arch/x86/pagetable.hh"
+#include "arch/x86/pagetable_walker.hh"
 #include "arch/x86/tlb.hh"
 #include "arch/x86/x86_traits.hh"
 #include "base/bitfield.hh"
@@ -55,13 +56,13 @@
 #include "mem/packet_access.hh"
 #include "mem/request.hh"
 
-#if FULL_SYSTEM
-#include "arch/x86/pagetable_walker.hh"
-#else
+#if !FULL_SYSTEM
 #include "mem/page_table.hh"
 #include "sim/process.hh"
 #endif
 
+#include "sim/full_system.hh"
+
 namespace X86ISA {
 
 TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size)
@@ -72,10 +73,8 @@ TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size)
     for (int x = 0; x < size; x++)
         freeList.push_back(&tlb[x]);
 
-#if FULL_SYSTEM
     walker = p->walker;
     walker->setTLB(this);
-#endif
 }
 
 TlbEntry *
@@ -293,40 +292,42 @@ TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
             // The vaddr already has the segment base applied.
             TlbEntry *entry = lookup(vaddr);
             if (!entry) {
-#if FULL_SYSTEM
-                Fault fault = walker->start(tc, translation, req, mode);
-                if (timing || fault != NoFault) {
-                    // This gets ignored in atomic mode.
-                    delayedResponse = true;
-                    return fault;
-                }
-                entry = lookup(vaddr);
-                assert(entry);
-#else
-                DPRINTF(TLB, "Handling a TLB miss for "
-                        "address %#x at pc %#x.\n",
-                        vaddr, tc->instAddr());
-
-                Process *p = tc->getProcessPtr();
-                TlbEntry newEntry;
-                bool success = p->pTable->lookup(vaddr, newEntry);
-                if (!success && mode != Execute) {
-                    // Check if we just need to grow the stack.
-                    if (p->fixupStackFault(vaddr)) {
-                        // If we did, lookup the entry for the new page.
-                        success = p->pTable->lookup(vaddr, newEntry);
+                if (FullSystem) {
+                    Fault fault = walker->start(tc, translation, req, mode);
+                    if (timing || fault != NoFault) {
+                        // This gets ignored in atomic mode.
+                        delayedResponse = true;
+                        return fault;
                     }
-                }
-                if (!success) {
-                    return new PageFault(vaddr, true, mode, true, false);
+                    entry = lookup(vaddr);
+                    assert(entry);
                 } else {
-                    Addr alignedVaddr = p->pTable->pageAlign(vaddr);
-                    DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
-                            newEntry.pageStart());
-                    entry = insert(alignedVaddr, newEntry);
-                }
-                DPRINTF(TLB, "Miss was serviced.\n");
+#if !FULL_SYSTEM
+                    DPRINTF(TLB, "Handling a TLB miss for "
+                            "address %#x at pc %#x.\n",
+                            vaddr, tc->instAddr());
+
+                    Process *p = tc->getProcessPtr();
+                    TlbEntry newEntry;
+                    bool success = p->pTable->lookup(vaddr, newEntry);
+                    if (!success && mode != Execute) {
+                        // Check if we just need to grow the stack.
+                        if (p->fixupStackFault(vaddr)) {
+                            // If we did, lookup the entry for the new page.
+                            success = p->pTable->lookup(vaddr, newEntry);
+                        }
+                    }
+                    if (!success) {
+                        return new PageFault(vaddr, true, mode, true, false);
+                    } else {
+                        Addr alignedVaddr = p->pTable->pageAlign(vaddr);
+                        DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
+                                newEntry.pageStart());
+                        entry = insert(alignedVaddr, newEntry);
+                    }
+                    DPRINTF(TLB, "Miss was serviced.\n");
 #endif
+                }
             }
             // Do paging protection checks.
             bool inUser = (m5Reg.cpl == 3 &&

diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index e4ea0e1b7f0a7d686d592fd9892e24ecff0d6f4a..e82784900319dd5c723a71d0c2a97715f29e719b 100644 (file)
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -85,15 +85,11 @@ namespace X86ISA
 
         EntryList::iterator lookupIt(Addr va, bool update_lru = true);
 
-#if FULL_SYSTEM
-      protected:
-
         Walker * walker;
+
       public:
         Walker *getWalker();
-#endif
 
-      public:
         void invalidateAll();
 
         void invalidateNonGlobal();

diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 6640f3ceafb6f938461520ad4e6672d8611f5987..43035600444ed493eefe287c0df25bfe32675204 100644 (file)
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -140,7 +140,8 @@ class BaseCPU(MemObject):
     tracer = Param.InstTracer(default_tracer, "Instruction tracer")
 
     _cached_ports = []
-    if buildEnv['TARGET_ISA'] in ['x86', 'arm'] and buildEnv['FULL_SYSTEM']:
+    if buildEnv['TARGET_ISA'] == 'x86' or \
+        (buildEnv['TARGET_ISA'] == 'arm' and buildEnv['FULL_SYSTEM']):
         _cached_ports = ["itb.walker.port", "dtb.walker.port"]
 
     _uncached_ports = []