[ARC] Use ACCL, ACCH registers whenever they are available.

gcc/
2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.c (arc_conditional_register_usage): Use ACCL,
	ACCH registers whenever they are available.

From-SVN: r247199

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index e55c5df7fd1ef08404a099a178b514462173c3cc..5faeb0e79b87279758366d794840b64bbe4e7b91 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
+
+       * config/arc/arc.c (arc_conditional_register_usage): Use ACCL,
+       ACCH registers whenever they are available.
+
 2017-04-25  Claudiu Zissulescu  <claziss@synopsys.com>
 
        * config/arc/arc.c (arc_conditional_register_usage): Make D0, D1

diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index dc201ee7450f881ac6007cf13d45d9b1536eddc8..0c6b96fcd161a502e1cef52e212ad874944cece6 100644 (file)
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -1585,6 +1585,15 @@ arc_conditional_register_usage (void)
     SET_HARD_REG_BIT (reg_class_contents[WRITABLE_CORE_REGS], ACCH_REGNO);
     SET_HARD_REG_BIT (reg_class_contents[CHEAP_CORE_REGS], ACCL_REGNO);
     SET_HARD_REG_BIT (reg_class_contents[CHEAP_CORE_REGS], ACCH_REGNO);
+    SET_HARD_REG_BIT (reg_class_contents[GENERAL_REGS], ACCL_REGNO);
+    SET_HARD_REG_BIT (reg_class_contents[GENERAL_REGS], ACCH_REGNO);
+    SET_HARD_REG_BIT (reg_class_contents[MPY_WRITABLE_CORE_REGS], ACCL_REGNO);
+    SET_HARD_REG_BIT (reg_class_contents[MPY_WRITABLE_CORE_REGS], ACCH_REGNO);
+
+     /* Allow the compiler to freely use them.  */
+    fixed_regs[ACCL_REGNO] = 0;
+    fixed_regs[ACCH_REGNO] = 0;
+
     arc_hard_regno_mode_ok[ACC_REG_FIRST] = D_MODES;
   }
 }