Simulate XScale BCUMOD register

diff --git a/sim/arm/ChangeLog b/sim/arm/ChangeLog
index f0639fe3c532dedbfc98b17ae5ef1799b1ae2d78..b6d8266289b51912368bc48fc74474242d10a4ad 100644 (file)
--- a/sim/arm/ChangeLog
+++ b/sim/arm/ChangeLog
@@ -1,3 +1,9 @@
+2002-05-21  Nick Clifton  <nickc@cambridge.redhat.com>
+
+       * armcopro.c (check_cp13_access): Allow access to register 1 when
+       CRm is 1.
+       (write_cp13_reg): Allow bit 0 of reg 1 of CRm 1 to be written to.
+
 2002-05-20  Nick Clifton  <nickc@cambridge.redhat.com>
 
        * Makefile.in (SWI_TARGET_SWITCHES): Define.

diff --git a/sim/arm/armcopro.c b/sim/arm/armcopro.c
index 75c6bfca62be6c2c1fa1b4435d7a3df42ef8549c..da409f06724f7890cd5faf24154fefbbfa445836 100644 (file)
--- a/sim/arm/armcopro.c
+++ b/sim/arm/armcopro.c
@@ -587,7 +587,7 @@ check_cp13_access (ARMul_State * state,
                   unsigned      opcode_1,
                   unsigned      opcode_2)
 {
-  /* Do not allow access to these register in USER mode.  */
+  /* Do not allow access to these registers in USER mode.  */
   if (state->Mode == USER26MODE || state->Mode == USER32MODE)
     return ARMul_CANT;
 
@@ -601,7 +601,7 @@ check_cp13_access (ARMul_State * state,
     return ARMul_CANT;
 
   /* Registers 0, 4 and 8 are defined when CRm == 0.
-     Registers 0, 4, 5, 6, 7, 8 are defined when CRm == 1.
+     Registers 0, 1, 4, 5, 6, 7, 8 are defined when CRm == 1.
      For all other CRm values undefined behaviour results.  */
   if (CRm == 0)
     {
@@ -610,7 +610,7 @@ check_cp13_access (ARMul_State * state,
     }
   else if (CRm == 1)
     {
-      if (reg == 0 || (reg >= 4 && reg <= 8))
+      if (reg == 0 || reg == 1 || (reg >= 4 && reg <= 8))
        return ARMul_DONE;
     }
 
@@ -659,6 +659,12 @@ write_cp13_reg (unsigned reg, unsigned CRm, ARMword value)
          value |= XScale_cp13_CR1_Regs[0] & (1UL << 31);
          break;
 
+       case 1: /* BCUMOD */
+         /* Only bit 0 is accecssible.  */
+         value &= 1;
+         value |= XScale_cp13_CR1_Regs[1] & ~ 1;
+         break;
+
        case 4: /* ELOG0 */
        case 5: /* ELOG1 */
        case 6: /* ECAR0 */